From bc4adc97cfb4aa239aba3abd39ff5d7827af0218 Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Wed, 19 Jul 2023 17:17:54 +0800 Subject: board: mediatek: add MT7988 reference boards This patch adds general board files based on MT7988 SoCs. MT7988 uses one mmc controller for booting from both SD and eMMC, and the pins of mmc controller booting from SD are also shared with one of spi controllers. So two configs are need for these boot types: 1. mt7988_rfb_defconfig - SPI-NOR, SPI-NAND and eMMC 2. mt7988_sd_rfb_defconfig - SPI-NAND and SD Signed-off-by: Weijie Gao --- arch/arm/dts/Makefile | 2 + arch/arm/dts/mt7988-rfb.dts | 182 +++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/mt7988-sd-rfb.dts | 134 ++++++++++++++++++++++++++++++ 3 files changed, 318 insertions(+) create mode 100644 arch/arm/dts/mt7988-rfb.dts create mode 100644 arch/arm/dts/mt7988-sd-rfb.dts (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e66c32e2689..8f43dba5863 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1341,6 +1341,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7986b-sd-rfb.dtb \ mt7986a-emmc-rfb.dtb \ mt7986b-emmc-rfb.dtb \ + mt7988-rfb.dtb \ + mt7988-sd-rfb.dtb \ mt8183-pumpkin.dtb \ mt8512-bm1-emmc.dtb \ mt8516-pumpkin.dtb \ diff --git a/arch/arm/dts/mt7988-rfb.dts b/arch/arm/dts/mt7988-rfb.dts new file mode 100644 index 00000000000..2c114284309 --- /dev/null +++ b/arch/arm/dts/mt7988-rfb.dts @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Sam Shih + */ + +/dts-v1/; +#include "mt7988.dtsi" +#include + +/ { + model = "mt7988-rfb"; + compatible = "mediatek,mt7988-rfb"; + + chosen { + stdout-path = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x10000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&uart0 { + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; +}; + +ð { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "usxgmii"; + mediatek,switch = "mt7988"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; +}; + +&pinctrl { + i2c1_pins: i2c1-pins { + mux { + function = "i2c"; + groups = "i2c1_0"; + }; + }; + + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4", + "pwm5", "pwm6", "pwm7"; + }; + }; + + spi0_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spi2_pins: spi2-pins { + mux { + function = "spi"; + groups = "spi2", "spi2_wp_hold"; + }; + }; + + mmc0_pins_default: mmc0default { + mux { + function = "flash"; + groups = "emmc_51"; + }; + + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + }; + + conf-clk { + pins = "EMMC_CK"; + }; + + conf-dsl { + pins = "EMMC_DSL"; + }; + + conf-rst { + pins = "EMMC_RSTB"; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + spi_nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + max-frequency = <52000000>; + bus-width = <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/mt7988-sd-rfb.dts b/arch/arm/dts/mt7988-sd-rfb.dts new file mode 100644 index 00000000000..a3df37d252d --- /dev/null +++ b/arch/arm/dts/mt7988-sd-rfb.dts @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Sam Shih + */ + +/dts-v1/; +#include "mt7988.dtsi" +#include + +/ { + model = "mt7988-rfb"; + compatible = "mediatek,mt7988-rfb", "mediatek,mt7988-sd-rfb"; + + chosen { + stdout-path = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x10000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&uart0 { + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; +}; + +ð { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "usxgmii"; + mediatek,switch = "mt7988"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; +}; + +&pinctrl { + i2c1_pins: i2c1-pins { + mux { + function = "i2c"; + groups = "i2c1_0"; + }; + }; + + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4", + "pwm5", "pwm6", "pwm7"; + }; + }; + + spi0_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + mmc1_pins_default: mmc1default { + mux { + function = "flash"; + groups = "emmc_45"; + }; + + conf-cmd-dat { + pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI", + "SPI2_CLK", "SPI2_HOLD"; + input-enable; + }; + + conf-clk { + pins = "SPI2_WP"; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + max-frequency = <52000000>; + bus-width = <4>; + cap-sd-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + status = "okay"; +}; -- cgit v1.3.1