From 9bcf9e49a24e1cd96565b8ccd40b23ab956c3376 Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Wed, 6 Sep 2023 14:18:12 +0900 Subject: riscv: bootstage: correct bootstage_report guard Below warning can be occurred when CONFIG_BOOTSTAGE and !CONFIG_SPL_BOOTSTAGE. It should be guarded by using CONFIG_IS_ENABLED for SPL build. arch/riscv/lib/bootm.c:46:9: warning: implicit declaration of function 'bootstage_report' 46 | bootstage_report(); | ^~~~~~~~~~~~~~~~ | bootstage_error Signed-off-by: Chanho Park Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/lib/bootm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 276677a5e2f..cc30efc9049 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -42,7 +42,7 @@ static void announce_and_cleanup(int fake) #ifdef CONFIG_BOOTSTAGE_FDT bootstage_fdt_add_report(); #endif -#ifdef CONFIG_BOOTSTAGE_REPORT +#if CONFIG_IS_ENABLED(BOOTSTAGE_REPORT) bootstage_report(); #endif -- cgit v1.3.1 From e637e455ca766d6b5bea5f4c5b9290ab07c87507 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 23 Sep 2023 01:35:26 +0200 Subject: riscv: enable CONFIG_DEBUG_UART by default Most boards don't enable the pre-console buffer. So we will not see any early messages. OpenSBI 1.3 provides us with the debug console extension that can fill this gap. For S-Mode U-Boot enable CONFIG_DEBUG_UART by default. Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 1c62c2345b0..06fae7ebe83 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -141,6 +141,7 @@ config RISCV_MMODE config RISCV_SMODE bool "Supervisor" + imply DEBUG_UART help Choose this option to build U-Boot for RISC-V S-Mode. -- cgit v1.3.1 From b68bf22fbb5cbce6f48d979a31a8bfb7230e9512 Mon Sep 17 00:00:00 2001 From: Randolph Date: Mon, 25 Sep 2023 17:24:51 +0800 Subject: configs: andes: add vender prefix for target name Modify "CONFIG_TARGET_AE350" to "CONFIG_TARGET_ANDES_AE350" Signed-off-by: Randolph Reviewed-by: Tom Rini --- arch/riscv/Kconfig | 4 ++-- arch/riscv/dts/Makefile | 2 +- board/AndesTech/ae350/Kconfig | 2 +- configs/ae350_rv32_defconfig | 3 ++- configs/ae350_rv32_spl_defconfig | 2 +- configs/ae350_rv32_spl_xip_defconfig | 2 +- configs/ae350_rv32_xip_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- configs/ae350_rv64_spl_defconfig | 2 +- configs/ae350_rv64_spl_xip_defconfig | 2 +- configs/ae350_rv64_xip_defconfig | 2 +- 11 files changed, 13 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 06fae7ebe83..183885ebe7d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -8,8 +8,8 @@ choice prompt "Target select" optional -config TARGET_AE350 - bool "Support ae350" +config TARGET_ANDES_AE350 + bool "Support Andes ae350" config TARGET_MICROCHIP_ICICLE bool "Support Microchip PolarFire-SoC Icicle Board" diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index f1525cb6680..be6c8a42272 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb diff --git a/board/AndesTech/ae350/Kconfig b/board/AndesTech/ae350/Kconfig index 75815bf99aa..a85e7d63517 100644 --- a/board/AndesTech/ae350/Kconfig +++ b/board/AndesTech/ae350/Kconfig @@ -1,4 +1,4 @@ -if TARGET_AE350 +if TARGET_ANDES_AE350 config SYS_CPU default "andesv5" diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index ce312a65341..8269b8d6556 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -8,7 +8,8 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y +CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 7f7ce0373bc..030ef57f071 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -10,7 +10,7 @@ CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_SYS_MONITOR_BASE=0x88000000 diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 7b0c6575949..e09ab2409a3 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -11,7 +11,7 @@ CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y CONFIG_SYS_MONITOR_BASE=0x88000000 diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index 641c10022f8..b90200a97e8 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -8,7 +8,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_XIP=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_FIT=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 02d8c07c81b..a4b9ad6162d 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -7,7 +7,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_FIT=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 4655050f707..5c3e6229635 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -9,7 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index ad721d1870a..3cb3444e92c 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -10,7 +10,7 @@ CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index 042d876702e..cc5e751c9b6 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -7,7 +7,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y CONFIG_XIP=y CONFIG_SYS_MONITOR_BASE=0x88000000 -- cgit v1.3.1 From 8a0d5f2f51b72b3cabacfe90ff196db3e1c4dc4d Mon Sep 17 00:00:00 2001 From: Yu Chien Peter Lin Date: Fri, 29 Sep 2023 12:03:07 +0800 Subject: riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode The Andes PLMT driver directly accesses the mtime MMIO region, indicating its intended use in the M-mode boot stage. However, since U-Boot proper (S-mode) also uses the PLMT driver, we need to specifically mark the region as readable through PMPCFGx (or S/U-mode read-only shared data region for Smepmp) in OpenSBI. Granting permission for this case doesn't make sense. Instead, we should use the generic RISC-V timer driver to read the mtime through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER config, which ensures that the PLMT driver is linked exclusively against M-mode U-Boot or U-Boot SPL binaries. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Samuel Holland --- arch/riscv/cpu/andesv5/Kconfig | 3 ++- drivers/timer/Kconfig | 9 ++++++++- drivers/timer/Makefile | 2 +- 3 files changed, 11 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andesv5/Kconfig index 82bb5a2a532..f311291aedb 100644 --- a/arch/riscv/cpu/andesv5/Kconfig +++ b/arch/riscv/cpu/andesv5/Kconfig @@ -4,8 +4,9 @@ config RISCV_NDS imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply ANDES_PLMT_TIMER + imply SPL_ANDES_PLMT_TIMER imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE) - imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE) imply V5L2_CACHE imply SPL_CPU imply SPL_OPENSBI diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index a98be9dfae4..60519c3b536 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -59,7 +59,14 @@ config ALTERA_TIMER config ANDES_PLMT_TIMER bool - depends on RISCV_MMODE || SPL_RISCV_MMODE + depends on RISCV_MMODE + help + The Andes PLMT block holds memory-mapped mtime register + associated with timer tick. + +config SPL_ANDES_PLMT_TIMER + bool + depends on SPL_RISCV_MMODE help The Andes PLMT block holds memory-mapped mtime register associated with timer tick. diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 1ef814970b9..b93145e8d43 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -4,7 +4,7 @@ obj-y += timer-uclass.o obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o -obj-$(CONFIG_ANDES_PLMT_TIMER) += andes_plmt_timer.o +obj-$(CONFIG_$(SPL_)ANDES_PLMT_TIMER) += andes_plmt_timer.o obj-$(CONFIG_ARC_TIMER) += arc_timer.o obj-$(CONFIG_ARM_TWD_TIMER) += arm_twd_timer.o obj-$(CONFIG_AST_TIMER) += ast_timer.o -- cgit v1.3.1