From 2390eb8b614e4dc038bc41706821b275c367d55d Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Tue, 10 Jun 2025 11:42:50 +0200 Subject: rockchip: px30/rk3326: Implement checkboard() to print SoC variant This implements checkboard() to print the current SoC model used by a board, e.g. one of: SoC: PX30 SoC: PX30S SoC: PX30K SoC: RK3326 SoC: RK3326S when U-Boot proper is running. The information is read from the OTP and also the DDR_GRF. There's no public information as far as I know about the layout and stored information on OTP but this was provided by Rockchip themselves through their support channel. The OTP stores the information of whether the SoC is PX30K or something else. To differentiate between PX30/RK3326 and PX30S/RK3326S, one needs to read some undocumented bitfield in a DDR_GRF register as done in vendor kernel, c.f. https://github.com/armbian/linux-rockchip/blob/rk-6.1-rkr5.1/drivers/soc/rockchip/rockchip-cpuinfo.c#L118-L133. I do not own a PX30S, nor RK3326/RK3326S so cannot test it works properly. Also add the OTP node to the pre-relocation phase of U-Boot proper so that the SoC variant can be printed when DISPLAY_BOARDINFO is enabled. This is not required if DISPLAY_BOARDINFO_LATE is enabled because this happens after relocation. If both are enabled, then the SoC variant will be printed twice in the boot log, e.g.: U-Boot 2025.07-rc3-00014-g7cb731574ae6-dirty (May 28 2025 - 13:52:47 +0200) Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit SoC: PX30 <---- due to DISPLAY_BOARDINFO DRAM: 2 GiB PMIC: RK809 (on=0x40, off=0x00) Core: 293 devices, 27 uclasses, devicetree: separate MMC: mmc@ff370000: 1, mmc@ff390000: 0 Loading Environment from MMC... Reading from MMC(1)... OK In: serial@ff030000 Out: serial@ff030000 Err: serial@ff030000 Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit SoC: PX30 <----- due to DISPLAY_BOARDINFO_LATE Net: eth0: ethernet@ff360000 Signed-off-by: Quentin Schulz Reviewed-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/px30-u-boot.dtsi | 4 +++ arch/arm/mach-rockchip/px30/px30.c | 61 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi index 157d0ea6930..2f726b0aaba 100644 --- a/arch/arm/dts/px30-u-boot.dtsi +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -27,6 +27,10 @@ }; }; +&otp { + bootph-some-ram; +}; + &uart2 { clock-frequency = <24000000>; bootph-all; diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index 8ce9ac561f0..5a5c119328f 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -2,10 +2,14 @@ /* * Copyright (c) 2017 Rockchip Electronics Co., Ltd */ + +#define LOG_CATEGORY LOGC_ARCH + #include #include #include #include +#include #include #include #include @@ -15,6 +19,7 @@ #include #include #include +#include const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/mmc@ff390000", @@ -442,3 +447,59 @@ void board_debug_uart_init(void) #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */ } #endif /* CONFIG_DEBUG_UART_BOARD_INIT */ + +#define PX30_OTP_SPECIFICATION_OFFSET 0x06 + +#define DDR_GRF_BASE_ADDR 0xff630000 +#define DDR_GRF_CON(n) (0 + (n) * 4) + +int checkboard(void) +{ + struct udevice *dev; + u8 specification; + u32 base_soc; + int ret; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return 0; + } + + /* base SoC: 0x26334b52 for RK3326; 0x30335850 for PX30 */ + ret = misc_read(dev, 0, &base_soc, 4); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + + if (base_soc != 0x26334b52 && base_soc != 0x30335850) { + log_debug("Could not identify SoC, got 0x%04x in OTP\n", base_soc); + return 0; + } + + /* SoC variant: 0x21 for PX30/PX30S/RK3326/RK3326S; 0x2b for PX30K */ + ret = misc_read(dev, PX30_OTP_SPECIFICATION_OFFSET, &specification, 1); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + + if (specification == 0x2b) { + printf("SoC: PX30K\n"); + return 0; + } + + /* From vendor kernel: drivers/soc/rockchip/rockchip-cpuinfo.c */ + specification = FIELD_GET(GENMASK(15, 14), + readl(DDR_GRF_BASE_ADDR + DDR_GRF_CON(1))); + log_debug("DDR specification is %d\n", specification); + printf("SoC: %s%s\n", base_soc == 0x26334b52 ? "RK3326" : "PX30", + specification == 0x3 ? "S" : ""); + + return 0; +} -- cgit v1.2.3 From 9d98a6b9803d9989528d320ad71d607914378d9e Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 9 Jun 2025 22:06:16 -0500 Subject: rockchip: Add support for GameForce Ace The GameForce Ace is an RK3588S based handheld gaming device. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3588/Kconfig | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 4e7942ada87..9fbe3f225aa 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -27,6 +27,23 @@ config TARGET_CM3588_NAS_RK3588 - 3.5mm Headphone out, 2.0mm PH-2A Mic in - 5V Fan connector, PWM beeper, IR receiver, RTC battery connector +config TARGET_GAMEFORCE_ACE_RK3588S + bool "GameForce Ace" + help + The GameForce Ace is a handheld game console from GameForce with + the Rockchip RK3588S SoC. + + Hardware features: + - Rockchip RK3588S SoC + - 12GB LPDDR4x RAM + - 128GB eMMC + - MicroSD card slot + - 1x USB 3.0 Type-C with DP AltMode support + - 1x HDMI 2.1 micro-HDMI out + - 1920x1080 touchscreen MIPI-DSI panel + - Analog joysticks and L/R triggers + - 16 digital buttons + config TARGET_GENBOOK_CM5_RK3588 bool "Cool Pi CM5 GenBook" help @@ -410,6 +427,7 @@ source "board/friendlyelec/cm3588-nas-rk3588/Kconfig" source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig" source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig" +source "board/gameforce/ace-rk3588s/Kconfig" source "board/hardkernel/odroid_m2/Kconfig" source "board/indiedroid/nova/Kconfig" source "board/khadas/khadas-edge2-rk3588s/Kconfig" -- cgit v1.2.3 From d48f063a5385a1bd79f048810826c823d09be8ec Mon Sep 17 00:00:00 2001 From: Da Xue Date: Tue, 10 Jun 2025 19:08:19 +0000 Subject: ram: rk3328: add ddr4-1600 sdram timing Add DDR4 1600MHz SDRAM timing data from LibreComputer u-boot sources for the ROC-3328-CC board. Signed-off-by: Da Xue Signed-off-by: Christian Hewitt Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi | 226 +++++++++++++++++++++++++++++++ 1 file changed, 226 insertions(+) create mode 100644 arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi (limited to 'arch') diff --git a/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi new file mode 100644 index 00000000000..9594bb42839 --- /dev/null +++ b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. + +&dmc { + rockchip,sdram-params = < + 0x1 + 0xA + 0x2 + 0x1 + 0x0 + 0x0 + 0x11 + 0x0 + 0x11 + 0x0 + 0 + + 0x94496354 + 0x00000000 + 0x0000002a + 0x000004e2 + 0x00000015 + 0x0000034a + 0x000000ff + + 800 + 0 + 1 + 0 + 0 + + 0x00000000 + 0x43041010 + 0x00000064 + 0x0061008c + 0x000000d0 + 0x000200c5 + 0x000000d4 + 0x00500000 + 0x000000d8 + 0x00000100 + 0x000000dc + 0x03140401 + 0x000000e0 + 0x00000000 + 0x000000e4 + 0x00110000 + 0x000000e8 + 0x00000420 + 0x000000ec + 0x00000400 + 0x000000f4 + 0x000f011f + 0x00000100 + 0x0c0e1b0e + 0x00000104 + 0x00030314 + 0x00000108 + 0x0506050b + 0x0000010c + 0x0040400c + 0x00000110 + 0x06030307 + 0x00000114 + 0x04040302 + 0x00000120 + 0x06060b06 + 0x00000124 + 0x00020308 + 0x00000180 + 0x01000040 + 0x00000184 + 0x00000000 + 0x00000190 + 0x07040003 + 0x00000198 + 0x05001100 + 0x000001a0 + 0xc0400003 + 0x00000240 + 0x0600060c + 0x00000244 + 0x00000201 + 0x00000250 + 0x00000f00 + 0x00000490 + 0x00000001 + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + + 0x00000004 + 0x0000000c + 0x00000028 + 0x0000000c + 0x0000002c + 0x00000000 + 0x00000030 + 0x00000009 + 0xffffffff + 0xffffffff + + 0x77 + 0x88 + 0x79 + 0x79 + 0x87 + 0x97 + 0x87 + 0x78 + 0x77 + 0x78 + 0x87 + 0x88 + 0x87 + 0x87 + 0x77 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + >; +}; -- cgit v1.2.3 From 578e168387dace1e4d146d8b7c8570b18dec238e Mon Sep 17 00:00:00 2001 From: Da Xue Date: Tue, 10 Jun 2025 19:08:20 +0000 Subject: arm64: dts: rockchip: roc-3328-cc: use 1600 ddr4 timing Swap the ROC-3328-CC from DDR4 666 to 1600 timing to boost performance. Signed-off-by: Da Xue Signed-off-by: Christian Hewitt Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi index 582d6ba49b4..c47d29c59de 100644 --- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi +++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi @@ -4,7 +4,7 @@ */ #include "rk3328-u-boot.dtsi" -#include "rk3328-sdram-ddr4-666.dtsi" +#include "rk3328-sdram-ddr4-1600.dtsi" / { smbios { -- cgit v1.2.3 From 108d9f11ea928a80976db80b5ff723ce8170ebe1 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:32:39 +0000 Subject: board: rockchip: Add minimal generic RK3576 board Add a minimal generic RK3576 board that only have eMMC, SDMMC and USB OTG enabled. This defconfig can be used to boot from eMMC or SD-card on most RK3576 boards that follow reference board design. eMMC and SD-card boot tested on: - ArmSoM CM5 - ArmSoM Sige5 - FriendlyElec NanoPi M5 - Luckfox Omni3576 - Toybrick TB-RK3576D Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3576-generic-u-boot.dtsi | 3 ++ arch/arm/dts/rk3576-generic.dts | 63 +++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3576/MAINTAINERS | 5 +++ 3 files changed, 71 insertions(+) create mode 100644 arch/arm/dts/rk3576-generic-u-boot.dtsi create mode 100644 arch/arm/dts/rk3576-generic.dts create mode 100644 arch/arm/mach-rockchip/rk3576/MAINTAINERS (limited to 'arch') diff --git a/arch/arm/dts/rk3576-generic-u-boot.dtsi b/arch/arm/dts/rk3576-generic-u-boot.dtsi new file mode 100644 index 00000000000..632fabb6af5 --- /dev/null +++ b/arch/arm/dts/rk3576-generic-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3576-u-boot.dtsi" diff --git a/arch/arm/dts/rk3576-generic.dts b/arch/arm/dts/rk3576-generic.dts new file mode 100644 index 00000000000..123be5378d9 --- /dev/null +++ b/arch/arm/dts/rk3576-generic.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Minimal generic DT for RK3576 with eMMC, SD-card and USB OTG enabled + */ + +/dts-v1/; + +#include +#include "rk3576.dtsi" + +/ { + model = "Generic RK3576"; + compatible = "rockchip,rk3576"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +&usb_drd0_dwc3 { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS new file mode 100644 index 00000000000..b5190c81846 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS @@ -0,0 +1,5 @@ +GENERIC-RK3576 +M: Jonas Karlman +S: Maintained +F: arch/arm/dts/rk3576-generic* +F: configs/generic-rk3576_defconfig -- cgit v1.2.3 From a72e8feaca46ed41a8d6bb4e8c5961a29fe7a39e Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:32:40 +0000 Subject: rockchip: rk3576: Implement checkboard() to print SoC variant Implement checkboard() to print current SoC model used by a board when U-Boot proper is running. U-Boot 2025.04 (Apr 22 2025 - 20:43:17 +0000) Model: Generic RK3576 SoC: RK3576 DRAM: 8 GiB Information about the SoC model and variant is read from OTP. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3576/rk3576.c | 48 ++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c index ba5c94b4b3d..2b1318f9532 100644 --- a/arch/arm/mach-rockchip/rk3576/rk3576.c +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -3,6 +3,10 @@ * Copyright (c) 2024 Rockchip Electronics Co., Ltd */ +#define LOG_CATEGORY LOGC_ARCH + +#include +#include #include #include #include @@ -153,3 +157,47 @@ int arch_cpu_init(void) return 0; } + +#define RK3576_OTP_CPU_CODE_OFFSET 0x02 +#define RK3576_OTP_SPECIFICATION_OFFSET 0x08 + +int checkboard(void) +{ + u8 cpu_code[2], specification; + struct udevice *dev; + char suffix[2]; + int ret; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return 0; + } + + /* cpu-code: SoC model, e.g. 0x35 0x76 */ + ret = misc_read(dev, RK3576_OTP_CPU_CODE_OFFSET, cpu_code, 2); + if (ret < 0) { + log_debug("Could not read cpu-code, ret=%d\n", ret); + return 0; + } + + /* specification: SoC variant, e.g. 0xA for RK3576J */ + ret = misc_read(dev, RK3576_OTP_SPECIFICATION_OFFSET, &specification, 1); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + specification &= 0x1f; + + /* for RK3576J i.e. '@' + 0xA = 'J' */ + suffix[0] = specification > 1 ? '@' + specification : '\0'; + suffix[1] = '\0'; + + printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix); + + return 0; +} -- cgit v1.2.3 From bdcda6be27b69a6e7ced1d59f5d6ceb07c5414ac Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:32:41 +0000 Subject: arm: dts: rockchip: Include OTP in U-Boot pre-reloc phase for RK3576 Update rk3576-u-boot.dtsi to include OTP in U-Boot pre-reloc phase for checkboard() to be able to read information about the running SoC model and variant from OTP and print it during boot: U-Boot 2025.04 (Apr 22 2025 - 20:43:17 +0000) Model: Generic RK3576 SoC: RK3576 DRAM: 8 GiB Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3576-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi index be99a48a630..fb5a107f47d 100644 --- a/arch/arm/dts/rk3576-u-boot.dtsi +++ b/arch/arm/dts/rk3576-u-boot.dtsi @@ -49,6 +49,10 @@ bootph-all; }; +&otp { + bootph-some-ram; +}; + &pcfg_pull_none { bootph-all; }; -- cgit v1.2.3 From ae2faeae673479014846c0c6280edb46782cf950 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 20:43:39 +0000 Subject: board: rockchip: Add ArmSoM Sige5 ArmSoM-Sige5 adopts the second-generation 8nm high-performance AIOT platform Rockchip RK3576, with a 6 TOPS computing power NPU and support for up to 16GB of large memory. It supports 4K video encoding and decoding, offers rich interfaces including dual gigabit Ethernet ports, WiFi 6 & BT5, and various video outputs. Features tested on a ArmSoM Sige5 v1.1: - SD-card boot - eMMC boot - Ethernet - PCIe NVMe Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi | 18 ++++++++++++++++++ arch/arm/mach-rockchip/rk3576/MAINTAINERS | 6 ++++++ 2 files changed, 24 insertions(+) create mode 100644 arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi (limited to 'arch') diff --git a/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi b/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi new file mode 100644 index 00000000000..7e0530d85d1 --- /dev/null +++ b/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3576-u-boot.dtsi" + +/ { + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; +}; + +&red_led { + default-state = "on"; +}; + +&sdhci { + cap-mmc-highspeed; +}; diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS index b5190c81846..94ef74d429f 100644 --- a/arch/arm/mach-rockchip/rk3576/MAINTAINERS +++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS @@ -3,3 +3,9 @@ M: Jonas Karlman S: Maintained F: arch/arm/dts/rk3576-generic* F: configs/generic-rk3576_defconfig + +SIGE5-RK3576 +M: Jonas Karlman +S: Maintained +F: arch/arm/dts/rk3576-armsom-sige5* +F: configs/sige5-rk3576_defconfig -- cgit v1.2.3 From 9b3b5e03b8ddb548e6ece7b35ad1d52b5363abf2 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 30 Jul 2025 23:52:42 +0000 Subject: rockchip: rk3528-generic: Fix boot after dts/upstream v6.16-dts merge The rk3528-generic target can no longer boot after v6.16-dts was merged into dts/upstream, and instead end up in a boot loop: No serial driver found resetting ... After Linux commit 34d2730fbbdd ("arm64: dts: rockchip: move rk3528 i2c+uart aliases to board files") there is no longer an alias for serial0 defined for the U-Boot only rk3528-generic device tree. Add a board specific aliases node that include the missing serial0 alias to resolve the boot issue and ensure that stdout-path = "serial0:..." can be resolved by U-Boot. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3528-generic.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/rk3528-generic.dts b/arch/arm/dts/rk3528-generic.dts index 3f6f0bed108..fe9e72c41cd 100644 --- a/arch/arm/dts/rk3528-generic.dts +++ b/arch/arm/dts/rk3528-generic.dts @@ -10,6 +10,11 @@ model = "Generic RK3528"; compatible = "rockchip,rk3528"; + aliases { + mmc0 = &sdhci; + serial0 = &uart0; + }; + chosen { stdout-path = "serial0:1500000n8"; }; -- cgit v1.2.3 From 2e3b37d589d3ccb3c7c11c0cca01f330a040c863 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 30 Jul 2025 23:52:43 +0000 Subject: arm: dts: rockchip: Use sdmmc node from dts/upstream on RK3528 Drop the sdmmc node from soc u-boot.dtsi and instead use the sdmmc node from rk3528.dtsi with v6.16-dts now merged to dts/upstream. This cleanup has no intended functional change. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3528-generic-u-boot.dtsi | 9 --------- arch/arm/dts/rk3528-generic.dts | 12 +++++++++++- arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi | 9 --------- arch/arm/dts/rk3528-u-boot.dtsi | 18 ------------------ 4 files changed, 11 insertions(+), 37 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/rk3528-generic-u-boot.dtsi b/arch/arm/dts/rk3528-generic-u-boot.dtsi index cc830b51456..9e1fb2a7eef 100644 --- a/arch/arm/dts/rk3528-generic-u-boot.dtsi +++ b/arch/arm/dts/rk3528-generic-u-boot.dtsi @@ -1,12 +1,3 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include "rk3528-u-boot.dtsi" - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - no-mmc; - no-sdio; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3528-generic.dts b/arch/arm/dts/rk3528-generic.dts index fe9e72c41cd..637ca03325e 100644 --- a/arch/arm/dts/rk3528-generic.dts +++ b/arch/arm/dts/rk3528-generic.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Minimal generic DT for RK3528 with eMMC enabled + * Minimal generic DT for RK3528 with eMMC and SD-card enabled */ /dts-v1/; @@ -12,6 +12,7 @@ aliases { mmc0 = &sdhci; + mmc1 = &sdmmc; serial0 = &uart0; }; @@ -30,6 +31,15 @@ status = "okay"; }; +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0m0_xfer>; diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi index 1372d8f1e38..05a58c136bc 100644 --- a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi +++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi @@ -5,12 +5,3 @@ &sdhci { mmc-hs200-1_8v; }; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - vmmc-supply = <&vcc_3v3>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3528-u-boot.dtsi b/arch/arm/dts/rk3528-u-boot.dtsi index eb6a55cd5c9..a18d33b3d36 100644 --- a/arch/arm/dts/rk3528-u-boot.dtsi +++ b/arch/arm/dts/rk3528-u-boot.dtsi @@ -27,24 +27,6 @@ compatible = "rockchip,rk3528-otp"; reg = <0x0 0xffce0000 0x0 0x4000>; }; - - sdmmc: mmc@ffc30000 { - compatible = "rockchip,rk3528-dw-mshc", - "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xffc30000 0x0 0x4000>; - clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x100>; - interrupts = ; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, - <&sdmmc_det>; - resets = <&cru SRST_H_SDMMC0>; - reset-names = "reset"; - rockchip,default-sample-phase = <90>; - status = "disabled"; - }; }; }; -- cgit v1.2.3 From 95ae8b040b891596c5a7916a0955d7820fc9e380 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 30 Jul 2025 23:52:44 +0000 Subject: arm: dts: rockchip: Set init-microvolt for pwm-regulators on Radxa E20C Radxa E20C has two main pwm-regulators, vdd_arm and vdd_logic. Add init-microvolt props to ensure the regulators are initialized at the recommended power-on sequence voltage instead of at max voltage. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi index 05a58c136bc..16c47e6b9a9 100644 --- a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi +++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi @@ -5,3 +5,11 @@ &sdhci { mmc-hs200-1_8v; }; + +&vdd_arm { + regulator-init-microvolt = <953000>; +}; + +&vdd_logic { + regulator-init-microvolt = <900000>; +}; -- cgit v1.2.3 From 58d39bbd773965404cd8cc41ebb94488b48ac1a4 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 30 Jul 2025 23:52:45 +0000 Subject: rockchip: rk3528: Disable USB3OTG U3 port early The RK3528 SoC comes with USB OTG support using a DWC3 controller with a USB2 PHY and a USB3 PHY (COMBPHY). Some board designs may not use the COMBPHY for USB3 purpose. For these board to use USB OTG the input clock source must change to use UTMI clk instead of PIPE clk. Change to always disable the USB3OTG U3 port early and leave it to the COMBPHY driver to re-enable the U3 port when a usb3-phy is described in the board device tree. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3528/rk3528.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c index 4892ff6ba9d..f9bfc445b85 100644 --- a/arch/arm/mach-rockchip/rk3528/rk3528.c +++ b/arch/arm/mach-rockchip/rk3528/rk3528.c @@ -9,6 +9,9 @@ #include #include +#define VPU_GRF_BASE 0xff340000 +#define USB3OTG_CON1 0x44 + #define FIREWALL_DDR_BASE 0xff2e0000 #define FW_DDR_MST6_REG 0x58 #define FW_DDR_MST7_REG 0x5c @@ -69,6 +72,9 @@ int arch_cpu_init(void) val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG); writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG); + /* Disable USB3OTG U3 port, later enabled in COMBPHY driver */ + writel(0xffff0181, VPU_GRF_BASE + USB3OTG_CON1); + return 0; } -- cgit v1.2.3 From ffa1485c8173668424ca0ad87020966658092772 Mon Sep 17 00:00:00 2001 From: Niu Zhihong Date: Wed, 23 Jul 2025 12:22:17 +0800 Subject: board: rockchip: Add Xunlong Orange Pi 5 Ultra The Orange Pi 5 Ultra is another board in the Orange Pi 5 family. Orange Pi 5 Ultra uses Rockchip RK3588, a new generation of octa-core 64-bit ARM processor, which includes quad-core A76 and quad-core A55. Features tested on a Orange Pi 5 Ultra 16GB: - SD-card boot - eMMC boot ROCKCHIP_TPL: https://github.com/rockchip-linux/rkbin/tree/master/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin BL31: https://github.com/rockchip-linux/rkbin/tree/master/bin/rk35/rk3588_bl31_v1.48.elf Signed-off-by: Niu Zhihong Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi (limited to 'arch') diff --git a/arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi b/arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi new file mode 100644 index 00000000000..1ab31a4ec5a --- /dev/null +++ b/arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-u-boot.dtsi" + +&fspim1_pins { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; + +&sfc { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; -- cgit v1.2.3 From 9d39a56922878562b263e45f45523021cf5e7789 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:17 +0000 Subject: rockchip: rk3588: Disable USB3OTG U3 ports early The RK3588 SoC comes with USB OTG support using a DWC3 controller with a USB2 PHY and a USB3 PHY (USBDP PHY). Some board designs may not use the USBDP PHY for USB3 purpose. For these board to use USB OTG the input clock source must change to use UTMI clk instead of PIPE clk. Change to always disable the USB3OTG U3 ports early and leave it to the USBDP PHY driver to re-enable the U3 port when a usb3-phy is described in the board device tree. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3588/rk3588.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index e2278ff792b..c01a4002089 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -15,6 +15,10 @@ #include #include +#define USB_GRF_BASE 0xfd5ac000 +#define USB3OTG0_CON1 0x001c +#define USB3OTG1_CON1 0x0034 + #define FIREWALL_DDR_BASE 0xfe030000 #define FW_DDR_MST5_REG 0x54 #define FW_DDR_MST13_REG 0x74 @@ -184,6 +188,10 @@ int arch_cpu_init(void) /* Disable JTAG exposed on SDMMC */ rk_clrreg(&sys_grf->soc_con[6], SYS_GRF_FORCE_JTAG); #endif + + /* Disable USB3OTG U3 ports, later enabled by USBDP PHY driver */ + writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1); + writel(0xffff0188, USB_GRF_BASE + USB3OTG1_CON1); #endif return 0; -- cgit v1.2.3 From be585d4916864387c53c82b4bde7f04093aac440 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:18 +0000 Subject: rockchip: rk3576: Disable USB3OTG0 U3 port early The RK3576 SoC comes with USB OTG support using a DWC3 controller with a USB2 PHY and a USB3 PHY (USBDP PHY). Some board designs may not use the USBDP PHY for USB3 purpose. For these board to use USB OTG the input clock source must change to use UTMI clk instead of PIPE clk. Change to always disable the USB3OTG0 U3 port early and leave it to the USBDP PHY driver to re-enable the U3 port when a usb3-phy is described in the board device tree. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3576/rk3576.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c index 2b1318f9532..a6c2fbdc484 100644 --- a/arch/arm/mach-rockchip/rk3576/rk3576.c +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -33,6 +33,9 @@ #define SGRF_DOMAIN_CON4 0x10 #define SGRF_DOMAIN_CON5 0x14 +#define USB_GRF_BASE 0x2601E000 +#define USB3OTG0_CON1 0x0030 + const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000", [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000", @@ -155,6 +158,9 @@ int arch_cpu_init(void) */ writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20); + /* Disable USB3OTG0 U3 port, later enabled by USBDP PHY driver */ + writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1); + return 0; } -- cgit v1.2.3 From 0e68a93d7c220e37cf6ffe88ba47373e39fe5001 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 21 Jul 2025 22:07:19 +0000 Subject: rockchip: rk3588-generic: Move usb nodes to board dts After the commit 7a53abb18325 ("rockchip: rk3588: Remove USB3 DRD nodes in u-boot.dtsi") was merged for v2024.10 there is no reason to keep the usb nodes for the Generic RK3588 board in the board u-boot.dtsi. Move usb related nodes from board u-boot.dtsi to main board device tree. While at it, also drop use of the usb3-phy as we only want to enable the usb2-phy to be compatible with as many boards as possible. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-generic-u-boot.dtsi | 18 ------------------ arch/arm/dts/rk3588-generic.dts | 16 ++++++++++++++++ 2 files changed, 16 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/rk3588-generic-u-boot.dtsi b/arch/arm/dts/rk3588-generic-u-boot.dtsi index f67301d87a6..853ed58cfe5 100644 --- a/arch/arm/dts/rk3588-generic-u-boot.dtsi +++ b/arch/arm/dts/rk3588-generic-u-boot.dtsi @@ -1,21 +1,3 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include "rk3588s-u-boot.dtsi" - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "peripheral"; - maximum-speed = "high-speed"; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588-generic.dts b/arch/arm/dts/rk3588-generic.dts index 95d757676f1..6740f9866f1 100644 --- a/arch/arm/dts/rk3588-generic.dts +++ b/arch/arm/dts/rk3588-generic.dts @@ -39,7 +39,23 @@ status = "okay"; }; +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; }; + +&usb_host0_xhci { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; -- cgit v1.2.3