From 92873f83d19fa8cedcace2b4c384e6b89ffd5faf Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 27 Jun 2021 17:51:01 -0600 Subject: x86: Don't set up MTRRs if previously done When starting U-Boot from a previous-stage bootloader we presumably don't need to set up the variable MTRRs. In fact this could be harmful if the existing settings are not what U-Boot uses. Skip that step in this case. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index e59215cc20e..c7f6c5a013e 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -423,7 +423,7 @@ static void setup_mtrr(void) u64 mtrr_cap; /* Configure fixed range MTRRs for some legacy regions */ - if (!gd->arch.has_mtrr) + if (!gd->arch.has_mtrr || !ll_boot_init()) return; mtrr_cap = native_read_msr(MTRR_CAP_MSR); -- cgit v1.2.3 From 0f5ca1d1f1d399191d6481d1c8853c9ca6fe25ff Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 27 Jun 2021 17:51:02 -0600 Subject: x86: Update the MP constants to avoid conflicts These constants conflict with error codes returned by the MP implementation when something is wrong. In particular, mp_first_cpu() returns MP_SELECT_BSP when running without multiprocessing enabled. Since this is -2, it is interpreted as an error by callers, which expect a positive CPU number for the first CPU. Correct this by using a different range for the pre-defined CPU numbers, above zero and out of the range of possible CPU values. For now it is safe to assume there are no more than 64K CPUs. This fixes the 'mtrr' command when CONFIG_SMP is not enabled. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/include/asm/mp.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h index 1a3ae8e3950..e48ba051d92 100644 --- a/arch/x86/include/asm/mp.h +++ b/arch/x86/include/asm/mp.h @@ -10,18 +10,22 @@ #include #include +#include struct udevice; enum { - /* Indicates that the function should run on all CPUs */ - MP_SELECT_ALL = -1, + /* + * Indicates that the function should run on all CPUs. We use a large + * number, above the number of real CPUs we expect to find. + */ + MP_SELECT_ALL = BIT(16), /* Run on boot CPUs */ - MP_SELECT_BSP = -2, + MP_SELECT_BSP, /* Run on non-boot CPUs */ - MP_SELECT_APS = -3, + MP_SELECT_APS, }; typedef int (*mp_callback_t)(struct udevice *cpu, void *arg); -- cgit v1.2.3 From 7052968707b2c16da6b9c43aa058435d2932eb82 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 27 Jun 2021 17:51:03 -0600 Subject: x86: Do cache set-up by default when booting from coreboot A recent change to disable cache setup when booting from coreboot assumed that this has been done by SPL. The result is that for the coreboot board, the cache is disabled (in start.S) and never re-enabled. If the cache was turned off, as it is on boards without SPL, we should turn it back on. Add this new condition. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/lib/init_helpers.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 67401b9ba79..f33194045f9 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -18,10 +18,20 @@ int init_cache_f_r(void) IS_ENABLED(CONFIG_FSP_VERSION2); int ret; - if (!ll_boot_init()) - return 0; - - do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) && + /* + * Supported configurations: + * + * booting from slimbootloader - in that case the MTRRs are already set + * up + * booting with FSPv1 - MTRRs are already set up + * booting with FSPv2 - MTRRs must be set here + * booting from coreboot - in this case there is no SPL, so we set up + * the MTRRs here + * Note: if there is an SPL, then it has already set up MTRRs so we + * don't need to do that here + */ + do_mtrr &= !IS_ENABLED(CONFIG_SPL) && + !IS_ENABLED(CONFIG_FSP_VERSION1) && !IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER); if (do_mtrr) { -- cgit v1.2.3 From c5c62155c542368269d7a0e968401e76abcc2490 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 27 Jun 2021 17:51:06 -0600 Subject: x86: Add function comments to cb_sysinfo.h Add a function comment for get_coreboot_info() and a declaration for cb_get_sysinfo(), since this may be called from elsewhere. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/include/asm/cb_sysinfo.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch') diff --git a/arch/x86/include/asm/cb_sysinfo.h b/arch/x86/include/asm/cb_sysinfo.h index 675eef6f2c9..75901359f98 100644 --- a/arch/x86/include/asm/cb_sysinfo.h +++ b/arch/x86/include/asm/cb_sysinfo.h @@ -215,6 +215,22 @@ struct sysinfo_t { extern struct sysinfo_t lib_sysinfo; +/** + * get_coreboot_info() - parse the coreboot sysinfo table + * + * Parses the coreboot table if found, setting the GD_FLG_SKIP_LL_INIT flag if + * so. + * + * @info: Place to put the parsed information + * @return 0 if OK, -ENOENT if no table found + */ int get_coreboot_info(struct sysinfo_t *info); +/** + * cb_get_sysinfo() - get a pointer to the parsed coreboot sysinfo + * + * @return pointer to sysinfo, or NULL if not available + */ +const struct sysinfo_t *cb_get_sysinfo(void); + #endif -- cgit v1.2.3 From 4dfe4b44cc7f0df78d9013619ec6c411e7b60bbd Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 27 Jun 2021 17:51:07 -0600 Subject: x86: coreboot: Use vendor in the Kconfig Use VENDOR_COREBOOT instead of TARGET_COREBOOT so we can have multiple coreboot boards, sharing options. Only SYS_CONFIG_NAME needs to be defined TARGET_COREBOOT. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/coreboot/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig index 497d6284ac1..b97c2779041 100644 --- a/arch/x86/cpu/coreboot/Kconfig +++ b/arch/x86/cpu/coreboot/Kconfig @@ -1,4 +1,4 @@ -if TARGET_COREBOOT +if VENDOR_COREBOOT config SYS_COREBOOT bool -- cgit v1.2.3 From 54e0bd1728a4db60fd87a5c385250e173d03674e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 27 Jun 2021 17:51:09 -0600 Subject: x86: cros: Check ROM exists before building vboot All the x86 devicetree files are built at once, whichever board is actually being built. If coreboot is the target build, CONFIG_ROM_SIZE is not defined and samus cannot build Chromium OS verified boot. Add this condition to avoid errors about CONFIG_ROM_SIZE being missing. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Reviewed-by: Jaehoon Chung --- arch/x86/dts/chromebook_coral.dts | 2 +- arch/x86/dts/chromebook_samus.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index c8cb4e21c6d..66c31efb6cd 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -10,7 +10,7 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -#ifdef CONFIG_CHROMEOS_VBOOT +#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE) #include "chromeos-x86.dtsi" #include "flashmap-x86-ro.dtsi" #include "flashmap-16mb-rw.dtsi" diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts index adaeb1ea355..ad35ab2e3fd 100644 --- a/arch/x86/dts/chromebook_samus.dts +++ b/arch/x86/dts/chromebook_samus.dts @@ -11,7 +11,7 @@ #include "smbios.dtsi" -#ifdef CONFIG_CHROMEOS_VBOOT +#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE) #include "chromeos-x86.dtsi" #include "flashmap-x86-ro.dtsi" #include "flashmap-8mb-rw.dtsi" -- cgit v1.2.3 From 2f91fc40039d2ef6f433d5c56c4f4701975f510f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 10 Jul 2021 21:15:21 -0600 Subject: x86: Ensure the e820 map is installed in all cases This is a revert of a recent logic change in setup_zimage(). We do actually need to install this information always. Change it to install from the Coreboot tables if available, else the normal source. Fixes: e7bae8283fe ("x86: Allow installing an e820 when booting from coreboot") Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/lib/zimage.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 90fc8a466d7..cf4210cd4ba 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -313,12 +313,12 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, int bootproto = get_boot_protocol(hdr, false); log_debug("Setup E820 entries\n"); - if (ll_boot_init()) { - setup_base->e820_entries = install_e820_map( - ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map); - } else if (IS_ENABLED(CONFIG_COREBOOT_SYSINFO)) { + if (IS_ENABLED(CONFIG_COREBOOT_SYSINFO)) { setup_base->e820_entries = cb_install_e820_map( ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map); + } else { + setup_base->e820_entries = install_e820_map( + ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map); } if (bootproto == 0x0100) { -- cgit v1.2.3