From c2a8b4f879e89a158fc1f9fbcf9d78b2ad4cefde Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Thu, 19 Dec 2019 18:59:27 +0800 Subject: powerpc/mpc85xx: drop eSDHC periperhal clock code The below patch added eSDHC periperhal clock code initially. 2d9ca2c mmc: fsl_esdhc: Add peripheral clock support The purpose was to fix up device tree properties "peripheral-frequency" so that linux could get the periperhal clock by it. However the implementation on both u-boot and linux was only for a Freescale SDK release. The linux part implementation had never been upstreamed. These code should not have been exist on u-boot mainline. Let's remove the powerpc part changes but keep the changes in fsl_esdhc driver. The changes in fsl_esdhc driver could be utilized to support SD UHS and eMMC HS200/HS400 speed modes for current Layerscape ARM platforms. Signed-off-by: Yangbo Lu --- arch/powerpc/cpu/mpc85xx/speed.c | 49 +------------------------------ arch/powerpc/include/asm/config_mpc85xx.h | 8 ----- 2 files changed, 1 insertion(+), 56 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 15b05fcc513..0c5252edc27 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -69,8 +69,7 @@ void get_sys_info(sys_info_t *sys_info) [14] = 4, /* CC4 PPL / 4 */ }; uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; -#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \ - defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) +#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) uint rcw_tmp; #endif uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; @@ -450,48 +449,6 @@ void get_sys_info(sys_info_t *sys_info) #endif #endif -#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK -#if defined(CONFIG_ARCH_T2080) -#define ESDHC_CLK_SEL 0x00000007 -#define ESDHC_CLK_SHIFT 0 -#define ESDHC_CLK_RCWSR 15 -#else /* Support T1040 T1024 by now */ -#define ESDHC_CLK_SEL 0xe0000000 -#define ESDHC_CLK_SHIFT 29 -#define ESDHC_CLK_RCWSR 7 -#endif - rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]); - switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) { - case 1: - sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK]; - break; - case 2: - sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2; - break; - case 3: - sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3; - break; -#if defined(CONFIG_SYS_SDHC_CLK_2_PLL) - case 4: - sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4; - break; -#if defined(CONFIG_ARCH_T2080) - case 5: - sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK]; - break; -#endif - case 6: - sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2; - break; - case 7: - sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3; - break; -#endif - default: - sys_info->freq_sdhc = 0; - printf("Error: Unknown SDHC peripheral clock select!\n"); - } -#endif #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { @@ -673,15 +630,11 @@ int get_clocks (void) gd->arch.i2c2_clk = gd->arch.i2c1_clk; #if defined(CONFIG_FSL_ESDHC) -#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK - gd->arch.sdhc_clk = sys_info.freq_sdhc / 2; -#else #if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010) gd->arch.sdhc_clk = gd->bus_clk; #else gd->arch.sdhc_clk = gd->bus_clk / 2; #endif -#endif #endif /* defined(CONFIG_FSL_ESDHC) */ #if defined(CONFIG_CPM2) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 946e74a93bb..4ca1e2b325f 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -331,9 +331,6 @@ #define CONFIG_SYS_FMAN_V3 #define CONFIG_FM_PLAT_CLK_DIV 1 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV -#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 - per rcw field value */ -#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK #define CONFIG_SYS_FSL_TBCLK_DIV 16 @@ -362,8 +359,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FM1_CLK 0 -#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 - per rcw field value */ #define CONFIG_QBMAN_CLK_DIV 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK @@ -402,9 +397,6 @@ #define CONFIG_PME_PLAT_CLK_DIV 1 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FM1_CLK 0 -#define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2 - per rcw field value */ -#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -- cgit v1.3.1 From ac76dd0836468445e1ba4d756617d677ed58f59b Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Thu, 19 Dec 2019 18:59:28 +0800 Subject: Add global variable sdhc_per_clk for arm/powerpc The QorIQ eSDHC controller supports two reference clocks. They are platform clock and periperhal clock. The global variable sdhc_clk has already been used for platform clock. This patch is to add another global variable sdhc_per_clk for periperhal clock, which provides higher frequency and is required to be used for SD UHS and eMMC HS200/HS400 speed modes. Signed-off-by: Yangbo Lu --- arch/arm/include/asm/global_data.h | 4 ++++ arch/powerpc/include/asm/global_data.h | 1 + 2 files changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 17740147eaf..f23b6bfb75b 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -13,6 +13,10 @@ struct arch_global_data { u32 sdhc_clk; #endif +#if defined(CONFIG_FSL_ESDHC) + u32 sdhc_per_clk; +#endif + #if defined(CONFIG_U_QE) u32 qe_clk; u32 brg_clk; diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index b6e4dd6c807..1620fba0143 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -14,6 +14,7 @@ struct arch_global_data { #if defined(CONFIG_FSL_ESDHC) u32 sdhc_clk; + u32 sdhc_per_clk; #if defined(CONFIG_FSL_ESDHC_ADAPTER_IDENT) u8 sdhc_adapter; #endif -- cgit v1.3.1 From f1bce084264f52caca80ca56815d6c4b4c5d5935 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Thu, 19 Dec 2019 18:59:30 +0800 Subject: Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usage The eSDHC reference clocks should be provided by speed.c in arch/. And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to select which clock to use. Because we can make the driver to select the periperhal clock which is better (provides higher frequency) automatically if its value is provided by speed.c. This patch is to drop this option and make driver to select clock automatically. Also fix peripheral clock calculation issue in fsl_lsch2_speed.c/fsl_lsch3_speed.c. Signed-off-by: Yangbo Lu --- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 29 +++++++------------- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 22 +++++++-------- drivers/mmc/Kconfig | 9 ------ drivers/mmc/fsl_esdhc.c | 32 +++++++++++++++------- 4 files changed, 42 insertions(+), 50 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 25e9a495f7f..fec231857bf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -125,7 +125,6 @@ void get_sys_info(struct sys_info *sys_info) } #endif -#ifdef CONFIG_FSL_ESDHC #define HWA_CGA_M2_CLK_SEL 0x00000007 #define HWA_CGA_M2_CLK_SHIFT 0 #if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB) @@ -148,11 +147,10 @@ void get_sys_info(struct sys_info *sys_info) break; #endif default: - printf("Error: Unknown peripheral clock select!\n"); + printf("Error: Unknown cluster group A mux 2 clock select!\n"); break; } #endif -#endif #if defined(CONFIG_FSL_IFC) sys_info->freq_localbus = sys_info->freq_systembus / @@ -179,28 +177,21 @@ unsigned long get_qman_freq(void) int get_clocks(void) { struct sys_info sys_info; - +#ifdef CONFIG_FSL_ESDHC + u32 clock = 0; +#endif get_sys_info(&sys_info); gd->cpu_clk = sys_info.freq_processor[0]; gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV; gd->mem_clk = sys_info.freq_ddrbus; - #ifdef CONFIG_FSL_ESDHC -#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) -#if defined(CONFIG_TARGET_LS1046ARDB) - gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2; -#endif -#if defined(CONFIG_TARGET_LS1043ARDB) - gd->arch.sdhc_clk = sys_info.freq_cga_m2; -#endif -#if defined(CONFIG_TARGET_LS1012ARDB) - gd->arch.sdhc_clk = sys_info.freq_systembus; -#endif -#else - gd->arch.sdhc_clk = (sys_info.freq_systembus / - CONFIG_SYS_FSL_PCLK_DIV) / - CONFIG_SYS_FSL_SDHC_CLK_DIV; +#if defined(CONFIG_ARCH_LS1012A) + clock = sys_info.freq_systembus; +#elif defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) + clock = sys_info.freq_cga_m2; #endif + gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV; + gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV; #endif if (gd->cpu_clk != 0) return 0; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 4b047a39c07..bd8b9cbdadd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -160,14 +160,14 @@ void get_sys_info(struct sys_info *sys_info) break; } #endif -#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) - sys_info->freq_cga_m2 = sys_info->freq_systembus; -#endif } int get_clocks(void) { struct sys_info sys_info; +#ifdef CONFIG_FSL_ESDHC + u32 clock = 0; +#endif get_sys_info(&sys_info); gd->cpu_clk = sys_info.freq_processor[0]; gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV; @@ -175,18 +175,16 @@ int get_clocks(void) #ifdef CONFIG_SYS_FSL_HAS_DP_DDR gd->arch.mem2_clk = sys_info.freq_ddrbus2; #endif -#if defined(CONFIG_FSL_ESDHC) -#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) -#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) - gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2; -#endif -#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) - gd->arch.sdhc_clk = sys_info.freq_cga_m2; + +#ifdef CONFIG_FSL_ESDHC +#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A) + clock = sys_info.freq_cga_m2; +#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) + clock = sys_info.freq_systembus; #endif -#else + gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV; gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV; #endif -#endif /* defined(CONFIG_FSL_ESDHC) */ if (gd->cpu_clk != 0) return 0; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 2bc19dd56b3..6371ffef11a 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -711,19 +711,10 @@ endif config FSL_ESDHC bool "Freescale/NXP eSDHC controller support" - select FSL_ESDHC_USE_PERIPHERAL_CLK if MMC_HS200_SUPPORT || MMC_UHS_SUPPORT help This selects support for the eSDHC (Enhanced Secure Digital Host Controller) found on numerous Freescale/NXP SoCs. -config FSL_ESDHC_USE_PERIPHERAL_CLK - bool "enable ESDHC peripheral clock support" - depends on FSL_ESDHC - help - eSDHC supports two reference clocks (platform clock and peripheral clock). - Peripheral clock which could provide higher clock frequency is required to - be used for tuning of SD UHS mode and eMMC HS200/HS400 modes. - config FSL_ESDHC_IMX bool "Freescale/NXP i.MX eSDHC controller support" help diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 8655503319e..112f1150158 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -81,6 +81,7 @@ struct fsl_esdhc_plat { struct fsl_esdhc_priv { struct fsl_esdhc *esdhc_regs; unsigned int sdhc_clk; + bool is_sdhc_per_clk; unsigned int clock; #if !CONFIG_IS_ENABLED(DM_MMC) struct mmc *mmc; @@ -523,7 +524,6 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); } -#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable) { struct fsl_esdhc *regs = priv->esdhc_regs; @@ -550,18 +550,18 @@ static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable) mdelay(1); } } -#endif static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) { struct fsl_esdhc *regs = priv->esdhc_regs; -#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK - /* Select to use peripheral clock */ - esdhc_clock_control(priv, false); - esdhc_setbits32(®s->esdhcctl, ESDHCCTL_PCS); - esdhc_clock_control(priv, true); -#endif + if (priv->is_sdhc_per_clk) { + /* Select to use peripheral clock */ + esdhc_clock_control(priv, false); + esdhc_setbits32(®s->esdhcctl, ESDHCCTL_PCS); + esdhc_clock_control(priv, true); + } + /* Set the clock speed */ if (priv->clock != mmc->clock) set_sysctl(priv, mmc, mmc->clock); @@ -779,6 +779,8 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); priv->sdhc_clk = cfg->sdhc_clk; + if (gd->arch.sdhc_per_clk) + priv->is_sdhc_per_clk = true; mmc_cfg = &plat->cfg; @@ -817,7 +819,11 @@ int fsl_esdhc_mmc_init(bd_t *bis) cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; - cfg->sdhc_clk = gd->arch.sdhc_clk; + /* Prefer peripheral clock which provides higher frequency. */ + if (gd->arch.sdhc_per_clk) + cfg->sdhc_clk = gd->arch.sdhc_per_clk; + else + cfg->sdhc_clk = gd->arch.sdhc_clk; return fsl_esdhc_initialize(bis, cfg); } #else /* DM_MMC */ @@ -839,7 +845,13 @@ static int fsl_esdhc_probe(struct udevice *dev) #endif priv->dev = dev; - priv->sdhc_clk = gd->arch.sdhc_clk; + if (gd->arch.sdhc_per_clk) { + priv->sdhc_clk = gd->arch.sdhc_per_clk; + priv->is_sdhc_per_clk = true; + } else { + priv->sdhc_clk = gd->arch.sdhc_clk; + } + if (priv->sdhc_clk <= 0) { dev_err(dev, "Unable to get clk for %s\n", dev->name); return -EINVAL; -- cgit v1.3.1