From 98036fbdaf0ac1d6dc3ab3cb6db24c020bb65d6f Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 27 Feb 2020 17:21:56 +0200 Subject: x86: acpi: Let OS know that console already had been initialized SPCR has no clue if the UART base clock speed is different to the default one. However, the SPCR 1.04 defines baud rate 0 as a preconfigured state of UART and OS is supposed not to touch the configuration of the serial device. Linux kernel supports that starting from v5.0, see commit b413b1abeb21 ("ACPI: SPCR: Consider baud rate 0 as preconfigured state") for the details. Signed-off-by: Andy Shevchenko Reviewed-by: Bin Meng --- arch/x86/lib/acpi_table.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 66e32f21bdb..074987e2943 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -471,6 +471,15 @@ static void acpi_create_spcr(struct acpi_spcr *spcr) spcr->pci_device_id = 0xffff; spcr->pci_vendor_id = 0xffff; + /* + * SPCR has no clue if the UART base clock speed is different + * to the default one. However, the SPCR 1.04 defines baud rate + * 0 as a preconfigured state of UART and OS is supposed not + * to touch the configuration of the serial device. + */ + if (serial_info.clock != SERIAL_DEFAULT_CLOCK) + spcr->baud_rate = 0; + /* Fix checksum */ header->checksum = table_compute_checksum((void *)spcr, header->length); } -- cgit v1.3.1 From 32e8ee004a3dad1a9cc06bd3ac44d8ba562afc3e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 8 Apr 2020 16:57:24 -0600 Subject: tpm: cr50: Use the correct GPIO binding This device should use ready-gpios rather than ready-gpio. Fix it. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/dts/chromebook_coral.dts | 2 +- doc/device-tree-bindings/gpio/intel,apl-gpio.txt | 2 +- doc/device-tree-bindings/interrupt-controller/intel,acpi-gpe.txt | 2 +- drivers/tpm/cr50_i2c.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index af52e11c89a..d48ef3573ec 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -292,7 +292,7 @@ reg = <0x50>; compatible = "google,cr50"; u-boot,i2c-offset-len = <0>; - ready-gpio = <&gpio_n 28 GPIO_ACTIVE_LOW>; + ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>; interrupts-extended = <&acpi_gpe 0x3c 0>; }; }; diff --git a/doc/device-tree-bindings/gpio/intel,apl-gpio.txt b/doc/device-tree-bindings/gpio/intel,apl-gpio.txt index cf0659b70ec..8422ff63abd 100644 --- a/doc/device-tree-bindings/gpio/intel,apl-gpio.txt +++ b/doc/device-tree-bindings/gpio/intel,apl-gpio.txt @@ -47,7 +47,7 @@ Example: reg = <0x50>; compatible = "google,cr50"; u-boot,i2c-offset-len = <0>; - ready-gpio = <&gpio_n GPIO_28 GPIO_ACTIVE_LOW>; + ready-gpios = <&gpio_n GPIO_28 GPIO_ACTIVE_LOW>; }; }; diff --git a/doc/device-tree-bindings/interrupt-controller/intel,acpi-gpe.txt b/doc/device-tree-bindings/interrupt-controller/intel,acpi-gpe.txt index d9252bf29f7..2fe02d8a227 100644 --- a/doc/device-tree-bindings/interrupt-controller/intel,acpi-gpe.txt +++ b/doc/device-tree-bindings/interrupt-controller/intel,acpi-gpe.txt @@ -25,6 +25,6 @@ Example: tpm@50 { reg = <0x50>; compatible = "google,cr50"; - ready-gpio = <&gpio_n 0x1c GPIO_ACTIVE_LOW>; + ready-gpios = <&gpio_n 0x1c GPIO_ACTIVE_LOW>; interrupts-extended = <&acpi_gpe 0x3c 0>; }; diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c index c1d2d2fa381..b67051af26a 100644 --- a/drivers/tpm/cr50_i2c.c +++ b/drivers/tpm/cr50_i2c.c @@ -607,7 +607,7 @@ static int cr50_i2c_ofdata_to_platdata(struct udevice *dev) priv->irq = irq; priv->use_irq = true; } else { - ret = gpio_request_by_name(dev, "ready-gpio", 0, + ret = gpio_request_by_name(dev, "ready-gpios", 0, &priv->ready_gpio, GPIOD_IS_IN); if (ret) { log_warning("Cr50 does not have an ready GPIO/interrupt (err=%d)\n", -- cgit v1.3.1 From 2831405447caeb55b5f6b625c8be9a4a2f8fcaca Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 8 Apr 2020 16:57:27 -0600 Subject: x86: Correct wording of coreboot source code Some files are taken or modified from coreboot, but the files are no-longer part of the coreboot project. Fix the wording in a few places. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Reviewed-by: Wolfgang Wallner --- arch/x86/cpu/coreboot/timestamp.c | 4 ++-- arch/x86/include/asm/arch-coreboot/timestamp.h | 4 ++-- arch/x86/include/asm/intel_pinctrl_defs.h | 2 -- 3 files changed, 4 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/x86/cpu/coreboot/timestamp.c b/arch/x86/cpu/coreboot/timestamp.c index e698200d704..e8ccaf22129 100644 --- a/arch/x86/cpu/coreboot/timestamp.c +++ b/arch/x86/cpu/coreboot/timestamp.c @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * This file is part of the coreboot project. - * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * Modified from the coreboot version */ #include diff --git a/arch/x86/include/asm/arch-coreboot/timestamp.h b/arch/x86/include/asm/arch-coreboot/timestamp.h index 9320afba561..85d42c02c46 100644 --- a/arch/x86/include/asm/arch-coreboot/timestamp.h +++ b/arch/x86/include/asm/arch-coreboot/timestamp.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * Taken from the coreboot version */ #ifndef __COREBOOT_TIMESTAMP_H__ diff --git a/arch/x86/include/asm/intel_pinctrl_defs.h b/arch/x86/include/asm/intel_pinctrl_defs.h index 6da06bb52b4..1ea141f082f 100644 --- a/arch/x86/include/asm/intel_pinctrl_defs.h +++ b/arch/x86/include/asm/intel_pinctrl_defs.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2015-2016 Intel Corp. * Copyright 2019 Google LLC * -- cgit v1.3.1 From 163085308576139ac0b0c65e3b81be78ab890aa9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 8 Apr 2020 16:57:28 -0600 Subject: x86: apl: Move p2sb ofdata reading to the correct method With P2SB the initial BAR (base-address register) is set up by TPL and this is used unchanged right through U-Boot. At present the reading of this address is split between the ofdata() and probe() methods. There are a few problems that are unique to the p2sb. One is that its children need to call pcr_read32(), etc. which needs to have the p2sb address correct. Also some of its children are pinctrl devices and pinctrl is used when any device is probed. So p2sb really needs to get its base address set up in ofdata_to_platdata(), before it is probed. Another point is that reading the p2sb BAR will not work if the p2sb is hidden. The FSP-S seems to hide it, presumably to avoid confusing PCI enumeration. Reading ofdata in ofdata_to_platdata() is the correct place anyway, so this is easy to fix. Move the code into one place and use the early-regs property in all cases for simplicity and to avoid needing to probe any PCI devices just to read the BAR. Signed-off-by: Simon Glass Reviewed-by: Wolfgang Wallner Tested-by: Wolfgang Wallner --- arch/x86/cpu/intel_common/p2sb.c | 33 +++++++++++---------------------- 1 file changed, 11 insertions(+), 22 deletions(-) (limited to 'arch') diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c index d5b4846e0a2..6f3c4416186 100644 --- a/arch/x86/cpu/intel_common/p2sb.c +++ b/arch/x86/cpu/intel_common/p2sb.c @@ -92,46 +92,35 @@ int p2sb_ofdata_to_platdata(struct udevice *dev) #if !CONFIG_IS_ENABLED(OF_PLATDATA) int ret; + u32 base[2]; + ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base)); + if (ret) + return log_msg_ret("Missing/short early-regs", ret); + plat->mmio_base = base[0]; + /* TPL sets up the initial BAR */ if (spl_phase() == PHASE_TPL) { - u32 base[2]; - - /* TPL sets up the initial BAR */ - ret = dev_read_u32_array(dev, "early-regs", base, - ARRAY_SIZE(base)); - if (ret) - return log_msg_ret("Missing/short early-regs", ret); - plat->mmio_base = base[0]; plat->bdf = pci_get_devfn(dev); if (plat->bdf < 0) return log_msg_ret("Cannot get p2sb PCI address", plat->bdf); } + upriv->mmio_base = plat->mmio_base; #else plat->mmio_base = plat->dtplat.early_regs[0]; plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]); -#endif upriv->mmio_base = plat->mmio_base; - debug("p2sb: mmio_base=%x\n", (uint)plat->mmio_base); +#endif return 0; } static int p2sb_probe(struct udevice *dev) { - if (spl_phase() == PHASE_TPL) { + if (spl_phase() == PHASE_TPL) return p2sb_early_init(dev); - } else { - struct p2sb_platdata *plat = dev_get_platdata(dev); - - plat->mmio_base = dev_read_addr_pci(dev); - /* Don't set BDF since it should not be used */ - if (!plat->mmio_base || plat->mmio_base == FDT_ADDR_T_NONE) - return -EINVAL; - - if (spl_phase() == PHASE_SPL) - return p2sb_spl_init(dev); - } + else if (spl_phase() == PHASE_SPL) + return p2sb_spl_init(dev); return 0; } -- cgit v1.3.1 From b2c386846332e9fc1571aa1eed3ac47b903bd32c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 8 Apr 2020 16:57:30 -0600 Subject: x86: apl: Add Global NVS table header Add the C version of this header. It includes a few Chrome OS bits which are disabled for a normal build. Signed-off-by: Simon Glass Reviewed-by: Wolfgang Wallner --- arch/x86/include/asm/arch-apollolake/global_nvs.h | 36 +++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 arch/x86/include/asm/arch-apollolake/global_nvs.h (limited to 'arch') diff --git a/arch/x86/include/asm/arch-apollolake/global_nvs.h b/arch/x86/include/asm/arch-apollolake/global_nvs.h new file mode 100644 index 00000000000..fe62194b02e --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/global_nvs.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015-2017 Intel Corp. + * (Written by Lance Zhao for Intel Corp.) + * Copyright Google LLC 2019 + * + * Modified from coreboot apollolake/include/soc/nvs.h + */ + +#ifndef _GLOBAL_NVS_H_ +#define _GLOBAL_NVS_H_ + +struct __packed acpi_global_nvs { + /* Miscellaneous */ + u8 pcnt; /* 0x00 - Processor Count */ + u8 ppcm; /* 0x01 - Max PPC State */ + u8 lids; /* 0x02 - LID State */ + u8 pwrs; /* 0x03 - AC Power State */ + u8 dpte; /* 0x04 - Enable DPTF */ + u32 cbmc; /* 0x05 - 0x08 - U-Boot Console */ + u64 pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ + u64 gpei; /* 0x11 - 0x18 - GPE Wake Source */ + u64 nhla; /* 0x19 - 0x20 - NHLT Address */ + u32 nhll; /* 0x21 - 0x24 - NHLT Length */ + u32 prt0; /* 0x25 - 0x28 - PERST_0 Address */ + u8 scdp; /* 0x29 - SD_CD GPIO portid */ + u8 scdo; /* 0x2a - GPIO pad offset relative to the community */ + u8 uior; /* 0x2b - UART debug controller init on S3 resume */ + u8 ecps; /* 0x2c - SGX Enabled status */ + u64 emna; /* 0x2d - 0x34 EPC base address */ + u64 elng; /* 0x35 - 0x3c EPC Length */ + u8 unused1[0x100 - 0x3d]; /* Pad out to 256 bytes */ + u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */ +}; + +#endif /* _GLOBAL_NVS_H_ */ -- cgit v1.3.1 From f50cc9528850ed546b44894cdc7ab4ceb4b30550 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 8 Apr 2020 16:57:34 -0600 Subject: acpi: Add a simple sandbox test Add a sandbox test for the basic ACPI functionality we have so far. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Reviewed-by: Wolfgang Wallner --- arch/sandbox/dts/test.dts | 4 +++ arch/sandbox/include/asm/acpi_table.h | 9 ++++++ include/dm/uclass-id.h | 1 + test/dm/Makefile | 1 + test/dm/acpi.c | 55 +++++++++++++++++++++++++++++++++++ 5 files changed, 70 insertions(+) create mode 100644 arch/sandbox/include/asm/acpi_table.h create mode 100644 test/dm/acpi.c (limited to 'arch') diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 4a277934a71..5fa951ad4b6 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -206,6 +206,10 @@ compatible = "denx,u-boot-devres-test"; }; + acpi-test { + compatible = "denx,u-boot-acpi-test"; + }; + clocks { clk_fixed: clk-fixed { compatible = "fixed-clock"; diff --git a/arch/sandbox/include/asm/acpi_table.h b/arch/sandbox/include/asm/acpi_table.h new file mode 100644 index 00000000000..921c7f4201d --- /dev/null +++ b/arch/sandbox/include/asm/acpi_table.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef __ASM_ACPI_TABLE_H__ +#define __ASM_ACPI_TABLE_H__ + +#endif /* __ASM_ACPI_TABLE_H__ */ diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 598f65ea7a3..37ada51f9f7 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -20,6 +20,7 @@ enum uclass_id { UCLASS_TEST_PROBE, UCLASS_TEST_DUMMY, UCLASS_TEST_DEVRES, + UCLASS_TEST_ACPI, UCLASS_SPI_EMUL, /* sandbox SPI device emulator */ UCLASS_I2C_EMUL, /* sandbox I2C device emulator */ UCLASS_I2C_EMUL_PARENT, /* parent for I2C device emulators */ diff --git a/test/dm/Makefile b/test/dm/Makefile index dd1ceff86c0..3daf8a544ea 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_UT_DM) += test-uclass.o # subsystem you must add sandbox tests here. obj-$(CONFIG_UT_DM) += core.o ifneq ($(CONFIG_SANDBOX),) +obj-$(CONFIG_ACPIGEN) += acpi.o obj-$(CONFIG_SOUND) += audio.o obj-$(CONFIG_BLK) += blk.o obj-$(CONFIG_BOARD) += board.o diff --git a/test/dm/acpi.c b/test/dm/acpi.c new file mode 100644 index 00000000000..3677cdd0cc5 --- /dev/null +++ b/test/dm/acpi.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Tests for ACPI table generation + * + * Copyright 2019 Google LLC + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include + +#define ACPI_TEST_DEV_NAME "ABCD" + +static int testacpi_get_name(const struct udevice *dev, char *out_name) +{ + return acpi_copy_name(out_name, ACPI_TEST_DEV_NAME); +} + +struct acpi_ops testacpi_ops = { + .get_name = testacpi_get_name, +}; + +static const struct udevice_id testacpi_ids[] = { + { .compatible = "denx,u-boot-acpi-test" }, + { } +}; + +U_BOOT_DRIVER(testacpi_drv) = { + .name = "testacpi_drv", + .of_match = testacpi_ids, + .id = UCLASS_TEST_ACPI, + ACPI_OPS_PTR(&testacpi_ops) +}; + +UCLASS_DRIVER(testacpi) = { + .name = "testacpi", + .id = UCLASS_TEST_ACPI, +}; + +/* Test ACPI get_name() */ +static int dm_test_acpi_get_name(struct unit_test_state *uts) +{ + char name[ACPI_NAME_MAX]; + struct udevice *dev; + + ut_assertok(uclass_first_device_err(UCLASS_TEST_ACPI, &dev)); + ut_assertok(acpi_get_name(dev, name)); + ut_asserteq_str(ACPI_TEST_DEV_NAME, name); + + return 0; +} +DM_TEST(dm_test_acpi_get_name, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); -- cgit v1.3.1 From 3cabcf966d42649cd60eb575c9cf5c22eb9e9123 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 8 Apr 2020 16:57:35 -0600 Subject: x86: Move acpi_s3.h to include/acpi/ This header relates to ACPI and we are about to add some more ACPI headers. Move this one into a new directory so they are together. The header inclusion in pci_rom.c is not specific to x86 anymore, so drop the #ifdef CONFIG_X86. Signed-off-by: Simon Glass Reviewed-by: Andy Shevchenko Reviewed-by: Wolfgang Wallner Reviewed-by: Bin Meng --- arch/x86/cpu/apollolake/cpu_spl.c | 2 +- arch/x86/cpu/apollolake/fsp_s.c | 2 +- arch/x86/cpu/apollolake/pmc.c | 2 +- arch/x86/cpu/baytrail/acpi.c | 4 +- arch/x86/cpu/cpu.c | 2 +- arch/x86/cpu/wakeup.S | 2 +- arch/x86/lib/acpi_s3.c | 2 +- arch/x86/lib/coreboot_table.c | 2 +- arch/x86/lib/fsp/fsp_common.c | 2 +- arch/x86/lib/fsp1/fsp_common.c | 2 +- arch/x86/lib/fsp2/fsp_dram.c | 2 +- drivers/pci/pci_rom.c | 4 +- drivers/power/acpi_pmc/acpi-pmc-uclass.c | 2 +- drivers/sysreset/sysreset_x86.c | 2 +- include/acpi/acpi_s3.h | 130 +++++++++++++++++++++++++++++++ include/acpi_s3.h | 130 ------------------------------- 16 files changed, 145 insertions(+), 147 deletions(-) create mode 100644 include/acpi/acpi_s3.h delete mode 100644 include/acpi_s3.h (limited to 'arch') diff --git a/arch/x86/cpu/apollolake/cpu_spl.c b/arch/x86/cpu/apollolake/cpu_spl.c index 8a39c3128e0..e2509e391fa 100644 --- a/arch/x86/cpu/apollolake/cpu_spl.c +++ b/arch/x86/cpu/apollolake/cpu_spl.c @@ -6,13 +6,13 @@ */ #include -#include #include #include #include #include #include #include +#include #include #include #include diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c index 1f22c1ea3c6..17cf1682ad0 100644 --- a/arch/x86/cpu/apollolake/fsp_s.c +++ b/arch/x86/cpu/apollolake/fsp_s.c @@ -5,11 +5,11 @@ */ #include -#include #include #include #include #include +#include #include #include #include diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c index aec0c8394c2..4ea7c7447bc 100644 --- a/arch/x86/cpu/apollolake/pmc.c +++ b/arch/x86/cpu/apollolake/pmc.c @@ -9,10 +9,10 @@ #define LOG_CATEGORY UCLASS_ACPI_PMC #include -#include #include #include #include +#include #include #include #include diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index f44228e6939..3c27391873c 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -4,15 +4,15 @@ */ #include -#include #include #include -#include +#include #include #include #include #include #include +#include void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, void *dsdt) diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index dae06949cc6..246ee50948c 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -19,7 +19,6 @@ */ #include -#include #include #include #include @@ -27,6 +26,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/cpu/wakeup.S b/arch/x86/cpu/wakeup.S index 244ca1276af..093bf3bcc5c 100644 --- a/arch/x86/cpu/wakeup.S +++ b/arch/x86/cpu/wakeup.S @@ -5,7 +5,7 @@ * From coreboot src/arch/x86/wakeup.S */ -#include +#include #include #include diff --git a/arch/x86/lib/acpi_s3.c b/arch/x86/lib/acpi_s3.c index 197636c4b50..c3759ec8492 100644 --- a/arch/x86/lib/acpi_s3.c +++ b/arch/x86/lib/acpi_s3.c @@ -4,7 +4,7 @@ */ #include -#include +#include #include #include #include diff --git a/arch/x86/lib/coreboot_table.c b/arch/x86/lib/coreboot_table.c index 2943e11d2a4..c996fc588df 100644 --- a/arch/x86/lib/coreboot_table.c +++ b/arch/x86/lib/coreboot_table.c @@ -4,9 +4,9 @@ */ #include -#include #include #include +#include #include #include diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 5eff0f99aad..267527eb344 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -4,11 +4,11 @@ */ #include -#include #include #include #include #include +#include #include #include #include diff --git a/arch/x86/lib/fsp1/fsp_common.c b/arch/x86/lib/fsp1/fsp_common.c index aee2a05044f..0a726807c2b 100644 --- a/arch/x86/lib/fsp1/fsp_common.c +++ b/arch/x86/lib/fsp1/fsp_common.c @@ -4,11 +4,11 @@ */ #include -#include #include #include #include #include +#include #include #include #include diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c index 90a238a2245..c8f2c09b6a7 100644 --- a/arch/x86/lib/fsp2/fsp_dram.c +++ b/arch/x86/lib/fsp2/fsp_dram.c @@ -5,9 +5,9 @@ */ #include -#include #include #include +#include #include #include #include diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 90f224b0452..6b17f18bc07 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -33,12 +33,10 @@ #include #include #include +#include #include -#ifdef CONFIG_X86 -#include DECLARE_GLOBAL_DATA_PTR; -#endif __weak bool board_should_run_oprom(struct udevice *dev) { diff --git a/drivers/power/acpi_pmc/acpi-pmc-uclass.c b/drivers/power/acpi_pmc/acpi-pmc-uclass.c index d43de87126c..1c79f835c66 100644 --- a/drivers/power/acpi_pmc/acpi-pmc-uclass.c +++ b/drivers/power/acpi_pmc/acpi-pmc-uclass.c @@ -6,9 +6,9 @@ #define LOG_CATEGORY UCLASS_ACPI_PMC #include -#include #include #include +#include #ifdef CONFIG_X86 #include #endif diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c index 8e2d1eaa7a1..bc911435602 100644 --- a/drivers/sysreset/sysreset_x86.c +++ b/drivers/sysreset/sysreset_x86.c @@ -6,11 +6,11 @@ */ #include -#include #include #include #include #include +#include #include #include diff --git a/include/acpi/acpi_s3.h b/include/acpi/acpi_s3.h new file mode 100644 index 00000000000..baa848dcd15 --- /dev/null +++ b/include/acpi/acpi_s3.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017, Bin Meng + */ + +#ifndef __ASM_ACPI_S3_H__ +#define __ASM_ACPI_S3_H__ + +#define WAKEUP_BASE 0x600 + +/* PM1_STATUS register */ +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define RTC_STS (1 << 10) +#define SLPBTN_STS (1 << 9) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMR_STS (1 << 0) + +/* PM1_CNT register */ +#define SLP_EN (1 << 13) +#define SLP_TYP_SHIFT 10 +#define SLP_TYP (7 << SLP_TYP_SHIFT) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 + +/* Memory size reserved for S3 resume */ +#define S3_RESERVE_SIZE 0x1000 + +#ifndef __ASSEMBLY__ + +extern char __wakeup[]; +extern int __wakeup_size; + +enum acpi_sleep_state { + ACPI_S0, + ACPI_S1, + ACPI_S2, + ACPI_S3, + ACPI_S4, + ACPI_S5, +}; + +/** + * acpi_ss_string() - get ACPI-defined sleep state string + * + * @pm1_cnt: ACPI-defined sleep state + * @return: a pointer to the sleep state string. + */ +static inline char *acpi_ss_string(enum acpi_sleep_state state) +{ + char *ss_string[] = { "S0", "S1", "S2", "S3", "S4", "S5"}; + + return ss_string[state]; +} + +/** + * acpi_sleep_from_pm1() - get ACPI-defined sleep state from PM1_CNT register + * + * @pm1_cnt: PM1_CNT register value + * @return: ACPI-defined sleep state if given valid PM1_CNT register value, + * -EINVAL otherwise. + */ +static inline enum acpi_sleep_state acpi_sleep_from_pm1(u32 pm1_cnt) +{ + switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { + case SLP_TYP_S0: + return ACPI_S0; + case SLP_TYP_S1: + return ACPI_S1; + case SLP_TYP_S3: + return ACPI_S3; + case SLP_TYP_S4: + return ACPI_S4; + case SLP_TYP_S5: + return ACPI_S5; + } + + return -EINVAL; +} + +/** + * chipset_prev_sleep_state() - Get chipset previous sleep state + * + * This returns chipset previous sleep state from ACPI registers. + * Platform codes must supply this routine in order to support ACPI S3. + * + * @return ACPI_S0/S1/S2/S3/S4/S5. + */ +enum acpi_sleep_state chipset_prev_sleep_state(void); + +/** + * chipset_clear_sleep_state() - Clear chipset sleep state + * + * This clears chipset sleep state in ACPI registers. + * Platform codes must supply this routine in order to support ACPI S3. + */ +void chipset_clear_sleep_state(void); + +struct acpi_fadt; +/** + * acpi_resume() - Do ACPI S3 resume + * + * This calls U-Boot wake up assembly stub and jumps to OS's wake up vector. + * + * @fadt: FADT table pointer in the ACPI table + * @return: Never returns + */ +void acpi_resume(struct acpi_fadt *fadt); + +/** + * acpi_s3_reserve() - Reserve memory for ACPI S3 resume + * + * This copies memory where real mode interrupt handler stubs reside to the + * reserved place on the stack. + * + * This routine should be called by reserve_arch() before U-Boot is relocated + * when ACPI S3 resume is enabled. + * + * @return: 0 always + */ +int acpi_s3_reserve(void); + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ACPI_S3_H__ */ diff --git a/include/acpi_s3.h b/include/acpi_s3.h deleted file mode 100644 index baa848dcd15..00000000000 --- a/include/acpi_s3.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, Bin Meng - */ - -#ifndef __ASM_ACPI_S3_H__ -#define __ASM_ACPI_S3_H__ - -#define WAKEUP_BASE 0x600 - -/* PM1_STATUS register */ -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define RTC_STS (1 << 10) -#define SLPBTN_STS (1 << 9) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMR_STS (1 << 0) - -/* PM1_CNT register */ -#define SLP_EN (1 << 13) -#define SLP_TYP_SHIFT 10 -#define SLP_TYP (7 << SLP_TYP_SHIFT) -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 - -/* Memory size reserved for S3 resume */ -#define S3_RESERVE_SIZE 0x1000 - -#ifndef __ASSEMBLY__ - -extern char __wakeup[]; -extern int __wakeup_size; - -enum acpi_sleep_state { - ACPI_S0, - ACPI_S1, - ACPI_S2, - ACPI_S3, - ACPI_S4, - ACPI_S5, -}; - -/** - * acpi_ss_string() - get ACPI-defined sleep state string - * - * @pm1_cnt: ACPI-defined sleep state - * @return: a pointer to the sleep state string. - */ -static inline char *acpi_ss_string(enum acpi_sleep_state state) -{ - char *ss_string[] = { "S0", "S1", "S2", "S3", "S4", "S5"}; - - return ss_string[state]; -} - -/** - * acpi_sleep_from_pm1() - get ACPI-defined sleep state from PM1_CNT register - * - * @pm1_cnt: PM1_CNT register value - * @return: ACPI-defined sleep state if given valid PM1_CNT register value, - * -EINVAL otherwise. - */ -static inline enum acpi_sleep_state acpi_sleep_from_pm1(u32 pm1_cnt) -{ - switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { - case SLP_TYP_S0: - return ACPI_S0; - case SLP_TYP_S1: - return ACPI_S1; - case SLP_TYP_S3: - return ACPI_S3; - case SLP_TYP_S4: - return ACPI_S4; - case SLP_TYP_S5: - return ACPI_S5; - } - - return -EINVAL; -} - -/** - * chipset_prev_sleep_state() - Get chipset previous sleep state - * - * This returns chipset previous sleep state from ACPI registers. - * Platform codes must supply this routine in order to support ACPI S3. - * - * @return ACPI_S0/S1/S2/S3/S4/S5. - */ -enum acpi_sleep_state chipset_prev_sleep_state(void); - -/** - * chipset_clear_sleep_state() - Clear chipset sleep state - * - * This clears chipset sleep state in ACPI registers. - * Platform codes must supply this routine in order to support ACPI S3. - */ -void chipset_clear_sleep_state(void); - -struct acpi_fadt; -/** - * acpi_resume() - Do ACPI S3 resume - * - * This calls U-Boot wake up assembly stub and jumps to OS's wake up vector. - * - * @fadt: FADT table pointer in the ACPI table - * @return: Never returns - */ -void acpi_resume(struct acpi_fadt *fadt); - -/** - * acpi_s3_reserve() - Reserve memory for ACPI S3 resume - * - * This copies memory where real mode interrupt handler stubs reside to the - * reserved place on the stack. - * - * This routine should be called by reserve_arch() before U-Boot is relocated - * when ACPI S3 resume is enabled. - * - * @return: 0 always - */ -int acpi_s3_reserve(void); - -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_ACPI_S3_H__ */ -- cgit v1.3.1 From 776cc2019467567b9a834f80cc5b03128efa372a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 8 Apr 2020 16:57:36 -0600 Subject: x86: Move acpi_table header to main include/ directory This file is potentially useful to other architectures saddled with ACPI so move most of its contents to a common location. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Reviewed-by: Wolfgang Wallner --- arch/x86/cpu/baytrail/acpi.c | 2 +- arch/x86/cpu/cpu.c | 2 +- arch/x86/cpu/quark/acpi.c | 2 +- arch/x86/cpu/tangier/acpi.c | 4 +- arch/x86/include/asm/acpi_table.h | 381 +----------------------------------- arch/x86/lib/acpi.c | 2 +- arch/x86/lib/acpi_s3.c | 2 +- arch/x86/lib/acpi_table.c | 2 +- arch/x86/lib/tables.c | 2 +- arch/x86/lib/zimage.c | 2 +- include/acpi/acpi_table.h | 394 ++++++++++++++++++++++++++++++++++++++ lib/efi_loader/efi_acpi.c | 2 +- 12 files changed, 412 insertions(+), 385 deletions(-) create mode 100644 include/acpi/acpi_table.h (limited to 'arch') diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index 3c27391873c..57723109796 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 246ee50948c..cec04b481b9 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -27,8 +27,8 @@ #include #include #include +#include #include -#include #include #include #include diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c index 7b6fc2f4a53..26cda3b3376 100644 --- a/arch/x86/cpu/quark/acpi.c +++ b/arch/x86/cpu/quark/acpi.c @@ -4,7 +4,7 @@ */ #include -#include +#include #include #include #include diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c index 8b128138b0d..4ec8fdd6f89 100644 --- a/arch/x86/cpu/tangier/acpi.c +++ b/arch/x86/cpu/tangier/acpi.c @@ -8,13 +8,13 @@ #include #include #include -#include -#include +#include #include #include #include #include #include +#include void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, void *dsdt) diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 7588913f937..928475cef4e 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -9,381 +9,14 @@ #ifndef __ASM_ACPI_TABLE_H__ #define __ASM_ACPI_TABLE_H__ -#define RSDP_SIG "RSD PTR " /* RSDP pointer signature */ -#define OEM_ID "U-BOOT" /* U-Boot */ -#define OEM_TABLE_ID "U-BOOTBL" /* U-Boot Table */ -#define ASLC_ID "INTL" /* Intel ASL Compiler */ - -#define ACPI_RSDP_REV_ACPI_1_0 0 -#define ACPI_RSDP_REV_ACPI_2_0 2 - -/* - * RSDP (Root System Description Pointer) - * Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum - */ -struct acpi_rsdp { - char signature[8]; /* RSDP signature */ - u8 checksum; /* Checksum of the first 20 bytes */ - char oem_id[6]; /* OEM ID */ - u8 revision; /* 0 for ACPI 1.0, others 2 */ - u32 rsdt_address; /* Physical address of RSDT (32 bits) */ - u32 length; /* Total RSDP length (incl. extended part) */ - u64 xsdt_address; /* Physical address of XSDT (64 bits) */ - u8 ext_checksum; /* Checksum of the whole table */ - u8 reserved[3]; -}; - -/* Generic ACPI header, provided by (almost) all tables */ -struct __packed acpi_table_header { - char signature[4]; /* ACPI signature (4 ASCII characters) */ - u32 length; /* Table length in bytes (incl. header) */ - u8 revision; /* Table version (not ACPI version!) */ - volatile u8 checksum; /* To make sum of entire table == 0 */ - char oem_id[6]; /* OEM identification */ - char oem_table_id[8]; /* OEM table identification */ - u32 oem_revision; /* OEM revision number */ - char aslc_id[4]; /* ASL compiler vendor ID */ - u32 aslc_revision; /* ASL compiler revision number */ -}; - -/* A maximum number of 32 ACPI tables ought to be enough for now */ -#define MAX_ACPI_TABLES 32 - -/* RSDT (Root System Description Table) */ -struct acpi_rsdt { - struct acpi_table_header header; - u32 entry[MAX_ACPI_TABLES]; -}; - -/* XSDT (Extended System Description Table) */ -struct acpi_xsdt { - struct acpi_table_header header; - u64 entry[MAX_ACPI_TABLES]; -}; - -/* FADT Preferred Power Management Profile */ -enum acpi_pm_profile { - ACPI_PM_UNSPECIFIED = 0, - ACPI_PM_DESKTOP, - ACPI_PM_MOBILE, - ACPI_PM_WORKSTATION, - ACPI_PM_ENTERPRISE_SERVER, - ACPI_PM_SOHO_SERVER, - ACPI_PM_APPLIANCE_PC, - ACPI_PM_PERFORMANCE_SERVER, - ACPI_PM_TABLET -}; - -/* FADT flags for p_lvl2_lat and p_lvl3_lat */ -#define ACPI_FADT_C2_NOT_SUPPORTED 101 -#define ACPI_FADT_C3_NOT_SUPPORTED 1001 - -/* FADT Boot Architecture Flags */ -#define ACPI_FADT_LEGACY_FREE 0x00 -#define ACPI_FADT_LEGACY_DEVICES (1 << 0) -#define ACPI_FADT_8042 (1 << 1) -#define ACPI_FADT_VGA_NOT_PRESENT (1 << 2) -#define ACPI_FADT_MSI_NOT_SUPPORTED (1 << 3) -#define ACPI_FADT_NO_PCIE_ASPM_CONTROL (1 << 4) - -/* FADT Feature Flags */ -#define ACPI_FADT_WBINVD (1 << 0) -#define ACPI_FADT_WBINVD_FLUSH (1 << 1) -#define ACPI_FADT_C1_SUPPORTED (1 << 2) -#define ACPI_FADT_C2_MP_SUPPORTED (1 << 3) -#define ACPI_FADT_POWER_BUTTON (1 << 4) -#define ACPI_FADT_SLEEP_BUTTON (1 << 5) -#define ACPI_FADT_FIXED_RTC (1 << 6) -#define ACPI_FADT_S4_RTC_WAKE (1 << 7) -#define ACPI_FADT_32BIT_TIMER (1 << 8) -#define ACPI_FADT_DOCKING_SUPPORTED (1 << 9) -#define ACPI_FADT_RESET_REGISTER (1 << 10) -#define ACPI_FADT_SEALED_CASE (1 << 11) -#define ACPI_FADT_HEADLESS (1 << 12) -#define ACPI_FADT_SLEEP_TYPE (1 << 13) -#define ACPI_FADT_PCI_EXPRESS_WAKE (1 << 14) -#define ACPI_FADT_PLATFORM_CLOCK (1 << 15) -#define ACPI_FADT_S4_RTC_VALID (1 << 16) -#define ACPI_FADT_REMOTE_POWER_ON (1 << 17) -#define ACPI_FADT_APIC_CLUSTER (1 << 18) -#define ACPI_FADT_APIC_PHYSICAL (1 << 19) -#define ACPI_FADT_HW_REDUCED_ACPI (1 << 20) -#define ACPI_FADT_LOW_PWR_IDLE_S0 (1 << 21) - -enum acpi_address_space_type { - ACPI_ADDRESS_SPACE_MEMORY = 0, /* System memory */ - ACPI_ADDRESS_SPACE_IO, /* System I/O */ - ACPI_ADDRESS_SPACE_PCI, /* PCI config space */ - ACPI_ADDRESS_SPACE_EC, /* Embedded controller */ - ACPI_ADDRESS_SPACE_SMBUS, /* SMBus */ - ACPI_ADDRESS_SPACE_PCC = 0x0a, /* Platform Comm. Channel */ - ACPI_ADDRESS_SPACE_FIXED = 0x7f /* Functional fixed hardware */ -}; - -enum acpi_address_space_size { - ACPI_ACCESS_SIZE_UNDEFINED = 0, - ACPI_ACCESS_SIZE_BYTE_ACCESS, - ACPI_ACCESS_SIZE_WORD_ACCESS, - ACPI_ACCESS_SIZE_DWORD_ACCESS, - ACPI_ACCESS_SIZE_QWORD_ACCESS -}; - -struct acpi_gen_regaddr { - u8 space_id; /* Address space ID */ - u8 bit_width; /* Register size in bits */ - u8 bit_offset; /* Register bit offset */ - u8 access_size; /* Access size */ - u32 addrl; /* Register address, low 32 bits */ - u32 addrh; /* Register address, high 32 bits */ -}; - -/* FADT (Fixed ACPI Description Table) */ -struct __packed acpi_fadt { - struct acpi_table_header header; - u32 firmware_ctrl; - u32 dsdt; - u8 res1; - u8 preferred_pm_profile; - u16 sci_int; - u32 smi_cmd; - u8 acpi_enable; - u8 acpi_disable; - u8 s4bios_req; - u8 pstate_cnt; - u32 pm1a_evt_blk; - u32 pm1b_evt_blk; - u32 pm1a_cnt_blk; - u32 pm1b_cnt_blk; - u32 pm2_cnt_blk; - u32 pm_tmr_blk; - u32 gpe0_blk; - u32 gpe1_blk; - u8 pm1_evt_len; - u8 pm1_cnt_len; - u8 pm2_cnt_len; - u8 pm_tmr_len; - u8 gpe0_blk_len; - u8 gpe1_blk_len; - u8 gpe1_base; - u8 cst_cnt; - u16 p_lvl2_lat; - u16 p_lvl3_lat; - u16 flush_size; - u16 flush_stride; - u8 duty_offset; - u8 duty_width; - u8 day_alrm; - u8 mon_alrm; - u8 century; - u16 iapc_boot_arch; - u8 res2; - u32 flags; - struct acpi_gen_regaddr reset_reg; - u8 reset_value; - u16 arm_boot_arch; - u8 minor_revision; - u32 x_firmware_ctl_l; - u32 x_firmware_ctl_h; - u32 x_dsdt_l; - u32 x_dsdt_h; - struct acpi_gen_regaddr x_pm1a_evt_blk; - struct acpi_gen_regaddr x_pm1b_evt_blk; - struct acpi_gen_regaddr x_pm1a_cnt_blk; - struct acpi_gen_regaddr x_pm1b_cnt_blk; - struct acpi_gen_regaddr x_pm2_cnt_blk; - struct acpi_gen_regaddr x_pm_tmr_blk; - struct acpi_gen_regaddr x_gpe0_blk; - struct acpi_gen_regaddr x_gpe1_blk; -}; - -/* FACS flags */ -#define ACPI_FACS_S4BIOS_F (1 << 0) -#define ACPI_FACS_64BIT_WAKE_F (1 << 1) - -/* FACS (Firmware ACPI Control Structure) */ -struct acpi_facs { - char signature[4]; /* "FACS" */ - u32 length; /* Length in bytes (>= 64) */ - u32 hardware_signature; /* Hardware signature */ - u32 firmware_waking_vector; /* Firmware waking vector */ - u32 global_lock; /* Global lock */ - u32 flags; /* FACS flags */ - u32 x_firmware_waking_vector_l; /* X FW waking vector, low */ - u32 x_firmware_waking_vector_h; /* X FW waking vector, high */ - u8 version; /* Version 2 */ - u8 res1[3]; - u32 ospm_flags; /* OSPM enabled flags */ - u8 res2[24]; -}; - -/* MADT flags */ -#define ACPI_MADT_PCAT_COMPAT (1 << 0) - -/* MADT (Multiple APIC Description Table) */ -struct acpi_madt { - struct acpi_table_header header; - u32 lapic_addr; /* Local APIC address */ - u32 flags; /* Multiple APIC flags */ -}; - -/* MADT: APIC Structure Type*/ -enum acpi_apic_types { - ACPI_APIC_LAPIC = 0, /* Processor local APIC */ - ACPI_APIC_IOAPIC, /* I/O APIC */ - ACPI_APIC_IRQ_SRC_OVERRIDE, /* Interrupt source override */ - ACPI_APIC_NMI_SRC, /* NMI source */ - ACPI_APIC_LAPIC_NMI, /* Local APIC NMI */ - ACPI_APIC_LAPIC_ADDR_OVERRIDE, /* Local APIC address override */ - ACPI_APIC_IOSAPIC, /* I/O SAPIC */ - ACPI_APIC_LSAPIC, /* Local SAPIC */ - ACPI_APIC_PLATFORM_IRQ_SRC, /* Platform interrupt sources */ - ACPI_APIC_LX2APIC, /* Processor local x2APIC */ - ACPI_APIC_LX2APIC_NMI, /* Local x2APIC NMI */ -}; - -/* MADT: Processor Local APIC Structure */ - -#define LOCAL_APIC_FLAG_ENABLED (1 << 0) - -struct acpi_madt_lapic { - u8 type; /* Type (0) */ - u8 length; /* Length in bytes (8) */ - u8 processor_id; /* ACPI processor ID */ - u8 apic_id; /* Local APIC ID */ - u32 flags; /* Local APIC flags */ -}; - -/* MADT: I/O APIC Structure */ -struct acpi_madt_ioapic { - u8 type; /* Type (1) */ - u8 length; /* Length in bytes (12) */ - u8 ioapic_id; /* I/O APIC ID */ - u8 reserved; - u32 ioapic_addr; /* I/O APIC address */ - u32 gsi_base; /* Global system interrupt base */ -}; - -/* MADT: Interrupt Source Override Structure */ -struct __packed acpi_madt_irqoverride { - u8 type; /* Type (2) */ - u8 length; /* Length in bytes (10) */ - u8 bus; /* ISA (0) */ - u8 source; /* Bus-relative int. source (IRQ) */ - u32 gsirq; /* Global system interrupt */ - u16 flags; /* MPS INTI flags */ -}; - -/* MADT: Local APIC NMI Structure */ -struct __packed acpi_madt_lapic_nmi { - u8 type; /* Type (4) */ - u8 length; /* Length in bytes (6) */ - u8 processor_id; /* ACPI processor ID */ - u16 flags; /* MPS INTI flags */ - u8 lint; /* Local APIC LINT# */ -}; - -/* MCFG (PCI Express MMIO config space BAR description table) */ -struct acpi_mcfg { - struct acpi_table_header header; - u8 reserved[8]; -}; - -struct acpi_mcfg_mmconfig { - u32 base_address_l; - u32 base_address_h; - u16 pci_segment_group_number; - u8 start_bus_number; - u8 end_bus_number; - u8 reserved[4]; -}; - -/* PM1_CNT bit defines */ -#define PM1_CNT_SCI_EN (1 << 0) - -/* ACPI global NVS structure */ +struct acpi_facs; +struct acpi_fadt; struct acpi_global_nvs; - -/* CSRT (Core System Resource Table) */ -struct acpi_csrt { - struct acpi_table_header header; -}; - -struct acpi_csrt_group { - u32 length; - u32 vendor_id; - u32 subvendor_id; - u16 device_id; - u16 subdevice_id; - u16 revision; - u16 reserved; - u32 shared_info_length; -}; - -struct acpi_csrt_shared_info { - u16 major_version; - u16 minor_version; - u32 mmio_base_low; - u32 mmio_base_high; - u32 gsi_interrupt; - u8 interrupt_polarity; - u8 interrupt_mode; - u8 num_channels; - u8 dma_address_width; - u16 base_request_line; - u16 num_handshake_signals; - u32 max_block_size; -}; - -/* DBG2 definitions are partially used for SPCR interface_type */ - -/* Types for port_type field */ - -#define ACPI_DBG2_SERIAL_PORT 0x8000 -#define ACPI_DBG2_1394_PORT 0x8001 -#define ACPI_DBG2_USB_PORT 0x8002 -#define ACPI_DBG2_NET_PORT 0x8003 - -/* Subtypes for port_subtype field */ - -#define ACPI_DBG2_16550_COMPATIBLE 0x0000 -#define ACPI_DBG2_16550_SUBSET 0x0001 -#define ACPI_DBG2_ARM_PL011 0x0003 -#define ACPI_DBG2_ARM_SBSA_32BIT 0x000D -#define ACPI_DBG2_ARM_SBSA_GENERIC 0x000E -#define ACPI_DBG2_ARM_DCC 0x000F -#define ACPI_DBG2_BCM2835 0x0010 - -#define ACPI_DBG2_1394_STANDARD 0x0000 - -#define ACPI_DBG2_USB_XHCI 0x0000 -#define ACPI_DBG2_USB_EHCI 0x0001 - -#define ACPI_DBG2_UNKNOWN 0x00FF - -/* SPCR (Serial Port Console Redirection table) */ -struct __packed acpi_spcr { - struct acpi_table_header header; - u8 interface_type; - u8 reserved[3]; - struct acpi_gen_regaddr serial_port; - u8 interrupt_type; - u8 pc_interrupt; - u32 interrupt; /* Global system interrupt */ - u8 baud_rate; - u8 parity; - u8 stop_bits; - u8 flow_control; - u8 terminal_type; - u8 reserved1; - u16 pci_device_id; /* Must be 0xffff if not PCI device */ - u16 pci_vendor_id; /* Must be 0xffff if not PCI device */ - u8 pci_bus; - u8 pci_device; - u8 pci_function; - u32 pci_flags; - u8 pci_segment; - u32 reserved2; -}; +struct acpi_madt_ioapic; +struct acpi_madt_irqoverride; +struct acpi_madt_lapic_nmi; +struct acpi_mcfg_mmconfig; +struct acpi_table_header; /* These can be used by the target port */ diff --git a/arch/x86/lib/acpi.c b/arch/x86/lib/acpi.c index cba9c24dd45..7431458dcf2 100644 --- a/arch/x86/lib/acpi.c +++ b/arch/x86/lib/acpi.c @@ -4,7 +4,7 @@ */ #include -#include +#include #include #include diff --git a/arch/x86/lib/acpi_s3.c b/arch/x86/lib/acpi_s3.c index c3759ec8492..52410a515df 100644 --- a/arch/x86/lib/acpi_s3.c +++ b/arch/x86/lib/acpi_s3.c @@ -5,8 +5,8 @@ #include #include +#include #include -#include #include #include diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 074987e2943..9346e165d89 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -12,8 +12,8 @@ #include #include #include +#include #include -#include #include #include #include diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index 7aea722d0b8..574d331d76f 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -6,10 +6,10 @@ #include #include #include +#include #include #include #include -#include #include /** diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 9b5e767ccc2..ffc09630b7d 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h new file mode 100644 index 00000000000..b4404a632c0 --- /dev/null +++ b/include/acpi/acpi_table.h @@ -0,0 +1,394 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Helpers for ACPI table generation + * + * Based on acpi.c from coreboot + * + * Copyright 2019 Google LLC + * + * Copyright (C) 2015, Saket Sinha + * Copyright (C) 2016, Bin Meng + */ + +#ifndef __ACPI_TABLE_H__ +#define __ACPI_TABLE_H__ + +#define RSDP_SIG "RSD PTR " /* RSDP pointer signature */ +#define OEM_ID "U-BOOT" /* U-Boot */ +#define OEM_TABLE_ID "U-BOOTBL" /* U-Boot Table */ +#define ASLC_ID "INTL" /* Intel ASL Compiler */ + +#define ACPI_RSDP_REV_ACPI_1_0 0 +#define ACPI_RSDP_REV_ACPI_2_0 2 + +/* + * RSDP (Root System Description Pointer) + * Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum + */ +struct acpi_rsdp { + char signature[8]; /* RSDP signature */ + u8 checksum; /* Checksum of the first 20 bytes */ + char oem_id[6]; /* OEM ID */ + u8 revision; /* 0 for ACPI 1.0, others 2 */ + u32 rsdt_address; /* Physical address of RSDT (32 bits) */ + u32 length; /* Total RSDP length (incl. extended part) */ + u64 xsdt_address; /* Physical address of XSDT (64 bits) */ + u8 ext_checksum; /* Checksum of the whole table */ + u8 reserved[3]; +}; + +/* Generic ACPI header, provided by (almost) all tables */ +struct __packed acpi_table_header { + char signature[4]; /* ACPI signature (4 ASCII characters) */ + u32 length; /* Table length in bytes (incl. header) */ + u8 revision; /* Table version (not ACPI version!) */ + volatile u8 checksum; /* To make sum of entire table == 0 */ + char oem_id[6]; /* OEM identification */ + char oem_table_id[8]; /* OEM table identification */ + u32 oem_revision; /* OEM revision number */ + char aslc_id[4]; /* ASL compiler vendor ID */ + u32 aslc_revision; /* ASL compiler revision number */ +}; + +/* A maximum number of 32 ACPI tables ought to be enough for now */ +#define MAX_ACPI_TABLES 32 + +/* RSDT (Root System Description Table) */ +struct acpi_rsdt { + struct acpi_table_header header; + u32 entry[MAX_ACPI_TABLES]; +}; + +/* XSDT (Extended System Description Table) */ +struct acpi_xsdt { + struct acpi_table_header header; + u64 entry[MAX_ACPI_TABLES]; +}; + +/* FADT Preferred Power Management Profile */ +enum acpi_pm_profile { + ACPI_PM_UNSPECIFIED = 0, + ACPI_PM_DESKTOP, + ACPI_PM_MOBILE, + ACPI_PM_WORKSTATION, + ACPI_PM_ENTERPRISE_SERVER, + ACPI_PM_SOHO_SERVER, + ACPI_PM_APPLIANCE_PC, + ACPI_PM_PERFORMANCE_SERVER, + ACPI_PM_TABLET +}; + +/* FADT flags for p_lvl2_lat and p_lvl3_lat */ +#define ACPI_FADT_C2_NOT_SUPPORTED 101 +#define ACPI_FADT_C3_NOT_SUPPORTED 1001 + +/* FADT Boot Architecture Flags */ +#define ACPI_FADT_LEGACY_FREE 0x00 +#define ACPI_FADT_LEGACY_DEVICES BIT(0) +#define ACPI_FADT_8042 BIT(1) +#define ACPI_FADT_VGA_NOT_PRESENT BIT(2) +#define ACPI_FADT_MSI_NOT_SUPPORTED BIT(3) +#define ACPI_FADT_NO_PCIE_ASPM_CONTROL BIT(4) + +/* FADT Feature Flags */ +#define ACPI_FADT_WBINVD BIT(0) +#define ACPI_FADT_WBINVD_FLUSH BIT(1) +#define ACPI_FADT_C1_SUPPORTED BIT(2) +#define ACPI_FADT_C2_MP_SUPPORTED BIT(3) +#define ACPI_FADT_POWER_BUTTON BIT(4) +#define ACPI_FADT_SLEEP_BUTTON BIT(5) +#define ACPI_FADT_FIXED_RTC BIT(6) +#define ACPI_FADT_S4_RTC_WAKE BIT(7) +#define ACPI_FADT_32BIT_TIMER BIT(8) +#define ACPI_FADT_DOCKING_SUPPORTED BIT(9) +#define ACPI_FADT_RESET_REGISTER BIT(10) +#define ACPI_FADT_SEALED_CASE BIT(11) +#define ACPI_FADT_HEADLESS BIT(12) +#define ACPI_FADT_SLEEP_TYPE BIT(13) +#define ACPI_FADT_PCI_EXPRESS_WAKE BIT(14) +#define ACPI_FADT_PLATFORM_CLOCK BIT(15) +#define ACPI_FADT_S4_RTC_VALID BIT(16) +#define ACPI_FADT_REMOTE_POWER_ON BIT(17) +#define ACPI_FADT_APIC_CLUSTER BIT(18) +#define ACPI_FADT_APIC_PHYSICAL BIT(19) +#define ACPI_FADT_HW_REDUCED_ACPI BIT(20) +#define ACPI_FADT_LOW_PWR_IDLE_S0 BIT(21) + +enum acpi_address_space_type { + ACPI_ADDRESS_SPACE_MEMORY = 0, /* System memory */ + ACPI_ADDRESS_SPACE_IO, /* System I/O */ + ACPI_ADDRESS_SPACE_PCI, /* PCI config space */ + ACPI_ADDRESS_SPACE_EC, /* Embedded controller */ + ACPI_ADDRESS_SPACE_SMBUS, /* SMBus */ + ACPI_ADDRESS_SPACE_PCC = 0x0a, /* Platform Comm. Channel */ + ACPI_ADDRESS_SPACE_FIXED = 0x7f /* Functional fixed hardware */ +}; + +enum acpi_address_space_size { + ACPI_ACCESS_SIZE_UNDEFINED = 0, + ACPI_ACCESS_SIZE_BYTE_ACCESS, + ACPI_ACCESS_SIZE_WORD_ACCESS, + ACPI_ACCESS_SIZE_DWORD_ACCESS, + ACPI_ACCESS_SIZE_QWORD_ACCESS +}; + +struct acpi_gen_regaddr { + u8 space_id; /* Address space ID */ + u8 bit_width; /* Register size in bits */ + u8 bit_offset; /* Register bit offset */ + u8 access_size; /* Access size */ + u32 addrl; /* Register address, low 32 bits */ + u32 addrh; /* Register address, high 32 bits */ +}; + +/* FADT (Fixed ACPI Description Table) */ +struct __packed acpi_fadt { + struct acpi_table_header header; + u32 firmware_ctrl; + u32 dsdt; + u8 res1; + u8 preferred_pm_profile; + u16 sci_int; + u32 smi_cmd; + u8 acpi_enable; + u8 acpi_disable; + u8 s4bios_req; + u8 pstate_cnt; + u32 pm1a_evt_blk; + u32 pm1b_evt_blk; + u32 pm1a_cnt_blk; + u32 pm1b_cnt_blk; + u32 pm2_cnt_blk; + u32 pm_tmr_blk; + u32 gpe0_blk; + u32 gpe1_blk; + u8 pm1_evt_len; + u8 pm1_cnt_len; + u8 pm2_cnt_len; + u8 pm_tmr_len; + u8 gpe0_blk_len; + u8 gpe1_blk_len; + u8 gpe1_base; + u8 cst_cnt; + u16 p_lvl2_lat; + u16 p_lvl3_lat; + u16 flush_size; + u16 flush_stride; + u8 duty_offset; + u8 duty_width; + u8 day_alrm; + u8 mon_alrm; + u8 century; + u16 iapc_boot_arch; + u8 res2; + u32 flags; + struct acpi_gen_regaddr reset_reg; + u8 reset_value; + u16 arm_boot_arch; + u8 minor_revision; + u32 x_firmware_ctl_l; + u32 x_firmware_ctl_h; + u32 x_dsdt_l; + u32 x_dsdt_h; + struct acpi_gen_regaddr x_pm1a_evt_blk; + struct acpi_gen_regaddr x_pm1b_evt_blk; + struct acpi_gen_regaddr x_pm1a_cnt_blk; + struct acpi_gen_regaddr x_pm1b_cnt_blk; + struct acpi_gen_regaddr x_pm2_cnt_blk; + struct acpi_gen_regaddr x_pm_tmr_blk; + struct acpi_gen_regaddr x_gpe0_blk; + struct acpi_gen_regaddr x_gpe1_blk; +}; + +/* FACS flags */ +#define ACPI_FACS_S4BIOS_F BIT(0) +#define ACPI_FACS_64BIT_WAKE_F BIT(1) + +/* FACS (Firmware ACPI Control Structure) */ +struct acpi_facs { + char signature[4]; /* "FACS" */ + u32 length; /* Length in bytes (>= 64) */ + u32 hardware_signature; /* Hardware signature */ + u32 firmware_waking_vector; /* Firmware waking vector */ + u32 global_lock; /* Global lock */ + u32 flags; /* FACS flags */ + u32 x_firmware_waking_vector_l; /* X FW waking vector, low */ + u32 x_firmware_waking_vector_h; /* X FW waking vector, high */ + u8 version; /* Version 2 */ + u8 res1[3]; + u32 ospm_flags; /* OSPM enabled flags */ + u8 res2[24]; +}; + +/* MADT flags */ +#define ACPI_MADT_PCAT_COMPAT BIT(0) + +/* MADT (Multiple APIC Description Table) */ +struct acpi_madt { + struct acpi_table_header header; + u32 lapic_addr; /* Local APIC address */ + u32 flags; /* Multiple APIC flags */ +}; + +/* MADT: APIC Structure Type*/ +enum acpi_apic_types { + ACPI_APIC_LAPIC = 0, /* Processor local APIC */ + ACPI_APIC_IOAPIC, /* I/O APIC */ + ACPI_APIC_IRQ_SRC_OVERRIDE, /* Interrupt source override */ + ACPI_APIC_NMI_SRC, /* NMI source */ + ACPI_APIC_LAPIC_NMI, /* Local APIC NMI */ + ACPI_APIC_LAPIC_ADDR_OVERRIDE, /* Local APIC address override */ + ACPI_APIC_IOSAPIC, /* I/O SAPIC */ + ACPI_APIC_LSAPIC, /* Local SAPIC */ + ACPI_APIC_PLATFORM_IRQ_SRC, /* Platform interrupt sources */ + ACPI_APIC_LX2APIC, /* Processor local x2APIC */ + ACPI_APIC_LX2APIC_NMI, /* Local x2APIC NMI */ +}; + +/* MADT: Processor Local APIC Structure */ + +#define LOCAL_APIC_FLAG_ENABLED BIT(0) + +struct acpi_madt_lapic { + u8 type; /* Type (0) */ + u8 length; /* Length in bytes (8) */ + u8 processor_id; /* ACPI processor ID */ + u8 apic_id; /* Local APIC ID */ + u32 flags; /* Local APIC flags */ +}; + +/* MADT: I/O APIC Structure */ +struct acpi_madt_ioapic { + u8 type; /* Type (1) */ + u8 length; /* Length in bytes (12) */ + u8 ioapic_id; /* I/O APIC ID */ + u8 reserved; + u32 ioapic_addr; /* I/O APIC address */ + u32 gsi_base; /* Global system interrupt base */ +}; + +/* MADT: Interrupt Source Override Structure */ +struct __packed acpi_madt_irqoverride { + u8 type; /* Type (2) */ + u8 length; /* Length in bytes (10) */ + u8 bus; /* ISA (0) */ + u8 source; /* Bus-relative int. source (IRQ) */ + u32 gsirq; /* Global system interrupt */ + u16 flags; /* MPS INTI flags */ +}; + +/* MADT: Local APIC NMI Structure */ +struct __packed acpi_madt_lapic_nmi { + u8 type; /* Type (4) */ + u8 length; /* Length in bytes (6) */ + u8 processor_id; /* ACPI processor ID */ + u16 flags; /* MPS INTI flags */ + u8 lint; /* Local APIC LINT# */ +}; + +/* MCFG (PCI Express MMIO config space BAR description table) */ +struct acpi_mcfg { + struct acpi_table_header header; + u8 reserved[8]; +}; + +struct acpi_mcfg_mmconfig { + u32 base_address_l; + u32 base_address_h; + u16 pci_segment_group_number; + u8 start_bus_number; + u8 end_bus_number; + u8 reserved[4]; +}; + +/* PM1_CNT bit defines */ +#define PM1_CNT_SCI_EN BIT(0) + +/* ACPI global NVS structure */ +struct acpi_global_nvs; + +/* CSRT (Core System Resource Table) */ +struct acpi_csrt { + struct acpi_table_header header; +}; + +struct acpi_csrt_group { + u32 length; + u32 vendor_id; + u32 subvendor_id; + u16 device_id; + u16 subdevice_id; + u16 revision; + u16 reserved; + u32 shared_info_length; +}; + +struct acpi_csrt_shared_info { + u16 major_version; + u16 minor_version; + u32 mmio_base_low; + u32 mmio_base_high; + u32 gsi_interrupt; + u8 interrupt_polarity; + u8 interrupt_mode; + u8 num_channels; + u8 dma_address_width; + u16 base_request_line; + u16 num_handshake_signals; + u32 max_block_size; +}; + +/* DBG2 definitions are partially used for SPCR interface_type */ + +/* Types for port_type field */ + +#define ACPI_DBG2_SERIAL_PORT 0x8000 +#define ACPI_DBG2_1394_PORT 0x8001 +#define ACPI_DBG2_USB_PORT 0x8002 +#define ACPI_DBG2_NET_PORT 0x8003 + +/* Subtypes for port_subtype field */ + +#define ACPI_DBG2_16550_COMPATIBLE 0x0000 +#define ACPI_DBG2_16550_SUBSET 0x0001 +#define ACPI_DBG2_ARM_PL011 0x0003 +#define ACPI_DBG2_ARM_SBSA_32BIT 0x000D +#define ACPI_DBG2_ARM_SBSA_GENERIC 0x000E +#define ACPI_DBG2_ARM_DCC 0x000F +#define ACPI_DBG2_BCM2835 0x0010 + +#define ACPI_DBG2_1394_STANDARD 0x0000 + +#define ACPI_DBG2_USB_XHCI 0x0000 +#define ACPI_DBG2_USB_EHCI 0x0001 + +#define ACPI_DBG2_UNKNOWN 0x00FF + +/* SPCR (Serial Port Console Redirection table) */ +struct __packed acpi_spcr { + struct acpi_table_header header; + u8 interface_type; + u8 reserved[3]; + struct acpi_gen_regaddr serial_port; + u8 interrupt_type; + u8 pc_interrupt; + u32 interrupt; /* Global system interrupt */ + u8 baud_rate; + u8 parity; + u8 stop_bits; + u8 flow_control; + u8 terminal_type; + u8 reserved1; + u16 pci_device_id; /* Must be 0xffff if not PCI device */ + u16 pci_vendor_id; /* Must be 0xffff if not PCI device */ + u8 pci_bus; + u8 pci_device; + u8 pci_function; + u32 pci_flags; + u8 pci_segment; + u32 reserved2; +}; + +#include + +#endif /* __ACPI_TABLE_H__ */ diff --git a/lib/efi_loader/efi_acpi.c b/lib/efi_loader/efi_acpi.c index a4e5e53d15e..9ae9c25c51e 100644 --- a/lib/efi_loader/efi_acpi.c +++ b/lib/efi_loader/efi_acpi.c @@ -7,7 +7,7 @@ #include #include -#include +#include static const efi_guid_t acpi_guid = EFI_ACPI_TABLE_GUID; -- cgit v1.3.1