From e6ea13eba9977d466985c301d255d63f40a34f24 Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 14 Mar 2024 20:03:10 +0530 Subject: arm: mach-k3: Fix config check for FS_LOADER load_firmware() API calls fs-loader APIs and checks for CONFIG_FS_LOADER before calling those APIs. The if check only checks for CONFIG_FS_LOADER but not for CONFIG_SPL_FS_LOADER. When CONFIG_FS_LOADER is enabled, load_firmware() API calls fs-loader APIs but this is done at SPL stage and at this time FS_LOADER is not built yet as a result we see below build error. AR spl/boot/built-in.o LD spl/u-boot-spl arm-none-linux-gnueabihf-ld.bfd: arch/arm/mach-k3/common.o: in function `load_firmware': /home/danish/workspace/u-boot/arch/arm/mach-k3/common.c:184: undefined reference to `get_fs_loader' arm-none-linux-gnueabihf-ld.bfd: /home/danish/workspace/u-boot/arch/arm/mach-k3/common.c:185: undefined reference to `request_firmware_into_buf' make[2]: *** [/home/danish/workspace/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make[1]: *** [/home/danish/workspace/u-boot/Makefile:2055: spl/u-boot-spl] Error 2 make[1]: Leaving directory '/home/danish/uboot_images/am64x/r5' make: *** [Makefile:177: sub-make] Error 2 Fix this by modifying the if check to CONFIG_IS_ENABLED(FS_LOADER) instead of IS_ENABLED(CONFIG_FS_LOADER) as the former will check for the appropriate config option (CONFIG_SPL_FS_LOADER / CONFIG_FS_LOADER) based on the build stage. Signed-off-by: MD Danish Anwar Acked-by: Ravi Gunasekaran --- arch/arm/mach-k3/r5/common.c | 2 +- arch/arm/mach-omap2/boot-common.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c index 7309573a3fa..c02f8d33099 100644 --- a/arch/arm/mach-k3/r5/common.c +++ b/arch/arm/mach-k3/r5/common.c @@ -70,7 +70,7 @@ int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr) char *name = NULL; int size = 0; - if (!IS_ENABLED(CONFIG_FS_LOADER)) + if (!CONFIG_IS_ENABLED(FS_LOADER)) return 0; *loadaddr = 0; diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index 57917da25cf..aa0ab13d5fb 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -190,7 +190,7 @@ int load_firmware(char *name_fw, u32 *loadaddr) struct udevice *fsdev; int size = 0; - if (!IS_ENABLED(CONFIG_FS_LOADER)) + if (!CONFIG_IS_ENABLED(FS_LOADER)) return 0; if (!*loadaddr) -- cgit v1.3.1 From e0b0a5eb9c4371254cbeea962d17502e38478aac Mon Sep 17 00:00:00 2001 From: Aniket Limaye Date: Wed, 6 Mar 2024 12:07:47 +0530 Subject: arm: dts: k3-j7200: Fix support for OSPI flash - Add the missing bootph-all property in the flash subnode for ospi - Add the missing overrides for the ospi node in the r5 devicetree Signed-off-by: Aniket Limaye Reviewed-by: Udit Kumar --- arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 4 ++++ arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 5 +++++ 2 files changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index 60ca6d21abb..c9fee0ea99b 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -195,6 +195,10 @@ &ospi0 { bootph-all; + + flash@0 { + bootph-all; + }; }; &serdes_ln_ctrl { diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index 018faaa13b6..195637a8366 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -83,3 +83,8 @@ &wkup_vtm0 { bootph-pre-ram; }; + +&ospi0 { + reg = <0x0 0x47040000 0x0 0x100>, + <0x0 0x50000000 0x0 0x8000000>; +}; -- cgit v1.3.1 From ef7d7a293c91b60c342210e7f261073ab269e7d2 Mon Sep 17 00:00:00 2001 From: Aniket Limaye Date: Wed, 6 Mar 2024 12:07:48 +0530 Subject: arm: dts: k3-j7200-r5-common: fix the mcu_timer0 clock frequency Correcting the clock-frequency property of the mcu_timer0 node Fixes: df73e791ce09 ("arm: dts: j7200: dts sync with Linux 6.6-rc1") Signed-off-by: Aniket Limaye Reviewed-by: Udit Kumar --- arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index 195637a8366..c4ca09b1e03 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -52,7 +52,7 @@ }; &mcu_timer0 { - clock-frequency = <25000000>; + clock-frequency = <250000000>; bootph-pre-ram; }; -- cgit v1.3.1 From db5c91b69a1a36a6e772524e1dd7e011d7ad0066 Mon Sep 17 00:00:00 2001 From: Aniket Limaye Date: Wed, 6 Mar 2024 12:07:49 +0530 Subject: arm: dts: k3-j7200-r5-common: Add missing overrides for ringacc and udmap Corrects the ti,sci property to point to dm_tifs node for proper functioning of mcu_ringacc and mcu_udmap. Fixes: df73e791ce09 ("arm: dts: j7200: dts sync with Linux 6.6-rc1") Signed-off-by: Aniket Limaye --- arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index c4ca09b1e03..fb7e2e50239 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -88,3 +88,11 @@ reg = <0x0 0x47040000 0x0 0x100>, <0x0 0x50000000 0x0 0x8000000>; }; + +&mcu_ringacc { + ti,sci = <&dm_tifs>; +}; + +&mcu_udmap { + ti,sci = <&dm_tifs>; +}; -- cgit v1.3.1 From c6a13f3d6f074a20680765309280994288c89ad1 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Wed, 6 Mar 2024 16:54:41 +0530 Subject: arm64: gic: Add power up sequence for GIC-600 Arm's GIC-600 features a Power Register (GICR_PWRR), which needs to be programmed to enable redistributor operation. Power on the redistributor and wait until the power on state is reflected by checking the bit GICR_PWRR.RDPD == 0. While running U-Boot in EL3 without enabling this register, GICR_WAKER.ChildrenAsleep bit is not getting cleared and loops infinitely. This register(GICR_PWRR) must be programmed to mark the frame as powered on, before accessing other registers in the frame. Rest of initialization sequence remains the same. ARM GIC-600 IP complies with ARM GICv3 architecture. Enable this config if GIC-600 IP present. Signed-off-by: Venkatesh Yadav Abbarapu --- arch/arm/Kconfig | 9 +++++++++ arch/arm/include/asm/gic.h | 1 + arch/arm/lib/gic_64.S | 10 +++++++++- arch/arm/mach-versal-net/Kconfig | 3 +++ 4 files changed, 22 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0d978c06d5a..a0842e19330 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -124,6 +124,15 @@ config GIC_V3_ITS ARM GICV3 has limitation, once the LPI table is enabled, LPI configuration table can not be re-programmed, unless GICV3 reset. +config GICV3_SUPPORT_GIC600 + bool "ARM GICV3 GIC600 SUPPORT" + help + ARM GIC-600 IP complies with ARM GICv3 architecture, but among others, + implements a power control register in the Redistributor frame.This + register must be programmed to mark the frame as powered on, before + accessing other registers in the frame. Rest of initialization sequence + remains the same. + config STATIC_RELA bool default y if ARM64 diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h index bd3a80cdf70..fb64ba076d7 100644 --- a/arch/arm/include/asm/gic.h +++ b/arch/arm/include/asm/gic.h @@ -57,6 +57,7 @@ #define GICR_TYPER 0x0008 #define GICR_STATUSR 0x0010 #define GICR_WAKER 0x0014 +#define GICR_PWRR 0x0024 #define GICR_SETLPIR 0x0040 #define GICR_CLRLPIR 0x0048 #define GICR_SEIR 0x0068 diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S index 86cd882fc75..7fa48648d9d 100644 --- a/arch/arm/lib/gic_64.S +++ b/arch/arm/lib/gic_64.S @@ -92,8 +92,16 @@ ENTRY(gic_init_secure_percpu) add x9, x9, #(2 << 16) b 1b +2: +#if defined(CONFIG_GICV3_SUPPORT_GIC600) + mov w10, #0x0 /* Power on redistributor */ + str w10, [x9, GICR_PWRR] +5: ldr w10, [x9, GICR_PWRR] /* Wait until the power on state is reflected */ + tbnz w10, #1, 5b /* If RDPD == 0 then powered on */ +#endif + /* x9: ReDistributor Base Address of Current CPU */ -2: mov w10, #~0x2 + mov w10, #~0x2 ldr w11, [x9, GICR_WAKER] and w11, w11, w10 /* Clear ProcessorSleep */ str w11, [x9, GICR_WAKER] diff --git a/arch/arm/mach-versal-net/Kconfig b/arch/arm/mach-versal-net/Kconfig index 1b5339993f8..54fb93aeb53 100644 --- a/arch/arm/mach-versal-net/Kconfig +++ b/arch/arm/mach-versal-net/Kconfig @@ -35,6 +35,9 @@ config SYS_MEM_RSVD_FOR_MMU config GICV3 def_bool y +config GICV3_SUPPORT_GIC600 + def_bool y + config SYS_MALLOC_LEN default 0x2000000 -- cgit v1.3.1 From 95167db37c4b669ae47be885cd1cc1832e754fff Mon Sep 17 00:00:00 2001 From: Lukasz Wiecaszek Date: Sun, 10 Mar 2024 11:29:58 +0100 Subject: arm: Check FEAT_CCIDX when parsing ccsidr_el1 register Current Cache Size ID Register (ccsidr_el1) has two "flavors" depending on whether FEAT_CCIDX is implemented or not. When FEAT_CCIDX is implemented Associativity parameter is coded on bits [23:3] and NumSets parameter on bits [55:32]. When FEAT_CCIDX is not implemented then Associativity parameter is coded on bits [12:3] and NumSets parameter on bits [27:13]. Current U-Boot code does not check whether FEAT_CCIDX is implemented and always parses ccsidr_el1 as if FEAT_CCIDX was not implemented. This is of course wrong on systems where FEAT_CCIDX is implemented. This patch fixes that problems and tests whether FEAT_CCIDX is implemented or not and accordingly parses the ccsidr_el1 register. Signed-off-by: Lukasz Wiecaszek --- arch/arm/cpu/armv8/cache.S | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index 3fe935cf283..c9e46859b4f 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -20,6 +20,7 @@ * * x0: cache level * x1: 0 clean & invalidate, 1 invalidate only + * x16: FEAT_CCIDX * x2~x9: clobbered */ .pushsection .text.__asm_dcache_level, "ax" @@ -29,8 +30,14 @@ ENTRY(__asm_dcache_level) isb /* sync change of cssidr_el1 */ mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ ubfx x2, x6, #0, #3 /* x2 <- log2(cache line size)-4 */ + cbz x16, 3f /* check for FEAT_CCIDX */ + ubfx x3, x6, #3, #21 /* x3 <- number of cache ways - 1 */ + ubfx x4, x6, #32, #24 /* x4 <- number of cache sets - 1 */ + b 4f +3: ubfx x3, x6, #3, #10 /* x3 <- number of cache ways - 1 */ ubfx x4, x6, #13, #15 /* x4 <- number of cache sets - 1 */ +4: add x2, x2, #4 /* x2 <- log2(cache line size) */ clz w5, w3 /* bit position of #ways */ /* x12 <- cache level << 1 */ @@ -74,6 +81,8 @@ ENTRY(__asm_dcache_all) ubfx x11, x10, #24, #3 /* x11 <- loc */ cbz x11, finished /* if loc is 0, exit */ mov x15, lr + mrs x16, s3_0_c0_c7_2 /* read value of id_aa64mmfr2_el1*/ + ubfx x16, x16, #20, #4 /* save FEAT_CCIDX identifier in x16 */ mov x0, #0 /* start flush at cache level 0 */ /* x0 <- cache level */ /* x10 <- clidr_el1 */ -- cgit v1.3.1