From a37b68820c432ff9b0b3dab597d94f7bbfa5d1e2 Mon Sep 17 00:00:00 2001 From: Rogier Stam Date: Wed, 9 Feb 2022 00:27:00 +0100 Subject: arm: mvebu: Fix Espressobin build for configs where ENV is not in SPI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When storing the UBoot Environment in for example EXT4, the U-Boot build is broken for several reasons: 1. armada-385-turris-omnia-u-boot.dtsi will not allow CONFIG_ENV_OFFSET and CONFIG_ENV_SIZE to be undefined 2. armada-37xx/board.c ft_board_setup function does not exist if CONFIG_ENV_IS_IN_SPI_FLASH is not defined This commit changes these files so that selecting a different location for the environment is possible. Signed-off-by: Rogier Stam Reviewed-by: Pali Rohár --- arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi index 3ff76c94629..008787e664c 100644 --- a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi +++ b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi @@ -38,6 +38,7 @@ }; }; +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH &spi0 { u-boot,dm-pre-reloc; @@ -56,6 +57,7 @@ }; }; }; +#endif &uart0 { u-boot,dm-pre-reloc; -- cgit v1.3.1 From 10154b81def9b66e7ad45d6e295e5ea640d79f1e Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Wed, 23 Feb 2022 14:15:45 +0100 Subject: arm: mvebu: a37xx: Add support for reading NB and SB fuse OTP value MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement reading NB and SB fuses of Armada 37xx SOC via U-Boot fuse API. Banks 0-43 are reserved for accessing Security OTP (not implemented yet). Bank 44 is used for accessing North Bridge OTP (69 bits via words 0-2). Bank 45 is used for accessing South Bridge OTP (97 bits via words 0-3). Write support is not implemented yet because it looks like that both North and South Bridge OTPs are already burned in factory with some data. The meaning of some bits of North Bridge is documented in WTMI source code. The meaning of bits in South Bridge is unknown. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/Kconfig | 1 + arch/arm/mach-mvebu/Makefile | 3 + arch/arm/mach-mvebu/armada3700/Makefile | 1 + arch/arm/mach-mvebu/armada3700/efuse.c | 136 ++++++++++++++++++++++++++++++++ 4 files changed, 141 insertions(+) create mode 100644 arch/arm/mach-mvebu/armada3700/efuse.c (limited to 'arch') diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 21d9db2638d..ccdb624ba7d 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -44,6 +44,7 @@ config ARMADA_XP config ARMADA_3700 bool select ARM64 + select HAVE_MVEBU_EFUSE # Armada 7K and 8K are very similar - use only one Kconfig symbol for both config ARMADA_8K diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index a5a20877dda..1b451889d24 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -27,7 +27,10 @@ obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o obj-$(CONFIG_ARMADA_MSYS) += ../../../drivers/ddr/marvell/axp/xor.o + +ifdef CONFIG_ARMADA_38X obj-$(CONFIG_MVEBU_EFUSE) += efuse.o +endif extra-y += kwbimage.cfg diff --git a/arch/arm/mach-mvebu/armada3700/Makefile b/arch/arm/mach-mvebu/armada3700/Makefile index 031b3e854e3..cd74726cc77 100644 --- a/arch/arm/mach-mvebu/armada3700/Makefile +++ b/arch/arm/mach-mvebu/armada3700/Makefile @@ -3,3 +3,4 @@ # Copyright (C) 2016 Stefan Roese obj-y = cpu.o +obj-$(CONFIG_MVEBU_EFUSE) += efuse.o diff --git a/arch/arm/mach-mvebu/armada3700/efuse.c b/arch/arm/mach-mvebu/armada3700/efuse.c new file mode 100644 index 00000000000..03778f17ea4 --- /dev/null +++ b/arch/arm/mach-mvebu/armada3700/efuse.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) 2017 Marvell International Ltd. + * (C) 2021 Pali Rohár + */ + +#include +#include +#include +#include +#include + +#define OTP_NB_REG_BASE ((void __iomem *)MVEBU_REGISTER(0x12600)) +#define OTP_SB_REG_BASE ((void __iomem *)MVEBU_REGISTER(0x1A200)) + +#define OTP_CONTROL_OFF 0x00 +#define OTP_MODE_BIT BIT(15) +#define OTP_RPTR_RST_BIT BIT(14) +#define OTP_POR_B_BIT BIT(13) +#define OTP_PRDT_BIT BIT(3) +#define OTP_READ_PORT_OFF 0x04 +#define OTP_READ_POINTER_OFF 0x08 +#define OTP_PTR_INC_BIT BIT(8) + +static void otp_read_parallel(void __iomem *base, u32 *data, u32 count) +{ + u32 regval; + + /* 1. Clear OTP_MODE_NB to parallel mode */ + regval = readl(base + OTP_CONTROL_OFF); + regval &= ~OTP_MODE_BIT; + writel(regval, base + OTP_CONTROL_OFF); + + /* 2. Set OTP_POR_B_NB enter normal operation */ + regval = readl(base + OTP_CONTROL_OFF); + regval |= OTP_POR_B_BIT; + writel(regval, base + OTP_CONTROL_OFF); + + /* 3. Set OTP_PTR_INC_NB to auto-increment pointer after each read */ + regval = readl(base + OTP_READ_POINTER_OFF); + regval |= OTP_PTR_INC_BIT; + writel(regval, base + OTP_READ_POINTER_OFF); + + /* 4. Set OTP_RPTR_RST_NB, then clear the same field */ + regval = readl(base + OTP_CONTROL_OFF); + regval |= OTP_RPTR_RST_BIT; + writel(regval, base + OTP_CONTROL_OFF); + + regval = readl(base + OTP_CONTROL_OFF); + regval &= ~OTP_RPTR_RST_BIT; + writel(regval, base + OTP_CONTROL_OFF); + + /* 5. Toggle OTP_PRDT_NB + * a. Set OTP_PRDT_NB to 1. + * b. Clear OTP_PRDT_NB to 0. + * c. Wait for a minimum of 100 ns. + * d. Set OTP_PRDT_NB to 1 + */ + regval = readl(base + OTP_CONTROL_OFF); + regval |= OTP_PRDT_BIT; + writel(regval, base + OTP_CONTROL_OFF); + + regval = readl(base + OTP_CONTROL_OFF); + regval &= ~OTP_PRDT_BIT; + writel(regval, base + OTP_CONTROL_OFF); + + ndelay(100); + + regval = readl(base + OTP_CONTROL_OFF); + regval |= OTP_PRDT_BIT; + writel(regval, base + OTP_CONTROL_OFF); + + while (count-- > 0) { + /* 6. Read the content of OTP 32-bits at a time */ + ndelay(100000); + *(data++) = readl(base + OTP_READ_PORT_OFF); + } +} + +/* + * Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits via 44 banks and words 0-2) + * Bank 44 is used for accessing North Bridge OTP (69 bits via words 0-2) + * Bank 45 is used for accessing South Bridge OTP (97 bits via words 0-3) + */ + +#define RWTM_ROWS 44 +#define RWTM_MAX_BANK (RWTM_ROWS - 1) +#define RWTM_ROW_WORDS 3 +#define OTP_NB_BANK RWTM_ROWS +#define OTP_NB_WORDS 3 +#define OTP_SB_BANK (RWTM_ROWS + 1) +#define OTP_SB_WORDS 4 + +int fuse_read(u32 bank, u32 word, u32 *val) +{ + if (bank <= RWTM_MAX_BANK) { + if (word >= RWTM_ROW_WORDS) + return -EINVAL; + /* TODO: not implemented yet */ + return -ENOSYS; + } else if (bank == OTP_NB_BANK) { + u32 data[OTP_NB_WORDS]; + if (word >= OTP_NB_WORDS) + return -EINVAL; + otp_read_parallel(OTP_NB_REG_BASE, data, OTP_NB_WORDS); + *val = data[word]; + return 0; + } else if (bank == OTP_SB_BANK) { + u32 data[OTP_SB_WORDS]; + if (word >= OTP_SB_WORDS) + return -EINVAL; + otp_read_parallel(OTP_SB_REG_BASE, data, OTP_SB_WORDS); + *val = data[word]; + return 0; + } else { + return -EINVAL; + } +} + +int fuse_prog(u32 bank, u32 word, u32 val) +{ + /* TODO: not implemented yet */ + return -ENOSYS; +} + +int fuse_sense(u32 bank, u32 word, u32 *val) +{ + /* not supported */ + return -ENOSYS; +} + +int fuse_override(u32 bank, u32 word, u32 val) +{ + /* not supported */ + return -ENOSYS; +} -- cgit v1.3.1 From 46ce9c78a99814639763d8ea9ac1bf7354b6ea8d Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Wed, 23 Feb 2022 14:15:47 +0100 Subject: arm: mvebu: a37xx: Move generic mbox code to arch/arm/mach-mvebu MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Generic A3720 mbox code is currently in Turris Mox specific board file board/CZ.NIC/turris_mox/mox_sp.c. Move it to board independent arch file arch/arm/mach-mvebu/armada3700/mbox.c. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/armada3700/Makefile | 2 +- arch/arm/mach-mvebu/armada3700/mbox.c | 67 ++++++++++++++++++++++++++++++++ arch/arm/mach-mvebu/include/mach/mbox.h | 23 +++++++++++ board/CZ.NIC/turris_mox/mox_sp.c | 69 +-------------------------------- 4 files changed, 92 insertions(+), 69 deletions(-) create mode 100644 arch/arm/mach-mvebu/armada3700/mbox.c create mode 100644 arch/arm/mach-mvebu/include/mach/mbox.h (limited to 'arch') diff --git a/arch/arm/mach-mvebu/armada3700/Makefile b/arch/arm/mach-mvebu/armada3700/Makefile index cd74726cc77..98350a41e04 100644 --- a/arch/arm/mach-mvebu/armada3700/Makefile +++ b/arch/arm/mach-mvebu/armada3700/Makefile @@ -2,5 +2,5 @@ # # Copyright (C) 2016 Stefan Roese -obj-y = cpu.o +obj-y = cpu.o mbox.o obj-$(CONFIG_MVEBU_EFUSE) += efuse.o diff --git a/arch/arm/mach-mvebu/armada3700/mbox.c b/arch/arm/mach-mvebu/armada3700/mbox.c new file mode 100644 index 00000000000..cb86b967c2e --- /dev/null +++ b/arch/arm/mach-mvebu/armada3700/mbox.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Marek Behun + */ + +#include +#include +#include +#include +#include +#include + +#define RWTM_BASE (MVEBU_REGISTER(0xb0000)) +#define RWTM_CMD_PARAM(i) (size_t)(RWTM_BASE + (i) * 4) +#define RWTM_CMD (RWTM_BASE + 0x40) +#define RWTM_CMD_RETSTATUS (RWTM_BASE + 0x80) +#define RWTM_CMD_STATUS(i) (size_t)(RWTM_BASE + 0x84 + (i) * 4) + +#define RWTM_HOST_INT_RESET (RWTM_BASE + 0xc8) +#define RWTM_HOST_INT_MASK (RWTM_BASE + 0xcc) +#define SP_CMD_COMPLETE BIT(0) + +#define MBOX_STS_SUCCESS (0x0 << 30) +#define MBOX_STS_FAIL (0x1 << 30) +#define MBOX_STS_BADCMD (0x2 << 30) +#define MBOX_STS_LATER (0x3 << 30) +#define MBOX_STS_ERROR(s) ((s) & (3 << 30)) +#define MBOX_STS_VALUE(s) (((s) >> 10) & 0xfffff) +#define MBOX_STS_CMD(s) ((s) & 0x3ff) + +int mbox_do_cmd(enum mbox_cmd cmd, u32 *out, int nout) +{ + const int tries = 50; + int i; + u32 status; + + clrbits_le32(RWTM_HOST_INT_MASK, SP_CMD_COMPLETE); + + writel(cmd, RWTM_CMD); + + for (i = 0; i < tries; ++i) { + mdelay(10); + if (readl(RWTM_HOST_INT_RESET) & SP_CMD_COMPLETE) + break; + } + + if (i == tries) { + /* if timed out, don't read status */ + setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE); + return -ETIMEDOUT; + } + + for (i = 0; i < nout; ++i) + out[i] = readl(RWTM_CMD_STATUS(i)); + status = readl(RWTM_CMD_RETSTATUS); + + setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE); + + if (MBOX_STS_CMD(status) != cmd) + return -EIO; + else if (MBOX_STS_ERROR(status) == MBOX_STS_FAIL) + return -(int)MBOX_STS_VALUE(status); + else if (MBOX_STS_ERROR(status) != MBOX_STS_SUCCESS) + return -EIO; + else + return MBOX_STS_VALUE(status); +} diff --git a/arch/arm/mach-mvebu/include/mach/mbox.h b/arch/arm/mach-mvebu/include/mach/mbox.h new file mode 100644 index 00000000000..98120493583 --- /dev/null +++ b/arch/arm/mach-mvebu/include/mach/mbox.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Marek Behun + */ + +#ifndef _MVEBU_MBOX_H +#define _MVEBU_MBOX_H + +enum mbox_cmd { + MBOX_CMD_GET_RANDOM = 1, + MBOX_CMD_BOARD_INFO, + MBOX_CMD_ECDSA_PUB_KEY, + MBOX_CMD_HASH, + MBOX_CMD_SIGN, + MBOX_CMD_VERIFY, + + MBOX_CMD_OTP_READ, + MBOX_CMD_OTP_WRITE, +}; + +int mbox_do_cmd(enum mbox_cmd cmd, u32 *in, int nout); + +#endif diff --git a/board/CZ.NIC/turris_mox/mox_sp.c b/board/CZ.NIC/turris_mox/mox_sp.c index cc57b9f095f..4de067bbebb 100644 --- a/board/CZ.NIC/turris_mox/mox_sp.c +++ b/board/CZ.NIC/turris_mox/mox_sp.c @@ -8,74 +8,7 @@ #include #include #include - -#define RWTM_BASE (MVEBU_REGISTER(0xb0000)) -#define RWTM_CMD_PARAM(i) (size_t)(RWTM_BASE + (i) * 4) -#define RWTM_CMD (RWTM_BASE + 0x40) -#define RWTM_CMD_RETSTATUS (RWTM_BASE + 0x80) -#define RWTM_CMD_STATUS(i) (size_t)(RWTM_BASE + 0x84 + (i) * 4) - -#define RWTM_HOST_INT_RESET (RWTM_BASE + 0xc8) -#define RWTM_HOST_INT_MASK (RWTM_BASE + 0xcc) -#define SP_CMD_COMPLETE BIT(0) - -#define MBOX_STS_SUCCESS (0x0 << 30) -#define MBOX_STS_FAIL (0x1 << 30) -#define MBOX_STS_BADCMD (0x2 << 30) -#define MBOX_STS_LATER (0x3 << 30) -#define MBOX_STS_ERROR(s) ((s) & (3 << 30)) -#define MBOX_STS_VALUE(s) (((s) >> 10) & 0xfffff) -#define MBOX_STS_CMD(s) ((s) & 0x3ff) - -enum mbox_cmd { - MBOX_CMD_GET_RANDOM = 1, - MBOX_CMD_BOARD_INFO, - MBOX_CMD_ECDSA_PUB_KEY, - MBOX_CMD_HASH, - MBOX_CMD_SIGN, - MBOX_CMD_VERIFY, - - MBOX_CMD_OTP_READ, - MBOX_CMD_OTP_WRITE -}; - -static int mbox_do_cmd(enum mbox_cmd cmd, u32 *out, int nout) -{ - const int tries = 50; - int i; - u32 status; - - clrbits_le32(RWTM_HOST_INT_MASK, SP_CMD_COMPLETE); - - writel(cmd, RWTM_CMD); - - for (i = 0; i < tries; ++i) { - mdelay(10); - if (readl(RWTM_HOST_INT_RESET) & SP_CMD_COMPLETE) - break; - } - - if (i == tries) { - /* if timed out, don't read status */ - setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE); - return -ETIMEDOUT; - } - - for (i = 0; i < nout; ++i) - out[i] = readl(RWTM_CMD_STATUS(i)); - status = readl(RWTM_CMD_RETSTATUS); - - setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE); - - if (MBOX_STS_CMD(status) != cmd) - return -EIO; - else if (MBOX_STS_ERROR(status) == MBOX_STS_FAIL) - return -(int)MBOX_STS_VALUE(status); - else if (MBOX_STS_ERROR(status) != MBOX_STS_SUCCESS) - return -EIO; - else - return MBOX_STS_VALUE(status); -} +#include const char *mox_sp_get_ecdsa_public_key(void) { -- cgit v1.3.1 From 85df8f9a211610d4406e644061220b5e2fd221c7 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Wed, 23 Feb 2022 14:15:48 +0100 Subject: arm: mvebu: a37xx: Extend mbox_do_cmd() code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allow to specify input parameters, define all available mbox commands supported by CZ.NIC's secure firmware and also Marvell's fuse.bin firmware and fix parsing response from Marvell OTP commands. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/armada3700/mbox.c | 20 ++++++++++++++++++-- arch/arm/mach-mvebu/include/mach/mbox.h | 19 ++++++++++++++++++- board/CZ.NIC/turris_mox/mox_sp.c | 4 ++-- 3 files changed, 38 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/armada3700/mbox.c b/arch/arm/mach-mvebu/armada3700/mbox.c index cb86b967c2e..eb1f82845f0 100644 --- a/arch/arm/mach-mvebu/armada3700/mbox.c +++ b/arch/arm/mach-mvebu/armada3700/mbox.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2018 Marek Behun + * Copyright (C) 2021 Pali Rohár */ #include @@ -15,6 +16,7 @@ #define RWTM_CMD (RWTM_BASE + 0x40) #define RWTM_CMD_RETSTATUS (RWTM_BASE + 0x80) #define RWTM_CMD_STATUS(i) (size_t)(RWTM_BASE + 0x84 + (i) * 4) +#define MAX_ARGS 16 #define RWTM_HOST_INT_RESET (RWTM_BASE + 0xc8) #define RWTM_HOST_INT_MASK (RWTM_BASE + 0xcc) @@ -27,15 +29,27 @@ #define MBOX_STS_ERROR(s) ((s) & (3 << 30)) #define MBOX_STS_VALUE(s) (((s) >> 10) & 0xfffff) #define MBOX_STS_CMD(s) ((s) & 0x3ff) +#define MBOX_STS_MARVELL_ERROR(s) ((s) == 0 ? 0 : \ + (s) == 2 ? ETIMEDOUT : \ + (s) == 3 ? EINVAL : \ + (s) == 4 ? ENOSYS : \ + EIO) -int mbox_do_cmd(enum mbox_cmd cmd, u32 *out, int nout) +int mbox_do_cmd(enum mbox_cmd cmd, u32 *in, int nin, u32 *out, int nout) { const int tries = 50; int i; u32 status; + if (nin > MAX_ARGS || nout > MAX_ARGS) + return -EINVAL; + clrbits_le32(RWTM_HOST_INT_MASK, SP_CMD_COMPLETE); + for (i = 0; i < nin; i++) + writel(in[i], RWTM_CMD_PARAM(i)); + for (; i < MAX_ARGS; i++) + writel(0x0, RWTM_CMD_PARAM(i)); writel(cmd, RWTM_CMD); for (i = 0; i < tries; ++i) { @@ -57,9 +71,11 @@ int mbox_do_cmd(enum mbox_cmd cmd, u32 *out, int nout) setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE); if (MBOX_STS_CMD(status) != cmd) - return -EIO; + return -MBOX_STS_MARVELL_ERROR(status); else if (MBOX_STS_ERROR(status) == MBOX_STS_FAIL) return -(int)MBOX_STS_VALUE(status); + else if (MBOX_STS_ERROR(status) == MBOX_STS_BADCMD) + return -ENOSYS; else if (MBOX_STS_ERROR(status) != MBOX_STS_SUCCESS) return -EIO; else diff --git a/arch/arm/mach-mvebu/include/mach/mbox.h b/arch/arm/mach-mvebu/include/mach/mbox.h index 98120493583..f1cb55f2bfe 100644 --- a/arch/arm/mach-mvebu/include/mach/mbox.h +++ b/arch/arm/mach-mvebu/include/mach/mbox.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2018 Marek Behun + * Copyright (C) 2021 Pali Rohár */ #ifndef _MVEBU_MBOX_H @@ -16,8 +17,24 @@ enum mbox_cmd { MBOX_CMD_OTP_READ, MBOX_CMD_OTP_WRITE, + + MBOX_CMD_REBOOT, + + /* OTP read commands supported by Marvell fuse.bin firmware */ + MBOX_CMD_OTP_READ_1B = 257, + MBOX_CMD_OTP_READ_8B, + MBOX_CMD_OTP_READ_32B, + MBOX_CMD_OTP_READ_64B, + MBOX_CMD_OTP_READ_256B, + + /* OTP write commands supported by Marvell fuse.bin firmware */ + MBOX_CMD_OTP_WRITE_1B = 513, + MBOX_CMD_OTP_WRITE_8B, + MBOX_CMD_OTP_WRITE_32B, + MBOX_CMD_OTP_WRITE_64B, + MBOX_CMD_OTP_WRITE_256B, }; -int mbox_do_cmd(enum mbox_cmd cmd, u32 *in, int nout); +int mbox_do_cmd(enum mbox_cmd cmd, u32 *in, int nin, u32 *out, int nout); #endif diff --git a/board/CZ.NIC/turris_mox/mox_sp.c b/board/CZ.NIC/turris_mox/mox_sp.c index 4de067bbebb..93e96b014fc 100644 --- a/board/CZ.NIC/turris_mox/mox_sp.c +++ b/board/CZ.NIC/turris_mox/mox_sp.c @@ -19,7 +19,7 @@ const char *mox_sp_get_ecdsa_public_key(void) if (public_key[0]) return public_key; - res = mbox_do_cmd(MBOX_CMD_ECDSA_PUB_KEY, out, 16); + res = mbox_do_cmd(MBOX_CMD_ECDSA_PUB_KEY, NULL, 0, out, 16); if (res < 0) return NULL; @@ -47,7 +47,7 @@ int mbox_sp_get_board_info(u64 *sn, u8 *mac1, u8 *mac2, int *bv, int *ram) u32 out[8]; int res; - res = mbox_do_cmd(MBOX_CMD_BOARD_INFO, out, 8); + res = mbox_do_cmd(MBOX_CMD_BOARD_INFO, NULL, 0, out, 8); if (res < 0) return res; -- cgit v1.3.1 From c8b00da69504dae6b768c1fd46fbe63641f99dd1 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Wed, 23 Feb 2022 14:15:49 +0100 Subject: arm: mvebu: a37xx: Add support for reading Security OTP values MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is not possible for the A53 core (on which U-Boot is running) to read it directly. For this purpose Marvell defined mbox API for sending OTP commands between CM3 and A53 cores. Implement these Marvell fuse reading mbox commands via U-Boot fuse API. Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits via 44 banks and words 0-2). Note that of the 67 bits, the 3 upper bits are: 1 lock bit and 2 auxiliary bits (meant for testing during the manufacture of the SOC, as I understand it). Also note that the lock bit and the auxiliary bits are not readable via Marvell commands. With CZ.NIC's commands the lock bit is readable. Write support is not implemented yet. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/armada3700/efuse.c | 39 ++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/armada3700/efuse.c b/arch/arm/mach-mvebu/armada3700/efuse.c index 03778f17ea4..50c73f36c56 100644 --- a/arch/arm/mach-mvebu/armada3700/efuse.c +++ b/arch/arm/mach-mvebu/armada3700/efuse.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #define OTP_NB_REG_BASE ((void __iomem *)MVEBU_REGISTER(0x12600)) @@ -77,6 +78,41 @@ static void otp_read_parallel(void __iomem *base, u32 *data, u32 count) } } +static int rwtm_otp_read(u8 row, u32 word, u32 *data) +{ + u32 out[3]; + u32 in[2]; + int res = -EINVAL; + + if (word < 2) { + /* + * MBOX_CMD_OTP_READ_32B command is supported by Marvell + * fuse.bin firmware and also by new CZ.NIC wtmi firmware. + * This command returns raw bits without ECC corrections. + * It does not provide access to the lock bit. + */ + in[0] = row; + in[1] = word * 32; + res = mbox_do_cmd(MBOX_CMD_OTP_READ_32B, in, 2, out, 1); + if (!res) + *data = out[0]; + } else if (word == 2) { + /* + * MBOX_CMD_OTP_READ command is supported only by new CZ.NIC + * wtmi firmware and provides access to all bits, including + * lock bit without doing ECC corrections. For compatibility + * with Marvell fuse.bin firmware, use this command only for + * accessing lock bit. + */ + in[0] = row; + res = mbox_do_cmd(MBOX_CMD_OTP_READ, in, 1, out, 3); + if (!res) + *data = out[2]; + } + + return res; +} + /* * Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits via 44 banks and words 0-2) * Bank 44 is used for accessing North Bridge OTP (69 bits via words 0-2) @@ -96,8 +132,7 @@ int fuse_read(u32 bank, u32 word, u32 *val) if (bank <= RWTM_MAX_BANK) { if (word >= RWTM_ROW_WORDS) return -EINVAL; - /* TODO: not implemented yet */ - return -ENOSYS; + return rwtm_otp_read(bank, word, val); } else if (bank == OTP_NB_BANK) { u32 data[OTP_NB_WORDS]; if (word >= OTP_NB_WORDS) -- cgit v1.3.1 From 9b02de852578ffdfb363c657da08ba26e96582ac Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 24 Mar 2022 10:57:36 +0100 Subject: arm: mvebu: dts: uDPU: update DTS Update the uDPU DTS to the version that is pending upstream [1][2]. [1] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20220322105857.1107016-1-robert.marko@sartura.hr/ [2] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20220322105857.1107016-2-robert.marko@sartura.hr/ Signed-off-by: Robert Marko Reviewed-by: Stefan Roese --- arch/arm/dts/armada-3720-uDPU.dts | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/armada-3720-uDPU.dts b/arch/arm/dts/armada-3720-uDPU.dts index 95d46e8d081..1f534c0c65f 100644 --- a/arch/arm/dts/armada-3720-uDPU.dts +++ b/arch/arm/dts/armada-3720-uDPU.dts @@ -99,7 +99,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_quad_pins>; - m25p80@0 { + spi-flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <54000000>; @@ -108,10 +108,15 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - /* only bootloader is located on the SPI */ + partition@0 { - label = "uboot"; - reg = <0 0x400000>; + label = "firmware"; + reg = <0x0 0x180000>; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x10000>; }; }; }; @@ -148,15 +153,15 @@ scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - lm75@48 { + nct375@48 { status = "okay"; - compatible = "lm75"; + compatible = "ti,tmp75c"; reg = <0x48>; }; - lm75@49 { + nct375@49 { status = "okay"; - compatible = "lm75"; + compatible = "ti,tmp75c"; reg = <0x49>; }; }; -- cgit v1.3.1 From 9e778c7ffc3184bd538f2ff73d395df608d907e5 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 24 Mar 2022 10:57:38 +0100 Subject: arm: mvebu: dts: uDPU: fix non-working networking uDPU is a bit of a specific device in that it does not have any copper ports nor any ethernet PHY-s but 2 SFP ports. This is an issue since MVNETA requires a PHY phandle or a fixed-link to be defined under its node. Since U-boot has no SFP support this is reasonable in order to know how to configure the MAC. However this also means that networking does not work on uDPU at all currently, and fails with: uDPU>> dhcp Could not get PHY for neta@30000: addr 0 phy_connect failed Could not get PHY for neta@40000: addr 1 phy_connect failed So, to provide working networking using only SFP-s let add the fixed-link at 1G which is much more common than 2.5G SFP-s as well as disable the TX_DISABLE pins like done on Armada 7040 and 8040 platforms. Since uDPU is not using any of the GPIO-s on the SB controller for any purpose other than GPIO, a call to the pinctrl must be made in order for it to get probed and thus register the SB GPIO bank, otherwise SB GPIO-s are not registered at all. Signed-off-by: Robert Marko Reviewed-by: Stefan Roese --- arch/arm/dts/armada-3720-uDPU-u-boot.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/armada-3720-uDPU-u-boot.dtsi b/arch/arm/dts/armada-3720-uDPU-u-boot.dtsi index cf8ae4412b9..47d87d4bd8f 100644 --- a/arch/arm/dts/armada-3720-uDPU-u-boot.dtsi +++ b/arch/arm/dts/armada-3720-uDPU-u-boot.dtsi @@ -31,3 +31,27 @@ &sdhci0 { u-boot,dm-pre-reloc; }; + +&pinctrl_sb { + sfp_pin: sfp-pin { + groups = "pcie1_clkreq"; + function = "gpio"; + }; +}; + +ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&sfp_pin>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +ð1 { + fixed-link { + speed = <1000>; + full-duplex; + }; +}; -- cgit v1.3.1 From 8b3d7ecdfec30d63684d86bd76632929b72d8a84 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Wed, 6 Apr 2022 14:18:18 +0200 Subject: arm: mvebu: Add support for reading LD0 and LD1 eFuse MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Armada 385 contains 64 lines of HD eFuse and 2 lines of LD eFuse. HD eFuse is used for secure boot and each line is 64 bits long + 1 lock bit. LD eFuse lines are 256 bits long + 1 lock bit. LD 0 line is reserved for Marvell Internal Use and LD 1 line is for General Purpose Data. U-Boot already contains HD eFuse reading and programming support. This patch implements LD eFuse reading support. LD 0 line is mapped to U-Boot fuse bank 64 and LD 1 line to fuse bank 65. LD 0 Marvell Internal Use line seems that was burned in factory with some data and can be read by U-Boot fuse command: => fuse read 64 0 9 LD 1 General Purpose Data line is by default empty and can be read by U-Boot fuse command: => fuse read 65 0 9 Signed-off-by: Pali Rohár Reviewed-by: Marek Behún --- arch/arm/mach-mvebu/efuse.c | 28 ++++++++++++++++++++++++++++ arch/arm/mach-mvebu/include/mach/efuse.h | 5 +++++ 2 files changed, 33 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/efuse.c b/arch/arm/mach-mvebu/efuse.c index c79eee98fe9..80318c339eb 100644 --- a/arch/arm/mach-mvebu/efuse.c +++ b/arch/arm/mach-mvebu/efuse.c @@ -27,6 +27,7 @@ enum { MVEBU_EFUSE_CTRL_PROGRAM_ENABLE = (1 << 31), + MVEBU_EFUSE_LD1_SELECT = (1 << 6), }; struct mvebu_hd_efuse { @@ -39,8 +40,10 @@ struct mvebu_hd_efuse { #ifndef DRY_RUN static struct mvebu_hd_efuse *efuses = (struct mvebu_hd_efuse *)(MBUS_EFUSE_BASE + 0xF9000); +static u32 *ld_efuses = (void *)MBUS_EFUSE_BASE + 0xF8F00; #else static struct mvebu_hd_efuse efuses[EFUSE_LINE_MAX + 1]; +static u32 ld_efuses[EFUSE_LD_WORDS]; #endif static int efuse_initialised; @@ -169,6 +172,21 @@ int mvebu_read_efuse(int nr, struct efuse_val *val) return 0; } +void mvebu_read_ld_efuse(int ld1, u32 *line) +{ + int i; + +#ifndef DRY_RUN + if (ld1) + setbits_le32(MVEBU_EFUSE_CONTROL, MVEBU_EFUSE_LD1_SELECT); + else + clrbits_le32(MVEBU_EFUSE_CONTROL, MVEBU_EFUSE_LD1_SELECT); +#endif + + for (i = 0; i < EFUSE_LD_WORDS; i++) + line[i] = readl(ld_efuses + i); +} + int mvebu_write_efuse(int nr, struct efuse_val *val) { return prog_efuse(nr, val, ~0, ~0); @@ -199,8 +217,18 @@ static int valid_prog_words; int fuse_read(u32 bank, u32 word, u32 *val) { struct efuse_val fuse_line; + u32 ld_line[EFUSE_LD_WORDS]; int res; + if ((bank == EFUSE_LD0_LINE || bank == EFUSE_LD1_LINE) && word < EFUSE_LD_WORDS) { + res = mvebu_efuse_init_hw(); + if (res) + return res; + mvebu_read_ld_efuse(bank == EFUSE_LD1_LINE, ld_line); + *val = ld_line[word]; + return 0; + } + if (bank < EFUSE_LINE_MIN || bank > EFUSE_LINE_MAX || word > 2) return -EINVAL; diff --git a/arch/arm/mach-mvebu/include/mach/efuse.h b/arch/arm/mach-mvebu/include/mach/efuse.h index bbc5844d849..122e735f2fc 100644 --- a/arch/arm/mach-mvebu/include/mach/efuse.h +++ b/arch/arm/mach-mvebu/include/mach/efuse.h @@ -53,8 +53,13 @@ enum efuse_line { EFUSE_LINE_MIN = 0, EFUSE_LINE_MAX = 63, + + EFUSE_LD0_LINE = 64, + EFUSE_LD1_LINE = 65, }; +#define EFUSE_LD_WORDS 9 + #endif int mvebu_efuse_init_hw(void); -- cgit v1.3.1 From 372779abc3efe869aaa3c61c4bf6e2fcbaa46b57 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Wed, 6 Apr 2022 16:20:18 +0200 Subject: arm: Introduce new CONFIG_SPL_SYS_NO_VECTOR_TABLE option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move OMAP4 specific option for disabling overwriting vector table into config option CONFIG_SPL_SYS_NO_VECTOR_TABLE. Signed-off-by: Pali Rohár --- arch/arm/Kconfig | 4 ++++ arch/arm/cpu/armv7/start.S | 4 +--- arch/arm/mach-omap2/Kconfig | 1 + 3 files changed, 6 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index efe33a58e1e..10726eae347 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -57,6 +57,10 @@ config SYS_INIT_SP_BSS_OFFSET that the early malloc region, global data (gd), and early stack usage do not overlap any appended DTB. +config SPL_SYS_NO_VECTOR_TABLE + depends on SPL + bool + config LINUX_KERNEL_IMAGE_HEADER depends on ARM64 bool diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index af87a5432ae..37036128a78 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -97,12 +97,10 @@ switch_to_hypervisor_ret: orr r0, r0, #0xc0 @ disable FIQ and IRQ msr cpsr,r0 +#if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE) /* * Setup vector: - * (OMAP4 spl TEXT_BASE is not 32 byte aligned. - * Continue to use ROM code vector only in OMAP4 spl) */ -#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */ mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register bic r0, #CR_V @ V = 0 diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 263142683b0..e1b9180a3bb 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -32,6 +32,7 @@ config OMAP34XX config OMAP44XX bool "OMAP44XX SoC" select SPL_USE_TINY_PRINTF + select SPL_SYS_NO_VECTOR_TABLE if SPL imply NAND_OMAP_ELM imply NAND_OMAP_GPMC imply SPL_DISPLAY_PRINT -- cgit v1.3.1 From 5165d2a04a777a9b636d6a3fe6d23f9c5086ff62 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Wed, 6 Apr 2022 16:20:19 +0200 Subject: arm: Do not compile vector table when SYS_NO_VECTOR_TABLE is enabled MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Vector table is not used when SYS_NO_VECTOR_TABLE is enabled. So do not compile it and reduce image size. Signed-off-by: Pali Rohár --- arch/arm/lib/vectors.S | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index 56f36815582..a54c84b062b 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -24,6 +24,7 @@ #else b reset #endif +#if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE) ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -31,6 +32,7 @@ ldr pc, _not_used ldr pc, _irq ldr pc, _fiq +#endif .endm @@ -87,6 +89,7 @@ _start: ARM_VECTORS #endif /* !defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) */ +#if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE) /* ************************************************************************* * @@ -118,6 +121,7 @@ _irq: .word irq _fiq: .word fiq .balignl 16,0xdeadbeef +#endif /* ************************************************************************* @@ -131,6 +135,7 @@ _fiq: .word fiq #ifdef CONFIG_SPL_BUILD +#if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE) .align 5 undefined_instruction: software_interrupt: @@ -141,6 +146,7 @@ irq: fiq: 1: b 1b /* hang and never return */ +#endif #else /* !CONFIG_SPL_BUILD */ -- cgit v1.3.1 From 2975bba6dfdd3c190a473686765e9a936938c394 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Wed, 6 Apr 2022 16:20:20 +0200 Subject: arm: mvebu: Enable CONFIG_SPL_SYS_NO_VECTOR_TABLE for 32-bit mvebu MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit U-Boot SPL is on 32-bit mvebu executed by the BootROM. And BootROM expects that U-Boot SPL returns execution back to the BootROM. Vectors during execution of U-Boot SPL should not be changed as BootROM does not expect it and uses its own vectors. So do not overwrite vectors in SPL build. Signed-off-by: Pali Rohár --- arch/arm/mach-mvebu/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index ccdb624ba7d..a3f273f4f94 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -15,6 +15,7 @@ config ARMADA_32BIT select SPL_SIMPLE_BUS if SPL select SUPPORT_SPL select TRANSLATION_OFFSET + select SPL_SYS_NO_VECTOR_TABLE if SPL config ARMADA_64BIT bool -- cgit v1.3.1 From 1d71bbca45b03eb5ba6cabbb2859047b8cb80229 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Thu, 7 Apr 2022 11:32:10 +0200 Subject: arm: mvebu: a37xx: Add support for writing Security OTP values MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement write support for Security OTP values via mailbox API commands MBOX_CMD_OTP_WRITE_32B and MBOX_CMD_OTP_WRITE. Write support for North and South Bridge OTPs are not implemented as these OTPs are already burned in factory with some data. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún --- arch/arm/mach-mvebu/armada3700/efuse.c | 50 ++++++++++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/armada3700/efuse.c b/arch/arm/mach-mvebu/armada3700/efuse.c index 50c73f36c56..07d5f394354 100644 --- a/arch/arm/mach-mvebu/armada3700/efuse.c +++ b/arch/arm/mach-mvebu/armada3700/efuse.c @@ -113,6 +113,41 @@ static int rwtm_otp_read(u8 row, u32 word, u32 *data) return res; } +static int rwtm_otp_write(u8 row, u32 word, u32 data) +{ + u32 in[4]; + int res = -EINVAL; + + if (word < 2) { + /* + * MBOX_CMD_OTP_WRITE_32B command is supported by Marvell + * fuse.bin firmware and also by new CZ.NIC wtmi firmware. + * This command writes only selected bits to OTP and does + * not calculate ECC bits. It does not allow to write the + * lock bit. + */ + in[0] = row; + in[1] = word * 32; + in[2] = data; + res = mbox_do_cmd(MBOX_CMD_OTP_WRITE_32B, in, 3, NULL, 0); + } else if (word == 2 && !(data & ~0x1)) { + /* + * MBOX_CMD_OTP_WRITE command is supported only by new CZ.NIC + * wtmi firmware and allows to write any bit to OTP, including + * the lock bit. It does not calculate or write ECC bits too. + * For compatibility with Marvell fuse.bin firmware, use this + * command only for writing the lock bit. + */ + in[0] = row; + in[1] = 0; + in[2] = 0; + in[3] = data; + res = mbox_do_cmd(MBOX_CMD_OTP_WRITE, in, 4, NULL, 0); + } + + return res; +} + /* * Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits via 44 banks and words 0-2) * Bank 44 is used for accessing North Bridge OTP (69 bits via words 0-2) @@ -154,8 +189,19 @@ int fuse_read(u32 bank, u32 word, u32 *val) int fuse_prog(u32 bank, u32 word, u32 val) { - /* TODO: not implemented yet */ - return -ENOSYS; + if (bank <= RWTM_MAX_BANK) { + if (word >= RWTM_ROW_WORDS) + return -EINVAL; + return rwtm_otp_write(bank, word, val); + } else if (bank == OTP_NB_BANK) { + /* TODO: not implemented yet */ + return -ENOSYS; + } else if (bank == OTP_SB_BANK) { + /* TODO: not implemented yet */ + return -ENOSYS; + } else { + return -EINVAL; + } } int fuse_sense(u32 bank, u32 word, u32 *val) -- cgit v1.3.1 From 08b99b67753a26ce142965151244261cdd73c490 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Fri, 8 Apr 2022 16:30:15 +0200 Subject: board: turris: Rename atsha204a@64 DT node to crypto@64 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DT node name should be generic, therefore rename atsha204a@64 to crypto@64. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún --- arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi | 2 +- board/CZ.NIC/turris_atsha_otp.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi index 008787e664c..64ebe2c6d47 100644 --- a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi +++ b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi @@ -29,7 +29,7 @@ u-boot,dm-pre-reloc; /* ATSHA204A at address 0x64 */ - atsha204a@64 { + crypto@64 { u-boot,dm-pre-reloc; compatible = "atmel,atsha204a"; reg = <0x64>; diff --git a/board/CZ.NIC/turris_atsha_otp.c b/board/CZ.NIC/turris_atsha_otp.c index 7a39b7f61d5..8c39f5e5241 100644 --- a/board/CZ.NIC/turris_atsha_otp.c +++ b/board/CZ.NIC/turris_atsha_otp.c @@ -21,7 +21,7 @@ static struct udevice *get_atsha204a_dev(void) /* Cannot be static because BSS does not have to be ready at this early stage */ struct udevice *dev; - if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) { + if (uclass_get_device_by_name(UCLASS_MISC, "crypto@64", &dev)) { puts("Cannot find ATSHA204A on I2C bus!\n"); dev = NULL; } -- cgit v1.3.1