From fe63d3cfb77ef5986951c04a9fa8fe73fb32fdb6 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 19 Feb 2019 16:49:05 +0100 Subject: ARM: dts: stm32: Sync DT with v4.20 kernel for stm32f7 Synchronize stm32f7 device tree with kernel v4.20. All pinctrl bindings are updated. Signed-off-by: Patrice Chotard --- arch/arm/dts/stm32746g-eval-u-boot.dtsi | 171 ++++---- arch/arm/dts/stm32746g-eval.dts | 102 +++-- arch/arm/dts/stm32f7-pinctrl.dtsi | 289 +++++++++++++ arch/arm/dts/stm32f7-u-boot.dtsi | 11 +- arch/arm/dts/stm32f746-disco-u-boot.dtsi | 174 ++++---- arch/arm/dts/stm32f746-disco.dts | 84 ++-- arch/arm/dts/stm32f746-pinctrl.dtsi | 11 + arch/arm/dts/stm32f746.dtsi | 699 +++++++++++++++++++++++-------- arch/arm/dts/stm32f769-disco-u-boot.dtsi | 142 +++---- arch/arm/dts/stm32f769-disco.dts | 93 +++- arch/arm/dts/stm32f769-pinctrl.dtsi | 11 + 11 files changed, 1287 insertions(+), 500 deletions(-) create mode 100644 arch/arm/dts/stm32f7-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32f746-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32f769-pinctrl.dtsi (limited to 'arch') diff --git a/arch/arm/dts/stm32746g-eval-u-boot.dtsi b/arch/arm/dts/stm32746g-eval-u-boot.dtsi index 27d3c8a4457..9b55bb7601b 100644 --- a/arch/arm/dts/stm32746g-eval-u-boot.dtsi +++ b/arch/arm/dts/stm32746g-eval-u-boot.dtsi @@ -19,7 +19,7 @@ gpio8 = &gpioi; gpio9 = &gpioj; gpio10 = &gpiok; - mmc0 = &sdio; + mmc0 = &sdio1; spi0 = &qspi; }; @@ -66,97 +66,114 @@ &pinctrl { ethernet_mii: mii@0 { pins { - pinmux = , - , - , - , - , - , - , - , - ; + pinmux = , /*ETH_MII_CRS */ + , /*ETH_MII_RX_CLK */ + , /*ETH_MII_RX_DV */ + , /*ETH_MII_MCO1 */ + , /*ETH_MII_TXD0 */ + , /*ETH_MII_TXD1 */ + , /*ETH_MII_TXD2 */ + , /*ETH_MII_TXD3 */ + , /*ETH_MII_TX_CLK */ + , /*ETH_MII_RXD0 */ + , /*ETH_MII_RXD1 */ + , /*ETH_MII_RXD2 */ + , /*ETH_MII_RXD3 */ + , /*ETH_MII_TX_EN */ + , /*ETH_MII_MDC */ + ; /*ETH_MII_MDIO */ slew-rate = <2>; }; }; fmc_pins: fmc@0 { pins { - pinmux = , /* FMC_D31 */ - , /* FMC_D30*/ - , /* FMC_D29 */ - , /* FMC_D28 */ - , /* FMC_D27 */ - , /* FMC_D26 */ - , /* FMC_D25 */ - , /* FMC_D24 */ - , /* FMC_D23 */ - , /* FMC_D22 */ - , /* FMC_D21 */ - , /* FMC_D20 */ - , /* FMC_D19 */ - , /* FMC_D18 */ - , /* FMC_D17 */ - , /* FMC_D16 */ - - , /* FMC_D15 */ - , /* FMC_D14*/ - , /* FMC_D13 */ - ,/* FMC_D12 */ - ,/* FMC_D11 */ - ,/* FMC_D10 */ - , /* FMC_D9 */ - , /* FMC_D8 */ - , /* FMC_D7 */ - , /* FMC_D6 */ - , /* FMC_D5*/ - , /* FMC_D4 */ - , /* FMC_D3 */ - , /* FMC_D2 */ - , /* FMC_D1 */ - , /* FMC_D0 */ - - , /* FMC_NBL3 */ - , /* FMC_NBL2 */ - , /* FMC_NBL1 */ - , /* FMC_NBL0 */ - - , /* FMC_A15 FMC_BA1 */ - , /* FMC_A14 FMC_BA0*/ - - , /* FMC_A11 */ - , /* FMC_A10 */ - , /* FMC_A9 */ - , /* FMC_A8 */ - , /* FMC_A7 */ - , /* FMC_A6 */ - , /* FUNC_FMC_A5 */ - , /* FMC_A4 */ - , /* FMC_A3 */ - , /* FMC_A2 */ - , /* FMC_A1 */ - , /* FMC_A0 */ - - ,/* FMC_SDNE0 */ - , /* FMC_SDNWE */ - , /* FMC_SDNRAS */ - , /* FMC_SDNCAS */ - , /* FMC_SDCKE0 */ - ; /* FMC_SDCLK */ + pinmux = , /* D31 */ + , /* D30 */ + , /* D29 */ + , /* D28 */ + , /* D27 */ + , /* D26 */ + , /* D25 */ + , /* D24 */ + , /* D23 */ + , /* D22 */ + , /* D21 */ + , /* D20 */ + , /* D19 */ + , /* D18 */ + , /* D17 */ + , /* D16 */ + + , /* D15 */ + , /* D14 */ + , /* D13 */ + , /* D12 */ + , /* D11 */ + , /* D10 */ + , /* D9 */ + , /* D8 */ + , /* D7 */ + , /* D6 */ + , /* D5 */ + , /* D4 */ + , /* D3 */ + , /* D2 */ + , /* D1 */ + , /* D0 */ + + , /* NBL3 */ + , /* NBL2 */ + , /* NBL1 */ + , /* NBL0 */ + + , /* BA1 */ + , /* BA0 */ + + , /* A11 */ + , /* A10 */ + , /* A9 */ + , /* A8 */ + , /* A7 */ + , /* A6 */ + , /* A5 */ + , /* A4 */ + , /* A3 */ + , /* A2 */ + , /* A1 */ + , /* A0 */ + + , /* SDNE0 */ + , /* SDNWE */ + , /* SDNRAS */ + , /* SDNCAS */ + , /* SDCKE0 */ + ; /* SDCLK> */ slew-rate = <2>; }; }; qspi_pins: qspi@0 { pins { - pinmux = , - , - , - , - , - ; + pinmux = , /* _FUNC_QUADSPI_CLK */ + , /*_FUNC_QUADSPI_BK1_NCS */ + , /* _FUNC_QUADSPI_BK1_IO0 */ + , /* _FUNC_QUADSPI_BK1_IO1 */ + , /* AF_FUNC_QUADSPI_BK1_IO3 */ + ; /* _FUNC_QUADSPI_BK1_IO2 */ slew-rate = <2>; }; }; + + usart1_pins_a: usart1@0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; + }; }; &qspi { diff --git a/arch/arm/dts/stm32746g-eval.dts b/arch/arm/dts/stm32746g-eval.dts index 94df80f69d1..8c081eaf20f 100644 --- a/arch/arm/dts/stm32746g-eval.dts +++ b/arch/arm/dts/stm32746g-eval.dts @@ -1,9 +1,5 @@ /* - * Copyright 2018 - Christophe Priouzeau - * - * Based on: - * stm32f746-disco.dts from U-boot 2018.01 - * Copyright 2016 - Lee Jones + * Copyright 2015 - Maxime Coquelin * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -46,55 +42,105 @@ /dts-v1/; #include "stm32f746.dtsi" -#include +#include "stm32f746-pinctrl.dtsi" +#include / { - model = "STMicroelectronics STM32F746G-EVAL board"; - compatible = "st,stm32f746g-eval", "st,stm32f746"; + model = "STMicroelectronics STM32746g-EVAL board"; + compatible = "st,stm32746g-eval", "st,stm32f746"; chosen { + bootargs = "root=/dev/ram"; stdout-path = "serial0:115200n8"; }; memory { - reg = <0xC0000000 0x2000000>; + reg = <0xc0000000 0x2000000>; }; aliases { serial0 = &usart1; }; + + leds { + compatible = "gpio-leds"; + green { + gpios = <&gpiof 10 1>; + linux,default-trigger = "heartbeat"; + }; + red { + gpios = <&gpiob 7 1>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@0 { + label = "Wake up"; + linux,code = ; + gpios = <&gpioc 13 0>; + }; + }; + + usbotg_hs_phy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; + clock-names = "main_clk"; + }; + + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &clk_hse { clock-frequency = <25000000>; }; -&pinctrl { - usart1_pins_a: usart1@0 { - pins1 { - pinmux = ; - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = ; - bias-disable; - }; - }; +&crc { + status = "okay"; }; -&usart1 { - pinctrl-0 = <&usart1_pins_a>; +&i2c1 { + pinctrl-0 = <&i2c1_pins_b>; pinctrl-names = "default"; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + +&rtc { status = "okay"; }; -&sdio { +&sdio1 { status = "okay"; + vmmc-supply = <&mmc_vcard>; + broken-cd; pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_pins_od>; + pinctrl-0 = <&sdio_pins_a>; + pinctrl-1 = <&sdio_pins_od_a>; bus-width = <4>; - max-frequency = <25000000>; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "otg"; + phys = <&usbotg_hs_phy>; + phy-names = "usb2-phy"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + status = "okay"; }; diff --git a/arch/arm/dts/stm32f7-pinctrl.dtsi b/arch/arm/dts/stm32f7-pinctrl.dtsi new file mode 100644 index 00000000000..9314128df18 --- /dev/null +++ b/arch/arm/dts/stm32f7-pinctrl.dtsi @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include +#include + +/ { + soc { + pinctrl: pin-controller { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40020000 0x3000>; + interrupt-parent = <&exti>; + st,syscfg = <&syscfg 0x8>; + pins-are-numbered; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; + st,bank-name = "GPIOA"; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x400 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; + st,bank-name = "GPIOB"; + }; + + gpioc: gpio@40020800 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x800 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; + st,bank-name = "GPIOC"; + }; + + gpiod: gpio@40020c00 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xc00 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; + st,bank-name = "GPIOD"; + }; + + gpioe: gpio@40021000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; + st,bank-name = "GPIOE"; + }; + + gpiof: gpio@40021400 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1400 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; + st,bank-name = "GPIOF"; + }; + + gpiog: gpio@40021800 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1800 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; + st,bank-name = "GPIOG"; + }; + + gpioh: gpio@40021c00 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1c00 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; + st,bank-name = "GPIOH"; + }; + + gpioi: gpio@40022000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; + st,bank-name = "GPIOI"; + }; + + gpioj: gpio@40022400 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2400 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; + st,bank-name = "GPIOJ"; + }; + + gpiok: gpio@40022800 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2800 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; + st,bank-name = "GPIOK"; + }; + + cec_pins_a: cec@0 { + pins { + pinmux = ; /* HDMI CEC */ + slew-rate = <0>; + drive-open-drain; + bias-disable; + }; + }; + + usart1_pins_a: usart1@0 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart1_pins_b: usart1@1 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + i2c1_pins_b: i2c1@0 { + pins { + pinmux = , /* I2C1 SDA */ + ; /* I2C1 SCL */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + usbotg_hs_pins_a: usbotg-hs@0 { + pins { + pinmux = , /* OTG_HS_ULPI_NXT */ + , /* OTG_HS_ULPI_DIR */ + , /* OTG_HS_ULPI_STP */ + , /* OTG_HS_ULPI_CK */ + , /* OTG_HS_ULPI_D0 */ + , /* OTG_HS_ULPI_D1 */ + , /* OTG_HS_ULPI_D2 */ + , /* OTG_HS_ULPI_D3 */ + , /* OTG_HS_ULPI_D4 */ + , /* OTG_HS_ULPI_D5 */ + , /* OTG_HS_ULPI_D6 */ + ; /* OTG_HS_ULPI_D7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_hs_pins_b: usbotg-hs@1 { + pins { + pinmux = , /* OTG_HS_ULPI_NXT */ + , /* OTG_HS_ULPI_DIR */ + , /* OTG_HS_ULPI_STP */ + , /* OTG_HS_ULPI_CK */ + , /* OTG_HS_ULPI_D0 */ + , /* OTG_HS_ULPI_D1 */ + , /* OTG_HS_ULPI_D2 */ + , /* OTG_HS_ULPI_D3 */ + , /* OTG_HS_ULPI_D4 */ + , /* OTG_HS_ULPI_D5 */ + , /* OTG_HS_ULPI_D6 */ + ; /* OTG_HS_ULPI_D7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_fs_pins_a: usbotg-fs@0 { + pins { + pinmux = , /* OTG_FS_ID */ + , /* OTG_FS_DM */ + ; /* OTG_FS_DP */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdio_pins_a: sdio_pins_a@0 { + pins { + pinmux = , /* SDMMC1 D0 */ + , /* SDMMC1 D1 */ + , /* SDMMC1 D2 */ + , /* SDMMC1 D3 */ + , /* SDMMC1 CLK */ + ; /* SDMMC1 CMD */ + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdio_pins_od_a: sdio_pins_od_a@0 { + pins1 { + pinmux = , /* SDMMC1 D0 */ + , /* SDMMC1 D1 */ + , /* SDMMC1 D2 */ + , /* SDMMC1 D3 */ + ; /* SDMMC1 CLK */ + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = ; /* SDMMC1 CMD */ + drive-open-drain; + slew-rate = <2>; + }; + }; + + sdio_pins_b: sdio_pins_b@0 { + pins { + pinmux = , /* SDMMC2 D0 */ + , /* SDMMC2 D1 */ + , /* SDMMC2 D2 */ + , /* SDMMC2 D3 */ + , /* SDMMC2 CLK */ + ; /* SDMMC2 CMD */ + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdio_pins_od_b: sdio_pins_od_b@0 { + pins1 { + pinmux = , /* SDMMC2 D0 */ + , /* SDMMC2 D1 */ + , /* SDMMC2 D2 */ + , /* SDMMC2 D3 */ + ; /* SDMMC2 CLK */ + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = ; /* SDMMC2 CMD */ + drive-open-drain; + slew-rate = <2>; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi index cf0cc3b408a..7816b79bcf9 100644 --- a/arch/arm/dts/stm32f7-u-boot.dtsi +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include /{ soc { u-boot,dm-pre-reloc; @@ -126,16 +127,6 @@ u-boot,dm-pre-reloc; }; }; - - usart1_pins_a: usart1@0 { - u-boot,dm-pre-reloc; - pins1 { - u-boot,dm-pre-reloc; - }; - pins2 { - u-boot,dm-pre-reloc; - }; - }; }; &pwrcfg { diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi index ceab5e5933d..bc337b1628b 100644 --- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi @@ -19,7 +19,7 @@ gpio8 = &gpioi; gpio9 = &gpioj; gpio10 = &gpiok; - mmc0 = &sdio; + mmc0 = &sdio1; spi0 = &qspi; }; @@ -109,15 +109,15 @@ &pinctrl { ethernet_mii: mii@0 { pins { - pinmux = , - , - , - , - , - , - , - , - ; + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_RMII_CRS_DV */ + , /* ETH_RMII_RXD0 */ + ; /* ETH_RMII_RXD1 */ slew-rate = <2>; }; }; @@ -126,99 +126,99 @@ u-boot,dm-pre-reloc; pins { u-boot,dm-pre-reloc; - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - - , - , - - , - , - - , - , - , - , - , - , - , - , - , - , - , - , - - , - , - , - , - , - ; + pinmux = , /* D15 */ + , /* D14 */ + , /* D13 */ + , /* D12 */ + , /* D11 */ + , /* D10 */ + , /* D9 */ + , /* D8 */ + , /* D7 */ + , /* D6 */ + , /* D5 */ + , /* D4 */ + , /* D3 */ + , /* D2 */ + , /* D1 */ + , /* D0 */ + + , /* NBL1 */ + , /* NBL0 */ + + , /* BA1 */ + , /* BA0 */ + + , /* A11 */ + , /* A10 */ + , /* A9 */ + , /* A8 */ + , /* A7 */ + , /* A6 */ + , /* A5 */ + , /* A4 */ + , /* A3 */ + , /* A2 */ + , /* A1 */ + , /* A0 */ + + , /* SDNE0 */ + , /* SDNWE */ + , /* SDNRAS */ + , /* SDNCAS */ + , /* SDCKE0 */ + ; /* SDCLK> */ slew-rate = <2>; }; }; ltdc_pins: ltdc@0 { pins { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + pinmux = , /* B0 */ + , /* B4 */ + , /* VSYNC */ + , /* HSYNC */ + , /* CLK */ + , /* R0 */ + , /* R1 */ + , /* R2 */ + , /* R3 */ + , /* R4 */ + , /* R5 */ + , /* R6 */ + , /* R7 */ + , /* G0 */ + , /* G1 */ + , /* G2 */ + , /* G3 */ + , /* G4 */ + , /* B1 */ + , /* B2 */ + , /* B3 */ + , /* G5 */ + , /* G6 */ + , /* G7 */ + , /* B5 */ + , /* B6 */ + , /* B7 */ + ; /* DE */ slew-rate = <2>; }; }; qspi_pins: qspi@0 { pins { - pinmux = , - , - , - , - , - ; + pinmux = , /* CLK */ + , /* BK1_NCS */ + , /* BK1_IO0 */ + , /* BK1_IO1 */ + , /* BK1_IO3 */ + ; /* BK1_IO2 */ slew-rate = <2>; }; }; - usart1_pins_a: usart1@0 { + usart1_pins_b: usart1@1 { u-boot,dm-pre-reloc; pins1 { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index d5687651706..e3a7bd338d6 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -1,10 +1,5 @@ /* - * Copyright 2016 - Michael Kurz - * Copyright 2016 - Vikas MANOCHA - * - * Based on: - * stm32f469-disco.dts from Linux - * Copyright 2016 - Lee Jones + * Copyright 2017 - Vikas MANOCHA * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -47,7 +42,8 @@ /dts-v1/; #include "stm32f746.dtsi" -#include +#include "stm32f746-pinctrl.dtsi" +#include #include / { @@ -55,7 +51,7 @@ compatible = "st,stm32f746-disco", "st,stm32f746"; chosen { - bootargs = "root=/dev/ram rdinit=/linuxrc"; + bootargs = "root=/dev/ram"; stdout-path = "serial0:115200n8"; }; @@ -67,39 +63,69 @@ serial0 = &usart1; }; + usbotg_hs_phy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; + clock-names = "main_clk"; + }; + + /* This turns on vbus for otg fs for host mode (dwc2) */ + vcc5v_otg_fs: vcc5v-otg-fs-regulator { + compatible = "regulator-fixed"; + gpio = <&gpiod 5 0>; + regulator-name = "vcc5_host1"; + regulator-always-on; + }; + + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &clk_hse { clock-frequency = <25000000>; }; -&pinctrl { - usart1_pins_a: usart1@0 { - pins1 { - pinmux = ; - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = ; - bias-disable; - }; - }; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_a>; +&i2c1 { + pinctrl-0 = <&i2c1_pins_b>; pinctrl-names = "default"; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; status = "okay"; }; -&sdio { +&sdio1 { status = "okay"; + vmmc-supply = <&mmc_vcard>; cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_pins_od>; + pinctrl-0 = <&sdio_pins_a>; + pinctrl-1 = <&sdio_pins_od_a>; bus-width = <4>; - max-frequency = <25000000>; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_b>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg_fs { + dr_mode = "host"; + pinctrl-0 = <&usbotg_fs_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "host"; + phys = <&usbotg_hs_phy>; + phy-names = "usb2-phy"; + pinctrl-0 = <&usbotg_hs_pins_b>; + pinctrl-names = "default"; + status = "okay"; }; diff --git a/arch/arm/dts/stm32f746-pinctrl.dtsi b/arch/arm/dts/stm32f746-pinctrl.dtsi new file mode 100644 index 00000000000..fcfd2ac7239 --- /dev/null +++ b/arch/arm/dts/stm32f746-pinctrl.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32f7-pinctrl.dtsi" + +&pinctrl{ + compatible = "st,stm32f746-pinctrl"; +}; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 7209864266d..f48d06a80d1 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -1,9 +1,4 @@ /* - * Copyright 2016 - Michael Kurz - * Copyright 2016 - Vikas MANOCHA - * - * Based on: - * stm32f429.dtsi from Linux * Copyright 2015 - Maxime Coquelin * * This file is dual-licensed: you can use it either under the terms @@ -45,8 +40,8 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include "skeleton.dtsi" #include "armv7-m.dtsi" -#include #include #include @@ -57,234 +52,584 @@ compatible = "fixed-clock"; clock-frequency = <0>; }; + + clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_i2s_ckin: clk-i2s-ckin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <48000000>; + }; }; soc { - usart1: serial@40011000 { - compatible = "st,stm32f7-usart", "st,stm32f7-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>; + timer2: timer@40000000 { + compatible = "st,stm32-timer"; + reg = <0x40000000 0x400>; + interrupts = <28>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; status = "disabled"; }; - pwrcfg: power-config@58024800 { - compatible = "syscon"; - reg = <0x40007000 0x400>; + timers2: timers@40000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000000 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@1 { + compatible = "st,stm32-timer-trigger"; + reg = <1>; + status = "disabled"; + }; }; - rcc: rcc@40023810 { - #reset-cells = <1>; - #clock-cells = <2>; - compatible = "st,stm32f746-rcc", "st,stm32-rcc"; - reg = <0x40023800 0x400>; - clocks = <&clk_hse>; - st,syscfg = <&pwrcfg>; + timer3: timer@40000400 { + compatible = "st,stm32-timer"; + reg = <0x40000400 0x400>; + interrupts = <29>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; + status = "disabled"; }; - pinctrl: pin-controller { + timers3: timers@40000400 { #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32f746-pinctrl"; - ranges = <0 0x40020000 0x3000>; - pins-are-numbered; - - gpioa: gpio@40020000 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x0 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; - st,bank-name = "GPIOA"; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000400 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; }; - gpiob: gpio@40020400 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; - st,bank-name = "GPIOB"; + timer@2 { + compatible = "st,stm32-timer-trigger"; + reg = <2>; + status = "disabled"; }; + }; + timer4: timer@40000800 { + compatible = "st,stm32-timer"; + reg = <0x40000800 0x400>; + interrupts = <30>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; + status = "disabled"; + }; - gpioc: gpio@40020800 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; - st,bank-name = "GPIOC"; + timers4: timers@40000800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000800 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; }; - gpiod: gpio@40020c00 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0xc00 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; - st,bank-name = "GPIOD"; + timer@3 { + compatible = "st,stm32-timer-trigger"; + reg = <3>; + status = "disabled"; + }; + }; + + timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; + }; + + timers5: timers@40000c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000C00 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; }; - gpioe: gpio@40021000 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x1000 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; - st,bank-name = "GPIOE"; + timer@4 { + compatible = "st,stm32-timer-trigger"; + reg = <4>; + status = "disabled"; }; + }; + + timer6: timer@40001000 { + compatible = "st,stm32-timer"; + reg = <0x40001000 0x400>; + interrupts = <54>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; + status = "disabled"; + }; + + timers6: timers@40001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001000 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; + clock-names = "int"; + status = "disabled"; - gpiof: gpio@40021400 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x1400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; - st,bank-name = "GPIOF"; + timer@5 { + compatible = "st,stm32-timer-trigger"; + reg = <5>; + status = "disabled"; }; + }; + + timer7: timer@40001400 { + compatible = "st,stm32-timer"; + reg = <0x40001400 0x400>; + interrupts = <55>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; + status = "disabled"; + }; + + timers7: timers@40001400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001400 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; + clock-names = "int"; + status = "disabled"; - gpiog: gpio@40021800 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x1800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; - st,bank-name = "GPIOG"; + timer@6 { + compatible = "st,stm32-timer-trigger"; + reg = <6>; + status = "disabled"; }; + }; + + timers12: timers@40001800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001800 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>; + clock-names = "int"; + status = "disabled"; - gpioh: gpio@40021c00 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x1c00 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; - st,bank-name = "GPIOH"; + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; }; - gpioi: gpio@40022000 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x2000 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; - st,bank-name = "GPIOI"; + timer@11 { + compatible = "st,stm32-timer-trigger"; + reg = <11>; + status = "disabled"; }; + }; + + timers13: timers@40001c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001C00 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; + clock-names = "int"; + status = "disabled"; - gpioj: gpio@40022400 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x2400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; - st,bank-name = "GPIOJ"; + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; }; + }; - gpiok: gpio@40022800 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x2800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; - st,bank-name = "GPIOK"; + timers14: timers@40002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40002000 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; }; + }; + + rtc: rtc@40002800 { + compatible = "st,stm32-rtc"; + reg = <0x40002800 0x400>; + clocks = <&rcc 1 CLK_RTC>; + clock-names = "ck_rtc"; + assigned-clocks = <&rcc 1 CLK_RTC>; + assigned-clock-parents = <&rcc 1 CLK_LSE>; + interrupt-parent = <&exti>; + interrupts = <17 1>; + interrupt-names = "alarm"; + st,syscfg = <&pwrcfg 0x00 0x100>; + status = "disabled"; + }; + + usart2: serial@40004400 { + compatible = "st,stm32f7-uart"; + reg = <0x40004400 0x400>; + interrupts = <38>; + clocks = <&rcc 1 CLK_USART2>; + status = "disabled"; + }; + + usart3: serial@40004800 { + compatible = "st,stm32f7-uart"; + reg = <0x40004800 0x400>; + interrupts = <39>; + clocks = <&rcc 1 CLK_USART3>; + status = "disabled"; + }; + + usart4: serial@40004c00 { + compatible = "st,stm32f7-uart"; + reg = <0x40004c00 0x400>; + interrupts = <52>; + clocks = <&rcc 1 CLK_UART4>; + status = "disabled"; + }; + + usart5: serial@40005000 { + compatible = "st,stm32f7-uart"; + reg = <0x40005000 0x400>; + interrupts = <53>; + clocks = <&rcc 1 CLK_UART5>; + status = "disabled"; + }; + + i2c1: i2c@40005400 { + compatible = "st,stm32f7-i2c"; + reg = <0x40005400 0x400>; + interrupts = <31>, + <32>; + resets = <&rcc STM32F7_APB1_RESET(I2C1)>; + clocks = <&rcc 1 CLK_I2C1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@40005800 { + compatible = "st,stm32f7-i2c"; + reg = <0x40005800 0x400>; + interrupts = <33>, + <34>; + resets = <&rcc STM32F7_APB1_RESET(I2C2)>; + clocks = <&rcc 1 CLK_I2C2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@40005C00 { + compatible = "st,stm32f7-i2c"; + reg = <0x40005C00 0x400>; + interrupts = <72>, + <73>; + resets = <&rcc STM32F7_APB1_RESET(I2C3)>; + clocks = <&rcc 1 CLK_I2C3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@40006000 { + compatible = "st,stm32f7-i2c"; + reg = <0x40006000 0x400>; + interrupts = <95>, + <96>; + resets = <&rcc STM32F7_APB1_RESET(I2C4)>; + clocks = <&rcc 1 CLK_I2C4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + cec: cec@40006c00 { + compatible = "st,stm32-cec"; + reg = <0x40006C00 0x400>; + interrupts = <94>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; + clock-names = "cec", "hdmi-cec"; + status = "disabled"; + }; + + usart7: serial@40007800 { + compatible = "st,stm32f7-uart"; + reg = <0x40007800 0x400>; + interrupts = <82>; + clocks = <&rcc 1 CLK_UART7>; + status = "disabled"; + }; + + usart8: serial@40007c00 { + compatible = "st,stm32f7-uart"; + reg = <0x40007c00 0x400>; + interrupts = <83>; + clocks = <&rcc 1 CLK_UART8>; + status = "disabled"; + }; + + timers1: timers@40010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>; + clock-names = "int"; + status = "disabled"; - sdio_pins: sdio_pins@0 { - pins { - pinmux = , - , - , - , - , - ; - drive-push-pull; - slew-rate = <2>; - }; + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; }; - sdio_pins_od: sdio_pins_od@0 { - pins1 { - pinmux = , - , - , - , - ; - drive-push-pull; - slew-rate = <2>; - }; - - pins2 { - pinmux = ; - drive-open-drain; - slew-rate = <2>; - }; + timer@0 { + compatible = "st,stm32-timer-trigger"; + reg = <0>; + status = "disabled"; }; + }; - sdio_pins_b: sdio_pins_b@0 { - pins { - pinmux = , - , - , - , - , - ; - drive-push-pull; - slew-rate = <2>; - }; + timers8: timers@40010400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010400 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; }; - sdio_pins_od_b: sdio_pins_od_b@0 { - pins1 { - pinmux = , - , - , - , - ; - drive-push-pull; - slew-rate = <2>; - }; - - pins2 { - pinmux = ; - drive-open-drain; - slew-rate = <2>; - }; + timer@7 { + compatible = "st,stm32-timer-trigger"; + reg = <7>; + status = "disabled"; }; + }; + usart1: serial@40011000 { + compatible = "st,stm32f7-uart"; + reg = <0x40011000 0x400>; + interrupts = <37>; + clocks = <&rcc 1 CLK_USART1>; + status = "disabled"; }; - sdio: sdio@40012c00 { - compatible = "st,stm32f4xx-sdio"; - reg = <0x40012c00 0x400>; - clocks = <&rcc 0 171>; - interrupts = <49>; + + usart6: serial@40011400 { + compatible = "st,stm32f7-uart"; + reg = <0x40011400 0x400>; + interrupts = <71>; + clocks = <&rcc 1 CLK_USART6>; status = "disabled"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_pins_od>; - pinctrl-names = "default", "opendrain"; - max-frequency = <48000000>; }; sdio2: sdio2@40011c00 { - compatible = "st,stm32f4xx-sdio"; + compatible = "arm,pl180", "arm,primecell"; + arm,primecell-periphid = <0x00880180>; reg = <0x40011c00 0x400>; - clocks = <&rcc 0 167>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>; + clock-names = "apb_pclk"; interrupts = <103>; + max-frequency = <48000000>; status = "disabled"; - pinctrl-0 = <&sdio_pins_b>; - pinctrl-1 = <&sdio_pins_od_b>; - pinctrl-names = "default", "opendrain"; + }; + + sdio1: sdio1@40012c00 { + compatible = "arm,pl180", "arm,primecell"; + arm,primecell-periphid = <0x00880180>; + reg = <0x40012c00 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>; + clock-names = "apb_pclk"; + interrupts = <49>; max-frequency = <48000000>; + status = "disabled"; }; - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; + syscfg: system-config@40013800 { + compatible = "syscon"; + reg = <0x40013800 0x400>; + }; + + exti: interrupt-controller@40013c00 { + compatible = "st,stm32-exti"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x40013C00 0x400>; + interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; + }; + + timers9: timers@40014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014000 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@8 { + compatible = "st,stm32-timer-trigger"; + reg = <8>; + status = "disabled"; + }; + }; + + timers10: timers@40014400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014400 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + + timers11: timers@40014800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014800 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + + pwrcfg: power-config@40007000 { + compatible = "syscon"; + reg = <0x40007000 0x400>; + }; + + crc: crc@40023000 { + compatible = "st,stm32f7-crc"; + reg = <0x40023000 0x400>; + clocks = <&rcc 0 12>; + status = "disabled"; + }; + + rcc: rcc@40023800 { + #reset-cells = <1>; + #clock-cells = <2>; + compatible = "st,stm32f746-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + clocks = <&clk_hse>, <&clk_i2s_ckin>; + st,syscfg = <&pwrcfg>; + assigned-clocks = <&rcc 1 CLK_HSE_RTC>; + assigned-clock-rates = <1000000>; + }; + + dma1: dma@40026000 { + compatible = "st,stm32-dma"; + reg = <0x40026000 0x400>; + interrupts = <11>, + <12>, + <13>, + <14>, + <15>, + <16>, + <17>, + <47>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>; + #dma-cells = <4>; + status = "disabled"; + }; + + dma2: dma@40026400 { + compatible = "st,stm32-dma"; + reg = <0x40026400 0x400>; + interrupts = <56>, + <57>, + <58>, + <59>, + <60>, + <68>, + <69>, + <70>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>; + #dma-cells = <4>; + st,mem2mem; + status = "disabled"; + }; + + usbotg_hs: usb@40040000 { + compatible = "st,stm32f7-hsotg"; + reg = <0x40040000 0x40000>; + interrupts = <77>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>; + clock-names = "otg"; + g-rx-fifo-size = <256>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <128 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + usbotg_fs: usb@50000000 { + compatible = "st,stm32f4x9-fsotg"; + reg = <0x50000000 0x40000>; + interrupts = <67>; + clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>; + clock-names = "otg"; + status = "disabled"; }; }; }; &systick { + clocks = <&rcc 1 0>; status = "okay"; }; diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi index 217c937b238..e9e43cba10b 100644 --- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi @@ -61,94 +61,94 @@ &pinctrl { ethernet_mii: mii@0 { pins { - pinmux = , - , - , - , - , - , - , - , - ; + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_RMII_CRS_DV */ + , /* ETH_RMII_RXD0 */ + ; /* ETH_RMII_RXD1 */ slew-rate = <2>; }; }; fmc_pins: fmc@0 { pins { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , + pinmux = , /* D31 */ + , /* D30 */ + , /* D29 */ + , /* D28 */ + , /* D27 */ + , /* D26 */ + , /* D25 */ + , /* D24 */ + , /* D23 */ + , /* D22 */ + , /* D21 */ + , /* D20 */ + , /* D19 */ + , /* D18 */ + , /* D17 */ + , /* D16 */ - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , + , /* D15 */ + , /* D14 */ + , /* D13 */ + , /* D12 */ + , /* D11 */ + , /* D10 */ + , /* D9 */ + , /* D8 */ + , /* D7 */ + , /* D6 */ + , /* D5 */ + , /* D4 */ + , /* D3 */ + , /* D2 */ + , /* D1 */ + , /* D0 */ - , - , - , - , + , /* NBL3 */ + , /* NBL2 */ + , /* NBL1 */ + , /* NBL0 */ - , - , + , /* BA1 */ + , /* BA0 */ - , - , - , - , - , - , - , - , - , - , - , - , + , /* A11 */ + , /* A10 */ + , /* A9 */ + , /* A8 */ + , /* A7 */ + , /* A6 */ + , /* A5 */ + , /* A4 */ + , /* A3 */ + , /* A2 */ + , /* A1 */ + , /* A0 */ - , - , - , - , - , - ; + , /* SDNE0 */ + , /* SDNWE */ + , /* SDNRAS */ + , /* SDNCAS */ + , /* SDCKE0 */ + ; /* SDCLK> */ slew-rate = <2>; }; }; qspi_pins: qspi@0 { pins { - pinmux = , - , - , - , - , - ; + pinmux = , /* CLK */ + , /* BK1_NCS */ + , /* BK1_IO0 */ + , /* BK1_IO1 */ + , /* BK1_IO3 */ + ; /* BK1_IO2 */ slew-rate = <2>; }; }; diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts index 046bb225a60..483d896e2bc 100644 --- a/arch/arm/dts/stm32f769-disco.dts +++ b/arch/arm/dts/stm32f769-disco.dts @@ -1,5 +1,5 @@ /* - * Copyright 2016 - Vikas Manocha + * Copyright 2017 - Vikas MANOCHA * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,14 +42,16 @@ /dts-v1/; #include "stm32f746.dtsi" -#include +#include "stm32f769-pinctrl.dtsi" +#include #include / { model = "STMicroelectronics STM32F769-DISCO board"; - compatible = "st,stm32f769-disco", "st,stm32f7"; + compatible = "st,stm32f769-disco", "st,stm32f769"; chosen { + bootargs = "root=/dev/ram"; stdout-path = "serial0:115200n8"; }; @@ -60,40 +62,89 @@ aliases { serial0 = &usart1; }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; -&pinctrl { - usart1_pins_a: usart1@0 { - pins1 { - pinmux = ; - bias-disable; - drive-push-pull; - slew-rate = <2>; + leds { + compatible = "gpio-leds"; + green { + gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; }; - pins2 { - pinmux = ; - bias-disable; + red { + gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>; }; }; + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@0 { + label = "User"; + linux,code = ; + gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; + }; + }; + + usbotg_hs_phy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; + clock-names = "main_clk"; + }; + + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; -&usart1 { - pinctrl-0 = <&usart1_pins_a>; +&cec { + pinctrl-0 = <&cec_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins_b>; pinctrl-names = "default"; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + +&rtc { status = "okay"; }; &sdio2 { status = "okay"; + vmmc-supply = <&mmc_vcard>; cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; + broken-cd; pinctrl-names = "default", "opendrain"; pinctrl-0 = <&sdio_pins_b>; pinctrl-1 = <&sdio_pins_od_b>; bus-width = <4>; - max-frequency = <25000000>; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "otg"; + phys = <&usbotg_hs_phy>; + phy-names = "usb2-phy"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + status = "okay"; }; diff --git a/arch/arm/dts/stm32f769-pinctrl.dtsi b/arch/arm/dts/stm32f769-pinctrl.dtsi new file mode 100644 index 00000000000..31005dd9929 --- /dev/null +++ b/arch/arm/dts/stm32f769-pinctrl.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32f7-pinctrl.dtsi" + +&pinctrl{ + compatible = "st,stm32f769-pinctrl"; +}; -- cgit v1.3.1