From 37997a214ed139760ea33fa8533087d44e991bf1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 16 Mar 2026 00:51:01 +0100 Subject: arm: renesas: Use stock lowlevel_init function and remove s_init Replace s_init() early initialization at the end of lowlevel_init by invoking the same code in mach_cpu_init(). The mach_cpu_init() is called a bit later, but as the code initializes timer and no code uses timer until mach_cpu_init(), this does not pose a problem. Signed-off-by: Marek Vasut --- board/renesas/common/gen3-spl.c | 4 ---- board/renesas/common/gen4-common.c | 4 +++- board/renesas/common/gen4-spl.c | 4 +++- board/renesas/common/gen5-common.c | 4 +++- 4 files changed, 9 insertions(+), 7 deletions(-) (limited to 'board/renesas') diff --git a/board/renesas/common/gen3-spl.c b/board/renesas/common/gen3-spl.c index 9590b5d6a2e..f833bfeaeee 100644 --- a/board/renesas/common/gen3-spl.c +++ b/board/renesas/common/gen3-spl.c @@ -29,10 +29,6 @@ u32 spl_boot_device(void) return BOOT_DEVICE_UART; } -void s_init(void) -{ -} - void reset_cpu(void) { } diff --git a/board/renesas/common/gen4-common.c b/board/renesas/common/gen4-common.c index ac87f2f08e3..c4a0335223c 100644 --- a/board/renesas/common/gen4-common.c +++ b/board/renesas/common/gen4-common.c @@ -41,10 +41,12 @@ static void init_gic_v3(void) writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0); } -void s_init(void) +int mach_cpu_init(void) { if (current_el() == 3) init_generic_timer(); + + return 0; } int board_early_init_f(void) diff --git a/board/renesas/common/gen4-spl.c b/board/renesas/common/gen4-spl.c index ebfefab7253..e4c1190eac7 100644 --- a/board/renesas/common/gen4-spl.c +++ b/board/renesas/common/gen4-spl.c @@ -82,7 +82,7 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) #define RTGRP3_BIT BIT(19) #define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT) -void s_init(void) +int mach_cpu_init(void) { /* Unlock CPG access */ writel(0x5A5AFFFF, CPGWPR); @@ -95,6 +95,8 @@ void s_init(void) writel(0x00ff00ff, APMU_BASE + 0x18); writel(0x00ff00ff, APMU_BASE + 0x1c); clrbits_le32(APMU_BASE + 0x68, BIT(29)); + + return 0; } void reset_cpu(void) diff --git a/board/renesas/common/gen5-common.c b/board/renesas/common/gen5-common.c index c60a76c5038..5160b32e2e3 100644 --- a/board/renesas/common/gen5-common.c +++ b/board/renesas/common/gen5-common.c @@ -37,10 +37,12 @@ static void init_gic_v3(void) writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0); } -void s_init(void) +int mach_cpu_init(void) { if (current_el() == 3) init_generic_timer(); + + return 0; } int board_early_init_f(void) -- cgit v1.2.3 From f18004993c94ce28537f051987e0f9767c5e0c9b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 25 Mar 2026 02:18:28 +0100 Subject: arm64: renesas: Make R-Car board code 32-bit ARMv8-M compatible The 64-bit R-Car board code is currently unbuildable on 32-bit ARM cores. Skip DRAM initialization bits to make the code compatible with these cores, because those cores do not use the DRAM, they only use SRAM. Signed-off-by: Marek Vasut --- board/renesas/common/rcar64-common.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'board/renesas') diff --git a/board/renesas/common/rcar64-common.c b/board/renesas/common/rcar64-common.c index bcb03792494..3d537be4d02 100644 --- a/board/renesas/common/rcar64-common.c +++ b/board/renesas/common/rcar64-common.c @@ -24,7 +24,8 @@ int dram_init(void) { int ret = fdtdec_setup_mem_size_base(); - if (current_el() == 3 && gd->ram_base == 0x48000000) { + if (IS_ENABLED(CONFIG_ARM64) && current_el() == 3 && + gd->ram_base == 0x48000000) { /* * If this U-Boot runs in EL3, make the bottom 128 MiB * available for loading of follow up firmware blobs. @@ -44,7 +45,7 @@ int dram_init_banksize(void) fdtdec_setup_memory_banksize(); - if (current_el() != 3) + if (IS_ENABLED(CONFIG_ARM64) && current_el() != 3) return 0; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { -- cgit v1.2.3