From cc6291e3b4a4a8520a3c4bb44eae2ecd8f1e9c0e Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 30 Jul 2025 17:42:16 +0200 Subject: board: phytec: phycore-am62ax: Add watchdog start to bootcmd Allows run-time control over watchdog auto-start and the timeout via setting the environment variable watchdog_timeout_ms. A value of zero means "do not start". Use CONFIG_WATCHDOG_TIMEOUT_MSECS as initial value. Users can enable the watchdog to monitor the boot process until userspace or OS takes over to serve the watchdog. Signed-off-by: Wadim Egorov --- board/phytec/phycore_am62ax/phycore_am62ax.env | 3 +++ 1 file changed, 3 insertions(+) (limited to 'board') diff --git a/board/phytec/phycore_am62ax/phycore_am62ax.env b/board/phytec/phycore_am62ax/phycore_am62ax.env index 797904013dc..3f4b3cc4f0d 100644 --- a/board/phytec/phycore_am62ax/phycore_am62ax.env +++ b/board/phytec/phycore_am62ax/phycore_am62ax.env @@ -2,6 +2,7 @@ #include #include #include +#include fdtaddr=0x88000000 loadaddr=0x82000000 @@ -27,3 +28,5 @@ spi_ramdisk_addr=0x2200000 bootmeths=script efi extlinux pxe boot_targets=mmc1 mmc0 spi_flash dhcp + +watchdog=watchdog@e000000 -- cgit v1.3.1 From d27b7a1c777abe1bc103c983d0af082345457e7d Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 30 Jul 2025 17:42:14 +0200 Subject: board: phytec: phycore-am62x: Add watchdog start to bootcmd Allows run-time control over watchdog auto-start and the timeout via setting the environment variable watchdog_timeout_ms. A value of zero means "do not start". Use CONFIG_WATCHDOG_TIMEOUT_MSECS as initial value. Users can enable the watchdog to monitor the boot process until userspace or OS takes over to serve the watchdog. Signed-off-by: Wadim Egorov --- board/phytec/phycore_am62x/phycore_am62x.env | 3 +++ configs/phycore_am62x_a53_defconfig | 7 ++++++- include/env/phytec/watchdog.env | 11 +++++++++++ 3 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 include/env/phytec/watchdog.env (limited to 'board') diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env index 797904013dc..3f4b3cc4f0d 100644 --- a/board/phytec/phycore_am62x/phycore_am62x.env +++ b/board/phytec/phycore_am62x/phycore_am62x.env @@ -2,6 +2,7 @@ #include #include #include +#include fdtaddr=0x88000000 loadaddr=0x82000000 @@ -27,3 +28,5 @@ spi_ramdisk_addr=0x2200000 bootmeths=script efi extlinux pxe boot_targets=mmc1 mmc0 spi_flash dhcp + +watchdog=watchdog@e000000 diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 978604b0232..931ec39905b 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -44,7 +44,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTCOMMAND="bootflow scan -lb; run ${boot}boot" +CONFIG_BOOTCOMMAND="run start_watchdog; bootflow scan -lb; run ${boot}boot" CONFIG_DEFAULT_FDT_FILE="oftree" # CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y @@ -79,6 +79,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_RTC=y @@ -175,5 +176,9 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_SPL_DFU=y +# CONFIG_WATCHDOG is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_K3_RTI=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 # CONFIG_HEXDUMP is not set diff --git a/include/env/phytec/watchdog.env b/include/env/phytec/watchdog.env new file mode 100644 index 00000000000..f2e65baf1e9 --- /dev/null +++ b/include/env/phytec/watchdog.env @@ -0,0 +1,11 @@ +watchdog_timeout_ms=CONFIG_WATCHDOG_TIMEOUT_MSECS +start_watchdog= + if test ${watchdog_timeout_ms} -gt 0; then; + if test -z "${watchdog}"; then; + echo No watchdog device set, skipping watchdog start; + else; + wdt dev ${watchdog}; + wdt start ${watchdog_timeout_ms}; + echo Watchdog started, timeout ${watchdog_timeout_ms} ms; + fi; + fi; -- cgit v1.3.1 From 9de098a9f85eaec64389fd7ea1848110e6da36f6 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 30 Jul 2025 17:42:15 +0200 Subject: board: phytec: phycore-am64x: Add watchdog start to bootcmd Allows run-time control over watchdog auto-start and the timeout via setting the environment variable watchdog_timeout_ms. A value of zero means "do not start". Use CONFIG_WATCHDOG_TIMEOUT_MSECS as initial value. Users can enable the watchdog to monitor the boot process until userspace or OS takes over to serve the watchdog. Signed-off-by: Wadim Egorov --- board/phytec/phycore_am64x/phycore_am64x.env | 3 +++ configs/phycore_am64x_a53_defconfig | 7 ++++++- 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/phytec/phycore_am64x/phycore_am64x.env b/board/phytec/phycore_am64x/phycore_am64x.env index 36ab16e2f7a..3775a27c1a3 100644 --- a/board/phytec/phycore_am64x/phycore_am64x.env +++ b/board/phytec/phycore_am64x/phycore_am64x.env @@ -1,6 +1,7 @@ #include #include #include +#include fdtaddr=0x88000000 loadaddr=0x82000000 @@ -26,3 +27,5 @@ spi_ramdisk_addr=0x2200000 bootmeths=script efi extlinux pxe boot_targets=mmc1 mmc0 spi_flash dhcp + +watchdog=watchdog@e000000 diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig index 62c9eec971d..cf1e9061f3c 100644 --- a/configs/phycore_am64x_a53_defconfig +++ b/configs/phycore_am64x_a53_defconfig @@ -39,7 +39,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTCOMMAND="bootflow scan -lb; run ${boot}boot" +CONFIG_BOOTCOMMAND="run start_watchdog; bootflow scan -lb; run ${boot}boot" CONFIG_DEFAULT_FDT_FILE="oftree" # CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y @@ -77,6 +77,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_RTC=y @@ -182,4 +183,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_MASS_STORAGE=y +# CONFIG_WATCHDOG is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_K3_RTI=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 -- cgit v1.3.1 From 58fa3b5159cf4090ed926507d7778ebd1dc0686f Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Thu, 7 Aug 2025 13:32:24 +0800 Subject: configs: npcm: remove CONFIG_SYS_SKIP_UART_INIT Set the uart clock frequency according to dts by default. If CONFIG_SYS_SKIP_UART_INIT is not enabled, no need to do board_set_console to change the console bootarg. Signed-off-by: Jim Liu --- board/nuvoton/arbel_evb/arbel_evb.c | 9 ++++++++- board/nuvoton/poleg_evb/poleg_evb.c | 2 ++ configs/arbel_evb_defconfig | 1 - configs/poleg_evb_defconfig | 1 - 4 files changed, 10 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c index 16dbaa96e8c..05c4dd187fe 100644 --- a/board/nuvoton/arbel_evb/arbel_evb.c +++ b/board/nuvoton/arbel_evb/arbel_evb.c @@ -94,5 +94,12 @@ int dram_init_banksize(void) return 0; } -EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, board_set_console); +static int last_stage_init(void) +{ +#ifdef CONFIG_SYS_SKIP_UART_INIT + return board_set_console(); +#endif + return 0; +} +EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init); diff --git a/board/nuvoton/poleg_evb/poleg_evb.c b/board/nuvoton/poleg_evb/poleg_evb.c index 0a3c052a019..9dfe9744363 100644 --- a/board/nuvoton/poleg_evb/poleg_evb.c +++ b/board/nuvoton/poleg_evb/poleg_evb.c @@ -64,7 +64,9 @@ static int last_stage_init(void) } sprintf(value, "ttyS%d,115200n8", dev->seq_); env_set("console", value); +#ifdef CONFIG_SYS_SKIP_UART_INIT return board_set_console(); +#endif } return 0; diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig index 8572ad204d8..11ad19f56db 100644 --- a/configs/arbel_evb_defconfig +++ b/configs/arbel_evb_defconfig @@ -17,7 +17,6 @@ CONFIG_SYS_LOAD_ADDR=0x06208000 CONFIG_WATCHDOG_TIMEOUT_MSECS=120000 # CONFIG_PSCI_RESET is not set CONFIG_ARCH_NPCM8XX=y -CONFIG_SYS_SKIP_UART_INIT=y CONFIG_TARGET_ARBEL_EVB=y CONFIG_ENV_ADDR=0x807C0000 # CONFIG_EFI_LOADER is not set diff --git a/configs/poleg_evb_defconfig b/configs/poleg_evb_defconfig index a87e918117c..0803fb1a857 100644 --- a/configs/poleg_evb_defconfig +++ b/configs/poleg_evb_defconfig @@ -16,7 +16,6 @@ CONFIG_DEFAULT_DEVICE_TREE="nuvoton-npcm750-evb" CONFIG_DM_RESET=y CONFIG_SYS_LOAD_ADDR=0x10000000 CONFIG_TARGET_POLEG=y -CONFIG_SYS_SKIP_UART_INIT=y CONFIG_ENV_ADDR=0x80100000 CONFIG_FIT=y CONFIG_USE_BOOTCOMMAND=y -- cgit v1.3.1 From 3bab8f17fb17c59f83ef409eb14b3aec92cd3f9b Mon Sep 17 00:00:00 2001 From: Andreas Dannenberg Date: Thu, 31 Jul 2025 13:29:46 +0530 Subject: board: ti: am62px: evm: Enable cache for AM62p Enable cache for AM62p to optimize performance of CPU to access data from memory. Reviewed-by: Alexander Sverdlin Signed-off-by: Andreas Dannenberg Signed-off-by: Chintan Vankar --- board/ti/am62px/evm.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'board') diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c index 2e85363cf5f..c06e3878d67 100644 --- a/board/ti/am62px/evm.c +++ b/board/ti/am62px/evm.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -41,6 +42,13 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; +#if IS_ENABLED(CONFIG_SPL_BUILD) +void spl_board_init(void) +{ + enable_caches(); +} +#endif + #if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { -- cgit v1.3.1 From 80b529d8776fe48eb595bc3eaf739751b5bea15c Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 31 Jul 2025 13:29:50 +0530 Subject: board: ti: j722s: evm: Enable cache for J722s Enable cache for J722s to optimize performance of CPU to access data from memory. Reviewed-by: Alexander Sverdlin Signed-off-by: Chintan Vankar --- board/ti/j722s/evm.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'board') diff --git a/board/ti/j722s/evm.c b/board/ti/j722s/evm.c index d2b94913c12..32d767cb7d2 100644 --- a/board/ti/j722s/evm.c +++ b/board/ti/j722s/evm.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -15,6 +16,13 @@ #include #include "../common/fdt_ops.h" +#if IS_ENABLED(CONFIG_SPL_BUILD) +void spl_board_init(void) +{ + enable_caches(); +} +#endif + #if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { -- cgit v1.3.1 From 29ce50acbb40d64aabf789640a2866a9f71aefa6 Mon Sep 17 00:00:00 2001 From: John Ma Date: Wed, 13 Aug 2025 14:31:16 -0700 Subject: board: phytec: common: k3: Making setup_mac_from_eeprom optional Making the setup_mac_from_eeprom optional for boards without CONFIG_PHYTEC_SOM_DETECTION_BLOCKS. Signed-off-by: John Ma Reviewed-by: Wadim Egorov --- board/phytec/common/k3/board.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c index 7f34d71d530..647f93a1d7a 100644 --- a/board/phytec/common/k3/board.c +++ b/board/phytec/common/k3/board.c @@ -176,6 +176,7 @@ static void boot_targets_setup(void) env_set("boot_targets", boot_targets); } +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS) static void setup_mac_from_eeprom(void) { struct phytec_api3_element *block_element; @@ -197,13 +198,15 @@ static void setup_mac_from_eeprom(void) } } } +#endif int board_late_init(void) { boot_targets_setup(); - if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)) - setup_mac_from_eeprom(); +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS) + setup_mac_from_eeprom(); +#endif #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) configure_capsule_updates(); -- cgit v1.3.1 From 51214ffcc543dde83ad687c35cb2de61a34e0602 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 14 Aug 2025 15:14:36 -0300 Subject: qemu_arm: Select CONFIG_SYS_EARLY_PCI_INIT Select CONFIG_SYS_EARLY_PCI_INIT so that eMMC emulation can work. Signed-off-by: Fabio Estevam Reviewed-by: Tom Rini Tested-by: Jan Kiszka --- board/emulation/qemu-arm/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'board') diff --git a/board/emulation/qemu-arm/Kconfig b/board/emulation/qemu-arm/Kconfig index 80ab9d8e1c3..447061b25cd 100644 --- a/board/emulation/qemu-arm/Kconfig +++ b/board/emulation/qemu-arm/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAS_CUSTOM_SYS_INIT_SP_ADDR select QFW if ACPI select QFW_MMIO if CMD_QFW + imply SYS_EARLY_PCI_INIT imply VIRTIO_MMIO imply VIRTIO_PCI imply VIRTIO_NET -- cgit v1.3.1 From 1fa340932946b337c7fd58cf8f825bb0c95f3e95 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 22 Jul 2025 10:15:05 +0200 Subject: xilinx: Make XILINX_OF_BOARD_DTB_ADDR depending on OF_BOARD only board_fdt_blob_setup() is guarded by OF_BOARD already that's why make no sense to depend also on OF_SEPARATE. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/063b2e618afb05a32d66218f3631a5f23b30ea3e.1753172103.git.michal.simek@amd.com --- board/xilinx/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index f7152d6ee6d..5c3240da073 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -55,7 +55,7 @@ config XILINX_OF_BOARD_DTB_ADDR default 0x8000 if MICROBLAZE default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP default 0x83000000 if TARGET_XILINX_MBV - depends on OF_BOARD || OF_SEPARATE + depends on OF_BOARD help Offset in the memory where the board configuration DTB is placed. -- cgit v1.3.1 From 88a1816a9b4ef6a202a832c7f59099ddae903e6b Mon Sep 17 00:00:00 2001 From: Dominik Haller Date: Fri, 15 Aug 2025 13:10:48 +0200 Subject: board: phytec: common: Add PHYTEC_EEPROM_BUS to Kconfig Add the option to choose a different bus number than 0 for the i2c eeprom based som detection. Signed-off-by: Dominik Haller Signed-off-by: Wadim Egorov --- board/phytec/common/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'board') diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index 65451a3b20d..08d6e5f3683 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -59,3 +59,9 @@ config PHYTEC_AM64_SOM_DETECTION help Support of I2C EEPROM based SoM detection. Supported for PHYTEC AM64x boards. + +config PHYTEC_EEPROM_BUS + int "Board EEPROM's I2C bus number" + range 0 8 + default 0 + depends on PHYTEC_SOM_DETECTION -- cgit v1.3.1 From 437f663e6c35bb210a115bbbd295efbd9d9c54a1 Mon Sep 17 00:00:00 2001 From: Dominik Haller Date: Fri, 15 Aug 2025 13:10:49 +0200 Subject: board: phytec: common: k3: Use CONFIG_PHYTEC_EEPROM_BUS Use CONFIG_PHYTEC_EEPROM_BUS instead of the hard coded value for the i2c bus. Signed-off-by: Dominik Haller Signed-off-by: Wadim Egorov --- board/phytec/common/k3/board.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c index 7f34d71d530..50d4a7c0d27 100644 --- a/board/phytec/common/k3/board.c +++ b/board/phytec/common/k3/board.c @@ -182,7 +182,7 @@ static void setup_mac_from_eeprom(void) struct phytec_eeprom_data data; int ret; - ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + ret = phytec_eeprom_data_setup(&data, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); if (ret || !data.valid) return; @@ -245,7 +245,7 @@ static void fdt_apply_som_overlays(void *blob) memcpy(fdt_copy, blob, fdt_size); - err = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + err = phytec_eeprom_data_setup(&data, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); if (err) goto fixup_error; @@ -292,7 +292,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_apply_som_overlays(blob); fdt_copy_fixed_partitions(blob); - ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + ret = phytec_eeprom_data_setup(&data, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); if (ret || !data.valid) return 0; -- cgit v1.3.1 From 9cf4f522fc96e29df4ab23f5bcbbbe432ae32237 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Fri, 15 Aug 2025 13:10:50 +0200 Subject: board: phytec: phycore-am62a: Update SoM detection Kconfig options Drop SUPPORT_EXTENSION_SCAN and enable PHYTEC_SOM_DETECTION_BLOCKS to align with other PHYTEC platforms. These options were missed when phyCORE-AM62Ax support was added. Signed-off-by: Wadim Egorov --- board/phytec/common/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index 08d6e5f3683..a72f66ee3f5 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -42,7 +42,7 @@ config PHYTEC_AM62A_SOM_DETECTION bool "Support SoM detection for AM62Ax PHYTEC platforms" depends on (TARGET_PHYCORE_AM62AX_A53 || TARGET_PHYCORE_AM62AX_R5) && \ PHYTEC_SOM_DETECTION - select SUPPORT_EXTENSION_SCAN + select PHYTEC_SOM_DETECTION_BLOCKS depends on SPL_I2C && DM_I2C default y help -- cgit v1.3.1 From a65798ddbb88b06539e2a109d686edd3fb3a8173 Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Fri, 22 Aug 2025 20:33:33 +0200 Subject: board: samsung: odroid: drop exynos_power_init exynos_power_init sets up regulators for the emmc and sdcard, but these regulators are already marked as always-on and boot-on and hence are handled already by the regulator-uclass. Since we currently try to set them up twice we get error -114 (EALREADY) from exynos_power_init on every boot: LDO20@VDDQ_EMMC_1.8V: set 1800000 uV; enabling (ret: -114) LDO22@VDDQ_EMMC_2.8V: set 2800000 uV; enabling (ret: -114) LDO21@TFLASH_2.8V: set 2800000 uV; enabling (ret: -114) Remove the superfluous exynos_power_init to silence these errors. Signed-off-by: Henrik Grimler Reviewed-by: Anand Moon Signed-off-by: Peng Fan --- board/samsung/odroid/odroid.c | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'board') diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 84d6d919f07..a48b8e94b77 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -428,21 +428,6 @@ void exynos_init(void) board_gpio_init(); } -int exynos_power_init(void) -{ - const char *mmc_regulators[] = { - "VDDQ_EMMC_1.8V", - "VDDQ_EMMC_2.8V", - "TFLASH_2.8V", - NULL, - }; - - if (regulator_list_autoset(mmc_regulators, NULL, true)) - pr_err("Unable to init all mmc regulators\n"); - - return 0; -} - #ifdef CONFIG_USB_GADGET static int s5pc210_phy_control(int on) { -- cgit v1.3.1 From eb314cb566abe0c6eb675c9c857a0cd1bb8c5cf9 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 25 Aug 2025 15:54:25 +0200 Subject: imx: kontron-sl-mx6ul: Fix include statements for local header The header from the local directory should use double quotes instead of brackets. Otherwise the compiler might not search the local directory. Fixes: 93935acc6f1d ("imx: imx6ul: kontron-sl-mx6ul: Select correct boot and env device") Signed-off-by: Frieder Schrempf --- board/kontron/sl-mx6ul/sl-mx6ul-common.c | 2 +- board/kontron/sl-mx6ul/sl-mx6ul.c | 3 ++- board/kontron/sl-mx6ul/spl.c | 3 ++- 3 files changed, 5 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/kontron/sl-mx6ul/sl-mx6ul-common.c b/board/kontron/sl-mx6ul/sl-mx6ul-common.c index 1f24acdfa3d..bda71a330ca 100644 --- a/board/kontron/sl-mx6ul/sl-mx6ul-common.c +++ b/board/kontron/sl-mx6ul/sl-mx6ul-common.c @@ -6,7 +6,7 @@ #include #include -#include +#include "sl-mx6ul-common.h" bool sl_mx6ul_is_spi_nor_boot(void) { diff --git a/board/kontron/sl-mx6ul/sl-mx6ul.c b/board/kontron/sl-mx6ul/sl-mx6ul.c index 0f45ea84fc7..16d89c64d61 100644 --- a/board/kontron/sl-mx6ul/sl-mx6ul.c +++ b/board/kontron/sl-mx6ul/sl-mx6ul.c @@ -9,7 +9,8 @@ #include #include #include -#include + +#include "sl-mx6ul-common.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/kontron/sl-mx6ul/spl.c b/board/kontron/sl-mx6ul/spl.c index 33e5337bcbc..8d55273dd9c 100644 --- a/board/kontron/sl-mx6ul/spl.c +++ b/board/kontron/sl-mx6ul/spl.c @@ -18,7 +18,8 @@ #include #include #include -#include + +#include "sl-mx6ul-common.h" DECLARE_GLOBAL_DATA_PTR; -- cgit v1.3.1 From 410d9ccc0388b77b1e21ba218b2e21138930c90f Mon Sep 17 00:00:00 2001 From: Annette Kobou Date: Mon, 25 Aug 2025 15:54:31 +0200 Subject: imx: kontron-sl-mx6ul: Autostart fastboot if booted from USB For booting via USB we want to automatically start the fastboot command in order to access the board via uuu or other tools. This allows for easier bringup of new boards during development and manufacturing. Signed-off-by: Annette Kobou Signed-off-by: Frieder Schrempf --- board/kontron/sl-mx6ul/sl-mx6ul.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'board') diff --git a/board/kontron/sl-mx6ul/sl-mx6ul.c b/board/kontron/sl-mx6ul/sl-mx6ul.c index 16d89c64d61..e33907ee124 100644 --- a/board/kontron/sl-mx6ul/sl-mx6ul.c +++ b/board/kontron/sl-mx6ul/sl-mx6ul.c @@ -5,7 +5,9 @@ #include #include +#include #include +#include #include #include #include @@ -87,6 +89,16 @@ int board_init(void) return 0; } +int board_late_init(void) +{ + if (is_boot_from_usb()) { + env_set("bootdelay", "0"); + env_set("bootcmd", "fastboot 0"); + } + + return 0; +} + enum env_location env_get_location(enum env_operation op, int prio) { if (prio) -- cgit v1.3.1 From 6bfd81c3394cfa02d9e5d45e8ad4ca8634b177fe Mon Sep 17 00:00:00 2001 From: Eberhard Stoll Date: Mon, 25 Aug 2025 15:54:34 +0200 Subject: imx: kontron-sl-mx6ul: Force default environment for serial loader boot In case of booting from serial loader (USB) we want to always use the default environment in order to get a defined state that is independent of any environment stored in persistent memory. This way we can avoid corruption of the boot process during development and manufacturing by existing environment settings in flash. Signed-off-by: Eberhard Stoll Signed-off-by: Frieder Schrempf --- board/kontron/sl-mx6ul/sl-mx6ul.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/kontron/sl-mx6ul/sl-mx6ul.c b/board/kontron/sl-mx6ul/sl-mx6ul.c index e33907ee124..65f9b75c1a0 100644 --- a/board/kontron/sl-mx6ul/sl-mx6ul.c +++ b/board/kontron/sl-mx6ul/sl-mx6ul.c @@ -104,10 +104,16 @@ enum env_location env_get_location(enum env_operation op, int prio) if (prio) return ENVL_UNKNOWN; + if (CONFIG_IS_ENABLED(ENV_IS_NOWHERE) && is_boot_from_usb()) + return ENVL_NOWHERE; + if (sl_mx6ul_is_spi_nor_boot() && CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH)) return ENVL_SPI_FLASH; else if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC)) return ENVL_MMC; - return ENVL_NOWHERE; + if (CONFIG_IS_ENABLED(ENV_IS_NOWHERE)) + return ENVL_NOWHERE; + + return ENVL_UNKNOWN; } -- cgit v1.3.1 From b4ab315a0a5c32607d0d12734d0d3cb03d813e8b Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Thu, 28 Aug 2025 10:20:08 +0200 Subject: board: phytec: phycore-imx93: Use CONFIG_PHYTEC_EEPROM_BUS Switch to use CONFIG_PHYTEC_EEPROM_BUS instead of the hard coded value of 2 for the EEPROM I2C bus for both SPL and U-Boot proper. Possible since commit 88a1816a9b4e ("board: phytec: common: Add PHYTEC_EEPROM_BUS to Kconfig"). Signed-off-by: Primoz Fiser Reviewed-by: Wadim Egorov --- board/phytec/phycore_imx93/phycore-imx93.c | 2 +- board/phytec/phycore_imx93/spl.c | 2 +- configs/imx93-phycore_defconfig | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx93/phycore-imx93.c index fab66caf2a1..c6a4e923b07 100644 --- a/board/phytec/phycore_imx93/phycore-imx93.c +++ b/board/phytec/phycore_imx93/phycore-imx93.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - int ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR); + int ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); if (ret) printf("%s: EEPROM data init failed\n", __func__); diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c index beaa536c600..7feee4bcf6f 100644 --- a/board/phytec/phycore_imx93/spl.c +++ b/board/phytec/phycore_imx93/spl.c @@ -52,7 +52,7 @@ void spl_dram_init(void) int ret; enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID; - ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR); + ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) goto out; diff --git a/configs/imx93-phycore_defconfig b/configs/imx93-phycore_defconfig index 53cd28dfcba..0acdfd2bf53 100644 --- a/configs/imx93-phycore_defconfig +++ b/configs/imx93-phycore_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_PHYTEC_SOM_DETECTION=y +CONFIG_PHYTEC_EEPROM_BUS=2 CONFIG_ENV_SOURCE_FILE="phycore_imx93" CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x700000 -- cgit v1.3.1 From 28d6f787b0deb3f66118857297a855233eba18d1 Mon Sep 17 00:00:00 2001 From: Benjamin Hahn Date: Tue, 2 Sep 2025 08:07:32 +0200 Subject: Add imx8mp-libra-fpsc board Add new imx8mp-libra-fpsc board. Bootph tags as well as USB device tree nodes are in u-boot.dtsi for now and will be removed when upstreamed. The Libra i.MX 8M Plus FPSC is a single board computer. It uses an i.MX 8M Plus FPSC [1] System on Module which utilizes the FPSC standard [2]. [1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-8m-plus-fpsc [2] https://www.phytec.eu/en/produkte/system-on-modules/fpsc Signed-off-by: Benjamin Hahn Reviewed-by: Teresa Remmet Tested-by: Teresa Remmet Signed-off-by: Yannic Moog --- arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi | 131 ++ arch/arm/mach-imx/imx8m/Kconfig | 10 + board/phytec/imx8mp-libra-fpsc/Kconfig | 16 + board/phytec/imx8mp-libra-fpsc/MAINTAINERS | 9 + board/phytec/imx8mp-libra-fpsc/Makefile | 10 + board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c | 89 + .../phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env | 19 + board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg | 9 + board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c | 1813 ++++++++++++++++++++ board/phytec/imx8mp-libra-fpsc/spl.c | 132 ++ configs/imx8mp-libra-fpsc_defconfig | 175 ++ doc/board/phytec/imx8mp-libra-fpsc.rst | 83 + doc/board/phytec/index.rst | 1 + include/configs/imx8mp-libra-fpsc.h | 27 + 14 files changed, 2524 insertions(+) create mode 100644 arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi create mode 100644 board/phytec/imx8mp-libra-fpsc/Kconfig create mode 100644 board/phytec/imx8mp-libra-fpsc/MAINTAINERS create mode 100644 board/phytec/imx8mp-libra-fpsc/Makefile create mode 100644 board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c create mode 100644 board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env create mode 100644 board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg create mode 100644 board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c create mode 100644 board/phytec/imx8mp-libra-fpsc/spl.c create mode 100644 configs/imx8mp-libra-fpsc_defconfig create mode 100644 doc/board/phytec/imx8mp-libra-fpsc.rst create mode 100644 include/configs/imx8mp-libra-fpsc.h (limited to 'board') diff --git a/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi new file mode 100644 index 00000000000..1320f1540ed --- /dev/null +++ b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include "imx8mp-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; + + bootstd { + bootph-verify; + compatible = "u-boot,boot-std"; + + filename-prefixes = "/", "/boot/"; + bootdev-order = "mmc2", "mmc1", "ethernet"; + + efi { + compatible = "u-boot,distro-efi"; + }; + + rauc { + compatible = "u-boot,distro-rauc"; + }; + + script { + compatible = "u-boot,script"; + }; + }; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart4 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc3 { + bootph-pre-ram; +}; + +&pinctrl_wdog { + bootph-pre-ram; +}; + +&gpio1 { + bootph-pre-ram; +}; + +&gpio2 { + bootph-pre-ram; +}; + +&gpio3 { + bootph-pre-ram; +}; + +&gpio4 { + bootph-pre-ram; +}; + +&gpio5 { + bootph-pre-ram; +}; + +&uart4 { + bootph-pre-ram; +}; + +&i2c1 { + bootph-pre-ram; +}; + +&pmic { + bootph-pre-ram; +}; + +/* USB1 Type-C */ +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + fsl,over-current-active-low; + fsl,power-active-low; + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +/* USB2 4-port USB3.0 HUB */ +&usb3_phy1 { + vbus-supply = <®_vdd_5v0>; + status = "okay"; +}; + +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + bootph-pre-ram; +}; + +&usdhc3 { + bootph-pre-ram; +}; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 74416a78847..e7bc154b805 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -345,6 +345,15 @@ config TARGET_PHYCORE_IMX8MP select IMX8M_LPDDR4 imply OF_UPSTREAM +config TARGET_IMX8MP_LIBRA_FPSC + bool "PHYTEC Libra i.MX 8M Plus FPSC" + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + imply OF_UPSTREAM + help + Libra i.MX8M Plus FPSC is an SBC based on the NXP i.MX 8M Plus SoC. + config TARGET_IMX8MM_CL_IOT_GATE bool "CompuLab iot-gate-imx8" select IMX8MM @@ -409,6 +418,7 @@ source "board/kontron/sl-mx8mm/Kconfig" source "board/menlo/mx8menlo/Kconfig" source "board/msc/sm2s_imx8mp/Kconfig" source "board/mntre/imx8mq_reform2/Kconfig" +source "board/phytec/imx8mp-libra-fpsc/Kconfig" source "board/phytec/phycore_imx8mm/Kconfig" source "board/phytec/phycore_imx8mp/Kconfig" source "board/polyhex/imx8mp_debix_model_a/Kconfig" diff --git a/board/phytec/imx8mp-libra-fpsc/Kconfig b/board/phytec/imx8mp-libra-fpsc/Kconfig new file mode 100644 index 00000000000..4961611f7b2 --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/Kconfig @@ -0,0 +1,16 @@ +if TARGET_IMX8MP_LIBRA_FPSC + +config SYS_BOARD + default "imx8mp-libra-fpsc" + +config SYS_VENDOR + default "phytec" + +config IMX_CONFIG + default "board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg" + +config SYS_CONFIG_NAME + default "imx8mp-libra-fpsc" + +source "board/phytec/common/Kconfig" +endif diff --git a/board/phytec/imx8mp-libra-fpsc/MAINTAINERS b/board/phytec/imx8mp-libra-fpsc/MAINTAINERS new file mode 100644 index 00000000000..1fd99888a2e --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/MAINTAINERS @@ -0,0 +1,9 @@ +Libra-i.MX 8M Plus +M: Teresa Remmet +W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-8m-plus-fpsc/ +S: Maintained +F: arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi +F: board/phytec/imx8mp-libra-fpsc/ +F: configs/imx8mp-libra-fpsc_defconfig +F: include/configs/imx8mp-libra-fpsc.h +F: doc/board/phytec/imx8mp-libra-fpsc.rst diff --git a/board/phytec/imx8mp-libra-fpsc/Makefile b/board/phytec/imx8mp-libra-fpsc/Makefile new file mode 100644 index 00000000000..21b35d9142f --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (C) 2025 PHYTEC Messtechnik GmbH + +obj-y += imx8mp-libra-fpsc.o + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +endif diff --git a/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c new file mode 100644 index 00000000000..ffa21da1b34 --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EEPROM_ADDR 0x51 + +#define TUSB_PORT_POL_CRTL_REG 0xB +#define TUSB_CUSTOM_POL BIT(7) +#define TUSB_P0_POL BIT(0) + +/* + * WORKAROUND for PCM-937-L 1618.0, 1618.1. + * USB HUB TUSB8042A has swapped upstream pin polarity. + * Set i2c registers to inform the hub that the lines + * are swapped. + */ +void tusb8042a_swap_lines(void) +{ + const u8 pol_swap_val = (TUSB_CUSTOM_POL | TUSB_P0_POL); + const int addr = 0x44; + struct udevice *dev = 0; + int ret = i2c_get_chip_for_busnum(2, addr, 1, &dev); + + if (!ret) + dm_i2c_write(dev, TUSB_PORT_POL_CRTL_REG, &pol_swap_val, 1); + else + printf("TUSB8042A: Failed to fixup USB HUB.\n"); +} + +int board_init(void) +{ + tusb8042a_swap_lines(); + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ + switch (get_boot_device()) { + case SD2_BOOT: + env_set_ulong("mmcdev", 1); + if (!strcmp(env_get("boot_targets"), env_get_default("boot_targets"))) + env_set("boot_targets", "mmc1 mmc2 ethernet"); + break; + case MMC3_BOOT: + env_set_ulong("mmcdev", 2); + break; + case USB_BOOT: + printf("Detect USB boot. Will enter fastboot mode!\n"); + if (!strcmp(env_get("bootcmd"), env_get_default("bootcmd"))) + env_set("bootcmd", "fastboot 0; bootflow scan -lb;"); + break; + default: + break; + } + + return 0; +} + +int board_phys_sdram_size(phys_size_t *size) +{ + if (!size) + return -EINVAL; + + *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE); + + return 0; +} diff --git a/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env new file mode 100644 index 00000000000..c744248ab7a --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env @@ -0,0 +1,19 @@ +boot_script_dhcp=boot.scr.uimg +console=ttymxc3,CONFIG_BAUDRATE +emmc_dev=2 /* This is needed by built-in uuu flash scripts */ +fdtfile=CONFIG_DEFAULT_FDT_FILE +fdt_addr_r=0x40480000 +fdt_overlay_addr_r=0x404a0000 +fit_fdtconf=conf-imx8mp-libra-rdk-fpsc.dtb +kernel_addr_r=0x40a00000 +kernel_comp_addr_r=0x43a00000 +kernel_comp_size=0x1e00000 +mmcroot=2 +pxefile_addr_r=0x45800000 +ramdisk_addr_r=0x45802000 +scriptaddr=0x47600000 +script_offset_f=0x0 +script_size_f=0x2000 +sd_dev=1 /* This is needed by built-in uuu flash scripts */ +ip_dyn=yes +nfsroot=/srv/nfs diff --git a/board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg b/board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg new file mode 100644 index 00000000000..6dedf1724ab --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + + +ROM_VERSION v2 +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x920000 diff --git a/board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c b/board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c new file mode 100644 index 00000000000..1b501828726 --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c @@ -0,0 +1,1813 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 NXP + * + * Code generated with DDR Tool v3.5.0_9-1ddf053d. + * DDR PHY FW2020.06 + */ + +#include +#include + +/* Initialize DDRC registers */ +struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x3d400304, 0x1}, + {0x3d400030, 0x1}, + {0x3d400000, 0xa1080020}, + {0x3d400020, 0x1323}, + {0x3d400024, 0x1e84800}, + {0x3d400064, 0x7a0118}, + {0x3d400070, 0x7027f90}, + {0x3d400074, 0x790}, + {0x3d4000d0, 0xc00307a3}, + {0x3d4000d4, 0xc50000}, + {0x3d4000dc, 0xf4003f}, + {0x3d4000e0, 0xe30000}, + {0x3d4000e8, 0x440048}, + {0x3d4000ec, 0x140048}, + {0x3d400100, 0x2028222a}, + {0x3d400104, 0x8083f}, + {0x3d40010c, 0xe0e000}, + {0x3d400110, 0x12040a12}, + {0x3d400114, 0x2050f0f}, + {0x3d400118, 0x1010009}, + {0x3d40011c, 0x502}, + {0x3d400130, 0x20800}, + {0x3d400134, 0xe100002}, + {0x3d400138, 0x120}, + {0x3d400144, 0xc80064}, + {0x3d400180, 0x3e8001e}, + {0x3d400184, 0x3207a12}, + {0x3d400188, 0x0}, + {0x3d400190, 0x4a3820e}, + {0x3d400194, 0x80303}, + {0x3d4001b4, 0x230e}, + {0x3d4001a0, 0xe0400018}, + {0x3d4001a4, 0xdf00e4}, + {0x3d4001a8, 0x80000000}, + {0x3d4001b0, 0x11}, + {0x3d4001c0, 0x7}, + {0x3d4001c4, 0x1}, + {0x3d4000f4, 0x799}, + {0x3d400108, 0x9141d1c}, + {0x3d400200, 0x1f}, + {0x3d400208, 0x0}, + {0x3d40020c, 0x0}, + {0x3d400210, 0x1f1f}, + {0x3d400204, 0x80808}, + {0x3d400214, 0x7070707}, + {0x3d400218, 0x7070707}, + {0x3d40021c, 0xf0f}, + {0x3d400250, 0x1705}, + {0x3d400254, 0x2c}, + {0x3d40025c, 0x4000030}, + {0x3d400264, 0x900093e7}, + {0x3d40026c, 0x2005574}, + {0x3d400400, 0x111}, + {0x3d400404, 0x72ff}, + {0x3d400408, 0x72ff}, + {0x3d400494, 0x2100e07}, + {0x3d400498, 0x620096}, + {0x3d40049c, 0x1100e07}, + {0x3d4004a0, 0xc8012c}, + {0x3d400028, 0x0}, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x0}, + {0x100a1, 0x1}, + {0x100a2, 0x2}, + {0x100a3, 0x3}, + {0x100a4, 0x4}, + {0x100a5, 0x5}, + {0x100a6, 0x6}, + {0x100a7, 0x7}, + {0x110a0, 0x0}, + {0x110a1, 0x1}, + {0x110a2, 0x3}, + {0x110a3, 0x4}, + {0x110a4, 0x5}, + {0x110a5, 0x2}, + {0x110a6, 0x7}, + {0x110a7, 0x6}, + {0x120a0, 0x0}, + {0x120a1, 0x1}, + {0x120a2, 0x3}, + {0x120a3, 0x2}, + {0x120a4, 0x5}, + {0x120a5, 0x4}, + {0x120a6, 0x7}, + {0x120a7, 0x6}, + {0x130a0, 0x0}, + {0x130a1, 0x1}, + {0x130a2, 0x2}, + {0x130a3, 0x3}, + {0x130a4, 0x4}, + {0x130a5, 0x5}, + {0x130a6, 0x6}, + {0x130a7, 0x7}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x1205f, 0x1ff}, + {0x1215f, 0x1ff}, + {0x1305f, 0x1ff}, + {0x1315f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x3055, 0x1ff}, + {0x4055, 0x1ff}, + {0x5055, 0x1ff}, + {0x6055, 0x1ff}, + {0x7055, 0x1ff}, + {0x8055, 0x1ff}, + {0x9055, 0x1ff}, + {0x200c5, 0x18}, + {0x2002e, 0x2}, + {0x90204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x20056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x1204d, 0x600}, + {0x1214d, 0x600}, + {0x1304d, 0x600}, + {0x1314d, 0x600}, + {0x10049, 0x618}, + {0x10149, 0x618}, + {0x11049, 0x618}, + {0x11149, 0x618}, + {0x12049, 0x618}, + {0x12149, 0x618}, + {0x13049, 0x618}, + {0x13149, 0x618}, + {0x43, 0x21}, + {0x1043, 0x21}, + {0x2043, 0x21}, + {0x3043, 0x21}, + {0x4043, 0x21}, + {0x5043, 0x21}, + {0x6043, 0x21}, + {0x7043, 0x21}, + {0x8043, 0x21}, + {0x9043, 0x21}, + {0x20018, 0x3}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x20008, 0x3e8}, + {0x20088, 0x9}, + {0x200b2, 0xdc}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x12043, 0x5a1}, + {0x12143, 0x5a1}, + {0x13043, 0x5a1}, + {0x13143, 0x5a1}, + {0x200fa, 0x1}, + {0x20019, 0x1}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5555}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x20025, 0x0}, + {0x2002d, 0x1}, + {0x2002c, 0x0}, +}; + +/* PHY trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x1205f, 0x0}, + {0x1215f, 0x0}, + {0x1305f, 0x0}, + {0x1315f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x3055, 0x0}, + {0x4055, 0x0}, + {0x5055, 0x0}, + {0x6055, 0x0}, + {0x7055, 0x0}, + {0x8055, 0x0}, + {0x9055, 0x0}, + {0x200c5, 0x0}, + {0x2002e, 0x0}, + {0x90204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x20056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x1204d, 0x0}, + {0x1214d, 0x0}, + {0x1304d, 0x0}, + {0x1314d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x12049, 0x0}, + {0x12149, 0x0}, + {0x13049, 0x0}, + {0x13149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x3043, 0x0}, + {0x4043, 0x0}, + {0x5043, 0x0}, + {0x6043, 0x0}, + {0x7043, 0x0}, + {0x8043, 0x0}, + {0x9043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x20008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x12043, 0x0}, + {0x12143, 0x0}, + {0x13043, 0x0}, + {0x13143, 0x0}, + {0x200fa, 0x0}, + {0x20019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x400fd, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x12011, 0x0}, + {0x12012, 0x0}, + {0x12013, 0x0}, + {0x12018, 0x0}, + {0x12002, 0x0}, + {0x120b2, 0x0}, + {0x121b4, 0x0}, + {0x122b4, 0x0}, + {0x123b4, 0x0}, + {0x124b4, 0x0}, + {0x125b4, 0x0}, + {0x126b4, 0x0}, + {0x127b4, 0x0}, + {0x128b4, 0x0}, + {0x13011, 0x0}, + {0x13012, 0x0}, + {0x13013, 0x0}, + {0x13018, 0x0}, + {0x13002, 0x0}, + {0x130b2, 0x0}, + {0x131b4, 0x0}, + {0x132b4, 0x0}, + {0x133b4, 0x0}, + {0x134b4, 0x0}, + {0x135b4, 0x0}, + {0x136b4, 0x0}, + {0x137b4, 0x0}, + {0x138b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x12068, 0x0}, + {0x12069, 0x0}, + {0x12168, 0x0}, + {0x12169, 0x0}, + {0x12268, 0x0}, + {0x12269, 0x0}, + {0x12368, 0x0}, + {0x12369, 0x0}, + {0x12468, 0x0}, + {0x12469, 0x0}, + {0x12568, 0x0}, + {0x12569, 0x0}, + {0x12668, 0x0}, + {0x12669, 0x0}, + {0x12768, 0x0}, + {0x12769, 0x0}, + {0x12868, 0x0}, + {0x12869, 0x0}, + {0x120aa, 0x0}, + {0x12062, 0x0}, + {0x12001, 0x0}, + {0x120a0, 0x0}, + {0x120a1, 0x0}, + {0x120a2, 0x0}, + {0x120a3, 0x0}, + {0x120a4, 0x0}, + {0x120a5, 0x0}, + {0x120a6, 0x0}, + {0x120a7, 0x0}, + {0x13068, 0x0}, + {0x13069, 0x0}, + {0x13168, 0x0}, + {0x13169, 0x0}, + {0x13268, 0x0}, + {0x13269, 0x0}, + {0x13368, 0x0}, + {0x13369, 0x0}, + {0x13468, 0x0}, + {0x13469, 0x0}, + {0x13568, 0x0}, + {0x13569, 0x0}, + {0x13668, 0x0}, + {0x13669, 0x0}, + {0x13768, 0x0}, + {0x13769, 0x0}, + {0x13868, 0x0}, + {0x13869, 0x0}, + {0x130aa, 0x0}, + {0x13062, 0x0}, + {0x13001, 0x0}, + {0x130a0, 0x0}, + {0x130a1, 0x0}, + {0x130a2, 0x0}, + {0x130a3, 0x0}, + {0x130a4, 0x0}, + {0x130a5, 0x0}, + {0x130a6, 0x0}, + {0x130a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x3080, 0x0}, + {0x4080, 0x0}, + {0x5080, 0x0}, + {0x6080, 0x0}, + {0x7080, 0x0}, + {0x8080, 0x0}, + {0x9080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x12020, 0x0}, + {0x12080, 0x0}, + {0x12081, 0x0}, + {0x120d0, 0x0}, + {0x120d1, 0x0}, + {0x1208c, 0x0}, + {0x1208d, 0x0}, + {0x12180, 0x0}, + {0x12181, 0x0}, + {0x121d0, 0x0}, + {0x121d1, 0x0}, + {0x1218c, 0x0}, + {0x1218d, 0x0}, + {0x120c0, 0x0}, + {0x120c1, 0x0}, + {0x121c0, 0x0}, + {0x121c1, 0x0}, + {0x122c0, 0x0}, + {0x122c1, 0x0}, + {0x123c0, 0x0}, + {0x123c1, 0x0}, + {0x124c0, 0x0}, + {0x124c1, 0x0}, + {0x125c0, 0x0}, + {0x125c1, 0x0}, + {0x126c0, 0x0}, + {0x126c1, 0x0}, + {0x127c0, 0x0}, + {0x127c1, 0x0}, + {0x128c0, 0x0}, + {0x128c1, 0x0}, + {0x120ae, 0x0}, + {0x120af, 0x0}, + {0x13020, 0x0}, + {0x13080, 0x0}, + {0x13081, 0x0}, + {0x130d0, 0x0}, + {0x130d1, 0x0}, + {0x1308c, 0x0}, + {0x1308d, 0x0}, + {0x13180, 0x0}, + {0x13181, 0x0}, + {0x131d0, 0x0}, + {0x131d1, 0x0}, + {0x1318c, 0x0}, + {0x1318d, 0x0}, + {0x130c0, 0x0}, + {0x130c1, 0x0}, + {0x131c0, 0x0}, + {0x131c1, 0x0}, + {0x132c0, 0x0}, + {0x132c1, 0x0}, + {0x133c0, 0x0}, + {0x133c1, 0x0}, + {0x134c0, 0x0}, + {0x134c1, 0x0}, + {0x135c0, 0x0}, + {0x135c1, 0x0}, + {0x136c0, 0x0}, + {0x136c1, 0x0}, + {0x137c0, 0x0}, + {0x137c1, 0x0}, + {0x138c0, 0x0}, + {0x138c1, 0x0}, + {0x130ae, 0x0}, + {0x130af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, + {0x12040, 0x0}, + {0x12140, 0x0}, + {0x12240, 0x0}, + {0x12340, 0x0}, + {0x12440, 0x0}, + {0x12540, 0x0}, + {0x12640, 0x0}, + {0x12740, 0x0}, + {0x12840, 0x0}, + {0x13040, 0x0}, + {0x13140, 0x0}, + {0x13240, 0x0}, + {0x13340, 0x0}, + {0x13440, 0x0}, + {0x13540, 0x0}, + {0x13640, 0x0}, + {0x13740, 0x0}, + {0x13840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xfa0}, + {0x54004, 0x2}, + {0x54005, 0x3c3c}, + {0x54006, 0x11}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x3ff4}, + {0x5401a, 0xe3}, + {0x5401b, 0x4844}, + {0x5401c, 0x4800}, + {0x5401e, 0x14}, + {0x5401f, 0x3ff4}, + {0x54020, 0xe3}, + {0x54021, 0x4844}, + {0x54022, 0x4800}, + {0x54024, 0x14}, + {0x5402b, 0x1000}, + {0x5402c, 0x1}, + {0x54032, 0xf400}, + {0x54033, 0xe33f}, + {0x54034, 0x4400}, + {0x54035, 0x48}, + {0x54036, 0x48}, + {0x54037, 0x1400}, + {0x54038, 0xf400}, + {0x54039, 0xe33f}, + {0x5403a, 0x4400}, + {0x5403b, 0x48}, + {0x5403c, 0x48}, + {0x5403d, 0x1400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xfa0}, + {0x54004, 0x2}, + {0x54005, 0x3c3c}, + {0x54006, 0x11}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400f, 0x100}, + {0x54010, 0x1f7f}, + {0x54012, 0x110}, + {0x54019, 0x3ff4}, + {0x5401a, 0xe3}, + {0x5401b, 0x4844}, + {0x5401c, 0x4800}, + {0x5401e, 0x14}, + {0x5401f, 0x3ff4}, + {0x54020, 0xe3}, + {0x54021, 0x4844}, + {0x54022, 0x4800}, + {0x54024, 0x14}, + {0x5402b, 0x1000}, + {0x5402c, 0x1}, + {0x54032, 0xf400}, + {0x54033, 0xe33f}, + {0x54034, 0x4400}, + {0x54035, 0x48}, + {0x54036, 0x48}, + {0x54037, 0x1400}, + {0x54038, 0xf400}, + {0x54039, 0xe33f}, + {0x5403a, 0x4400}, + {0x5403b, 0x48}, + {0x5403c, 0x48}, + {0x5403d, 0x1400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x0}, + {0x90051, 0x45a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x448}, + {0x90055, 0x109}, + {0x90056, 0x40}, + {0x90057, 0x633}, + {0x90058, 0x179}, + {0x90059, 0x1}, + {0x9005a, 0x618}, + {0x9005b, 0x109}, + {0x9005c, 0x40c0}, + {0x9005d, 0x633}, + {0x9005e, 0x149}, + {0x9005f, 0x8}, + {0x90060, 0x4}, + {0x90061, 0x48}, + {0x90062, 0x4040}, + {0x90063, 0x633}, + {0x90064, 0x149}, + {0x90065, 0x0}, + {0x90066, 0x4}, + {0x90067, 0x48}, + {0x90068, 0x40}, + {0x90069, 0x633}, + {0x9006a, 0x149}, + {0x9006b, 0x10}, + {0x9006c, 0x4}, + {0x9006d, 0x18}, + {0x9006e, 0x0}, + {0x9006f, 0x4}, + {0x90070, 0x78}, + {0x90071, 0x549}, + {0x90072, 0x633}, + {0x90073, 0x159}, + {0x90074, 0xd49}, + {0x90075, 0x633}, + {0x90076, 0x159}, + {0x90077, 0x94a}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0x441}, + {0x9007b, 0x633}, + {0x9007c, 0x149}, + {0x9007d, 0x42}, + {0x9007e, 0x633}, + {0x9007f, 0x149}, + {0x90080, 0x1}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x0}, + {0x90084, 0xe0}, + {0x90085, 0x109}, + {0x90086, 0xa}, + {0x90087, 0x10}, + {0x90088, 0x109}, + {0x90089, 0x9}, + {0x9008a, 0x3c0}, + {0x9008b, 0x149}, + {0x9008c, 0x9}, + {0x9008d, 0x3c0}, + {0x9008e, 0x159}, + {0x9008f, 0x18}, + {0x90090, 0x10}, + {0x90091, 0x109}, + {0x90092, 0x0}, + {0x90093, 0x3c0}, + {0x90094, 0x109}, + {0x90095, 0x18}, + {0x90096, 0x4}, + {0x90097, 0x48}, + {0x90098, 0x18}, + {0x90099, 0x4}, + {0x9009a, 0x58}, + {0x9009b, 0xb}, + {0x9009c, 0x10}, + {0x9009d, 0x109}, + {0x9009e, 0x1}, + {0x9009f, 0x10}, + {0x900a0, 0x109}, + {0x900a1, 0x5}, + {0x900a2, 0x7c0}, + {0x900a3, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x790}, + {0x900a6, 0x11a}, + {0x900a7, 0x8}, + {0x900a8, 0x7aa}, + {0x900a9, 0x2a}, + {0x900aa, 0x10}, + {0x900ab, 0x7b2}, + {0x900ac, 0x2a}, + {0x900ad, 0x0}, + {0x900ae, 0x7c8}, + {0x900af, 0x109}, + {0x900b0, 0x10}, + {0x900b1, 0x10}, + {0x900b2, 0x109}, + {0x900b3, 0x10}, + {0x900b4, 0x2a8}, + {0x900b5, 0x129}, + {0x900b6, 0x8}, + {0x900b7, 0x370}, + {0x900b8, 0x129}, + {0x900b9, 0xa}, + {0x900ba, 0x3c8}, + {0x900bb, 0x1a9}, + {0x900bc, 0xc}, + {0x900bd, 0x408}, + {0x900be, 0x199}, + {0x900bf, 0x14}, + {0x900c0, 0x790}, + {0x900c1, 0x11a}, + {0x900c2, 0x8}, + {0x900c3, 0x4}, + {0x900c4, 0x18}, + {0x900c5, 0xe}, + {0x900c6, 0x408}, + {0x900c7, 0x199}, + {0x900c8, 0x8}, + {0x900c9, 0x8568}, + {0x900ca, 0x108}, + {0x900cb, 0x18}, + {0x900cc, 0x790}, + {0x900cd, 0x16a}, + {0x900ce, 0x8}, + {0x900cf, 0x1d8}, + {0x900d0, 0x169}, + {0x900d1, 0x10}, + {0x900d2, 0x8558}, + {0x900d3, 0x168}, + {0x900d4, 0x70}, + {0x900d5, 0x788}, + {0x900d6, 0x16a}, + {0x900d7, 0x1ff8}, + {0x900d8, 0x85a8}, + {0x900d9, 0x1e8}, + {0x900da, 0x50}, + {0x900db, 0x798}, + {0x900dc, 0x16a}, + {0x900dd, 0x60}, + {0x900de, 0x7a0}, + {0x900df, 0x16a}, + {0x900e0, 0x8}, + {0x900e1, 0x8310}, + {0x900e2, 0x168}, + {0x900e3, 0x8}, + {0x900e4, 0xa310}, + {0x900e5, 0x168}, + {0x900e6, 0xa}, + {0x900e7, 0x408}, + {0x900e8, 0x169}, + {0x900e9, 0x6e}, + {0x900ea, 0x0}, + {0x900eb, 0x68}, + {0x900ec, 0x0}, + {0x900ed, 0x408}, + {0x900ee, 0x169}, + {0x900ef, 0x0}, + {0x900f0, 0x8310}, + {0x900f1, 0x168}, + {0x900f2, 0x0}, + {0x900f3, 0xa310}, + {0x900f4, 0x168}, + {0x900f5, 0x1ff8}, + {0x900f6, 0x85a8}, + {0x900f7, 0x1e8}, + {0x900f8, 0x68}, + {0x900f9, 0x798}, + {0x900fa, 0x16a}, + {0x900fb, 0x78}, + {0x900fc, 0x7a0}, + {0x900fd, 0x16a}, + {0x900fe, 0x68}, + {0x900ff, 0x790}, + {0x90100, 0x16a}, + {0x90101, 0x8}, + {0x90102, 0x8b10}, + {0x90103, 0x168}, + {0x90104, 0x8}, + {0x90105, 0xab10}, + {0x90106, 0x168}, + {0x90107, 0xa}, + {0x90108, 0x408}, + {0x90109, 0x169}, + {0x9010a, 0x58}, + {0x9010b, 0x0}, + {0x9010c, 0x68}, + {0x9010d, 0x0}, + {0x9010e, 0x408}, + {0x9010f, 0x169}, + {0x90110, 0x0}, + {0x90111, 0x8b10}, + {0x90112, 0x168}, + {0x90113, 0x1}, + {0x90114, 0xab10}, + {0x90115, 0x168}, + {0x90116, 0x0}, + {0x90117, 0x1d8}, + {0x90118, 0x169}, + {0x90119, 0x80}, + {0x9011a, 0x790}, + {0x9011b, 0x16a}, + {0x9011c, 0x18}, + {0x9011d, 0x7aa}, + {0x9011e, 0x6a}, + {0x9011f, 0xa}, + {0x90120, 0x0}, + {0x90121, 0x1e9}, + {0x90122, 0x8}, + {0x90123, 0x8080}, + {0x90124, 0x108}, + {0x90125, 0xf}, + {0x90126, 0x408}, + {0x90127, 0x169}, + {0x90128, 0xc}, + {0x90129, 0x0}, + {0x9012a, 0x68}, + {0x9012b, 0x9}, + {0x9012c, 0x0}, + {0x9012d, 0x1a9}, + {0x9012e, 0x0}, + {0x9012f, 0x408}, + {0x90130, 0x169}, + {0x90131, 0x0}, + {0x90132, 0x8080}, + {0x90133, 0x108}, + {0x90134, 0x8}, + {0x90135, 0x7aa}, + {0x90136, 0x6a}, + {0x90137, 0x0}, + {0x90138, 0x8568}, + {0x90139, 0x108}, + {0x9013a, 0xb7}, + {0x9013b, 0x790}, + {0x9013c, 0x16a}, + {0x9013d, 0x1f}, + {0x9013e, 0x0}, + {0x9013f, 0x68}, + {0x90140, 0x8}, + {0x90141, 0x8558}, + {0x90142, 0x168}, + {0x90143, 0xf}, + {0x90144, 0x408}, + {0x90145, 0x169}, + {0x90146, 0xd}, + {0x90147, 0x0}, + {0x90148, 0x68}, + {0x90149, 0x0}, + {0x9014a, 0x408}, + {0x9014b, 0x169}, + {0x9014c, 0x0}, + {0x9014d, 0x8558}, + {0x9014e, 0x168}, + {0x9014f, 0x8}, + {0x90150, 0x3c8}, + {0x90151, 0x1a9}, + {0x90152, 0x3}, + {0x90153, 0x370}, + {0x90154, 0x129}, + {0x90155, 0x20}, + {0x90156, 0x2aa}, + {0x90157, 0x9}, + {0x90158, 0x8}, + {0x90159, 0xe8}, + {0x9015a, 0x109}, + {0x9015b, 0x0}, + {0x9015c, 0x8140}, + {0x9015d, 0x10c}, + {0x9015e, 0x10}, + {0x9015f, 0x8138}, + {0x90160, 0x104}, + {0x90161, 0x8}, + {0x90162, 0x448}, + {0x90163, 0x109}, + {0x90164, 0xf}, + {0x90165, 0x7c0}, + {0x90166, 0x109}, + {0x90167, 0x0}, + {0x90168, 0xe8}, + {0x90169, 0x109}, + {0x9016a, 0x47}, + {0x9016b, 0x630}, + {0x9016c, 0x109}, + {0x9016d, 0x8}, + {0x9016e, 0x618}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0xe0}, + {0x90172, 0x109}, + {0x90173, 0x0}, + {0x90174, 0x7c8}, + {0x90175, 0x109}, + {0x90176, 0x8}, + {0x90177, 0x8140}, + {0x90178, 0x10c}, + {0x90179, 0x0}, + {0x9017a, 0x478}, + {0x9017b, 0x109}, + {0x9017c, 0x0}, + {0x9017d, 0x1}, + {0x9017e, 0x8}, + {0x9017f, 0x8}, + {0x90180, 0x4}, + {0x90181, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x29}, + {0x90026, 0x68}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x7d}, + {0x2000c, 0xfa}, + {0x2000d, 0x9c4}, + {0x2000e, 0x2c}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x400fd, 0xf}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x12011, 0x1}, + {0x12012, 0x1}, + {0x12013, 0x180}, + {0x12018, 0x1}, + {0x12002, 0x6209}, + {0x120b2, 0x1}, + {0x121b4, 0x1}, + {0x122b4, 0x1}, + {0x123b4, 0x1}, + {0x124b4, 0x1}, + {0x125b4, 0x1}, + {0x126b4, 0x1}, + {0x127b4, 0x1}, + {0x128b4, 0x1}, + {0x13011, 0x1}, + {0x13012, 0x1}, + {0x13013, 0x180}, + {0x13018, 0x1}, + {0x13002, 0x6209}, + {0x130b2, 0x1}, + {0x131b4, 0x1}, + {0x132b4, 0x1}, + {0x133b4, 0x1}, + {0x134b4, 0x1}, + {0x135b4, 0x1}, + {0x136b4, 0x1}, + {0x137b4, 0x1}, + {0x138b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x2}, + {0xd0000, 0x1}, +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 4000mts 1D */ + .drate = 4000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P0 4000mts 2D */ + .drate = 4000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 4000, }, +}; diff --git a/board/phytec/imx8mp-libra-fpsc/spl.c b/board/phytec/imx8mp-libra-fpsc/spl.c new file mode 100644 index 00000000000..d704d588579 --- /dev/null +++ b/board/phytec/imx8mp-libra-fpsc/spl.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) +#include "../common/imx8m_som_detection.h" +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define EEPROM_ADDR 0x51 + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_dram_init(void) +{ +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) + int ret; + + ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR); + if (!ret) { + ret = phytec_imx8m_detect(NULL); + if (!ret) + phytec_print_som_info(NULL); + } +#endif + + ddr_init(&dram_timing); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +int power_init_board(void) +{ + struct pmic *p; + int ret; + + ret = power_pca9450_init(0, 0x25); + if (ret) + printf("power init failed"); + p = pmic_get("PCA9450"); + pmic_probe(p); + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + + /* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */ + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); + pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); + + /* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */ + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + + /* Set WDOG_B_CFG to cold reset */ + pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); + + return 0; +} + +void spl_board_init(void) +{ + arch_misc_init(); + + /* Set GIC clock to 500Mhz for OD VDD_SOC. */ + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); + clock_enable(CCGR_GIC, 1); +} + +int board_fit_config_name_match(const char *name) +{ + return 0; +} + +void board_init_f(ulong dummy) +{ + int ret; + + arch_cpu_init(); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + + enable_tzc380(); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); +} diff --git a/configs/imx8mp-libra-fpsc_defconfig b/configs/imx8mp-libra-fpsc_defconfig new file mode 100644 index 00000000000..a23e604425d --- /dev/null +++ b/configs/imx8mp-libra-fpsc_defconfig @@ -0,0 +1,175 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SF_DEFAULT_SPEED=80000000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x3C0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-libra-rdk-fpsc" +CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x7e000000 +CONFIG_TARGET_IMX8MP_LIBRA_FPSC=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x960000 +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SYS_LOAD_ADDR=0x47602000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x3e0000 +CONFIG_IMX_BOOTAUX=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTSTD_FULL=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_FDT_FIXUP_PARTITIONS=y +CONFIG_DEFAULT_FDT_FILE="imx8mp-libra-rdk-fpsc.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_SIZE=4096 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MMC_REG=y +CONFIG_CMD_MTD=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x13000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=2 +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc2boot0" +CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc2boot1" +CONFIG_FASTBOOT_MMC_USER_SUPPORT=y +CONFIG_FASTBOOT_MMC_USER_NAME="mmc2" +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +# CONFIG_SPL_DM_I2C is not set +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x51 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_TI_DP83867=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SPL_POWER_LEGACY=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y +CONFIG_POWER_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_POWER_I2C=y +CONFIG_DM_RNG=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_IMX_WATCHDOG=y diff --git a/doc/board/phytec/imx8mp-libra-fpsc.rst b/doc/board/phytec/imx8mp-libra-fpsc.rst new file mode 100644 index 00000000000..26752ac1882 --- /dev/null +++ b/doc/board/phytec/imx8mp-libra-fpsc.rst @@ -0,0 +1,83 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Libra i.MX 8M Plus FPSC +======================= + +The Libra i.MX 8M Plus FPSC is a SBC based with the phyCORE-i.MX 8M Plus FPSC +SoM. +The phyCORE-i.MX 8M Plus FPSC with 2GB of main memory is supported. + +Quick Start +----------- + +- Build the ARM Trusted firmware binary +- Build the OP-TEE binary +- Get ddr firmware +- Build U-Boot +- Boot + +Build the ARM Trusted firmware binary +------------------------------------- + +.. code-block:: bash + + $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git + $ cd trusted-firmware-a + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ + PLAT=imx8mp \ + IMX_BOOT_UART_BASE=0x30a60000 \ + BL32_BASE=0x7e000000 \ + SPD=opteed \ + bl31 + +Build the OP-TEE binary +----------------------- + +.. code-block:: bash + + $ git clone https://github.com/OP-TEE/optee_os.git + $ cd optee_os + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ + CFG_TEE_BENCHMARK=n \ + O=out/arm \ + PLATFORM=imx-mx8mp_libra_fpsc + +Get the ddr firmware +-------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin + $ chmod +x firmware-imx-8.28-994fa14.bin + $ ./firmware-imx-8.28-994fa14.bin + +Build U-Boot for SD card +------------------------ + +Copy binaries +^^^^^^^^^^^^^ + +.. code-block:: bash + + $ cp /build/imx8mp/release/bl31.bin . + $ cp /out/arm/core/tee-raw.bin tee.bin + $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr4*.bin . + +Build U-Boot +^^^^^^^^^^^^ + +.. code-block:: bash + + $ make -j $(nproc) \ + CROSS_COMPILE=aarch64-linux-gnu- \ + imx8mp-libra-fpsc_defconfig \ + flash.bin + +Flash SD card +^^^^^^^^^^^^^ + +.. code-block:: bash + + $ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=fsync diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst index 1ae30c2dcd5..e24040a496e 100644 --- a/doc/board/phytec/index.rst +++ b/doc/board/phytec/index.rst @@ -6,6 +6,7 @@ PHYTEC .. toctree:: :maxdepth: 2 + imx8mp-libra-fpsc imx8mm-phygate-tauri-l imx93-phycore phycore-am62x diff --git a/include/configs/imx8mp-libra-fpsc.h b/include/configs/imx8mp-libra-fpsc.h new file mode 100644 index 00000000000..cde91dc3642 --- /dev/null +++ b/include/configs/imx8mp-libra-fpsc.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#ifndef __IMX8MP_LIBRA_FPSC_H +#define __IMX8MP_LIBRA_FPSC_H + +#include +#include + +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +/* Link Definitions */ + +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K + +#define CFG_SYS_SDRAM_BASE 0x40000000 + +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) /* 3GB */ +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G) /* 5GB */ + +#endif /* __IMX8MP_LIBRA_FPSC_H */ -- cgit v1.3.1 From 8633643769b5d5b30567b89a1c0fb00b8f2ac7b2 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Mon, 25 Aug 2025 10:23:10 -0500 Subject: board: ti: am65x: Overwrite get_overlay_mmc Unlike other K3 SoC's, am65 SoC has the capability to detect daughter cards and automatically generate a list of white-space separated overlays in name_overlays environment variable. When applied during boot with get_overlay_mmc, the path to overlays with default distribution is incorrect where path is currently: boot/dtb and the overlays exist in boot/dtb/ti. Fix the path in get_overlay_mmc so that overlays are automatically applied correctly during boot time. Signed-off-by: Judith Mendez --- board/ti/am65x/am65x.env | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'board') diff --git a/board/ti/am65x/am65x.env b/board/ti/am65x/am65x.env index 631997e4c97..b6cdfc9bd96 100644 --- a/board/ti/am65x/am65x.env +++ b/board/ti/am65x/am65x.env @@ -17,6 +17,15 @@ bootpart=1:2 bootdir=/boot rd_spec=- +get_overlay_mmc= + fdt address ${fdtaddr}; + fdt resize 0x100000; + for overlay in $name_overlays; + do; + load mmc ${bootpart} ${dtboaddr} ${bootdir}/dtb/ti/${overlay} && + fdt apply ${dtboaddr}; + done; + init_ubi= run args_all args_ubi; sf probe; -- cgit v1.3.1 From 4d1caf58d22f8be26ded411d5774eaa6eaa3714f Mon Sep 17 00:00:00 2001 From: Bhimeswararao Matsa Date: Mon, 1 Sep 2025 20:09:45 +0530 Subject: board: ti: fdt_ops: make ti_set_fdt_env() const-correct Make the fdt_map parameter a pointer to const, since the function only reads the mapping table. This improves API correctness and allows maps to live in read-only data. No functional change intended Signed-off-by: Bhimeswararao Matsa --- board/ti/common/fdt_ops.c | 2 +- board/ti/common/fdt_ops.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/ti/common/fdt_ops.c b/board/ti/common/fdt_ops.c index 47df5726ff0..0486d2e7802 100644 --- a/board/ti/common/fdt_ops.c +++ b/board/ti/common/fdt_ops.c @@ -9,7 +9,7 @@ #include #include "fdt_ops.h" -void ti_set_fdt_env(const char *board_name, struct ti_fdt_map *fdt_map) +void ti_set_fdt_env(const char *board_name, const struct ti_fdt_map *fdt_map) { char *fdt_file_name = NULL; char fdtfile[TI_FDT_FILE_MAX]; diff --git a/board/ti/common/fdt_ops.h b/board/ti/common/fdt_ops.h index 5d304994fb6..5375303ba8e 100644 --- a/board/ti/common/fdt_ops.h +++ b/board/ti/common/fdt_ops.h @@ -37,6 +37,6 @@ struct ti_fdt_map { * @board_name: match to search with (max of TI_BOARD_NAME_MAX chars) * @fdt_map: NULL terminated array of device tree file name matches. */ -void ti_set_fdt_env(const char *board_name, struct ti_fdt_map *fdt_map); +void ti_set_fdt_env(const char *board_name, const struct ti_fdt_map *fdt_map); #endif /* __FDT_OPS_H */ -- cgit v1.3.1 From 83bb1c438486a03184795b0dfa970271496b24bf Mon Sep 17 00:00:00 2001 From: Anshul Dalal Date: Tue, 2 Sep 2025 10:27:07 +0530 Subject: board: ti: common: Kconfig: add CMD_MEMINFO Add CMD_MEMINFO and CMD_MEMINFO_MAP to list of configs implied by TI_COMMON_CMD_OPTIONS. This allows users to easily view the memory configuration and the memory maps at runtime. Signed-off-by: Anshul Dalal --- board/ti/common/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'board') diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig index 2de4212d9b8..f481812247c 100644 --- a/board/ti/common/Kconfig +++ b/board/ti/common/Kconfig @@ -40,6 +40,8 @@ config TI_COMMON_CMD_OPTIONS imply CMD_GPIO imply CMD_GPT imply CMD_I2C + imply CMD_MEMINFO + imply CMD_MEMINFO_MAP imply CMD_MII imply CMD_MMC imply CMD_MMC_REG -- cgit v1.3.1 From 1c735620e19e2ae07705cc38da1552ee6a696ff0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 7 Sep 2025 03:00:46 +0200 Subject: board: dhelectronics: Check pointer before access in dh_get_value_from_eeprom_buffer() The eip pointer in dh_get_value_from_eeprom_buffer() might be NULL. The current NULL pointer check happens too late, after the eip was accessed in variable assignment. Reorder the two, so the NULL pointer check happens first, and any access second, otherwise the access may trigger a hang or other undefined behavior. Signed-off-by: Marek Vasut Reviewed-by: Christoph Niedermaier --- board/dhelectronics/common/dh_common.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/dhelectronics/common/dh_common.c b/board/dhelectronics/common/dh_common.c index 8c052c45007..d3a3f0ff11f 100644 --- a/board/dhelectronics/common/dh_common.c +++ b/board/dhelectronics/common/dh_common.c @@ -131,14 +131,17 @@ int dh_read_eeprom_id_page(u8 *eeprom_buffer, const char *alias) int dh_get_value_from_eeprom_buffer(enum eip_request_values request, u8 *data, int data_len, struct eeprom_id_page *eip) { - const char fin_chr = (eip->pl.item_prefix & DH_ITEM_PREFIX_FIN_BIT) ? - DH_ITEM_PREFIX_FIN_FLASHED_CHR : DH_ITEM_PREFIX_FIN_HALF_CHR; - const u8 soc_coded = eip->pl.item_prefix & 0xf; + char fin_chr; + u8 soc_coded; char soc_chr; if (!eip) return -EINVAL; + fin_chr = (eip->pl.item_prefix & DH_ITEM_PREFIX_FIN_BIT) ? + DH_ITEM_PREFIX_FIN_FLASHED_CHR : DH_ITEM_PREFIX_FIN_HALF_CHR; + soc_coded = eip->pl.item_prefix & 0xf; + /* Copy requested data */ switch (request) { case DH_MAC0: -- cgit v1.3.1 From fd396316432ad4a0f2998ea9eee9720be0e5d5f8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 7 Sep 2025 03:00:47 +0200 Subject: board: dhelectronics: Use isascii() before isprint() in dh_read_eeprom_id_page() The isprint() checks printability across all 256 characters, some of the upper 128 characters are printable and produce artifacts on UART. Call isascii() first to only consider the bottom 7bit ASCII characters as printable, and then check their printability using isprint(). This fixes a rare misprint in case the ID page content is uninitialized or corrupted. Signed-off-by: Marek Vasut Reviewed-by: Christoph Niedermaier --- board/dhelectronics/common/dh_common.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/dhelectronics/common/dh_common.c b/board/dhelectronics/common/dh_common.c index d3a3f0ff11f..6101ecc7ebc 100644 --- a/board/dhelectronics/common/dh_common.c +++ b/board/dhelectronics/common/dh_common.c @@ -88,9 +88,9 @@ int dh_read_eeprom_id_page(u8 *eeprom_buffer, const char *alias) /* Validate header ID */ if (eip->hdr.id[0] != 'D' || eip->hdr.id[1] != 'H' || eip->hdr.id[2] != 'E') { printf("%s: Error validating header ID! (got %c%c%c (0x%02x 0x%02x 0x%02x) != expected DHE)\n", - __func__, isprint(eip->hdr.id[0]) ? eip->hdr.id[0] : '.', - isprint(eip->hdr.id[1]) ? eip->hdr.id[1] : '.', - isprint(eip->hdr.id[2]) ? eip->hdr.id[2] : '.', + __func__, (isascii(eip->hdr.id[0]) && isprint(eip->hdr.id[0])) ? eip->hdr.id[0] : '.', + (isascii(eip->hdr.id[1]) && isprint(eip->hdr.id[1])) ? eip->hdr.id[1] : '.', + (isascii(eip->hdr.id[2]) && isprint(eip->hdr.id[2])) ? eip->hdr.id[2] : '.', eip->hdr.id[0], eip->hdr.id[1], eip->hdr.id[2]); return -EINVAL; } -- cgit v1.3.1 From 686b48af6d6f4e33f10dc707e9a8c8213b682348 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 28 Aug 2025 15:03:35 +0200 Subject: starfive: avoid NULL dereference in fdt_check_header() If the u-boot.itb read from SD-card is invalid, fdt_check_header() may be called with a NULL pointer. This was observed on an StarFive VisionFive Lite when trying to revover the board via UART. Add a missing check in the starfive board code. Signed-off-by: Heinrich Schuchardt Reviewed-by: E Shattow --- board/starfive/visionfive2/spl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index 3dfa931b655..fe14b44ce28 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -23,7 +23,8 @@ DECLARE_GLOBAL_DATA_PTR; void spl_perform_fixups(struct spl_image_info *spl_image) { /* Update the memory size which read from eeprom or DT */ - fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size); + if (spl_image->fdt_addr) + fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size); } static void jh7110_jtag_init(void) -- cgit v1.3.1 From d141a41feb005a9f6a830006f1a4b66d1a3a3cd2 Mon Sep 17 00:00:00 2001 From: Jamie Gibbons Date: Tue, 2 Sep 2025 11:10:58 +0100 Subject: board: microchip: icicle: rename all icicle files to generic Make all Icicle Kit files generic. This supports the addition of upcoming support for other MPFS boards. Signed-off-by: Jamie Gibbons Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 6 +- board/microchip/mpfs_generic/Kconfig | 67 +++++++++ board/microchip/mpfs_generic/MAINTAINERS | 7 + board/microchip/mpfs_generic/Makefile | 7 + board/microchip/mpfs_generic/mpfs_generic.c | 204 ++++++++++++++++++++++++++++ board/microchip/mpfs_icicle/Kconfig | 67 --------- board/microchip/mpfs_icicle/MAINTAINERS | 7 - board/microchip/mpfs_icicle/Makefile | 7 - board/microchip/mpfs_icicle/mpfs_icicle.c | 204 ---------------------------- configs/microchip_mpfs_generic_defconfig | 29 ++++ configs/microchip_mpfs_icicle_defconfig | 29 ---- include/configs/microchip_mpfs_generic.h | 32 +++++ include/configs/microchip_mpfs_icicle.h | 32 ----- 13 files changed, 349 insertions(+), 349 deletions(-) create mode 100644 board/microchip/mpfs_generic/Kconfig create mode 100644 board/microchip/mpfs_generic/MAINTAINERS create mode 100644 board/microchip/mpfs_generic/Makefile create mode 100644 board/microchip/mpfs_generic/mpfs_generic.c delete mode 100644 board/microchip/mpfs_icicle/Kconfig delete mode 100644 board/microchip/mpfs_icicle/MAINTAINERS delete mode 100644 board/microchip/mpfs_icicle/Makefile delete mode 100644 board/microchip/mpfs_icicle/mpfs_icicle.c create mode 100644 configs/microchip_mpfs_generic_defconfig delete mode 100644 configs/microchip_mpfs_icicle_defconfig create mode 100644 include/configs/microchip_mpfs_generic.h delete mode 100644 include/configs/microchip_mpfs_icicle.h (limited to 'board') diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f0d2c904349..265b5320777 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -23,8 +23,8 @@ config TARGET_K230_CANMV config TARGET_LICHEERV_NANO bool "Support LicheeRV Nano Board" -config TARGET_MICROCHIP_ICICLE - bool "Support Microchip PolarFire-SoC Icicle Board" +config TARGET_MICROCHIP_GENERIC + bool "Support Microchip PolarFire-SoC Boards" config TARGET_MILKV_DUO bool "Support Milk-v Duo Board" @@ -108,7 +108,7 @@ source "board/andestech/voyager/Kconfig" source "board/aspeed/ibex_ast2700/Kconfig" source "board/canaan/k230_canmv/Kconfig" source "board/emulation/qemu-riscv/Kconfig" -source "board/microchip/mpfs_icicle/Kconfig" +source "board/microchip/mpfs_generic/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" diff --git a/board/microchip/mpfs_generic/Kconfig b/board/microchip/mpfs_generic/Kconfig new file mode 100644 index 00000000000..8dcf55a0311 --- /dev/null +++ b/board/microchip/mpfs_generic/Kconfig @@ -0,0 +1,67 @@ +if TARGET_MICROCHIP_GENERIC + +config SYS_BOARD + default "mpfs_generic" + +config SYS_VENDOR + default "microchip" + +config SYS_CPU + default "generic" + +config SYS_CONFIG_NAME + default "microchip_mpfs_generic" + +config TEXT_BASE + default 0x80000000 if !RISCV_SMODE + default 0x80200000 if RISCV_SMODE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select GENERIC_RISCV + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + imply SMP + imply CLK_CCF + imply CLK_MPFS + imply REGMAP + imply SYSCON + imply SYS_NS16550 + imply CMD_DHCP + imply CMD_EXT2 + imply CMD_EXT4 + imply CMD_FAT + imply CMD_FS_GENERIC + imply CMD_NET + imply CMD_PING + imply CMD_MMC + imply DOS_PARTITION + imply EFI_PARTITION + imply IP_DYN + imply ISO_PARTITION + imply MACB + imply MII + imply PHY_LIB + imply PHY_VITESSE + imply MMC + imply MMC_WRITE + imply MMC_SDHCI + imply MMC_SDHCI_CADENCE + imply MMC_SDHCI_ADMA + imply MMC_HS200_SUPPORT + imply CMD_I2C + imply DM_I2C + imply SYS_I2C_MICROCHIP + imply MTD + imply SPI + imply DM_SPI + imply MICROCHIP_COREQSPI + imply MTD_SPI_NAND + imply CMD_MTD + imply CMD_MTDPARTS + imply DM_MAILBOX + imply MPFS_MBOX + imply MISC + imply MPFS_SYSCONTROLLER + +endif diff --git a/board/microchip/mpfs_generic/MAINTAINERS b/board/microchip/mpfs_generic/MAINTAINERS new file mode 100644 index 00000000000..3de99144c41 --- /dev/null +++ b/board/microchip/mpfs_generic/MAINTAINERS @@ -0,0 +1,7 @@ +Microchip MPFS Generic +M: Conor Dooley +M: Jamie Gibbons +S: Maintained +F: board/microchip/mpfs_generic/ +F: include/configs/microchip_mpfs_generic.h +F: configs/microchip_mpfs_generic_defconfig diff --git a/board/microchip/mpfs_generic/Makefile b/board/microchip/mpfs_generic/Makefile new file mode 100644 index 00000000000..dfe4b2634e6 --- /dev/null +++ b/board/microchip/mpfs_generic/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Microchip Technology Inc. +# Padmarao Begari +# + +obj-y += mpfs_generic.o diff --git a/board/microchip/mpfs_generic/mpfs_generic.c b/board/microchip/mpfs_generic/mpfs_generic.c new file mode 100644 index 00000000000..739a9b6cd76 --- /dev/null +++ b/board/microchip/mpfs_generic/mpfs_generic.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Microchip Technology Inc. + * Padmarao Begari + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) +#define PERIPH_RESET_VALUE 0x1e8u + +static unsigned char mac_addr[6]; + +#if defined(CONFIG_MULTI_DTB_FIT) +int board_fit_config_name_match(const char *name) +{ + const void *fdt; + int list_len; + + /* + * If there's not a HSS provided dtb, there's no point re-selecting + * since we'd just end up re-selecting the same dtb again. + */ + if (!gd->arch.firmware_fdt_addr) + return -EINVAL; + + fdt = (void *)gd->arch.firmware_fdt_addr; + + list_len = fdt_stringlist_count(fdt, 0, "compatible"); + if (list_len < 1) + return -EINVAL; + + for (int i = 0; i < list_len; i++) { + int len, match; + const char *compat; + char copy[64]; + char *devendored; + + compat = fdt_stringlist_get(fdt, 0, "compatible", i, &len); + if (!compat) + return -EINVAL; + + /* + * The naming scheme for compatibles doesn't produce anything + * close to this long. + */ + if (len >= 64) + return -EINVAL; + + strncpy(copy, compat, 64); + strtok(copy, ","); + + devendored = strtok(NULL, ","); + if (!devendored) + return -EINVAL; + + match = strcmp(devendored, name); + if (!match) + return 0; + } + + return -EINVAL; +} +#endif + +int board_fdt_blob_setup(void **fdtp) +{ + fdtp = (void *)_end; + + /* + * The devicetree provided by the previous stage is very minimal due to + * severe space constraints. The firmware performs no fixups etc. + * U-Boot, if providing a devicetree, almost certainly has a better + * more complete one than the firmware so that provided by the firmware + * is ignored for OF_SEPARATE. + */ + if (IS_ENABLED(CONFIG_OF_BOARD) && !IS_ENABLED(CONFIG_MULTI_DTB_FIT)) { + if (gd->arch.firmware_fdt_addr) + fdtp = (void *)(uintptr_t)gd->arch.firmware_fdt_addr; + } + + return 0; +} + +int board_init(void) +{ + /* For now nothing to do here. */ + + return 0; +} + +int board_early_init_f(void) +{ + unsigned int val; + + /* Reset uart, mmc peripheral */ + val = readl(MPFS_SYSREG_SOFT_RESET); + val = (val & ~(PERIPH_RESET_VALUE)); + writel(val, MPFS_SYSREG_SOFT_RESET); + + return 0; +} + +int board_late_init(void) +{ + u32 ret; + int node; + u8 device_serial_number[16] = {0}; + void *blob = (void *)gd->fdt_blob; + struct udevice *dev; + struct mpfs_sys_serv *sys_serv_priv; + + ret = uclass_get_device_by_name(UCLASS_MISC, "syscontroller", &dev); + if (ret) { + debug("%s: system controller setup failed\n", __func__); + return ret; + } + + sys_serv_priv = kzalloc(sizeof(*sys_serv_priv), GFP_KERNEL); + if (!sys_serv_priv) + return -ENOMEM; + + sys_serv_priv->dev = dev; + + sys_serv_priv->sys_controller = mpfs_syscontroller_get(dev); + ret = IS_ERR(sys_serv_priv->sys_controller); + if (ret) { + debug("%s: Failed to register system controller sub device ret=%d\n", __func__, ret); + return -ENODEV; + } + + ret = mpfs_syscontroller_read_sernum(sys_serv_priv, device_serial_number); + if (ret) { + printf("Cannot read device serial number\n"); + return -EINVAL; + } + + /* Update MAC address with device serial number */ + mac_addr[0] = 0x00; + mac_addr[1] = 0x04; + mac_addr[2] = 0xA3; + mac_addr[3] = device_serial_number[2]; + mac_addr[4] = device_serial_number[1]; + mac_addr[5] = device_serial_number[0]; + + node = fdt_path_offset(blob, "/soc/ethernet@20112000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20112000\n"); + return -ENODEV; + } + } + + mac_addr[5] = device_serial_number[0] + 1; + + node = fdt_path_offset(blob, "/soc/ethernet@20110000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20110000\n"); + return -ENODEV; + } + } + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u32 ret; + int node; + + node = fdt_path_offset(blob, "/soc/ethernet@20110000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20110000\n"); + return -ENODEV; + } + } + + mac_addr[5] -= 1; + + node = fdt_path_offset(blob, "/soc/ethernet@20112000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20112000\n"); + return -ENODEV; + } + } + + return 0; +} diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig deleted file mode 100644 index 760dffc488b..00000000000 --- a/board/microchip/mpfs_icicle/Kconfig +++ /dev/null @@ -1,67 +0,0 @@ -if TARGET_MICROCHIP_ICICLE - -config SYS_BOARD - default "mpfs_icicle" - -config SYS_VENDOR - default "microchip" - -config SYS_CPU - default "generic" - -config SYS_CONFIG_NAME - default "microchip_mpfs_icicle" - -config TEXT_BASE - default 0x80000000 if !RISCV_SMODE - default 0x80200000 if RISCV_SMODE - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select GENERIC_RISCV - select BOARD_EARLY_INIT_F - select BOARD_LATE_INIT - imply SMP - imply CLK_CCF - imply CLK_MPFS - imply REGMAP - imply SYSCON - imply SYS_NS16550 - imply CMD_DHCP - imply CMD_EXT2 - imply CMD_EXT4 - imply CMD_FAT - imply CMD_FS_GENERIC - imply CMD_NET - imply CMD_PING - imply CMD_MMC - imply DOS_PARTITION - imply EFI_PARTITION - imply IP_DYN - imply ISO_PARTITION - imply MACB - imply MII - imply PHY_LIB - imply PHY_VITESSE - imply MMC - imply MMC_WRITE - imply MMC_SDHCI - imply MMC_SDHCI_CADENCE - imply MMC_SDHCI_ADMA - imply MMC_HS200_SUPPORT - imply CMD_I2C - imply DM_I2C - imply SYS_I2C_MICROCHIP - imply MTD - imply SPI - imply DM_SPI - imply MICROCHIP_COREQSPI - imply MTD_SPI_NAND - imply CMD_MTD - imply CMD_MTDPARTS - imply DM_MAILBOX - imply MPFS_MBOX - imply MISC - imply MPFS_SYSCONTROLLER - -endif diff --git a/board/microchip/mpfs_icicle/MAINTAINERS b/board/microchip/mpfs_icicle/MAINTAINERS deleted file mode 100644 index d092b5a8111..00000000000 --- a/board/microchip/mpfs_icicle/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -Microchip MPFS icicle -M: Conor Dooley -M: Cyril Jean -S: Maintained -F: board/microchip/mpfs_icicle/ -F: include/configs/microchip_mpfs_icicle.h -F: configs/microchip_mpfs_icicle_defconfig diff --git a/board/microchip/mpfs_icicle/Makefile b/board/microchip/mpfs_icicle/Makefile deleted file mode 100644 index 72b0410dda8..00000000000 --- a/board/microchip/mpfs_icicle/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2019 Microchip Technology Inc. -# Padmarao Begari -# - -obj-y += mpfs_icicle.o diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c deleted file mode 100644 index 739a9b6cd76..00000000000 --- a/board/microchip/mpfs_icicle/mpfs_icicle.c +++ /dev/null @@ -1,204 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2019 Microchip Technology Inc. - * Padmarao Begari - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) -#define PERIPH_RESET_VALUE 0x1e8u - -static unsigned char mac_addr[6]; - -#if defined(CONFIG_MULTI_DTB_FIT) -int board_fit_config_name_match(const char *name) -{ - const void *fdt; - int list_len; - - /* - * If there's not a HSS provided dtb, there's no point re-selecting - * since we'd just end up re-selecting the same dtb again. - */ - if (!gd->arch.firmware_fdt_addr) - return -EINVAL; - - fdt = (void *)gd->arch.firmware_fdt_addr; - - list_len = fdt_stringlist_count(fdt, 0, "compatible"); - if (list_len < 1) - return -EINVAL; - - for (int i = 0; i < list_len; i++) { - int len, match; - const char *compat; - char copy[64]; - char *devendored; - - compat = fdt_stringlist_get(fdt, 0, "compatible", i, &len); - if (!compat) - return -EINVAL; - - /* - * The naming scheme for compatibles doesn't produce anything - * close to this long. - */ - if (len >= 64) - return -EINVAL; - - strncpy(copy, compat, 64); - strtok(copy, ","); - - devendored = strtok(NULL, ","); - if (!devendored) - return -EINVAL; - - match = strcmp(devendored, name); - if (!match) - return 0; - } - - return -EINVAL; -} -#endif - -int board_fdt_blob_setup(void **fdtp) -{ - fdtp = (void *)_end; - - /* - * The devicetree provided by the previous stage is very minimal due to - * severe space constraints. The firmware performs no fixups etc. - * U-Boot, if providing a devicetree, almost certainly has a better - * more complete one than the firmware so that provided by the firmware - * is ignored for OF_SEPARATE. - */ - if (IS_ENABLED(CONFIG_OF_BOARD) && !IS_ENABLED(CONFIG_MULTI_DTB_FIT)) { - if (gd->arch.firmware_fdt_addr) - fdtp = (void *)(uintptr_t)gd->arch.firmware_fdt_addr; - } - - return 0; -} - -int board_init(void) -{ - /* For now nothing to do here. */ - - return 0; -} - -int board_early_init_f(void) -{ - unsigned int val; - - /* Reset uart, mmc peripheral */ - val = readl(MPFS_SYSREG_SOFT_RESET); - val = (val & ~(PERIPH_RESET_VALUE)); - writel(val, MPFS_SYSREG_SOFT_RESET); - - return 0; -} - -int board_late_init(void) -{ - u32 ret; - int node; - u8 device_serial_number[16] = {0}; - void *blob = (void *)gd->fdt_blob; - struct udevice *dev; - struct mpfs_sys_serv *sys_serv_priv; - - ret = uclass_get_device_by_name(UCLASS_MISC, "syscontroller", &dev); - if (ret) { - debug("%s: system controller setup failed\n", __func__); - return ret; - } - - sys_serv_priv = kzalloc(sizeof(*sys_serv_priv), GFP_KERNEL); - if (!sys_serv_priv) - return -ENOMEM; - - sys_serv_priv->dev = dev; - - sys_serv_priv->sys_controller = mpfs_syscontroller_get(dev); - ret = IS_ERR(sys_serv_priv->sys_controller); - if (ret) { - debug("%s: Failed to register system controller sub device ret=%d\n", __func__, ret); - return -ENODEV; - } - - ret = mpfs_syscontroller_read_sernum(sys_serv_priv, device_serial_number); - if (ret) { - printf("Cannot read device serial number\n"); - return -EINVAL; - } - - /* Update MAC address with device serial number */ - mac_addr[0] = 0x00; - mac_addr[1] = 0x04; - mac_addr[2] = 0xA3; - mac_addr[3] = device_serial_number[2]; - mac_addr[4] = device_serial_number[1]; - mac_addr[5] = device_serial_number[0]; - - node = fdt_path_offset(blob, "/soc/ethernet@20112000"); - if (node >= 0) { - ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); - if (ret) { - printf("Error setting local-mac-address property for ethernet@20112000\n"); - return -ENODEV; - } - } - - mac_addr[5] = device_serial_number[0] + 1; - - node = fdt_path_offset(blob, "/soc/ethernet@20110000"); - if (node >= 0) { - ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); - if (ret) { - printf("Error setting local-mac-address property for ethernet@20110000\n"); - return -ENODEV; - } - } - - return 0; -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - u32 ret; - int node; - - node = fdt_path_offset(blob, "/soc/ethernet@20110000"); - if (node >= 0) { - ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); - if (ret) { - printf("Error setting local-mac-address property for ethernet@20110000\n"); - return -ENODEV; - } - } - - mac_addr[5] -= 1; - - node = fdt_path_offset(blob, "/soc/ethernet@20112000"); - if (node >= 0) { - ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); - if (ret) { - printf("Error setting local-mac-address property for ethernet@20112000\n"); - return -ENODEV; - } - } - - return 0; -} diff --git a/configs/microchip_mpfs_generic_defconfig b/configs/microchip_mpfs_generic_defconfig new file mode 100644 index 00000000000..0ed0cae93eb --- /dev/null +++ b/configs/microchip_mpfs_generic_defconfig @@ -0,0 +1,29 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="microchip/mpfs-icicle-kit" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_LOAD_ADDR=0x80200000 +CONFIG_SYS_MEM_TOP_HIDE=0x400000 +# CONFIG_DEBUG_UART is not set +CONFIG_TARGET_MICROCHIP_GENERIC=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="microchip/mpfs-icicle-kit.dtb" +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_OF_UPSTREAM=y +CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_DM_MTD=y +CONFIG_SYSRESET=y diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig deleted file mode 100644 index 9f933592c9d..00000000000 --- a/configs/microchip_mpfs_icicle_defconfig +++ /dev/null @@ -1,29 +0,0 @@ -CONFIG_RISCV=y -CONFIG_SYS_MALLOC_LEN=0x800000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_DEFAULT_DEVICE_TREE="microchip/mpfs-icicle-kit" -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SYS_LOAD_ADDR=0x80200000 -CONFIG_SYS_MEM_TOP_HIDE=0x400000 -# CONFIG_DEBUG_UART is not set -CONFIG_TARGET_MICROCHIP_ICICLE=y -CONFIG_ARCH_RV64I=y -CONFIG_RISCV_SMODE=y -CONFIG_FIT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_DEFAULT_FDT_FILE="microchip/mpfs-icicle-kit.dtb" -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=282 -CONFIG_DISPLAY_CPUINFO=y -CONFIG_DISPLAY_BOARDINFO=y -CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_OF_UPSTREAM=y -CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y -CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_BOOTP_SEND_HOSTNAME=y -CONFIG_DM_MTD=y -CONFIG_SYSRESET=y diff --git a/include/configs/microchip_mpfs_generic.h b/include/configs/microchip_mpfs_generic.h new file mode 100644 index 00000000000..0077f6a5f95 --- /dev/null +++ b/include/configs/microchip_mpfs_generic.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Microchip Technology Inc. + * Padmarao Begari + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CFG_SYS_SDRAM_BASE 0x80000000 + +/* Environment options */ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) + +#include + +#define CFG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x84000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "scriptaddr=0x88100000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + BOOTENV + +#endif /* __CONFIG_H */ diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h deleted file mode 100644 index 0077f6a5f95..00000000000 --- a/include/configs/microchip_mpfs_icicle.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2019 Microchip Technology Inc. - * Padmarao Begari - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CFG_SYS_SDRAM_BASE 0x80000000 - -/* Environment options */ - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) - -#include - -#define CFG_EXTRA_ENV_SETTINGS \ - "bootm_size=0x10000000\0" \ - "kernel_addr_r=0x84000000\0" \ - "fdt_addr_r=0x88000000\0" \ - "scriptaddr=0x88100000\0" \ - "pxefile_addr_r=0x88200000\0" \ - "ramdisk_addr_r=0x88300000\0" \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - BOOTENV - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 41e5a6520b125265f8010f958bb6eef050c08c92 Mon Sep 17 00:00:00 2001 From: Jamie Gibbons Date: Tue, 2 Sep 2025 11:11:03 +0100 Subject: board: microchip: mpfs_generic: include processing of dtbos Include the use of the process dtbo functionality added in the MPFS system controller driver. Signed-off-by: Jamie Gibbons Reviewed-by: Leo Yu-Chi Liang --- board/microchip/mpfs_generic/mpfs_generic.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'board') diff --git a/board/microchip/mpfs_generic/mpfs_generic.c b/board/microchip/mpfs_generic/mpfs_generic.c index 739a9b6cd76..fac4b6aecba 100644 --- a/board/microchip/mpfs_generic/mpfs_generic.c +++ b/board/microchip/mpfs_generic/mpfs_generic.c @@ -172,6 +172,8 @@ int board_late_init(void) } } + mpfs_syscontroller_process_dtbo(sys_serv_priv); + return 0; } -- cgit v1.3.1 From edaaedb5dd0fee9fcdfe41d92659914dc9d1d44d Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Wed, 10 Sep 2025 18:23:27 +0900 Subject: board: qemu-sbsa: Fix mistyped GICV3 definition The config "GIC_V3" seems to be typo, and currently "GICV3" remains disabled. Since "GIC_V3_ITS" is enabled in qemu-sbsa, "GICV3" should also be enabled. Fixes: 6d722894fd48 ("board: emulation: Add QEMU sbsa support") Signed-off-by: Kunihiko Hayashi --- board/emulation/qemu-sbsa/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/emulation/qemu-sbsa/Kconfig b/board/emulation/qemu-sbsa/Kconfig index 9ea6303ec9c..1f058a43932 100644 --- a/board/emulation/qemu-sbsa/Kconfig +++ b/board/emulation/qemu-sbsa/Kconfig @@ -34,7 +34,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select PCIE_ECAM_GENERIC select SYS_PCI_64BIT select USB - select GIC_V3 + select GICV3 select GIC_V3_ITS select SYS_FLASH_CFI_WIDTH_16BIT imply AHCI_GENERIC -- cgit v1.3.1 From 8918b60e33157dd6abaaf11ea24437da133eed0a Mon Sep 17 00:00:00 2001 From: Mathieu Dubois-Briand Date: Mon, 15 Sep 2025 14:57:02 +0200 Subject: imx93_frdm: Add support for flashing board with UUU Allow to flash a board using NXP UUU utility: - Enable fastboot support on USB. - Add fastboot partition aliases with names used by UUU. Also add extra environment variables used by UUU. - Set 'dofastboot' environment variable based on boot device configuration, allowing to automatically enter fastboot when booting from USB. Signed-off-by: Mathieu Dubois-Briand --- board/freescale/imx93_frdm/imx93_frdm.c | 6 ++++++ board/freescale/imx93_frdm/imx93_frdm.env | 8 ++++++++ configs/imx93_frdm_defconfig | 14 ++++++++++++++ doc/board/nxp/imx93_frdm.rst | 22 ++++++++++++++++++++++ 4 files changed, 50 insertions(+) (limited to 'board') diff --git a/board/freescale/imx93_frdm/imx93_frdm.c b/board/freescale/imx93_frdm/imx93_frdm.c index c74fd85712f..c436ac6aa47 100644 --- a/board/freescale/imx93_frdm/imx93_frdm.c +++ b/board/freescale/imx93_frdm/imx93_frdm.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -55,5 +56,10 @@ int board_late_init(void) env_set("board_rev", "iMX93"); } + if (get_boot_device() == USB_BOOT) { + printf("USB boot detected. Will enter fasboot mode\n"); + env_set_ulong("dofastboot", 1); + } + return 0; } diff --git a/board/freescale/imx93_frdm/imx93_frdm.env b/board/freescale/imx93_frdm/imx93_frdm.env index 528a953c8df..111f38ed72a 100644 --- a/board/freescale/imx93_frdm/imx93_frdm.env +++ b/board/freescale/imx93_frdm/imx93_frdm.env @@ -19,8 +19,16 @@ kernel_addr_r=CONFIG_SYS_LOAD_ADDR loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} boot_os=booti ${loadaddr} - ${fdt_addr_r} +fastboot_partition_alias_all=0:0 +fastboot_partition_alias_bootloader=0.1 +emmc_dev=0 +sd_dev=1 +dofastboot=0 bsp_bootcmd= + if test ${dofastboot} = 1; then + fastboot 0; + fi; echo Running BSP bootcmd ...; mmc dev ${mmcdev}; run mmcargs; diff --git a/configs/imx93_frdm_defconfig b/configs/imx93_frdm_defconfig index 4f837ca9282..eddd36c618d 100644 --- a/configs/imx93_frdm_defconfig +++ b/configs/imx93_frdm_defconfig @@ -30,6 +30,7 @@ CONFIG_EFI_VAR_BUF_SIZE=139264 CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +# CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx93-11x11-frdm.dtb" CONFIG_SYS_CBSIZE=2048 @@ -58,6 +59,7 @@ CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_BIND is not set CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_FUSE=y @@ -91,6 +93,11 @@ CONFIG_ADC_IMX93=y CONFIG_SPL_CLK_IMX93=y CONFIG_CLK_IMX93=y CONFIG_DFU_MMC=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_IMX_RGPIO2P=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y @@ -116,6 +123,13 @@ CONFIG_SYSRESET=y CONFIG_SYSRESET_CMD_POWEROFF=y CONFIG_SYSRESET_PSCI=y CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y CONFIG_ULP_WATCHDOG=y CONFIG_WDT=y CONFIG_SHA384=y diff --git a/doc/board/nxp/imx93_frdm.rst b/doc/board/nxp/imx93_frdm.rst index a1f526fd4cc..3c3e5f49b04 100644 --- a/doc/board/nxp/imx93_frdm.rst +++ b/doc/board/nxp/imx93_frdm.rst @@ -13,6 +13,7 @@ Quick Start - Get ahab-container.img - Build U-Boot - Boot from the SD card +- Boot using USB serial download (uuu) Get and Build the ARM Trusted firmware -------------------------------------- @@ -73,3 +74,24 @@ Boot from the SD card at /dev/ttyACM0. - Power on the board by connecting a USB Type-C cable into the P1 Power USB Port. + +Boot using USB serial download (uuu) +------------------------------------ + +- Configure SW1 boot switches to serial download boot mode: + 0001 SW1[3:0] - ("Serial downloader (USB)" Boot Mode) +- Plug USB Type-C cable into the P2 device port. +- Connect a USB Type-C cable into the P16 Debug USB Port and connect + using a terminal emulator at 115200 bps, 8n1. The console will show up + at /dev/ttyACM0. +- Power on the board by connecting a USB Type-C cable into the P1 + Power USB Port. +- Use NXP Universal Update Utility `NXP Universal Update Utility`_ to boot or + flash the device. E.g. following command can be used to flash an image onto + the eMMC storage: + +.. code-block:: bash + + $ uuu -V -b emmc_all + +.. _`NXP Universal Update Utility`: https://github.com/nxp-imx/mfgtools -- cgit v1.3.1 From cb1292450d89391b56e83e00e4520935f95d403e Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Thu, 18 Sep 2025 08:13:56 +0200 Subject: doc: phytec: update imx8m docs for optee builds OP-TEE configs are enabled by default, change the doc to no longer declare OP-TEE as optional. Also remove CFG_TEE_BENCHMARK as it is no longer present in optee_os. Further, phycore-imx8mm and imx8mm-phygate-tauri-l use different build instructions, so dissolve the common file for building OP-TEE. Reviewed-by: Teresa Remmet Signed-off-by: Yannic Moog --- board/phytec/phycore_imx8mm/MAINTAINERS | 1 - doc/board/phytec/imx8mm-optee-build.rsti | 14 -------------- doc/board/phytec/imx8mm-phygate-tauri-l.rst | 18 ++++++++++++------ doc/board/phytec/imx8mp-libra-fpsc.rst | 1 - doc/board/phytec/phycore-imx8mm.rst | 18 ++++++++++++------ doc/board/phytec/phycore-imx8mp.rst | 16 ++++++---------- 6 files changed, 30 insertions(+), 38 deletions(-) delete mode 100644 doc/board/phytec/imx8mm-optee-build.rsti (limited to 'board') diff --git a/board/phytec/phycore_imx8mm/MAINTAINERS b/board/phytec/phycore_imx8mm/MAINTAINERS index 7631e1cb331..58c5e2d0af9 100644 --- a/board/phytec/phycore_imx8mm/MAINTAINERS +++ b/board/phytec/phycore_imx8mm/MAINTAINERS @@ -9,6 +9,5 @@ F: configs/imx8mm-phygate-tauri-l_defconfig F: configs/phycore-imx8mm_defconfig F: doc/board/phytec/imx8mm-phygate-tauri-l.rst F: doc/board/phytec/index.rst -F: doc/board/phytec/imx8mm-optee-build.rsti F: doc/board/phytec/phycore_imx8mm.rst F: include/configs/phycore_imx8mm.h diff --git a/doc/board/phytec/imx8mm-optee-build.rsti b/doc/board/phytec/imx8mm-optee-build.rsti deleted file mode 100644 index c83de5cc7cf..00000000000 --- a/doc/board/phytec/imx8mm-optee-build.rsti +++ /dev/null @@ -1,14 +0,0 @@ -Build the OP-TEE binary (optional) ----------------------------------- - -.. code-block:: bash - - $ git clone https://github.com/OP-TEE/optee_os.git - $ cd optee_os - $ make CFG_TEE_BENCHMARK=n \ - CROSS_COMPILE=aarch64-linux-gnu- \ - O=out/arm \ - PLATFORM=imx-mx8mmevk \ - CFG_TZDRAM_START=0x56000000 \ - CFG_DDR_SIZE=0x80000000 \ - CFG_UART_BASE=UART3_BASE diff --git a/doc/board/phytec/imx8mm-phygate-tauri-l.rst b/doc/board/phytec/imx8mm-phygate-tauri-l.rst index 0d9e1024f8c..bc58a141e4f 100644 --- a/doc/board/phytec/imx8mm-phygate-tauri-l.rst +++ b/doc/board/phytec/imx8mm-phygate-tauri-l.rst @@ -9,7 +9,7 @@ Quick Start ----------- - Build the ARM Trusted firmware binary -- Build the OP-TEE binary (optional) +- Build the OP-TEE binary - Get ddr firmware - Build U-Boot - Boot @@ -23,12 +23,18 @@ Build the ARM Trusted firmware binary $ cd trusted-firmware-a $ export CROSS_COMPILE=aarch64-linux-gnu- $ export IMX_BOOT_UART_BASE=0x30880000 - $ # with optee - $ make PLAT=imx8mm BL32_BASE=0x56000000 SPD=opteed bl31 - $ # without optee - $ make PLAT=imx8mm bl31 + $ make PLAT=imx8mm BL32_BASE=0xbe000000 SPD=opteed bl31 -.. include:: imx8mm-optee-build.rsti +Build the OP-TEE binary +----------------------- + +.. code-block:: bash + + $ git clone https://github.com/OP-TEE/optee_os.git + $ cd optee_os + $ make CROSS_COMPILE=aarch64-linux-gnu- \ + O=out/arm \ + PLATFORM=imx-mx8mm_phygate_tauri_l Get the ddr firmware -------------------- diff --git a/doc/board/phytec/imx8mp-libra-fpsc.rst b/doc/board/phytec/imx8mp-libra-fpsc.rst index 26752ac1882..87b7a99ee71 100644 --- a/doc/board/phytec/imx8mp-libra-fpsc.rst +++ b/doc/board/phytec/imx8mp-libra-fpsc.rst @@ -40,7 +40,6 @@ Build the OP-TEE binary $ cd optee_os $ make -j $(nproc) \ CROSS_COMPILE=aarch64-linux-gnu- \ - CFG_TEE_BENCHMARK=n \ O=out/arm \ PLATFORM=imx-mx8mp_libra_fpsc diff --git a/doc/board/phytec/phycore-imx8mm.rst b/doc/board/phytec/phycore-imx8mm.rst index 08f5949e02d..f8fa420019c 100644 --- a/doc/board/phytec/phycore-imx8mm.rst +++ b/doc/board/phytec/phycore-imx8mm.rst @@ -9,7 +9,7 @@ Quick Start ----------- - Build the ARM Trusted firmware binary -- Build the OP-TEE binary (optional) +- Build the OP-TEE binary - Get ddr firmware - Build U-Boot - Boot @@ -23,12 +23,18 @@ Build the ARM Trusted firmware binary $ cd trusted-firmware-a $ export CROSS_COMPILE=aarch64-linux-gnu- $ export IMX_BOOT_UART_BASE=0x30880000 - $ # with optee - $ make PLAT=imx8mm BL32_BASE=0x56000000 SPD=opteed bl31 - $ # without optee - $ make PLAT=imx8mm bl31 + $ make PLAT=imx8mm BL32_BASE=0x7e000000 SPD=opteed bl31 -.. include:: imx8mm-optee-build.rsti +Build the OP-TEE binary +----------------------- + +.. code-block:: bash + + $ git clone https://github.com/OP-TEE/optee_os.git + $ cd optee_os + $ make CROSS_COMPILE=aarch64-linux-gnu- \ + O=out/arm \ + PLATFORM=imx-mx8mm_phyboard_polis Get the ddr firmware -------------------- diff --git a/doc/board/phytec/phycore-imx8mp.rst b/doc/board/phytec/phycore-imx8mp.rst index 50be9912653..df087072062 100644 --- a/doc/board/phytec/phycore-imx8mp.rst +++ b/doc/board/phytec/phycore-imx8mp.rst @@ -9,7 +9,7 @@ Quick Start ----------- - Build the ARM Trusted firmware binary -- Build the OP-TEE binary (optional) +- Build the OP-TEE binary - Get ddr firmware - Build U-Boot - Boot @@ -23,23 +23,19 @@ Build the ARM Trusted firmware binary $ cd trusted-firmware-a $ export CROSS_COMPILE=aarch64-linux-gnu- $ export IMX_BOOT_UART_BASE=0x30860000 - $ # with optee - $ make PLAT=imx8mp SPD=opteed bl31 - $ # without optee - $ make PLAT=imx8mp bl31 + $ make PLAT=imx8mp BL32_BASE=0x7e000000 SPD=opteed bl31 -Build the OP-TEE binary (optional) ----------------------------------- +Build the OP-TEE binary +----------------------- .. code-block:: bash $ git clone https://github.com/OP-TEE/optee_os.git $ cd optee_os - $ make CFG_TEE_BENCHMARK=n \ - CROSS_COMPILE=aarch64-linux-gnu- \ + $ make CROSS_COMPILE=aarch64-linux-gnu- \ O=out/arm \ PLATFORM=imx-mx8mp_phyboard_pollux \ - CFG_TZDRAM_START=0x56000000 + CFG_TZDRAM_START=0x7e000000 Get the ddr firmware -------------------- -- cgit v1.3.1 From 998c6cc450e61152b6d0e800989d2d19358e25c2 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 23 Sep 2025 10:14:55 +0800 Subject: imx95: Add get_reset_reason() to retrieve the LM/system last booted/shutdown reasons System Manager provides the last booted and shutdown reasons of the logical machines (LM) and system using the SCMI misc protocol (Protocol ID: 0x84, Message ID: 0xA). This path adds get_reset_reason() to query and print these reasons in SPL and U-Boot. Signed-off-by: Peng Fan Signed-off-by: Alice Guo Reviewed-by: Ye Li --- arch/arm/include/asm/arch-imx9/sys_proto.h | 1 + arch/arm/mach-imx/imx9/scmi/soc.c | 110 +++++++++++++++++++++++++++++ board/freescale/imx95_evk/spl.c | 3 + include/scmi_nxp_protocols.h | 55 +++++++++++++++ 4 files changed, 169 insertions(+) create mode 100644 include/scmi_nxp_protocols.h (limited to 'board') diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h index 455aa95339e..dead7a99a66 100644 --- a/arch/arm/include/asm/arch-imx9/sys_proto.h +++ b/arch/arm/include/asm/arch-imx9/sys_proto.h @@ -21,6 +21,7 @@ int m33_prepare(void); int low_drive_freq_update(void *blob); enum imx9_soc_voltage_mode soc_target_voltage_mode(void); +int get_reset_reason(bool sys, bool lm); #define is_voltage_mode(mode) (soc_target_voltage_mode() == (mode)) diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index f973652d0cb..f04b9255cdb 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -17,8 +17,10 @@ #include #include #include +#include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -468,6 +470,114 @@ err: printf("%s: fuse read err: %d\n", __func__, ret); } +static char *rst_string[32] = { + "cm33_lockup", + "cm33_swreq", + "cm7_lockup", + "cm7_swreq", + "fccu", + "jtag_sw", + "ele", + "tempsense", + "wdog1", + "wdog2", + "wdog3", + "wdog4", + "wdog5", + "jtag", + "cm33_exc", + "bbm", + "sw", + "sm_err", "fusa_sreco", "pmic", "unused", "unused", "unused", + "unused", "unused", "unused", "unused", "unused", "unused", + "unused", "unused", + "por" +}; + +int get_reset_reason(bool sys, bool lm) +{ + struct scmi_imx_misc_reset_reason_in in = { + .flags = MISC_REASON_FLAG_SYSTEM, + }; + + struct scmi_imx_misc_reset_reason_out out = { 0 }; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_IMX_MISC, + .message_id = SCMI_IMX_MISC_RESET_REASON, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + struct udevice *dev; + + ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev); + if (ret) + return ret; + + if (sys) { + ret = devm_scmi_process_msg(dev, &msg); + if (out.status) { + printf("%s:%d for SYS\n", __func__, out.status); + return ret; + } + + if (out.bootflags & MISC_BOOT_FLAG_VLD) { + printf("SYS Boot reason: %s, origin: %ld, errid: %ld\n", + rst_string[out.bootflags & MISC_BOOT_FLAG_REASON], + out.bootflags & MISC_BOOT_FLAG_ORG_VLD ? + FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags) : -1, + out.bootflags & MISC_BOOT_FLAG_ERR_VLD ? + FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags) : -1 + ); + } + if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) { + printf("SYS shutdown reason: %s, origin: %ld, errid: %ld\n", + rst_string[out.bootflags & MISC_SHUTDOWN_FLAG_REASON], + out.bootflags & MISC_SHUTDOWN_FLAG_ORG_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.bootflags) : -1, + out.bootflags & MISC_SHUTDOWN_FLAG_ERR_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.bootflags) : -1 + ); + } + } + + if (lm) { + in.flags = 0; + memset(&out, 0, sizeof(struct scmi_imx_misc_reset_reason_out)); + + ret = devm_scmi_process_msg(dev, &msg); + if (out.status) { + printf("%s:%d for LM\n", __func__, out.status); + return ret; + } + + if (out.bootflags & MISC_BOOT_FLAG_VLD) { + printf("LM Boot reason: %s, origin: %ld, errid: %ld\n", + rst_string[out.bootflags & MISC_BOOT_FLAG_REASON], + out.bootflags & MISC_BOOT_FLAG_ORG_VLD ? + FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags) : -1, + out.bootflags & MISC_BOOT_FLAG_ERR_VLD ? + FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags) : -1 + ); + } + + if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) { + printf("LM shutdown reason: %s, origin: %ld, errid: %ld\n", + rst_string[out.bootflags & MISC_SHUTDOWN_FLAG_REASON], + out.bootflags & MISC_SHUTDOWN_FLAG_ORG_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.bootflags) : -1, + out.bootflags & MISC_SHUTDOWN_FLAG_ERR_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.bootflags) : -1 + ); + } + } + + return 0; +} + const char *get_imx_type(u32 imxtype) { switch (imxtype) { diff --git a/board/freescale/imx95_evk/spl.c b/board/freescale/imx95_evk/spl.c index 08f4da0bb73..3d64097b4c7 100644 --- a/board/freescale/imx95_evk/spl.c +++ b/board/freescale/imx95_evk/spl.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -65,5 +66,7 @@ void board_init_f(ulong dummy) debug("SOC: 0x%x\n", gd->arch.soc_rev); debug("LC: 0x%x\n", gd->arch.lifecycle); + get_reset_reason(true, false); + board_init_r(NULL, 0); } diff --git a/include/scmi_nxp_protocols.h b/include/scmi_nxp_protocols.h new file mode 100644 index 00000000000..fe6ecd6a7cf --- /dev/null +++ b/include/scmi_nxp_protocols.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright 2025 NXP + */ + +#ifndef _SCMI_NXP_PROTOCOLS_H +#define _SCMI_NXP_PROTOCOLS_H + +#include +#include + +enum scmi_imx_protocol { + SCMI_IMX_PROTOCOL_ID_MISC = 0x84, +}; + +#define SCMI_PAYLOAD_LEN 100 + +#define SCMI_ARRAY(X, Y) ((SCMI_PAYLOAD_LEN - (X)) / sizeof(Y)) + +#define SCMI_IMX_MISC_RESET_REASON 0xA + +struct scmi_imx_misc_reset_reason_in { +#define MISC_REASON_FLAG_SYSTEM BIT(0) + u32 flags; +}; + +struct scmi_imx_misc_reset_reason_out { + s32 status; + /* Boot reason flags */ +#define MISC_BOOT_FLAG_VLD BIT(31) +#define MISC_BOOT_FLAG_ORG_VLD BIT(28) +#define MISC_BOOT_FLAG_ORIGIN GENMASK(27, 24) +#define MISC_BOOT_FLAG_O_SHIFT 24 +#define MISC_BOOT_FLAG_ERR_VLD BIT(23) +#define MISC_BOOT_FLAG_ERR_ID GENMASK(22, 8) +#define MISC_BOOT_FLAG_E_SHIFT 8 +#define MISC_BOOT_FLAG_REASON GENMASK(7, 0) + u32 bootflags; + /* Shutdown reason flags */ +#define MISC_SHUTDOWN_FLAG_VLD BIT(31) +#define MISC_SHUTDOWN_FLAG_EXT_LEN GENMASK(30, 29) +#define MISC_SHUTDOWN_FLAG_ORG_VLD BIT(28) +#define MISC_SHUTDOWN_FLAG_ORIGIN GENMASK(27, 24) +#define MISC_SHUTDOWN_FLAG_O_SHIFT 24 +#define MISC_SHUTDOWN_FLAG_ERR_VLD BIT(23) +#define MISC_SHUTDOWN_FLAG_ERR_ID GENMASK(22, 8) +#define MISC_SHUTDOWN_FLAG_E_SHIFT 8 +#define MISC_SHUTDOWN_FLAG_REASON GENMASK(7, 0) + u32 shutdownflags; + /* Array of extended info words */ +#define MISC_MAX_EXTINFO SCMI_ARRAY(16, u32) + u32 extInfo[MISC_MAX_EXTINFO]; +}; + +#endif -- cgit v1.3.1 From 3d4e14f4c903819b15ec7e83a29d175692557b3f Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 23 Sep 2025 10:15:04 +0800 Subject: imx94_evk: Add i.MX943 EVK board support Add board-level code and defconfig for the i.MX943 EVK board, supporting multiple SOM variants: 19x19 LPDDR5, 19x19 LPDDR4 and 15x15 LPDDR4. Signed-off-by: Ye Li Signed-off-by: Alice Guo Acked-by: Peng Fan Reviewed-by: Jacky Bai --- arch/arm/mach-imx/Makefile | 2 +- arch/arm/mach-imx/imx9/Kconfig | 8 +++ board/freescale/imx94_evk/Kconfig | 12 ++++ board/freescale/imx94_evk/MAINTAINERS | 6 ++ board/freescale/imx94_evk/Makefile | 11 +++ board/freescale/imx94_evk/imx94_evk.c | 41 ++++++++++++ board/freescale/imx94_evk/imx94_evk.env | 100 +++++++++++++++++++++++++++ board/freescale/imx94_evk/spl.c | 81 ++++++++++++++++++++++ configs/imx943_evk_defconfig | 115 ++++++++++++++++++++++++++++++++ doc/board/nxp/imx943_evk.rst | 112 +++++++++++++++++++++++++++++++ doc/board/nxp/index.rst | 1 + include/configs/imx94_evk.h | 24 +++++++ 12 files changed, 512 insertions(+), 1 deletion(-) create mode 100644 board/freescale/imx94_evk/Kconfig create mode 100644 board/freescale/imx94_evk/MAINTAINERS create mode 100644 board/freescale/imx94_evk/Makefile create mode 100644 board/freescale/imx94_evk/imx94_evk.c create mode 100644 board/freescale/imx94_evk/imx94_evk.env create mode 100644 board/freescale/imx94_evk/spl.c create mode 100644 configs/imx943_evk_defconfig create mode 100644 doc/board/nxp/imx943_evk.rst create mode 100644 include/configs/imx94_evk.h (limited to 'board') diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index fa2cdaba144..1efe690e876 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -223,7 +223,7 @@ endif ifeq ($(CONFIG_ARCH_IMX9)$(CONFIG_ARCH_IMX8ULP), y) -ifneq ($(and $(CONFIG_IMX95),$(CONFIG_BINMAN)),) +ifneq ($(and $(CONFIG_BINMAN),$(or $(CONFIG_IMX95),$(CONFIG_IMX94))),) SPL: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) else diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index f2011448c23..48f458fa55c 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -106,6 +106,13 @@ config TARGET_IMX95_19X19_EVK imply BOOTSTD_FULL imply OF_UPSTREAM +config TARGET_IMX943_EVK + bool "imx943_evk" + select IMX94 + imply BOOTSTD_BOOTCOMMAND + imply BOOTSTD_FULL + imply OF_UPSTREAM + endchoice source "board/freescale/imx91_evk/Kconfig" @@ -114,6 +121,7 @@ source "board/freescale/imx93_frdm/Kconfig" source "board/freescale/imx93_qsb/Kconfig" source "board/phytec/phycore_imx93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" +source "board/freescale/imx94_evk/Kconfig" source "board/freescale/imx95_evk/Kconfig" endif diff --git a/board/freescale/imx94_evk/Kconfig b/board/freescale/imx94_evk/Kconfig new file mode 100644 index 00000000000..a4237244ace --- /dev/null +++ b/board/freescale/imx94_evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX943_EVK + +config SYS_BOARD + default "imx94_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx94_evk" + +endif diff --git a/board/freescale/imx94_evk/MAINTAINERS b/board/freescale/imx94_evk/MAINTAINERS new file mode 100644 index 00000000000..95309430734 --- /dev/null +++ b/board/freescale/imx94_evk/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX94 EVK BOARD +M: Alice Guo +S: Maintained +F: board/freescale/imx94_evk/ +F: include/configs/imx94_evk.h +F: configs/imx943_evk_defconfig diff --git a/board/freescale/imx94_evk/Makefile b/board/freescale/imx94_evk/Makefile new file mode 100644 index 00000000000..ca31602f6ba --- /dev/null +++ b/board/freescale/imx94_evk/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx94_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/freescale/imx94_evk/imx94_evk.c b/board/freescale/imx94_evk/imx94_evk.c new file mode 100644 index 00000000000..28d512ac5f3 --- /dev/null +++ b/board/freescale/imx94_evk/imx94_evk.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include +#include +#include +#include +#include + +int board_early_init_f(void) +{ + init_uart_clk(0); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + board_late_mmc_env_init(); + + env_set("sec_boot", "no"); + + if (IS_ENABLED(CONFIG_AHAB_BOOT)) + env_set("sec_boot", "yes"); + + return 0; +} + +int board_phys_sdram_size(phys_size_t *size) +{ + *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE; + + return 0; +} diff --git a/board/freescale/imx94_evk/imx94_evk.env b/board/freescale/imx94_evk/imx94_evk.env new file mode 100644 index 00000000000..2baf1bbadcb --- /dev/null +++ b/board/freescale/imx94_evk/imx94_evk.env @@ -0,0 +1,100 @@ +#ifdef CONFIG_AHAB_BOOT +sec_boot=yes +#else +sec_boot=no +#endif + +jh_root_dtb=imx943-evk-root.dtb +jh_mmcboot=setenv fdtfile ${jh_root_dtb}; + setenv jh_clk kvm.enable_virt_at_load=false cpuidle.off=1 clk_ignore_unused kvm-arm.mode=nvhe; + setenv jh_root_mem 0x60000000@0x90000000,0x100000000@0x100000000; + if run loadimage; then + run mmcboot; + else run jh_netboot; fi; +jh_netboot=setenv fdtfile ${jh_root_dtb}; + setenv jh_root_mem 0x60000000@0x90000000,0x100000000@0x100000000; + setenv jh_clk kvm.enable_virt_at_load=false cpuidle.off=1 clk_ignore_unused kvm-arm.mode=nvhe; run netboot; + +initrd_addr=0x93800000 +emmc_dev=0 +sd_dev=1 +scriptaddr=0x93500000 +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +image=Image +splashimage=0xA0000000 +console=ttyLP0,115200 earlycon +fdt_addr_r=0x93000000 +fdt_addr=0x93000000 +cntr_addr=0xA8000000 +cntr_file=os_cntr_signed.bin +boot_fit=no +fdtfile=CONFIG_DEFAULT_FDT_FILE +bootm_size=0x10000000 +mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcautodetect=yes +mmcargs=setenv bootargs ${jh_clk} ${mcore_args} console=${console} root=${mmcroot} +prepare_mcore=setenv mcore_args pd_ignore_unused; +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} +auth_os=booti ${cntr_addr} +boot_os=booti ${loadaddr} - ${fdt_addr_r}; +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${sec_boot} = yes; then + run auth_os; + else + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if run loadfdt; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; + fi; +netargs=setenv bootargs ${jh_clk} ${mcore_args} console=${console} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if test ${sec_boot} = yes; then + ${get_cmd} ${cntr_addr} ${cntr_file}; + run auth_os; + else + ${get_cmd} ${loadaddr} ${image}; + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; + fi; +bsp_bootcmd=echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; if mmc rescan; then + if run loadbootscript; then + run bootscript; + else + if test ${sec_boot} = yes; then + if run loadcntr; then + run mmcboot; + else run netboot; + fi; + else + if run loadimage; then + run mmcboot; + else run netboot; + fi; + fi; + fi; + fi; diff --git a/board/freescale/imx94_evk/spl.c b/board/freescale/imx94_evk/spl.c new file mode 100644 index 00000000000..341b165b3c8 --- /dev/null +++ b/board/freescale/imx94_evk/spl.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + case QSPI_BOOT: + return BOOT_DEVICE_SPI; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_board_init(void) +{ + int ret; + + puts("Normal Boot\n"); + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); +} + +/* SCMI support by default */ +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + if (IS_ENABLED(CONFIG_SPL_RECOVER_DATA_SECTION) && + IS_ENABLED(CONFIG_SPL_BUILD)) + spl_save_restore_data(); + + timer_init(); + + spl_early_init(); + + /* Need enable SCMI drivers and ELE driver before enabling console */ + ret = imx9_probe_mu(); + if (ret) + hang(); /* if MU not probed, nothing can output, just hang here */ + + arch_cpu_init(); + + board_early_init_f(); + + preloader_console_init(); + + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + + get_reset_reason(true, false); + + board_init_r(NULL, 0); +} diff --git a/configs/imx943_evk_defconfig b/configs/imx943_evk_defconfig new file mode 100644 index 00000000000..27230ed3207 --- /dev/null +++ b/configs/imx943_evk_defconfig @@ -0,0 +1,115 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x90200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="imx94_evk" +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx943-evk" +CONFIG_TARGET_IMX943_EVK=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_TEXT_BASE=0x20480000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x204d6000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SYS_LOAD_ADDR=0x90400000 +CONFIG_SPL=y +CONFIG_SPL_RECOVER_DATA_SECTION=y +CONFIG_PCI=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_SYS_MEMTEST_START=0x90000000 +CONFIG_SYS_MEMTEST_END=0xA0000000 +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx943-evk.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x30000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x93200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_THERMAL=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_CLK_CCF=y +CONFIG_CLK_SCMI=y +CONFIG_SPL_CLK_SCMI=y +CONFIG_SPL_FIRMWARE=y +# CONFIG_SCMI_AGENT_SMCCC is not set +CONFIG_IMX_RGPIO2P=y +CONFIG_IMX_MU_MBOX=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX_SCMI=y +CONFIG_POWER_DOMAIN=y +CONFIG_SCMI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_ULP_WATCHDOG=y diff --git a/doc/board/nxp/imx943_evk.rst b/doc/board/nxp/imx943_evk.rst new file mode 100644 index 00000000000..651db08a0f7 --- /dev/null +++ b/doc/board/nxp/imx943_evk.rst @@ -0,0 +1,112 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +imx943_evk +======================= + +U-Boot for the NXP i.MX943 19x19 EVK board + +Quick Start +----------- + +- Get ahab-container.img +- Get DDR PHY Firmware Images +- Get and Build OEI Images +- Get and Build System Manager Image +- Get and Build the ARM Trusted Firmware +- Build the Bootloader Image +- Boot + +Get ahab-container.img +-------------------------------------- + +Note: srctree is U-Boot source directory + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-2.0.2-89161a8.bin + $ sh firmware-ele-imx-2.0.2-89161a8.bin --auto-accept + $ cp firmware-ele-imx-2.0.2-89161a8/mx943a0-ahab-container.img $(srctree) + +Get DDR PHY Firmware Images +-------------------------------------- + +Note: srctree is U-Boot source directory + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin + $ sh firmware-imx-8.28-994fa14.bin --auto-accept + $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr5*v202409.bin $(srctree) + +Get and Build OEI Images +-------------------------------------- + +Note: srctree is U-Boot source directory +Get OEI from: https://github.com/nxp-imx/imx-oei +branch: master + +.. code-block:: bash + + $ sudo apt -y install make gcc g++-multilib srecord + $ wget https://developer.arm.com/-/media/Files/downloads/gnu/13.3.rel1/binrel/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz + $ tar xvf arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz + $ export TOOLS=$PWD + $ git clone -b master https://github.com/nxp-imx/imx-oei.git + $ cd imx-oei + $ make board=mx943lp5-19 oei=ddr DEBUG=1 all + $ cp build/mx943lp5-19/ddr/oei-m33-ddr.bin $(srctree) + +Get and Build System Manager Image +-------------------------------------- + +Note: srctree is U-Boot source directory +Get System Manager from: https://github.com/nxp-imx/imx-sm +branch: master + +.. code-block:: bash + + $ sudo apt -y install make gcc g++-multilib srecord + $ wget https://developer.arm.com/-/media/Files/downloads/gnu/13.3.rel1/binrel/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz + $ tar xvf arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz + $ export TOOLS=$PWD + $ git clone -b master https://github.com/nxp-imx/imx-sm.git + $ cd imx-sm + $ make config=mx94evk all + $ cp build/mx94evk/m33_image.bin $(srctree) + +Get and Build the ARM Trusted Firmware +-------------------------------------- + +Note: srctree is U-Boot source directory +Get ATF from: https://github.com/nxp-imx/imx-atf/ +branch: lf_v2.12 + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-poky-linux- + $ unset LDFLAGS + $ unset AS + $ git clone -b lf_v2.12 https://github.com/nxp-imx/imx-atf.git + $ cd imx-atf + $ make PLAT=imx94 bl31 + $ cp build/imx94/release/bl31.bin $(srctree) + +Build the Bootloader Image +-------------------------- + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-poky-linux- + $ make imx943_evk_defconfig + $ make + +Copy flash.bin to the MicroSD card: + +.. code-block:: bash + + $ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync + +Boot +---- + +Set i.MX943 boot device to MicroSD card diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst index aa7d857346d..670501164b5 100644 --- a/doc/board/nxp/index.rst +++ b/doc/board/nxp/index.rst @@ -16,6 +16,7 @@ NXP Semiconductors imx93_9x9_qsb imx93_11x11_evk imx93_frdm + imx943_evk imx95_evk imxrt1020-evk imxrt1050-evk diff --git a/include/configs/imx94_evk.h b/include/configs/imx94_evk.h new file mode 100644 index 00000000000..f93c3c4e4a8 --- /dev/null +++ b/include/configs/imx94_evk.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 NXP + */ + +#ifndef __IMX94_EVK_H +#define __IMX94_EVK_H + +#include +#include +#include + +#define CFG_SYS_INIT_RAM_ADDR 0x90000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x90000000 +#define PHYS_SDRAM 0x90000000 +#define PHYS_SDRAM_SIZE 0x70000000UL /* 2GB - 256MB DDR */ +#define PHYS_SDRAM_2_SIZE 0x180000000 /* 8GB */ + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG3_BASE_ADDR + +#endif -- cgit v1.3.1 From 2767386806c254820ea22a812bb02e5405495a29 Mon Sep 17 00:00:00 2001 From: Debbie Horsfall Date: Wed, 17 Sep 2025 17:22:21 +0100 Subject: vexpress64: Set the DM_RNG property Enable the DM_RNG virtio random number generator driver in order to consume entropy within U-Boot. This allows U-Boot to inject entropy to the kernel via UEFI, so the kernel can use that early, for instance for address layout randomisation, or when the kernel does not provide an entropy driver itself. Signed-off-by: Debbie Horsfall Reviewed-by: Andre Przywara --- board/armltd/vexpress64/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'board') diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 7e8709444fe..610ab0ac37d 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -21,6 +21,8 @@ config VEXPRESS64_BASE_MODEL imply EFI_SET_TIME if DM_RTC select LINUX_KERNEL_IMAGE_HEADER select POSITION_INDEPENDENT + imply DM_RNG + imply RNG_ARM_RNDR choice prompt "VExpress64 board variant" -- cgit v1.3.1 From 1f3f1e090a2695e0b17cbf9dc50ccb59d100458f Mon Sep 17 00:00:00 2001 From: Debbie Horsfall Date: Wed, 17 Sep 2025 17:22:22 +0100 Subject: arm: vexpress64: Enable SYSRESET and SYSRESET_PSCI Select SYSRESET on Vexpress64 to enable system reset to support other features, such as capsule-on-disk. Select SYSRESET_PSCI if PSCI is inferred from the firmware (via ARM_PSCI_FW). Select ARM_SMCCC for Vexpress64 boards which in turn selects ARM_PSCI_FW. The sysreset uclass unconditionally implements a reset_cpu() function. Remove the empty reset_cpu() in vexpress64 board code. Signed-off-by: Debbie Horsfall --- arch/arm/Kconfig | 2 ++ board/armltd/vexpress64/Kconfig | 2 ++ board/armltd/vexpress64/vexpress64.c | 5 ----- 3 files changed, 4 insertions(+), 5 deletions(-) (limited to 'board') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 16db046f4b8..0a1bd6958fe 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1418,6 +1418,8 @@ config ARCH_VEXPRESS64 select MTD_NOR_FLASH if MTD select FLASH_CFI_DRIVER if MTD select ENV_IS_IN_FLASH if MTD + select SYSRESET + select SYSRESET_PSCI if ARM_PSCI_FW imply DISTRO_DEFAULTS config TARGET_CORSTONE1000 diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 610ab0ac37d..9ef3fa1b379 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -23,6 +23,7 @@ config VEXPRESS64_BASE_MODEL select POSITION_INDEPENDENT imply DM_RNG imply RNG_ARM_RNDR + select ARM_SMCCC choice prompt "VExpress64 board variant" @@ -48,6 +49,7 @@ config TARGET_VEXPRESS64_JUNO select USB_EHCI_GENERIC if USB select USB_OHCI_HCD if USB select USB_OHCI_GENERIC if USB + select ARM_SMCCC imply OF_HAS_PRIOR_STAGE endchoice diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 0b75c1358f0..e8f1c2fe9fe 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -206,11 +206,6 @@ int board_fdt_blob_setup(void **fdtp) #endif #endif -/* Actual reset is done via PSCI. */ -void reset_cpu(void) -{ -} - /* * Board specific ethernet initialization routine. */ -- cgit v1.3.1 From d521fa32cc692a44c7c11d4b2a86f371d614e727 Mon Sep 17 00:00:00 2001 From: Viacheslav Bocharov Date: Wed, 3 Sep 2025 14:06:03 +0300 Subject: ARM: amlogic: fix JetHub D1 eth mac fallback generation JetHome has allocated a special range for MAC fallback on JetHub D1/D1+ devices. Signed-off-by: Viacheslav Bocharov Link: https://lore.kernel.org/r/20250903110726.546083-1-adeep@lexina.in Signed-off-by: Neil Armstrong --- board/amlogic/jethub-j100/jethub-j100.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) (limited to 'board') diff --git a/board/amlogic/jethub-j100/jethub-j100.c b/board/amlogic/jethub-j100/jethub-j100.c index 9e87fb9f9d7..79732864d03 100644 --- a/board/amlogic/jethub-j100/jethub-j100.c +++ b/board/amlogic/jethub-j100/jethub-j100.c @@ -19,21 +19,17 @@ int misc_init_r(void) { u8 mac_addr[ARP_HLEN + 1]; char serial[SM_SERIAL_SIZE]; - u32 sid; + u16 sid; if (!meson_sm_get_serial(serial, SM_SERIAL_SIZE)) { - sid = crc32(0, (unsigned char *)serial, SM_SERIAL_SIZE); - /* Ensure the NIC specific bytes of the mac are not all 0 */ - if ((sid & 0xffff) == 0) - sid |= 0x800000; - - /* OUI registered MAC address */ - mac_addr[0] = 0x10; - mac_addr[1] = 0x27; - mac_addr[2] = 0xBE; - mac_addr[3] = (sid >> 16) & 0xff; - mac_addr[4] = (sid >> 8) & 0xff; - mac_addr[5] = (sid >> 0) & 0xff; + sid = crc32(0, (unsigned char *)serial, SM_SERIAL_SIZE) & 0xFFFF; + /* OUI registered fallback MAC address */ + mac_addr[0] = 0xF0; + mac_addr[1] = 0x57; + mac_addr[2] = 0x8D; + mac_addr[3] = 0x00; + mac_addr[4] = (sid >> 8) & 0xFF; + mac_addr[5] = sid & 0xFF; mac_addr[ARP_HLEN] = '\0'; eth_env_set_enetaddr("ethaddr", mac_addr); -- cgit v1.3.1