From fac7fc43cfc63a778f8385917cf86fae7a1eb446 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 4 Mar 2022 16:30:09 +0000 Subject: vexpress64: Kconfig: move board definitions out of arch/arm At the moment we define three "VExpress64" boards in arch/arm/Kconfig, plus have a second Kconfig file in board/armltd/Kconfig. One of those three boards is actually bogus (TARGET_VEXPRESS64_AEMV8A), that stanza looks like being forgotten in a previous cleanup. To remove the clutter from the generic Kconfig file, just define some ARCH_VEXPRESS64 symbol there, enable some common options, and do the board/model specific configuration in the board/armltd Kconfig file. That allows to streamline and fine tune the configuration later, and to also pull a lot of "non user choices" out of the defconfigs. Signed-off-by: Andre Przywara --- board/armltd/vexpress64/Kconfig | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 4aab3f092ec..55fe0118e1b 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -1,4 +1,4 @@ -if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO +if ARCH_VEXPRESS64 config SYS_BOARD default "vexpress64" @@ -9,6 +9,24 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "vexpress_aemv8" +choice + prompt "VExpress64 board variant" + +config TARGET_VEXPRESS64_BASE_FVP + bool "Support Versatile Express ARMv8a FVP BASE model" + select SEMIHOSTING + +config TARGET_VEXPRESS64_JUNO + bool "Support Versatile Express Juno Development Platform" + select DM_ETH + select USB + select OF_CONTROL + select CLK + select BLK + imply OF_HAS_PRIOR_STAGE + +endchoice + config JUNO_DTB_PART string "NOR flash partition holding DTB" default "board.dtb" -- cgit v1.3.1 From c0fce929564f996f6f21418827c48519eb79d1b6 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 4 Mar 2022 16:30:11 +0000 Subject: vexpress64: fvp: enable OF_CONTROL The FVP base model is relying on a DT for Linux operation, so there is no reason we would need to rely on hardcoded information for U-Boot. Letting U-Boot use a DT will open up the usage of actual peripherals, beyond the support for semihosting only. Enable OF_CONTROL in the Kconfig, and use the latest dts files from Linux. Depending on whether we use the boot-wrapper or TF-A, there is already a DTB provided or not, respectively. To cover the boot-wrapper, we add an arm64 Linux kernel header, which allows the boot-wrapper to treat U-Boot like a Linux kernel. U-Boot will find the pointer to the DTB in x0, and will use it. Even though TF-A carries a DT, at the moment this is not made available to non-secure world, so to not break users, we use the U-Boot provided DTB copy in that case. For some reason TF-A puts some DT like structure at the address x0 is pointing at, but that is very small and doesn't carry any hardware information. Make the code to ignore those small DTBs. Signed-off-by: Andre Przywara --- arch/arm/Kconfig | 2 ++ arch/arm/dts/Makefile | 1 + board/armltd/vexpress64/Kconfig | 8 ++++++-- board/armltd/vexpress64/vexpress64.c | 8 +++++++- configs/vexpress_aemv8a_semi_defconfig | 2 +- 5 files changed, 17 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8f70d5d5a5a..0691292ea6c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1256,6 +1256,8 @@ config ARCH_VEXPRESS64 select DM select DM_SERIAL select PL01X_SERIAL + select OF_CONTROL + select CLK config TARGET_TOTAL_COMPUTE bool "Support Total Compute Platform" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index beaaf15131c..fe726d422be 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1185,6 +1185,7 @@ dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb # TODO(Linus Walleij ): Should us a single vexpress # Kconfig option to build all of these. See examples above. dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb +dtb-$(CONFIG_TARGET_VEXPRESS64_BASE_FVP) += fvp-base-revc.dtb dtb-$(CONFIG_TARGET_VEXPRESS64_JUNO) += juno-r2.dtb dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 55fe0118e1b..34126446a7d 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -15,13 +15,14 @@ choice config TARGET_VEXPRESS64_BASE_FVP bool "Support Versatile Express ARMv8a FVP BASE model" select SEMIHOSTING + select LINUX_KERNEL_IMAGE_HEADER + select POSITION_INDEPENDENT + select OF_BOARD config TARGET_VEXPRESS64_JUNO bool "Support Versatile Express Juno Development Platform" select DM_ETH select USB - select OF_CONTROL - select CLK select BLK imply OF_HAS_PRIOR_STAGE @@ -34,4 +35,7 @@ config JUNO_DTB_PART The ARM partition name in the NOR flash memory holding the device tree blob to configure U-Boot. +config LNX_KRNL_IMG_TEXT_OFFSET_BASE + default SYS_TEXT_BASE + endif diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 5e22e89824e..7d5e5516f9f 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -168,11 +168,17 @@ void *board_fdt_blob_setup(int *err) } #endif - if (fdt_magic(prior_stage_fdt_address) == FDT_MAGIC) { + if (fdt_magic(prior_stage_fdt_address) == FDT_MAGIC && + fdt_totalsize(prior_stage_fdt_address) > 0x100) { *err = 0; return (void *)prior_stage_fdt_address; } + if (fdt_magic(gd->fdt_blob) == FDT_MAGIC) { + *err = 0; + return (void *)gd->fdt_blob; + } + *err = -ENXIO; return NULL; } diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index 959b3b3461b..dd06a1c1fb5 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_DEFAULT_DEVICE_TREE="fvp-base-revc" CONFIG_IDENT_STRING=" vexpress_aemv8a" CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xff000000 @@ -46,4 +47,3 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y -CONFIG_OF_LIBFDT=y -- cgit v1.3.1 From 5865038257d1a38dd71f8107e4510f3c0c0dd584 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 4 Mar 2022 16:30:13 +0000 Subject: vexpress64: move hardware setting from defconfig to Kconfig The defconfigs for the Arm Juno board and the FVP model are quite large, setting a lot of platform-fixed variables like SYS_TEXT_BASE. As those values are not really a user choice, let's provide default values for them in our Kconfig file, so a lot of cruft can be removed from the defconfig files. This also moves the driver selection out of there, since this is again not something a user should really decide on. Instead we allow users to enable or disable subsystems, and select the appropriate drivers based on that in the Kconfig file. Signed-off-by: Andre Przywara --- arch/arm/Kconfig | 4 ++++ board/armltd/vexpress64/Kconfig | 41 +++++++++++++++++++++++++++++++--- configs/vexpress_aemv8a_juno_defconfig | 21 ++--------------- configs/vexpress_aemv8a_semi_defconfig | 10 --------- 4 files changed, 44 insertions(+), 32 deletions(-) (limited to 'board') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0691292ea6c..7e613c7ed78 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1258,6 +1258,10 @@ config ARCH_VEXPRESS64 select PL01X_SERIAL select OF_CONTROL select CLK + select BLK + select MTD_NOR_FLASH if MTD + select FLASH_CFI_DRIVER if MTD + select ENV_IS_IN_FLASH if MTD config TARGET_TOTAL_COMPUTE bool "Support Total Compute Platform" diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 34126446a7d..512bbbe72e6 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -15,15 +15,24 @@ choice config TARGET_VEXPRESS64_BASE_FVP bool "Support Versatile Express ARMv8a FVP BASE model" select SEMIHOSTING + select VIRTIO_BLK if VIRTIO_MMIO + select VIRTIO_NET if VIRTIO_MMIO + select DM_ETH if VIRTIO_NET select LINUX_KERNEL_IMAGE_HEADER select POSITION_INDEPENDENT select OF_BOARD config TARGET_VEXPRESS64_JUNO bool "Support Versatile Express Juno Development Platform" - select DM_ETH - select USB - select BLK + select PCIE_ECAM_GENERIC if PCI + select SATA_SIL + select SMC911X if DM_ETH + select SMC911X_32_BIT if SMC911X + select CMD_USB if USB + select USB_EHCI_HCD if USB + select USB_EHCI_GENERIC if USB + select USB_OHCI_HCD if USB + select USB_OHCI_GENERIC if USB imply OF_HAS_PRIOR_STAGE endchoice @@ -38,4 +47,30 @@ config JUNO_DTB_PART config LNX_KRNL_IMG_TEXT_OFFSET_BASE default SYS_TEXT_BASE +config SYS_TEXT_BASE + default 0x88000000 if TARGET_VEXPRESS64_BASE_FVP + default 0xe0000000 if TARGET_VEXPRESS64_JUNO + +config SYS_MALLOC_LEN + default 0x810000 if TARGET_VEXPRESS64_JUNO + default 0x840000 if TARGET_VEXPRESS64_BASE_FVP + +config SYS_MALLOC_F_LEN + default 0x2000 + +config SYS_LOAD_ADDR + default 0x90000000 + +config ENV_ADDR + default 0x0BFC0000 if TARGET_VEXPRESS64_JUNO + default 0x0FFC0000 if TARGET_VEXPRESS64_BASE_FVP + +config ENV_SIZE + default 0x10000 if TARGET_VEXPRESS64_JUNO + default 0x40000 + +config ENV_SECT_SIZE + default 0x10000 if TARGET_VEXPRESS64_JUNO + default 0x40000 + endif diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index 1f8f101f211..a5d72474673 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -1,11 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_VEXPRESS64=y -CONFIG_SYS_TEXT_BASE=0xe0000000 -CONFIG_SYS_MALLOC_LEN=0x810000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x10000 -CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="juno-r2" CONFIG_IDENT_STRING=" vexpress_aemv8a" CONFIG_TARGET_VEXPRESS64_JUNO=y @@ -13,7 +8,6 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xff000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y -CONFIG_SYS_LOAD_ADDR=0x90000000 CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/sda2 rw rootwait earlycon=pl011,0x7ff80000 debug user_debug=31 androidboot.hardware=juno loglevel=9" @@ -28,7 +22,6 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y CONFIG_CMD_SATA=y -CONFIG_CMD_USB=y # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_BOOTFILESIZE=y @@ -36,21 +29,11 @@ CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_CACHE=y # CONFIG_CMD_SLEEP is not set CONFIG_CMD_UBI=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xBFC0000 -CONFIG_SATA_SIL=y # CONFIG_MMC is not set CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y -CONFIG_SMC911X=y -CONFIG_SMC911X_32_BIT=y +CONFIG_DM_ETH=y CONFIG_PCI=y -CONFIG_PCIE_ECAM_GENERIC=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB=y diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index dd06a1c1fb5..b47aba2bc35 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -1,19 +1,13 @@ CONFIG_ARM=y # CONFIG_ARM64_CRC32 is not set CONFIG_ARCH_VEXPRESS64=y -CONFIG_SYS_TEXT_BASE=0x88000000 -CONFIG_SYS_MALLOC_LEN=0x840000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DEFAULT_DEVICE_TREE="fvp-base-revc" CONFIG_IDENT_STRING=" vexpress_aemv8a" CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xff000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y -CONFIG_SYS_LOAD_ADDR=0x90000000 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y @@ -38,12 +32,8 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xFFC0000 # CONFIG_MMC is not set CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y -- cgit v1.3.1 From 30cacb8123459328c46c25f65196bb4885dcdb05 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 4 Mar 2022 16:30:16 +0000 Subject: vexpress64: generalise page table generation In preparation for the ARMv8-R64 FVP support, which has DRAM mapped at 0x0, generalise the page table generation, by using symbolic names for the address ranges instead of fixed numbers. We already define the base of the DRAM and MMIO regions, so just use those symbols in the page table description. Rename V2M_BASE to the more speaking V2M_DRAM_BASE on the way. On the VExpress memory map, the address space right after 4GB is of no particular interest to software, as the whole of DRAM is mapped at 32GB instead. The first 2 GB alias to the lower 2GB of DRAM mapped below 4GB, so we skip this part and map some more of the high DRAM, should anyone need it. Signed-off-by: Andre Przywara --- board/armltd/vexpress64/vexpress64.c | 24 ++++++++++++++++++------ include/configs/vexpress_aemv8.h | 4 ++-- 2 files changed, 20 insertions(+), 8 deletions(-) (limited to 'board') diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 7d5e5516f9f..c3ad1fcc78a 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include "pcie.h" #include @@ -38,16 +39,27 @@ U_BOOT_DRVINFO(vexpress_serials) = { static struct mm_region vexpress64_mem_map[] = { { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, + .virt = V2M_PA_BASE, + .phys = V2M_PA_BASE, + .size = SZ_2G, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0xff80000000UL, + .virt = V2M_DRAM_BASE, + .phys = V2M_DRAM_BASE, + .size = SZ_2G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* + * DRAM beyond 2 GiB is located high. Let's map just some + * of it, although U-Boot won't realistically use it, and + * the actual available amount might be smaller on the model. + */ + .virt = 0x880000000UL, /* 32 + 2 GiB */ + .phys = 0x880000000UL, + .size = 6UL * SZ_1G, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 74060c63490..e0f9bbeb16c 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -20,7 +20,7 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* CS register bases for the original memory map. */ -#define V2M_BASE 0x80000000 +#define V2M_DRAM_BASE 0x80000000 #define V2M_PA_BASE 0x00000000 #define V2M_PA_CS0 (V2M_PA_BASE + 0x00000000) @@ -100,7 +100,7 @@ #endif /* Physical Memory Map */ -#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1 (V2M_DRAM_BASE) /* SDRAM Bank #1 */ /* Top 16MB reserved for secure world use */ #define DRAM_SEC_SIZE 0x01000000 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE -- cgit v1.3.1 From 1a1143a45457161e90ea4cd5f3b0561d924ed8fe Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 4 Mar 2022 16:30:17 +0000 Subject: vexpress64: pick DRAM size from DT So far the DRAM size for both the Juno and the FVP model were hardcoded in our config header file. For the Juno this is fine, as all models have 8 GiB of DRAM, but the DRAM size can be configured on the model command line. Drop the fixed DRAM size setup, instead look up the size in the device tree, that we now have for every board. This allows a user to inject a DT with the proper size, and be able to use the full amount of DRAM. Signed-off-by: Andre Przywara --- board/armltd/vexpress64/vexpress64.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) (limited to 'board') diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index c3ad1fcc78a..709ebf3fb08 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -88,20 +88,12 @@ int board_init(void) int dram_init(void) { - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; + return fdtdec_setup_mem_size_base(); } int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -#ifdef PHYS_SDRAM_2 - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; -#endif - - return 0; + return fdtdec_setup_memory_banksize(); } /* Assigned in lowlevel_init.S -- cgit v1.3.1 From 8d78a6b67467145f7e02295ca5d4944251dbc645 Mon Sep 17 00:00:00 2001 From: Peter Hoyes Date: Fri, 4 Mar 2022 16:30:18 +0000 Subject: vexpress64: Add ARMv8R-64 board variant The ARMv8-R64 architecture introduces optional VMSA (paging based MMU) support in the EL1/0 translation regime, which makes that part mostly compatible to ARMv8-A. Add a new board variant to describe the "BASE-R64" FVP model, which inherits a lot from the existing v8-A FVP support. One major difference is that the memory map in "inverted": DRAM starts at 0x0, MMIO is at 2GB [1]. * Create new TARGET_VEXPRESS64_BASER_FVP target, sharing most of the exising configuration. * Implement inverted memory map in vexpress_aemv8.h * Create vexpress_aemv8r defconfig * Provide an MMU memory map for the BASER_FVP * Update vexpress64 documentation At the moment the boot-wrapper is the only supported secure firmware. As there is no official DT for the board yet, we rely on it being supplied by the boot-wrapper into U-Boot, so use OF_HAS_PRIOR_STAGE, and go with a dummy DT for now. [1] https://developer.arm.com/documentation/100964/1114/Base-Platform/Base---memory/BaseR-Platform-memory-map Signed-off-by: Peter Hoyes [Andre: rebase and add Linux kernel header] Signed-off-by: Andre Przywara [trini: Add MAINTAINERS entry for Peter] --- arch/arm/dts/Makefile | 1 + arch/arm/dts/arm_fvp.dts | 11 +++++++++++ board/armltd/vexpress64/Kconfig | 22 +++++++++++++++++----- board/armltd/vexpress64/MAINTAINERS | 5 +++++ configs/vexpress_aemv8r_defconfig | 14 ++++++++++++++ doc/arch/arm64.rst | 3 ++- doc/board/armltd/vexpress64.rst | 1 + include/configs/vexpress_aemv8.h | 23 +++++++++++++++++++++++ 8 files changed, 74 insertions(+), 6 deletions(-) create mode 100644 arch/arm/dts/arm_fvp.dts create mode 100644 configs/vexpress_aemv8r_defconfig (limited to 'board') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fe726d422be..99dc7bc7773 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1186,6 +1186,7 @@ dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb # Kconfig option to build all of these. See examples above. dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb dtb-$(CONFIG_TARGET_VEXPRESS64_BASE_FVP) += fvp-base-revc.dtb +dtb-$(CONFIG_TARGET_VEXPRESS64_BASER_FVP) += arm_fvp.dtb dtb-$(CONFIG_TARGET_VEXPRESS64_JUNO) += juno-r2.dtb dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb diff --git a/arch/arm/dts/arm_fvp.dts b/arch/arm/dts/arm_fvp.dts new file mode 100644 index 00000000000..3a4ad5d1801 --- /dev/null +++ b/arch/arm/dts/arm_fvp.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Empty device tree for the Arm Ltd FVP platform model + + * Copyright 2022 Arm Ltd. + */ + +/dts-v1/; + +/ { +}; diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 512bbbe72e6..a0314c65379 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -9,19 +9,28 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "vexpress_aemv8" -choice - prompt "VExpress64 board variant" - -config TARGET_VEXPRESS64_BASE_FVP - bool "Support Versatile Express ARMv8a FVP BASE model" +config VEXPRESS64_BASE_MODEL + bool select SEMIHOSTING select VIRTIO_BLK if VIRTIO_MMIO select VIRTIO_NET if VIRTIO_MMIO select DM_ETH if VIRTIO_NET select LINUX_KERNEL_IMAGE_HEADER select POSITION_INDEPENDENT + +choice + prompt "VExpress64 board variant" + +config TARGET_VEXPRESS64_BASE_FVP + bool "Support Versatile Express ARMv8a FVP BASE model" + select VEXPRESS64_BASE_MODEL select OF_BOARD +config TARGET_VEXPRESS64_BASER_FVP + bool "Support Versatile Express ARMv8r64 FVP BASE model" + select VEXPRESS64_BASE_MODEL + imply OF_HAS_PRIOR_STAGE + config TARGET_VEXPRESS64_JUNO bool "Support Versatile Express Juno Development Platform" select PCIE_ECAM_GENERIC if PCI @@ -50,6 +59,7 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE config SYS_TEXT_BASE default 0x88000000 if TARGET_VEXPRESS64_BASE_FVP default 0xe0000000 if TARGET_VEXPRESS64_JUNO + default 0x00001000 if TARGET_VEXPRESS64_BASER_FVP config SYS_MALLOC_LEN default 0x810000 if TARGET_VEXPRESS64_JUNO @@ -59,11 +69,13 @@ config SYS_MALLOC_F_LEN default 0x2000 config SYS_LOAD_ADDR + default 0x10000000 if TARGET_VEXPRESS64_BASER_FVP default 0x90000000 config ENV_ADDR default 0x0BFC0000 if TARGET_VEXPRESS64_JUNO default 0x0FFC0000 if TARGET_VEXPRESS64_BASE_FVP + default 0x8FFC0000 if TARGET_VEXPRESS64_BASER_FVP config ENV_SIZE default 0x10000 if TARGET_VEXPRESS64_JUNO diff --git a/board/armltd/vexpress64/MAINTAINERS b/board/armltd/vexpress64/MAINTAINERS index 0ba044d7ff8..b3ecc9bba03 100644 --- a/board/armltd/vexpress64/MAINTAINERS +++ b/board/armltd/vexpress64/MAINTAINERS @@ -14,3 +14,8 @@ JUNO DEVELOPMENT PLATFORM BOARD M: Linus Walleij S: Maintained F: configs/vexpress_aemv8a_juno_defconfig + +VEXPRESS64 ARMV8R-64 +M: Peter Hoyes +S: Maintained +F: configs/vexpress_aemv8r_defconfig diff --git a/configs/vexpress_aemv8r_defconfig b/configs/vexpress_aemv8r_defconfig new file mode 100644 index 00000000000..612797e47d5 --- /dev/null +++ b/configs/vexpress_aemv8r_defconfig @@ -0,0 +1,14 @@ +CONFIG_ARM=y +CONFIG_ARCH_VEXPRESS64=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_DEFAULT_DEVICE_TREE="arm_fvp" +CONFIG_IDENT_STRING=" vexpress_aemv8r64" +CONFIG_TARGET_VEXPRESS64_BASER_FVP=y +CONFIG_REMAKE_ELF=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x9c090000 rootfstype=ext4 root=/dev/vda2 rw rootwait" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SYS_PROMPT="VExpress64# " +# CONFIG_MMC is not set +CONFIG_VIRTIO_MMIO=y diff --git a/doc/arch/arm64.rst b/doc/arch/arm64.rst index 80498f6f6b8..7c0713504c4 100644 --- a/doc/arch/arm64.rst +++ b/doc/arch/arm64.rst @@ -18,7 +18,8 @@ Notes classical firmware (like initial hardware setup, CPU errata workarounds or SMP bringup). U-Boot can be entered in EL2 when its main purpose is that of a boot loader. It can drop to lower exception levels before - entering the OS. + entering the OS. For ARMv8-R it is recommened to enter at S-EL1, as for this + architecture there is no S-EL3. 2. U-Boot for arm64 is compiled with AArch64-gcc. AArch64-gcc use rela relocation format, a tool(tools/relocate-rela) by Scott Wood diff --git a/doc/board/armltd/vexpress64.rst b/doc/board/armltd/vexpress64.rst index d87b1c38f5b..a7f771d2667 100644 --- a/doc/board/armltd/vexpress64.rst +++ b/doc/board/armltd/vexpress64.rst @@ -6,6 +6,7 @@ Arm Versatile Express The vexpress_* board configuration supports the following platforms: * FVP_Base_RevC-2xAEMvA + * FVP_BaseR_AEMv8R * Juno development board Fixed Virtual Platforms diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index e0f9bbeb16c..efffea97c2e 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -20,8 +20,13 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* CS register bases for the original memory map. */ +#ifdef CONFIG_TARGET_VEXPRESS64_BASER_FVP +#define V2M_DRAM_BASE 0x00000000 +#define V2M_PA_BASE 0x80000000 +#else #define V2M_DRAM_BASE 0x80000000 #define V2M_PA_BASE 0x00000000 +#endif #define V2M_PA_CS0 (V2M_PA_BASE + 0x00000000) #define V2M_PA_CS1 (V2M_PA_BASE + 0x14000000) @@ -229,6 +234,24 @@ "boot_name=boot.img\0" \ "boot_addr_r=" __stringify(VEXPRESS_BOOT_ADDR) "\0" +#elif CONFIG_TARGET_VEXPRESS64_BASER_FVP /* ARMv8-R base model */ + +#define BOOT_TARGET_DEVICES(func) \ + func(MEM, mem, na) \ + FUNC_VIRTIO(func) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#define VEXPRESS_KERNEL_ADDR 0x00200000 +#define VEXPRESS_PXEFILE_ADDR 0x0fb00000 +#define VEXPRESS_FDT_ADDR 0x0fc00000 +#define VEXPRESS_SCRIPT_ADDR 0x0fd00000 +#define VEXPRESS_RAMDISK_ADDR 0x0fe00000 + +#define EXTRA_ENV_NAMES \ + "kernel_name=Image\0" \ + "ramdisk_name=ramdisk.img\0" \ + "fdtfile=board.dtb\0" #endif #include -- cgit v1.3.1 From 71230cdaa9597d410f1e8aca62ea5a0daeebc0ac Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:10 -0400 Subject: nxp: ls1046ardb: Convert README to rST This converts the readme for this board to rST. I have tried not to change any semantics from the original (though I did convert MB to M). Signed-off-by: Sean Anderson --- board/freescale/ls1046ardb/MAINTAINERS | 1 + board/freescale/ls1046ardb/README | 76 ------------------------- doc/board/nxp/index.rst | 1 + doc/board/nxp/ls1046ardb.rst | 100 +++++++++++++++++++++++++++++++++ 4 files changed, 102 insertions(+), 76 deletions(-) delete mode 100644 board/freescale/ls1046ardb/README create mode 100644 doc/board/nxp/ls1046ardb.rst (limited to 'board') diff --git a/board/freescale/ls1046ardb/MAINTAINERS b/board/freescale/ls1046ardb/MAINTAINERS index efdea22bdeb..3c8cfe720dc 100644 --- a/board/freescale/ls1046ardb/MAINTAINERS +++ b/board/freescale/ls1046ardb/MAINTAINERS @@ -14,3 +14,4 @@ F: configs/ls1046ardb_tfa_SECURE_BOOT_defconfig F: configs/ls1046ardb_SECURE_BOOT_defconfig F: configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig F: configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +F: doc/board/nxp/ls1046ardb.rst diff --git a/board/freescale/ls1046ardb/README b/board/freescale/ls1046ardb/README deleted file mode 100644 index 90c44f4bce3..00000000000 --- a/board/freescale/ls1046ardb/README +++ /dev/null @@ -1,76 +0,0 @@ -Overview --------- -The LS1046A Reference Design Board (RDB) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS1046A -LayerScape Architecture processor. The LS1046ARDB provides SW development -platform for the Freescale LS1046A processor series, with a complete -debugging environment. The LS1046A RDB is lead-free and RoHS-compliant. - -LS1046A SoC Overview --------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A -SoC overview. - - LS1046ARDB board Overview - ----------------------- - - SERDES1 Connections, 4 lanes supporting: - - Lane0: 10GBase-R with x1 RJ45 connector - - Lane1: 10GBase-R Cage - - Lane2: SGMII.5 - - Lane3: SGMII.6 - - SERDES2 Connections, 4 lanes supporting: - - Lane0: PCIe1 with miniPCIe slot - - Lane1: PCIe2 with PCIe x2 slot - - Lane2: PCIe3 with PCIe x4 slot - - Lane3: SATA - - DDR Controller - - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s - -IFC/Local Bus - - One 512 MB NAND flash with ECC support - - CPLD connection - - USB 3.0 - - one Type A port, one Micro-AB port - - SDHC: connects directly to a full SD/MMC slot - - DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz) - - 4 I2C controllers - - UART - - Two 4-pin serial ports at up to 115.2 Kbit/s - - Two DB9 D-Type connectors supporting one Serial port each - - ARM JTAG support - -Memory map from core's view ----------------------------- -Start Address End Address Description Size -0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB -0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB -0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB -0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB -0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB -0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB -0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB -0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB -0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M -0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M -0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB -0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G -0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G -0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G - -QSPI flash map: -Start Address End Address Description Size -0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI 1MB -0x00_4010_0000 - 0x00_402F_FFFF U-Boot 2MB -0x00_4030_0000 - 0x00_403F_FFFF U-Boot Env 1MB -0x00_4040_0000 - 0x00_405F_FFFF PPA 2MB -0x00_4060_0000 - 0x00_408F_FFFF Secure boot header - + bootscript 3MB -0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB -0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB -0x00_4098_0000 - 0x00_40FF_FFFF Reserved 6MB -0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB - -Booting Options ---------------- -a) QSPI boot -b) SD boot -c) eMMC boot diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst index 63956287c5b..4514b8951ba 100644 --- a/doc/board/nxp/index.rst +++ b/doc/board/nxp/index.rst @@ -13,6 +13,7 @@ NXP Semiconductors imx8qxp_mek imxrt1020-evk imxrt1050-evk + ls1046ardb mx6sabreauto mx6sabresd mx6ul_14x14_evk diff --git a/doc/board/nxp/ls1046ardb.rst b/doc/board/nxp/ls1046ardb.rst new file mode 100644 index 00000000000..4bfeaa93ddb --- /dev/null +++ b/doc/board/nxp/ls1046ardb.rst @@ -0,0 +1,100 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +LS1046ARDB +========== + +The LS1046A Reference Design Board (RDB) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS1046A +LayerScape Architecture processor. The LS1046ARDB provides SW development +platform for the Freescale LS1046A processor series, with a complete +debugging environment. The LS1046A RDB is lead-free and RoHS-compliant. + +LS1046A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A +SoC overview. + +LS1046ARDB board Overview +------------------------- +- SERDES1 Connections, 4 lanes supporting: + + - Lane0: 10GBase-R with x1 RJ45 connector + - Lane1: 10GBase-R Cage + - Lane2: SGMII.5 + - Lane3: SGMII.6 + +- SERDES2 Connections, 4 lanes supporting: + + - Lane0: PCIe1 with miniPCIe slot + - Lane1: PCIe2 with PCIe x2 slot + - Lane2: PCIe3 with PCIe x4 slot + - Lane3: SATA + +- DDR Controller + + - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s + +- IFC/Local Bus + + - One 512 MB NAND flash with ECC support + - CPLD connection + +- USB 3.0 + + - one Type A port, one Micro-AB port + +- SDHC: connects directly to a full SD/MMC slot +- DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz) +- 4 I2C controllers +- UART + + - Two 4-pin serial ports at up to 115.2 Kbit/s + - Two DB9 D-Type connectors supporting one Serial port each + +- ARM JTAG support + +Memory map from core's view +---------------------------- + +================== ================== ================ ===== +Start Address End Address Description Size +================== ================== ================ ===== +``0x00_0000_0000`` ``0x00_000F_FFFF`` Secure Boot ROM 1M +``0x00_0100_0000`` ``0x00_0FFF_FFFF`` CCSRBAR 240M +``0x00_1000_0000`` ``0x00_1000_FFFF`` OCRAM0 64K +``0x00_1001_0000`` ``0x00_1001_FFFF`` OCRAM1 64K +``0x00_2000_0000`` ``0x00_20FF_FFFF`` DCSR 16M +``0x00_7E80_0000`` ``0x00_7E80_FFFF`` IFC - NAND Flash 64K +``0x00_7FB0_0000`` ``0x00_7FB0_0FFF`` IFC - CPLD 4K +``0x00_8000_0000`` ``0x00_FFFF_FFFF`` DRAM1 2G +``0x05_0000_0000`` ``0x05_07FF_FFFF`` QMAN S/W Portal 128M +``0x05_0800_0000`` ``0x05_0FFF_FFFF`` BMAN S/W Portal 128M +``0x08_8000_0000`` ``0x09_FFFF_FFFF`` DRAM2 6G +``0x40_0000_0000`` ``0x47_FFFF_FFFF`` PCI Express1 32G +``0x48_0000_0000`` ``0x4F_FFFF_FFFF`` PCI Express2 32G +``0x50_0000_0000`` ``0x57_FFFF_FFFF`` PCI Express3 32G +================== ================== ================ ===== + +QSPI flash map +-------------- + +================== ================== ================== ===== +Start Address End Address Description Size +================== ================== ================== ===== +``0x00_4000_0000`` ``0x00_400F_FFFF`` RCW + PBI 1M +``0x00_4010_0000`` ``0x00_402F_FFFF`` U-Boot 2M +``0x00_4030_0000`` ``0x00_403F_FFFF`` U-Boot Env 1M +``0x00_4040_0000`` ``0x00_405F_FFFF`` PPA 2M +``0x00_4060_0000`` ``0x00_408F_FFFF`` Secure boot header 3M + + bootscript +``0x00_4090_0000`` ``0x00_4093_FFFF`` FMan ucode 256K +``0x00_4094_0000`` ``0x00_4097_FFFF`` QE/uQE firmware 256K +``0x00_4098_0000`` ``0x00_40FF_FFFF`` Reserved 6M +``0x00_4100_0000`` ``0x00_43FF_FFFF`` FIT Image 48M +================== ================== ================== ===== + +Booting Options +--------------- +- QSPI boot +- SD boot +- eMMC boot -- cgit v1.3.1 From 93c3d329707e0d8dc98e5f86938bbedbe15b5349 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 17:16:05 -0400 Subject: ls1046ardb: Add support for JTAG boot This adds support for booting entirely from JTAG while using a hard-coded RCW. With these steps, it is not necessary to program a "good" RCW using CodeWarrior. The method here can be performed with any JTAG adapter supported by OpenOCD, including the on-board CMSIS-DAP (albeit very slowly). These steps require LS1046A support in OpenOCD, which was added in [1]. [1] https://sourceforge.net/p/openocd/code/ci/5b70c1f679755677c925b4e6dd2c3d8be4715717/ Signed-off-by: Sean Anderson [trini: Add reference to doc/board/nxp/ls1046ardb.rst] --- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 2 + board/freescale/ls1046ardb/ls1046ardb.c | 10 +++++ doc/board/nxp/ls1046ardb.rst | 73 +++++++++++++++++++++++++++++++++ doc/usage/semihosting.rst | 3 +- include/configs/ls1046ardb.h | 2 + 5 files changed, 89 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 564cc27c8b2..1a7dde30a58 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -27,6 +27,8 @@ DECLARE_GLOBAL_DATA_PTR; u32 spl_boot_device(void) { + if (IS_ENABLED(CONFIG_SPL_SEMIHOSTING)) + return BOOT_DEVICE_SMH; #ifdef CONFIG_SPL_MMC return BOOT_DEVICE_MMC1; #endif diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c index d0abfe8869f..9af7cf763be 100644 --- a/board/freescale/ls1046ardb/ls1046ardb.c +++ b/board/freescale/ls1046ardb/ls1046ardb.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include #include #include @@ -27,6 +29,14 @@ DECLARE_GLOBAL_DATA_PTR; +struct serial_device *default_serial_console(void) +{ +#if IS_ENABLED(CONFIG_SEMIHOSTING_SERIAL) + return &serial_smh_device; +#endif + return &eserial1_device; +} + int board_early_init_f(void) { fsl_lsch2_early_init_f(); diff --git a/doc/board/nxp/ls1046ardb.rst b/doc/board/nxp/ls1046ardb.rst index e4499a13fb7..35465d00612 100644 --- a/doc/board/nxp/ls1046ardb.rst +++ b/doc/board/nxp/ls1046ardb.rst @@ -110,6 +110,79 @@ SD boot and eMMC boot ``{ SW5[0:8], SW4[0] }`` should be ``0010_0000_0``. eMMC is selected only if there is no SD card in the slot. +.. _ls1046ardb_jtag: + +JTAG boot +^^^^^^^^^ + +To recover a bricked board, or to perform initial programming, the ls1046 +supports using two hard-coded Reset Configuration Words (RCWs). Unfortunately, +this configuration disables most functionality, including the uarts and ethernet. +However, the SD/MMC and flash controllers are still functional. To get around +the lack of a serial console, we will use ARM semihosting instead. When +enabled, OpenOCD will interpret certain instructions as calls to the host +operating system. This allows U-Boot to use the console, read/write files, or +run arbitrary commands (!). + +When configuring U-Boot, ensure that ``CONFIG_SEMIHOSTING``, +``CONFIG_SPL_SEMIHOSTING``, and ``CONFIG_SEMIHOSTING_SERIAL`` are enabled. +``{ SW5[0:8], SW4[0] }`` should be ``0100_1111_0``. Additionally, ``SW4[7]`` +should be set to ``0``. Connect to the "console" USB connector on the front of +the enclosure. + +Create a new file called ``u-boot.tcl`` (or whatever you choose) with the +following contents:: + + # Load the configuration for the LS1046ARDB + source [find board/nxp_rdb-ls1046a.cfg] + # Initialize the scan chain + init + # Stop the processor + halt + # Enable semihosting + arm semihosting enable + # Load U-Boot SPL + load_image spl/u-boot-spl 0 elf + # Start executing SPL at the beginning of OCRAM + resume 0x10000000 + +Then, launch openocd like:: + + openocd -f u-boot.tcl + +You should see the U-boot SPL banner followed by the banner for U-Boot proper +in the output of openocd. The CMSIS-DAP adapter is slow, so this can take a +long time. If you don't see it, something has gone wrong. After a while, you +should see the prompt. You can load an image using semihosting by running:: + + => load hostfs - $loadaddr + +Note that openocd's terminal is "cooked," so commands will only be sent to +U-Boot when you press enter, and all commands will be echoed twice. +Additionally, openocd will block when waiting for input, ignoring gdb, JTAG +events, and Ctrl-Cs. To make openocd process these events, just hit enter. + +Using an external JTAG adapter +"""""""""""""""""""""""""""""" + +The CMSIS-DAP adapter can be rather slow. To speed up booting, use an external +JTAG adapter. The following examples assume you are using a J-Link, though any +adapter supported by OpenOCD will do. Ensure that ``SW4[7]`` is ``1``. Attach +your jtag adapter to J22. Modify ``u-boot.tcl`` and replace the first two lines +with the following:: + + # Load the J-Link configuration (or whatever your adapter is) + source [find interface/jlink.cfg] + # Use JTAG, since the J-Link also supports SWD + transport select jtag + # The reset pin resets the whole CPU + reset_config srst_only + # Load the LS1046A config + source [find target/ls1046a.cfg] + +You can proceed as normal through the rest of the steps above. I got a speedup +of around 100x by using a J-Link. + Debug UART ---------- diff --git a/doc/usage/semihosting.rst b/doc/usage/semihosting.rst index 1d793983a7d..6a280b455e0 100644 --- a/doc/usage/semihosting.rst +++ b/doc/usage/semihosting.rst @@ -62,7 +62,8 @@ so you will need to enable it:: 'arm semihosting enable' -c resume Note that enabling semihosting can only be done after attaching to the -board with ``init``, and must be done while the CPU is halted. +board with ``init``, and must be done while the CPU is halted. For a more +extended example, refer to the :ref:`LS1046ARDB docs `. Loading files ------------- diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 04c3ad02c8f..df699bca34a 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -140,6 +140,8 @@ #endif #endif +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + #include #endif /* __LS1046ARDB_H__ */ -- cgit v1.3.1 From 53b953f2ebad6263352cb1247618dc5b965863cc Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:33 -0400 Subject: arm64: ls1046a: Support semihosting fallback Use the semihosting_enabled function to determine whether or not to enable semihosting devices. This allows for graceful fallback in the event a debugger is not attached. Signed-off-by: Sean Anderson --- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 3 ++- board/freescale/ls1046ardb/ls1046ardb.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 1a7dde30a58..5f09ef0a4af 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -27,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR; u32 spl_boot_device(void) { - if (IS_ENABLED(CONFIG_SPL_SEMIHOSTING)) + if (semihosting_enabled()) return BOOT_DEVICE_SMH; #ifdef CONFIG_SPL_MMC return BOOT_DEVICE_MMC1; diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c index 9af7cf763be..f2949cf8b69 100644 --- a/board/freescale/ls1046ardb/ls1046ardb.c +++ b/board/freescale/ls1046ardb/ls1046ardb.c @@ -32,7 +32,8 @@ DECLARE_GLOBAL_DATA_PTR; struct serial_device *default_serial_console(void) { #if IS_ENABLED(CONFIG_SEMIHOSTING_SERIAL) - return &serial_smh_device; + if (semihosting_enabled()) + return &serial_smh_device; #endif return &eserial1_device; } -- cgit v1.3.1