From 2b8dc36b4c515979da330a96d9fcc9bbbe5385fa Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Tue, 14 May 2024 17:50:11 +0800 Subject: andes: Unify naming policy for Andes related source Signed-off-by: Leo Yu-Chi Liang --- board/AndesTech/ae350/Kconfig | 44 ---------- board/AndesTech/ae350/MAINTAINERS | 17 ---- board/AndesTech/ae350/Makefile | 6 -- board/AndesTech/ae350/ae350.c | 165 -------------------------------------- board/andestech/ae350/Kconfig | 44 ++++++++++ board/andestech/ae350/MAINTAINERS | 17 ++++ board/andestech/ae350/Makefile | 6 ++ board/andestech/ae350/ae350.c | 165 ++++++++++++++++++++++++++++++++++++++ 8 files changed, 232 insertions(+), 232 deletions(-) delete mode 100644 board/AndesTech/ae350/Kconfig delete mode 100644 board/AndesTech/ae350/MAINTAINERS delete mode 100644 board/AndesTech/ae350/Makefile delete mode 100644 board/AndesTech/ae350/ae350.c create mode 100644 board/andestech/ae350/Kconfig create mode 100644 board/andestech/ae350/MAINTAINERS create mode 100644 board/andestech/ae350/Makefile create mode 100644 board/andestech/ae350/ae350.c (limited to 'board') diff --git a/board/AndesTech/ae350/Kconfig b/board/AndesTech/ae350/Kconfig deleted file mode 100644 index a85e7d63517..00000000000 --- a/board/AndesTech/ae350/Kconfig +++ /dev/null @@ -1,44 +0,0 @@ -if TARGET_ANDES_AE350 - -config SYS_CPU - default "andesv5" - -config SYS_BOARD - default "ae350" - -config SYS_VENDOR - default "AndesTech" - -config SYS_SOC - default "ae350" - -config SYS_CONFIG_NAME - default "ae350" - -config ENV_SIZE - default 0x2000 if ENV_IS_IN_SPI_FLASH - -config ENV_OFFSET - default 0x140000 if ENV_IS_IN_SPI_FLASH - -config SPL_TEXT_BASE - default 0x800000 - -config SPL_OPENSBI_LOAD_ADDR - default 0x00000000 - -config SYS_FDT_BASE - hex - default 0x800f0000 if OF_SEPARATE - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select RISCV_NDS - select SUPPORT_SPL - select BINMAN if SPL - imply SMP - imply SPL_RAM_SUPPORT - imply SPL_RAM_DEVICE - imply OF_HAS_PRIOR_STAGE - -endif diff --git a/board/AndesTech/ae350/MAINTAINERS b/board/AndesTech/ae350/MAINTAINERS deleted file mode 100644 index a6bc90baf88..00000000000 --- a/board/AndesTech/ae350/MAINTAINERS +++ /dev/null @@ -1,17 +0,0 @@ -AE350 BOARD -M: Rick Chen -S: Maintained -F: board/AndesTech/ae350/ -F: include/configs/ae350.h -F: configs/ae350_rv32_defconfig -F: configs/ae350_rv32_falcon_defconfig -F: configs/ae350_rv32_falcon_xip_defconfig -F: configs/ae350_rv32_spl_defconfig -F: configs/ae350_rv32_spl_xip_defconfig -F: configs/ae350_rv32_xip_defconfig -F: configs/ae350_rv64_defconfig -F: configs/ae350_rv64_falcon_defconfig -F: configs/ae350_rv64_falcon_xip_defconfig -F: configs/ae350_rv64_spl_defconfig -F: configs/ae350_rv64_spl_xip_defconfig -F: configs/ae350_rv64_xip_defconfig diff --git a/board/AndesTech/ae350/Makefile b/board/AndesTech/ae350/Makefile deleted file mode 100644 index 705ae43af5d..00000000000 --- a/board/AndesTech/ae350/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2017 Andes Technology Corporation. -# Rick Chen, Andes Technology Corporation - -obj-y := ae350.o diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c deleted file mode 100644 index 62b93b4ecba..00000000000 --- a/board/AndesTech/ae350/ae350.c +++ /dev/null @@ -1,165 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ - -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) -#include -#endif -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscellaneous platform dependent initializations - */ -#if IS_ENABLED(CONFIG_MISC_INIT_R) -int misc_init_r(void) -{ - long csr_marchid = 0; - const long mask_64 = 0x8000; - const long mask_cpu = 0xff; - char cpu_name[10] = {}; - -#if CONFIG_IS_ENABLED(RISCV_SMODE) - sbi_get_marchid(&csr_marchid); -#elif CONFIG_IS_ENABLED(RISCV_MMODE) - csr_marchid = csr_read(CSR_MARCHID); -#endif - if (mask_64 & csr_marchid) - snprintf(cpu_name, sizeof(cpu_name), "ax%lx", (mask_cpu & csr_marchid)); - else - snprintf(cpu_name, sizeof(cpu_name), "a%lx", (mask_cpu & csr_marchid)); - - return env_set("cpu", cpu_name); -} -#endif - -int board_init(void) -{ - gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; - - return 0; -} - -int dram_init(void) -{ - return fdtdec_setup_mem_size_base(); -} - -int dram_init_banksize(void) -{ - return fdtdec_setup_memory_banksize(); -} - -#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) -int board_eth_init(struct bd_info *bd) -{ - return ftmac100_initialize(bd); -} -#endif - -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - return 0; -} - -#define ANDES_HW_DTB_ADDRESS 0xF2000000 -void *board_fdt_blob_setup(int *err) -{ - *err = 0; - - if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) { - if (fdt_magic((uintptr_t)gd->arch.firmware_fdt_addr) == FDT_MAGIC) - return (void *)(ulong)gd->arch.firmware_fdt_addr; - } - - if (fdt_magic(CONFIG_SYS_FDT_BASE) == FDT_MAGIC) - return (void *)CONFIG_SYS_FDT_BASE; - return (void *)ANDES_HW_DTB_ADDRESS; - - *err = -EINVAL; - return NULL; -} - -#ifdef CONFIG_SPL_BOARD_INIT -void spl_board_init() -{ - /* enable v5l2 cache */ - if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) - enable_caches(); -} -#endif - -int smc_init(void) -{ - int node = -1; - const char *compat = "andestech,atfsmc020"; - void *blob = (void *)gd->fdt_blob; - fdt_addr_t addr; - struct ftsmc020_bank *regs; - - node = fdt_node_offset_by_compatible(blob, -1, compat); - if (node < 0) - return -FDT_ERR_NOTFOUND; - - addr = fdtdec_get_addr_size_auto_noparent(blob, node, - "reg", 0, NULL, false); - - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; - - regs = (struct ftsmc020_bank *)(uintptr_t)addr; - regs->cr &= ~FTSMC020_BANK_WPROT; - - return 0; -} - -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - smc_init(); - - return 0; -} -#endif - -#ifdef CONFIG_SPL -void board_boot_order(u32 *spl_boot_list) -{ - u8 i; - u32 boot_devices[] = { -#ifdef CONFIG_SPL_RAM_SUPPORT - BOOT_DEVICE_RAM, -#endif -#ifdef CONFIG_SPL_MMC - BOOT_DEVICE_MMC1, -#endif - }; - - for (i = 0; i < ARRAY_SIZE(boot_devices); i++) - spl_boot_list[i] = boot_devices[i]; -} -#endif - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* boot using first FIT config */ - return 0; -} -#endif diff --git a/board/andestech/ae350/Kconfig b/board/andestech/ae350/Kconfig new file mode 100644 index 00000000000..096564b3dc1 --- /dev/null +++ b/board/andestech/ae350/Kconfig @@ -0,0 +1,44 @@ +if TARGET_ANDES_AE350 + +config SYS_CPU + default "andes" + +config SYS_BOARD + default "ae350" + +config SYS_VENDOR + default "andestech" + +config SYS_SOC + default "ae350" + +config SYS_CONFIG_NAME + default "ae350" + +config ENV_SIZE + default 0x2000 if ENV_IS_IN_SPI_FLASH + +config ENV_OFFSET + default 0x140000 if ENV_IS_IN_SPI_FLASH + +config SPL_TEXT_BASE + default 0x800000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x00000000 + +config SYS_FDT_BASE + hex + default 0x800f0000 if OF_SEPARATE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select RISCV_ANDES + select SUPPORT_SPL + select BINMAN if SPL + imply SMP + imply SPL_RAM_SUPPORT + imply SPL_RAM_DEVICE + imply OF_HAS_PRIOR_STAGE + +endif diff --git a/board/andestech/ae350/MAINTAINERS b/board/andestech/ae350/MAINTAINERS new file mode 100644 index 00000000000..31e34e610df --- /dev/null +++ b/board/andestech/ae350/MAINTAINERS @@ -0,0 +1,17 @@ +AE350 BOARD +M: Rick Chen +S: Maintained +F: board/andestech/ae350/ +F: include/configs/ae350.h +F: configs/ae350_rv32_defconfig +F: configs/ae350_rv32_falcon_defconfig +F: configs/ae350_rv32_falcon_xip_defconfig +F: configs/ae350_rv32_spl_defconfig +F: configs/ae350_rv32_spl_xip_defconfig +F: configs/ae350_rv32_xip_defconfig +F: configs/ae350_rv64_defconfig +F: configs/ae350_rv64_falcon_defconfig +F: configs/ae350_rv64_falcon_xip_defconfig +F: configs/ae350_rv64_spl_defconfig +F: configs/ae350_rv64_spl_xip_defconfig +F: configs/ae350_rv64_xip_defconfig diff --git a/board/andestech/ae350/Makefile b/board/andestech/ae350/Makefile new file mode 100644 index 00000000000..705ae43af5d --- /dev/null +++ b/board/andestech/ae350/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2017 Andes Technology Corporation. +# Rick Chen, Andes Technology Corporation + +obj-y := ae350.o diff --git a/board/andestech/ae350/ae350.c b/board/andestech/ae350/ae350.c new file mode 100644 index 00000000000..5ae5baed6ba --- /dev/null +++ b/board/andestech/ae350/ae350.c @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ + +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initializations + */ +#if IS_ENABLED(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ + long csr_marchid = 0; + const long mask_64 = 0x8000; + const long mask_cpu = 0xff; + char cpu_name[10] = {}; + +#if CONFIG_IS_ENABLED(RISCV_SMODE) + sbi_get_marchid(&csr_marchid); +#elif CONFIG_IS_ENABLED(RISCV_MMODE) + csr_marchid = csr_read(CSR_MARCHID); +#endif + if (mask_64 & csr_marchid) + snprintf(cpu_name, sizeof(cpu_name), "ax%lx", (mask_cpu & csr_marchid)); + else + snprintf(cpu_name, sizeof(cpu_name), "a%lx", (mask_cpu & csr_marchid)); + + return env_set("cpu", cpu_name); +} +#endif + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; + + return 0; +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) +int board_eth_init(struct bd_info *bd) +{ + return ftmac100_initialize(bd); +} +#endif + +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + return 0; +} + +#define ANDES_HW_DTB_ADDRESS 0xF2000000 +void *board_fdt_blob_setup(int *err) +{ + *err = 0; + + if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) { + if (fdt_magic((uintptr_t)gd->arch.firmware_fdt_addr) == FDT_MAGIC) + return (void *)(ulong)gd->arch.firmware_fdt_addr; + } + + if (fdt_magic(CONFIG_SYS_FDT_BASE) == FDT_MAGIC) + return (void *)CONFIG_SYS_FDT_BASE; + return (void *)ANDES_HW_DTB_ADDRESS; + + *err = -EINVAL; + return NULL; +} + +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init() +{ + /* enable andes-l2 cache */ + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + enable_caches(); +} +#endif + +int smc_init(void) +{ + int node = -1; + const char *compat = "andestech,atfsmc020"; + void *blob = (void *)gd->fdt_blob; + fdt_addr_t addr; + struct ftsmc020_bank *regs; + + node = fdt_node_offset_by_compatible(blob, -1, compat); + if (node < 0) + return -FDT_ERR_NOTFOUND; + + addr = fdtdec_get_addr_size_auto_noparent(blob, node, + "reg", 0, NULL, false); + + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + regs = (struct ftsmc020_bank *)(uintptr_t)addr; + regs->cr &= ~FTSMC020_BANK_WPROT; + + return 0; +} + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + smc_init(); + + return 0; +} +#endif + +#ifdef CONFIG_SPL +void board_boot_order(u32 *spl_boot_list) +{ + u8 i; + u32 boot_devices[] = { +#ifdef CONFIG_SPL_RAM_SUPPORT + BOOT_DEVICE_RAM, +#endif +#ifdef CONFIG_SPL_MMC + BOOT_DEVICE_MMC1, +#endif + }; + + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) + spl_boot_list[i] = boot_devices[i]; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* boot using first FIT config */ + return 0; +} +#endif -- cgit v1.3.1