From b2e02d28653edac48d6def9791f2fa0ebc491498 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 17 Dec 2014 15:50:36 +0800 Subject: x86: Add basic support to queensbay platform and crownbay board Implement minimum required functions for the basic support to queensbay platform and crownbay board. Currently the implementation is to call fsp_init() in the car_init(). We may move that call to cpu_init_f() in the future. Signed-off-by: Bin Meng Acked-by: Simon Glass --- board/intel/crownbay/MAINTAINERS | 6 ++++++ board/intel/crownbay/Makefile | 7 +++++++ board/intel/crownbay/crownbay.c | 21 +++++++++++++++++++++ board/intel/crownbay/start.S | 9 +++++++++ 4 files changed, 43 insertions(+) create mode 100644 board/intel/crownbay/MAINTAINERS create mode 100644 board/intel/crownbay/Makefile create mode 100644 board/intel/crownbay/crownbay.c create mode 100644 board/intel/crownbay/start.S (limited to 'board') diff --git a/board/intel/crownbay/MAINTAINERS b/board/intel/crownbay/MAINTAINERS new file mode 100644 index 00000000000..1eb68693df3 --- /dev/null +++ b/board/intel/crownbay/MAINTAINERS @@ -0,0 +1,6 @@ +INTEL CROWNBAY BOARD +M: Bin Meng +S: Maintained +F: board/intel/crownbay/ +F: include/configs/crownbay.h +F: configs/crownbay_defconfig diff --git a/board/intel/crownbay/Makefile b/board/intel/crownbay/Makefile new file mode 100644 index 00000000000..aeb219b4e57 --- /dev/null +++ b/board/intel/crownbay/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014, Bin Meng +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += crownbay.o start.o diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c new file mode 100644 index 00000000000..8c6df98bf7d --- /dev/null +++ b/board/intel/crownbay/crownbay.c @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, 4) + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + lpc47m_enable_serial(SERIAL_DEV, UART0_BASE); + + return 0; +} diff --git a/board/intel/crownbay/start.S b/board/intel/crownbay/start.S new file mode 100644 index 00000000000..cf92b4c0b34 --- /dev/null +++ b/board/intel/crownbay/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret -- cgit v1.3.1 From b71eec3129c2626bfb1e98141b317d958e3cf384 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 17 Dec 2014 15:50:38 +0800 Subject: x86: ich6-gpio: Add Intel Tunnel Creek GPIO support Intel Tunnel Creek GPIO register block is compatible with current ich6-gpio driver, except the offset and content of GPIO block base address register in the LPC PCI configuration space are different. Use u16 instead of u32 to store the 16-bit I/O address of the GPIO registers so that it could support both Ivybridge and Tunnel Creek. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/include/asm/arch-queensbay/gpio.h | 13 +++++++++++++ arch/x86/include/asm/gpio.h | 4 ++-- board/coreboot/coreboot/coreboot.c | 2 +- board/google/chromebook_link/link.c | 2 +- board/intel/crownbay/crownbay.c | 5 +++++ drivers/gpio/intel_ich6_gpio.c | 20 ++++++++++++-------- 6 files changed, 34 insertions(+), 12 deletions(-) create mode 100644 arch/x86/include/asm/arch-queensbay/gpio.h (limited to 'board') diff --git a/arch/x86/include/asm/arch-queensbay/gpio.h b/arch/x86/include/asm/arch-queensbay/gpio.h new file mode 100644 index 00000000000..ab4e059131d --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/gpio.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _X86_ARCH_GPIO_H_ +#define _X86_ARCH_GPIO_H_ + +/* Where in config space is the register that points to the GPIO registers? */ +#define PCI_CFG_GPIOBASE 0x44 + +#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h index 1787e5210c3..10994273881 100644 --- a/arch/x86/include/asm/gpio.h +++ b/arch/x86/include/asm/gpio.h @@ -11,7 +11,7 @@ #include struct ich6_bank_platdata { - uint32_t base_addr; + uint16_t base_addr; const char *bank_name; }; @@ -147,7 +147,7 @@ struct pch_gpio_map { } set3; }; -void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio); +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio); void ich_gpio_set_gpio_map(const struct pch_gpio_map *map); #endif /* _X86_GPIO_H_ */ diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c index b260f9a1636..154faf62393 100644 --- a/board/coreboot/coreboot/coreboot.c +++ b/board/coreboot/coreboot/coreboot.c @@ -16,7 +16,7 @@ int arch_early_init_r(void) return 0; } -void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio) +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) { return; } diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index 4d95c1c9273..9978e92006d 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -125,7 +125,7 @@ int board_early_init_f(void) return 0; } -void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio) +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) { /* GPIO Set 1 */ if (gpio->set1.level) diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c index 8c6df98bf7d..54670d3ac7e 100644 --- a/board/intel/crownbay/crownbay.c +++ b/board/intel/crownbay/crownbay.c @@ -19,3 +19,8 @@ int board_early_init_f(void) return 0; } + +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) +{ + return; +} diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c index 3433216cb63..7720cc3dadf 100644 --- a/drivers/gpio/intel_ich6_gpio.c +++ b/drivers/gpio/intel_ich6_gpio.c @@ -39,9 +39,9 @@ struct ich6_bank_priv { /* These are I/O addresses */ - uint32_t use_sel; - uint32_t io_sel; - uint32_t lvl; + uint16_t use_sel; + uint16_t io_sel; + uint16_t lvl; }; /* TODO: Move this to device tree, or platform data */ @@ -57,7 +57,7 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) u8 tmpbyte; u16 tmpword; u32 tmplong; - u32 gpiobase; + u16 gpiobase; int offset; /* Where should it be? */ @@ -116,11 +116,15 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) /* * GPIOBASE moved to its current offset with ICH6, but prior to * that it was unused (or undocumented). Check that it looks - * okay: not all ones or zeros, and mapped to I/O space (bit 0). + * okay: not all ones or zeros. + * + * Note we don't need check bit0 here, because the Tunnel Creek + * GPIO base address register bit0 is reserved (read returns 0), + * while on the Ivybridge the bit0 is used to indicate it is an + * I/O space. */ tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE); - if (tmplong == 0x00000000 || tmplong == 0xffffffff || - !(tmplong & 0x00000001)) { + if (tmplong == 0x00000000 || tmplong == 0xffffffff) { debug("%s: unexpected GPIOBASE value\n", __func__); return -ENODEV; } @@ -131,7 +135,7 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) * at the offset that we just read. Bit 0 indicates that it's * an I/O address, not a memory address, so mask that off. */ - gpiobase = tmplong & 0xfffffffe; + gpiobase = tmplong & 0xfffe; offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1); if (offset == -1) { debug("%s: Invalid register offset %d\n", __func__, offset); -- cgit v1.3.1 From 58f542de30e3bae9845726af36e0e25b5b458e8c Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 17 Dec 2014 15:50:40 +0800 Subject: x86: Add queensbay and crownbay Kconfig files Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/Kconfig | 13 +++++++ arch/x86/cpu/queensbay/Kconfig | 79 ++++++++++++++++++++++++++++++++++++++++++ board/intel/crownbay/Kconfig | 20 +++++++++++ 3 files changed, 112 insertions(+) create mode 100644 arch/x86/cpu/queensbay/Kconfig create mode 100644 board/intel/crownbay/Kconfig (limited to 'board') diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index fdfb6187b8e..ebf72b3ee07 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -32,6 +32,15 @@ config TARGET_CHROMEBOOK_LINK and it provides a 2560x1700 high resolution touch-enabled LCD display. +config TARGET_CROWNBAY + bool "Support Intel Crown Bay CRB" + help + This is the Intel Crown Bay Customer Reference Board. It contains + the Intel Atom Processor E6xx populated on the COM Express module + with 1GB DDR2 soldered down memory and a carrier board with the + Intel Platform Controller Hub EG20T, other system components and + peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. + endchoice config RAMBASE @@ -310,8 +319,12 @@ endmenu source "arch/x86/cpu/ivybridge/Kconfig" +source "arch/x86/cpu/queensbay/Kconfig" + source "board/coreboot/coreboot/Kconfig" source "board/google/chromebook_link/Kconfig" +source "board/intel/crownbay/Kconfig" + endmenu diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig new file mode 100644 index 00000000000..56fe85ccad0 --- /dev/null +++ b/arch/x86/cpu/queensbay/Kconfig @@ -0,0 +1,79 @@ +# +# Copyright (C) 2014, Bin Meng +# +# SPDX-License-Identifier: GPL-2.0+ +# + +config INTEL_QUEENSBAY + bool + select HAVE_FSP + select HAVE_CMC + +if INTEL_QUEENSBAY + +config HAVE_FSP + bool "Add an Firmware Support Package binary" + help + Select this option to add an Firmware Support Package binary to + the resulting U-Boot image. It is a binary blob which U-Boot uses + to set up SDRAM and other chipset specific initialization. + + Note: Without this binary U-Boot will not be able to set up its + SDRAM so will not boot. + +config FSP_FILE + string "Firmware Support Package binary filename" + depends on HAVE_FSP + default "fsp.bin" + help + The filename of the file to use as Firmware Support Package binary + in the board directory. + +config FSP_LOCATION + hex "Firmware Support Package binary location" + depends on HAVE_FSP + default 0xfffc0000 + help + FSP is not Position Independent Code (PIC) and the whole FSP has to + be rebased if it is placed at a location which is different from the + perferred base address specified during the FSP build. Use Intel's + Binary Configuration Tool (BCT) to do the rebase. + + The default base address of 0xfffc0000 indicates that the binary must + be located at offset 0xc0000 from the beginning of a 1MB flash device. + +config FSP_TEMP_RAM_ADDR + hex + default 0x2000000 + help + Stack top address which is used in FspInit after DRAM is ready and + CAR is disabled. + +config HAVE_CMC + bool "Add a Chipset Micro Code state machine binary" + help + Select this option to add a Chipset Micro Code state machine binary + to the resulting U-Boot image. It is a 64K data block of machine + specific code which must be put in the flash for the processor to + access when powered up before system BIOS is executed. + +config CMC_FILE + string "Chipset Micro Code state machine filename" + depends on HAVE_CMC + default "cmc.bin" + help + The filename of the file to use as Chipset Micro Code state machine + binary in the board directory. + +config CMC_LOCATION + hex "Chipset Micro Code state machine binary location" + depends on HAVE_CMC + default 0xfffb0000 + help + The location of the CMC binary is determined by a strap. It must be + put in flash at a location matching the strap-determined base address. + + The default base address of 0xfffb0000 indicates that the binary must + be located at offset 0xb0000 from the beginning of a 1MB flash device. + +endif diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig new file mode 100644 index 00000000000..4709f9b55d5 --- /dev/null +++ b/board/intel/crownbay/Kconfig @@ -0,0 +1,20 @@ +if TARGET_CROWNBAY + +config SYS_BOARD + default "crownbay" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "queensbay" + +config SYS_CONFIG_NAME + default "crownbay" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select INTEL_QUEENSBAY + select BOARD_ROMSIZE_KB_1024 + +endif -- cgit v1.3.1 From 0ff65eb99c3ed4d452b9c74dae8c4f736d92303f Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 17 Dec 2014 15:50:45 +0800 Subject: x86: crownbay: Enable Intel E1000 NIC support We don't have driver for the Intel Topcliff PCH Gigabit Ethernet controller for now, so enable the Intle E1000 NIC support, which can be plugged into any PCIe slot on the Crown Bay board. Signed-off-by: Bin Meng Acked-by: Simon Glass --- board/intel/crownbay/crownbay.c | 6 ++++++ include/configs/crownbay.h | 1 + 2 files changed, 7 insertions(+) (limited to 'board') diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c index 54670d3ac7e..2a254efe3dd 100644 --- a/board/intel/crownbay/crownbay.c +++ b/board/intel/crownbay/crownbay.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #define SERIAL_DEV PNP_DEV(0x2e, 4) @@ -24,3 +25,8 @@ void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) { return; } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index a051b1149b5..09a52ab0df4 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -37,6 +37,7 @@ #define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP +#define CONFIG_E1000 #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \ -- cgit v1.3.1 From 058235c06bd09b32c7e300c92d5eafa237f246c8 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 24 Dec 2014 02:02:19 +0100 Subject: vexpress64: take over maintenance of the semi vexpress64 As agreed with Steve Rae I'm taking over maintenance of the semihosted, emulated FVP/foundation model Versatile Express 64 bit board variant. Signed-off-by: Linus Walleij Acked-by: Steve Rae --- board/armltd/vexpress64/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/armltd/vexpress64/MAINTAINERS b/board/armltd/vexpress64/MAINTAINERS index 97c4b0e574b..66c8dffa163 100644 --- a/board/armltd/vexpress64/MAINTAINERS +++ b/board/armltd/vexpress64/MAINTAINERS @@ -6,6 +6,6 @@ F: include/configs/vexpress_aemv8a.h F: configs/vexpress_aemv8a_defconfig VEXPRESS_AEMV8A_SEMI BOARD -M: Steve Rae +M: Linus Walleij S: Maintained F: configs/vexpress_aemv8a_semi_defconfig -- cgit v1.3.1 From 3207d8fc9cc8fcc91d0dcc02890c7aaff48a6a27 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 5 Dec 2014 20:56:46 -0700 Subject: ARM: rpi: only set usbethaddr on relevant systems Model A and CM RPis don't have an on-board USB Ethernet device. Hence, there's no point setting $usbethaddr based on the device fuses. Use the model detection code to gate this. Note that the fuses are actually programmed even on those devices though. Signed-off-by: Stephen Warren --- board/raspberrypi/rpi/rpi.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'board') diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 7dbd40ecf87..ca8e86dead6 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -82,58 +82,72 @@ struct msg_get_clock_rate { static const struct { const char *name; const char *fdtfile; + bool has_onboard_eth; } models[] = { [BCM2835_BOARD_REV_B_I2C0_2] = { "Model B (no P5)", "bcm2835-rpi-b-i2c0.dtb", + true, }, [BCM2835_BOARD_REV_B_I2C0_3] = { "Model B (no P5)", "bcm2835-rpi-b-i2c0.dtb", + true, }, [BCM2835_BOARD_REV_B_I2C1_4] = { "Model B", "bcm2835-rpi-b.dtb", + true, }, [BCM2835_BOARD_REV_B_I2C1_5] = { "Model B", "bcm2835-rpi-b.dtb", + true, }, [BCM2835_BOARD_REV_B_I2C1_6] = { "Model B", "bcm2835-rpi-b.dtb", + true, }, [BCM2835_BOARD_REV_A_7] = { "Model A", "bcm2835-rpi-a.dtb", + false, }, [BCM2835_BOARD_REV_A_8] = { "Model A", "bcm2835-rpi-a.dtb", + false, }, [BCM2835_BOARD_REV_A_9] = { "Model A", "bcm2835-rpi-a.dtb", + false, }, [BCM2835_BOARD_REV_B_REV2_d] = { "Model B rev2", "bcm2835-rpi-b-rev2.dtb", + true, }, [BCM2835_BOARD_REV_B_REV2_e] = { "Model B rev2", "bcm2835-rpi-b-rev2.dtb", + true, }, [BCM2835_BOARD_REV_B_REV2_f] = { "Model B rev2", "bcm2835-rpi-b-rev2.dtb", + true, }, [BCM2835_BOARD_REV_B_PLUS] = { "Model B+", "bcm2835-rpi-b-plus.dtb", + true, }, [BCM2835_BOARD_REV_CM] = { "Compute Module", "bcm2835-rpi-cm.dtb", + false, }, }; @@ -177,6 +191,9 @@ static void set_usbethaddr(void) ALLOC_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1, 16); int ret; + if (!models[rpi_board_rev].has_onboard_eth) + return; + if (getenv("usbethaddr")) return; -- cgit v1.3.1 From 47705eff7a822105dfddaa03aadfe95f05849892 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 23 Dec 2014 20:01:43 -0700 Subject: ARM: rpi: support model A+ Add a board rev entry for the new model A+, and augment the board rev error handling code to be a bit more verbose. Signed-off-by: Stephen Warren --- arch/arm/include/asm/arch-bcm2835/mbox.h | 1 + board/raspberrypi/rpi/rpi.c | 14 ++++++++++++-- 2 files changed, 13 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h index 0289ba6a917..88d2ec11a7c 100644 --- a/arch/arm/include/asm/arch-bcm2835/mbox.h +++ b/arch/arm/include/asm/arch-bcm2835/mbox.h @@ -140,6 +140,7 @@ struct bcm2835_mbox_tag_hdr { #define BCM2835_BOARD_REV_B_REV2_f 0xf #define BCM2835_BOARD_REV_B_PLUS 0x10 #define BCM2835_BOARD_REV_CM 0x11 +#define BCM2835_BOARD_REV_A_PLUS 0x12 struct bcm2835_mbox_tag_get_board_rev { struct bcm2835_mbox_tag_hdr tag_hdr; diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index ca8e86dead6..6227e9bc12b 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -149,6 +149,11 @@ static const struct { "bcm2835-rpi-cm.dtb", false, }, + [BCM2835_BOARD_REV_A_PLUS] = { + "Model A+", + "bcm2835-rpi-a-plus.dtb", + false, + }, }; u32 rpi_board_rev = 0; @@ -260,12 +265,17 @@ static void get_board_rev(void) } rpi_board_rev = msg->get_board_rev.body.resp.rev; - if (rpi_board_rev >= ARRAY_SIZE(models)) + if (rpi_board_rev >= ARRAY_SIZE(models)) { + printf("RPI: Board rev %u outside known range\n", + rpi_board_rev); rpi_board_rev = 0; + } name = models[rpi_board_rev].name; - if (!name) + if (!name) { + printf("RPI: Board rev %u unknown\n", rpi_board_rev); name = "Unknown model"; + } printf("RPI model: %s\n", name); } -- cgit v1.3.1 From 914627fe1c575112cd2aa14ab83cfa249e6810d6 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 23 Dec 2014 20:01:44 -0700 Subject: ARM: rpi: consolidate board rev error checking Create a fake model table entry with default values, so we can error check the board rev value once when querying it from the firmware, rather than error-checking for invalid board rev values every time the model table is used. Signed-off-by: Stephen Warren --- board/raspberrypi/rpi/rpi.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) (limited to 'board') diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 6227e9bc12b..c18271fce82 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -84,6 +84,11 @@ static const struct { const char *fdtfile; bool has_onboard_eth; } models[] = { + [0] = { + "Unknown model", + "bcm2835-rpi-other.dtb", + false, + }, [BCM2835_BOARD_REV_B_I2C0_2] = { "Model B (no P5)", "bcm2835-rpi-b-i2c0.dtb", @@ -185,9 +190,6 @@ static void set_fdtfile(void) return; fdtfile = models[rpi_board_rev].fdtfile; - if (!fdtfile) - fdtfile = "bcm2835-rpi-other.dtb"; - setenv("fdtfile", fdtfile); } @@ -270,12 +272,12 @@ static void get_board_rev(void) rpi_board_rev); rpi_board_rev = 0; } - - name = models[rpi_board_rev].name; - if (!name) { + if (!models[rpi_board_rev].name) { printf("RPI: Board rev %u unknown\n", rpi_board_rev); - name = "Unknown model"; + rpi_board_rev = 0; } + + name = models[rpi_board_rev].name; printf("RPI model: %s\n", name); } -- cgit v1.3.1