From 0963060c9912c404280e5540018d02777b3400af Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Tue, 11 Dec 2018 11:34:46 +0000 Subject: imx: Add PHYTEC phyBOARD-i.MX6UL-Segin Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on the PHYTEC phyCORE-i.MX6UL SOM (PCL063). CPU: Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 44C Reset cause: POR Board: PHYTEC phyCORE-i.MX6UL I2C: ready DRAM: 256 MiB NAND: 512 MiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: FEC0 Working: - Eth0 - i2C - MMC/SD - NAND - UART (1 & 5) - USB (host & otg) Signed-off-by: Martyn Welch --- board/phytec/pcl063/Kconfig | 12 +++ board/phytec/pcl063/MAINTAINERS | 8 ++ board/phytec/pcl063/Makefile | 7 ++ board/phytec/pcl063/README | 26 +++++ board/phytec/pcl063/pcl063.c | 206 ++++++++++++++++++++++++++++++++++++++++ board/phytec/pcl063/spl.c | 160 +++++++++++++++++++++++++++++++ 6 files changed, 419 insertions(+) create mode 100644 board/phytec/pcl063/Kconfig create mode 100644 board/phytec/pcl063/MAINTAINERS create mode 100644 board/phytec/pcl063/Makefile create mode 100644 board/phytec/pcl063/README create mode 100644 board/phytec/pcl063/pcl063.c create mode 100644 board/phytec/pcl063/spl.c (limited to 'board') diff --git a/board/phytec/pcl063/Kconfig b/board/phytec/pcl063/Kconfig new file mode 100644 index 00000000000..977db70f641 --- /dev/null +++ b/board/phytec/pcl063/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PCL063 + +config SYS_BOARD + default "pcl063" + +config SYS_VENDOR + default "phytec" + +config SYS_CONFIG_NAME + default "pcl063" + +endif diff --git a/board/phytec/pcl063/MAINTAINERS b/board/phytec/pcl063/MAINTAINERS new file mode 100644 index 00000000000..c65a951f3dd --- /dev/null +++ b/board/phytec/pcl063/MAINTAINERS @@ -0,0 +1,8 @@ +PCL063 BOARD +M: Martyn Welch +S: Maintained +F: arch/arm/dts/imx6ul-pcl063.dtsi +F: arch/arm/dts/imx6ul-phycore-segin.dts +F: board/phytec/pcl063/ +F: configs/phycore_pcl063_defconfig +F: include/configs/pcl063.h diff --git a/board/phytec/pcl063/Makefile b/board/phytec/pcl063/Makefile new file mode 100644 index 00000000000..53c73c9b082 --- /dev/null +++ b/board/phytec/pcl063/Makefile @@ -0,0 +1,7 @@ +# Copyright (C) 2018 Collabora Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := pcl063.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/phytec/pcl063/README b/board/phytec/pcl063/README new file mode 100644 index 00000000000..be83bdb0d84 --- /dev/null +++ b/board/phytec/pcl063/README @@ -0,0 +1,26 @@ +How to use U-Boot on PHYTEC phyBOARD-i.MX6UL-Segin +-------------------------------------------------- + +- Configure and build U-Boot for phyCORE-i.MX6UL: + + $ make mrproper + $ make phycore_pcl063_defconfig + $ make + + This will generate SPL and u-boot-dtb.img images. + +- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card: + + $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Jumper settings: + + JP1: Open: Boot from NAND + Closed: Boot from SD/MMC1 + +- Connect the Serial cable to UART0 and the PC for the console. + +- Insert the micro SD card in the board and power it up. + +- U-Boot messages should come up. diff --git a/board/phytec/pcl063/pcl063.c b/board/phytec/pcl063/pcl063.c new file mode 100644 index 00000000000..38b233d1b07 --- /dev/null +++ b/board/phytec/pcl063/pcl063.c @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Collabora Ltd. + * + * Based on board/ccv/xpress/xpress.c: + * Copyright (C) 2015-2016 Stefan Roese + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart5_pads[] = { + MX6_PAD_UART5_TX_DATA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART5_RX_DATA__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); +} + +#ifdef CONFIG_NAND_MXS + +#define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP) + +#define NANDREADYPC MUX_PAD_CTRL(NAND_PAD_READY0_CTRL) + +static iomux_v3_cfg_t const gpmi_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | NANDREADYPC, +}; + +static void setup_gpmi_nand(void) +{ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); +} + +#endif /* CONFIG_NAND_MXS */ + +#ifdef CONFIG_FEC_MXC + +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \ + PAD_CTL_SRE_FAST) + +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_ODE) + +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); +} + +static int setup_fec(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(0, ENET_50MHZ); + if (ret) + return ret; + + /* + * Use 50M anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(1, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + /* + * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select + * 50 MHz RMII clock mode. + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif /* CONFIG_FEC_MXC */ + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_iomux_fec(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + return 0; +} + +int checkboard(void) +{ + puts("Board: PHYTEC phyCORE-i.MX6UL\n"); + + return 0; +} diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c new file mode 100644 index 00000000000..b93cd493f21 --- /dev/null +++ b/board/phytec/pcl063/spl.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Collabora Ltd. + * + * Based on board/ccv/xpress/spl.c: + * Copyright (C) 2015-2016 Stefan Roese + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */ + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpdgctrl0 = 0x41480148, + .p0_mprddlctl = 0x40403E42, + .p0_mpwrdlctl = 0x40405852, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, /* Bus size = 16bit */ + .cs_density = 18, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1, + .rtt_nom = 1, + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .pd_fast_exit = 1, + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 933, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 1, + .trcd = 1391, + .trcmin = 4791, + .trasmin = 3400, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); +} + +static void spl_dram_init(void) +{ + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[] = { + { + .esdhc_base = USDHC1_BASE_ADDR, + .max_bus_width = 4, + }, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +#endif /* CONFIG_FSL_ESDHC */ + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* Setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* Setup iomux and fec */ + board_early_init_f(); + + /* Setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); +} -- cgit v1.3.1 From 9e3c0174da842dd88f5feaffbf843ba332233897 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 11 Dec 2018 16:40:38 -0200 Subject: pico-imx7d: Add LCD support Add support for the VXT VL050-8048NT-C01 panel connected through the 24 bit parallel LCDIF interface. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador --- board/technexion/pico-imx7d/pico-imx7d.c | 55 ++++++++++++++++++++++++++++++++ configs/pico-hobbit-imx7d_defconfig | 1 + configs/pico-imx7d_defconfig | 1 + configs/pico-pi-imx7d_defconfig | 1 + include/configs/pico-imx7d.h | 12 +++++++ 5 files changed, 70 insertions(+) (limited to 'board') diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index 53e14693a53..767d13dfe5d 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -39,8 +39,16 @@ DECLARE_GLOBAL_DATA_PTR; #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_49OHM) + +#define LCD_SYNC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_196OHM) + #ifdef CONFIG_SYS_I2C_MXC #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + /* I2C4 for PMIC */ static struct i2c_pads_info i2c_pad_info4 = { .scl = { @@ -246,11 +254,58 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL), + MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL), + MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL), + MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void setup_lcd(void) +{ + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + /* Set Brightness to high */ + gpio_direction_output(IMX_GPIO_NR(1, 11) , 1); + /* Set LCD enable to high */ + gpio_direction_output(IMX_GPIO_NR(1, 6) , 1); +} +#endif + int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_VIDEO_MXS + setup_lcd(); +#endif #ifdef CONFIG_FEC_MXC setup_fec(); #endif diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index cb4a6bf0bbf..f58d5171ba3 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -57,4 +57,5 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_VIDEO=y CONFIG_OF_LIBFDT=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index f90d75787ac..7e13923cb43 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -57,4 +57,5 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_VIDEO=y CONFIG_OF_LIBFDT=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 8e48ba71bee..c8ac2ffd5f4 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -57,4 +57,5 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_VIDEO=y CONFIG_OF_LIBFDT=y diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 1884c5844de..0f6d6b78945 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -64,10 +64,12 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ + "splashpos=m,m\0" \ "console=ttymxc4\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "videomode=video=ctfb:x:800,y:480,depth:24,mode:0,pclk:30000,le:46,ri:210,up:22,lo:23,hs:20,vs:10,sync:0,vmode:0\0" \ BOOTMENU_ENV \ "fdt_addr=0x83000000\0" \ "fdt_addr_r=0x83000000\0" \ @@ -131,6 +133,16 @@ #define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif + /* FLASH and environment organization */ #define CONFIG_ENV_SIZE SZ_8K -- cgit v1.3.1 From d8a32f52a6fc21c012e55ac5fbcc245493b515b7 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 8 Jan 2019 12:42:29 +0100 Subject: arm: dts: imx7: colibri: split dt for raw NAND and eMMC devices In preparation of adding CONFIG_DM_MMC support use separate device trees for raw NAND and eMMC devices. Signed-off-by: Stefan Agner Acked-by: Marcel Ziswiler --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx7-colibri-emmc.dts | 16 +++++ arch/arm/dts/imx7-colibri-rawnand.dts | 46 ++++++++++++ arch/arm/dts/imx7-colibri.dts | 124 --------------------------------- arch/arm/dts/imx7-colibri.dtsi | 87 +++++++++++++++++++++++ board/toradex/colibri_imx7/MAINTAINERS | 3 + configs/colibri_imx7_defconfig | 2 +- 7 files changed, 154 insertions(+), 127 deletions(-) create mode 100644 arch/arm/dts/imx7-colibri-emmc.dts create mode 100644 arch/arm/dts/imx7-colibri-rawnand.dts delete mode 100644 arch/arm/dts/imx7-colibri.dts create mode 100644 arch/arm/dts/imx7-colibri.dtsi (limited to 'board') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0e0bad9471a..46f1d693dc2 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -464,8 +464,7 @@ dtb-$(CONFIG_MX6UL) += \ dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb -dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ - imx7d-sdb.dtb \ +dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ imx7d-sdb-qspi.dtb dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb diff --git a/arch/arm/dts/imx7-colibri-emmc.dts b/arch/arm/dts/imx7-colibri-emmc.dts new file mode 100644 index 00000000000..295ca059168 --- /dev/null +++ b/arch/arm/dts/imx7-colibri-emmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex AG + */ + +/dts-v1/; +#include "imx7-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX7D 1GB (eMMC)"; + compatible = "toradex,imx7d-colibri-emmc", "fsl,imx7d"; + + chosen { + stdout-path = &uart1; + }; +}; diff --git a/arch/arm/dts/imx7-colibri-rawnand.dts b/arch/arm/dts/imx7-colibri-rawnand.dts new file mode 100644 index 00000000000..4eb86fb011e --- /dev/null +++ b/arch/arm/dts/imx7-colibri-rawnand.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex AG + */ + +/dts-v1/; +#include "imx7-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX7S/D"; + compatible = "toradex,imx7-colibri", "fsl,imx7"; + + chosen { + stdout-path = &uart1; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + fsl,use-minimum-ecc; + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + status = "okay"; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpmi-nand-grp { + fsl,pins = < + MX7D_PAD_SD3_CLK__NAND_CLE 0x71 + MX7D_PAD_SD3_CMD__NAND_ALE 0x71 + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 + MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 + MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 + MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 + MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 + MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 + MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 + MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 + >; + }; +}; diff --git a/arch/arm/dts/imx7-colibri.dts b/arch/arm/dts/imx7-colibri.dts deleted file mode 100644 index dca501be25c..00000000000 --- a/arch/arm/dts/imx7-colibri.dts +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2016 Toradex AG - */ - -/dts-v1/; -#include -#include "imx7d.dtsi" - -/ { - model = "Toradex Colibri iMX7S/D"; - compatible = "toradex,imx7-colibri", "fsl,imx7"; - - chosen { - stdout-path = &uart1; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - fsl,use-minimum-ecc; - nand-on-flash-bbt; - nand-ecc-mode = "hw"; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - scl-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - status = "okay"; - - rn5t567@33 { - compatible = "ricoh,rn5t567"; - reg = <0x33>; - }; -}; - -&i2c4 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - sda-gpios = <&gpio7 9 GPIO_ACTIVE_LOW>; - scl-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; - uart-has-rtscts; - fsl,dte-mode; - status = "okay"; -}; - -&iomuxc { - pinctrl_gpmi_nand: gpmi-nand-grp { - fsl,pins = < - MX7D_PAD_SD3_CLK__NAND_CLE 0x71 - MX7D_PAD_SD3_CMD__NAND_ALE 0x71 - MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 - MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 - MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 - MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 - MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 - MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 - MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 - MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 - MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 - MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 - MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 - MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 - >; - }; - - pinctrl_i2c4: i2c4-grp { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f - MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f - >; - }; - - pinctrl_i2c4_gpio: i2c4-gpio-grp { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f - MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f - >; - }; - - pinctrl_uart1: uart1-grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 - MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 - MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 - >; - }; - - pinctrl_uart1_ctrl1: uart1-ctrl1-grp { - fsl,pins = < - MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */ - MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */ - >; - }; -}; - -&iomuxc_lpsr { - pinctrl_i2c1: i2c1-grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f - MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_i2c1_gpio: i2c1-gpio-grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f - MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f - >; - }; -}; diff --git a/arch/arm/dts/imx7-colibri.dtsi b/arch/arm/dts/imx7-colibri.dtsi new file mode 100644 index 00000000000..47295117aaa --- /dev/null +++ b/arch/arm/dts/imx7-colibri.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2016-2019 Toradex AG + */ + +/dts-v1/; +#include +#include "imx7d.dtsi" + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + scl-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + status = "okay"; + + rn5t567@33 { + compatible = "ricoh,rn5t567"; + reg = <0x33>; + }; +}; + +&i2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + sda-gpios = <&gpio7 9 GPIO_ACTIVE_LOW>; + scl-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; + uart-has-rtscts; + fsl,dte-mode; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c4: i2c4-grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f + MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_i2c4_gpio: i2c4-gpio-grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f + MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 + MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 + MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 + >; + }; + + pinctrl_uart1_ctrl1: uart1-ctrl1-grp { + fsl,pins = < + MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */ + MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */ + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f + MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f + >; + }; +}; diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS index 9c1d42aa8cb..f55f8045f45 100644 --- a/board/toradex/colibri_imx7/MAINTAINERS +++ b/board/toradex/colibri_imx7/MAINTAINERS @@ -8,3 +8,6 @@ F: board/toradex/colibri_imx7/ F: include/configs/colibri_imx7.h F: configs/colibri_imx7_defconfig F: configs/colibri_imx7_emmc_defconfig +F: arch/arm/dts/imx7-colibri.dtsi +F: arch/arm/dts/imx7-colibri-emmc.dts +F: arch/arm/dts/imx7-colibri-rawnand.dts diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 5a496236db0..2e4350c1a65 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -44,7 +44,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:512k(mx7-bcb),1536k(u-boot1)ro,1536k CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y -CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri" +CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri-rawnand" CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DFU_MMC=y -- cgit v1.3.1 From 72a1d113889af1d58e29cbaf9af806cc5dd5630e Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 8 Jan 2019 12:42:34 +0100 Subject: colibri_imx7: drop legacy usdhc support Drop legacy pinmux/usdhc board configuration. Signed-off-by: Stefan Agner Acked-by: Marcel Ziswiler --- board/toradex/colibri_imx7/colibri_imx7.c | 97 ------------------------------- 1 file changed, 97 deletions(-) (limited to 'board') diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index a4c99626b4f..392fda92dae 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -33,9 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ - PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) - #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) @@ -64,17 +61,6 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), }; -static iomux_v3_cfg_t const usdhc1_pads[] = { - MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - - MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - #ifdef CONFIG_USB_EHCI_MX7 static iomux_v3_cfg_t const usb_cdet_pads[] = { MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -109,24 +95,6 @@ static void setup_gpmi_nand(void) } #endif -#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC -static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { - MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), - - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; -#endif - #ifdef CONFIG_VIDEO_MXS static iomux_v3_cfg_t const lcd_pads[] = { MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), @@ -211,71 +179,6 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -#ifdef CONFIG_FSL_ESDHC - -#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 0) - -static struct fsl_esdhc_cfg usdhc_cfg[] = { -#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC - {USDHC3_BASE_ADDR}, -#endif - {USDHC1_BASE_ADDR, 0, 4}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = !gpio_get_value(USDHC1_CD_GPIO); - break; -#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC - case USDHC3_BASE_ADDR: - ret = 1; - break; -#endif - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int i, ret; - /* USDHC1 is mmc0, USDHC3 is mmc1 */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); - gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); - gpio_direction_input(USDHC1_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - break; -#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC - case 1: - imx_iomux_v3_setup_multiple_pads(usdhc3_emmc_pads, - ARRAY_SIZE(usdhc3_emmc_pads)); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; -#endif - default: - printf("Warning: you configured more USDHC controllers" - "(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} -#endif - #ifdef CONFIG_FEC_MXC int board_eth_init(bd_t *bis) { -- cgit v1.3.1 From 018e3fd2d1a73044154056faf0c69d57c81af58f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 21 Dec 2018 06:21:34 +0000 Subject: imx8qxp: mek: default enable SPL Enable SPL for i.MX8QXP MEK, and currently use SPL FIT. The SPL enable SPL_DM to use MMC/PINCTRL/POWER DOMAIN/CLK. Note: SPL FIT could not support secure boot chain, because i.MX8/8X only support i.MX container format. This container format has not been upstreamed, so we use FIT for now. When SPL container supported, we could switch to that. Signed-off-by: Peng Fan --- board/freescale/imx8qxp_mek/Makefile | 1 + board/freescale/imx8qxp_mek/imximage.cfg | 4 +- board/freescale/imx8qxp_mek/spl.c | 75 ++++++++++++++++++++++++++++++++ configs/imx8qxp_mek_defconfig | 24 ++++++++++ include/configs/imx8qxp_mek.h | 26 +++++++++++ 5 files changed, 127 insertions(+), 3 deletions(-) create mode 100644 board/freescale/imx8qxp_mek/spl.c (limited to 'board') diff --git a/board/freescale/imx8qxp_mek/Makefile b/board/freescale/imx8qxp_mek/Makefile index f9ee8aeff36..acaadcd84a4 100644 --- a/board/freescale/imx8qxp_mek/Makefile +++ b/board/freescale/imx8qxp_mek/Makefile @@ -5,3 +5,4 @@ # obj-y += imx8qxp_mek.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/freescale/imx8qxp_mek/imximage.cfg b/board/freescale/imx8qxp_mek/imximage.cfg index bbffb1a88f0..259a1646bf9 100644 --- a/board/freescale/imx8qxp_mek/imximage.cfg +++ b/board/freescale/imx8qxp_mek/imximage.cfg @@ -19,6 +19,4 @@ CONTAINER /* Add scfw image with exec attribute */ IMAGE SCU mx8qx-mek-scfw-tcm.bin /* Add ATF image with exec attribute */ -IMAGE A35 bl31.bin 0x80000000 -/* Add U-Boot image with load attribute */ -DATA A35 u-boot-dtb.bin 0x80020000 +IMAGE A35 spl/u-boot-spl.bin 0x00100000 diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c new file mode 100644 index 00000000000..95ce9f37e8b --- /dev/null +++ b/board/freescale/imx8qxp_mek/spl.c @@ -0,0 +1,75 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + struct udevice *dev; + int offset; + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd"); + while (offset != -FDT_ERR_NOTFOUND) { + lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset), + NULL, true); + offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset, + "nxp,imx8-pd"); + } + + uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index 58b4ca08611..a87dbd17ffb 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -1,11 +1,28 @@ CONFIG_ARM=y CONFIG_ARCH_IMX8=y CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y CONFIG_NR_DRAM_BANKS=3 +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_CPU=y # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_CLK=y @@ -18,8 +35,11 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y CONFIG_CLK_IMX8=y CONFIG_CPU=y CONFIG_DM_GPIO=y @@ -41,12 +61,16 @@ CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8_POWER_DOMAIN=y CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y # CONFIG_EFI_LOADER is not set diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index d34d174cac9..312e30dc6c1 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -9,6 +9,32 @@ #include #include +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_TEXT_BASE 0x0 +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x250 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_MALLOC_F_ADDR 0x00120000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#define CONFIG_OF_EMBED +#endif + #define CONFIG_REMAKE_ELF #define CONFIG_BOARD_EARLY_INIT_F -- cgit v1.3.1 From 59ceb152f84811a89f9f23c52e4eb0c805b9d618 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 21 Dec 2018 06:21:37 +0000 Subject: imx8qxp: mek: update README Update README after we switch to use SPL Signed-off-by: Peng Fan --- board/freescale/imx8qxp_mek/README | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/freescale/imx8qxp_mek/README b/board/freescale/imx8qxp_mek/README index e91e193d117..f32290e3a2b 100644 --- a/board/freescale/imx8qxp_mek/README +++ b/board/freescale/imx8qxp_mek/README @@ -39,16 +39,18 @@ $ cp imx-sc-firmware-0.7/mx8qx-mek-scfw-tcm.bin . Build U-Boot ============ - +$ export ATF_LOAD_ADDR=0x80000000 +$ export BL33_LOAD_ADDR=0x80020000 $ make imx8qxp_mek_defconfig -$ make +$ make flash.bin +$ dd if=u-boot.itb of=flash.bin bs=512 seek=528 Flash the binary into the SD card ================================= Burn the flash.bin binary to SD card offset 32KB: -$ sudo dd if=u-boot-dtb.imx of=/dev/sd[x] bs=1024 seek=32 +$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 Boot ==== -- cgit v1.3.1 From 430630cb032c14880e69ae9d45403d78c318628a Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Wed, 2 Jan 2019 08:58:29 +0200 Subject: imx8mq_evk/README: remove ARCH environment variable There is no need to set the ARCH variable when building U-Boot. In fact, the ARCH name in U-Boot is 'arm'. Signed-off-by: Baruch Siach --- board/freescale/imx8mq_evk/README | 1 - 1 file changed, 1 deletion(-) (limited to 'board') diff --git a/board/freescale/imx8mq_evk/README b/board/freescale/imx8mq_evk/README index 07dbfb01fed..1da6eaf2427 100644 --- a/board/freescale/imx8mq_evk/README +++ b/board/freescale/imx8mq_evk/README @@ -23,7 +23,6 @@ $ cp firmware-imx-7.9/firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srcte Build U-Boot ==================== -$ export ARCH=arm64 $ export CROSS_COMPILE=aarch64-poky-linux- $ make imx8mq_evk_defconfig $ make flash.bin -- cgit v1.3.1 From 764d94736c343ed70201534bdb2cae5bd0193709 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Fri, 18 Jan 2019 17:40:10 +0000 Subject: arm: imx7s-warp: Convert to DM MMC initialization Converts from fixed initialization of MMC to DM initialization of MMC. Signed-off-by: Bryan O'Donoghue Cc: Albert Aribaud Cc: Peng Fan Cc: Fabio Estevam Cc: Stefano Babic --- board/warp7/warp7.c | 34 ---------------------------------- configs/warp7_bl33_defconfig | 1 + configs/warp7_defconfig | 1 + 3 files changed, 2 insertions(+), 34 deletions(-) (limited to 'board') diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index 3d32b3eb52b..146d722b15c 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -30,8 +30,6 @@ DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \ PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ - PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) @@ -74,43 +72,11 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; -static iomux_v3_cfg_t const usdhc3_pads[] = { - MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_RESET_B__SD3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); }; -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC3_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - /* Assume uSDHC3 emmc is always present */ - return 1; -} - -int board_mmc_init(bd_t *bis) -{ - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} - int board_early_init_f(void) { setup_iomux_uart(); diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index 3624b134a56..53665e6fa52 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -25,6 +25,7 @@ CONFIG_OF_CONTROL=y CONFIG_CMD_FS_GENERIC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DFU_MMC=y +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index 66533de3f31..ed2a9fface5 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -34,6 +34,7 @@ CONFIG_OF_CONTROL=y CONFIG_CMD_FS_GENERIC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DFU_MMC=y +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_OPTEE=y CONFIG_USB=y -- cgit v1.3.1 From ce36f56aca33fcfb736f213d5b187fff59b6dd4f Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Fri, 18 Jan 2019 17:40:13 +0000 Subject: warp7: defconfig: Switch to DM for I2C This commit switches to DM I2C for warp7 and warp7_bl33 defconfigs. Signed-off-by: Bryan O'Donoghue Reviewed-by: Peng Fan Cc: Peng Fan Cc: Fabio Estevam Cc: Stefano Babic --- board/warp7/warp7.c | 24 ------------------------ configs/warp7_bl33_defconfig | 1 + configs/warp7_defconfig | 1 + include/configs/warp7.h | 2 -- 4 files changed, 2 insertions(+), 26 deletions(-) (limited to 'board') diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index 146d722b15c..19f0df4d097 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -31,26 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \ PAD_CTL_HYS) -#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ - PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) - -#ifdef CONFIG_SYS_I2C_MXC -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* I2C1 for PMIC */ -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC, - .gp = IMX_GPIO_NR(4, 8), - }, - .sda = { - .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC, - .gp = IMX_GPIO_NR(4, 9), - }, -}; -#endif - int dram_init(void) { gd->ram_size = PHYS_SDRAM_SIZE; @@ -130,10 +110,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - #ifdef CONFIG_SYS_I2C_MXC - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - #endif - return 0; } diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index c7b8c549416..4758d2bcfab 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -45,3 +45,4 @@ CONFIG_DEFAULT_DEVICE_TREE="imx7s-warp" CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index 44d7742ca90..25cf2786dfa 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -58,3 +58,4 @@ CONFIG_DEFAULT_DEVICE_TREE="imx7s-warp" CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y diff --git a/include/configs/warp7.h b/include/configs/warp7.h index a391dfb5c10..41eb8d7e1dd 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -126,9 +126,7 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* I2C configs */ -#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 #define CONFIG_SYS_I2C_SPEED 100000 /* PMIC */ -- cgit v1.3.1 From 8ba377321c862a7498458972618f0278c6c2043b Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Fri, 18 Jan 2019 17:40:14 +0000 Subject: arm: imx7s-warp: Convert to DM PMIC This patch converts the warp7 and warp7_bl33 board ports over to using the DM PMIC model. Signed-off-by: Bryan O'Donoghue Reviewed-by: Peng Fan Cc: Peng Fan Cc: Fabio Estevam Cc: Stefano Babic --- board/warp7/warp7.c | 27 +++++++++++---------------- configs/warp7_bl33_defconfig | 6 ++++++ configs/warp7_defconfig | 6 ++++++ include/configs/warp7.h | 6 ------ 4 files changed, 23 insertions(+), 22 deletions(-) (limited to 'board') diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index 19f0df4d097..6ebeb08e331 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -64,29 +64,24 @@ int board_early_init_f(void) return 0; } -#ifdef CONFIG_POWER -#define I2C_PMIC 0 -static struct pmic *pfuze; +#ifdef CONFIG_DM_PMIC int power_init_board(void) { - int ret; - unsigned int reg, rev_id; + struct udevice *dev; + int ret, dev_id, rev_id; - ret = power_pfuze3000_init(I2C_PMIC); - if (ret) + ret = pmic_get("pfuze3000", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) return ret; - pfuze = pmic_get("PFUZE3000"); - ret = pmic_probe(pfuze); - if (ret) - return ret; - - pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); - pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); - printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); /* disable Low Power Mode during standby mode */ - pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1); + pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); return 0; } diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index 4758d2bcfab..05f40d05eca 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -46,3 +46,9 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index 25cf2786dfa..c01044b1a31 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -59,3 +59,9 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 41eb8d7e1dd..043f2861b62 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -129,12 +129,6 @@ #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_SPEED 100000 -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE3000 -#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 - /* environment organization */ #define CONFIG_ENV_SIZE SZ_8K -- cgit v1.3.1 From 79ae06ff58c9049073ecae15dd55927d32ad5fda Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Fri, 28 Dec 2018 08:47:40 -0600 Subject: imx6q_logic: Enable MMC booting from SPL The MMC booting wasn't previously fitting into the codespace. This patch enables MMC booting from the baseboard by reducing some DM overhead during SPL. Signed-off-by: Adam Ford --- board/logicpd/imx6/imx6logic.c | 72 ++++++++++++++++++++++++++++++++++++++++++ configs/imx6q_logic_defconfig | 15 ++++----- 2 files changed, 78 insertions(+), 9 deletions(-) (limited to 'board') diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c index ce1c8a5d6bc..89cf53c24d8 100644 --- a/board/logicpd/imx6/imx6logic.c +++ b/board/logicpd/imx6/imx6logic.c @@ -60,6 +60,7 @@ static iomux_v3_cfg_t const uart3_pads[] = { MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), }; +#ifndef CONFIG_SPL_BUILD static void fixup_enet_clock(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -108,6 +109,7 @@ static void fixup_enet_clock(void) dm_gpio_set_value(&reset, 1); mdelay(50); } +#endif static void setup_iomux_uart(void) { @@ -158,7 +160,9 @@ int overwrite_console(void) int board_early_init_f(void) { +#ifndef CONFIG_SPL_BUILD fixup_enet_clock(); +#endif setup_iomux_uart(); setup_nand_pins(); return 0; @@ -200,6 +204,74 @@ int spl_start_uboot(void) } #endif +/* SD interface */ +#define USDHC_PAD_CTRL \ + (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[] = { + {USDHC1_BASE_ADDR}, /* SOM */ + {USDHC2_BASE_ADDR} /* Baseboard */ +}; + +int board_mmc_init(bd_t *bis) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned int reg = readl(&psrc->sbmr1) >> 11; + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1-SOM + * 0x2 SD2-Baseboard + */ + + reg &= 0x3; /* Only care about bottom 2 bits */ + + switch (reg) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = usdhc_cfg[1].sdhc_clk; + break; + } + + return fsl_esdhc_initialize(bis, &usdhc_cfg[reg]); +} + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} +#endif + static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index ff2befc0518..fb834b74c49 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -4,26 +4,26 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6LOGICPD=y +CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_SPL=y +CONFIG_SPL_FAT_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_BOUNCE_BUFFER=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SEPARATE_BSS=y +# CONFIG_TPL_BANNER_PRINT is not set +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y @@ -48,13 +48,11 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),16m(kernel),1m(dtb),-(fs)" CONFIG_CMD_UBI=y -CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd" CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_SPL_DM=y CONFIG_PCF8575_GPIO=y -CONFIG_SYS_I2C_MXC=y +CONFIG_DM_I2C=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_FSL_ESDHC=y @@ -65,7 +63,6 @@ CONFIG_PHY_ATHEROS=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC_PFUZE100=y CONFIG_MXC_UART=y -- cgit v1.3.1 From b64b5ad11505b79fc9212fa04124addd34792f65 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Fri, 28 Dec 2018 08:55:41 -0600 Subject: ARM: DTS: imx6q-logicpd: Update DTS/DTSI files The i.MX6 SOM and development kits have undergone significant updates and changes over the past few months. This re-sync's the U-Boot with Logic PD's BSP. Signed-off-by: Adam Ford --- arch/arm/dts/imx6-logicpd-baseboard.dtsi | 596 +++++++++++++++++++++++++++++++ arch/arm/dts/imx6-logicpd-som.dtsi | 373 +++++++++++++++++++ arch/arm/dts/imx6q-logicpd.dts | 188 +++++----- arch/arm/dts/imx6qdl-logicpd.dtsi | 361 ------------------- board/logicpd/imx6/MAINTAINERS | 3 + 5 files changed, 1060 insertions(+), 461 deletions(-) create mode 100644 arch/arm/dts/imx6-logicpd-baseboard.dtsi create mode 100644 arch/arm/dts/imx6-logicpd-som.dtsi delete mode 100644 arch/arm/dts/imx6qdl-logicpd.dtsi (limited to 'board') diff --git a/arch/arm/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/dts/imx6-logicpd-baseboard.dtsi new file mode 100644 index 00000000000..303c09334ba --- /dev/null +++ b/arch/arm/dts/imx6-logicpd-baseboard.dtsi @@ -0,0 +1,596 @@ +/* + * Copyright 2018 Logic PD, Inc. + * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + keyboard { + compatible = "gpio-keys"; + + btn0 { + gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>; + label = "btn0"; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + btn1 { + gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>; + label = "btn1"; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + btn2 { + gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>; + label = "btn2"; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + btn3 { + gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>; + label = "btn3"; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + }; + + leds { + compatible = "gpio-leds"; + + gen_led0 { + label = "led0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led0>; + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + }; + + gen_led1 { + label = "led1"; + gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>; + }; + + gen_led2 { + label = "led2"; + gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + gen_led3 { + label = "led3"; + gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + reg_usb_otg_vbus: regulator-otg-vbus@0 { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_h1_vbus: regulator-usbh1vbus@1 { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_3v3: regulator-3v3@2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_3v3>; + compatible = "regulator-fixed"; + regulator-name = "reg_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_enet: regulator-ethernet@3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_pwr>; + compatible = "regulator-fixed"; + regulator-name = "ethernet-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + vin-supply = <&sw4_reg>; + }; + + reg_audio: regulator-audio@4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_audio>; + compatible = "regulator-fixed"; + regulator-name = "3v3_aud"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_3v3>; + }; + + reg_hdmi: regulator-hdmi@5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_hdmi>; + compatible = "regulator-fixed"; + regulator-name = "hdmi-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_3v3>; + }; + + reg_uart3: regulator-uart3@6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_uart3>; + compatible = "regulator-fixed"; + regulator-name = "uart3-supply"; + gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_3v3>; + }; + + reg_1v8: regulator-1v8@7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_1v8>; + compatible = "regulator-fixed"; + regulator-name = "1v8-supply"; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_3v3>; + }; + + reg_pcie: regulator@8 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + mipi_pwr: regulator@9 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_pwr>; + regulator-name = "mipi_pwr_en"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + ssi-controller = <&ssi2>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + mux-int-port = <2>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-duration = <10>; + phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + phy-supply = <®_enet>; + interrupt-parent = <&gpio1>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + no-1-8-v; + keep-power-in-suspend; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xclk"; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + PLLVDD-supply = <®_audio>; + SPKVDD1-supply = <®_audio>; + SPKVDD2-supply = <®_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0013 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x8014 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; +}; + +&i2c3 { + ov5640: camera@10 { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x10>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xclk"; + DOVDD-supply = <&mipi_pwr>; + AVDD-supply = <&mipi_pwr>; + DVDD-supply = <&mipi_pwr>; + reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; + powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; + + port { + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + + pcf8575: gpio@20 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcf8574>; + compatible = "nxp,pcf8575"; + reg = <0x20>; + interrupt-parent = <&gpio6>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + lines-initial-states = <0x0710>; + wakeup-source; + }; +}; + +&mipi_csi { + status = "okay"; + + port@0 { + reg = <0>; + + mipi_csi2_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; + status = "okay"; + vpcie-supply = <®_pcie>; + /* fsl,max-link-speed = <2>; */ +}; + +&ssi2 { + status = "okay"; +}; + +&iomuxc { + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; + + pinctrl_i2c1: i2c1 { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_enet_pwr: enet_pwr { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 + >; + }; + + pinctrl_mipi_pwr: pwr_mipi { + fsl,pins = ; + }; + + pinctrl_ov5640: ov5640grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b1 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b1 + >; + }; + + pinctrl_reg_hdmi: reg_hdmi { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059 + MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069 + >; + }; + + pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */ + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */ + >; + }; + + pinctrl_reg_audio: audio-reg { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + >; + }; + + pinctrl_pcie: pcie { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_pcie_reg: pciereggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + pinctrl_pcf8574: pcf8575-pins { + fsl,pins = < + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* R_LCD_DCLK */ + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */ + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* R_LCD_HSYNC */ + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* R_LCD_VSYNC */ + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* R_LCD_MDISP */ + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_uart3: uart3reg { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + >; + }; + + pinctrl_reg_3v3: reg-3v3 { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 + >; + }; + + pinctrl_reg_1v8: reg-1v8 { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 + >; + }; + + pinctrl_led0: led0 { + fsl,pins = < + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6-logicpd-som.dtsi b/arch/arm/dts/imx6-logicpd-som.dtsi new file mode 100644 index 00000000000..3fc50babf09 --- /dev/null +++ b/arch/arm/dts/imx6-logicpd-som.dtsi @@ -0,0 +1,373 @@ +/* + * Copyright 2018 Logic PD + * This file is adapted from imx6qdl-sabresd.dtsi. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x10000000 0x80000000>; + }; + + reg_wl18xx_vmmc: regulator-wl18xx { + compatible = "regulator-fixed"; + regulator-name = "vwl1837"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 0 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +/* Reroute power feeding the CPU to come from the external PMIC */ +®_arm +{ + vin-supply = <&sw1a_reg>; +}; + +®_soc +{ + vin-supply = <&sw1c_reg>; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; + nand-on-flash-bbt; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vddcore"; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vddsoc"; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "gen_3v3"; + regulator-boot-on; + /* regulator-always-on; */ + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-name = "sw3a_vddr"; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-name = "sw3b_vddr"; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "gen_rgmii"; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-name = "gen_5v0"; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "gen_vsns"; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "gen_1v5"; + }; + + vgen2_reg: vgen2 { + regulator-name = "vgen2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-name = "gen_vadj_0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + vgen4_reg: vgen4 { + regulator-name = "gen_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-name = "gen_adj_1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-name = "gen_2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + coin_reg: coin { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + }; + }; + + temp_sense0: tmp102@4a { + compatible = "ti,tmp102"; + reg = <0x4a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tempsense>; + interrupt-parent = <&gpio6>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; + + temp_sense1: tmp102@49 { + compatible = "ti,tmp102"; + reg = <0x49>; + interrupt-parent = <&gpio6>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; + + mfg_eeprom: at24@51 { + compatible = "atmel,24c64"; + pagesize = <32>; + read-only; + reg = <0x51>; + }; + + user_eeprom: at24@52 { + compatible = "atmel,24c64"; + pagesize = <32>; + reg = <0x52>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x1b0b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */ + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17049 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10049 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17049 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17049 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17049 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17049 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x130b0 /* WL_IRQ */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* WLAN_EN */ + >; + }; + + pinctrl_tempsense: tempsensegrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Temp Sense Alert */ + >; + }; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; + uart-has-rtscts; + bluetooth { + compatible = "ti,wl1837-st"; + enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + non-removable; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; + vmmc-supply = <&sw2_reg>; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_wl18xx_vmmc>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupt-parent = <&gpio7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + tcxo-clock-frequency = <26000000>; + }; +}; diff --git a/arch/arm/dts/imx6q-logicpd.dts b/arch/arm/dts/imx6q-logicpd.dts index d1e7a389d09..dcea784477b 100644 --- a/arch/arm/dts/imx6q-logicpd.dts +++ b/arch/arm/dts/imx6q-logicpd.dts @@ -1,5 +1,5 @@ /* - * Copyright 2017 Logic PD, Inc. + * Copyright 2018 Logic PD, Inc. * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc. * * This file is dual-licensed: you can use it either under the terms @@ -42,149 +42,137 @@ */ /dts-v1/; - -#include "imx6qdl-logicpd.dtsi" +#include "imx6q.dtsi" +#include "imx6-logicpd-som.dtsi" +#include "imx6-logicpd-baseboard.dtsi" / { - model = "Logic PD i.MX6QDL SOM"; + model = "Logic PD i.MX6QD SOM-M3 (HDMI)"; compatible = "fsl,imx6q"; - reg_usb_otg_vbus: regulator-otg-vbus@0 { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; + backlight: backlight_lvds { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 20000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <®_lcd>; }; - reg_usb_h1_vbus: regulator-usbh1vbus@1 { + reg_lcd: regulator-lcd { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_reg>; compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + regulator-name = "lcd_panel_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + vin-supply = <®_3v3>; + startup-delay-us = <500000>; }; - reg_3v3: regulator-3v3@2 { + lcd_reset: lcd_reset { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_reset>; compatible = "regulator-fixed"; - regulator-name = "reg_3v3"; + regulator-name = "nLCD_RESET"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_lcd>; + }; + + panel-lvds0 { + compatible = "ampire,am800480b3tmqw"; + backlight = <&backlight>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; }; }; -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; +&hdmi { + ddc-i2c-bus = <&i2c3>; status = "okay"; }; -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; +&i2c1 { + ili_touch: ilitouch@26 { + compatible = "ili,ili2117a"; + reg = <0x26>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_RISING>; + ili2117a,poll-period = <10>; + ili2117a,max-touch = <2>; + }; }; -&usbh2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh2>; - phy_type = "hsic"; - disable-over-current; - status = "okay"; +®_hdmi { + regulator-always-on; }; -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; +&ldb { status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; + }; -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rmii"; - phy-speed = <10>; +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; +}; + +&pwm3 { status = "okay"; }; &usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - status = "okay"; }; &iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* nINT */ - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 /* Ethernet Reset */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x130b0 - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x130b0 - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x130b0 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 - >; - }; - pinctrl_uart3: uart3grp { + pinctrl_lcd_reg: lcdreg { fsl,pins = < - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */ >; }; - pinctrl_usbh1: usbh1grp { + pinctrl_lcd_reset: lcdreset { fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* USB_H1_PWR_EN */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */ >; }; - pinctrl_usbh2: usbh2grp { + pinctrl_touchscreen: touchscreengrp { fsl,pins = < - MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x17030 - MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x13030 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 /* USB_OTG_PWR_EN */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* TOUCH_nPINTDAV */ >; }; }; + diff --git a/arch/arm/dts/imx6qdl-logicpd.dtsi b/arch/arm/dts/imx6qdl-logicpd.dtsi deleted file mode 100644 index db1a63dcdeb..00000000000 --- a/arch/arm/dts/imx6qdl-logicpd.dtsi +++ /dev/null @@ -1,361 +0,0 @@ -/* - * Copyright 2016 Logic PD - * This file is adapted from imx6qdl-sabresd.dtsi. - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include "imx6q.dtsi" - -/ { - chosen { - stdout-path = &uart1; - }; - - memory { - reg = <0x10000000 0x80000000>; - }; -}; - -/* Reroute power feeding the CPU to come from the external PMIC */ -®_arm -{ - vin-supply = <&sw1a_reg>; -}; - -®_soc -{ - vin-supply = <&sw1c_reg>; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pmic: pfuze100@08 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vddcore"; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vddsoc"; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "gen_3v3"; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-name = "sw3a_vddr"; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-name = "sw3b_vddr"; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "gen_rgmii"; - }; - - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-name = "gen_5v0"; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "gen_vsns"; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "gen_1v5"; - }; - - vgen2_reg: vgen2 { - regulator-name = "vgen2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-name = "gen_vadj_0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - vgen4_reg: vgen4 { - regulator-name = "gen_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-name = "gen_adj_1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-name = "gen_2v5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - }; - }; - - mfg_eeprom: at24@51 { - compatible = "atmel,24c64"; - pagesize = <32>; - read-only; - reg = <0x51>; - }; - - user_eeprom: at24@52 { - compatible = "atmel,24c64"; - pagesize = <32>; - reg = <0x52>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0 - MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0 - MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x1b0b0 - MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x1b0b0 - MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x1b0b0 - MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x1b0b0 - MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x1b0b0 - MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x1b0b0 - MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x1b0b0 - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x80000000 - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x80000000 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x80000000 - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x80000000 - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000 - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000 - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000 - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x80000000 - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 - MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x80000000 - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x80000000 - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x80000000 - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x80000000 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x80000000 - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x80000000 - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x80000000 - MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x80000000 - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x80000000 - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x80000000 - MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x80000000 - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x80000000 - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x80000000 - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 - MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x80000000 - MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x80000000 - MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x80000000 - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 - MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 - MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000 - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x80000000 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x80000000 - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x80000000 - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000 - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000 - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x80000000 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x80000000 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x80000000 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 - MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x80000000 - MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x80000000 - MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x80000000 - MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x80000000 - MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x80000000 - MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x80000000 - MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x80000000 - MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x80000000 - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x80000000 - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WL_IRQ */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1f0b0 /* WLAN_EN */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1f0b0 /* BT_EN */ - >; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; - keep-power-in-suspend; - enable-sdio-wakeup; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - non-removable; - keep-power-in-suspend; - enable-sdio-wakeup; - vmmc-supply = <&sw2_reg>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@0 { - compatible = "ti,wl1837"; - reg = <2>; - interrupt-parent = <&gpio7>; - interrupts = <1 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/board/logicpd/imx6/MAINTAINERS b/board/logicpd/imx6/MAINTAINERS index 5db7d2cadd9..20ec5918e48 100644 --- a/board/logicpd/imx6/MAINTAINERS +++ b/board/logicpd/imx6/MAINTAINERS @@ -4,3 +4,6 @@ S: Maintained F: board/logicpd/imx6/ F: include/configs/imx6_logic.h F: configs/imx6q_logic_defconfig +F: arch/arm/dts/imx6-logicpd-baseboard.dtsi +F: arch/arm/dts/imx6-logicpd-som.dtsi +F: arch/arm/dts/imx6q-logicpd.dts -- cgit v1.3.1 From 6d69e535116ba9d6d3b8e4dc57cf3543301b59df Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Fri, 28 Dec 2018 10:24:15 -0600 Subject: ARM: imx6q_logic: Enable Falcon Mode and fatwrite This patch enables Falcon Mode by default and updates the README file to show instructions on how to run from the micro SD card or eMMC. This patch also enables fatwrite to help assist with writing the 'args' to the microSD card. Signed-off-by: Adam Ford --- board/logicpd/imx6/README | 48 ++++++++++++++++++++++++++++++++++++++++++- configs/imx6q_logic_defconfig | 2 ++ 2 files changed, 49 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/logicpd/imx6/README b/board/logicpd/imx6/README index df43b55d6bf..26d053a32c3 100644 --- a/board/logicpd/imx6/README +++ b/board/logicpd/imx6/README @@ -22,8 +22,17 @@ To build U-Boot for the Dual and Quad variants: Flashing U-Boot into the SD card -------------------------------- +U-Boot is now building with SPL enabled which means there are two files to +load into the SD card. Make sure the card is formatted with at least two +partitions with the first partition being FAT32. First copy u-boot-dtb.img +to the first partition then burn SPL to the SD card with dd. +The SPL portion is programmed into a certain location for use by the internal +bootROM and it cannot be changed. The following instructions assume the SD +card is located as /dev/sdb. + + cp u-boot-dtb.img /dev/media/logic/boot + sudo dd if=SPL of=/dev/sdb bs=1k seek=1 oflag=sync status=none && sync -See README.imximage for details on booting from SD Flashing U-Boot into NAND ------------------------- @@ -32,6 +41,43 @@ with: kobs-ng init -v -x u-boot-dtb.imx + +Using Falcon Mode +----------------- +With Falcon Mode enabled, U-Boot can be bypassed by having SPL directly load +the kernel. The device tree, Kernel and boot args must first be configured, +and stored to a file on the micro SD card called 'args' +The kernel uImage is built with LOAD_ADDR=0x12000000 and the device tree is +assummed to be imx6q-logicpd.dtb. + +By default the mmcroot is set to the baseboard. + + # Establish bootargs + run mmcargs + + # Load Linux Kernel uImage + fatload mmc 1 $loadaddr uImage + + # Load Device Tree + run loadfdt + + # Setup the blob that will get passed to the kernel + spl export fdt ${loadaddr} - ${fdt_addr_r} + + # Note the starting and ending address of the updated device tree. + # for this example: + # Loading Device Tree to 1ffdf000, end 1fff038b ... OK + # Notice that 0x1fff038b - 1ffdf000 = 0x1138b + # now Add 1, so the length is 0x1138c. + + fatwrite mmc 1 0x1ffdf000 args 0x1138c + + # Reset the board and it will bypass U-Boot and SPL will directly boot + # the uImage + +To interrupt the boot sequence and force U-Boot to load, hold the 'c' button +while starting. + Additional Support Documentation can be found at: https://support.logicpd.com/ diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index b5b6d011b9d..ec5b96c02f9 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_OS_BOOT=y CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_USB_GADGET=y @@ -78,3 +79,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_FAT_WRITE=y -- cgit v1.3.1