From cffe815a7656420884e816bb9110ad052889405a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 3 Nov 2013 22:03:03 -0200 Subject: wandboard: Return the error immediately when ipuv3_fb_init() fails If ipuv3_fb_init() fails, we should return the error immediately. Signed-off-by: Fabio Estevam --- board/wandboard/wandboard.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 23a78c16638..99150f9b895 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -230,8 +230,10 @@ int board_video_skip(void) ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24); - if (ret) + if (ret) { printf("HDMI cannot be configured: %d\n", ret); + return ret; + } imx_enable_hdmi_phy(); -- cgit v1.3.1 From c243a832c85d832151f647b1f83e6d6120527f34 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 3 Nov 2013 22:03:04 -0200 Subject: wandboard: Return the error when cpu_eth_init() fails When cpu_eth_init() fails we should not return success. Signed-off-by: Fabio Estevam --- board/wandboard/wandboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 99150f9b895..bf9898c3fe0 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -265,7 +265,7 @@ int board_eth_init(bd_t *bis) if (ret) printf("FEC MXC: %s:failed\n", __func__); - return 0; + return ret; } int board_early_init_f(void) -- cgit v1.3.1 From 90fb985863670afd70b7a534df12fd451476a964 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 3 Nov 2013 22:12:56 -0200 Subject: titanium: Return the error when cpu_eth_init() fails When cpu_eth_init() fails we should not return success. Signed-off-by: Fabio Estevam Acked-by: Stefan Roese --- board/freescale/titanium/titanium.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/titanium/titanium.c b/board/freescale/titanium/titanium.c index 6025eb73155..9a317bc1378 100644 --- a/board/freescale/titanium/titanium.c +++ b/board/freescale/titanium/titanium.c @@ -272,7 +272,7 @@ int board_eth_init(bd_t *bis) if (ret) printf("FEC MXC: %s:failed\n", __func__); - return 0; + return ret; } int board_early_init_f(void) -- cgit v1.3.1 From c2cde27d58cfa0b09b8ed4577fa313fdfaa57660 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 4 Nov 2013 08:35:28 +0100 Subject: mx6: titanium: Move BSP code to barco board directory Since the titanium board is not a Freescale board, move its BSP code from the freescale board directory to the newly created barco board directory. Signed-off-by: Stefan Roese Cc: Peter Korsgaard Cc: Stefano Babic Acked-by: Peter Korsgaard --- board/barco/titanium/Makefile | 9 + board/barco/titanium/imximage.cfg | 167 ++++++++++++++++++ board/barco/titanium/titanium.c | 323 ++++++++++++++++++++++++++++++++++ board/freescale/titanium/Makefile | 9 - board/freescale/titanium/imximage.cfg | 167 ------------------ board/freescale/titanium/titanium.c | 323 ---------------------------------- boards.cfg | 2 +- 7 files changed, 500 insertions(+), 500 deletions(-) create mode 100644 board/barco/titanium/Makefile create mode 100644 board/barco/titanium/imximage.cfg create mode 100644 board/barco/titanium/titanium.c delete mode 100644 board/freescale/titanium/Makefile delete mode 100644 board/freescale/titanium/imximage.cfg delete mode 100644 board/freescale/titanium/titanium.c (limited to 'board') diff --git a/board/barco/titanium/Makefile b/board/barco/titanium/Makefile new file mode 100644 index 00000000000..0ad4cb9b156 --- /dev/null +++ b/board/barco/titanium/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := titanium.o diff --git a/board/barco/titanium/imximage.cfg b/board/barco/titanium/imximage.cfg new file mode 100644 index 00000000000..7219256ae0a --- /dev/null +++ b/board/barco/titanium/imximage.cfg @@ -0,0 +1,167 @@ +/* + * Projectiondesign AS + * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg + * + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * sd, nand + */ +BOOT_FROM nand + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 + +DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 + +DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 + +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 + +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 + +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 + +/* (differential input) */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +/* disable ddr pullups */ +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +/* (differential input) */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 + +/* Read data DQ Byte0-3 delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + +/* + * MDMISC mirroring interleaved (row/bank/col) + */ +DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 + +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 +DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F diff --git a/board/barco/titanium/titanium.c b/board/barco/titanium/titanium.c new file mode 100644 index 00000000000..9a317bc1378 --- /dev/null +++ b/board/barco/titanium/titanium.c @@ -0,0 +1,323 @@ +/* + * Copyright (C) 2013 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO_5_27 | PC, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO_5_26 | PC, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, + .gp = IMX_GPIO_NR(7, 11) + } +}; + +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t const enet_pads1[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* pin 35 - 1 (PHY_AD2) on reset */ + MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 42 PHY nRST */ + MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads2[] = { + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +iomux_v3_cfg_t nfc_pads[] = { + MX6_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nfc_pads, + ARRAY_SIZE(nfc_pads)); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} + +static void setup_iomux_enet(void) +{ + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); + gpio_direction_output(IMX_GPIO_NR(6, 30), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + + /* Need delay 10ms according to KSZ9021 spec */ + udelay(1000 * 10); + gpio_set_value(IMX_GPIO_NR(3, 23), 1); + + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); +} + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); +} + +#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{ + return 0; +} + +#endif + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[1] = { + { USDHC3_BASE_ADDR }, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) { + gpio_direction_input(IMX_GPIO_NR(7, 0)); + return !gpio_get_value(IMX_GPIO_NR(7, 0)); + } + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + /* + * Only one USDHC controller on titianium + */ + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} +#endif + +int board_phy_config(struct phy_device *phydev) +{ + /* min rx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); + /* min tx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); + /* max rx/tx clock delay, min rx/tx control */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_enet(); + + ret = cpu_eth_init(bis); + if (ret) + printf("FEC MXC: %s:failed\n", __func__); + + return ret; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + + setup_gpmi_nand(); + + return 0; +} + +int checkboard(void) +{ + puts("Board: Titanium\n"); + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* NAND */ + { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, + /* 4 bit bus width */ + { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) }, + { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) }, + { NULL, 0 }, +}; +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + return 0; +} diff --git a/board/freescale/titanium/Makefile b/board/freescale/titanium/Makefile deleted file mode 100644 index 0ad4cb9b156..00000000000 --- a/board/freescale/titanium/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (C) 2007, Guennadi Liakhovetski -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := titanium.o diff --git a/board/freescale/titanium/imximage.cfg b/board/freescale/titanium/imximage.cfg deleted file mode 100644 index 7219256ae0a..00000000000 --- a/board/freescale/titanium/imximage.cfg +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Projectiondesign AS - * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg - * - * Copyright (C) 2011 Freescale Semiconductor, Inc. - * Jason Liu - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Refer docs/README.imxmage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * sd, nand - */ -BOOT_FROM nand - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -#define __ASSEMBLY__ -#include -#include "asm/arch/mx6-ddr.h" -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 - -DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 - -DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 -DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 - -DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 -DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 - -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 - -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 - -DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 - -/* (differential input) */ -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -/* disable ddr pullups */ -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -/* (differential input) */ -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 - -/* Read data DQ Byte0-3 delay */ -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 - -/* - * MDMISC mirroring interleaved (row/bank/col) - */ -DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 - -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 -DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21 -DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 -DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 -DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 -DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B -DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039 -DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 -DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 -DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359 -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348 -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341 -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933 -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36 -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044 -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F diff --git a/board/freescale/titanium/titanium.c b/board/freescale/titanium/titanium.c deleted file mode 100644 index 9a317bc1378..00000000000 --- a/board/freescale/titanium/titanium.c +++ /dev/null @@ -1,323 +0,0 @@ -/* - * Copyright (C) 2013 Stefan Roese - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - - return 0; -} - -iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) - -struct i2c_pads_info i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO_5_27 | PC, - .gp = IMX_GPIO_NR(5, 27) - }, - .sda = { - .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO_5_26 | PC, - .gp = IMX_GPIO_NR(5, 26) - } -}; - -struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, - .gp = IMX_GPIO_NR(7, 11) - } -}; - -iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -iomux_v3_cfg_t const enet_pads1[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - /* pin 35 - 1 (PHY_AD2) on reset */ - MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 32 - 1 - (MODE0) all */ - MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 31 - 1 - (MODE1) all */ - MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 28 - 1 - (MODE2) all */ - MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 27 - 1 - (MODE3) all */ - MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ - MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 42 PHY nRST */ - MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -iomux_v3_cfg_t const enet_pads2[] = { - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -iomux_v3_cfg_t nfc_pads[] = { - MX6_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_gpmi_nand(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - /* config gpmi nand iomux */ - imx_iomux_v3_setup_multiple_pads(nfc_pads, - ARRAY_SIZE(nfc_pads)); - - /* config gpmi and bch clock to 100 MHz */ - clrsetbits_le32(&mxc_ccm->cs2cdr, - MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, - MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | - MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | - MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); - - /* enable gpmi and bch clock gating */ - setbits_le32(&mxc_ccm->CCGR4, - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); - - /* enable apbh clock gating */ - setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); -} - -static void setup_iomux_enet(void) -{ - gpio_direction_output(IMX_GPIO_NR(3, 23), 0); - gpio_direction_output(IMX_GPIO_NR(6, 30), 1); - gpio_direction_output(IMX_GPIO_NR(6, 25), 1); - gpio_direction_output(IMX_GPIO_NR(6, 27), 1); - gpio_direction_output(IMX_GPIO_NR(6, 28), 1); - gpio_direction_output(IMX_GPIO_NR(6, 29), 1); - imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); - gpio_direction_output(IMX_GPIO_NR(6, 24), 1); - - /* Need delay 10ms according to KSZ9021 spec */ - udelay(1000 * 10); - gpio_set_value(IMX_GPIO_NR(3, 23), 1); - - imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); -} - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); - imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); - imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); -} - -#ifdef CONFIG_USB_EHCI_MX6 -int board_ehci_hcd_init(int port) -{ - return 0; -} - -#endif - -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg usdhc_cfg[1] = { - { USDHC3_BASE_ADDR }, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - - if (cfg->esdhc_base == USDHC3_BASE_ADDR) { - gpio_direction_input(IMX_GPIO_NR(7, 0)); - return !gpio_get_value(IMX_GPIO_NR(7, 0)); - } - - return 0; -} - -int board_mmc_init(bd_t *bis) -{ - /* - * Only one USDHC controller on titianium - */ - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} -#endif - -int board_phy_config(struct phy_device *phydev) -{ - /* min rx data delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); - /* min tx data delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); - /* max rx/tx clock delay, min rx/tx control */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int board_eth_init(bd_t *bis) -{ - int ret; - - setup_iomux_enet(); - - ret = cpu_eth_init(bis); - if (ret) - printf("FEC MXC: %s:failed\n", __func__); - - return ret; -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); - - setup_gpmi_nand(); - - return 0; -} - -int checkboard(void) -{ - puts("Board: Titanium\n"); - - return 0; -} - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* NAND */ - { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, - /* 4 bit bus width */ - { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) }, - { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) }, - { NULL, 0 }, -}; -#endif - -int misc_init_r(void) -{ -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - - return 0; -} diff --git a/boards.cfg b/boards.cfg index 36f09242a59..7a32d3f2c7b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -302,7 +302,7 @@ Active arm armv7 mx6 freescale mx6qsabreauto Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam -Active arm armv7 mx6 freescale titanium titanium titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg Stefan Roese +Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat -- cgit v1.3.1 From 10fda48779fc86e74e4482cbc7667431237cf60c Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Mon, 4 Nov 2013 17:00:51 -0700 Subject: i.MX6DQ/DLS: replace pad names with their Linux kernel equivalents Signed-off-by: Eric Nelson --- arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 1824 ++++++++++++------------- arch/arm/include/asm/arch-mx6/mx6q_pins.h | 1698 +++++++++++------------ board/barco/titanium/titanium.c | 106 +- board/boundary/nitrogen6x/nitrogen6x.c | 170 +-- board/congatec/cgtqmx6eval/cgtqmx6eval.c | 40 +- board/freescale/mx6qarm2/mx6qarm2.c | 66 +- board/freescale/mx6qsabreauto/mx6qsabreauto.c | 60 +- board/freescale/mx6sabresd/mx6sabresd.c | 90 +- board/udoo/udoo.c | 20 +- board/wandboard/wandboard.c | 54 +- 10 files changed, 2064 insertions(+), 2064 deletions(-) (limited to 'board') diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index 73734078e99..94f49c01f3e 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -10,399 +10,399 @@ #include enum { - MX6_PAD_CSI0_DAT10__IPU1_CSI0_D_10 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x0360, 0x004C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__AUD3_RXC = IOMUX_PAD(0x0360, 0x004C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0360, 0x004C, 2, 0x07F8, 0, 0), - MX6_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__UART1_RXD = IOMUX_PAD(0x0360, 0x004C, 3, 0x08FC, 0, 0), + MX6_PAD_CSI0_DAT10__UART1_TX_DATA = IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__UART1_RX_DATA = IOMUX_PAD(0x0360, 0x004C, 3, 0x08FC, 0, 0), MX6_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x0360, 0x004C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__GPIO_5_28 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__GPIO5_IO28 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__SIMBA_TRACE_7 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__IPU1_CSI0_D_11 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x0364, 0x0050, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__ARM_TRACE07 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__AUD3_RXFS = IOMUX_PAD(0x0364, 0x0050, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0800, 0, 0), - MX6_PAD_CSI0_DAT11__UART1_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0), + MX6_PAD_CSI0_DAT11__UART1_TX_DATA = IOMUX_PAD(0x0364, 0x0050, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA = IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0), MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0364, 0x0050, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__GPIO_5_29 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__GPIO5_IO29 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 = IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__SIMBA_TRACE_8 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__IPU1_CSI0_D_12 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__WEIM_WEIM_D_8 = IOMUX_PAD(0x0368, 0x0054, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__ARM_TRACE08 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__EIM_DATA08 = IOMUX_PAD(0x0368, 0x0054, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 = IOMUX_PAD(0x0368, 0x0054, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_TXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x0914, 0, 0), + MX6_PAD_CSI0_DAT12__UART4_TX_DATA = IOMUX_PAD(0x0368, 0x0054, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__UART4_RX_DATA = IOMUX_PAD(0x0368, 0x0054, 3, 0x0914, 0, 0), MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0368, 0x0054, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__GPIO_5_30 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__GPIO5_IO30 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__SIMBA_TRACE_9 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__IPU1_CSI0_D_13 = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__WEIM_WEIM_D_9 = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__ARM_TRACE09 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__EIM_DATA09 = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 = IOMUX_PAD(0x036C, 0x0058, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_TXD = IOMUX_PAD(0x036C, 0x0058, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_RXD = IOMUX_PAD(0x036C, 0x0058, 3, 0x0914, 1, 0), + MX6_PAD_CSI0_DAT13__UART4_TX_DATA = IOMUX_PAD(0x036C, 0x0058, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__UART4_RX_DATA = IOMUX_PAD(0x036C, 0x0058, 3, 0x0914, 1, 0), MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x036C, 0x0058, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__GPIO_5_31 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__GPIO5_IO31 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__SIMBA_TRACE_10 = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__IPU1_CSI0_D_14 = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__WEIM_WEIM_D_10 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__ARM_TRACE10 = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__EIM_DATA10 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 = IOMUX_PAD(0x0370, 0x005C, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_TXD = IOMUX_PAD(0x0370, 0x005C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_RXD = IOMUX_PAD(0x0370, 0x005C, 3, 0x091C, 0, 0), + MX6_PAD_CSI0_DAT14__UART5_TX_DATA = IOMUX_PAD(0x0370, 0x005C, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__UART5_RX_DATA = IOMUX_PAD(0x0370, 0x005C, 3, 0x091C, 0, 0), MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0370, 0x005C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__GPIO_6_0 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__GPIO6_IO00 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__SIMBA_TRACE_11 = IOMUX_PAD(0x0370, 0x005C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__IPU1_CSI0_D_15 = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__WEIM_WEIM_D_11 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__ARM_TRACE11 = IOMUX_PAD(0x0370, 0x005C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__EIM_DATA11 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 = IOMUX_PAD(0x0374, 0x0060, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_TXD = IOMUX_PAD(0x0374, 0x0060, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_RXD = IOMUX_PAD(0x0374, 0x0060, 3, 0x091C, 1, 0), + MX6_PAD_CSI0_DAT15__UART5_TX_DATA = IOMUX_PAD(0x0374, 0x0060, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__UART5_RX_DATA = IOMUX_PAD(0x0374, 0x0060, 3, 0x091C, 1, 0), MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0374, 0x0060, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__GPIO_6_1 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__GPIO6_IO01 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__SIMBA_TRACE_12 = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__IPU1_CSI0_D_16 = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__WEIM_WEIM_D_12 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__ARM_TRACE12 = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__EIM_DATA12 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 = IOMUX_PAD(0x0378, 0x0064, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_CTS = IOMUX_PAD(0x0378, 0x0064, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x0378, 0x0064, 3, 0x0910, 0, 0), + MX6_PAD_CSI0_DAT16__UART4_CTS_B = IOMUX_PAD(0x0378, 0x0064, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__UART4_RTS_B = IOMUX_PAD(0x0378, 0x0064, 3, 0x0910, 0, 0), MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x0378, 0x0064, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__GPIO_6_2 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__GPIO6_IO02 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__SIMBA_TRACE_13 = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__IPU1_CSI0_D_17 = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__WEIM_WEIM_D_13 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__ARM_TRACE13 = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__EIM_DATA13 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 = IOMUX_PAD(0x037C, 0x0068, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x037C, 0x0068, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__UART4_RTS = IOMUX_PAD(0x037C, 0x0068, 3, 0x0910, 1, 0), + MX6_PAD_CSI0_DAT17__UART4_CTS_B = IOMUX_PAD(0x037C, 0x0068, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__UART4_RTS_B = IOMUX_PAD(0x037C, 0x0068, 3, 0x0910, 1, 0), MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x037C, 0x0068, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__GPIO_6_3 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__GPIO6_IO03 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__SIMBA_TRACE_14 = IOMUX_PAD(0x037C, 0x0068, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__IPU1_CSI0_D_18 = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__WEIM_WEIM_D_14 = IOMUX_PAD(0x0380, 0x006C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__ARM_TRACE14 = IOMUX_PAD(0x037C, 0x0068, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__EIM_DATA14 = IOMUX_PAD(0x0380, 0x006C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 = IOMUX_PAD(0x0380, 0x006C, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_CTS = IOMUX_PAD(0x0380, 0x006C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x0380, 0x006C, 3, 0x0918, 0, 0), + MX6_PAD_CSI0_DAT18__UART5_CTS_B = IOMUX_PAD(0x0380, 0x006C, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__UART5_RTS_B = IOMUX_PAD(0x0380, 0x006C, 3, 0x0918, 0, 0), MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0380, 0x006C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__GPIO_6_4 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__GPIO6_IO04 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__SIMBA_TRACE_15 = IOMUX_PAD(0x0380, 0x006C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__IPU1_CSI0_D_19 = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__WEIM_WEIM_D_15 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__ARM_TRACE15 = IOMUX_PAD(0x0380, 0x006C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__EIM_DATA15 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 = IOMUX_PAD(0x0384, 0x0070, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x0384, 0x0070, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__UART5_RTS = IOMUX_PAD(0x0384, 0x0070, 3, 0x0918, 1, 0), + MX6_PAD_CSI0_DAT19__UART5_CTS_B = IOMUX_PAD(0x0384, 0x0070, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__UART5_RTS_B = IOMUX_PAD(0x0384, 0x0070, 3, 0x0918, 1, 0), MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0384, 0x0070, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__GPIO_6_5 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__GPIO6_IO05 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 = IOMUX_PAD(0x0384, 0x0070, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__IPU1_CSI0_D_4 = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__WEIM_WEIM_D_2 = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__EIM_DATA02 = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0388, 0x0074, 2, 0x07D8, 0, 0), - MX6_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x0388, 0x0074, 3, 0x08C0, 0, 0), - MX6_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0388, 0x0074, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__GPIO_5_22 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__KEY_COL5 = IOMUX_PAD(0x0388, 0x0074, 3, 0x08C0, 0, 0), + MX6_PAD_CSI0_DAT4__AUD3_TXC = IOMUX_PAD(0x0388, 0x0074, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__GPIO5_IO22 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__SIMBA_TRACE_1 = IOMUX_PAD(0x0388, 0x0074, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__IPU1_CSI0_D_5 = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__WEIM_WEIM_D_3 = IOMUX_PAD(0x038C, 0x0078, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__ARM_TRACE01 = IOMUX_PAD(0x0388, 0x0074, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__EIM_DATA03 = IOMUX_PAD(0x038C, 0x0078, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x038C, 0x0078, 2, 0x07E0, 0, 0), - MX6_PAD_CSI0_DAT5__KPP_ROW_5 = IOMUX_PAD(0x038C, 0x0078, 3, 0x08CC, 0, 0), - MX6_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x038C, 0x0078, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__GPIO_5_23 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__KEY_ROW5 = IOMUX_PAD(0x038C, 0x0078, 3, 0x08CC, 0, 0), + MX6_PAD_CSI0_DAT5__AUD3_TXD = IOMUX_PAD(0x038C, 0x0078, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__GPIO5_IO23 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__SIMBA_TRACE_2 = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__IPU1_CSI0_D_6 = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__WEIM_WEIM_D_4 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__ARM_TRACE02 = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__EIM_DATA04 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0390, 0x007C, 2, 0x07DC, 0, 0), - MX6_PAD_CSI0_DAT6__KPP_COL_6 = IOMUX_PAD(0x0390, 0x007C, 3, 0x08C4, 0, 0), - MX6_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x0390, 0x007C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__GPIO_5_24 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__KEY_COL6 = IOMUX_PAD(0x0390, 0x007C, 3, 0x08C4, 0, 0), + MX6_PAD_CSI0_DAT6__AUD3_TXFS = IOMUX_PAD(0x0390, 0x007C, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__GPIO5_IO24 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__SIMBA_TRACE_3 = IOMUX_PAD(0x0390, 0x007C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__IPU1_CSI0_D_7 = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__WEIM_WEIM_D_5 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__ARM_TRACE03 = IOMUX_PAD(0x0390, 0x007C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__EIM_DATA05 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0394, 0x0080, 2, 0x07E4, 0, 0), - MX6_PAD_CSI0_DAT7__KPP_ROW_6 = IOMUX_PAD(0x0394, 0x0080, 3, 0x08D0, 0, 0), - MX6_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x0394, 0x0080, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__GPIO_5_25 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__KEY_ROW6 = IOMUX_PAD(0x0394, 0x0080, 3, 0x08D0, 0, 0), + MX6_PAD_CSI0_DAT7__AUD3_RXD = IOMUX_PAD(0x0394, 0x0080, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__GPIO5_IO25 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__SIMBA_TRACE_4 = IOMUX_PAD(0x0394, 0x0080, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__IPU1_CSI0_D_8 = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__WEIM_WEIM_D_6 = IOMUX_PAD(0x0398, 0x0084, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__ARM_TRACE04 = IOMUX_PAD(0x0394, 0x0080, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__EIM_DATA06 = IOMUX_PAD(0x0398, 0x0084, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0398, 0x0084, 2, 0x07F4, 0, 0), - MX6_PAD_CSI0_DAT8__KPP_COL_7 = IOMUX_PAD(0x0398, 0x0084, 3, 0x08C8, 0, 0), + MX6_PAD_CSI0_DAT8__KEY_COL7 = IOMUX_PAD(0x0398, 0x0084, 3, 0x08C8, 0, 0), MX6_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0), - MX6_PAD_CSI0_DAT8__GPIO_5_26 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__GPIO5_IO26 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__SIMBA_TRACE_5 = IOMUX_PAD(0x0398, 0x0084, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__IPU1_CSI0_D_9 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__WEIM_WEIM_D_7 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__ARM_TRACE05 = IOMUX_PAD(0x0398, 0x0084, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__EIM_DATA07 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x039C, 0x0088, 2, 0x07FC, 0, 0), - MX6_PAD_CSI0_DAT9__KPP_ROW_7 = IOMUX_PAD(0x039C, 0x0088, 3, 0x08D4, 0, 0), + MX6_PAD_CSI0_DAT9__KEY_ROW7 = IOMUX_PAD(0x039C, 0x0088, 3, 0x08D4, 0, 0), MX6_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0), - MX6_PAD_CSI0_DAT9__GPIO_5_27 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__GPIO5_IO27 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 = IOMUX_PAD(0x039C, 0x0088, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__SIMBA_TRACE_6 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__ARM_TRACE06 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__EIM_DATA00 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 = IOMUX_PAD(0x03A0, 0x008C, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__GPIO_5_20 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 = IOMUX_PAD(0x03A0, 0x008C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__SIMBA_TRCLK = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__ARM_TRACE_CLK = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__CCM_CLKO = IOMUX_PAD(0x03A4, 0x0090, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__CCM_CLKO1 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__GPIO_5_19 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__GPIO5_IO19 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x03A4, 0x0090, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__SIMBA_TRCTL = IOMUX_PAD(0x03A4, 0x0090, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__ARM_TRACE_CTL = IOMUX_PAD(0x03A4, 0x0090, 7, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__GPIO_5_18 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 = IOMUX_PAD(0x03A8, 0x0094, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__SIMBA_EVENTO = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_PIXCLK__ARM_EVENTO = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 = IOMUX_PAD(0x03AC, 0x0098, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__EIM_DATA01 = IOMUX_PAD(0x03AC, 0x0098, 1, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__GPIO_5_21 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__GPIO5_IO21 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 = IOMUX_PAD(0x03AC, 0x0098, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__SIMBA_TRACE_0 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__ARM_TRACE00 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_DISP_CLK__LCDIF_CLK = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0000, 0, 0), + MX6_PAD_DI0_DISP_CLK__LCD_CLK = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 = IOMUX_PAD(0x03B0, 0x009C, 4, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), + MX6_PAD_DI0_DISP_CLK__GPIO4_IO16 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__TPSMP_HDATA_DIR = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__LCDIF_WR_RWN = IOMUX_PAD(0x03B0, 0x009C, 8, 0x0000, 0, 0), + MX6_PAD_DI0_DISP_CLK__LCD_WR_RWN = IOMUX_PAD(0x03B0, 0x009C, 8, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN15__LCDIF_ENABLE = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__LCD_ENABLE = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__AUD6_TXC = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__GPIO4_IO17 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__PL301_SIM_MX6DL_PER1_HSIZE_0 = IOMUX_PAD(0x03B4, 0x00A0, 7, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__LCDIF_RD_E = IOMUX_PAD(0x03B4, 0x00A0, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN2__LCDIF_HSYNC = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x08D8, 0, 0), - MX6_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__LCD_RD_E = IOMUX_PAD(0x03B4, 0x00A0, 8, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN2__LCD_HSYNC = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x08D8, 0, 0), + MX6_PAD_DI0_PIN2__AUD6_TXD = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__GPIO4_IO18 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 = IOMUX_PAD(0x03B8, 0x00A4, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__PL301_SIM_MX6DL_PER1_HADDR_9 = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__LCDIF_RS = IOMUX_PAD(0x03B8, 0x00A4, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN3__LCDIF_VSYNC = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__LCD_RS = IOMUX_PAD(0x03B8, 0x00A4, 8, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN3__LCD_VSYNC = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__AUD6_TXFS = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__GPIO_4_19 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__GPIO4_IO19 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__PL301_SIM_MX6DL_PER1_HADDR_10 = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__LCDIF_CS = IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__LCDIF_BUSY = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, 0), - MX6_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x092C, 0, 0), + MX6_PAD_DI0_PIN3__LCD_CS = IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN4__LCD_BUSY = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, 0), + MX6_PAD_DI0_PIN4__AUD6_RXD = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__SD1_WP = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x092C, 0, 0), MX6_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__GPIO4_IO20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__PL301_SIM_MX6DL_PER1_HADDR_11 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__LCDIF_RESET = IOMUX_PAD(0x03C0, 0x00AC, 8, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT0__LCDIF_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__LCD_RESET = IOMUX_PAD(0x03C0, 0x00AC, 8, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT0__LCD_DATA00 = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN = IOMUX_PAD(0x03C4, 0x00B0, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT0__GPIO4_IO21 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__PL301_SIM_MX6DL_PER1_HSIZE_1 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT1__LCDIF_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT1__LCD_DATA01 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT1__GPIO4_IO22 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__PL301_SIM_MX6DL_PER1_HADDR_12 = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT10__LCDIF_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT10__LCD_DATA10 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT10__GPIO4_IO31 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__PL301_SIM_MX6DL_PER1_HADDR_21 = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT11__LCDIF_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT11__LCD_DATA11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT11__GPIO5_IO05 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__PL301_SIM_MX6DL_PER1_HADDR_22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT12__LCDIF_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT12__LCD_DATA12 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT12__GPIO5_IO06 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__PL301_SIM_MX6DL_PER1_HADDR_23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT13__LCDIF_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x07BC, 0, 0), + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT13__LCD_DATA13 = IOMUX_PAD(0x03D8, 0x00C4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT13__AUD5_RXFS = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x07BC, 0, 0), MX6_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT13__GPIO5_IO07 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT13__PL301_SIM_MX6DL_PER1_HADDR_24 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT14__LCDIF_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03DC, 0x00C8, 3, 0x07B8, 0, 0), + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT14__LCD_DATA14 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT14__AUD5_RXC = IOMUX_PAD(0x03DC, 0x00C8, 3, 0x07B8, 0, 0), MX6_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT14__GPIO5_IO08 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT14__PL301_SIM_MX6DL_PER1_HSIZE_2 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT15__LCDIF_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT15__LCD_DATA15 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x07E8, 0, 0), MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0804, 0, 0), MX6_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT15__GPIO5_IO09 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__PL301_SIM_MX6DL_PER1_HADDR_25 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT16__LCDIF_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT16__LCD_DATA16 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x07FC, 1, 0), - MX6_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x07C0, 0, 0), - MX6_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x08E8, 0, 0), - MX6_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT16__AUD5_TXC = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x07C0, 0, 0), + MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x08E8, 0, 0), + MX6_PAD_DISP0_DAT16__GPIO5_IO10 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__PL301_SIM_MX6DL_PER1_HADDR_26 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT17__LCDIF_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT17__LCD_DATA17 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x07F8, 1, 0), - MX6_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x07B4, 0, 0), - MX6_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x08EC, 0, 0), - MX6_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT17__AUD5_TXD = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x07B4, 0, 0), + MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x08EC, 0, 0), + MX6_PAD_DISP0_DAT17__GPIO5_IO11 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__PL301_SIM_MX6DL_PER1_HADDR_27 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT18__LCDIF_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT18__LCD_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x0800, 1, 0), - MX6_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x07C4, 0, 0), - MX6_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x07A4, 0, 0), - MX6_PAD_DISP0_DAT18__GPIO_5_12 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT18__AUD5_TXFS = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x07C4, 0, 0), + MX6_PAD_DISP0_DAT18__AUD4_RXFS = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x07A4, 0, 0), + MX6_PAD_DISP0_DAT18__GPIO5_IO12 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 = IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT19__LCDIF_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT18__EIM_CS2_B = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT19__LCD_DATA19 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x07F4, 1, 0), - MX6_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x03F0, 0x00DC, 3, 0x07B0, 0, 0), - MX6_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x03F0, 0x00DC, 4, 0x07A0, 0, 0), - MX6_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT19__AUD5_RXD = IOMUX_PAD(0x03F0, 0x00DC, 3, 0x07B0, 0, 0), + MX6_PAD_DISP0_DAT19__AUD4_RXC = IOMUX_PAD(0x03F0, 0x00DC, 4, 0x07A0, 0, 0), + MX6_PAD_DISP0_DAT19__GPIO5_IO13 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT2__LCDIF_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT19__EIM_CS3_B = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__LCD_DATA02 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__GPIO4_IO23 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 = IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__PL301_SIM_MX6DL_PER1_HADDR_13 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT20__LCDIF_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT20__LCD_DATA20 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x07D8, 1, 0), - MX6_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x07A8, 0, 0), + MX6_PAD_DISP0_DAT20__AUD4_TXC = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x07A8, 0, 0), MX6_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT20__GPIO5_IO14 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 = IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__PL301_SIM_MX6DL_PER1_HADDR_28 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT21__LCDIF_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT21__LCD_DATA21 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x07E0, 1, 0), - MX6_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x079C, 0, 0), + MX6_PAD_DISP0_DAT21__AUD4_TXD = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x079C, 0, 0), MX6_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT21__GPIO5_IO15 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 = IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__PL301_SIM_MX6DL_PER1_HADDR_29 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT22__LCDIF_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT22__LCD_DATA22 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x0400, 0x00EC, 2, 0x07DC, 1, 0), - MX6_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x0400, 0x00EC, 3, 0x07AC, 0, 0), + MX6_PAD_DISP0_DAT22__AUD4_TXFS = IOMUX_PAD(0x0400, 0x00EC, 3, 0x07AC, 0, 0), MX6_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT22__GPIO5_IO16 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 = IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__PL301_SIM_MX6DL_PER1_HADDR_30 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT23__LCDIF_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT23__LCD_DATA23 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x07E4, 1, 0), - MX6_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0798, 0, 0), + MX6_PAD_DISP0_DAT23__AUD4_RXD = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0798, 0, 0), MX6_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT23__GPIO5_IO17 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 = IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__PL301_SIM_MX6DL_PER1_HADDR_31 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT3__LCDIF_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT3__LCD_DATA03 = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0408, 0x00F4, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 = IOMUX_PAD(0x0408, 0x00F4, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT3__GPIO4_IO24 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 = IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__PL301_SIM_MX6DL_PER1_HADDR_14 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT4__LCDIF_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT4__LCD_DATA04 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 = IOMUX_PAD(0x040C, 0x00F8, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT4__GPIO4_IO25 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__PL301_SIM_MX6DL_PER1_HADDR_15 = IOMUX_PAD(0x040C, 0x00F8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT5__LCDIF_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT5__LCD_DATA05 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0410, 0x00FC, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__AUD6_RXFS = IOMUX_PAD(0x0410, 0x00FC, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__GPIO4_IO26 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 = IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__PL301_SIM_MX6DL_PER1_HADDR_16 = IOMUX_PAD(0x0410, 0x00FC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT6__LCDIF_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT6__LCD_DATA06 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x0414, 0x0100, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC = IOMUX_PAD(0x0414, 0x0100, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__AUD6_RXC = IOMUX_PAD(0x0414, 0x0100, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__GPIO4_IO27 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 = IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__PL301_SIM_MX6DL_PER1_HADDR_17 = IOMUX_PAD(0x0414, 0x0100, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT7__LCDIF_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT7__LCD_DATA07 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x0418, 0x0104, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 = IOMUX_PAD(0x0418, 0x0104, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT7__GPIO4_IO28 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 = IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__PL301_SIM_MX6DL_PER1_HADDR_18 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT8__LCDIF_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x041C, 0x0108, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x041C, 0x0108, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT8__LCD_DATA08 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__PWM1_OUT = IOMUX_PAD(0x041C, 0x0108, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__WDOG1_B = IOMUX_PAD(0x041C, 0x0108, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x041C, 0x0108, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__GPIO4_IO29 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 = IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__PL301_SIM_MX6DL_PER1_HADDR_19 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT9__LCDIF_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x0420, 0x010C, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT9__LCD_DATA09 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__PWM2_OUT = IOMUX_PAD(0x0420, 0x010C, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__WDOG2_B = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x0420, 0x010C, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__GPIO4_IO30 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 = IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__PL301_SIM_MX6DL_PER1_HADDR_20 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0), MX6_PAD_DRAM_A0__MMDC_DRAM_A_0 = IOMUX_PAD(0x0424, NO_MUX_I, 0, 0x0000, 0, 0), @@ -516,635 +516,635 @@ enum { MX6_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 = IOMUX_PAD(0x04D4, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 = IOMUX_PAD(0x04D8, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_SDWE__MMDC_DRAM_SDWE = IOMUX_PAD(0x04DC, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A16__WEIM_WEIM_A_16 = IOMUX_PAD(0x04E0, 0x0110, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A16__EIM_ADDR16 = IOMUX_PAD(0x04E0, 0x0110, 0, 0x0000, 0, 0), MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x04E0, 0x0110, 1, 0x0000, 0, 0), MX6_PAD_EIM_A16__IPU1_CSI1_PIXCLK = IOMUX_PAD(0x04E0, 0x0110, 2, 0x08B8, 0, 0), MX6_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 = IOMUX_PAD(0x04E0, 0x0110, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A16__GPIO_2_22 = IOMUX_PAD(0x04E0, 0x0110, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A16__GPIO2_IO22 = IOMUX_PAD(0x04E0, 0x0110, 5, 0x0000, 0, 0), MX6_PAD_EIM_A16__TPSMP_HDATA_6 = IOMUX_PAD(0x04E0, 0x0110, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A16__SRC_BT_CFG_16 = IOMUX_PAD(0x04E0, 0x0110, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A16__EPDC_SDDO_0 = IOMUX_PAD(0x04E0, 0x0110, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A17__WEIM_WEIM_A_17 = IOMUX_PAD(0x04E4, 0x0114, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU1_DISP1_DAT_12 = IOMUX_PAD(0x04E4, 0x0114, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU1_CSI1_D_12 = IOMUX_PAD(0x04E4, 0x0114, 2, 0x0890, 0, 0), + MX6_PAD_EIM_A16__SRC_BOOT_CFG16 = IOMUX_PAD(0x04E0, 0x0110, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A16__EPDC_DATA00 = IOMUX_PAD(0x04E0, 0x0110, 8, 0x0000, 0, 0), + MX6_PAD_EIM_A17__EIM_ADDR17 = IOMUX_PAD(0x04E4, 0x0114, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 = IOMUX_PAD(0x04E4, 0x0114, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A17__IPU1_CSI1_DATA12 = IOMUX_PAD(0x04E4, 0x0114, 2, 0x0890, 0, 0), MX6_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 = IOMUX_PAD(0x04E4, 0x0114, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A17__GPIO_2_21 = IOMUX_PAD(0x04E4, 0x0114, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A17__GPIO2_IO21 = IOMUX_PAD(0x04E4, 0x0114, 5, 0x0000, 0, 0), MX6_PAD_EIM_A17__TPSMP_HDATA_5 = IOMUX_PAD(0x04E4, 0x0114, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A17__SRC_BT_CFG_17 = IOMUX_PAD(0x04E4, 0x0114, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A17__EPDC_PWRSTAT = IOMUX_PAD(0x04E4, 0x0114, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A18__WEIM_WEIM_A_18 = IOMUX_PAD(0x04E8, 0x0118, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU1_DISP1_DAT_13 = IOMUX_PAD(0x04E8, 0x0118, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU1_CSI1_D_13 = IOMUX_PAD(0x04E8, 0x0118, 2, 0x0894, 0, 0), + MX6_PAD_EIM_A17__SRC_BOOT_CFG17 = IOMUX_PAD(0x04E4, 0x0114, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A17__EPDC_PWR_STAT = IOMUX_PAD(0x04E4, 0x0114, 8, 0x0000, 0, 0), + MX6_PAD_EIM_A18__EIM_ADDR18 = IOMUX_PAD(0x04E8, 0x0118, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 = IOMUX_PAD(0x04E8, 0x0118, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A18__IPU1_CSI1_DATA13 = IOMUX_PAD(0x04E8, 0x0118, 2, 0x0894, 0, 0), MX6_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 = IOMUX_PAD(0x04E8, 0x0118, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A18__GPIO_2_20 = IOMUX_PAD(0x04E8, 0x0118, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A18__GPIO2_IO20 = IOMUX_PAD(0x04E8, 0x0118, 5, 0x0000, 0, 0), MX6_PAD_EIM_A18__TPSMP_HDATA_4 = IOMUX_PAD(0x04E8, 0x0118, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A18__SRC_BT_CFG_18 = IOMUX_PAD(0x04E8, 0x0118, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A18__EPDC_PWRCTRL_0 = IOMUX_PAD(0x04E8, 0x0118, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A19__WEIM_WEIM_A_19 = IOMUX_PAD(0x04EC, 0x011C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU1_DISP1_DAT_14 = IOMUX_PAD(0x04EC, 0x011C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU1_CSI1_D_14 = IOMUX_PAD(0x04EC, 0x011C, 2, 0x0898, 0, 0), + MX6_PAD_EIM_A18__SRC_BOOT_CFG18 = IOMUX_PAD(0x04E8, 0x0118, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A18__EPDC_PWR_CTRL0 = IOMUX_PAD(0x04E8, 0x0118, 8, 0x0000, 0, 0), + MX6_PAD_EIM_A19__EIM_ADDR19 = IOMUX_PAD(0x04EC, 0x011C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 = IOMUX_PAD(0x04EC, 0x011C, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A19__IPU1_CSI1_DATA14 = IOMUX_PAD(0x04EC, 0x011C, 2, 0x0898, 0, 0), MX6_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 = IOMUX_PAD(0x04EC, 0x011C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A19__GPIO_2_19 = IOMUX_PAD(0x04EC, 0x011C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A19__GPIO2_IO19 = IOMUX_PAD(0x04EC, 0x011C, 5, 0x0000, 0, 0), MX6_PAD_EIM_A19__TPSMP_HDATA_3 = IOMUX_PAD(0x04EC, 0x011C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A19__SRC_BT_CFG_19 = IOMUX_PAD(0x04EC, 0x011C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A19__EPDC_PWRCTRL_1 = IOMUX_PAD(0x04EC, 0x011C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A20__WEIM_WEIM_A_20 = IOMUX_PAD(0x04F0, 0x0120, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU1_DISP1_DAT_15 = IOMUX_PAD(0x04F0, 0x0120, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU1_CSI1_D_15 = IOMUX_PAD(0x04F0, 0x0120, 2, 0x089C, 0, 0), + MX6_PAD_EIM_A19__SRC_BOOT_CFG19 = IOMUX_PAD(0x04EC, 0x011C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A19__EPDC_PWR_CTRL1 = IOMUX_PAD(0x04EC, 0x011C, 8, 0x0000, 0, 0), + MX6_PAD_EIM_A20__EIM_ADDR20 = IOMUX_PAD(0x04F0, 0x0120, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 = IOMUX_PAD(0x04F0, 0x0120, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A20__IPU1_CSI1_DATA15 = IOMUX_PAD(0x04F0, 0x0120, 2, 0x089C, 0, 0), MX6_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 = IOMUX_PAD(0x04F0, 0x0120, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A20__GPIO_2_18 = IOMUX_PAD(0x04F0, 0x0120, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A20__GPIO2_IO18 = IOMUX_PAD(0x04F0, 0x0120, 5, 0x0000, 0, 0), MX6_PAD_EIM_A20__TPSMP_HDATA_2 = IOMUX_PAD(0x04F0, 0x0120, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A20__SRC_BT_CFG_20 = IOMUX_PAD(0x04F0, 0x0120, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A20__EPDC_PWRCTRL_2 = IOMUX_PAD(0x04F0, 0x0120, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A21__WEIM_WEIM_A_21 = IOMUX_PAD(0x04F4, 0x0124, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU1_DISP1_DAT_16 = IOMUX_PAD(0x04F4, 0x0124, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU1_CSI1_D_16 = IOMUX_PAD(0x04F4, 0x0124, 2, 0x08A0, 0, 0), + MX6_PAD_EIM_A20__SRC_BOOT_CFG20 = IOMUX_PAD(0x04F0, 0x0120, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A20__EPDC_PWR_CTRL2 = IOMUX_PAD(0x04F0, 0x0120, 8, 0x0000, 0, 0), + MX6_PAD_EIM_A21__EIM_ADDR21 = IOMUX_PAD(0x04F4, 0x0124, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 = IOMUX_PAD(0x04F4, 0x0124, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A21__IPU1_CSI1_DATA16 = IOMUX_PAD(0x04F4, 0x0124, 2, 0x08A0, 0, 0), MX6_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 = IOMUX_PAD(0x04F4, 0x0124, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A21__GPIO_2_17 = IOMUX_PAD(0x04F4, 0x0124, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A21__GPIO2_IO17 = IOMUX_PAD(0x04F4, 0x0124, 5, 0x0000, 0, 0), MX6_PAD_EIM_A21__TPSMP_HDATA_1 = IOMUX_PAD(0x04F4, 0x0124, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A21__SRC_BT_CFG_21 = IOMUX_PAD(0x04F4, 0x0124, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A21__SRC_BOOT_CFG21 = IOMUX_PAD(0x04F4, 0x0124, 7, 0x0000, 0, 0), MX6_PAD_EIM_A21__EPDC_GDCLK = IOMUX_PAD(0x04F4, 0x0124, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A22__WEIM_WEIM_A_22 = IOMUX_PAD(0x04F8, 0x0128, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU1_DISP1_DAT_17 = IOMUX_PAD(0x04F8, 0x0128, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU1_CSI1_D_17 = IOMUX_PAD(0x04F8, 0x0128, 2, 0x08A4, 0, 0), - MX6_PAD_EIM_A22__GPIO_2_16 = IOMUX_PAD(0x04F8, 0x0128, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A22__EIM_ADDR22 = IOMUX_PAD(0x04F8, 0x0128, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 = IOMUX_PAD(0x04F8, 0x0128, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A22__IPU1_CSI1_DATA17 = IOMUX_PAD(0x04F8, 0x0128, 2, 0x08A4, 0, 0), + MX6_PAD_EIM_A22__GPIO2_IO16 = IOMUX_PAD(0x04F8, 0x0128, 5, 0x0000, 0, 0), MX6_PAD_EIM_A22__TPSMP_HDATA_0 = IOMUX_PAD(0x04F8, 0x0128, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A22__SRC_BT_CFG_22 = IOMUX_PAD(0x04F8, 0x0128, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A22__SRC_BOOT_CFG22 = IOMUX_PAD(0x04F8, 0x0128, 7, 0x0000, 0, 0), MX6_PAD_EIM_A22__EPDC_GDSP = IOMUX_PAD(0x04F8, 0x0128, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A23__WEIM_WEIM_A_23 = IOMUX_PAD(0x04FC, 0x012C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_DISP1_DAT_18 = IOMUX_PAD(0x04FC, 0x012C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_CSI1_D_18 = IOMUX_PAD(0x04FC, 0x012C, 2, 0x08A8, 0, 0), - MX6_PAD_EIM_A23__IPU1_SISG_3 = IOMUX_PAD(0x04FC, 0x012C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A23__GPIO_6_6 = IOMUX_PAD(0x04FC, 0x012C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A23__EIM_ADDR23 = IOMUX_PAD(0x04FC, 0x012C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 = IOMUX_PAD(0x04FC, 0x012C, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A23__IPU1_CSI1_DATA18 = IOMUX_PAD(0x04FC, 0x012C, 2, 0x08A8, 0, 0), + MX6_PAD_EIM_A23__IPU1_SISG3 = IOMUX_PAD(0x04FC, 0x012C, 4, 0x0000, 0, 0), + MX6_PAD_EIM_A23__GPIO6_IO06 = IOMUX_PAD(0x04FC, 0x012C, 5, 0x0000, 0, 0), MX6_PAD_EIM_A23__PL301_SIM_MX6DL_PER1_HPROT_3 = IOMUX_PAD(0x04FC, 0x012C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A23__SRC_BT_CFG_23 = IOMUX_PAD(0x04FC, 0x012C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A23__SRC_BOOT_CFG23 = IOMUX_PAD(0x04FC, 0x012C, 7, 0x0000, 0, 0), MX6_PAD_EIM_A23__EPDC_GDOE = IOMUX_PAD(0x04FC, 0x012C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A24__WEIM_WEIM_A_24 = IOMUX_PAD(0x0500, 0x0130, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_DISP1_DAT_19 = IOMUX_PAD(0x0500, 0x0130, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_CSI1_D_19 = IOMUX_PAD(0x0500, 0x0130, 2, 0x08AC, 0, 0), - MX6_PAD_EIM_A24__IPU1_SISG_2 = IOMUX_PAD(0x0500, 0x0130, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A24__GPIO_5_4 = IOMUX_PAD(0x0500, 0x0130, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A24__EIM_ADDR24 = IOMUX_PAD(0x0500, 0x0130, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 = IOMUX_PAD(0x0500, 0x0130, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A24__IPU1_CSI1_DATA19 = IOMUX_PAD(0x0500, 0x0130, 2, 0x08AC, 0, 0), + MX6_PAD_EIM_A24__IPU1_SISG2 = IOMUX_PAD(0x0500, 0x0130, 4, 0x0000, 0, 0), + MX6_PAD_EIM_A24__GPIO5_IO04 = IOMUX_PAD(0x0500, 0x0130, 5, 0x0000, 0, 0), MX6_PAD_EIM_A24__PL301_SIM_MX6DL_PER1_HPROT_2 = IOMUX_PAD(0x0500, 0x0130, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A24__SRC_BT_CFG_24 = IOMUX_PAD(0x0500, 0x0130, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A24__SRC_BOOT_CFG24 = IOMUX_PAD(0x0500, 0x0130, 7, 0x0000, 0, 0), MX6_PAD_EIM_A24__EPDC_GDRL = IOMUX_PAD(0x0500, 0x0130, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A25__WEIM_WEIM_A_25 = IOMUX_PAD(0x0504, 0x0134, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A25__EIM_ADDR25 = IOMUX_PAD(0x0504, 0x0134, 0, 0x0000, 0, 0), MX6_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x0504, 0x0134, 1, 0x0000, 0, 0), MX6_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x0504, 0x0134, 2, 0x0000, 0, 0), MX6_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x0504, 0x0134, 3, 0x0000, 0, 0), MX6_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x0504, 0x0134, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A25__GPIO_5_2 = IOMUX_PAD(0x0504, 0x0134, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A25__GPIO5_IO02 = IOMUX_PAD(0x0504, 0x0134, 5, 0x0000, 0, 0), MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x0504, 0x0134, 6, 0x085C, 0, 0), MX6_PAD_EIM_A25__PL301_SIM_MX6DL_PER1_HBURST_0 = IOMUX_PAD(0x0504, 0x0134, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A25__EPDC_SDDO_15 = IOMUX_PAD(0x0504, 0x0134, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A25__WEIM_ACLK_FREERUN = IOMUX_PAD(0x0504, 0x0134, 9, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__WEIM_WEIM_BCLK = IOMUX_PAD(0x0508, 0x0138, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A25__EPDC_DATA15 = IOMUX_PAD(0x0504, 0x0134, 8, 0x0000, 0, 0), + MX6_PAD_EIM_A25__EIM_ACLK_FREERUN = IOMUX_PAD(0x0504, 0x0134, 9, 0x0000, 0, 0), + MX6_PAD_EIM_BCLK__EIM_BCLK = IOMUX_PAD(0x0508, 0x0138, 0, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x0508, 0x0138, 1, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__GPIO_6_31 = IOMUX_PAD(0x0508, 0x0138, 5, 0x0000, 0, 0), + MX6_PAD_EIM_BCLK__GPIO6_IO31 = IOMUX_PAD(0x0508, 0x0138, 5, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x0508, 0x0138, 6, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__EPDC_SDCE_9 = IOMUX_PAD(0x0508, 0x0138, 8, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__WEIM_WEIM_CS_0 = IOMUX_PAD(0x050C, 0x013C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__IPU1_DI1_PIN5 = IOMUX_PAD(0x050C, 0x013C, 1, 0x0000, 0, 0), + MX6_PAD_EIM_BCLK__EPDC_SDCE9 = IOMUX_PAD(0x0508, 0x0138, 8, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__EIM_CS0_B = IOMUX_PAD(0x050C, 0x013C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__IPU1_DI1_PIN05 = IOMUX_PAD(0x050C, 0x013C, 1, 0x0000, 0, 0), MX6_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x050C, 0x013C, 2, 0x07F4, 2, 0), MX6_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 = IOMUX_PAD(0x050C, 0x013C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__GPIO_2_23 = IOMUX_PAD(0x050C, 0x013C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__GPIO2_IO23 = IOMUX_PAD(0x050C, 0x013C, 5, 0x0000, 0, 0), MX6_PAD_EIM_CS0__TPSMP_HDATA_7 = IOMUX_PAD(0x050C, 0x013C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__EPDC_SDDO_6 = IOMUX_PAD(0x050C, 0x013C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__WEIM_WEIM_CS_1 = IOMUX_PAD(0x0510, 0x0140, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__IPU1_DI1_PIN6 = IOMUX_PAD(0x0510, 0x0140, 1, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__EPDC_DATA06 = IOMUX_PAD(0x050C, 0x013C, 8, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__EIM_CS1_B = IOMUX_PAD(0x0510, 0x0140, 0, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__IPU1_DI1_PIN06 = IOMUX_PAD(0x0510, 0x0140, 1, 0x0000, 0, 0), MX6_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0510, 0x0140, 2, 0x07FC, 2, 0), MX6_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 = IOMUX_PAD(0x0510, 0x0140, 4, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__GPIO_2_24 = IOMUX_PAD(0x0510, 0x0140, 5, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__GPIO2_IO24 = IOMUX_PAD(0x0510, 0x0140, 5, 0x0000, 0, 0), MX6_PAD_EIM_CS1__TPSMP_HDATA_8 = IOMUX_PAD(0x0510, 0x0140, 6, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__EPDC_SDDO_8 = IOMUX_PAD(0x0510, 0x0140, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D16__WEIM_WEIM_D_16 = IOMUX_PAD(0x0514, 0x0144, 0, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__EPDC_DATA08 = IOMUX_PAD(0x0510, 0x0140, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D16__EIM_DATA16 = IOMUX_PAD(0x0514, 0x0144, 0, 0x0000, 0, 0), MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0), - MX6_PAD_EIM_D16__IPU1_DI0_PIN5 = IOMUX_PAD(0x0514, 0x0144, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D16__IPU1_CSI1_D_18 = IOMUX_PAD(0x0514, 0x0144, 3, 0x08A8, 1, 0), + MX6_PAD_EIM_D16__IPU1_DI0_PIN05 = IOMUX_PAD(0x0514, 0x0144, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D16__IPU1_CSI1_DATA18 = IOMUX_PAD(0x0514, 0x0144, 3, 0x08A8, 1, 0), MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x0514, 0x0144, 4, 0x0864, 0, 0), - MX6_PAD_EIM_D16__GPIO_3_16 = IOMUX_PAD(0x0514, 0x0144, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D16__GPIO3_IO16 = IOMUX_PAD(0x0514, 0x0144, 5, 0x0000, 0, 0), MX6_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, 0), MX6_PAD_EIM_D16__TPSMP_HTRANS_0 = IOMUX_PAD(0x0514, 0x0144, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D16__EPDC_SDDO_10 = IOMUX_PAD(0x0514, 0x0144, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D17__WEIM_WEIM_D_17 = IOMUX_PAD(0x0518, 0x0148, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D16__EPDC_DATA10 = IOMUX_PAD(0x0514, 0x0144, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D17__EIM_DATA17 = IOMUX_PAD(0x0518, 0x0148, 0, 0x0000, 0, 0), MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0), - MX6_PAD_EIM_D17__IPU1_DI0_PIN6 = IOMUX_PAD(0x0518, 0x0148, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D17__IPU1_DI0_PIN06 = IOMUX_PAD(0x0518, 0x0148, 2, 0x0000, 0, 0), MX6_PAD_EIM_D17__IPU1_CSI1_PIXCLK = IOMUX_PAD(0x0518, 0x0148, 3, 0x08B8, 1, 0), - MX6_PAD_EIM_D17__DCIC1_DCIC_OUT = IOMUX_PAD(0x0518, 0x0148, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D17__GPIO_3_17 = IOMUX_PAD(0x0518, 0x0148, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D17__DCIC1_OUT = IOMUX_PAD(0x0518, 0x0148, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D17__GPIO3_IO17 = IOMUX_PAD(0x0518, 0x0148, 5, 0x0000, 0, 0), MX6_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, 0), MX6_PAD_EIM_D17__PL301_SIM_MX6DL_PER1_HBURST_1 = IOMUX_PAD(0x0518, 0x0148, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D17__EPDC_VCOM_0 = IOMUX_PAD(0x0518, 0x0148, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D18__WEIM_WEIM_D_18 = IOMUX_PAD(0x051C, 0x014C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D17__EPDC_VCOM0 = IOMUX_PAD(0x0518, 0x0148, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D18__EIM_DATA18 = IOMUX_PAD(0x051C, 0x014C, 0, 0x0000, 0, 0), MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0), - MX6_PAD_EIM_D18__IPU1_DI0_PIN7 = IOMUX_PAD(0x051C, 0x014C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D18__IPU1_CSI1_D_17 = IOMUX_PAD(0x051C, 0x014C, 3, 0x08A4, 1, 0), + MX6_PAD_EIM_D18__IPU1_DI0_PIN07 = IOMUX_PAD(0x051C, 0x014C, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D18__IPU1_CSI1_DATA17 = IOMUX_PAD(0x051C, 0x014C, 3, 0x08A4, 1, 0), MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x051C, 0x014C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D18__GPIO_3_18 = IOMUX_PAD(0x051C, 0x014C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D18__GPIO3_IO18 = IOMUX_PAD(0x051C, 0x014C, 5, 0x0000, 0, 0), MX6_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0), MX6_PAD_EIM_D18__PL301_SIM_MX6DL_PER1_HBURST_2 = IOMUX_PAD(0x051C, 0x014C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D18__EPDC_VCOM_1 = IOMUX_PAD(0x051C, 0x014C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D19__WEIM_WEIM_D_19 = IOMUX_PAD(0x0520, 0x0150, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D18__EPDC_VCOM1 = IOMUX_PAD(0x051C, 0x014C, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D19__EIM_DATA19 = IOMUX_PAD(0x0520, 0x0150, 0, 0x0000, 0, 0), MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x0520, 0x0150, 1, 0x07E8, 1, 0), - MX6_PAD_EIM_D19__IPU1_DI0_PIN8 = IOMUX_PAD(0x0520, 0x0150, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D19__IPU1_CSI1_D_16 = IOMUX_PAD(0x0520, 0x0150, 3, 0x08A0, 1, 0), - MX6_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x0520, 0x0150, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D19__UART1_RTS = IOMUX_PAD(0x0520, 0x0150, 4, 0x08F8, 0, 0), - MX6_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x0520, 0x0150, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D19__IPU1_DI0_PIN08 = IOMUX_PAD(0x0520, 0x0150, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D19__IPU1_CSI1_DATA16 = IOMUX_PAD(0x0520, 0x0150, 3, 0x08A0, 1, 0), + MX6_PAD_EIM_D19__UART1_CTS_B = IOMUX_PAD(0x0520, 0x0150, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D19__UART1_RTS_B = IOMUX_PAD(0x0520, 0x0150, 4, 0x08F8, 0, 0), + MX6_PAD_EIM_D19__GPIO3_IO19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D19__EPIT1_OUT = IOMUX_PAD(0x0520, 0x0150, 6, 0x0000, 0, 0), MX6_PAD_EIM_D19__PL301_SIM_MX6DL_PER1_HRESP = IOMUX_PAD(0x0520, 0x0150, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D19__EPDC_SDDO_12 = IOMUX_PAD(0x0520, 0x0150, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D20__WEIM_WEIM_D_20 = IOMUX_PAD(0x0524, 0x0154, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D19__EPDC_DATA12 = IOMUX_PAD(0x0520, 0x0150, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D20__EIM_DATA20 = IOMUX_PAD(0x0524, 0x0154, 0, 0x0000, 0, 0), MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x0524, 0x0154, 1, 0x0808, 0, 0), MX6_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x0524, 0x0154, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D20__IPU1_CSI1_D_15 = IOMUX_PAD(0x0524, 0x0154, 3, 0x089C, 1, 0), - MX6_PAD_EIM_D20__UART1_CTS = IOMUX_PAD(0x0524, 0x0154, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D20__UART1_RTS = IOMUX_PAD(0x0524, 0x0154, 4, 0x08F8, 1, 0), - MX6_PAD_EIM_D20__GPIO_3_20 = IOMUX_PAD(0x0524, 0x0154, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D20__EPIT2_EPITO = IOMUX_PAD(0x0524, 0x0154, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D20__IPU1_CSI1_DATA15 = IOMUX_PAD(0x0524, 0x0154, 3, 0x089C, 1, 0), + MX6_PAD_EIM_D20__UART1_CTS_B = IOMUX_PAD(0x0524, 0x0154, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D20__UART1_RTS_B = IOMUX_PAD(0x0524, 0x0154, 4, 0x08F8, 1, 0), + MX6_PAD_EIM_D20__GPIO3_IO20 = IOMUX_PAD(0x0524, 0x0154, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D20__EPIT2_OUT = IOMUX_PAD(0x0524, 0x0154, 6, 0x0000, 0, 0), MX6_PAD_EIM_D20__TPSMP_HTRANS_1 = IOMUX_PAD(0x0524, 0x0154, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D21__WEIM_WEIM_D_21 = IOMUX_PAD(0x0528, 0x0158, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D21__EIM_DATA21 = IOMUX_PAD(0x0528, 0x0158, 0, 0x0000, 0, 0), MX6_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x0528, 0x0158, 1, 0x0000, 0, 0), MX6_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x0528, 0x0158, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D21__IPU1_CSI1_D_11 = IOMUX_PAD(0x0528, 0x0158, 3, 0x088C, 0, 0), - MX6_PAD_EIM_D21__USBOH3_USBOTG_OC = IOMUX_PAD(0x0528, 0x0158, 4, 0x0920, 0, 0), - MX6_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D21__IPU1_CSI1_DATA11 = IOMUX_PAD(0x0528, 0x0158, 3, 0x088C, 0, 0), + MX6_PAD_EIM_D21__USB_OTG_OC = IOMUX_PAD(0x0528, 0x0158, 4, 0x0920, 0, 0), + MX6_PAD_EIM_D21__GPIO3_IO21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0), MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0), - MX6_PAD_EIM_D21__SPDIF_IN1 = IOMUX_PAD(0x0528, 0x0158, 7, 0x08F0, 0, 0), - MX6_PAD_EIM_D22__WEIM_WEIM_D_22 = IOMUX_PAD(0x052C, 0x015C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D21__SPDIF_IN = IOMUX_PAD(0x0528, 0x0158, 7, 0x08F0, 0, 0), + MX6_PAD_EIM_D22__EIM_DATA22 = IOMUX_PAD(0x052C, 0x015C, 0, 0x0000, 0, 0), MX6_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x052C, 0x015C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU1_DI0_PIN1 = IOMUX_PAD(0x052C, 0x015C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU1_CSI1_D_10 = IOMUX_PAD(0x052C, 0x015C, 3, 0x0888, 0, 0), - MX6_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x052C, 0x015C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D22__GPIO_3_22 = IOMUX_PAD(0x052C, 0x015C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D22__SPDIF_OUT1 = IOMUX_PAD(0x052C, 0x015C, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D22__IPU1_DI0_PIN01 = IOMUX_PAD(0x052C, 0x015C, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D22__IPU1_CSI1_DATA10 = IOMUX_PAD(0x052C, 0x015C, 3, 0x0888, 0, 0), + MX6_PAD_EIM_D22__USB_OTG_PWR = IOMUX_PAD(0x052C, 0x015C, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D22__GPIO3_IO22 = IOMUX_PAD(0x052C, 0x015C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D22__SPDIF_OUT = IOMUX_PAD(0x052C, 0x015C, 6, 0x0000, 0, 0), MX6_PAD_EIM_D22__PL301_SIM_MX6DL_PER1_HWRITE = IOMUX_PAD(0x052C, 0x015C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D22__EPDC_SDCE_6 = IOMUX_PAD(0x052C, 0x015C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D23__WEIM_WEIM_D_23 = IOMUX_PAD(0x0530, 0x0160, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D22__EPDC_SDCE6 = IOMUX_PAD(0x052C, 0x015C, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D23__EIM_DATA23 = IOMUX_PAD(0x0530, 0x0160, 0, 0x0000, 0, 0), MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x0530, 0x0160, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x0530, 0x0160, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D23__UART3_RTS = IOMUX_PAD(0x0530, 0x0160, 2, 0x0908, 0, 0), - MX6_PAD_EIM_D23__UART1_DCD = IOMUX_PAD(0x0530, 0x0160, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D23__UART3_CTS_B = IOMUX_PAD(0x0530, 0x0160, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D23__UART3_RTS_B = IOMUX_PAD(0x0530, 0x0160, 2, 0x0908, 0, 0), + MX6_PAD_EIM_D23__UART1_DCD_B = IOMUX_PAD(0x0530, 0x0160, 3, 0x0000, 0, 0), MX6_PAD_EIM_D23__IPU1_CSI1_DATA_EN = IOMUX_PAD(0x0530, 0x0160, 4, 0x08B0, 0, 0), - MX6_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI1_PIN2 = IOMUX_PAD(0x0530, 0x0160, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D23__GPIO3_IO23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D23__IPU1_DI1_PIN02 = IOMUX_PAD(0x0530, 0x0160, 6, 0x0000, 0, 0), MX6_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x0530, 0x0160, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D23__EPDC_SDDO_11 = IOMUX_PAD(0x0530, 0x0160, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D24__WEIM_WEIM_D_24 = IOMUX_PAD(0x0534, 0x0164, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D23__EPDC_DATA11 = IOMUX_PAD(0x0530, 0x0160, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D24__EIM_DATA24 = IOMUX_PAD(0x0534, 0x0164, 0, 0x0000, 0, 0), MX6_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x0534, 0x0164, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_TXD = IOMUX_PAD(0x0534, 0x0164, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_RXD = IOMUX_PAD(0x0534, 0x0164, 2, 0x090C, 0, 0), + MX6_PAD_EIM_D24__UART3_TX_DATA = IOMUX_PAD(0x0534, 0x0164, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D24__UART3_RX_DATA = IOMUX_PAD(0x0534, 0x0164, 2, 0x090C, 0, 0), MX6_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x0534, 0x0164, 3, 0x07EC, 0, 0), MX6_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x0534, 0x0164, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D24__GPIO_3_24 = IOMUX_PAD(0x0534, 0x0164, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D24__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0534, 0x0164, 6, 0x07BC, 1, 0), - MX6_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x0534, 0x0164, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D24__EPDC_SDCE_7 = IOMUX_PAD(0x0534, 0x0164, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D25__WEIM_WEIM_D_25 = IOMUX_PAD(0x0538, 0x0168, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D24__GPIO3_IO24 = IOMUX_PAD(0x0534, 0x0164, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D24__AUD5_RXFS = IOMUX_PAD(0x0534, 0x0164, 6, 0x07BC, 1, 0), + MX6_PAD_EIM_D24__UART1_DTR_B = IOMUX_PAD(0x0534, 0x0164, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D24__EPDC_SDCE7 = IOMUX_PAD(0x0534, 0x0164, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D25__EIM_DATA25 = IOMUX_PAD(0x0538, 0x0168, 0, 0x0000, 0, 0), MX6_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x0538, 0x0168, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D25__UART3_TXD = IOMUX_PAD(0x0538, 0x0168, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x0538, 0x0168, 2, 0x090C, 1, 0), + MX6_PAD_EIM_D25__UART3_TX_DATA = IOMUX_PAD(0x0538, 0x0168, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D25__UART3_RX_DATA = IOMUX_PAD(0x0538, 0x0168, 2, 0x090C, 1, 0), MX6_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x0538, 0x0168, 3, 0x07F0, 0, 0), MX6_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x0538, 0x0168, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D25__GPIO_3_25 = IOMUX_PAD(0x0538, 0x0168, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D25__AUDMUX_AUD5_RXC = IOMUX_PAD(0x0538, 0x0168, 6, 0x07B8, 1, 0), - MX6_PAD_EIM_D25__UART1_DSR = IOMUX_PAD(0x0538, 0x0168, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D25__EPDC_SDCE_8 = IOMUX_PAD(0x0538, 0x0168, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D26__WEIM_WEIM_D_26 = IOMUX_PAD(0x053C, 0x016C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D25__GPIO3_IO25 = IOMUX_PAD(0x0538, 0x0168, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D25__AUD5_RXC = IOMUX_PAD(0x0538, 0x0168, 6, 0x07B8, 1, 0), + MX6_PAD_EIM_D25__UART1_DSR_B = IOMUX_PAD(0x0538, 0x0168, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D25__EPDC_SDCE8 = IOMUX_PAD(0x0538, 0x0168, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D26__EIM_DATA26 = IOMUX_PAD(0x053C, 0x016C, 0, 0x0000, 0, 0), MX6_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x053C, 0x016C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_CSI0_D_1 = IOMUX_PAD(0x053C, 0x016C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_CSI1_D_14 = IOMUX_PAD(0x053C, 0x016C, 3, 0x0898, 1, 0), - MX6_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D26__UART2_RXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0904, 0, 0), - MX6_PAD_EIM_D26__GPIO_3_26 = IOMUX_PAD(0x053C, 0x016C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_SISG_2 = IOMUX_PAD(0x053C, 0x016C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_DISP1_DAT_22 = IOMUX_PAD(0x053C, 0x016C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_CSI0_DATA01 = IOMUX_PAD(0x053C, 0x016C, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_CSI1_DATA14 = IOMUX_PAD(0x053C, 0x016C, 3, 0x0898, 1, 0), + MX6_PAD_EIM_D26__UART2_TX_DATA = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D26__UART2_RX_DATA = IOMUX_PAD(0x053C, 0x016C, 4, 0x0904, 0, 0), + MX6_PAD_EIM_D26__GPIO3_IO26 = IOMUX_PAD(0x053C, 0x016C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_SISG2 = IOMUX_PAD(0x053C, 0x016C, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 = IOMUX_PAD(0x053C, 0x016C, 7, 0x0000, 0, 0), MX6_PAD_EIM_D26__EPDC_SDOED = IOMUX_PAD(0x053C, 0x016C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D27__WEIM_WEIM_D_27 = IOMUX_PAD(0x0540, 0x0170, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D27__EIM_DATA27 = IOMUX_PAD(0x0540, 0x0170, 0, 0x0000, 0, 0), MX6_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x0540, 0x0170, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_CSI0_D_0 = IOMUX_PAD(0x0540, 0x0170, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_CSI1_D_13 = IOMUX_PAD(0x0540, 0x0170, 3, 0x0894, 1, 0), - MX6_PAD_EIM_D27__UART2_TXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0), - MX6_PAD_EIM_D27__GPIO_3_27 = IOMUX_PAD(0x0540, 0x0170, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_SISG_3 = IOMUX_PAD(0x0540, 0x0170, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_DISP1_DAT_23 = IOMUX_PAD(0x0540, 0x0170, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_CSI0_DATA00 = IOMUX_PAD(0x0540, 0x0170, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_CSI1_DATA13 = IOMUX_PAD(0x0540, 0x0170, 3, 0x0894, 1, 0), + MX6_PAD_EIM_D27__UART2_TX_DATA = IOMUX_PAD(0x0540, 0x0170, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D27__UART2_RX_DATA = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0), + MX6_PAD_EIM_D27__GPIO3_IO27 = IOMUX_PAD(0x0540, 0x0170, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_SISG3 = IOMUX_PAD(0x0540, 0x0170, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 = IOMUX_PAD(0x0540, 0x0170, 7, 0x0000, 0, 0), MX6_PAD_EIM_D27__EPDC_SDOE = IOMUX_PAD(0x0540, 0x0170, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D28__WEIM_WEIM_D_28 = IOMUX_PAD(0x0544, 0x0174, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D28__EIM_DATA28 = IOMUX_PAD(0x0544, 0x0174, 0, 0x0000, 0, 0), MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0), MX6_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x0544, 0x0174, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU1_CSI1_D_12 = IOMUX_PAD(0x0544, 0x0174, 3, 0x0890, 1, 0), - MX6_PAD_EIM_D28__UART2_CTS = IOMUX_PAD(0x0544, 0x0174, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D28__UART2_RTS = IOMUX_PAD(0x0544, 0x0174, 4, 0x0900, 0, 0), - MX6_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D28__IPU1_CSI1_DATA12 = IOMUX_PAD(0x0544, 0x0174, 3, 0x0890, 1, 0), + MX6_PAD_EIM_D28__UART2_DTE_RTS_B = IOMUX_PAD(0x0544, 0x0174, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D28__UART2_DTE_CTS_B = IOMUX_PAD(0x0544, 0x0174, 4, 0x0900, 0, 0), + MX6_PAD_EIM_D28__GPIO3_IO28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0), MX6_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x0544, 0x0174, 6, 0x0000, 0, 0), MX6_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x0544, 0x0174, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D28__EPDC_PWRCTRL_3 = IOMUX_PAD(0x0544, 0x0174, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D29__WEIM_WEIM_D_29 = IOMUX_PAD(0x0548, 0x0178, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D28__EPDC_PWR_CTRL3 = IOMUX_PAD(0x0544, 0x0174, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D29__EIM_DATA29 = IOMUX_PAD(0x0548, 0x0178, 0, 0x0000, 0, 0), MX6_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x0548, 0x0178, 1, 0x0000, 0, 0), MX6_PAD_EIM_D29__ECSPI4_SS0 = IOMUX_PAD(0x0548, 0x0178, 2, 0x0808, 1, 0), - MX6_PAD_EIM_D29__UART2_CTS = IOMUX_PAD(0x0548, 0x0178, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D29__UART2_RTS = IOMUX_PAD(0x0548, 0x0178, 4, 0x0900, 1, 0), - MX6_PAD_EIM_D29__GPIO_3_29 = IOMUX_PAD(0x0548, 0x0178, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D29__UART2_CTS_B = IOMUX_PAD(0x0548, 0x0178, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D29__UART2_RTS_B = IOMUX_PAD(0x0548, 0x0178, 4, 0x0900, 1, 0), + MX6_PAD_EIM_D29__GPIO3_IO29 = IOMUX_PAD(0x0548, 0x0178, 5, 0x0000, 0, 0), MX6_PAD_EIM_D29__IPU1_CSI1_VSYNC = IOMUX_PAD(0x0548, 0x0178, 6, 0x08BC, 0, 0), MX6_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x0548, 0x0178, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D29__EPDC_PWRWAKE = IOMUX_PAD(0x0548, 0x0178, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D30__WEIM_WEIM_D_30 = IOMUX_PAD(0x054C, 0x017C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_DISP1_DAT_21 = IOMUX_PAD(0x054C, 0x017C, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D29__EPDC_PWR_WAKE = IOMUX_PAD(0x0548, 0x0178, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D30__EIM_DATA30 = IOMUX_PAD(0x054C, 0x017C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 = IOMUX_PAD(0x054C, 0x017C, 1, 0x0000, 0, 0), MX6_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x054C, 0x017C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_CSI0_D_3 = IOMUX_PAD(0x054C, 0x017C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x054C, 0x017C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D30__UART3_RTS = IOMUX_PAD(0x054C, 0x017C, 4, 0x0908, 1, 0), - MX6_PAD_EIM_D30__GPIO_3_30 = IOMUX_PAD(0x054C, 0x017C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x054C, 0x017C, 6, 0x0924, 0, 0), + MX6_PAD_EIM_D30__IPU1_CSI0_DATA03 = IOMUX_PAD(0x054C, 0x017C, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D30__UART3_CTS_B = IOMUX_PAD(0x054C, 0x017C, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D30__UART3_RTS_B = IOMUX_PAD(0x054C, 0x017C, 4, 0x0908, 1, 0), + MX6_PAD_EIM_D30__GPIO3_IO30 = IOMUX_PAD(0x054C, 0x017C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D30__USB_H1_OC = IOMUX_PAD(0x054C, 0x017C, 6, 0x0924, 0, 0), MX6_PAD_EIM_D30__PL301_SIM_MX6DL_PER1_HPROT_0 = IOMUX_PAD(0x054C, 0x017C, 7, 0x0000, 0, 0), MX6_PAD_EIM_D30__EPDC_SDOEZ = IOMUX_PAD(0x054C, 0x017C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D31__WEIM_WEIM_D_31 = IOMUX_PAD(0x0550, 0x0180, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20 = IOMUX_PAD(0x0550, 0x0180, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D31__EIM_DATA31 = IOMUX_PAD(0x0550, 0x0180, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 = IOMUX_PAD(0x0550, 0x0180, 1, 0x0000, 0, 0), MX6_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x0550, 0x0180, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_CSI0_D_2 = IOMUX_PAD(0x0550, 0x0180, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_CTS = IOMUX_PAD(0x0550, 0x0180, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x0550, 0x0180, 4, 0x0908, 2, 0), - MX6_PAD_EIM_D31__GPIO_3_31 = IOMUX_PAD(0x0550, 0x0180, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x0550, 0x0180, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D31__IPU1_CSI0_DATA02 = IOMUX_PAD(0x0550, 0x0180, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D31__UART3_CTS_B = IOMUX_PAD(0x0550, 0x0180, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D31__UART3_RTS_B = IOMUX_PAD(0x0550, 0x0180, 4, 0x0908, 2, 0), + MX6_PAD_EIM_D31__GPIO3_IO31 = IOMUX_PAD(0x0550, 0x0180, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D31__USB_H1_PWR = IOMUX_PAD(0x0550, 0x0180, 6, 0x0000, 0, 0), MX6_PAD_EIM_D31__PL301_SIM_MX6DL_PER1_HPROT_1 = IOMUX_PAD(0x0550, 0x0180, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D31__EPDC_SDCLK = IOMUX_PAD(0x0550, 0x0180, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D31__WEIM_ACLK_FREERUN = IOMUX_PAD(0x0550, 0x0180, 9, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 = IOMUX_PAD(0x0554, 0x0184, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU1_DISP1_DAT_9 = IOMUX_PAD(0x0554, 0x0184, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU1_CSI1_D_9 = IOMUX_PAD(0x0554, 0x0184, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D31__EPDC_SDCLK_P = IOMUX_PAD(0x0550, 0x0180, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D31__EIM_ACLK_FREERUN = IOMUX_PAD(0x0550, 0x0180, 9, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__EIM_AD00 = IOMUX_PAD(0x0554, 0x0184, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 = IOMUX_PAD(0x0554, 0x0184, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__IPU1_CSI1_DATA09 = IOMUX_PAD(0x0554, 0x0184, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 = IOMUX_PAD(0x0554, 0x0184, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__GPIO_3_0 = IOMUX_PAD(0x0554, 0x0184, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__GPIO3_IO00 = IOMUX_PAD(0x0554, 0x0184, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA0__TPSMP_HDATA_14 = IOMUX_PAD(0x0554, 0x0184, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__SRC_BT_CFG_0 = IOMUX_PAD(0x0554, 0x0184, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__EPDC_SDCLKN = IOMUX_PAD(0x0554, 0x0184, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 = IOMUX_PAD(0x0558, 0x0188, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU1_DISP1_DAT_8 = IOMUX_PAD(0x0558, 0x0188, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU1_CSI1_D_8 = IOMUX_PAD(0x0558, 0x0188, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__SRC_BOOT_CFG00 = IOMUX_PAD(0x0554, 0x0184, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__EPDC_SDCLK_N = IOMUX_PAD(0x0554, 0x0184, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__EIM_AD01 = IOMUX_PAD(0x0558, 0x0188, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 = IOMUX_PAD(0x0558, 0x0188, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__IPU1_CSI1_DATA08 = IOMUX_PAD(0x0558, 0x0188, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 = IOMUX_PAD(0x0558, 0x0188, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE = IOMUX_PAD(0x0558, 0x0188, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__GPIO_3_1 = IOMUX_PAD(0x0558, 0x0188, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__GPIO3_IO01 = IOMUX_PAD(0x0558, 0x0188, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA1__TPSMP_HDATA_15 = IOMUX_PAD(0x0558, 0x0188, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__SRC_BT_CFG_1 = IOMUX_PAD(0x0558, 0x0188, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__SRC_BOOT_CFG01 = IOMUX_PAD(0x0558, 0x0188, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA1__EPDC_SDLE = IOMUX_PAD(0x0558, 0x0188, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 = IOMUX_PAD(0x055C, 0x018C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__EIM_AD10 = IOMUX_PAD(0x055C, 0x018C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x055C, 0x018C, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA10__IPU1_CSI1_DATA_EN = IOMUX_PAD(0x055C, 0x018C, 2, 0x08B0, 1, 0), MX6_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 = IOMUX_PAD(0x055C, 0x018C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__GPIO_3_10 = IOMUX_PAD(0x055C, 0x018C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__GPIO3_IO10 = IOMUX_PAD(0x055C, 0x018C, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA10__TPSMP_HDATA_24 = IOMUX_PAD(0x055C, 0x018C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__SRC_BT_CFG_10 = IOMUX_PAD(0x055C, 0x018C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__EPDC_SDDO_1 = IOMUX_PAD(0x055C, 0x018C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 = IOMUX_PAD(0x0560, 0x0190, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__IPU1_DI1_PIN2 = IOMUX_PAD(0x0560, 0x0190, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x055C, 0x018C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__EPDC_DATA01 = IOMUX_PAD(0x055C, 0x018C, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__EIM_AD11 = IOMUX_PAD(0x0560, 0x0190, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 = IOMUX_PAD(0x0560, 0x0190, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA11__IPU1_CSI1_HSYNC = IOMUX_PAD(0x0560, 0x0190, 2, 0x08B4, 0, 0), MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 = IOMUX_PAD(0x0560, 0x0190, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 = IOMUX_PAD(0x0560, 0x0190, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__GPIO_3_11 = IOMUX_PAD(0x0560, 0x0190, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__GPIO3_IO11 = IOMUX_PAD(0x0560, 0x0190, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA11__TPSMP_HDATA_25 = IOMUX_PAD(0x0560, 0x0190, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__SRC_BT_CFG_11 = IOMUX_PAD(0x0560, 0x0190, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__EPDC_SDDO_3 = IOMUX_PAD(0x0560, 0x0190, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 = IOMUX_PAD(0x0564, 0x0194, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__IPU1_DI1_PIN3 = IOMUX_PAD(0x0564, 0x0194, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0560, 0x0190, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__EPDC_DATA03 = IOMUX_PAD(0x0560, 0x0190, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__EIM_AD12 = IOMUX_PAD(0x0564, 0x0194, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 = IOMUX_PAD(0x0564, 0x0194, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA12__IPU1_CSI1_VSYNC = IOMUX_PAD(0x0564, 0x0194, 2, 0x08BC, 1, 0), MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 = IOMUX_PAD(0x0564, 0x0194, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 = IOMUX_PAD(0x0564, 0x0194, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__GPIO_3_12 = IOMUX_PAD(0x0564, 0x0194, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__GPIO3_IO12 = IOMUX_PAD(0x0564, 0x0194, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA12__TPSMP_HDATA_26 = IOMUX_PAD(0x0564, 0x0194, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__SRC_BT_CFG_12 = IOMUX_PAD(0x0564, 0x0194, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__EPDC_SDDO_2 = IOMUX_PAD(0x0564, 0x0194, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 = IOMUX_PAD(0x0568, 0x0198, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0564, 0x0194, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__EPDC_DATA02 = IOMUX_PAD(0x0564, 0x0194, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__EIM_AD13 = IOMUX_PAD(0x0568, 0x0198, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x0568, 0x0198, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x0568, 0x0198, 2, 0x07D0, 0, 0), MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 = IOMUX_PAD(0x0568, 0x0198, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 = IOMUX_PAD(0x0568, 0x0198, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__GPIO_3_13 = IOMUX_PAD(0x0568, 0x0198, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__GPIO3_IO13 = IOMUX_PAD(0x0568, 0x0198, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA13__TPSMP_HDATA_27 = IOMUX_PAD(0x0568, 0x0198, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__SRC_BT_CFG_13 = IOMUX_PAD(0x0568, 0x0198, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__EPDC_SDDO_13 = IOMUX_PAD(0x0568, 0x0198, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 = IOMUX_PAD(0x056C, 0x019C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x0568, 0x0198, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__EPDC_DATA13 = IOMUX_PAD(0x0568, 0x0198, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__EIM_AD14 = IOMUX_PAD(0x056C, 0x019C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x056C, 0x019C, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x056C, 0x019C, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 = IOMUX_PAD(0x056C, 0x019C, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 = IOMUX_PAD(0x056C, 0x019C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__GPIO_3_14 = IOMUX_PAD(0x056C, 0x019C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__GPIO3_IO14 = IOMUX_PAD(0x056C, 0x019C, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA14__TPSMP_HDATA_28 = IOMUX_PAD(0x056C, 0x019C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__SRC_BT_CFG_14 = IOMUX_PAD(0x056C, 0x019C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__EPDC_SDDO_14 = IOMUX_PAD(0x056C, 0x019C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 = IOMUX_PAD(0x0570, 0x01A0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN1 = IOMUX_PAD(0x0570, 0x01A0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN4 = IOMUX_PAD(0x0570, 0x01A0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x056C, 0x019C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__EPDC_DATA14 = IOMUX_PAD(0x056C, 0x019C, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__EIM_AD15 = IOMUX_PAD(0x0570, 0x01A0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__IPU1_DI1_PIN01 = IOMUX_PAD(0x0570, 0x01A0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__IPU1_DI1_PIN04 = IOMUX_PAD(0x0570, 0x01A0, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 = IOMUX_PAD(0x0570, 0x01A0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__GPIO_3_15 = IOMUX_PAD(0x0570, 0x01A0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__GPIO3_IO15 = IOMUX_PAD(0x0570, 0x01A0, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA15__TPSMP_HDATA_29 = IOMUX_PAD(0x0570, 0x01A0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__SRC_BT_CFG_15 = IOMUX_PAD(0x0570, 0x01A0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__EPDC_SDDO_9 = IOMUX_PAD(0x0570, 0x01A0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 = IOMUX_PAD(0x0574, 0x01A4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU1_DISP1_DAT_7 = IOMUX_PAD(0x0574, 0x01A4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU1_CSI1_D_7 = IOMUX_PAD(0x0574, 0x01A4, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0570, 0x01A0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__EPDC_DATA09 = IOMUX_PAD(0x0570, 0x01A0, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__EIM_AD02 = IOMUX_PAD(0x0574, 0x01A4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 = IOMUX_PAD(0x0574, 0x01A4, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__IPU1_CSI1_DATA07 = IOMUX_PAD(0x0574, 0x01A4, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 = IOMUX_PAD(0x0574, 0x01A4, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE = IOMUX_PAD(0x0574, 0x01A4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__GPIO_3_2 = IOMUX_PAD(0x0574, 0x01A4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__GPIO3_IO02 = IOMUX_PAD(0x0574, 0x01A4, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA2__TPSMP_HDATA_16 = IOMUX_PAD(0x0574, 0x01A4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__SRC_BT_CFG_2 = IOMUX_PAD(0x0574, 0x01A4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__EPDC_BDR_0 = IOMUX_PAD(0x0574, 0x01A4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 = IOMUX_PAD(0x0578, 0x01A8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU1_DISP1_DAT_6 = IOMUX_PAD(0x0578, 0x01A8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU1_CSI1_D_6 = IOMUX_PAD(0x0578, 0x01A8, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__SRC_BOOT_CFG02 = IOMUX_PAD(0x0574, 0x01A4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__EPDC_BDR0 = IOMUX_PAD(0x0574, 0x01A4, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__EIM_AD03 = IOMUX_PAD(0x0578, 0x01A8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 = IOMUX_PAD(0x0578, 0x01A8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__IPU1_CSI1_DATA06 = IOMUX_PAD(0x0578, 0x01A8, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 = IOMUX_PAD(0x0578, 0x01A8, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ = IOMUX_PAD(0x0578, 0x01A8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__GPIO_3_3 = IOMUX_PAD(0x0578, 0x01A8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__GPIO3_IO03 = IOMUX_PAD(0x0578, 0x01A8, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA3__TPSMP_HDATA_17 = IOMUX_PAD(0x0578, 0x01A8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__SRC_BT_CFG_3 = IOMUX_PAD(0x0578, 0x01A8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__EPDC_BDR_1 = IOMUX_PAD(0x0578, 0x01A8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 = IOMUX_PAD(0x057C, 0x01AC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU1_DISP1_DAT_5 = IOMUX_PAD(0x057C, 0x01AC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU1_CSI1_D_5 = IOMUX_PAD(0x057C, 0x01AC, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__SRC_BOOT_CFG03 = IOMUX_PAD(0x0578, 0x01A8, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__EPDC_BDR1 = IOMUX_PAD(0x0578, 0x01A8, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__EIM_AD04 = IOMUX_PAD(0x057C, 0x01AC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 = IOMUX_PAD(0x057C, 0x01AC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__IPU1_CSI1_DATA05 = IOMUX_PAD(0x057C, 0x01AC, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 = IOMUX_PAD(0x057C, 0x01AC, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN = IOMUX_PAD(0x057C, 0x01AC, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__GPIO_3_4 = IOMUX_PAD(0x057C, 0x01AC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__GPIO3_IO04 = IOMUX_PAD(0x057C, 0x01AC, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA4__TPSMP_HDATA_18 = IOMUX_PAD(0x057C, 0x01AC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__SRC_BT_CFG_4 = IOMUX_PAD(0x057C, 0x01AC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__EPDC_SDCE_0 = IOMUX_PAD(0x057C, 0x01AC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 = IOMUX_PAD(0x0580, 0x01B0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU1_DISP1_DAT_4 = IOMUX_PAD(0x0580, 0x01B0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU1_CSI1_D_4 = IOMUX_PAD(0x0580, 0x01B0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__SRC_BOOT_CFG04 = IOMUX_PAD(0x057C, 0x01AC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__EPDC_SDCE0 = IOMUX_PAD(0x057C, 0x01AC, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__EIM_AD05 = IOMUX_PAD(0x0580, 0x01B0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 = IOMUX_PAD(0x0580, 0x01B0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__IPU1_CSI1_DATA04 = IOMUX_PAD(0x0580, 0x01B0, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 = IOMUX_PAD(0x0580, 0x01B0, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP = IOMUX_PAD(0x0580, 0x01B0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__GPIO_3_5 = IOMUX_PAD(0x0580, 0x01B0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__GPIO3_IO05 = IOMUX_PAD(0x0580, 0x01B0, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA5__TPSMP_HDATA_19 = IOMUX_PAD(0x0580, 0x01B0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__SRC_BT_CFG_5 = IOMUX_PAD(0x0580, 0x01B0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__EPDC_SDCE_1 = IOMUX_PAD(0x0580, 0x01B0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 = IOMUX_PAD(0x0584, 0x01B4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU1_DISP1_DAT_3 = IOMUX_PAD(0x0584, 0x01B4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU1_CSI1_D_3 = IOMUX_PAD(0x0584, 0x01B4, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__SRC_BOOT_CFG05 = IOMUX_PAD(0x0580, 0x01B0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__EPDC_SDCE1 = IOMUX_PAD(0x0580, 0x01B0, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__EIM_AD06 = IOMUX_PAD(0x0584, 0x01B4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 = IOMUX_PAD(0x0584, 0x01B4, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__IPU1_CSI1_DATA03 = IOMUX_PAD(0x0584, 0x01B4, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 = IOMUX_PAD(0x0584, 0x01B4, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN = IOMUX_PAD(0x0584, 0x01B4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__GPIO_3_6 = IOMUX_PAD(0x0584, 0x01B4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__GPIO3_IO06 = IOMUX_PAD(0x0584, 0x01B4, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA6__TPSMP_HDATA_20 = IOMUX_PAD(0x0584, 0x01B4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__SRC_BT_CFG_6 = IOMUX_PAD(0x0584, 0x01B4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__EPDC_SDCE_2 = IOMUX_PAD(0x0584, 0x01B4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 = IOMUX_PAD(0x0588, 0x01B8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU1_DISP1_DAT_2 = IOMUX_PAD(0x0588, 0x01B8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU1_CSI1_D_2 = IOMUX_PAD(0x0588, 0x01B8, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__SRC_BOOT_CFG06 = IOMUX_PAD(0x0584, 0x01B4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__EPDC_SDCE2 = IOMUX_PAD(0x0584, 0x01B4, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__EIM_AD07 = IOMUX_PAD(0x0588, 0x01B8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 = IOMUX_PAD(0x0588, 0x01B8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__IPU1_CSI1_DATA02 = IOMUX_PAD(0x0588, 0x01B8, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 = IOMUX_PAD(0x0588, 0x01B8, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__GPIO_3_7 = IOMUX_PAD(0x0588, 0x01B8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__GPIO3_IO07 = IOMUX_PAD(0x0588, 0x01B8, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA7__TPSMP_HDATA_21 = IOMUX_PAD(0x0588, 0x01B8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__SRC_BT_CFG_7 = IOMUX_PAD(0x0588, 0x01B8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__EPDC_SDCE_3 = IOMUX_PAD(0x0588, 0x01B8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 = IOMUX_PAD(0x058C, 0x01BC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU1_DISP1_DAT_1 = IOMUX_PAD(0x058C, 0x01BC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU1_CSI1_D_1 = IOMUX_PAD(0x058C, 0x01BC, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__SRC_BOOT_CFG07 = IOMUX_PAD(0x0588, 0x01B8, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__EPDC_SDCE3 = IOMUX_PAD(0x0588, 0x01B8, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__EIM_AD08 = IOMUX_PAD(0x058C, 0x01BC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 = IOMUX_PAD(0x058C, 0x01BC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__IPU1_CSI1_DATA01 = IOMUX_PAD(0x058C, 0x01BC, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 = IOMUX_PAD(0x058C, 0x01BC, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__GPIO_3_8 = IOMUX_PAD(0x058C, 0x01BC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__GPIO3_IO08 = IOMUX_PAD(0x058C, 0x01BC, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA8__TPSMP_HDATA_22 = IOMUX_PAD(0x058C, 0x01BC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__SRC_BT_CFG_8 = IOMUX_PAD(0x058C, 0x01BC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__EPDC_SDCE_4 = IOMUX_PAD(0x058C, 0x01BC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 = IOMUX_PAD(0x0590, 0x01C0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU1_DISP1_DAT_0 = IOMUX_PAD(0x0590, 0x01C0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU1_CSI1_D_0 = IOMUX_PAD(0x0590, 0x01C0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__SRC_BOOT_CFG08 = IOMUX_PAD(0x058C, 0x01BC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__EPDC_SDCE4 = IOMUX_PAD(0x058C, 0x01BC, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__EIM_AD09 = IOMUX_PAD(0x0590, 0x01C0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 = IOMUX_PAD(0x0590, 0x01C0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__IPU1_CSI1_DATA00 = IOMUX_PAD(0x0590, 0x01C0, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 = IOMUX_PAD(0x0590, 0x01C0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__GPIO_3_9 = IOMUX_PAD(0x0590, 0x01C0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__GPIO3_IO09 = IOMUX_PAD(0x0590, 0x01C0, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA9__TPSMP_HDATA_23 = IOMUX_PAD(0x0590, 0x01C0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__SRC_BT_CFG_9 = IOMUX_PAD(0x0590, 0x01C0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__EPDC_SDCE_5 = IOMUX_PAD(0x0590, 0x01C0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__WEIM_WEIM_EB_0 = IOMUX_PAD(0x0594, 0x01C4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU1_DISP1_DAT_11 = IOMUX_PAD(0x0594, 0x01C4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU1_CSI1_D_11 = IOMUX_PAD(0x0594, 0x01C4, 2, 0x088C, 1, 0), + MX6_PAD_EIM_DA9__SRC_BOOT_CFG09 = IOMUX_PAD(0x0590, 0x01C0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__EPDC_SDCE5 = IOMUX_PAD(0x0590, 0x01C0, 8, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__EIM_EB0_B = IOMUX_PAD(0x0594, 0x01C4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 = IOMUX_PAD(0x0594, 0x01C4, 1, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__IPU1_CSI1_DATA11 = IOMUX_PAD(0x0594, 0x01C4, 2, 0x088C, 1, 0), MX6_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 = IOMUX_PAD(0x0594, 0x01C4, 3, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__CCM_PMIC_RDY = IOMUX_PAD(0x0594, 0x01C4, 4, 0x07D4, 0, 0), - MX6_PAD_EIM_EB0__GPIO_2_28 = IOMUX_PAD(0x0594, 0x01C4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__CCM_PMIC_READY = IOMUX_PAD(0x0594, 0x01C4, 4, 0x07D4, 0, 0), + MX6_PAD_EIM_EB0__GPIO2_IO28 = IOMUX_PAD(0x0594, 0x01C4, 5, 0x0000, 0, 0), MX6_PAD_EIM_EB0__TPSMP_HDATA_12 = IOMUX_PAD(0x0594, 0x01C4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__SRC_BT_CFG_27 = IOMUX_PAD(0x0594, 0x01C4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__EPDC_PWRCOM = IOMUX_PAD(0x0594, 0x01C4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__WEIM_WEIM_EB_1 = IOMUX_PAD(0x0598, 0x01C8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU1_DISP1_DAT_10 = IOMUX_PAD(0x0598, 0x01C8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU1_CSI1_D_10 = IOMUX_PAD(0x0598, 0x01C8, 2, 0x0888, 1, 0), + MX6_PAD_EIM_EB0__SRC_BOOT_CFG27 = IOMUX_PAD(0x0594, 0x01C4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__EPDC_PWR_COM = IOMUX_PAD(0x0594, 0x01C4, 8, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__EIM_EB1_B = IOMUX_PAD(0x0598, 0x01C8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 = IOMUX_PAD(0x0598, 0x01C8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__IPU1_CSI1_DATA10 = IOMUX_PAD(0x0598, 0x01C8, 2, 0x0888, 1, 0), MX6_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 = IOMUX_PAD(0x0598, 0x01C8, 3, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__GPIO_2_29 = IOMUX_PAD(0x0598, 0x01C8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__GPIO2_IO29 = IOMUX_PAD(0x0598, 0x01C8, 5, 0x0000, 0, 0), MX6_PAD_EIM_EB1__TPSMP_HDATA_13 = IOMUX_PAD(0x0598, 0x01C8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__SRC_BT_CFG_28 = IOMUX_PAD(0x0598, 0x01C8, 7, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__SRC_BOOT_CFG28 = IOMUX_PAD(0x0598, 0x01C8, 7, 0x0000, 0, 0), MX6_PAD_EIM_EB1__EPDC_SDSHR = IOMUX_PAD(0x0598, 0x01C8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__WEIM_WEIM_EB_2 = IOMUX_PAD(0x059C, 0x01CC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB2__EIM_EB2_B = IOMUX_PAD(0x059C, 0x01CC, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x059C, 0x01CC, 1, 0x07E4, 2, 0), MX6_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x059C, 0x01CC, 2, 0x07D0, 1, 0), - MX6_PAD_EIM_EB2__IPU1_CSI1_D_19 = IOMUX_PAD(0x059C, 0x01CC, 3, 0x08AC, 1, 0), + MX6_PAD_EIM_EB2__IPU1_CSI1_DATA19 = IOMUX_PAD(0x059C, 0x01CC, 3, 0x08AC, 1, 0), MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x059C, 0x01CC, 4, 0x0860, 0, 0), - MX6_PAD_EIM_EB2__GPIO_2_30 = IOMUX_PAD(0x059C, 0x01CC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB2__GPIO2_IO30 = IOMUX_PAD(0x059C, 0x01CC, 5, 0x0000, 0, 0), MX6_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, 0), - MX6_PAD_EIM_EB2__SRC_BT_CFG_30 = IOMUX_PAD(0x059C, 0x01CC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__EPDC_SDDO_5 = IOMUX_PAD(0x059C, 0x01CC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__WEIM_WEIM_EB_3 = IOMUX_PAD(0x05A0, 0x01D0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB2__SRC_BOOT_CFG30 = IOMUX_PAD(0x059C, 0x01CC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_EB2__EPDC_DATA05 = IOMUX_PAD(0x059C, 0x01CC, 8, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__EIM_EB3_B = IOMUX_PAD(0x05A0, 0x01D0, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB3__ECSPI4_RDY = IOMUX_PAD(0x05A0, 0x01D0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_CTS = IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_RTS = IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0908, 3, 0), - MX6_PAD_EIM_EB3__UART1_RI = IOMUX_PAD(0x05A0, 0x01D0, 3, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__UART3_CTS_B = IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__UART3_RTS_B = IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0908, 3, 0), + MX6_PAD_EIM_EB3__UART1_RI_B = IOMUX_PAD(0x05A0, 0x01D0, 3, 0x0000, 0, 0), MX6_PAD_EIM_EB3__IPU1_CSI1_HSYNC = IOMUX_PAD(0x05A0, 0x01D0, 4, 0x08B4, 1, 0), - MX6_PAD_EIM_EB3__GPIO_2_31 = IOMUX_PAD(0x05A0, 0x01D0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__IPU1_DI1_PIN3 = IOMUX_PAD(0x05A0, 0x01D0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__SRC_BT_CFG_31 = IOMUX_PAD(0x05A0, 0x01D0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__EPDC_SDCE_0 = IOMUX_PAD(0x05A0, 0x01D0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__WEIM_ACLK_FREERUN = IOMUX_PAD(0x05A0, 0x01D0, 9, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__WEIM_WEIM_LBA = IOMUX_PAD(0x05A4, 0x01D4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__GPIO2_IO31 = IOMUX_PAD(0x05A0, 0x01D0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__IPU1_DI1_PIN03 = IOMUX_PAD(0x05A0, 0x01D0, 6, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__SRC_BOOT_CFG31 = IOMUX_PAD(0x05A0, 0x01D0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__EPDC_SDCE0 = IOMUX_PAD(0x05A0, 0x01D0, 8, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__EIM_ACLK_FREERUN = IOMUX_PAD(0x05A0, 0x01D0, 9, 0x0000, 0, 0), + MX6_PAD_EIM_LBA__EIM_LBA_B = IOMUX_PAD(0x05A4, 0x01D4, 0, 0x0000, 0, 0), MX6_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x05A4, 0x01D4, 1, 0x0000, 0, 0), MX6_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x05A4, 0x01D4, 2, 0x0804, 1, 0), - MX6_PAD_EIM_LBA__GPIO_2_27 = IOMUX_PAD(0x05A4, 0x01D4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_LBA__GPIO2_IO27 = IOMUX_PAD(0x05A4, 0x01D4, 5, 0x0000, 0, 0), MX6_PAD_EIM_LBA__TPSMP_HDATA_11 = IOMUX_PAD(0x05A4, 0x01D4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__SRC_BT_CFG_26 = IOMUX_PAD(0x05A4, 0x01D4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__EPDC_SDDO_4 = IOMUX_PAD(0x05A4, 0x01D4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_OE__WEIM_WEIM_OE = IOMUX_PAD(0x05A8, 0x01D8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_OE__IPU1_DI1_PIN7 = IOMUX_PAD(0x05A8, 0x01D8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_LBA__SRC_BOOT_CFG26 = IOMUX_PAD(0x05A4, 0x01D4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_LBA__EPDC_DATA04 = IOMUX_PAD(0x05A4, 0x01D4, 8, 0x0000, 0, 0), + MX6_PAD_EIM_OE__EIM_OE_B = IOMUX_PAD(0x05A8, 0x01D8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_OE__IPU1_DI1_PIN07 = IOMUX_PAD(0x05A8, 0x01D8, 1, 0x0000, 0, 0), MX6_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x05A8, 0x01D8, 2, 0x07F8, 2, 0), MX6_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 = IOMUX_PAD(0x05A8, 0x01D8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_OE__GPIO_2_25 = IOMUX_PAD(0x05A8, 0x01D8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_OE__GPIO2_IO25 = IOMUX_PAD(0x05A8, 0x01D8, 5, 0x0000, 0, 0), MX6_PAD_EIM_OE__TPSMP_HDATA_9 = IOMUX_PAD(0x05A8, 0x01D8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_OE__EPDC_PWRIRQ = IOMUX_PAD(0x05A8, 0x01D8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_RW__WEIM_WEIM_RW = IOMUX_PAD(0x05AC, 0x01DC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_RW__IPU1_DI1_PIN8 = IOMUX_PAD(0x05AC, 0x01DC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_OE__EPDC_PWR_IRQ = IOMUX_PAD(0x05A8, 0x01D8, 8, 0x0000, 0, 0), + MX6_PAD_EIM_RW__EIM_RW = IOMUX_PAD(0x05AC, 0x01DC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_RW__IPU1_DI1_PIN08 = IOMUX_PAD(0x05AC, 0x01DC, 1, 0x0000, 0, 0), MX6_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x05AC, 0x01DC, 2, 0x0800, 2, 0), MX6_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 = IOMUX_PAD(0x05AC, 0x01DC, 4, 0x0000, 0, 0), - MX6_PAD_EIM_RW__GPIO_2_26 = IOMUX_PAD(0x05AC, 0x01DC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_RW__GPIO2_IO26 = IOMUX_PAD(0x05AC, 0x01DC, 5, 0x0000, 0, 0), MX6_PAD_EIM_RW__TPSMP_HDATA_10 = IOMUX_PAD(0x05AC, 0x01DC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_RW__SRC_BT_CFG_29 = IOMUX_PAD(0x05AC, 0x01DC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_RW__EPDC_SDDO_7 = IOMUX_PAD(0x05AC, 0x01DC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__WEIM_WEIM_WAIT = IOMUX_PAD(0x05B0, 0x01E0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B = IOMUX_PAD(0x05B0, 0x01E0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__GPIO_5_0 = IOMUX_PAD(0x05B0, 0x01E0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_RW__SRC_BOOT_CFG29 = IOMUX_PAD(0x05AC, 0x01DC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_RW__EPDC_DATA07 = IOMUX_PAD(0x05AC, 0x01DC, 8, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__EIM_WAIT_B = IOMUX_PAD(0x05B0, 0x01E0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__EIM_DTACK_B = IOMUX_PAD(0x05B0, 0x01E0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__GPIO5_IO00 = IOMUX_PAD(0x05B0, 0x01E0, 5, 0x0000, 0, 0), MX6_PAD_EIM_WAIT__TPSMP_HDATA_30 = IOMUX_PAD(0x05B0, 0x01E0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__SRC_BT_CFG_25 = IOMUX_PAD(0x05B0, 0x01E0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__SRC_BOOT_CFG25 = IOMUX_PAD(0x05B0, 0x01E0, 7, 0x0000, 0, 0), MX6_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x05B4, 0x01E4, 1, 0x0828, 0, 0), - MX6_PAD_ENET_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x05B4, 0x01E4, 2, 0x0840, 0, 0), - MX6_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x05B4, 0x01E4, 3, 0x08F4, 0, 0), - MX6_PAD_ENET_CRS_DV__GPIO_1_25 = IOMUX_PAD(0x05B4, 0x01E4, 5, 0x0000, 0, 0), + MX6_PAD_ENET_CRS_DV__ESAI_TX_CLK = IOMUX_PAD(0x05B4, 0x01E4, 2, 0x0840, 0, 0), + MX6_PAD_ENET_CRS_DV__SPDIF_EXT_CLK = IOMUX_PAD(0x05B4, 0x01E4, 3, 0x08F4, 0, 0), + MX6_PAD_ENET_CRS_DV__GPIO1_IO25 = IOMUX_PAD(0x05B4, 0x01E4, 5, 0x0000, 0, 0), MX6_PAD_ENET_CRS_DV__PHY_TDO = IOMUX_PAD(0x05B4, 0x01E4, 6, 0x0000, 0, 0), MX6_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD = IOMUX_PAD(0x05B4, 0x01E4, 7, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__MLB_MLBDAT = IOMUX_PAD(0x05B8, 0x01E8, 0, 0x08E0, 0, 0), + MX6_PAD_ENET_MDC__MLB_DATA = IOMUX_PAD(0x05B8, 0x01E8, 0, 0x08E0, 0, 0), MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__ESAI1_TX5_RX0 = IOMUX_PAD(0x05B8, 0x01E8, 2, 0x0858, 0, 0), + MX6_PAD_ENET_MDC__ESAI_TX5_RX0 = IOMUX_PAD(0x05B8, 0x01E8, 2, 0x0858, 0, 0), MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x05B8, 0x01E8, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__GPIO_1_31 = IOMUX_PAD(0x05B8, 0x01E8, 5, 0x0000, 0, 0), + MX6_PAD_ENET_MDC__GPIO1_IO31 = IOMUX_PAD(0x05B8, 0x01E8, 5, 0x0000, 0, 0), MX6_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET = IOMUX_PAD(0x05B8, 0x01E8, 7, 0x0000, 0, 0), MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0), - MX6_PAD_ENET_MDIO__ESAI1_SCKR = IOMUX_PAD(0x05BC, 0x01EC, 2, 0x083C, 0, 0), + MX6_PAD_ENET_MDIO__ESAI_RX_CLK = IOMUX_PAD(0x05BC, 0x01EC, 2, 0x083C, 0, 0), MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x05BC, 0x01EC, 3, 0x0000, 0, 0), MX6_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x05BC, 0x01EC, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__GPIO_1_22 = IOMUX_PAD(0x05BC, 0x01EC, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__SPDIF_PLOCK = IOMUX_PAD(0x05BC, 0x01EC, 6, 0x0000, 0, 0), + MX6_PAD_ENET_MDIO__GPIO1_IO22 = IOMUX_PAD(0x05BC, 0x01EC, 5, 0x0000, 0, 0), + MX6_PAD_ENET_MDIO__SPDIF_LOCK = IOMUX_PAD(0x05BC, 0x01EC, 6, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x05C0, 0x01F0, 2, 0x082C, 0, 0), + MX6_PAD_ENET_REF_CLK__ESAI_RX_FS = IOMUX_PAD(0x05C0, 0x01F0, 2, 0x082C, 0, 0), MX6_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 = IOMUX_PAD(0x05C0, 0x01F0, 3, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__GPIO_1_23 = IOMUX_PAD(0x05C0, 0x01F0, 5, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__SPDIF_SRCLK = IOMUX_PAD(0x05C0, 0x01F0, 6, 0x0000, 0, 0), + MX6_PAD_ENET_REF_CLK__GPIO1_IO23 = IOMUX_PAD(0x05C0, 0x01F0, 5, 0x0000, 0, 0), + MX6_PAD_ENET_REF_CLK__SPDIF_SR_CLK = IOMUX_PAD(0x05C0, 0x01F0, 6, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH = IOMUX_PAD(0x05C0, 0x01F0, 7, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ANATOP_USBOTG_ID = IOMUX_PAD(0x05C4, 0x01F4, 0, 0x0790, 0, 0), + MX6_PAD_ENET_RX_ER__USB_OTG_ID = IOMUX_PAD(0x05C4, 0x01F4, 0, 0x0790, 0, 0), MX6_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x05C4, 0x01F4, 1, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x05C4, 0x01F4, 2, 0x0834, 0, 0), - MX6_PAD_ENET_RX_ER__SPDIF_IN1 = IOMUX_PAD(0x05C4, 0x01F4, 3, 0x08F0, 1, 0), + MX6_PAD_ENET_RX_ER__ESAI_RX_HF_CLK = IOMUX_PAD(0x05C4, 0x01F4, 2, 0x0834, 0, 0), + MX6_PAD_ENET_RX_ER__SPDIF_IN = IOMUX_PAD(0x05C4, 0x01F4, 3, 0x08F0, 1, 0), MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT = IOMUX_PAD(0x05C4, 0x01F4, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__GPIO_1_24 = IOMUX_PAD(0x05C4, 0x01F4, 5, 0x0000, 0, 0), + MX6_PAD_ENET_RX_ER__GPIO1_IO24 = IOMUX_PAD(0x05C4, 0x01F4, 5, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__PHY_TDI = IOMUX_PAD(0x05C4, 0x01F4, 6, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD = IOMUX_PAD(0x05C4, 0x01F4, 7, 0x0000, 0, 0), MX6_PAD_ENET_RXD0__OSC32K_32K_OUT = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__ENET_RDATA_0 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0818, 0, 0), - MX6_PAD_ENET_RXD0__ESAI1_HCKT = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x0838, 0, 0), - MX6_PAD_ENET_RXD0__SPDIF_OUT1 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0818, 0, 0), + MX6_PAD_ENET_RXD0__ESAI_TX_HF_CLK = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x0838, 0, 0), + MX6_PAD_ENET_RXD0__SPDIF_OUT = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), + MX6_PAD_ENET_RXD0__GPIO1_IO27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), MX6_PAD_ENET_RXD0__PHY_TMS = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0), MX6_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV = IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__MLB_MLBSIG = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x08E4, 0, 0), - MX6_PAD_ENET_RXD1__ENET_RDATA_1 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x081C, 0, 0), - MX6_PAD_ENET_RXD1__ESAI1_FST = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x0830, 0, 0), + MX6_PAD_ENET_RXD1__MLB_SIG = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x08E4, 0, 0), + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x081C, 0, 0), + MX6_PAD_ENET_RXD1__ESAI_TX_FS = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x0830, 0, 0), MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__GPIO_1_26 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), + MX6_PAD_ENET_RXD1__GPIO1_IO26 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), MX6_PAD_ENET_RXD1__PHY_TCK = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0), MX6_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET = IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__ESAI1_TX3_RX2 = IOMUX_PAD(0x05D0, 0x0200, 2, 0x0850, 0, 0), - MX6_PAD_ENET_TX_EN__GPIO_1_28 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), + MX6_PAD_ENET_TX_EN__ESAI_TX3_RX2 = IOMUX_PAD(0x05D0, 0x0200, 2, 0x0850, 0, 0), + MX6_PAD_ENET_TX_EN__GPIO1_IO28 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__I2C4_SCL = IOMUX_PAD(0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, 0), - MX6_PAD_ENET_TXD0__ENET_TDATA_0 = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__ESAI1_TX4_RX1 = IOMUX_PAD(0x05D4, 0x0204, 2, 0x0854, 0, 0), - MX6_PAD_ENET_TXD0__GPIO_1_30 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), + MX6_PAD_ENET_TXD0__ESAI_TX4_RX1 = IOMUX_PAD(0x05D4, 0x0204, 2, 0x0854, 0, 0), + MX6_PAD_ENET_TXD0__GPIO1_IO30 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), MX6_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD = IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__MLB_MLBCLK = IOMUX_PAD(0x05D8, 0x0208, 0, 0x08DC, 0, 0), - MX6_PAD_ENET_TXD1__ENET_TDATA_1 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__ESAI1_TX2_RX3 = IOMUX_PAD(0x05D8, 0x0208, 2, 0x084C, 0, 0), + MX6_PAD_ENET_TXD1__MLB_CLK = IOMUX_PAD(0x05D8, 0x0208, 0, 0x08DC, 0, 0), + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0000, 0, 0), + MX6_PAD_ENET_TXD1__ESAI_TX2_RX3 = IOMUX_PAD(0x05D8, 0x0208, 2, 0x084C, 0, 0), MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__GPIO_1_29 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), + MX6_PAD_ENET_TXD1__GPIO1_IO29 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD = IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__I2C4_SDA = IOMUX_PAD(0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, 0), - MX6_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0000, 0, 0), - MX6_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x05DC, 0x020C, 2, 0x08C0, 1, 0), - MX6_PAD_GPIO_0__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0794, 0, 0), - MX6_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_0__GPIO_1_0 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x05DC, 0x020C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05E0, 0x0210, 0, 0x083C, 1, 0), - MX6_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05E0, 0x0210, 2, 0x08CC, 1, 0), + MX6_PAD_GPIO_0__CCM_CLKO1 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0000, 0, 0), + MX6_PAD_GPIO_0__KEY_COL5 = IOMUX_PAD(0x05DC, 0x020C, 2, 0x08C0, 1, 0), + MX6_PAD_GPIO_0__ASRC_EXT_CLK = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0794, 0, 0), + MX6_PAD_GPIO_0__EPIT1_OUT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_0__GPIO1_IO00 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_0__USB_H1_PWR = IOMUX_PAD(0x05DC, 0x020C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_0__SNVS_VIO_5 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_1__ESAI_RX_CLK = IOMUX_PAD(0x05E0, 0x0210, 0, 0x083C, 1, 0), + MX6_PAD_GPIO_1__WDOG2_B = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_1__KEY_ROW5 = IOMUX_PAD(0x05E0, 0x0210, 2, 0x08CC, 1, 0), MX6_PAD_GPIO_1__USB_OTG_ID = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0), - MX6_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_1__PWM2_OUT = IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_1__GPIO1_IO01 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_1__SD1_CD_B = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, 0), MX6_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0850, 1, 0), + MX6_PAD_GPIO_16__ESAI_TX3_RX2 = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0850, 1, 0), MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x05E4, 0x0214, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT = IOMUX_PAD(0x05E4, 0x0214, 2, 0x080C, 0, 0), - MX6_PAD_GPIO_16__USDHC1_LCTL = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x05E4, 0x0214, 4, 0x08F0, 2, 0), - MX6_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_16__ENET_REF_CLK = IOMUX_PAD(0x05E4, 0x0214, 2, 0x080C, 0, 0), + MX6_PAD_GPIO_16__SD1_LCTL = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_16__SPDIF_IN = IOMUX_PAD(0x05E4, 0x0214, 4, 0x08F0, 2, 0), + MX6_PAD_GPIO_16__GPIO7_IO11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), MX6_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0), - MX6_PAD_GPIO_16__SJC_DE_B = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_17__ESAI1_TX0 = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0844, 0, 0), + MX6_PAD_GPIO_16__JTAG_DE_B = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_17__ESAI_TX0 = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0844, 0, 0), MX6_PAD_GPIO_17__ENET_1588_EVENT3_IN = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_17__CCM_PMIC_RDY = IOMUX_PAD(0x05E8, 0x0218, 2, 0x07D4, 1, 0), - MX6_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x08E8, 1, 0), - MX6_PAD_GPIO_17__SPDIF_OUT1 = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_17__CCM_PMIC_READY = IOMUX_PAD(0x05E8, 0x0218, 2, 0x07D4, 1, 0), + MX6_PAD_GPIO_17__SDMA_EXT_EVENT0 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x08E8, 1, 0), + MX6_PAD_GPIO_17__SPDIF_OUT = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_17__GPIO7_IO12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), MX6_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_18__ESAI1_TX1 = IOMUX_PAD(0x05EC, 0x021C, 0, 0x0848, 0, 0), + MX6_PAD_GPIO_18__ESAI_TX1 = IOMUX_PAD(0x05EC, 0x021C, 0, 0x0848, 0, 0), MX6_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0814, 0, 0), - MX6_PAD_GPIO_18__USDHC3_VSELECT = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x08EC, 1, 0), - MX6_PAD_GPIO_18__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05EC, 0x021C, 4, 0x0794, 1, 0), - MX6_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_18__SD3_VSELECT = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_18__SDMA_EXT_EVENT1 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x08EC, 1, 0), + MX6_PAD_GPIO_18__ASRC_EXT_CLK = IOMUX_PAD(0x05EC, 0x021C, 4, 0x0794, 1, 0), + MX6_PAD_GPIO_18__GPIO7_IO13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_18__SNVS_VIO_5_CTL = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0), MX6_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x05F0, 0x0220, 0, 0x08C0, 2, 0), + MX6_PAD_GPIO_19__KEY_COL5 = IOMUX_PAD(0x05F0, 0x0220, 0, 0x08C0, 2, 0), MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x05F0, 0x0220, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x05F0, 0x0220, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_19__SPDIF_OUT = IOMUX_PAD(0x05F0, 0x0220, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_19__CCM_CLKO1 = IOMUX_PAD(0x05F0, 0x0220, 3, 0x0000, 0, 0), MX6_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_19__GPIO4_IO05 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), MX6_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0), MX6_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x05F4, 0x0224, 0, 0x0830, 1, 0), + MX6_PAD_GPIO_2__ESAI_TX_FS = IOMUX_PAD(0x05F4, 0x0224, 0, 0x0830, 1, 0), MX6_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08D0, 1, 0), + MX6_PAD_GPIO_2__KEY_ROW6 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08D0, 1, 0), MX6_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0), MX6_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_2__GPIO_1_2 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_2__USDHC2_WP = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x05F4, 0x0224, 7, 0x08E0, 1, 0), - MX6_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x05F8, 0x0228, 0, 0x0834, 1, 0), + MX6_PAD_GPIO_2__GPIO1_IO02 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_2__SD2_WP = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_2__MLB_DATA = IOMUX_PAD(0x05F4, 0x0224, 7, 0x08E0, 1, 0), + MX6_PAD_GPIO_3__ESAI_RX_HF_CLK = IOMUX_PAD(0x05F8, 0x0228, 0, 0x0834, 1, 0), MX6_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0), MX6_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, 0), - MX6_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0), MX6_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_3__GPIO_1_3 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x05F8, 0x0228, 6, 0x0924, 1, 0), - MX6_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x05F8, 0x0228, 7, 0x08DC, 1, 0), - MX6_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0838, 1, 0), + MX6_PAD_GPIO_3__GPIO1_IO03 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_3__USB_H1_OC = IOMUX_PAD(0x05F8, 0x0228, 6, 0x0924, 1, 0), + MX6_PAD_GPIO_3__MLB_CLK = IOMUX_PAD(0x05F8, 0x0228, 7, 0x08DC, 1, 0), + MX6_PAD_GPIO_4__ESAI_TX_HF_CLK = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0838, 1, 0), MX6_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x05FC, 0x022C, 2, 0x08C8, 1, 0), + MX6_PAD_GPIO_4__KEY_COL7 = IOMUX_PAD(0x05FC, 0x022C, 2, 0x08C8, 1, 0), MX6_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0), MX6_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_4__GPIO_1_4 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_4__USDHC2_CD = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_4__GPIO1_IO04 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_4__SD2_CD_B = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0000, 0, 0), MX6_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x0600, 0x0230, 0, 0x084C, 1, 0), + MX6_PAD_GPIO_5__ESAI_TX2_RX3 = IOMUX_PAD(0x0600, 0x0230, 0, 0x084C, 1, 0), MX6_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 = IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x0600, 0x0230, 2, 0x08D4, 1, 0), - MX6_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_5__KEY_ROW7 = IOMUX_PAD(0x0600, 0x0230, 2, 0x08D4, 1, 0), + MX6_PAD_GPIO_5__CCM_CLKO1 = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0), MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_5__GPIO1_IO05 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0), - MX6_PAD_GPIO_5__SIMBA_EVENTI = IOMUX_PAD(0x0600, 0x0230, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x0604, 0x0234, 0, 0x0840, 1, 0), + MX6_PAD_GPIO_5__ARM_EVENTI = IOMUX_PAD(0x0600, 0x0230, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_6__ESAI_TX_CLK = IOMUX_PAD(0x0604, 0x0234, 0, 0x0840, 1, 0), MX6_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0), MX6_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0), MX6_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0), MX6_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_6__GPIO_1_6 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_6__USDHC2_LCTL = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x0604, 0x0234, 7, 0x08E4, 1, 0), - MX6_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x0608, 0x0238, 0, 0x0854, 1, 0), - MX6_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x0608, 0x0238, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_TXD = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_RXD = IOMUX_PAD(0x0608, 0x0238, 4, 0x0904, 2, 0), - MX6_PAD_GPIO_7__GPIO_1_7 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_6__GPIO1_IO06 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_6__SD2_LCTL = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_6__MLB_SIG = IOMUX_PAD(0x0604, 0x0234, 7, 0x08E4, 1, 0), + MX6_PAD_GPIO_7__ESAI_TX4_RX1 = IOMUX_PAD(0x0608, 0x0238, 0, 0x0854, 1, 0), + MX6_PAD_GPIO_7__EPIT1_OUT = IOMUX_PAD(0x0608, 0x0238, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_7__FLEXCAN1_TX = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_7__UART2_TX_DATA = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_7__UART2_RX_DATA = IOMUX_PAD(0x0608, 0x0238, 4, 0x0904, 2, 0), + MX6_PAD_GPIO_7__GPIO1_IO07 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_7__SPDIF_LOCK = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_7__USB_OTG_HOST_MODE = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0), MX6_PAD_GPIO_7__I2C4_SCL = IOMUX_PAD(0x0608, 0x0238, 8 | IOMUX_CONFIG_SION, 0x0880, 1, 0), - MX6_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x060C, 0x023C, 0, 0x0858, 1, 0), - MX6_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x060C, 0x023C, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x060C, 0x023C, 3, 0x07C8, 0, 0), - MX6_PAD_GPIO_8__UART2_TXD = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_8__UART2_RXD = IOMUX_PAD(0x060C, 0x023C, 4, 0x0904, 3, 0), - MX6_PAD_GPIO_8__GPIO_1_8 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x060C, 0x023C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_8__ESAI_TX5_RX0 = IOMUX_PAD(0x060C, 0x023C, 0, 0x0858, 1, 0), + MX6_PAD_GPIO_8__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_8__EPIT2_OUT = IOMUX_PAD(0x060C, 0x023C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_8__FLEXCAN1_RX = IOMUX_PAD(0x060C, 0x023C, 3, 0x07C8, 0, 0), + MX6_PAD_GPIO_8__UART2_TX_DATA = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_8__UART2_RX_DATA = IOMUX_PAD(0x060C, 0x023C, 4, 0x0904, 3, 0), + MX6_PAD_GPIO_8__GPIO1_IO08 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_8__SPDIF_SR_CLK = IOMUX_PAD(0x060C, 0x023C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0), MX6_PAD_GPIO_8__I2C4_SDA = IOMUX_PAD(0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, 0), - MX6_PAD_GPIO_9__ESAI1_FSR = IOMUX_PAD(0x0610, 0x0240, 0, 0x082C, 1, 0), - MX6_PAD_GPIO_9__WDOG1_WDOG_B = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_9__KPP_COL_6 = IOMUX_PAD(0x0610, 0x0240, 2, 0x08C4, 1, 0), + MX6_PAD_GPIO_9__ESAI_RX_FS = IOMUX_PAD(0x0610, 0x0240, 0, 0x082C, 1, 0), + MX6_PAD_GPIO_9__WDOG1_B = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_9__KEY_COL6 = IOMUX_PAD(0x0610, 0x0240, 2, 0x08C4, 1, 0), MX6_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_9__PWM1_PWMO = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_9__GPIO_1_9 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_9__USDHC1_WP = IOMUX_PAD(0x0610, 0x0240, 6, 0x092C, 1, 0), + MX6_PAD_GPIO_9__PWM1_OUT = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_9__GPIO1_IO09 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_9__SD1_WP = IOMUX_PAD(0x0610, 0x0240, 6, 0x092C, 1, 0), MX6_PAD_GPIO_9__SRC_EARLY_RST = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0), MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x0614, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x0618, NO_MUX_I, 0, 0x0000, 0, 0), @@ -1153,89 +1153,89 @@ enum { MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x0624, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_JTAG_TRSTB__SJC_TRSTB = IOMUX_PAD(0x0628, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x062C, 0x0244, 0, 0x07D8, 3, 0), - MX6_PAD_KEY_COL0__ENET_RDATA_3 = IOMUX_PAD(0x062C, 0x0244, 1, 0x0824, 0, 0), - MX6_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x062C, 0x0244, 2, 0x07C0, 1, 0), - MX6_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x062C, 0x0244, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_TXD = IOMUX_PAD(0x062C, 0x0244, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_RXD = IOMUX_PAD(0x062C, 0x0244, 4, 0x0914, 2, 0), - MX6_PAD_KEY_COL0__GPIO_4_6 = IOMUX_PAD(0x062C, 0x0244, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__DCIC1_DCIC_OUT = IOMUX_PAD(0x062C, 0x0244, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__ENET_RX_DATA3 = IOMUX_PAD(0x062C, 0x0244, 1, 0x0824, 0, 0), + MX6_PAD_KEY_COL0__AUD5_TXC = IOMUX_PAD(0x062C, 0x0244, 2, 0x07C0, 1, 0), + MX6_PAD_KEY_COL0__KEY_COL0 = IOMUX_PAD(0x062C, 0x0244, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__UART4_TX_DATA = IOMUX_PAD(0x062C, 0x0244, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__UART4_RX_DATA = IOMUX_PAD(0x062C, 0x0244, 4, 0x0914, 2, 0), + MX6_PAD_KEY_COL0__GPIO4_IO06 = IOMUX_PAD(0x062C, 0x0244, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__DCIC1_OUT = IOMUX_PAD(0x062C, 0x0244, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x062C, 0x0244, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x0630, 0x0248, 0, 0x07DC, 3, 0), MX6_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x0630, 0x0248, 1, 0x0810, 1, 0), - MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x0630, 0x0248, 2, 0x07C4, 1, 0), - MX6_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x0630, 0x0248, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_TXD = IOMUX_PAD(0x0630, 0x0248, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_RXD = IOMUX_PAD(0x0630, 0x0248, 4, 0x091C, 2, 0), - MX6_PAD_KEY_COL1__GPIO_4_8 = IOMUX_PAD(0x0630, 0x0248, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__USDHC1_VSELECT = IOMUX_PAD(0x0630, 0x0248, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__AUD5_TXFS = IOMUX_PAD(0x0630, 0x0248, 2, 0x07C4, 1, 0), + MX6_PAD_KEY_COL1__KEY_COL1 = IOMUX_PAD(0x0630, 0x0248, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__UART5_TX_DATA = IOMUX_PAD(0x0630, 0x0248, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__UART5_RX_DATA = IOMUX_PAD(0x0630, 0x0248, 4, 0x091C, 2, 0), + MX6_PAD_KEY_COL1__GPIO4_IO08 = IOMUX_PAD(0x0630, 0x0248, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__SD1_VSELECT = IOMUX_PAD(0x0630, 0x0248, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL1__PL301_SIM_MX6DL_PER1_HADDR_1 = IOMUX_PAD(0x0630, 0x0248, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x0634, 0x024C, 0, 0x07E8, 2, 0), - MX6_PAD_KEY_COL2__ENET_RDATA_2 = IOMUX_PAD(0x0634, 0x024C, 1, 0x0820, 0, 0), - MX6_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x0634, 0x024C, 2, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x0634, 0x024C, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__ENET_RX_DATA2 = IOMUX_PAD(0x0634, 0x024C, 1, 0x0820, 0, 0), + MX6_PAD_KEY_COL2__FLEXCAN1_TX = IOMUX_PAD(0x0634, 0x024C, 2, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__KEY_COL2 = IOMUX_PAD(0x0634, 0x024C, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x0634, 0x024C, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__GPIO_4_10 = IOMUX_PAD(0x0634, 0x024C, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP = IOMUX_PAD(0x0634, 0x024C, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__GPIO4_IO10 = IOMUX_PAD(0x0634, 0x024C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE = IOMUX_PAD(0x0634, 0x024C, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL2__PL301_SIM_MX6DL_PER1_HADDR_3 = IOMUX_PAD(0x0634, 0x024C, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x0638, 0x0250, 0, 0x07F0, 1, 0), MX6_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x0638, 0x0250, 1, 0x0000, 0, 0), MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x0638, 0x0250, 2, 0x0860, 1, 0), - MX6_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x0638, 0x0250, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__KEY_COL3 = IOMUX_PAD(0x0638, 0x0250, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0), - MX6_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x0638, 0x0250, 6, 0x08F0, 3, 0), + MX6_PAD_KEY_COL3__GPIO4_IO12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__SPDIF_IN = IOMUX_PAD(0x0638, 0x0250, 6, 0x08F0, 3, 0), MX6_PAD_KEY_COL3__PL301_SIM_MX6DL_PER1_HADDR_5 = IOMUX_PAD(0x0638, 0x0250, 7, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x063C, 0x0254, 0, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__IPU1_SISG_4 = IOMUX_PAD(0x063C, 0x0254, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x063C, 0x0254, 2, 0x0920, 1, 0), - MX6_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x063C, 0x0254, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_CTS = IOMUX_PAD(0x063C, 0x0254, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x063C, 0x0254, 4, 0x0918, 2, 0), - MX6_PAD_KEY_COL4__GPIO_4_14 = IOMUX_PAD(0x063C, 0x0254, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__FLEXCAN2_TX = IOMUX_PAD(0x063C, 0x0254, 0, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__IPU1_SISG4 = IOMUX_PAD(0x063C, 0x0254, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__USB_OTG_OC = IOMUX_PAD(0x063C, 0x0254, 2, 0x0920, 1, 0), + MX6_PAD_KEY_COL4__KEY_COL4 = IOMUX_PAD(0x063C, 0x0254, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__UART5_CTS_B = IOMUX_PAD(0x063C, 0x0254, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__UART5_RTS_B = IOMUX_PAD(0x063C, 0x0254, 4, 0x0918, 2, 0), + MX6_PAD_KEY_COL4__GPIO4_IO14 = IOMUX_PAD(0x063C, 0x0254, 5, 0x0000, 0, 0), MX6_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 = IOMUX_PAD(0x063C, 0x0254, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL4__PL301_SIM_MX6DL_PER1_HADDR_7 = IOMUX_PAD(0x063C, 0x0254, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x0640, 0x0258, 0, 0x07E0, 3, 0), - MX6_PAD_KEY_ROW0__ENET_TDATA_3 = IOMUX_PAD(0x0640, 0x0258, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x0640, 0x0258, 2, 0x07B4, 1, 0), - MX6_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x0640, 0x0258, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__UART4_TXD = IOMUX_PAD(0x0640, 0x0258, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__UART4_RXD = IOMUX_PAD(0x0640, 0x0258, 4, 0x0914, 3, 0), - MX6_PAD_KEY_ROW0__GPIO_4_7 = IOMUX_PAD(0x0640, 0x0258, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__DCIC2_DCIC_OUT = IOMUX_PAD(0x0640, 0x0258, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__ENET_TX_DATA3 = IOMUX_PAD(0x0640, 0x0258, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__AUD5_TXD = IOMUX_PAD(0x0640, 0x0258, 2, 0x07B4, 1, 0), + MX6_PAD_KEY_ROW0__KEY_ROW0 = IOMUX_PAD(0x0640, 0x0258, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__UART4_TX_DATA = IOMUX_PAD(0x0640, 0x0258, 4, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__UART4_RX_DATA = IOMUX_PAD(0x0640, 0x0258, 4, 0x0914, 3, 0), + MX6_PAD_KEY_ROW0__GPIO4_IO07 = IOMUX_PAD(0x0640, 0x0258, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__DCIC2_OUT = IOMUX_PAD(0x0640, 0x0258, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__PL301_SIM_MX6DL_PER1_HADDR_0 = IOMUX_PAD(0x0640, 0x0258, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x025C, 0, 0x07E4, 3, 0), MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x0644, 0x025C, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x0644, 0x025C, 2, 0x07B0, 1, 0), - MX6_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x0644, 0x025C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__UART5_TXD = IOMUX_PAD(0x0644, 0x025C, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__UART5_RXD = IOMUX_PAD(0x0644, 0x025C, 4, 0x091C, 3, 0), - MX6_PAD_KEY_ROW1__GPIO_4_9 = IOMUX_PAD(0x0644, 0x025C, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__USDHC2_VSELECT = IOMUX_PAD(0x0644, 0x025C, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__AUD5_RXD = IOMUX_PAD(0x0644, 0x025C, 2, 0x07B0, 1, 0), + MX6_PAD_KEY_ROW1__KEY_ROW1 = IOMUX_PAD(0x0644, 0x025C, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__UART5_TX_DATA = IOMUX_PAD(0x0644, 0x025C, 4, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__UART5_RX_DATA = IOMUX_PAD(0x0644, 0x025C, 4, 0x091C, 3, 0), + MX6_PAD_KEY_ROW1__GPIO4_IO09 = IOMUX_PAD(0x0644, 0x025C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__SD2_VSELECT = IOMUX_PAD(0x0644, 0x025C, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__PL301_SIM_MX6DL_PER1_HADDR_2 = IOMUX_PAD(0x0644, 0x025C, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x0648, 0x0260, 0, 0x07EC, 1, 0), - MX6_PAD_KEY_ROW2__ENET_TDATA_2 = IOMUX_PAD(0x0648, 0x0260, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x0648, 0x0260, 2, 0x07C8, 1, 0), - MX6_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x0648, 0x0260, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__USDHC2_VSELECT = IOMUX_PAD(0x0648, 0x0260, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__GPIO_4_11 = IOMUX_PAD(0x0648, 0x0260, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__ENET_TX_DATA2 = IOMUX_PAD(0x0648, 0x0260, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__FLEXCAN1_RX = IOMUX_PAD(0x0648, 0x0260, 2, 0x07C8, 1, 0), + MX6_PAD_KEY_ROW2__KEY_ROW2 = IOMUX_PAD(0x0648, 0x0260, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__SD2_VSELECT = IOMUX_PAD(0x0648, 0x0260, 4, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__GPIO4_IO11 = IOMUX_PAD(0x0648, 0x0260, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x0648, 0x0260, 6, 0x085C, 1, 0), MX6_PAD_KEY_ROW2__PL301_SIM_MX6DL_PER1_HADDR_4 = IOMUX_PAD(0x0648, 0x0260, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x064C, 0x0264, 0, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x064C, 0x0264, 1, 0x0794, 2, 0), + MX6_PAD_KEY_ROW3__ASRC_EXT_CLK = IOMUX_PAD(0x064C, 0x0264, 1, 0x0794, 2, 0), MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x064C, 0x0264, 2, 0x0864, 1, 0), - MX6_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x064C, 0x0264, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__KEY_ROW3 = IOMUX_PAD(0x064C, 0x0264, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0), - MX6_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__USDHC1_VSELECT = IOMUX_PAD(0x064C, 0x0264, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__GPIO4_IO13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__SD1_VSELECT = IOMUX_PAD(0x064C, 0x0264, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__PL301_SIM_MX6DL_PER1_HADDR_6 = IOMUX_PAD(0x064C, 0x0264, 7, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x0650, 0x0268, 0, 0x07CC, 0, 0), - MX6_PAD_KEY_ROW4__IPU1_SISG_5 = IOMUX_PAD(0x0650, 0x0268, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x0650, 0x0268, 2, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x0650, 0x0268, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x0650, 0x0268, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__UART5_RTS = IOMUX_PAD(0x0650, 0x0268, 4, 0x0918, 3, 0), - MX6_PAD_KEY_ROW4__GPIO_4_15 = IOMUX_PAD(0x0650, 0x0268, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__FLEXCAN2_RX = IOMUX_PAD(0x0650, 0x0268, 0, 0x07CC, 0, 0), + MX6_PAD_KEY_ROW4__IPU1_SISG5 = IOMUX_PAD(0x0650, 0x0268, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__USB_OTG_PWR = IOMUX_PAD(0x0650, 0x0268, 2, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__KEY_ROW4 = IOMUX_PAD(0x0650, 0x0268, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__UART5_CTS_B = IOMUX_PAD(0x0650, 0x0268, 4, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__UART5_RTS_B = IOMUX_PAD(0x0650, 0x0268, 4, 0x0918, 3, 0), + MX6_PAD_KEY_ROW4__GPIO4_IO15 = IOMUX_PAD(0x0650, 0x0268, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 = IOMUX_PAD(0x0650, 0x0268, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__PL301_SIM_MX6DL_PER1_HADDR_8 = IOMUX_PAD(0x0650, 0x0268, 7, 0x0000, 0, 0), MX6_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), @@ -1248,117 +1248,117 @@ enum { MX6_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__RAWNAND_ALE = IOMUX_PAD(0x0654, 0x026C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__USDHC4_RST = IOMUX_PAD(0x0654, 0x026C, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__NAND_ALE = IOMUX_PAD(0x0654, 0x026C, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__SD4_RESET = IOMUX_PAD(0x0654, 0x026C, 1, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 = IOMUX_PAD(0x0654, 0x026C, 2, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 = IOMUX_PAD(0x0654, 0x026C, 3, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 = IOMUX_PAD(0x0654, 0x026C, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__GPIO_6_8 = IOMUX_PAD(0x0654, 0x026C, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__GPIO6_IO08 = IOMUX_PAD(0x0654, 0x026C, 5, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 = IOMUX_PAD(0x0654, 0x026C, 6, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__USDHC3_CLKI = IOMUX_PAD(0x0654, 0x026C, 8, 0x0934, 0, 0), - MX6_PAD_NANDF_CLE__RAWNAND_CLE = IOMUX_PAD(0x0658, 0x0270, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CLE__NAND_CLE = IOMUX_PAD(0x0658, 0x0270, 0, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 = IOMUX_PAD(0x0658, 0x0270, 2, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 = IOMUX_PAD(0x0658, 0x0270, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 = IOMUX_PAD(0x0658, 0x0270, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__GPIO_6_7 = IOMUX_PAD(0x0658, 0x0270, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CLE__GPIO6_IO07 = IOMUX_PAD(0x0658, 0x0270, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 = IOMUX_PAD(0x0658, 0x0270, 6, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__USDHC3_CLKO = IOMUX_PAD(0x0658, 0x0270, 8, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__RAWNAND_CE0N = IOMUX_PAD(0x065C, 0x0274, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS0__NAND_CE0_B = IOMUX_PAD(0x065C, 0x0274, 0, 0x0000, 0, 0), MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 = IOMUX_PAD(0x065C, 0x0274, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 = IOMUX_PAD(0x065C, 0x0274, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__GPIO_6_11 = IOMUX_PAD(0x065C, 0x0274, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS0__GPIO6_IO11 = IOMUX_PAD(0x065C, 0x0274, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CS0__USDHC1_CLKO = IOMUX_PAD(0x065C, 0x0274, 8, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__RAWNAND_CE1N = IOMUX_PAD(0x0660, 0x0278, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__USDHC4_VSELECT = IOMUX_PAD(0x0660, 0x0278, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__USDHC3_VSELECT = IOMUX_PAD(0x0660, 0x0278, 2, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__NAND_CE1_B = IOMUX_PAD(0x0660, 0x0278, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__SD4_VSELECT = IOMUX_PAD(0x0660, 0x0278, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__SD3_VSELECT = IOMUX_PAD(0x0660, 0x0278, 2, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 = IOMUX_PAD(0x0660, 0x0278, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__GPIO6_IO14 = IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__PL301_SIM_MX6DL_PER1_HREADYOUT = IOMUX_PAD(0x0660, 0x0278, 7, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__USDHC1_CLKI = IOMUX_PAD(0x0660, 0x0278, 8, 0x0928, 0, 0), - MX6_PAD_NANDF_CS2__RAWNAND_CE2N = IOMUX_PAD(0x0664, 0x027C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__IPU1_SISG_0 = IOMUX_PAD(0x0664, 0x027C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x0664, 0x027C, 2, 0x0844, 1, 0), - MX6_PAD_NANDF_CS2__WEIM_WEIM_CRE = IOMUX_PAD(0x0664, 0x027C, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__NAND_CE2_B = IOMUX_PAD(0x0664, 0x027C, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__IPU1_SISG0 = IOMUX_PAD(0x0664, 0x027C, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__ESAI_TX0 = IOMUX_PAD(0x0664, 0x027C, 2, 0x0844, 1, 0), + MX6_PAD_NANDF_CS2__EIM_CRE = IOMUX_PAD(0x0664, 0x027C, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x0664, 0x027C, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__GPIO_6_15 = IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__GPIO6_IO15 = IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__USDHC2_CLKO = IOMUX_PAD(0x0664, 0x027C, 8, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__RAWNAND_CE3N = IOMUX_PAD(0x0668, 0x0280, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__IPU1_SISG_1 = IOMUX_PAD(0x0668, 0x0280, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__ESAI1_TX1 = IOMUX_PAD(0x0668, 0x0280, 2, 0x0848, 1, 0), - MX6_PAD_NANDF_CS3__WEIM_WEIM_A_26 = IOMUX_PAD(0x0668, 0x0280, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__NAND_CE3_B = IOMUX_PAD(0x0668, 0x0280, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__IPU1_SISG1 = IOMUX_PAD(0x0668, 0x0280, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__ESAI_TX1 = IOMUX_PAD(0x0668, 0x0280, 2, 0x0848, 1, 0), + MX6_PAD_NANDF_CS3__EIM_ADDR26 = IOMUX_PAD(0x0668, 0x0280, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 = IOMUX_PAD(0x0668, 0x0280, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__GPIO_6_16 = IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__GPIO6_IO16 = IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__TPSMP_CLK = IOMUX_PAD(0x0668, 0x0280, 7, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__USDHC2_CLKI = IOMUX_PAD(0x0668, 0x0280, 8, 0x0930, 0, 0), MX6_PAD_NANDF_CS3__I2C4_SDA = IOMUX_PAD(0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, 0), - MX6_PAD_NANDF_D0__RAWNAND_D0 = IOMUX_PAD(0x066C, 0x0284, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__USDHC1_DAT4 = IOMUX_PAD(0x066C, 0x0284, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__NAND_DATA00 = IOMUX_PAD(0x066C, 0x0284, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__SD1_DATA4 = IOMUX_PAD(0x066C, 0x0284, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 = IOMUX_PAD(0x066C, 0x0284, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 = IOMUX_PAD(0x066C, 0x0284, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 = IOMUX_PAD(0x066C, 0x0284, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__GPIO_2_0 = IOMUX_PAD(0x066C, 0x0284, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__GPIO2_IO00 = IOMUX_PAD(0x066C, 0x0284, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 = IOMUX_PAD(0x066C, 0x0284, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__RAWNAND_D1 = IOMUX_PAD(0x0670, 0x0288, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__USDHC1_DAT5 = IOMUX_PAD(0x0670, 0x0288, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__NAND_DATA01 = IOMUX_PAD(0x0670, 0x0288, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__SD1_DATA5 = IOMUX_PAD(0x0670, 0x0288, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 = IOMUX_PAD(0x0670, 0x0288, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 = IOMUX_PAD(0x0670, 0x0288, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 = IOMUX_PAD(0x0670, 0x0288, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__GPIO2_IO01 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 = IOMUX_PAD(0x0670, 0x0288, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__RAWNAND_D2 = IOMUX_PAD(0x0674, 0x028C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__USDHC1_DAT6 = IOMUX_PAD(0x0674, 0x028C, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__NAND_DATA02 = IOMUX_PAD(0x0674, 0x028C, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__SD1_DATA6 = IOMUX_PAD(0x0674, 0x028C, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 = IOMUX_PAD(0x0674, 0x028C, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 = IOMUX_PAD(0x0674, 0x028C, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 = IOMUX_PAD(0x0674, 0x028C, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__GPIO2_IO02 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 = IOMUX_PAD(0x0674, 0x028C, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__RAWNAND_D3 = IOMUX_PAD(0x0678, 0x0290, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__USDHC1_DAT7 = IOMUX_PAD(0x0678, 0x0290, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__NAND_DATA03 = IOMUX_PAD(0x0678, 0x0290, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__SD1_DATA7 = IOMUX_PAD(0x0678, 0x0290, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 = IOMUX_PAD(0x0678, 0x0290, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 = IOMUX_PAD(0x0678, 0x0290, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 = IOMUX_PAD(0x0678, 0x0290, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__GPIO2_IO03 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 = IOMUX_PAD(0x0678, 0x0290, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__RAWNAND_D4 = IOMUX_PAD(0x067C, 0x0294, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__USDHC2_DAT4 = IOMUX_PAD(0x067C, 0x0294, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__NAND_DATA04 = IOMUX_PAD(0x067C, 0x0294, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__SD2_DATA4 = IOMUX_PAD(0x067C, 0x0294, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 = IOMUX_PAD(0x067C, 0x0294, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 = IOMUX_PAD(0x067C, 0x0294, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 = IOMUX_PAD(0x067C, 0x0294, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__GPIO2_IO04 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 = IOMUX_PAD(0x067C, 0x0294, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__RAWNAND_D5 = IOMUX_PAD(0x0680, 0x0298, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__USDHC2_DAT5 = IOMUX_PAD(0x0680, 0x0298, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__NAND_DATA05 = IOMUX_PAD(0x0680, 0x0298, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__SD2_DATA5 = IOMUX_PAD(0x0680, 0x0298, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 = IOMUX_PAD(0x0680, 0x0298, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 = IOMUX_PAD(0x0680, 0x0298, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 = IOMUX_PAD(0x0680, 0x0298, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__GPIO_2_5 = IOMUX_PAD(0x0680, 0x0298, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__GPIO2_IO05 = IOMUX_PAD(0x0680, 0x0298, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 = IOMUX_PAD(0x0680, 0x0298, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__RAWNAND_D6 = IOMUX_PAD(0x0684, 0x029C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__USDHC2_DAT6 = IOMUX_PAD(0x0684, 0x029C, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__NAND_DATA06 = IOMUX_PAD(0x0684, 0x029C, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__SD2_DATA6 = IOMUX_PAD(0x0684, 0x029C, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 = IOMUX_PAD(0x0684, 0x029C, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 = IOMUX_PAD(0x0684, 0x029C, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 = IOMUX_PAD(0x0684, 0x029C, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__GPIO2_IO06 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 = IOMUX_PAD(0x0684, 0x029C, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__RAWNAND_D7 = IOMUX_PAD(0x0688, 0x02A0, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__USDHC2_DAT7 = IOMUX_PAD(0x0688, 0x02A0, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__NAND_DATA07 = IOMUX_PAD(0x0688, 0x02A0, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__SD2_DATA7 = IOMUX_PAD(0x0688, 0x02A0, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 = IOMUX_PAD(0x0688, 0x02A0, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 = IOMUX_PAD(0x0688, 0x02A0, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 = IOMUX_PAD(0x0688, 0x02A0, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__GPIO_2_7 = IOMUX_PAD(0x0688, 0x02A0, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__GPIO2_IO07 = IOMUX_PAD(0x0688, 0x02A0, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0688, 0x02A0, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__RAWNAND_READY0 = IOMUX_PAD(0x068C, 0x02A4, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__NAND_READY_B = IOMUX_PAD(0x068C, 0x02A4, 0, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 = IOMUX_PAD(0x068C, 0x02A4, 2, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 = IOMUX_PAD(0x068C, 0x02A4, 3, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 = IOMUX_PAD(0x068C, 0x02A4, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__GPIO_6_10 = IOMUX_PAD(0x068C, 0x02A4, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__GPIO6_IO10 = IOMUX_PAD(0x068C, 0x02A4, 5, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 = IOMUX_PAD(0x068C, 0x02A4, 6, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__USDHC4_CLKI = IOMUX_PAD(0x068C, 0x02A4, 8, 0x0938, 0, 0), - MX6_PAD_NANDF_WP_B__RAWNAND_RESETN = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__NAND_WP_B = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__GPIO_6_9 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__GPIO6_IO09 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__USDHC4_CLKO = IOMUX_PAD(0x0690, 0x02A8, 8, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__I2C4_SCL = IOMUX_PAD(0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0), @@ -1366,305 +1366,305 @@ enum { MX6_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_POR_B__SRC_POR_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_RESET_IN_B__SRC_RESET_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0), - MX6_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD0__HSI_RX_READY = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD0__RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0), + MX6_PAD_RGMII_RD0__GPIO6_IO25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0), - MX6_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD1__HSI_TX_FLAG = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD1__RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0), + MX6_PAD_RGMII_RD1__GPIO6_IO27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0), MX6_PAD_RGMII_RD1__SJC_FAIL = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0), - MX6_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD2__HSI_TX_DATA = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD2__RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0), + MX6_PAD_RGMII_RD2__GPIO6_IO28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE = IOMUX_PAD(0x06A0, 0x02B8, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0), - MX6_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD3__HSI_TX_WAKE = IOMUX_PAD(0x06A0, 0x02B8, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD3__RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0), + MX6_PAD_RGMII_RD3__GPIO6_IO29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__USBOH3_H3_DATA = IOMUX_PAD(0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX6_PAD_RGMII_RX_CTL__USB_H3_DATA = IOMUX_PAD(0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0), - MX6_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0), MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE = IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE_START = IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP), - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0), - MX6_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RXC__USB_H3_STROBE = IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP), + MX6_PAD_RGMII_RXC__RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0), + MX6_PAD_RGMII_RXC__GPIO6_IO30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__GPIO_6_20 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__HSI_TX_READY = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__GPIO6_IO20 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__GPIO_6_21 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__HSI_RX_FLAG = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__GPIO6_IO21 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0), MX6_PAD_RGMII_TD1__CCM_PLL3_BYP = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__GPIO_6_22 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__HSI_RX_DATA = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__GPIO6_IO22 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0), MX6_PAD_RGMII_TD2__CCM_PLL2_BYP = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__GPIO_6_23 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__HSI_RX_WAKE = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__GPIO6_IO23 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 = IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE_START = IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP), + MX6_PAD_RGMII_TX_CTL__USB_H2_STROBE = IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__GPIO_6_26 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TX_CTL__GPIO6_IO26 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x080C, 1, 0), - MX6_PAD_RGMII_TXC__USBOH3_H2_DATA = IOMUX_PAD(0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x08F4, 1, 0), - MX6_PAD_RGMII_TXC__GPIO_6_19 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TX_CTL__ENET_REF_CLK = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x080C, 1, 0), + MX6_PAD_RGMII_TXC__USB_H2_DATA = IOMUX_PAD(0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__SPDIF_EXT_CLK = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x08F4, 1, 0), + MX6_PAD_RGMII_TXC__GPIO6_IO19 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, 0), + MX6_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, 0), MX6_PAD_SD1_CLK__OSC32K_32K_OUT = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0), MX6_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__GPIO_1_20 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPIO1_IO20 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), MX6_PAD_SD1_CLK__PHY_DTB_0 = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__PWM4_PWMO = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPT_CMPOUT1 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__PWM4_OUT = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPT_COMPARE1 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPIO1_IO18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), MX6_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 = IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__SD1_DATA0 = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS = IOMUX_PAD(0x06CC, 0x02E4, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__GPT_CAPIN1 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__GPT_CAPTURE1 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 = IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__GPIO_1_16 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__GPIO1_IO16 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 = IOMUX_PAD(0x06CC, 0x02E4, 6, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 = IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__PWM3_PWMO = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPT_CAPIN2 = IOMUX_PAD(0x06D0, 0x02E8, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__SD1_DATA1 = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__PWM3_OUT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__GPT_CAPTURE2 = IOMUX_PAD(0x06D0, 0x02E8, 3, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 = IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPIO_1_17 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__GPIO1_IO17 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 = IOMUX_PAD(0x06D0, 0x02E8, 6, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 = IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__GPT_CMPOUT2 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__PWM2_PWMO = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_WDOG_B = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__GPIO_1_19 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__SD1_DATA2 = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__GPT_COMPARE2 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__PWM2_OUT = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__WDOG1_B = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__GPIO1_IO19 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__WDOG1_RESET_B_DEB = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0), MX6_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 = IOMUX_PAD(0x06D4, 0x02EC, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPT_CMPOUT3 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__PWM1_PWMO = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_WDOG_B = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__SD1_DATA3 = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__GPT_COMPARE3 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__PWM1_OUT = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__WDOG2_B = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__GPIO1_IO21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__WDOG2_RESET_B_DEB = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), MX6_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 = IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x06DC, 0x02F4, 0, 0x0930, 1, 0), - MX6_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x08C0, 3, 0), - MX6_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x06DC, 0x02F4, 3, 0x07A4, 1, 0), + MX6_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x06DC, 0x02F4, 0, 0x0930, 1, 0), + MX6_PAD_SD2_CLK__KEY_COL5 = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x08C0, 3, 0), + MX6_PAD_SD2_CLK__AUD4_RXFS = IOMUX_PAD(0x06DC, 0x02F4, 3, 0x07A4, 1, 0), MX6_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 = IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__GPIO_1_10 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__GPIO1_IO10 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), MX6_PAD_SD2_CLK__PHY_DTB_1 = IOMUX_PAD(0x06DC, 0x02F4, 6, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x08CC, 2, 0), - MX6_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x06E0, 0x02F8, 3, 0x07A0, 1, 0), + MX6_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__KEY_ROW5 = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x08CC, 2, 0), + MX6_PAD_SD2_CMD__AUD4_RXC = IOMUX_PAD(0x06E0, 0x02F8, 3, 0x07A0, 1, 0), MX6_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__GPIO_1_11 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0798, 1, 0), - MX6_PAD_SD2_DAT0__KPP_ROW_7 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x08D4, 2, 0), - MX6_PAD_SD2_DAT0__GPIO_1_15 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__DCIC2_DCIC_OUT = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__GPIO1_IO11 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__SD2_DATA0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__AUD4_RXD = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0798, 1, 0), + MX6_PAD_SD2_DAT0__KEY_ROW7 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x08D4, 2, 0), + MX6_PAD_SD2_DAT0__GPIO1_IO15 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__DCIC2_OUT = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 = IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__WEIM_WEIM_CS_2 = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x06E8, 0x0300, 3, 0x07AC, 1, 0), - MX6_PAD_SD2_DAT1__KPP_COL_7 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x08C8, 2, 0), - MX6_PAD_SD2_DAT1__GPIO_1_14 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__SD2_DATA1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__EIM_CS2_B = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__AUD4_TXFS = IOMUX_PAD(0x06E8, 0x0300, 3, 0x07AC, 1, 0), + MX6_PAD_SD2_DAT1__KEY_COL7 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x08C8, 2, 0), + MX6_PAD_SD2_DAT1__GPIO1_IO14 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__CCM_WAIT = IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 = IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__WEIM_WEIM_CS_3 = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__AUDMUX_AUD4_TXD = IOMUX_PAD(0x06EC, 0x0304, 3, 0x079C, 1, 0), - MX6_PAD_SD2_DAT2__KPP_ROW_6 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x08D0, 2, 0), - MX6_PAD_SD2_DAT2__GPIO_1_13 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__SD2_DATA2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__EIM_CS3_B = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__AUD4_TXD = IOMUX_PAD(0x06EC, 0x0304, 3, 0x079C, 1, 0), + MX6_PAD_SD2_DAT2__KEY_ROW6 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x08D0, 2, 0), + MX6_PAD_SD2_DAT2__GPIO1_IO13 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__CCM_STOP = IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 = IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__KPP_COL_6 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x08C4, 2, 0), - MX6_PAD_SD2_DAT3__AUDMUX_AUD4_TXC = IOMUX_PAD(0x06F0, 0x0308, 3, 0x07A8, 1, 0), + MX6_PAD_SD2_DAT3__SD2_DATA3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__KEY_COL6 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x08C4, 2, 0), + MX6_PAD_SD2_DAT3__AUD4_TXC = IOMUX_PAD(0x06F0, 0x0308, 3, 0x07A8, 1, 0), MX6_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 = IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__GPIO_1_12 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__GPIO1_IO12 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__SJC_DONE = IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 = IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0), - MX6_PAD_SD3_CLK__UART2_CTS = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__UART2_RTS = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0900, 2, 0), - MX6_PAD_SD3_CLK__CAN1_RXCAN = IOMUX_PAD(0x06F4, 0x030C, 2, 0x07C8, 2, 0), + MX6_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0), + MX6_PAD_SD3_CLK__UART2_CTS_B = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__UART2_RTS_B = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0900, 2, 0), + MX6_PAD_SD3_CLK__FLEXCAN1_RX = IOMUX_PAD(0x06F4, 0x030C, 2, 0x07C8, 2, 0), MX6_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 = IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0), MX6_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 = IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__GPIO_7_3 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__GPIO7_IO03 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0), MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 = IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0), MX6_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 = IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__UART2_CTS = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__UART2_RTS = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0900, 3, 0), - MX6_PAD_SD3_CMD__CAN1_TXCAN = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__UART2_CTS_B = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__UART2_RTS_B = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0900, 3, 0), + MX6_PAD_SD3_CMD__FLEXCAN1_TX = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0), MX6_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 = IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0), MX6_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 = IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__GPIO_7_2 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__GPIO7_IO02 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0), MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 = IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0), MX6_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 = IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__UART1_CTS = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__UART1_RTS = IOMUX_PAD(0x06FC, 0x0314, 1, 0x08F8, 2, 0), - MX6_PAD_SD3_DAT0__CAN2_TXCAN = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__SD3_DATA0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__UART1_CTS_B = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__UART1_RTS_B = IOMUX_PAD(0x06FC, 0x0314, 1, 0x08F8, 2, 0), + MX6_PAD_SD3_DAT0__FLEXCAN2_TX = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__GPIO_7_4 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__GPIO7_IO04 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 = IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 = IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_CTS = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_RTS = IOMUX_PAD(0x0700, 0x0318, 1, 0x08F8, 3, 0), - MX6_PAD_SD3_DAT1__CAN2_RXCAN = IOMUX_PAD(0x0700, 0x0318, 2, 0x07CC, 1, 0), + MX6_PAD_SD3_DAT1__SD3_DATA1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__UART1_CTS_B = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__UART1_RTS_B = IOMUX_PAD(0x0700, 0x0318, 1, 0x08F8, 3, 0), + MX6_PAD_SD3_DAT1__FLEXCAN2_RX = IOMUX_PAD(0x0700, 0x0318, 2, 0x07CC, 1, 0), MX6_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__GPIO_7_5 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__GPIO7_IO05 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 = IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 = IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__SD3_DATA2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 = IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 = IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__GPIO_7_6 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__GPIO7_IO06 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 = IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 = IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__UART3_CTS = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__UART3_RTS = IOMUX_PAD(0x0708, 0x0320, 1, 0x0908, 4, 0), + MX6_PAD_SD3_DAT3__SD3_DATA3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__UART3_CTS_B = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__UART3_RTS_B = IOMUX_PAD(0x0708, 0x0320, 1, 0x0908, 4, 0), MX6_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 = IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 = IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__GPIO_7_7 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__GPIO7_IO07 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 = IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 = IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__USDHC3_DAT4 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__UART2_TXD = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__UART2_RXD = IOMUX_PAD(0x070C, 0x0324, 1, 0x0904, 4, 0), + MX6_PAD_SD3_DAT4__SD3_DATA4 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT4__UART2_TX_DATA = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT4__UART2_RX_DATA = IOMUX_PAD(0x070C, 0x0324, 1, 0x0904, 4, 0), MX6_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 = IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__GPIO_7_1 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT4__GPIO7_IO01 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 = IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 = IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__USDHC3_DAT5 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_TXD = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_RXD = IOMUX_PAD(0x0710, 0x0328, 1, 0x0904, 5, 0), + MX6_PAD_SD3_DAT5__SD3_DATA5 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__UART2_TX_DATA = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__UART2_RX_DATA = IOMUX_PAD(0x0710, 0x0328, 1, 0x0904, 5, 0), MX6_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 = IOMUX_PAD(0x0710, 0x0328, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 = IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__GPIO7_IO00 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 = IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 = IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__USDHC3_DAT6 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__UART1_TXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0), + MX6_PAD_SD3_DAT6__SD3_DATA6 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT6__UART1_TX_DATA = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT6__UART1_RX_DATA = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0), MX6_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 = IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__GPIO_6_18 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT6__GPIO6_IO18 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 = IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 = IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__USDHC3_DAT7 = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_RXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x08FC, 3, 0), + MX6_PAD_SD3_DAT7__SD3_DATA7 = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__UART1_TX_DATA = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__UART1_RX_DATA = IOMUX_PAD(0x0718, 0x0330, 1, 0x08FC, 3, 0), MX6_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 = IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 = IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__GPIO_6_17 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__GPIO6_IO17 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 = IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV = IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0), - MX6_PAD_SD3_RST__USDHC3_RST = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_CTS = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_RTS = IOMUX_PAD(0x071C, 0x0334, 1, 0x0908, 5, 0), + MX6_PAD_SD3_RST__SD3_RESET = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0), + MX6_PAD_SD3_RST__UART3_CTS_B = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), + MX6_PAD_SD3_RST__UART3_RTS_B = IOMUX_PAD(0x071C, 0x0334, 1, 0x0908, 5, 0), MX6_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 = IOMUX_PAD(0x071C, 0x0334, 2, 0x0000, 0, 0), MX6_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 = IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0), MX6_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 = IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0), - MX6_PAD_SD3_RST__GPIO_7_8 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), + MX6_PAD_SD3_RST__GPIO7_IO08 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), MX6_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 = IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0), MX6_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 = IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0), - MX6_PAD_SD4_CLK__RAWNAND_WRN = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__UART3_TXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__UART3_RXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x090C, 2, 0), + MX6_PAD_SD4_CLK__SD4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0), + MX6_PAD_SD4_CLK__NAND_WE_B = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__UART3_TX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__UART3_RX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x090C, 2, 0), MX6_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__GPIO_7_10 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__RAWNAND_RDN = IOMUX_PAD(0x0724, 0x033C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_TXD = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_RXD = IOMUX_PAD(0x0724, 0x033C, 2, 0x090C, 3, 0), + MX6_PAD_SD4_CLK__GPIO7_IO10 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__SD4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__NAND_RE_B = IOMUX_PAD(0x0724, 0x033C, 1, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__UART3_TX_DATA = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__UART3_RX_DATA = IOMUX_PAD(0x0724, 0x033C, 2, 0x090C, 3, 0), MX6_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 = IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__GPIO_7_9 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__GPIO7_IO09 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__RAWNAND_D8 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__RAWNAND_DQS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__SD4_DATA0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__NAND_DQS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__GPIO_2_8 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__GPIO2_IO08 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__RAWNAND_D9 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__PWM3_PWMO = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__SD4_DATA1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__PWM3_OUT = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 = IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__GPIO_2_9 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__GPIO2_IO09 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__RAWNAND_D10 = IOMUX_PAD(0x0730, 0x0348, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__PWM4_PWMO = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__SD4_DATA2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__PWM4_OUT = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 = IOMUX_PAD(0x0730, 0x0348, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__GPIO_2_10 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__GPIO2_IO10 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 = IOMUX_PAD(0x0730, 0x0348, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__RAWNAND_D11 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT3__SD4_DATA3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 = IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__GPIO_2_11 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT3__GPIO2_IO11 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__RAWNAND_D12 = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__USDHC4_DAT4 = IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__UART2_TXD = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__UART2_RXD = IOMUX_PAD(0x0738, 0x0350, 2, 0x0904, 6, 0), + MX6_PAD_SD4_DAT4__SD4_DATA4 = IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT4__UART2_TX_DATA = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT4__UART2_RX_DATA = IOMUX_PAD(0x0738, 0x0350, 2, 0x0904, 6, 0), MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 = IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 = IOMUX_PAD(0x0738, 0x0350, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__GPIO_2_12 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT4__GPIO2_IO12 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__RAWNAND_D13 = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__USDHC4_DAT5 = IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_CTS = IOMUX_PAD(0x073C, 0x0354, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_RTS = IOMUX_PAD(0x073C, 0x0354, 2, 0x0900, 4, 0), + MX6_PAD_SD4_DAT5__SD4_DATA5 = IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__UART2_CTS_B = IOMUX_PAD(0x073C, 0x0354, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__UART2_RTS_B = IOMUX_PAD(0x073C, 0x0354, 2, 0x0900, 4, 0), MX6_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 = IOMUX_PAD(0x073C, 0x0354, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 = IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__GPIO_2_13 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__GPIO2_IO13 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 = IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__RAWNAND_D14 = IOMUX_PAD(0x0740, 0x0358, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__USDHC4_DAT6 = IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__UART2_CTS = IOMUX_PAD(0x0740, 0x0358, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__UART2_RTS = IOMUX_PAD(0x0740, 0x0358, 2, 0x0900, 5, 0), + MX6_PAD_SD4_DAT6__SD4_DATA6 = IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT6__UART2_CTS_B = IOMUX_PAD(0x0740, 0x0358, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT6__UART2_RTS_B = IOMUX_PAD(0x0740, 0x0358, 2, 0x0900, 5, 0), MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 = IOMUX_PAD(0x0740, 0x0358, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 = IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__GPIO_2_14 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT6__GPIO2_IO14 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 = IOMUX_PAD(0x0740, 0x0358, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__RAWNAND_D15 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__USDHC4_DAT7 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_TXD = IOMUX_PAD(0x0744, 0x035C, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_RXD = IOMUX_PAD(0x0744, 0x035C, 2, 0x0904, 7, 0), + MX6_PAD_SD4_DAT7__SD4_DATA7 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__UART2_TX_DATA = IOMUX_PAD(0x0744, 0x035C, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__UART2_RX_DATA = IOMUX_PAD(0x0744, 0x035C, 2, 0x0904, 7, 0), MX6_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 = IOMUX_PAD(0x0744, 0x035C, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 = IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__GPIO_2_15 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__GPIO2_IO15 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0), }; #endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h index fe9a8c343d5..a85a5fd9c98 100644 --- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h @@ -12,772 +12,772 @@ #include enum { - MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__SD2_DATA1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0), - MX6_PAD_SD2_DAT1__WEIM_WEIM_CS_2 = IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0), - MX6_PAD_SD2_DAT1__KPP_COL_7 = IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0), - MX6_PAD_SD2_DAT1__GPIO_1_14 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__EIM_CS2_B = IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__AUD4_TXFS = IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0), + MX6_PAD_SD2_DAT1__KEY_COL7 = IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0), + MX6_PAD_SD2_DAT1__GPIO1_IO14 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__CCM_WAIT = IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__ANATOP_TESTO_0 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__SD2_DATA2 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0), - MX6_PAD_SD2_DAT2__WEIM_WEIM_CS_3 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__AUDMUX_AUD4_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0), - MX6_PAD_SD2_DAT2__KPP_ROW_6 = IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0), - MX6_PAD_SD2_DAT2__GPIO_1_13 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__EIM_CS3_B = IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__AUD4_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0), + MX6_PAD_SD2_DAT2__KEY_ROW6 = IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0), + MX6_PAD_SD2_DAT2__GPIO1_IO13 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__CCM_STOP = IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__ANATOP_TESTO_1 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__SD2_DATA0 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0), - MX6_PAD_SD2_DAT0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0), - MX6_PAD_SD2_DAT0__KPP_ROW_7 = IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0), - MX6_PAD_SD2_DAT0__GPIO_1_15 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__DCIC2_DCIC_OUT = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__AUD4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0), + MX6_PAD_SD2_DAT0__KEY_ROW7 = IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0), + MX6_PAD_SD2_DAT0__GPIO1_IO15 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__DCIC2_OUT = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__TESTO_2 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__USBOH3_H2_DATA = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0), - MX6_PAD_RGMII_TXC__GPIO_6_19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__USB_H2_DATA = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__RGMII_TXC = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__SPDIF_EXT_CLK = IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0), + MX6_PAD_RGMII_TXC__GPIO6_IO19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__ANATOP_24M_OUT = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__GPIO_6_20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__HSI_TX_READY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__GPIO6_IO20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__GPIO_6_21 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__HSI_RX_FLAG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__GPIO6_IO21 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0), MX6_PAD_RGMII_TD1__CCM_PLL3_BYP = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__GPIO_6_22 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__HSI_RX_DATA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__GPIO6_IO22 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0), MX6_PAD_RGMII_TD2__CCM_PLL2_BYP = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__GPIO_6_23 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__HSI_RX_WAKE = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__GPIO6_IO23 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__USBOH3_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RX_CTL__USB_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0), - MX6_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0), - MX6_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD0__HSI_RX_READY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD0__RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0), + MX6_PAD_RGMII_RD0__GPIO6_IO25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TX_CTL__USB_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__GPIO_6_26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TX_CTL__GPIO6_IO26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__ANATOP_REF_OUT = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0), - MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0), - MX6_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TX_CTL__ENET_REF_CLK = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0), + MX6_PAD_RGMII_RD1__HSI_TX_FLAG = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD1__RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0), + MX6_PAD_RGMII_RD1__GPIO6_IO27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0), MX6_PAD_RGMII_RD1__SJC_FAIL = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0), - MX6_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD2__HSI_TX_DATA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD2__RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0), + MX6_PAD_RGMII_RD2__GPIO6_IO28 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0), - MX6_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD3__HSI_TX_WAKE = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD3__RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0), + MX6_PAD_RGMII_RD3__GPIO6_IO29 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0), - MX6_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RXC__USB_H3_STROBE = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RXC__RGMII_RXC = IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0), + MX6_PAD_RGMII_RXC__GPIO6_IO30 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A25__WEIM_WEIM_A_25 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A25__EIM_ADDR25 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), MX6_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), MX6_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0), MX6_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0), MX6_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A25__GPIO_5_2 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A25__GPIO5_IO02 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0), MX6_PAD_EIM_A25__PL301_PER1_HBURST_0 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__WEIM_WEIM_EB_2 = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB2__EIM_EB2_B = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0), MX6_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0), - MX6_PAD_EIM_EB2__IPU2_CSI1_D_19 = IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0), + MX6_PAD_EIM_EB2__IPU2_CSI1_DATA19 = IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0), MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0), - MX6_PAD_EIM_EB2__GPIO_2_30 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB2__GPIO2_IO30 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), MX6_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x03A0, 0x008C, 22, 0x08A0, 0, 0), - MX6_PAD_EIM_EB2__SRC_BT_CFG_30 = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D16__WEIM_WEIM_D_16 = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB2__SRC_BOOT_CFG30 = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D16__EIM_DATA16 = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0), MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0), - MX6_PAD_EIM_D16__IPU1_DI0_PIN5 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D16__IPU2_CSI1_D_18 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0), + MX6_PAD_EIM_D16__IPU1_DI0_PIN05 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D16__IPU2_CSI1_DATA18 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0), MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0), - MX6_PAD_EIM_D16__GPIO_3_16 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D16__GPIO3_IO16 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), MX6_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0090, 22, 0x08A4, 0, 0), - MX6_PAD_EIM_D17__WEIM_WEIM_D_17 = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D17__EIM_DATA17 = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0), MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0), - MX6_PAD_EIM_D17__IPU1_DI0_PIN6 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D17__IPU1_DI0_PIN06 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0), MX6_PAD_EIM_D17__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0), - MX6_PAD_EIM_D17__DCIC1_DCIC_OUT = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D17__GPIO_3_17 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D17__DCIC1_OUT = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D17__GPIO3_IO17 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), MX6_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x03A8, 0x0094, 22, 0x08A8, 0, 0), MX6_PAD_EIM_D17__PL301_PER1_HBURST_1 = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D18__WEIM_WEIM_D_18 = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D18__EIM_DATA18 = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0), - MX6_PAD_EIM_D18__IPU1_DI0_PIN7 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D18__IPU2_CSI1_D_17 = IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0), + MX6_PAD_EIM_D18__IPU1_DI0_PIN07 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D18__IPU2_CSI1_DATA17 = IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0), MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D18__GPIO_3_18 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D18__GPIO3_IO18 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), MX6_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x03AC, 0x0098, 22, 0x08AC, 0, 0), MX6_PAD_EIM_D18__PL301_PER1_HBURST_2 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D19__WEIM_WEIM_D_19 = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D19__EIM_DATA19 = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0), MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0), - MX6_PAD_EIM_D19__IPU1_DI0_PIN8 = IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D19__IPU2_CSI1_D_16 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0), - MX6_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0), - MX6_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D19__IPU1_DI0_PIN08 = IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D19__IPU2_CSI1_DATA16 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0), + MX6_PAD_EIM_D19__UART1_RTS_B = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0), + MX6_PAD_EIM_D19__GPIO3_IO19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D19__EPIT1_OUT = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0), MX6_PAD_EIM_D19__PL301MX6QPER1_HRESP = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D20__WEIM_WEIM_D_20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D20__EIM_DATA20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0), MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0), MX6_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0), - MX6_PAD_EIM_D20__UART1_CTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D20__UART1_RTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0), - MX6_PAD_EIM_D20__GPIO_3_20 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D20__EPIT2_EPITO = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D21__WEIM_WEIM_D_21 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D20__IPU2_CSI1_DATA15 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0), + MX6_PAD_EIM_D20__UART1_CTS_B = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D20__UART1_RTS_B = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0), + MX6_PAD_EIM_D20__GPIO3_IO20 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D20__EPIT2_OUT = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D21__EIM_DATA21 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0), MX6_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0), MX6_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D21__IPU2_CSI1_D_11 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0), - MX6_PAD_EIM_D21__USBOH3_USBOTG_OC = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0), - MX6_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D21__IPU2_CSI1_DATA11 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0), + MX6_PAD_EIM_D21__USB_OTG_OC = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0), + MX6_PAD_EIM_D21__GPIO3_IO21 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x03B8, 0x00A4, 22, 0x0898, 0, 0), - MX6_PAD_EIM_D21__SPDIF_IN1 = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0), - MX6_PAD_EIM_D22__WEIM_WEIM_D_22 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D21__SPDIF_IN = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0), + MX6_PAD_EIM_D22__EIM_DATA22 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0), MX6_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU1_DI0_PIN1 = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU2_CSI1_D_10 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0), - MX6_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D22__GPIO_3_22 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D22__SPDIF_OUT1 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D22__IPU1_DI0_PIN01 = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D22__IPU2_CSI1_DATA10 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0), + MX6_PAD_EIM_D22__USB_OTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D22__GPIO3_IO22 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D22__SPDIF_OUT = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), MX6_PAD_EIM_D22__PL301MX6QPER1_HWRITE = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D23__WEIM_WEIM_D_23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D23__EIM_DATA23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0), - MX6_PAD_EIM_D23__UART1_DCD = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D23__UART3_RTS_B = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0), + MX6_PAD_EIM_D23__UART1_DCD_B = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0), MX6_PAD_EIM_D23__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0), - MX6_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI1_PIN2 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D23__GPIO3_IO23 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D23__IPU1_DI1_PIN02 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0), MX6_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__WEIM_WEIM_EB_3 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__EIM_EB3_B = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB3__ECSPI4_RDY = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_CTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_RTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0), - MX6_PAD_EIM_EB3__UART1_RI = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__UART3_CTS_B = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__UART3_RTS_B = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0), + MX6_PAD_EIM_EB3__UART1_RI_B = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0), MX6_PAD_EIM_EB3__IPU2_CSI1_HSYNC = IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0), - MX6_PAD_EIM_EB3__GPIO_2_31 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__IPU1_DI1_PIN3 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__SRC_BT_CFG_31 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D24__WEIM_WEIM_D_24 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__GPIO2_IO31 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__IPU1_DI1_PIN03 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__SRC_BOOT_CFG31 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D24__EIM_DATA24 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0), MX6_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_TXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_TXD_RXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0), + MX6_PAD_EIM_D24__UART3_TX_DATA = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D24__UART3_RX_DATA = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0), MX6_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0), MX6_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D24__GPIO_3_24 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D24__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0), - MX6_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D25__WEIM_WEIM_D_25 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D24__GPIO3_IO24 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D24__AUD5_RXFS = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0), + MX6_PAD_EIM_D24__UART1_DTR_B = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D25__EIM_DATA25 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), MX6_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0), + MX6_PAD_EIM_D25__UART3_RX_DATA = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0), MX6_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0), MX6_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D25__GPIO_3_25 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D25__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0), - MX6_PAD_EIM_D25__UART1_DSR = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D26__WEIM_WEIM_D_26 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D25__GPIO3_IO25 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D25__AUD5_RXC = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0), + MX6_PAD_EIM_D25__UART1_DSR_B = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D26__EIM_DATA26 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0), MX6_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_CSI0_D_1 = IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU2_CSI1_D_14 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0), - MX6_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D26__UART2_TXD_RXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0), - MX6_PAD_EIM_D26__GPIO_3_26 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_SISG_2 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_DISP1_DAT_22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D27__WEIM_WEIM_D_27 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_CSI0_DATA01 = IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU2_CSI1_DATA14 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0), + MX6_PAD_EIM_D26__UART2_TX_DATA = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D26__UART2_RX_DATA = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0), + MX6_PAD_EIM_D26__GPIO3_IO26 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_SISG2 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D27__EIM_DATA27 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0), MX6_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_CSI0_D_0 = IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU2_CSI1_D_13 = IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0), - MX6_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0), - MX6_PAD_EIM_D27__GPIO_3_27 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_SISG_3 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_DISP1_DAT_23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D28__WEIM_WEIM_D_28 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_CSI0_DATA00 = IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU2_CSI1_DATA13 = IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0), + MX6_PAD_EIM_D27__UART2_RX_DATA = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0), + MX6_PAD_EIM_D27__GPIO3_IO27 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_SISG3 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D28__EIM_DATA28 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0), MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x03D8, 0x00C4, 17, 0x089C, 0, 0), MX6_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU2_CSI1_D_12 = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0), - MX6_PAD_EIM_D28__UART2_CTS = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0), - MX6_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D28__IPU2_CSI1_DATA12 = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0), + MX6_PAD_EIM_D28__UART2_DTE_CTS_B = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0), + MX6_PAD_EIM_D28__GPIO3_IO28 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), MX6_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0), MX6_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D29__WEIM_WEIM_D_29 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D29__EIM_DATA29 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0), MX6_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), MX6_PAD_EIM_D29__ECSPI4_SS0 = IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0), - MX6_PAD_EIM_D29__UART2_CTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D29__UART2_RTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0), - MX6_PAD_EIM_D29__GPIO_3_29 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D29__UART2_CTS_B = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D29__UART2_RTS_B = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0), + MX6_PAD_EIM_D29__GPIO3_IO29 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), MX6_PAD_EIM_D29__IPU2_CSI1_VSYNC = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0), MX6_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D30__WEIM_WEIM_D_30 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_DISP1_DAT_21 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D30__EIM_DATA30 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), MX6_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_CSI0_D_3 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0), - MX6_PAD_EIM_D30__GPIO_3_30 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0), + MX6_PAD_EIM_D30__IPU1_CSI0_DATA03 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D30__UART3_RTS_B = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0), + MX6_PAD_EIM_D30__GPIO3_IO30 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D30__USB_H1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0), MX6_PAD_EIM_D30__PL301MX6QPER1_HPROT_0 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D31__WEIM_WEIM_D_31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D31__EIM_DATA31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), MX6_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_CSI0_D_2 = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_CTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0), - MX6_PAD_EIM_D31__GPIO_3_31 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D31__IPU1_CSI0_DATA02 = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D31__UART3_CTS_B = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D31__UART3_RTS_B = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0), + MX6_PAD_EIM_D31__GPIO3_IO31 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D31__USB_H1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0), MX6_PAD_EIM_D31__PL301MX6QPER1_HPROT_1 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A24__WEIM_WEIM_A_24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_DISP1_DAT_19 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU2_CSI1_D_19 = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0), - MX6_PAD_EIM_A24__IPU2_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A24__GPIO_5_4 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A24__EIM_ADDR24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A24__IPU2_CSI1_DATA19 = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0), + MX6_PAD_EIM_A24__IPU2_SISG2 = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0), + MX6_PAD_EIM_A24__IPU1_SISG2 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0), + MX6_PAD_EIM_A24__GPIO5_IO04 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), MX6_PAD_EIM_A24__PL301MX6QPER1_HPROT_2 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A24__SRC_BT_CFG_24 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A23__WEIM_WEIM_A_23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_DISP1_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU2_CSI1_D_18 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0), - MX6_PAD_EIM_A23__IPU2_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A23__GPIO_6_6 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A24__SRC_BOOT_CFG24 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A23__EIM_ADDR23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A23__IPU2_CSI1_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0), + MX6_PAD_EIM_A23__IPU2_SISG3 = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0), + MX6_PAD_EIM_A23__IPU1_SISG3 = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0), + MX6_PAD_EIM_A23__GPIO6_IO06 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), MX6_PAD_EIM_A23__PL301MX6QPER1_HPROT_3 = IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A23__SRC_BT_CFG_23 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A22__WEIM_WEIM_A_22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU1_DISP1_DAT_17 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU2_CSI1_D_17 = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0), - MX6_PAD_EIM_A22__GPIO_2_16 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A23__SRC_BOOT_CFG23 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A22__EIM_ADDR22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A22__IPU2_CSI1_DATA17 = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0), + MX6_PAD_EIM_A22__GPIO2_IO16 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), MX6_PAD_EIM_A22__TPSMP_HDATA_0 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A22__SRC_BT_CFG_22 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A21__WEIM_WEIM_A_21 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU1_DISP1_DAT_16 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU2_CSI1_D_16 = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0), + MX6_PAD_EIM_A22__SRC_BOOT_CFG22 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A21__EIM_ADDR21 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A21__IPU2_CSI1_DATA16 = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0), MX6_PAD_EIM_A21__RESERVED_RESERVED = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0), MX6_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A21__GPIO_2_17 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A21__GPIO2_IO17 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), MX6_PAD_EIM_A21__TPSMP_HDATA_1 = IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A21__SRC_BT_CFG_21 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A20__WEIM_WEIM_A_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU1_DISP1_DAT_15 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0), + MX6_PAD_EIM_A21__SRC_BOOT_CFG21 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A20__EIM_ADDR20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A20__IPU2_CSI1_DATA15 = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0), MX6_PAD_EIM_A20__RESERVED_RESERVED = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0), MX6_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A20__GPIO_2_18 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A20__GPIO2_IO18 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), MX6_PAD_EIM_A20__TPSMP_HDATA_2 = IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A20__SRC_BT_CFG_20 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A19__WEIM_WEIM_A_19 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU1_DISP1_DAT_14 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU2_CSI1_D_14 = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0), + MX6_PAD_EIM_A20__SRC_BOOT_CFG20 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A19__EIM_ADDR19 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A19__IPU2_CSI1_DATA14 = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0), MX6_PAD_EIM_A19__RESERVED_RESERVED = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0), MX6_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A19__GPIO_2_19 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A19__GPIO2_IO19 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), MX6_PAD_EIM_A19__TPSMP_HDATA_3 = IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A19__SRC_BT_CFG_19 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A18__WEIM_WEIM_A_18 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU1_DISP1_DAT_13 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU2_CSI1_D_13 = IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0), + MX6_PAD_EIM_A19__SRC_BOOT_CFG19 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A18__EIM_ADDR18 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A18__IPU2_CSI1_DATA13 = IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0), MX6_PAD_EIM_A18__RESERVED_RESERVED = IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0), MX6_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A18__GPIO_2_20 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A18__GPIO2_IO20 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), MX6_PAD_EIM_A18__TPSMP_HDATA_4 = IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A18__SRC_BT_CFG_18 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A17__WEIM_WEIM_A_17 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU1_DISP1_DAT_12 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU2_CSI1_D_12 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0), + MX6_PAD_EIM_A18__SRC_BOOT_CFG18 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A17__EIM_ADDR17 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A17__IPU2_CSI1_DATA12 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0), MX6_PAD_EIM_A17__RESERVED_RESERVED = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0), MX6_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A17__GPIO_2_21 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A17__GPIO2_IO21 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), MX6_PAD_EIM_A17__TPSMP_HDATA_5 = IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A17__SRC_BT_CFG_17 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A16__WEIM_WEIM_A_16 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A17__SRC_BOOT_CFG17 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A16__EIM_ADDR16 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0), MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0), MX6_PAD_EIM_A16__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0), MX6_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A16__GPIO_2_22 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A16__GPIO2_IO22 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), MX6_PAD_EIM_A16__TPSMP_HDATA_6 = IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A16__SRC_BT_CFG_16 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__WEIM_WEIM_CS_0 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__IPU1_DI1_PIN5 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A16__SRC_BOOT_CFG16 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__EIM_CS0_B = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__IPU1_DI1_PIN05 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), MX6_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0), MX6_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__GPIO_2_23 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__GPIO2_IO23 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), MX6_PAD_EIM_CS0__TPSMP_HDATA_7 = IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__WEIM_WEIM_CS_1 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__IPU1_DI1_PIN6 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__EIM_CS1_B = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__IPU1_DI1_PIN06 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), MX6_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0), MX6_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__GPIO_2_24 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__GPIO2_IO24 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), MX6_PAD_EIM_CS1__TPSMP_HDATA_8 = IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_OE__WEIM_WEIM_OE = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0), - MX6_PAD_EIM_OE__IPU1_DI1_PIN7 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), + MX6_PAD_EIM_OE__EIM_OE_B = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0), + MX6_PAD_EIM_OE__IPU1_DI1_PIN07 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), MX6_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0), MX6_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0), - MX6_PAD_EIM_OE__GPIO_2_25 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), + MX6_PAD_EIM_OE__GPIO2_IO25 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), MX6_PAD_EIM_OE__TPSMP_HDATA_9 = IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0), - MX6_PAD_EIM_RW__WEIM_WEIM_RW = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0), - MX6_PAD_EIM_RW__IPU1_DI1_PIN8 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), + MX6_PAD_EIM_RW__EIM_RW = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0), + MX6_PAD_EIM_RW__IPU1_DI1_PIN08 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), MX6_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0), MX6_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0), - MX6_PAD_EIM_RW__GPIO_2_26 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), + MX6_PAD_EIM_RW__GPIO2_IO26 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), MX6_PAD_EIM_RW__TPSMP_HDATA_10 = IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0), - MX6_PAD_EIM_RW__SRC_BT_CFG_29 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__WEIM_WEIM_LBA = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0), + MX6_PAD_EIM_RW__SRC_BOOT_CFG29 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0), + MX6_PAD_EIM_LBA__EIM_LBA_B = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0), MX6_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), MX6_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0), - MX6_PAD_EIM_LBA__GPIO_2_27 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), + MX6_PAD_EIM_LBA__GPIO2_IO27 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), MX6_PAD_EIM_LBA__TPSMP_HDATA_11 = IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__SRC_BT_CFG_26 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__WEIM_WEIM_EB_0 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU1_DISP1_DAT_11 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU2_CSI1_D_11 = IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0), + MX6_PAD_EIM_LBA__SRC_BOOT_CFG26 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__EIM_EB0_B = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__IPU2_CSI1_DATA11 = IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0), MX6_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__CCM_PMIC_RDY = IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0), - MX6_PAD_EIM_EB0__GPIO_2_28 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__CCM_PMIC_READY = IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0), + MX6_PAD_EIM_EB0__GPIO2_IO28 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), MX6_PAD_EIM_EB0__TPSMP_HDATA_12 = IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__SRC_BT_CFG_27 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__WEIM_WEIM_EB_1 = IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU1_DISP1_DAT_10 = IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU2_CSI1_D_10 = IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0), + MX6_PAD_EIM_EB0__SRC_BOOT_CFG27 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__EIM_EB1_B = IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 = IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__IPU2_CSI1_DATA10 = IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0), MX6_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 = IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__GPIO_2_29 = IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__GPIO2_IO29 = IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0), MX6_PAD_EIM_EB1__TPSMP_HDATA_13 = IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__SRC_BT_CFG_28 = IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 = IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU1_DISP1_DAT_9 = IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU2_CSI1_D_9 = IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__SRC_BOOT_CFG28 = IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__EIM_AD00 = IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 = IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__IPU2_CSI1_DATA09 = IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 = IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__GPIO_3_0 = IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__GPIO3_IO00 = IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA0__TPSMP_HDATA_14 = IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__SRC_BT_CFG_0 = IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 = IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU1_DISP1_DAT_8 = IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU2_CSI1_D_8 = IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__SRC_BOOT_CFG00 = IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__EIM_AD01 = IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 = IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__IPU2_CSI1_DATA08 = IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 = IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA1__USBPHY1_TX_LS_MODE = IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__GPIO_3_1 = IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__GPIO3_IO01 = IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA1__TPSMP_HDATA_15 = IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__SRC_BT_CFG_1 = IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 = IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU1_DISP1_DAT_7 = IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU2_CSI1_D_7 = IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__SRC_BOOT_CFG01 = IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__EIM_AD02 = IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 = IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__IPU2_CSI1_DATA07 = IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 = IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA2__USBPHY1_TX_HS_MODE = IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__GPIO_3_2 = IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__GPIO3_IO02 = IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA2__TPSMP_HDATA_16 = IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__SRC_BT_CFG_2 = IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 = IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU1_DISP1_DAT_6 = IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU2_CSI1_D_6 = IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__SRC_BOOT_CFG02 = IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__EIM_AD03 = IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 = IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__IPU2_CSI1_DATA06 = IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 = IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA3__USBPHY1_TX_HIZ = IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__GPIO_3_3 = IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__GPIO3_IO03 = IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA3__TPSMP_HDATA_17 = IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__SRC_BT_CFG_3 = IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 = IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU1_DISP1_DAT_5 = IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU2_CSI1_D_5 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__SRC_BOOT_CFG03 = IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__EIM_AD04 = IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 = IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__IPU2_CSI1_DATA05 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 = IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN = IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__GPIO_3_4 = IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__GPIO3_IO04 = IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA4__TPSMP_HDATA_18 = IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__SRC_BT_CFG_4 = IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 = IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU1_DISP1_DAT_4 = IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU2_CSI1_D_4 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__SRC_BOOT_CFG04 = IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__EIM_AD05 = IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 = IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__IPU2_CSI1_DATA04 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 = IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP = IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__GPIO_3_5 = IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__GPIO3_IO05 = IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA5__TPSMP_HDATA_19 = IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__SRC_BT_CFG_5 = IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 = IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU1_DISP1_DAT_3 = IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU2_CSI1_D_3 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__SRC_BOOT_CFG05 = IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__EIM_AD06 = IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 = IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__IPU2_CSI1_DATA03 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 = IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN = IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__GPIO_3_6 = IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__GPIO3_IO06 = IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA6__TPSMP_HDATA_20 = IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__SRC_BT_CFG_6 = IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 = IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU1_DISP1_DAT_2 = IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU2_CSI1_D_2 = IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__SRC_BOOT_CFG06 = IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__EIM_AD07 = IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 = IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__IPU2_CSI1_DATA02 = IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 = IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__GPIO_3_7 = IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__GPIO3_IO07 = IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA7__TPSMP_HDATA_21 = IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__SRC_BT_CFG_7 = IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 = IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU1_DISP1_DAT_1 = IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU2_CSI1_D_1 = IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__SRC_BOOT_CFG07 = IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__EIM_AD08 = IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 = IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__IPU2_CSI1_DATA01 = IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 = IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__GPIO_3_8 = IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__GPIO3_IO08 = IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA8__TPSMP_HDATA_22 = IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__SRC_BT_CFG_8 = IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 = IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU1_DISP1_DAT_0 = IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU2_CSI1_D_0 = IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__SRC_BOOT_CFG08 = IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__EIM_AD09 = IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 = IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__IPU2_CSI1_DATA00 = IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 = IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__GPIO_3_9 = IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__GPIO3_IO09 = IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA9__TPSMP_HDATA_23 = IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__SRC_BT_CFG_9 = IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 = IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__SRC_BOOT_CFG09 = IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__EIM_AD10 = IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA10__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0), MX6_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 = IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__GPIO_3_10 = IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__GPIO3_IO10 = IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA10__TPSMP_HDATA_24 = IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__SRC_BT_CFG_10 = IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 = IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__IPU1_DI1_PIN2 = IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__EIM_AD11 = IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 = IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA11__IPU2_CSI1_HSYNC = IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0), MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 = IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 = IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__GPIO_3_11 = IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__GPIO3_IO11 = IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA11__TPSMP_HDATA_25 = IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__SRC_BT_CFG_11 = IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 = IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__IPU1_DI1_PIN3 = IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__EIM_AD12 = IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 = IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA12__IPU2_CSI1_VSYNC = IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0), MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 = IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 = IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__GPIO_3_12 = IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__GPIO3_IO12 = IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA12__TPSMP_HDATA_26 = IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__SRC_BT_CFG_12 = IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 = IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__EIM_AD13 = IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0), MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 = IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 = IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__GPIO_3_13 = IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__GPIO3_IO13 = IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA13__TPSMP_HDATA_27 = IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__SRC_BT_CFG_13 = IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 = IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__EIM_AD14 = IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 = IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 = IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__GPIO_3_14 = IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__GPIO3_IO14 = IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA14__TPSMP_HDATA_28 = IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__SRC_BT_CFG_14 = IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 = IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN1 = IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN4 = IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__EIM_AD15 = IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__IPU1_DI1_PIN01 = IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__IPU1_DI1_PIN04 = IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 = IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__GPIO_3_15 = IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__GPIO3_IO15 = IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA15__TPSMP_HDATA_29 = IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__SRC_BT_CFG_15 = IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__WEIM_WEIM_WAIT = IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B = IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__GPIO_5_0 = IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__EIM_WAIT_B = IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__EIM_DTACK_B = IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__GPIO5_IO00 = IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0), MX6_PAD_EIM_WAIT__TPSMP_HDATA_30 = IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__SRC_BT_CFG_25 = IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__WEIM_WEIM_BCLK = IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__SRC_BOOT_CFG25 = IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0), + MX6_PAD_EIM_BCLK__EIM_BCLK = IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__GPIO_6_31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0), + MX6_PAD_EIM_BCLK__GPIO6_IO31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0), + MX6_PAD_DI0_DISP_CLK__GPIO4_IO16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__GPIO4_IO17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN2__IPU2_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN2__IPU2_DI0_PIN02 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 = IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__GPIO4_IO18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__MMDC_DEBUG_2 = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__PL301_PER1_HADDR_9 = IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN3__IPU2_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN3__IPU2_DI0_PIN03 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 = IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__GPIO_4_19 = IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__GPIO4_IO19 = IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__PL301_PER1_HADDR_10 = IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU2_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0), + MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 = IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__IPU2_DI0_PIN04 = IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__SD1_WP = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0), MX6_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN4__GPIO4_IO20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__PL301_PER1_HADDR_11 = IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN = IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT0__GPIO4_IO21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL = IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT1__GPIO4_IO22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__GPIO4_IO23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__MMDC_DEBUG_7 = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR = IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT3__GPIO4_IO24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 = IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT4__GPIO4_IO25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__PL301_PER1_HADR_15 = IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS = IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__GPIO4_IO26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__MMDC_DEBUG_10 = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT = IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__GPIO4_IO27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__MMDC_DEBUG_11 = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 = IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT7__GPIO4_IO28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__PWM1_OUT = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__WDOG1_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 = IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__GPIO4_IO29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__MMDC_DEBUG_13 = IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__PWM2_OUT = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__WDOG2_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 = IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__GPIO4_IO30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__MMDC_DEBUG_14 = IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__USDHC1_DBG_6 = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT10__GPIO4_IO31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT11__GPIO5_IO05 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__RESERVED_RESERVED = IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT12__GPIO5_IO06 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__MMDC_DEBUG_17 = IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0), + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT13__AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0), MX6_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT13__GPIO5_IO07 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT13__MMDC_DEBUG_18 = IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0), + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT14__AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0), MX6_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT14__GPIO5_IO08 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT14__MMDC_DEBUG_19 = IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0), MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0), MX6_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 = IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT15__GPIO5_IO09 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__MMDC_DEBUG_20 = IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0), - MX6_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0), - MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0), - MX6_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT16__AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0), + MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0), + MX6_PAD_DISP0_DAT16__GPIO5_IO10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__MMDC_DEBUG_21 = IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0), - MX6_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0), - MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0), - MX6_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT17__AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0), + MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0), + MX6_PAD_DISP0_DAT17__GPIO5_IO11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__MMDC_DEBUG_22 = IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__PL301_PER1_HADR27 = IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0), - MX6_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0), - MX6_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0), - MX6_PAD_DISP0_DAT18__GPIO_5_12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT18__AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0), + MX6_PAD_DISP0_DAT18__AUD4_RXFS = IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0), + MX6_PAD_DISP0_DAT18__GPIO5_IO12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT18__MMDC_DEBUG_23 = IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT18__EIM_CS2_B = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0), - MX6_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0), - MX6_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0), - MX6_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT19__AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0), + MX6_PAD_DISP0_DAT19__AUD4_RXC = IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0), + MX6_PAD_DISP0_DAT19__GPIO5_IO13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__MMDC_DEBUG_24 = IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT19__EIM_CS3_B = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0), - MX6_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0), + MX6_PAD_DISP0_DAT20__AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0), MX6_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 = IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT20__GPIO5_IO14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__MMDC_DEBUG_25 = IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0), - MX6_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0), + MX6_PAD_DISP0_DAT21__AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0), MX6_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 = IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT21__GPIO5_IO15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__MMDC_DEBUG_26 = IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0), - MX6_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0), + MX6_PAD_DISP0_DAT22__AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0), MX6_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 = IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT22__GPIO5_IO16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__MMDC_DEBUG_27 = IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0), - MX6_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0), + MX6_PAD_DISP0_DAT23__AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0), MX6_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 = IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT23__GPIO5_IO17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__MMDC_DEBUG_28 = IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__PL301_PER1_HADR31 = IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0), MX6_PAD_ENET_MDIO__RESERVED_RESERVED = IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0), MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0), - MX6_PAD_ENET_MDIO__ESAI1_SCKR = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0), + MX6_PAD_ENET_MDIO__ESAI_RX_CLK = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0), MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 = IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__ENET_1588_EVT1_OUT = IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__GPIO_1_22 = IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__SPDIF_PLOCK = IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0), + MX6_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0), + MX6_PAD_ENET_MDIO__GPIO1_IO22 = IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0), + MX6_PAD_ENET_MDIO__SPDIF_LOCK = IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__RESERVED_RSRVED = IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0), + MX6_PAD_ENET_REF_CLK__ESAI_RX_FS = IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0), MX6_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 = IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__GPIO_1_23 = IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__SPDIF_SRCLK = IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0), + MX6_PAD_ENET_REF_CLK__GPIO1_IO23 = IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0), + MX6_PAD_ENET_REF_CLK__SPDIF_SR_CLK = IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__USBPHY1_RX_SQH = IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0), - MX6_PAD_ENET_RX_ER__SPDIF_IN1 = IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0), - MX6_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT = IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__GPIO_1_24 = IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0), + MX6_PAD_ENET_RX_ER__ESAI_RX_HF_CLK = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0), + MX6_PAD_ENET_RX_ER__SPDIF_IN = IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0), + MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT = IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0), + MX6_PAD_ENET_RX_ER__GPIO1_IO24 = IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__PHY_TDI = IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD = IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0), MX6_PAD_ENET_CRS_DV__RESERVED_RSRVED = IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0), MX6_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0), - MX6_PAD_ENET_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0), - MX6_PAD_ENET_CRS_DV__SPDIF_EXTCLK = IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0), - MX6_PAD_ENET_CRS_DV__GPIO_1_25 = IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0), + MX6_PAD_ENET_CRS_DV__ESAI_TX_CLK = IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0), + MX6_PAD_ENET_CRS_DV__SPDIF_EXT_CLK = IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0), + MX6_PAD_ENET_CRS_DV__GPIO1_IO25 = IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0), MX6_PAD_ENET_CRS_DV__PHY_TDO = IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0), MX6_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD = IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__MLB_MLBSIG = IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0), - MX6_PAD_ENET_RXD1__ENET_RDATA_1 = IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0), - MX6_PAD_ENET_RXD1__ESAI1_FST = IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0), - MX6_PAD_ENET_RXD1__ENET_1588_EVT3_OUT = IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__GPIO_1_26 = IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0), + MX6_PAD_ENET_RXD1__MLB_SIG = IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0), + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 = IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0), + MX6_PAD_ENET_RXD1__ESAI_TX_FS = IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0), + MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT = IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0), + MX6_PAD_ENET_RXD1__GPIO1_IO26 = IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0), MX6_PAD_ENET_RXD1__PHY_TCK = IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0), MX6_PAD_ENET_RXD1__USBPHY1_RX_DISCON = IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0), MX6_PAD_ENET_RXD0__OSC32K_32K_OUT = IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__ENET_RDATA_0 = IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0), - MX6_PAD_ENET_RXD0__ESAI1_HCKT = IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0), - MX6_PAD_ENET_RXD0__SPDIF_OUT1 = IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0), + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 = IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0), + MX6_PAD_ENET_RXD0__ESAI_TX_HF_CLK = IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0), + MX6_PAD_ENET_RXD0__SPDIF_OUT = IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0), + MX6_PAD_ENET_RXD0__GPIO1_IO27 = IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0), MX6_PAD_ENET_RXD0__PHY_TMS = IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0), MX6_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV = IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__RESERVED_RSRVED = IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__ESAI1_TX3_RX2 = IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0), - MX6_PAD_ENET_TX_EN__GPIO_1_28 = IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0), + MX6_PAD_ENET_TX_EN__ESAI_TX3_RX2 = IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0), + MX6_PAD_ENET_TX_EN__GPIO1_IO28 = IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__SATA_PHY_TDI = IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__USBPHY2_RX_SQH = IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__MLB_MLBCLK = IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0), - MX6_PAD_ENET_TXD1__ENET_TDATA_1 = IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__ESAI1_TX2_RX3 = IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0), + MX6_PAD_ENET_TXD1__MLB_CLK = IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0), + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 = IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0), + MX6_PAD_ENET_TXD1__ESAI_TX2_RX3 = IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0), MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__GPIO_1_29 = IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0), + MX6_PAD_ENET_TXD1__GPIO1_IO29 = IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__SATA_PHY_TDO = IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD = IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0), MX6_PAD_ENET_TXD0__RESERVED_RSRVED = IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__ENET_TDATA_0 = IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__ESAI1_TX4_RX1 = IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0), - MX6_PAD_ENET_TXD0__GPIO_1_30 = IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0), + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 = IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0), + MX6_PAD_ENET_TXD0__ESAI_TX4_RX1 = IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0), + MX6_PAD_ENET_TXD0__GPIO1_IO30 = IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0), MX6_PAD_ENET_TXD0__SATA_PHY_TCK = IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0), MX6_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD = IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__MLB_MLBDAT = IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0), + MX6_PAD_ENET_MDC__MLB_DATA = IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0), MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__ESAI1_TX5_RX0 = IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0), + MX6_PAD_ENET_MDC__ESAI_TX5_RX0 = IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0), MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__GPIO_1_31 = IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0), + MX6_PAD_ENET_MDC__GPIO1_IO31 = IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0), MX6_PAD_ENET_MDC__SATA_PHY_TMS = IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0), MX6_PAD_ENET_MDC__USBPHY2_RX_DISCON = IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0), MX6_PAD_DRAM_D40__MMDC_DRAM_D_40 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), @@ -892,357 +892,357 @@ enum { MX6_PAD_DRAM_D62__MMDC_DRAM_D_62 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_D63__MMDC_DRAM_D_63 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0), - MX6_PAD_KEY_COL0__ENET_RDATA_3 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0), - MX6_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0), - MX6_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_TXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_TXD_RXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0), - MX6_PAD_KEY_COL0__GPIO_4_6 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__DCIC1_DCIC_OUT = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__ENET_RX_DATA3 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0), + MX6_PAD_KEY_COL0__AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0), + MX6_PAD_KEY_COL0__KEY_COL0 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__UART4_TX_DATA = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__UART4_RX_DATA = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0), + MX6_PAD_KEY_COL0__GPIO4_IO06 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__DCIC1_OUT = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0), - MX6_PAD_KEY_ROW0__ENET_TDATA_3 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0), - MX6_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__UART4_RXD = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0), - MX6_PAD_KEY_ROW0__GPIO_4_7 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__DCIC2_DCIC_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__ENET_TX_DATA3 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0), + MX6_PAD_KEY_ROW0__KEY_ROW0 = IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__UART4_RX_DATA = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0), + MX6_PAD_KEY_ROW0__GPIO4_IO07 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__DCIC2_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__PL301_PER1_HADR_0 = IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0), MX6_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0), - MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0), - MX6_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_TXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_TXD_RXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0), - MX6_PAD_KEY_COL1__GPIO_4_8 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__USDHC1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0), + MX6_PAD_KEY_COL1__KEY_COL1 = IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__UART5_TX_DATA = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__UART5_RX_DATA = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0), + MX6_PAD_KEY_COL1__GPIO4_IO08 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__SD1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL1__PL301MX_PER1_HADR_1 = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0), MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0), - MX6_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__UART5_RXD = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0), - MX6_PAD_KEY_ROW1__GPIO_4_9 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__USDHC2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0), + MX6_PAD_KEY_ROW1__KEY_ROW1 = IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__UART5_RX_DATA = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0), + MX6_PAD_KEY_ROW1__GPIO4_IO09 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__SD2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__PL301_PER1_HADDR_2 = IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0), - MX6_PAD_KEY_COL2__ENET_RDATA_2 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0), - MX6_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__ENET_RX_DATA2 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0), + MX6_PAD_KEY_COL2__FLEXCAN1_TX = IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__KEY_COL2 = IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__GPIO_4_10 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__GPIO4_IO10 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL2__PL301_PER1_HADDR_3 = IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0), - MX6_PAD_KEY_ROW2__ENET_TDATA_2 = IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0), - MX6_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__USDHC2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__GPIO_4_11 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__ENET_TX_DATA2 = IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__FLEXCAN1_RX = IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0), + MX6_PAD_KEY_ROW2__KEY_ROW2 = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__SD2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__GPIO4_IO11 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0), MX6_PAD_KEY_ROW2__PL301_PER1_HADR_4 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0), MX6_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0), - MX6_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__KEY_COL3 = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x05E0, 0x0210, 20, 0x08A0, 1, 0), - MX6_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0), + MX6_PAD_KEY_COL3__GPIO4_IO12 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__SPDIF_IN = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0), MX6_PAD_KEY_COL3__PL301_PER1_HADR_5 = IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0), + MX6_PAD_KEY_ROW3__ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0), MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0), - MX6_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__KEY_ROW3 = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x05E4, 0x0214, 20, 0x08A4, 1, 0), - MX6_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__USDHC1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__GPIO4_IO13 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__SD1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__PL301_PER1_HADR_6 = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__IPU1_SISG_4 = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0), - MX6_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_CTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0), - MX6_PAD_KEY_COL4__GPIO_4_14 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__FLEXCAN2_TX = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__IPU1_SISG4 = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__USB_OTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0), + MX6_PAD_KEY_COL4__KEY_COL4 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__UART5_CTS_B = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__UART5_RTS_B = IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0), + MX6_PAD_KEY_COL4__GPIO4_IO14 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), MX6_PAD_KEY_COL4__MMDC_DEBUG_49 = IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL4__PL301_PER1_HADDR_7 = IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0), - MX6_PAD_KEY_ROW4__IPU1_SISG_5 = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0), - MX6_PAD_KEY_ROW4__GPIO_4_15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__FLEXCAN2_RX = IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0), + MX6_PAD_KEY_ROW4__IPU1_SISG5 = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__USB_OTG_PWR = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__KEY_ROW4 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__UART5_RTS_B = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0), + MX6_PAD_KEY_ROW4__GPIO4_IO15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__MMDC_DEBUG_50 = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__PL301_PER1_HADR_8 = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0), - MX6_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0), - MX6_PAD_GPIO_0__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0), - MX6_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_0__GPIO_1_0 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0), - MX6_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0), - MX6_PAD_GPIO_1__USB_OTG_ID = IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_0__CCM_CLKO1 = IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0), + MX6_PAD_GPIO_0__KEY_COL5 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0), + MX6_PAD_GPIO_0__ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0), + MX6_PAD_GPIO_0__EPIT1_OUT = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_0__GPIO1_IO00 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_0__USB_H1_PWR = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_0__SNVS_VIO_5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_1__ESAI_RX_CLK = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0), + MX6_PAD_GPIO_1__WDOG2_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_1__KEY_ROW5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0), + MX6_PAD_GPIO_1__USB_OTG_ID = IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_1__PWM2_OUT = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_1__GPIO1_IO01 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_1__SD1_CD_B = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), MX6_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_9__ESAI1_FSR = IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0), - MX6_PAD_GPIO_9__WDOG1_WDOG_B = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_9__KPP_COL_6 = IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0), + MX6_PAD_GPIO_9__ESAI_RX_FS = IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0), + MX6_PAD_GPIO_9__WDOG1_B = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_9__KEY_COL6 = IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0), MX6_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_9__PWM1_PWMO = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_9__GPIO_1_9 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_9__USDHC1_WP = IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0), + MX6_PAD_GPIO_9__PWM1_OUT = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_9__GPIO1_IO09 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_9__SD1_WP = IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0), MX6_PAD_GPIO_9__SRC_EARLY_RST = IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0), + MX6_PAD_GPIO_3__ESAI_RX_HF_CLK = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0), MX6_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0), MX6_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05FC, 0x022C, 18, 0x08A8, 1, 0), - MX6_PAD_GPIO_3__ANATOP_24M_OUT = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0), MX6_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_3__GPIO_1_3 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0), - MX6_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0), - MX6_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0), + MX6_PAD_GPIO_3__GPIO1_IO03 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_3__USB_H1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0), + MX6_PAD_GPIO_3__MLB_CLK = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0), + MX6_PAD_GPIO_6__ESAI_TX_CLK = IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0), MX6_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 = IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0), MX6_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0600, 0x0230, 18, 0x08AC, 1, 0), MX6_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0), MX6_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_6__GPIO_1_6 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_6__USDHC2_LCTL = IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0), - MX6_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0), + MX6_PAD_GPIO_6__GPIO1_IO06 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_6__SD2_LCTL = IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_6__MLB_SIG = IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0), + MX6_PAD_GPIO_2__ESAI_TX_FS = IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0), MX6_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0), + MX6_PAD_GPIO_2__KEY_ROW6 = IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0), MX6_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0), MX6_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_2__GPIO_1_2 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_2__USDHC2_WP = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0), - MX6_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0), + MX6_PAD_GPIO_2__GPIO1_IO02 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_2__SD2_WP = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_2__MLB_DATA = IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0), + MX6_PAD_GPIO_4__ESAI_TX_HF_CLK = IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0), MX6_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 = IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0), + MX6_PAD_GPIO_4__KEY_COL7 = IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0), MX6_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0), MX6_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_4__GPIO_1_4 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_4__USDHC2_CD = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_4__GPIO1_IO04 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_4__SD2_CD_B = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0), MX6_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0), + MX6_PAD_GPIO_5__ESAI_TX2_RX3 = IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0), MX6_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0), - MX6_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_5__KEY_ROW7 = IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0), + MX6_PAD_GPIO_5__CCM_CLKO1 = IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0), MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_5__GPIO1_IO05 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0), MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x060C, 0x023C, 22, 0x08A8, 2, 0), - MX6_PAD_GPIO_5__CHEETAH_EVENTI = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0), + MX6_PAD_GPIO_5__ARM_EVENTI = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_7__ESAI_TX4_RX1 = IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0), MX6_PAD_GPIO_7__ECSPI5_RDY = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_TXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_TXD_RXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0), - MX6_PAD_GPIO_7__GPIO_1_7 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0), - MX6_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT = IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0), - MX6_PAD_GPIO_8__UART2_RXD = IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0), - MX6_PAD_GPIO_8__GPIO_1_8 = IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK = IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0), + MX6_PAD_GPIO_7__EPIT1_OUT = IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_7__FLEXCAN1_TX = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_7__UART2_TX_DATA = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_7__UART2_RX_DATA = IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0), + MX6_PAD_GPIO_7__GPIO1_IO07 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_7__SPDIF_LOCK = IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_7__USB_OTG_HOST_MODE = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_8__ESAI_TX5_RX0 = IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0), + MX6_PAD_GPIO_8__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_8__EPIT2_OUT = IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_8__FLEXCAN1_RX = IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0), + MX6_PAD_GPIO_8__UART2_RX_DATA = IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0), + MX6_PAD_GPIO_8__GPIO1_IO08 = IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_8__SPDIF_SR_CLK = IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE = IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_16__ESAI_TX3_RX2 = IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0), MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ENET_ETHERNET_REF_OUT = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0), - MX6_PAD_GPIO_16__USDHC1_LCTL = IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0), - MX6_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_16__ENET_REF_CLK = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0), + MX6_PAD_GPIO_16__SD1_LCTL = IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_16__SPDIF_IN = IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0), + MX6_PAD_GPIO_16__GPIO7_IO11 = IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0), MX6_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x0618, 0x0248, 22, 0x08AC, 2, 0), - MX6_PAD_GPIO_16__SJC_DE_B = IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_17__ESAI1_TX0 = IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0), + MX6_PAD_GPIO_16__JTAG_DE_B = IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_17__ESAI_TX0 = IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0), MX6_PAD_GPIO_17__ENET_1588_EVENT3_IN = IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_17__CCM_PMIC_RDY = IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0), - MX6_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0), - MX6_PAD_GPIO_17__SPDIF_OUT1 = IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_17__CCM_PMIC_READY = IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0), + MX6_PAD_GPIO_17__SDMA_EXT_EVENT0 = IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0), + MX6_PAD_GPIO_17__SPDIF_OUT = IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_17__GPIO7_IO12 = IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0), MX6_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_18__ESAI1_TX1 = IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0), + MX6_PAD_GPIO_18__ESAI_TX1 = IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0), MX6_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0), - MX6_PAD_GPIO_18__USDHC3_VSELECT = IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0), - MX6_PAD_GPIO_18__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0), - MX6_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_18__SD3_VSELECT = IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_18__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0), + MX6_PAD_GPIO_18__ASRC_EXT_CLK = IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0), + MX6_PAD_GPIO_18__GPIO7_IO13 = IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_18__SNVS_VIO_5_CTL = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0), MX6_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0), + MX6_PAD_GPIO_19__KEY_COL5 = IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0), MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_19__SPDIF_OUT = IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_19__CCM_CLKO1 = IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0), MX6_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_19__GPIO4_IO05 = IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0), MX6_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0), MX6_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 = IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__GPIO_5_18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 = IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__CHEETAH_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_PIXCLK__ARM_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 = IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__CCM_CLKO = IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__CCM_CLKO1 = IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__GPIO_5_19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__GPIO5_IO19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__CHEETAH_TRCTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 = IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__ARM_TRACE_CTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__EIM_DATA00 = IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 = IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__GPIO_5_20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 = IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__CHEETAH_TRCLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__ARM_TRACE_CLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__EIM_DATA01 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 = IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__GPIO_5_21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__GPIO5_IO21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__MMDC_DEBUG_32 = IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__IPU1_CSI0_D_4 = IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__WEIM_WEIM_D_2 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__ARM_TRACE00 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 = IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__EIM_DATA02 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0), - MX6_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0), - MX6_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__GPIO_5_22 = IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__KEY_COL5 = IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0), + MX6_PAD_CSI0_DAT4__AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__GPIO5_IO22 = IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__MMDC_DEBUG_43 = IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__CHEETAH_TRACE_1 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__IPU1_CSI0_D_5 = IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__WEIM_WEIM_D_3 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__ARM_TRACE01 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 = IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__EIM_DATA03 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0), - MX6_PAD_CSI0_DAT5__KPP_ROW_5 = IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0), - MX6_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__GPIO_5_23 = IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__KEY_ROW5 = IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0), + MX6_PAD_CSI0_DAT5__AUD3_TXD = IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__GPIO5_IO23 = IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 = IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__CHEETAH_TRACE_2 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__IPU1_CSI0_D_6 = IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__WEIM_WEIM_D_4 = IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__ARM_TRACE02 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 = IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__EIM_DATA04 = IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0), - MX6_PAD_CSI0_DAT6__KPP_COL_6 = IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0), - MX6_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__GPIO_5_24 = IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__KEY_COL6 = IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0), + MX6_PAD_CSI0_DAT6__AUD3_TXFS = IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__GPIO5_IO24 = IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 = IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__CHEETAH_TRACE_3 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__IPU1_CSI0_D_7 = IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__WEIM_WEIM_D_5 = IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__ARM_TRACE03 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 = IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__EIM_DATA05 = IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0), - MX6_PAD_CSI0_DAT7__KPP_ROW_6 = IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0), - MX6_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__GPIO_5_25 = IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__KEY_ROW6 = IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0), + MX6_PAD_CSI0_DAT7__AUD3_RXD = IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__GPIO5_IO25 = IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 = IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__CHEETAH_TRACE_4 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__IPU1_CSI0_D_8 = IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__WEIM_WEIM_D_6 = IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__ARM_TRACE04 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 = IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__EIM_DATA06 = IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0), - MX6_PAD_CSI0_DAT8__KPP_COL_7 = IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0), + MX6_PAD_CSI0_DAT8__KEY_COL7 = IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0), MX6_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0648, 0x0278, 20, 0x089C, 1, 0), - MX6_PAD_CSI0_DAT8__GPIO_5_26 = IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__GPIO5_IO26 = IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 = IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__CHEETAH_TRACE_5 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__IPU1_CSI0_D_9 = IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__WEIM_WEIM_D_7 = IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__ARM_TRACE05 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 = IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__EIM_DATA07 = IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0), - MX6_PAD_CSI0_DAT9__KPP_ROW_7 = IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0), + MX6_PAD_CSI0_DAT9__KEY_ROW7 = IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0), MX6_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x064C, 0x027C, 20, 0x0898, 1, 0), - MX6_PAD_CSI0_DAT9__GPIO_5_27 = IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__GPIO5_IO27 = IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 = IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__CHEETAH_TRACE_6 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__IPU1_CSI0_D_10 = IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__ARM_TRACE06 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 = IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0), - MX6_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__UART1_TXD_RXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0), + MX6_PAD_CSI0_DAT10__UART1_TX_DATA = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__UART1_RX_DATA = IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0), MX6_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__GPIO_5_28 = IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__GPIO5_IO28 = IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__CHEETAH_TRACE_7 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__IPU1_CSI0_D_11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__ARM_TRACE07 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0), - MX6_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0), MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__GPIO_5_29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__GPIO5_IO29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 = IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__CHEETAH_TRACE_8 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__IPU1_CSI0_D_12 = IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__WEIM_WEIM_D_8 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__ARM_TRACE08 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 = IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__EIM_DATA08 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 = IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_TXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_TXD_RXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0), + MX6_PAD_CSI0_DAT12__UART4_TX_DATA = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__UART4_RX_DATA = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0), MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__GPIO_5_30 = IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__GPIO5_IO30 = IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__CHEETAH_TRACE_9 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__IPU1_CSI0_D_13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__WEIM_WEIM_D_9 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__ARM_TRACE09 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__EIM_DATA09 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 = IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_RXD = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0), + MX6_PAD_CSI0_DAT13__UART4_RX_DATA = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0), MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__GPIO_5_31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__GPIO5_IO31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 = IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__CHEETAH_TRACE_10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__IPU1_CSI0_D_14 = IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__WEIM_WEIM_D_10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__ARM_TRACE10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 = IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__EIM_DATA10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 = IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_TXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_TXD_RXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0), + MX6_PAD_CSI0_DAT14__UART5_TX_DATA = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__UART5_RX_DATA = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0), MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__GPIO_6_0 = IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__GPIO6_IO00 = IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__CHEETAH_TRACE_11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__IPU1_CSI0_D_15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__WEIM_WEIM_D_11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__ARM_TRACE11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__EIM_DATA11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 = IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_RXD = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0), + MX6_PAD_CSI0_DAT15__UART5_RX_DATA = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0), MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__GPIO_6_1 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__GPIO6_IO01 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 = IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__CHEETAH_TRACE_12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__IPU1_CSI0_D_16 = IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__WEIM_WEIM_D_12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__ARM_TRACE12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 = IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__EIM_DATA12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 = IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_CTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0), + MX6_PAD_CSI0_DAT16__UART4_CTS_B = IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__UART4_RTS_B = IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0), MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__GPIO_6_2 = IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__GPIO6_IO02 = IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 = IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__CHEETAH_TRACE_13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__IPU1_CSI0_D_17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__WEIM_WEIM_D_13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__ARM_TRACE13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__EIM_DATA13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 = IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0), + MX6_PAD_CSI0_DAT17__UART4_RTS_B = IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0), MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__GPIO_6_3 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__GPIO6_IO03 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 = IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__CHEETAH_TRACE_14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__IPU1_CSI0_D_18 = IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__WEIM_WEIM_D_14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__ARM_TRACE14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 = IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__EIM_DATA14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 = IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_CTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0), + MX6_PAD_CSI0_DAT18__UART5_CTS_B = IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__UART5_RTS_B = IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0), MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__GPIO_6_4 = IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__GPIO6_IO04 = IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 = IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__CHEETAH_TRACE_15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__IPU1_CSI0_D_19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__WEIM_WEIM_D_15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__ARM_TRACE15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__EIM_DATA15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 = IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0), + MX6_PAD_CSI0_DAT19__UART5_RTS_B = IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0), MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__GPIO_6_5 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__GPIO6_IO05 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 = IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__ANATOP_TESTO_9 = IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0), MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0), @@ -1269,362 +1269,362 @@ enum { MX6_PAD_RESET_IN_B__SRC_RESET_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__USDHC3_DAT7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_TXD_RXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0), + MX6_PAD_SD3_DAT7__SD3_DATA7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__UART1_TX_DATA = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__UART1_RX_DATA = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0), MX6_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__GPIO_6_17 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__GPIO6_IO17 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__USBPHY2_CLK20DIV = IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__USDHC3_DAT6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0), + MX6_PAD_SD3_DAT6__SD3_DATA6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT6__UART1_RX_DATA = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0), MX6_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 = IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__GPIO_6_18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT6__GPIO6_IO18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__ANATOP_TESTO_10 = IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__USDHC3_DAT5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_TXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_TXD_RXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0), + MX6_PAD_SD3_DAT5__SD3_DATA5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__UART2_TX_DATA = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__UART2_RX_DATA = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0), MX6_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 = IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__GPIO7_IO00 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__ANATOP_TESTO_11 = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__USDHC3_DAT4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__UART2_RXD = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0), + MX6_PAD_SD3_DAT4__SD3_DATA4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT4__UART2_RX_DATA = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0), MX6_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 = IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__GPIO_7_1 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT4__GPIO7_IO01 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__ANATOP_TESTO_12 = IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__UART2_CTS = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0), - MX6_PAD_SD3_CMD__CAN1_TXCAN = IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__UART2_RTS_B = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0), + MX6_PAD_SD3_CMD__FLEXCAN1_TX = IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0), MX6_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0), MX6_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__GPIO_7_2 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__GPIO7_IO02 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0), MX6_PAD_SD3_CMD__ANATOP_TESTO_13 = IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__UART2_CTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__UART2_RTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0), - MX6_PAD_SD3_CLK__CAN1_RXCAN = IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0), + MX6_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__UART2_CTS_B = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__UART2_RTS_B = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0), + MX6_PAD_SD3_CLK__FLEXCAN1_RX = IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0), MX6_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0), MX6_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__GPIO_7_3 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__GPIO7_IO03 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0), MX6_PAD_SD3_CLK__ANATOP_TESTO_14 = IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__UART1_CTS = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0), - MX6_PAD_SD3_DAT0__CAN2_TXCAN = IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__SD3_DATA0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__UART1_RTS_B = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0), + MX6_PAD_SD3_DAT0__FLEXCAN2_TX = IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__GPIO_7_4 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__GPIO7_IO04 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__ANATOP_TESTO_15 = IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_CTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_RTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0), - MX6_PAD_SD3_DAT1__CAN2_RXCAN = IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0), + MX6_PAD_SD3_DAT1__SD3_DATA1 = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__UART1_CTS_B = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__UART1_RTS_B = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0), + MX6_PAD_SD3_DAT1__FLEXCAN2_RX = IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0), MX6_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__GPIO_7_5 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__GPIO7_IO05 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__ANATOP_TESTI_0 = IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__SD3_DATA2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 = IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__GPIO_7_6 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__GPIO7_IO06 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__ANATOP_TESTI_1 = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__UART3_CTS = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0), + MX6_PAD_SD3_DAT3__SD3_DATA3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__UART3_RTS_B = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0), MX6_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 = IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__GPIO_7_7 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__GPIO7_IO07 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__ANATOP_TESTI_2 = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0), - MX6_PAD_SD3_RST__USDHC3_RST = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_CTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_RTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0), + MX6_PAD_SD3_RST__SD3_RESET = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), + MX6_PAD_SD3_RST__UART3_CTS_B = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), + MX6_PAD_SD3_RST__UART3_RTS_B = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0), MX6_PAD_SD3_RST__PCIE_CTRL_MUX_30 = IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0), MX6_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0), MX6_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0), - MX6_PAD_SD3_RST__GPIO_7_8 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), + MX6_PAD_SD3_RST__GPIO7_IO08 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), MX6_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 = IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0), MX6_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 = IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__RAWNAND_CLE = IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__IPU2_SISG_4 = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CLE__NAND_CLE = IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CLE__IPU2_SISG4 = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 = IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__GPIO_6_7 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CLE__GPIO6_IO07 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__TPSMP_HTRANS_0 = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__RAWNAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__USDHC4_RST = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__NAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__SD4_RESET = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__GPIO_6_8 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__GPIO6_IO08 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__TPSMP_HTRANS_1 = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__RAWNAND_RESETN = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__IPU2_SISG_5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__NAND_WP_B = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__IPU2_SISG5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__GPIO_6_9 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__GPIO6_IO09 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 = IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__RAWNAND_READY0 = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__IPU2_DI0_PIN1 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__NAND_READY_B = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__IPU2_DI0_PIN01 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__GPIO_6_10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__GPIO6_IO10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 = IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 = IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__RAWNAND_CE0N = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS0__NAND_CE0_B = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__GPIO_6_11 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS0__GPIO6_IO11 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 = IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__RAWNAND_CE1N = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__USDHC4_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__USDHC3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__NAND_CE1_B = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__SD4_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__SD3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 = IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__GPIO6_IO14 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__PL301_PER1_HRDYOUT = IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__RAWNAND_CE2N = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__IPU1_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0), - MX6_PAD_NANDF_CS2__WEIM_WEIM_CRE = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__NAND_CE2_B = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__IPU1_SISG0 = IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__ESAI_TX0 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0), + MX6_PAD_NANDF_CS2__EIM_CRE = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__GPIO_6_15 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__IPU2_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__RAWNAND_CE3N = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__IPU1_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__ESAI1_TX1 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0), - MX6_PAD_NANDF_CS3__WEIM_WEIM_A_26 = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__GPIO6_IO15 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__IPU2_SISG0 = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__NAND_CE3_B = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__IPU1_SISG1 = IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__ESAI_TX1 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0), + MX6_PAD_NANDF_CS3__EIM_ADDR26 = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__GPIO_6_16 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__IPU2_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__GPIO6_IO16 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__IPU2_SISG1 = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__TPSMP_CLK = IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x06DC, 0x02F4, 16, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__RAWNAND_RDN = IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_TXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_TXD_RXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0), + MX6_PAD_SD4_CMD__SD4_CMD = IOMUX_PAD(0x06DC, 0x02F4, 16, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__NAND_RE_B = IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__UART3_TX_DATA = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__UART3_RX_DATA = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0), MX6_PAD_SD4_CMD__PCIE_CTRL_MUX_5 = IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__GPIO_7_9 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__GPIO7_IO09 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), MX6_PAD_SD4_CMD__TPSMP_HDATA_DIR = IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__RAWNAND_WRN = IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__UART3_RXD = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0), + MX6_PAD_SD4_CLK__SD4_CLK = IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__NAND_WE_B = IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__UART3_RX_DATA = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0), MX6_PAD_SD4_CLK__PCIE_CTRL_MUX_6 = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__GPIO_7_10 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__RAWNAND_D0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__USDHC1_DAT4 = IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__GPIO7_IO10 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__NAND_DATA00 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__SD1_DATA4 = IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 = IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__GPIO_2_0 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__GPIO2_IO00 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__RAWNAND_D1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__USDHC1_DAT5 = IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__NAND_DATA01 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__SD1_DATA5 = IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__GPIO2_IO01 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__RAWNAND_D2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__USDHC1_DAT6 = IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__NAND_DATA02 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__SD1_DATA6 = IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__GPIO2_IO02 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__RAWNAND_D3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__USDHC1_DAT7 = IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__NAND_DATA03 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__SD1_DATA7 = IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__GPIO2_IO03 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__RAWNAND_D4 = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__USDHC2_DAT4 = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__NAND_DATA04 = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__SD2_DATA4 = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 = IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__GPIO2_IO04 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__RAWNAND_D5 = IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__USDHC2_DAT5 = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__NAND_DATA05 = IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__SD2_DATA5 = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__GPIO_2_5 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__GPIO2_IO05 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__RAWNAND_D6 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__USDHC2_DAT6 = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__NAND_DATA06 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__SD2_DATA6 = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__GPIO2_IO06 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__RAWNAND_D7 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__USDHC2_DAT7 = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__NAND_DATA07 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__SD2_DATA7 = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__GPIO_2_7 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__GPIO2_IO07 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__RAWNAND_D8 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__RAWNAND_DQS = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__SD4_DATA0 = IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__NAND_DQS = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__GPIO_2_8 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__GPIO2_IO08 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__RAWNAND_D9 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__PWM3_PWMO = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__SD4_DATA1 = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__PWM3_OUT = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__GPIO_2_9 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__GPIO2_IO09 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__RAWNAND_D10 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__PWM4_PWMO = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__SD4_DATA2 = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__PWM4_OUT = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__GPIO_2_10 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__GPIO2_IO10 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__RAWNAND_D11 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT3__SD4_DATA3 = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__GPIO_2_11 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT3__GPIO2_IO11 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__RAWNAND_D12 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__USDHC4_DAT4 = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__UART2_RXD = IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0), + MX6_PAD_SD4_DAT4__SD4_DATA4 = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT4__UART2_RX_DATA = IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0), MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__GPIO_2_12 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT4__GPIO2_IO12 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__RAWNAND_D13 = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__USDHC4_DAT5 = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_CTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_RTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0), + MX6_PAD_SD4_DAT5__SD4_DATA5 = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__UART2_CTS_B = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__UART2_RTS_B = IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0), MX6_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__GPIO_2_13 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__GPIO2_IO13 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__RAWNAND_D14 = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__USDHC4_DAT6 = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__UART2_CTS = IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0), + MX6_PAD_SD4_DAT6__SD4_DATA6 = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT6__UART2_RTS_B = IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0), MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__GPIO_2_14 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT6__GPIO2_IO14 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__RAWNAND_D15 = IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__USDHC4_DAT7 = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_TXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_TXD_RXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0), + MX6_PAD_SD4_DAT7__SD4_DATA7 = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__UART2_TX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__UART2_RX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0), MX6_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__GPIO_2_15 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__GPIO2_IO15 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__SD1_DATA1 = IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0), - MX6_PAD_SD1_DAT1__PWM3_PWMO = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPT_CAPIN2 = IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__PWM3_OUT = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__GPT_CAPTURE2 = IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 = IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPIO_1_17 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__GPIO1_IO17 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 = IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__ANATOP_TESTO_8 = IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__SD1_DATA0 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0), MX6_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__GPT_CAPIN1 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__GPT_CAPTURE1 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__GPIO_1_16 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__GPIO1_IO16 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 = IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__ANATOP_TESTO_7 = IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__SD1_DATA3 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0), MX6_PAD_SD1_DAT3__ECSPI5_SS2 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPT_CMPOUT3 = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__PWM1_PWMO = IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_WDOG_B = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__GPT_COMPARE3 = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__PWM1_OUT = IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__WDOG2_B = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__GPIO1_IO21 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__WDOG2_RESET_B_DEB = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0), MX6_PAD_SD1_DAT3__ANATOP_TESTO_6 = IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0730, 0x0348, 16, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x0730, 0x0348, 16, 0x0000, 0, 0), MX6_PAD_SD1_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0), - MX6_PAD_SD1_CMD__PWM4_PWMO = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPT_CMPOUT1 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__PWM4_OUT = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPT_COMPARE1 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPIO1_IO18 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0), MX6_PAD_SD1_CMD__ANATOP_TESTO_5 = IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__SD1_DATA2 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0), MX6_PAD_SD1_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0), - MX6_PAD_SD1_DAT2__GPT_CMPOUT2 = IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__PWM2_PWMO = IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_WDOG_B = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__GPIO_1_19 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__GPT_COMPARE2 = IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__PWM2_OUT = IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__WDOG1_B = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__GPIO1_IO19 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__WDOG1_RESET_B_DEB = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0), MX6_PAD_SD1_DAT2__ANATOP_TESTO_4 = IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0), MX6_PAD_SD1_CLK__ECSPI5_SCLK = IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0), MX6_PAD_SD1_CLK__OSC32K_32K_OUT = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0), MX6_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__GPIO_1_20 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPIO1_IO20 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0), MX6_PAD_SD1_CLK__PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0), MX6_PAD_SD1_CLK__SATA_PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0), MX6_PAD_SD2_CLK__ECSPI5_SCLK = IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0), - MX6_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0), - MX6_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0), + MX6_PAD_SD2_CLK__KEY_COL5 = IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0), + MX6_PAD_SD2_CLK__AUD4_RXFS = IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0), MX6_PAD_SD2_CLK__PCIE_CTRL_MUX_9 = IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__GPIO_1_10 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__GPIO1_IO10 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), MX6_PAD_SD2_CLK__PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0), MX6_PAD_SD2_CLK__SATA_PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0740, 0x0358, 16, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x0740, 0x0358, 16, 0x0000, 0, 0), MX6_PAD_SD2_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0), - MX6_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0), - MX6_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0), + MX6_PAD_SD2_CMD__KEY_ROW5 = IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0), + MX6_PAD_SD2_CMD__AUD4_RXC = IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0), MX6_PAD_SD2_CMD__PCIE_CTRL_MUX_10 = IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__GPIO_1_11 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__GPIO1_IO11 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__SD2_DATA3 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__ECSPI5_SS3 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__KPP_COL_6 = IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0), - MX6_PAD_SD2_DAT3__AUDMUX_AUD4_TXC = IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0), + MX6_PAD_SD2_DAT3__KEY_COL6 = IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0), + MX6_PAD_SD2_DAT3__AUD4_TXC = IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0), MX6_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 = IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__GPIO_1_12 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__GPIO1_IO12 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__SJC_DONE = IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__ANATOP_TESTO_3 = IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0), }; diff --git a/board/barco/titanium/titanium.c b/board/barco/titanium/titanium.c index 9a317bc1378..c3775ef7b3b 100644 --- a/board/barco/titanium/titanium.c +++ b/board/barco/titanium/titanium.c @@ -45,18 +45,18 @@ int dram_init(void) } iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) @@ -64,12 +64,12 @@ iomux_v3_cfg_t const uart4_pads[] = { struct i2c_pads_info i2c_pad_info0 = { .scl = { .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO_5_27 | PC, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC, .gp = IMX_GPIO_NR(5, 27) }, .sda = { .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO_5_26 | PC, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, .gp = IMX_GPIO_NR(5, 26) } }; @@ -77,81 +77,81 @@ struct i2c_pads_info i2c_pad_info0 = { struct i2c_pads_info i2c_pad_info2 = { .scl = { .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, .gp = IMX_GPIO_NR(1, 3) }, .sda = { .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, .gp = IMX_GPIO_NR(7, 11) } }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const enet_pads1[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), /* pin 35 - 1 (PHY_AD2) on reset */ - MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 32 - 1 - (MODE0) all */ - MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 31 - 1 - (MODE1) all */ - MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 28 - 1 - (MODE2) all */ - MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 27 - 1 - (MODE3) all */ - MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ - MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 42 PHY nRST */ - MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads2[] = { - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; iomux_v3_cfg_t nfc_pads[] = { - MX6_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_gpmi_nand(void) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 53cb8dffd0d..616ad550aff 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -71,13 +71,13 @@ int dram_init(void) } iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) @@ -86,12 +86,12 @@ iomux_v3_cfg_t const uart2_pads[] = { struct i2c_pads_info i2c_pad_info0 = { .scl = { .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC, + .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, .gp = IMX_GPIO_NR(3, 21) }, .sda = { .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC, + .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, .gp = IMX_GPIO_NR(3, 28) } }; @@ -100,12 +100,12 @@ struct i2c_pads_info i2c_pad_info0 = { struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, .gp = IMX_GPIO_NR(4, 12) }, .sda = { .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, .gp = IMX_GPIO_NR(4, 13) } }; @@ -114,87 +114,87 @@ struct i2c_pads_info i2c_pad_info1 = { struct i2c_pads_info i2c_pad_info2 = { .scl = { .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC, + .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC, .gp = IMX_GPIO_NR(1, 5) }, .sda = { .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, .gp = IMX_GPIO_NR(7, 11) } }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const enet_pads1[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), /* pin 35 - 1 (PHY_AD2) on reset */ - MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 32 - 1 - (MODE0) all */ - MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 31 - 1 - (MODE1) all */ - MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 28 - 1 - (MODE2) all */ - MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 27 - 1 - (MODE3) all */ - MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ - MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 42 PHY nRST */ - MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads2[] = { - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; static iomux_v3_cfg_t const misc_pads[] = { MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP), /* OTG Power enable */ - MX6_PAD_EIM_D22__GPIO_3_22 | MUX_PAD_CTRL(OUTPUT_40OHM), + MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM), }; /* wl1271 pads on nitrogen6x */ iomux_v3_cfg_t const wl12xx_pads[] = { - (MX6_PAD_NANDF_CS1__GPIO_6_14 & ~MUX_PAD_CTRL_MASK) + (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(WEAK_PULLDOWN), - (MX6_PAD_NANDF_CS2__GPIO_6_15 & ~MUX_PAD_CTRL_MASK) + (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(OUTPUT_40OHM), - (MX6_PAD_NANDF_CS3__GPIO_6_16 & ~MUX_PAD_CTRL_MASK) + (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(OUTPUT_40OHM), }; #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14) @@ -204,17 +204,17 @@ iomux_v3_cfg_t const wl12xx_pads[] = { /* Button assignments for J14 */ static iomux_v3_cfg_t const button_pads[] = { /* Menu */ - MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Back */ - MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Labelled Search (mapped to Power under Android) */ - MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Home */ - MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Volume Down */ - MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Volume Up */ - MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), }; static void setup_iomux_enet(void) @@ -238,7 +238,7 @@ static void setup_iomux_enet(void) } iomux_v3_cfg_t const usb_pads[] = { - MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_uart(void) @@ -330,7 +330,7 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_MXC_SPI iomux_v3_cfg_t const ecspi1_pads[] = { /* SS1 */ - MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -431,44 +431,44 @@ int setup_sata(void) static iomux_v3_cfg_t const backlight_pads[] = { /* Backlight on RGB connector: J15 */ - MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21) /* Backlight on LVDS connector: J6 */ - MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18) }; static iomux_v3_cfg_t const rgb_pads[] = { MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, - MX6_PAD_DI0_PIN4__GPIO_4_20, - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, + MX6_PAD_DI0_PIN4__GPIO4_IO20, + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, }; struct display_info_t { diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 1ea68f46688..749253429b1 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -35,32 +35,32 @@ int dram_init(void) } iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_GPIO_4__GPIO_1_4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; static void setup_iomux_uart(void) diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index 05c938fcc97..1b4791c8a41 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -38,52 +38,52 @@ int dram_init(void) } iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index c55ee8783d5..1cf649ceeb0 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -51,25 +51,25 @@ int dram_init(void) } iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; @@ -77,12 +77,12 @@ iomux_v3_cfg_t const enet_pads[] = { struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, - .gpio_mode = MX6_PAD_EIM_EB2__GPIO_2_30 | PC, + .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, .gp = IMX_GPIO_NR(2, 30) }, .sda = { .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, .gp = IMX_GPIO_NR(4, 13) } }; @@ -94,22 +94,22 @@ struct i2c_pads_info i2c_pad_info1 = { struct i2c_pads_info i2c_pad_info2 = { .scl = { .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, .gp = IMX_GPIO_NR(1, 3) }, .sda = { .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D18__GPIO_3_18 | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, .gp = IMX_GPIO_NR(3, 18) } }; iomux_v3_cfg_t const i2c3_pads[] = { - MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), }; iomux_v3_cfg_t const port_exp[] = { - MX6_PAD_SD2_DAT0__GPIO_1_15 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_enet(void) @@ -118,18 +118,18 @@ static void setup_iomux_enet(void) } iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_uart(void) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 9dbe605cf4a..1ecedaccd1d 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -45,28 +45,28 @@ int dram_init(void) } iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), /* AR8031 PHY Reset */ - MX6_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_enet(void) @@ -80,44 +80,44 @@ static void setup_iomux_enet(void) } iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; static void setup_iomux_uart(void) diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c index e9d63750a88..ab7b655e99b 100644 --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -40,22 +40,22 @@ int dram_init(void) } static iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; static iomux_v3_cfg_t const wdog_pads[] = { - MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_D19__GPIO_3_19, + MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D19__GPIO3_IO19, }; static void setup_iomux_uart(void) diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index bf9898c3fe0..0043bc6460a 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -51,50 +51,50 @@ int dram_init(void) } static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const usdhc1_pads[] = { - MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* Carrier MicroSD Card Detect */ - MX6_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* SOM MicroSD Card Detect */ - MX6_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), /* AR8031 PHY Reset */ - MX6_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_uart(void) -- cgit v1.3.1 From 56f9cfbb48b56dfc08debaa78624aa7522520c0b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 20 Nov 2013 20:26:03 -0200 Subject: mx51evk: Fix pmic_init() argument On mx51evk board the PMIC is connected via SPI interface, so it does not make sense to pass I2C_PMIC into the pmic_init() interface. Pass the SPI bus number via CONFIG_FSL_PMIC_BUS option instead. Signed-off-by: Fabio Estevam Acked-by: Stefano Babic --- board/freescale/mx51evk/mx51evk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index d01465ecaef..9b43c84e791 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -174,7 +174,7 @@ static void power_init(void) struct pmic *p; int ret; - ret = pmic_init(I2C_PMIC); + ret = pmic_init(CONFIG_FSL_PMIC_BUS); if (ret) return; -- cgit v1.3.1 From 4e785c6ae90724b8e0b9610a61e6afc0a8f4379d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 20 Nov 2013 20:26:04 -0200 Subject: mx31pdk: Fix pmic_init() argument On mx31pdk board the PMIC is connected via SPI interface, so it does not make sense to pass I2C_PMIC into the pmic_init() interface. Pass the SPI bus number via CONFIG_FSL_PMIC_BUS option instead. Signed-off-by: Fabio Estevam --- board/freescale/mx31pdk/mx31pdk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index 148b4f47a51..13b9d51dd18 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -85,7 +85,7 @@ int board_late_init(void) struct pmic *p; int ret; - ret = pmic_init(I2C_PMIC); + ret = pmic_init(CONFIG_FSL_PMIC_BUS); if (ret) return ret; -- cgit v1.3.1 From d74b331f2ff083252d53b136f3cec9cb1ca2fc9e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 20 Nov 2013 20:26:05 -0200 Subject: efikamx: Fix pmic_init() argument On efikamx board the PMIC is connected via SPI interface, so it does not make sense to pass I2C_PMIC into the pmic_init() interface. Pass the SPI bus number via CONFIG_FSL_PMIC_BUS option instead. Signed-off-by: Fabio Estevam --- board/genesi/mx51_efikamx/efikamx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c index 76753f90f6b..16769e53327 100644 --- a/board/genesi/mx51_efikamx/efikamx.c +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -159,7 +159,7 @@ static void power_init(void) struct pmic *p; int ret; - ret = pmic_init(I2C_PMIC); + ret = pmic_init(CONFIG_FSL_PMIC_BUS); if (ret) return; -- cgit v1.3.1 From b48e3b04101eaae7a40107c447ed377561021997 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Nov 2013 10:34:26 -0200 Subject: mx6sabresd: Fix wrong colors in LVDS splash Currently HDMI splash screen is selected by default on mx6sabresd boards. As LVDS is also enabled, this causes incorrect colors to be displayed im the LVDS panel. Fix this by selecting the LVDS panel as the default splash output and only keep HDMI or LVDS turned on at the same time. Acked-by: Liu Ying Signed-off-by: Fabio Estevam --- board/freescale/mx6sabresd/mx6sabresd.c | 31 +++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) (limited to 'board') diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 1ecedaccd1d..db9fdff92d8 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -249,8 +249,22 @@ static int detect_hdmi(struct display_info_t const *dev) return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT; } + +static void disable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + int reg = readl(&iomux->gpr[2]); + + reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK | + IOMUXC_GPR2_LVDS_CH1_MODE_MASK); + + writel(reg, &iomux->gpr[2]); +} + static void do_enable_hdmi(struct display_info_t const *dev) { + disable_lvds(dev); imx_enable_hdmi_phy(); } @@ -263,14 +277,15 @@ static void enable_lvds(struct display_info_t const *dev) IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT; writel(reg, &iomux->gpr[2]); } + static struct display_info_t const displays[] = {{ .bus = -1, .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, - .enable = do_enable_hdmi, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = NULL, + .enable = enable_lvds, .mode = { - .name = "HDMI", + .name = "Hannstar-XGA", .refresh = 60, .xres = 1024, .yres = 768, @@ -286,11 +301,11 @@ static struct display_info_t const displays[] = {{ } }, { .bus = -1, .addr = 0, - .pixfmt = IPU_PIX_FMT_LVDS666, - .detect = NULL, - .enable = enable_lvds, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, .mode = { - .name = "Hannstar-XGA", + .name = "HDMI", .refresh = 60, .xres = 1024, .yres = 768, -- cgit v1.3.1 From 8bfa9c692e024bcf2b0b95be33adfa710301f83f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 8 Nov 2013 16:20:54 -0200 Subject: mx6sabresd: Add SPI NOR support mx6sabre board has a m25p32 SPI NOR connected to ECSPI1 port. Add support for it. This patch allows the SPI NOR flash to be succesfully detected: => sf probe SF: Detected M25P32 with page size 256 Bytes, erase size 64 KiB, total 4 MiB Signed-off-by: Fabio Estevam --- board/freescale/mx6sabresd/mx6sabresd.c | 19 +++++++++++++++++++ include/configs/mx6sabre_common.h | 12 ++++++++++++ 2 files changed, 31 insertions(+) (limited to 'board') diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index db9fdff92d8..851cbe9b32d 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -37,6 +37,9 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -120,6 +123,18 @@ iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; +iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); +} + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); @@ -455,6 +470,10 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + return 0; } diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 79d1f347b68..d52c9a89eb5 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -18,6 +18,7 @@ #define CONFIG_DISPLAY_BOARDINFO #include +#include #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS @@ -60,6 +61,17 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_ATHEROS +#define CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(4, 9) << 8)) +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -- cgit v1.3.1 From 953ab736afa0fca087b9e7626daa28ca7adc9fa8 Mon Sep 17 00:00:00 2001 From: Giuseppe Pagano Date: Fri, 15 Nov 2013 17:42:50 +0100 Subject: udoo: Move and optimize platform register setting. Previous uDoo configuration adopts register settings for DDR3, clock, muxing, etc. taken from Nitrogen6x. uDoo schematics is rather different from that board, and it needs customized setting for most of the registers. All this changes can be considered atomical since it is part of initial support of the board. Patch changes uDoo configuration files path to a specific one, and adopt optimized value for every configured register. Signed-off-by: Giuseppe Pagano Tested-by: Fabio Estevam CC: Stefano Babic CC: Fabio Estevam --- board/udoo/1066mhz_4x256mx16.cfg | 55 +++++++++++++++++++++++++ board/udoo/clocks.cfg | 32 +++++++++++++++ board/udoo/ddr-setup.cfg | 87 ++++++++++++++++++++++++++++++++++++++++ board/udoo/udoo.cfg | 29 ++++++++++++++ boards.cfg | 2 +- 5 files changed, 204 insertions(+), 1 deletion(-) create mode 100644 board/udoo/1066mhz_4x256mx16.cfg create mode 100644 board/udoo/clocks.cfg create mode 100644 board/udoo/ddr-setup.cfg create mode 100644 board/udoo/udoo.cfg (limited to 'board') diff --git a/board/udoo/1066mhz_4x256mx16.cfg b/board/udoo/1066mhz_4x256mx16.cfg new file mode 100644 index 00000000000..1ac0aec7739 --- /dev/null +++ b/board/udoo/1066mhz_4x256mx16.cfg @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 + +DATA 4, MX6_MMDC_P0_MDCFG0, 0x54597955 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB + +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 + +DATA 4, MX6_MMDC_P0_MDOR, 0x00591023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 + +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 + +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 + +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43510360 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0342033F +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x033F033F +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03290266 + +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B3E4141 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x47413B4A +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x42404843 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4C3F4C45 + +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00350035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00010001 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00010001 + +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + diff --git a/board/udoo/clocks.cfg b/board/udoo/clocks.cfg new file mode 100644 index 00000000000..9cd1af128f7 --- /dev/null +++ b/board/udoo/clocks.cfg @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF + +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + diff --git a/board/udoo/ddr-setup.cfg b/board/udoo/ddr-setup.cfg new file mode 100644 index 00000000000..78cbe17db4b --- /dev/null +++ b/board/udoo/ddr-setup.cfg @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * DDR3 settings + * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), + * memory bus width: 64 bits x16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 64 bits x16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 32 bits x16/x32 + */ +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 + +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 + +DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 + +DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 + +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 + +/* (differential input) */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +/* (differential input) */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +/* disable ddr pullups */ +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 + +/* Read data DQ Byte0-3 delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + diff --git a/board/udoo/udoo.cfg b/board/udoo/udoo.cfg new file mode 100644 index 00000000000..8d7ff25f7f9 --- /dev/null +++ b/board/udoo/udoo.cfg @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "1066mhz_4x256mx16.cfg" +#include "clocks.cfg" diff --git a/boards.cfg b/boards.cfg index 7a32d3f2c7b..87740de42ef 100644 --- a/boards.cfg +++ b/boards.cfg @@ -285,7 +285,7 @@ Active arm armv7 mx5 freescale mx53smd Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg - Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg - Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic -Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Fabio Estevam +Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam -- cgit v1.3.1 From 078813d21db0600d440625327a1728c32e9fcc90 Mon Sep 17 00:00:00 2001 From: Giuseppe Pagano Date: Fri, 15 Nov 2013 17:42:51 +0100 Subject: udoo: Add ethernet support (FEC + Micrel KSZ9031). Add Ethernet and networking support on uDoo board (FEC +phy Micrel KSZ9031). Ethernet speed is currently limited to 10/100Mbps. Signed-off-by: Giuseppe Pagano Tested-by: Fabio Estevam CC: Stefano Babic CC: Fabio Estevam --- board/udoo/udoo.c | 140 +++++++++++++++++++++++++++++++++++++++++++++++++ include/configs/udoo.h | 16 ++++++ include/micrel.h | 5 ++ 3 files changed, 161 insertions(+) (limited to 'board') diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c index ab7b655e99b..3257aafe1a4 100644 --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -18,6 +19,9 @@ #include #include #include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -25,6 +29,9 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) @@ -58,6 +65,99 @@ static iomux_v3_cfg_t const wdog_pads[] = { MX6_PAD_EIM_D19__GPIO3_IO19, }; +int mx6_rgmii_rework(struct phy_device *phydev) +{ + /* + * Bug: Apparently uDoo does not works with Gigabit switches... + * Limiting speed to 10/100Mbps, and setting master mode, seems to + * be the only way to have a successfull PHY auto negotiation. + * How to fix: Understand why Linux kernel do not have this issue. + */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); + + /* control data pad skew - devaddr = 0x02, register = 0x04 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* rx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* tx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); + return 0; +} + +static iomux_v3_cfg_t const enet_pads1[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* RGMII reset */ + MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* Ethernet power supply */ + MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const enet_pads2[] = { + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + udelay(20); + gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */ + + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */ + + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + udelay(1000); + + gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */ + + /* Need 100ms delay to exit from reset. */ + udelay(1000 * 100); + + gpio_free(IMX_GPIO_NR(6, 24)); + gpio_free(IMX_GPIO_NR(6, 25)); + gpio_free(IMX_GPIO_NR(6, 27)); + gpio_free(IMX_GPIO_NR(6, 28)); + gpio_free(IMX_GPIO_NR(6, 29)); + + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); +} + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); @@ -77,6 +177,37 @@ int board_mmc_getcd(struct mmc *mmc) return 1; /* Always present */ } +int board_eth_init(bd_t *bis) +{ + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + setup_iomux_enet(); + +#ifdef CONFIG_FEC_MXC + bus = fec_get_miibus(base, -1); + if (!bus) + return 0; + /* scan phy 4,5,6,7 */ + phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); + + if (!phydev) { + free(bus); + return 0; + } + printf("using phy at %d\n", phydev->addr); + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + free(phydev); + free(bus); + } +#endif + return 0; +} + int board_mmc_init(bd_t *bis) { imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); @@ -94,6 +225,15 @@ int board_early_init_f(void) return 0; } +int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + int board_init(void) { /* address of boot parameters */ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 78df071795a..b9a493cd1ee 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -34,6 +34,22 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE +/* Network support */ + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 6 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9031 + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 diff --git a/include/micrel.h b/include/micrel.h index e1c62d83cb3..1d72b50ec39 100644 --- a/include/micrel.h +++ b/include/micrel.h @@ -15,6 +15,11 @@ #define MII_KSZ9031_MOD_DATA_POST_INC_RW 0x8000 #define MII_KSZ9031_MOD_DATA_POST_INC_W 0xC000 +#define MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW 0x4 +#define MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW 0x5 +#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6 +#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW 0x8 + struct phy_device; int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val); int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum); -- cgit v1.3.1 From db6801dec36c9e0703c47ec065ee17278edbe904 Mon Sep 17 00:00:00 2001 From: Giuseppe Pagano Date: Fri, 15 Nov 2013 17:42:54 +0100 Subject: udoo: Fix watchdog during kernel boot. uDoo uses APX823-31W5 watchdog chip. Timeout is about 1.2 seconds. To disabled watchdog during kernel boot, WDI pin of that chip needs to be in "high impedance" state. I.mx6 gpio configuration does not contemplate tristate, so pin is set as input in high impedance. Signed-off-by: Giuseppe Pagano Reviewed-by: Fabio Estevam CC: Stefano Babic CC: Fabio Estevam --- board/udoo/udoo.c | 1 + 1 file changed, 1 insertion(+) (limited to 'board') diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c index 3257aafe1a4..081d517f53c 100644 --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -168,6 +168,7 @@ static void setup_iomux_wdog(void) imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); gpio_direction_output(WDT_TRG, 0); gpio_direction_output(WDT_EN, 1); + gpio_direction_input(WDT_TRG); } static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; -- cgit v1.3.1 From 12115c6ad3b91e60b874afd29ce041ef552ed1e1 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 23 Aug 2013 12:26:49 -0400 Subject: am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF Test on Beaglebone white over cpsw, usb ether and SD card (read and write), performance increased, crc32 of data matches. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/board.c | 8 ++++++++ board/siemens/common/board.c | 9 --------- 2 files changed, 8 insertions(+), 9 deletions(-) (limited to 'board') diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 803aa9c5457..c7dad6681d1 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -241,3 +241,11 @@ void s_init(void) sdram_init(); #endif } + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif /* !CONFIG_SYS_DCACHE_OFF */ diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index 32d2ee4de94..7e8731bb3b9 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -159,13 +159,4 @@ U_BOOT_CMD( "Sends U-Boot into infinite loop", "" ); - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - printf("Enable d-cache\n"); - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif /* CONFIG_SYS_DCACHE_OFF */ #endif /* !CONFIG_SPL_BUILD */ -- cgit v1.3.1 From 550e3756c52ae1c93df2a5528ab5ff6d69c7dcdc Mon Sep 17 00:00:00 2001 From: Tapani Utriainen Date: Wed, 4 Dec 2013 09:27:33 +0100 Subject: arm, omap3: Add support for TechNexion modules Add support for TechNexion TAO3530 SoM This patch has been posted quite a long time ago. I ported it to the latest mainline U-Boot version. With some additional cleanup and enhancements. Signed-off-by: Tapani Utriainen CC: Sandeep Paulraj Signed-off-by: Stefan Roese Cc: Thorsten Eisbein Cc: Tom Rini --- board/technexion/tao3530/Makefile | 5 + board/technexion/tao3530/tao3530.c | 170 +++++++++++++++++ board/technexion/tao3530/tao3530.h | 364 +++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/tao3530.h | 301 ++++++++++++++++++++++++++++++ 5 files changed, 841 insertions(+) create mode 100644 board/technexion/tao3530/Makefile create mode 100644 board/technexion/tao3530/tao3530.c create mode 100644 board/technexion/tao3530/tao3530.h create mode 100644 include/configs/tao3530.h (limited to 'board') diff --git a/board/technexion/tao3530/Makefile b/board/technexion/tao3530/Makefile new file mode 100644 index 00000000000..2aff38311cf --- /dev/null +++ b/board/technexion/tao3530/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := tao3530.o diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c new file mode 100644 index 00000000000..0668c256f3d --- /dev/null +++ b/board/technexion/tao3530/tao3530.c @@ -0,0 +1,170 @@ +/* + * Maintainer : + * Tapani Utriainen + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "tao3530.h" + +DECLARE_GLOBAL_DATA_PTR; + +int tao3530_revision(void) +{ + int ret = 0; + + /* char *label argument is unused in gpio_request() */ + ret = gpio_request(65, ""); + if (ret) { + puts("Error: GPIO 65 not available\n"); + goto out; + } + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); + + ret = gpio_request(1, ""); + if (ret) { + puts("Error: GPIO 1 not available\n"); + goto out2; + } + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M4)); + + ret = gpio_direction_input(65); + if (ret) { + puts("Error: GPIO 65 not available for input\n"); + goto out3; + } + + ret = gpio_direction_input(1); + if (ret) { + puts("Error: GPIO 1 not available for input\n"); + goto out3; + } + + ret = gpio_get_value(65) << 1 | gpio_get_value(1); + +out3: + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M0)); + gpio_free(1); +out2: + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); + gpio_free(65); +out: + + return ret; +} + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP3_TAO3530; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: misc_init_r + * Description: Configure board specific parts + */ +int misc_init_r(void) +{ + struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; + struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE; + + twl4030_power_init(); + twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); + + /* Configure GPIOs to output */ + /* GPIO23 */ + writel(~(GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe); + writel(~(GPIO31 | GPIO30 | GPIO22 | GPIO21 | + GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe); + + /* Set GPIOs */ + writel(GPIO10 | GPIO8 | GPIO2 | GPIO1, + &gpio6_base->setdataout); + writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | + GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout); + + dieid_num_r(); + + /* Set memory size environment variable, depending on revision */ + switch (tao3530_revision()) { + case 0x2: /* Rev C1 -- 256MB */ + setenv("mem_size", "mem=256M"); + break; + case 0x3: /* Rev A2/B2 -- 128MB */ + setenv("mem_size", "mem=128M"); + break; + default: + printf("Warning: Unknown TAO3530 rev, setting mem=128M\n"); + } + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_TAO3530(); +} + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0, 0, 0, -1, -1); + + return 0; +} +#endif + +#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD) +/* Call usb_stop() before starting the kernel */ +void show_boot_progress(int val) +{ + if (val == BOOTSTAGE_ID_RUN_OS) + usb_stop(); +} + +static struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED +}; + +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); +} + +int ehci_hcd_stop(int index) +{ + return omap_ehci_hcd_stop(); +} +#endif /* CONFIG_USB_EHCI */ diff --git a/board/technexion/tao3530/tao3530.h b/board/technexion/tao3530/tao3530.h new file mode 100644 index 00000000000..1ea767dbf2f --- /dev/null +++ b/board/technexion/tao3530/tao3530.h @@ -0,0 +1,364 @@ +/* + * (C) Copyright TechNexion 2010 + * Edward Lin + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _TAO3530_H_ +#define _TAO3530_H_ + +const omap3_sysinfo sysinfo = { + DDR_STACKED, + "OMAP3 TAO-3530 board", + "NAND", +}; + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_TAO3530() \ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) \ + /* - CAM_RESET*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ + /*Audio Interface */\ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \ + /*Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) \ + /* MMC2 WLAN */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \ + /*Bluetooth*/\ + MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \ + /*LocalBus LAN Reset*/\ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) \ + /*LocalBus LAN IRQ*/\ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M1)) \ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) \ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) \ + /* USB EHCI (port 2) */\ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) \ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) \ + /* - VIO_1V8*/\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M1)) \ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M1)) \ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M1)) \ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M1)) \ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M1)) \ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) \ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) \ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(ETK_D14_ES2), (IEN|PTU|DIS|M3)) \ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) + +#endif diff --git a/boards.cfg b/boards.cfg index 2128996a1e6..e9d3324c4af 100644 --- a/boards.cfg +++ b/boards.cfg @@ -328,6 +328,7 @@ Active arm armv7 omap3 logicpd zoom1 Active arm armv7 omap3 logicpd zoom2 omap3_zoom2 - Tom Rix Active arm armv7 omap3 matrix_vision mvblx omap3_mvblx - Michael Jones Active arm armv7 omap3 nokia rx51 nokia_rx51 - Pali Rohár +Active arm armv7 omap3 technexion tao3530 tao3530 - Tapani Utriainen Active arm armv7 omap3 technexion twister twister - Stefano Babic Active arm armv7 omap3 teejet mt_ventoux mt_ventoux - Stefano Babic Active arm armv7 omap3 ti am3517crane am3517_crane - Nagendra T S diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h new file mode 100644 index 00000000000..cf20ae78f06 --- /dev/null +++ b/include/configs/tao3530.h @@ -0,0 +1,301 @@ +/* + * Configuration settings for the TechNexion TAO-3530 SOM + * equipped on Thunder baseboard. + * + * Edward Lin + * Tapani Utriainen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ + +#define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON + +#define MACH_TYPE_OMAP3_TAO3530 2836 + +#define CONFIG_SDRC /* Has an SDRC controller */ + +#include /* get chip and board defs */ +#include + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_MISC_INIT_R + +#define CONFIG_OF_LIBFDT + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_DOS_PARTITION + +/* commands to include */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ + "1920k(u-boot),128k(u-boot-env),"\ + "4m(kernel),-(fs)" + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_OMAP34XX +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_I2C_MULTI_BUS + +/* + * TWL4030 + */ +#define CONFIG_TWL4030_POWER +#define CONFIG_TWL4030_LED + +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_QUIET_TEST +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand at */ + /* CS0 */ +#define GPMC_NAND_ECC_LP_x16_LAYOUT + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ + /* devices */ +/* Environment information */ +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyO2,115200n8\0" \ + "mpurate=600\0" \ + "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ + "tv_mode=omapfb.mode=tv:ntsc\0" \ + "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ + "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ + "extra_options= \0" \ + "mem_size=mem=128M \0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "nandroot=ubi0:rootfs ubi.mtd=4\0" \ + "nandrootfstype=ubifs\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${mem_size} " \ + "mpurate=${mpurate} " \ + "${video_mode} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype} " \ + "${extra_options}\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${mem_size} " \ + "mpurate=${mpurate} " \ + "${video_mode} " \ + "${network_setting} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype} "\ + "${extra_options}\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT "TAO-3530 # " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* turn on command-line edit/hist/auto */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_COMMAND_HISTORY +#define CONFIG_AUTO_COMPLETE + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_SYS_ALT_MEMTEST 1 +#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ + /* defaults */ +#define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ +#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ + /* load address */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ +#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define CONFIG_ENV_IS_IN_NAND 1 +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_OMAP3_SPI + +/* + * USB + * + * Currently only EHCI is enabled, the MUSB OTG controller + * is not enabled. + */ + +/* USB EHCI */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 + +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX + +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETHER_RNDIS +#define CONFIG_USB_STORAGE +#define CONGIG_CMD_STORAGE + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From a9f524904730a0f722483938bf7eb8baedbc2448 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 4 Dec 2013 09:27:34 +0100 Subject: arm: omap3: Add SPL support to tao3530 Add SPL support for the Technexion TAO3530 SOM to replace x-loader. Tested with the Thunder baseboard. Currently this is only tested with the TAO3530 SOM revision (Ax/Bx). Tested by booting via MMC and NAND. Signed-off-by: Stefan Roese Cc: Tapani Utriainen Cc: Thorsten Eisbein Cc: Tom Rini --- board/technexion/tao3530/tao3530.c | 27 +++++++++++++++- include/configs/tao3530.h | 65 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c index 0668c256f3d..9268d388776 100644 --- a/board/technexion/tao3530/tao3530.c +++ b/board/technexion/tao3530/tao3530.c @@ -67,6 +67,31 @@ out: return ret; } +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ + if (tao3530_revision() < 3) { + /* 256MB / Bank */ + timings->mcfg = MCFG(256 << 20, 14); /* RAS-width 14 */ + timings->ctrla = HYNIX_V_ACTIMA_165; + timings->ctrlb = HYNIX_V_ACTIMB_165; + } else { + /* 128MB / Bank */ + timings->mcfg = MCFG(128 << 20, 13); /* RAS-width 13 */ + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + } + + timings->mr = MICRON_V_MR_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; +} +#endif + /* * Routine: board_init * Description: Early hardware init. @@ -134,7 +159,7 @@ void set_muxconf_regs(void) MUX_TAO3530(); } -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0, 0, 0, -1, -1); diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index cf20ae78f06..fdc6c066da0 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -5,6 +5,8 @@ * Edward Lin * Tapani Utriainen * + * Copyright (C) 2013 Stefan Roese + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -298,4 +300,67 @@ #define CONFIG_USB_STORAGE #define CONGIG_CMD_STORAGE +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_NAND_SIMPLE + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_OMAP3_ID_NAND +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +/* + * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: + * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT + */ +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13 } +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +/* + * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the + * older x-loader implementations. And move the BSS area so that it + * doesn't overlap with TEXT_BASE. + */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + #endif /* __CONFIG_H */ -- cgit v1.3.1 From b36f457c1bc726f4452fdc55230a067c1704eaf8 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 4 Dec 2013 09:27:35 +0100 Subject: arm: omap3: Remove bootargs mem_size handling The memory size is autodetected and is passed to the Linux kernel either via ATAGs or device-tree (dtb). So there is no need to pass it via the bootargs. Signed-off-by: Stefan Roese Cc: Tapani Utriainen Cc: Thorsten Eisbein Cc: Tom Rini --- board/technexion/tao3530/tao3530.c | 12 ------------ include/configs/tao3530.h | 3 --- 2 files changed, 15 deletions(-) (limited to 'board') diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c index 9268d388776..814537bd7a8 100644 --- a/board/technexion/tao3530/tao3530.c +++ b/board/technexion/tao3530/tao3530.c @@ -133,18 +133,6 @@ int misc_init_r(void) dieid_num_r(); - /* Set memory size environment variable, depending on revision */ - switch (tao3530_revision()) { - case 0x2: /* Rev C1 -- 256MB */ - setenv("mem_size", "mem=256M"); - break; - case 0x3: /* Rev A2/B2 -- 128MB */ - setenv("mem_size", "mem=128M"); - break; - default: - printf("Warning: Unknown TAO3530 rev, setting mem=128M\n"); - } - return 0; } diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index fdc6c066da0..9abfe829022 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -146,21 +146,18 @@ "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ "extra_options= \0" \ - "mem_size=mem=128M \0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ "mmcrootfstype=ext3 rootwait\0" \ "nandroot=ubi0:rootfs ubi.mtd=4\0" \ "nandrootfstype=ubifs\0" \ "mmcargs=setenv bootargs console=${console} " \ - "${mem_size} " \ "mpurate=${mpurate} " \ "${video_mode} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype} " \ "${extra_options}\0" \ "nandargs=setenv bootargs console=${console} " \ - "${mem_size} " \ "mpurate=${mpurate} " \ "${video_mode} " \ "${network_setting} " \ -- cgit v1.3.1 From fcd9adc3c698349cf23b2561cdb58ca805fc9817 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 4 Dec 2013 09:27:36 +0100 Subject: arm: omap3: Add board revision output to tao3530 Signed-off-by: Stefan Roese Cc: Tapani Utriainen Cc: Thorsten Eisbein Cc: Tom Rini --- board/technexion/tao3530/tao3530.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'board') diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c index 814537bd7a8..5041eaf7d30 100644 --- a/board/technexion/tao3530/tao3530.c +++ b/board/technexion/tao3530/tao3530.c @@ -131,6 +131,23 @@ int misc_init_r(void) writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout); + switch (tao3530_revision()) { + case 0: + puts("TAO-3530 REV Reserve 1\n"); + break; + case 1: + puts("TAO-3530 REV Reserve 2\n"); + break; + case 2: + puts("TAO-3530 REV Cx\n"); + break; + case 3: + puts("TAO-3530 REV Ax/Bx\n"); + break; + default: + puts("Unknown board revision\n"); + } + dieid_num_r(); return 0; -- cgit v1.3.1 From 8f0cbd62edb6fad4d62272ef3f76b3dd74c3a1ad Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 4 Dec 2013 09:27:37 +0100 Subject: arm: omap3: Add HEAD acoustics (HA) board variant omap3_ha to tao3530 The Head acoustics (HA) baseboard used the Technexion TAO3530 SOM and has only some minor differences to the Technexion Thunder baseboard. This patch adds support for this HA baseboard / TAO3530 as the "omap3_ha" build target. Signed-off-by: Stefan Roese Cc: Tapani Utriainen Cc: Thorsten Eisbein Cc: Tom Rini --- board/technexion/tao3530/tao3530.c | 15 +++++++++++++++ board/technexion/tao3530/tao3530.h | 7 +++++++ boards.cfg | 1 + 3 files changed, 23 insertions(+) (limited to 'board') diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c index 5041eaf7d30..44a82406aa9 100644 --- a/board/technexion/tao3530/tao3530.c +++ b/board/technexion/tao3530/tao3530.c @@ -75,6 +75,18 @@ out: */ void get_board_mem_timings(struct board_sdrc_timings *timings) { +#if defined(CONFIG_SYS_BOARD_OMAP3_HA) + /* + * Switch baseboard LED to red upon power-on + */ + MUX_OMAP3_HA(); + + /* Request a gpio before using it */ + gpio_request(111, ""); + /* Sets the gpio as output and its value to 1, switch LED to red */ + gpio_direction_output(111, 1); +#endif + if (tao3530_revision() < 3) { /* 256MB / Bank */ timings->mcfg = MCFG(256 << 20, 14); /* RAS-width 14 */ @@ -162,6 +174,9 @@ int misc_init_r(void) void set_muxconf_regs(void) { MUX_TAO3530(); +#if defined(CONFIG_SYS_BOARD_OMAP3_HA) + MUX_OMAP3_HA(); +#endif } #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) diff --git a/board/technexion/tao3530/tao3530.h b/board/technexion/tao3530/tao3530.h index 1ea767dbf2f..daff1094802 100644 --- a/board/technexion/tao3530/tao3530.h +++ b/board/technexion/tao3530/tao3530.h @@ -9,7 +9,11 @@ const omap3_sysinfo sysinfo = { DDR_STACKED, +#if defined(CONFIG_SYS_BOARD_OMAP3_HA) + "HEAD acoustics OMAP3-HA", +#else "OMAP3 TAO-3530 board", +#endif "NAND", }; @@ -361,4 +365,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) \ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) +#define MUX_OMAP3_HA() \ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M4)) /* GPIO_111 */ + #endif diff --git a/boards.cfg b/boards.cfg index e9d3324c4af..b662149e669 100644 --- a/boards.cfg +++ b/boards.cfg @@ -328,6 +328,7 @@ Active arm armv7 omap3 logicpd zoom1 Active arm armv7 omap3 logicpd zoom2 omap3_zoom2 - Tom Rix Active arm armv7 omap3 matrix_vision mvblx omap3_mvblx - Michael Jones Active arm armv7 omap3 nokia rx51 nokia_rx51 - Pali Rohár +Active arm armv7 omap3 technexion tao3530 omap3_ha tao3530:SYS_BOARD_OMAP3_HA Stefan Roese Active arm armv7 omap3 technexion tao3530 tao3530 - Tapani Utriainen Active arm armv7 omap3 technexion twister twister - Stefano Babic Active arm armv7 omap3 teejet mt_ventoux mt_ventoux - Stefano Babic -- cgit v1.3.1 From 3e51b7c8b8b076dc5115ca4b6a457f55f6de3cae Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 4 Dec 2013 13:54:18 +0100 Subject: arm: omap3: Add SPL support to cm_t35 Add SPL U-Boot support to replace x-loader on the Compulab cm_t35 board. Currently only the 256MiB SDRAM board versions are supported. Tested by booting via MMC and NAND. Signed-off-by: Stefan Roese Cc: Tom Rini Cc: Igor Grinberg Cc: Nikita Kiryanov Acked-by: Igor Grinberg --- board/compulab/cm_t35/cm_t35.c | 18 +++++++++++- include/configs/cm_t35.h | 65 ++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 80 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index bc8e0cad949..00bcf41bb3b 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -105,6 +105,22 @@ static inline int splash_load_from_nand(void) } #endif /* CONFIG_CMD_NAND */ +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ + timings->mr = MICRON_V_MR_165; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */ + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; +} +#endif + int splash_screen_prepare(void) { char *env_splashimage_value; @@ -440,7 +456,7 @@ void set_muxconf_regs(void) cm_t3730_set_muxconf(); } -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_getcd(struct mmc *mmc) { u8 val; diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index e72187e30bc..29178199155 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -27,8 +27,6 @@ #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ #define CONFIG_OMAP_COMMON -#define CONFIG_SYS_TEXT_BASE 0x80008000 - #define CONFIG_SDRC /* The chip has SDRC controller */ #include /* get chip and board defs */ @@ -330,4 +328,67 @@ #define CONFIG_OMAP3_SPI +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_NAND_SIMPLE + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_OMAP3_ID_NAND +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +/* + * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: + * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT + */ +#define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12 } +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +/* + * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the + * older x-loader implementations. And move the BSS area so that it + * doesn't overlap with TEXT_BASE. + */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + #endif /* __CONFIG_H */ -- cgit v1.3.1 From 6a1df37349d6a01c505ffe5e11e5f623f3d9652e Mon Sep 17 00:00:00 2001 From: Yegor Yefremov Date: Wed, 11 Dec 2013 15:41:11 +0100 Subject: am3517_evm: activate Ethernet PHY Pin 30 is connected to PHY's RESET# signal, so it must be put to high. Otherwise PHY won't be found via MDIO interface. Signed-off-by: Yegor Yefremov --- board/logicpd/am3517evm/am3517evm.c | 32 ++++++++++++++++++++++++++++++++ board/logicpd/am3517evm/am3517evm.h | 2 +- include/configs/am3517_evm.h | 5 +++++ 3 files changed, 38 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index 15699054603..24be6eabfcd 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -31,6 +32,9 @@ DECLARE_GLOBAL_DATA_PTR; +#define AM3517_IP_SW_RESET 0x48002598 +#define CPGMACSS_SW_RST (1 << 1) + /* * Routine: board_init * Description: Early hardware init. @@ -98,6 +102,9 @@ static void am3517_evm_musb_init(void) */ int misc_init_r(void) { + volatile unsigned int ctr; + u32 reset; + #ifdef CONFIG_SYS_I2C_OMAP34XX i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif @@ -106,6 +113,31 @@ int misc_init_r(void) am3517_evm_musb_init(); + /* activate PHY reset */ + gpio_direction_output(30, 0); + gpio_set_value(30, 0); + + ctr = 0; + do { + udelay(1000); + ctr++; + } while (ctr < 300); + + /* deactivate PHY reset */ + gpio_set_value(30, 1); + + /* allow the PHY to stabilize and settle down */ + ctr = 0; + do { + udelay(1000); + ctr++; + } while (ctr < 300); + + /* ensure that the module is out of reset */ + reset = readl(AM3517_IP_SW_RESET); + reset &= (~CPGMACSS_SW_RST); + writel(reset,AM3517_IP_SW_RESET); + return 0; } diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h index 704af847a73..d407d66ae69 100644 --- a/board/logicpd/am3517evm/am3517evm.h +++ b/board/logicpd/am3517evm/am3517evm.h @@ -315,7 +315,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ /*SYS_nRESWARM */\ - MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \ + MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | EN | M4)) \ /* - GPIO30 */\ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ /* - PEN_IRQ */\ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 1fa477aac83..b8b99c806fa 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -57,6 +57,11 @@ * Hardware drivers */ +/* + * OMAP GPIO configuration + */ +#define CONFIG_OMAP_GPIO + /* * NS16550 Configuration */ -- cgit v1.3.1 From 570aa2fac3322e2e8c9dc5b4c1ac4ac95c22f9f6 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 20 Nov 2013 21:17:36 -0200 Subject: imx: Explicitly pass the I2C bus number in pmic_init() The pmic_init() function has the I2C or SPI bus number that is connected to the PMIC. Instead of passing I2C_PMIC, explicitly pass the I2C bus number via I2C_x definition. The motivation for doing this is to avoid people just doing a copy and paste of I2C_PMIC into their board file when another I2C bus is actually used to interface to their PMIC. This also makes more obvious which is the I2C bus connected to the PMIC, without having to search in the source code for the meaning of the 'I2C_PMIC' number. Signed-off-by: Fabio Estevam Acked-by: Stefano Babic --- board/freescale/mx25pdk/mx25pdk.c | 2 +- board/freescale/mx35pdk/mx35pdk.c | 2 +- board/freescale/mx53evk/mx53evk.c | 2 +- board/freescale/mx53loco/mx53loco.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c index ebe3bcb6edd..71a395c226c 100644 --- a/board/freescale/mx25pdk/mx25pdk.c +++ b/board/freescale/mx25pdk/mx25pdk.c @@ -138,7 +138,7 @@ int board_late_init(void) mx25pdk_fec_init(); - ret = pmic_init(I2C_PMIC); + ret = pmic_init(I2C_0); if (ret) return ret; diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index 9fabef5af57..12467a9adae 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -213,7 +213,7 @@ int board_late_init(void) struct pmic *p; int ret; - ret = pmic_init(I2C_PMIC); + ret = pmic_init(I2C_0); if (ret) return ret; diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c index 3b398b6d76e..13519e26da2 100644 --- a/board/freescale/mx53evk/mx53evk.c +++ b/board/freescale/mx53evk/mx53evk.c @@ -81,7 +81,7 @@ void power_init(void) struct pmic *p; int ret; - ret = pmic_init(I2C_PMIC); + ret = pmic_init(I2C_0); if (ret) return; diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index ae7eca85b08..db0bf17363e 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -258,7 +258,7 @@ static int power_init(void) } if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) { - ret = pmic_init(I2C_PMIC); + ret = pmic_init(I2C_0); if (ret) return ret; -- cgit v1.3.1 From b47abc36aaa4695ed50226ca1f3bd8f0b58bdaa6 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Wed, 13 Nov 2013 16:36:19 -0700 Subject: i.MX6 (DQ/DLS): use macros for mux and pad declarations This allows the use of either or both declarations from the files mx6q_pins.h and mx6dl_pins.h. All board files should include with one of the following defined in boards.cfg MX6Q - for boards targeting i.MX6Q or i.MX6D MX6DL - for boards targeting i.MX6DL MX6S - for boards targeting i.MX6S MX6QDL - for boards that support any of the above with run-time detection Pad declarations will be MX6_PAD_x for single-variant boards and MX6Q_PAD_x and MX6DL_PAD_x for boards supporting both processor classes. Signed-off-by: Eric Nelson Acked-by: Stefano Babic --- arch/arm/include/asm/arch-mx6/mx6-pins.h | 33 +- arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 2141 ++++++++++++------------- arch/arm/include/asm/arch-mx6/mx6q_pins.h | 2050 ++++++++++++----------- board/barco/titanium/titanium.c | 2 +- board/freescale/mx6qarm2/mx6qarm2.c | 2 +- board/freescale/mx6qsabreauto/mx6qsabreauto.c | 2 +- 6 files changed, 2121 insertions(+), 2109 deletions(-) (limited to 'board') diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h index 1c9e3fe2041..dcd7f8f3278 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h @@ -6,18 +6,37 @@ #ifndef __ASM_ARCH_MX6_PINS_H__ #define __ASM_ARCH_MX6_PINS_H__ -#ifdef CONFIG_MX6Q +#include + +#define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \ + prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc) + +#ifdef CONFIG_MX6QDL +enum { +#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ + MX6_PAD_DECLARE(MX6Q_PAD_,name, pco, mc, mm, sio, si, pc), #include "mx6q_pins.h" -#else -#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +#undef MX6_PAD_DECL +#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ + MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc), #include "mx6dl_pins.h" -#else -#if defined(CONFIG_MX6SL) +}; +#elif defined(CONFIG_MX6Q) +enum { +#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ + MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc), +#include "mx6q_pins.h" +}; +#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +enum { +#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ + MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc), +#include "mx6dl_pins.h" +}; +#elif defined(CONFIG_MX6SL) #include "mx6sl_pins.h" #else #error "Please select cpu" -#endif /* CONFIG_MX6SL */ -#endif /* CONFIG_MX6DL or CONFIG_MX6S */ #endif /* CONFIG_MX6Q */ #endif /*__ASM_ARCH_MX6_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index d194eb03e4f..55cc9ad6fc0 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -7,1077 +7,1074 @@ #ifndef __ASM_ARCH_MX6_MX6DL_PINS_H__ #define __ASM_ARCH_MX6_MX6DL_PINS_H__ -#include +MX6_PAD_DECL(CSI0_DAT10__IPU1_CSI0_DATA10, 0x0360, 0x004C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__AUD3_RXC, 0x0360, 0x004C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__ECSPI2_MISO, 0x0360, 0x004C, 2, 0x07F8, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__UART1_TX_DATA, 0x0360, 0x004C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__UART1_RX_DATA, 0x0360, 0x004C, 3, 0x08FC, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__GPIO5_IO28, 0x0360, 0x004C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__ARM_TRACE07, 0x0360, 0x004C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__IPU1_CSI0_DATA11, 0x0364, 0x0050, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__AUD3_RXFS, 0x0364, 0x0050, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__ECSPI2_SS0, 0x0364, 0x0050, 2, 0x0800, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__UART1_TX_DATA, 0x0364, 0x0050, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__UART1_RX_DATA, 0x0364, 0x0050, 3, 0x08FC, 1, 0) +MX6_PAD_DECL(CSI0_DAT11__GPIO5_IO29, 0x0364, 0x0050, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__ARM_TRACE08, 0x0364, 0x0050, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__IPU1_CSI0_DATA12, 0x0368, 0x0054, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__EIM_DATA08, 0x0368, 0x0054, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__UART4_TX_DATA, 0x0368, 0x0054, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__UART4_RX_DATA, 0x0368, 0x0054, 3, 0x0914, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__GPIO5_IO30, 0x0368, 0x0054, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__ARM_TRACE09, 0x0368, 0x0054, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__IPU1_CSI0_DATA13, 0x036C, 0x0058, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__EIM_DATA09, 0x036C, 0x0058, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__UART4_TX_DATA, 0x036C, 0x0058, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__UART4_RX_DATA, 0x036C, 0x0058, 3, 0x0914, 1, 0) +MX6_PAD_DECL(CSI0_DAT13__GPIO5_IO31, 0x036C, 0x0058, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__ARM_TRACE10, 0x036C, 0x0058, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__IPU1_CSI0_DATA14, 0x0370, 0x005C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__EIM_DATA10, 0x0370, 0x005C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__UART5_TX_DATA, 0x0370, 0x005C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__UART5_RX_DATA, 0x0370, 0x005C, 3, 0x091C, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__GPIO6_IO00, 0x0370, 0x005C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__ARM_TRACE11, 0x0370, 0x005C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__IPU1_CSI0_DATA15, 0x0374, 0x0060, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__EIM_DATA11, 0x0374, 0x0060, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__UART5_TX_DATA, 0x0374, 0x0060, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__UART5_RX_DATA, 0x0374, 0x0060, 3, 0x091C, 1, 0) +MX6_PAD_DECL(CSI0_DAT15__GPIO6_IO01, 0x0374, 0x0060, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__ARM_TRACE12, 0x0374, 0x0060, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__IPU1_CSI0_DATA16, 0x0378, 0x0064, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__EIM_DATA12, 0x0378, 0x0064, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__UART4_CTS_B, 0x0378, 0x0064, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__UART4_RTS_B, 0x0378, 0x0064, 3, 0x0910, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__GPIO6_IO02, 0x0378, 0x0064, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__ARM_TRACE13, 0x0378, 0x0064, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__IPU1_CSI0_DATA17, 0x037C, 0x0068, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__EIM_DATA13, 0x037C, 0x0068, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__UART4_CTS_B, 0x037C, 0x0068, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__UART4_RTS_B, 0x037C, 0x0068, 3, 0x0910, 1, 0) +MX6_PAD_DECL(CSI0_DAT17__GPIO6_IO03, 0x037C, 0x0068, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__ARM_TRACE14, 0x037C, 0x0068, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__IPU1_CSI0_DATA18, 0x0380, 0x006C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__EIM_DATA14, 0x0380, 0x006C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__UART5_CTS_B, 0x0380, 0x006C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__UART5_RTS_B, 0x0380, 0x006C, 3, 0x0918, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__GPIO6_IO04, 0x0380, 0x006C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__ARM_TRACE15, 0x0380, 0x006C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__IPU1_CSI0_DATA19, 0x0384, 0x0070, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__EIM_DATA15, 0x0384, 0x0070, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__UART5_CTS_B, 0x0384, 0x0070, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__UART5_RTS_B, 0x0384, 0x0070, 3, 0x0918, 1, 0) +MX6_PAD_DECL(CSI0_DAT19__GPIO6_IO05, 0x0384, 0x0070, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__IPU1_CSI0_DATA04, 0x0388, 0x0074, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__EIM_DATA02, 0x0388, 0x0074, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__ECSPI1_SCLK, 0x0388, 0x0074, 2, 0x07D8, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__KEY_COL5, 0x0388, 0x0074, 3, 0x08C0, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__AUD3_TXC, 0x0388, 0x0074, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__GPIO5_IO22, 0x0388, 0x0074, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__ARM_TRACE01, 0x0388, 0x0074, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__IPU1_CSI0_DATA05, 0x038C, 0x0078, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__EIM_DATA03, 0x038C, 0x0078, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__ECSPI1_MOSI, 0x038C, 0x0078, 2, 0x07E0, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__KEY_ROW5, 0x038C, 0x0078, 3, 0x08CC, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__AUD3_TXD, 0x038C, 0x0078, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__GPIO5_IO23, 0x038C, 0x0078, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__ARM_TRACE02, 0x038C, 0x0078, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__IPU1_CSI0_DATA06, 0x0390, 0x007C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__EIM_DATA04, 0x0390, 0x007C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__ECSPI1_MISO, 0x0390, 0x007C, 2, 0x07DC, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__KEY_COL6, 0x0390, 0x007C, 3, 0x08C4, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__AUD3_TXFS, 0x0390, 0x007C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__GPIO5_IO24, 0x0390, 0x007C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__ARM_TRACE03, 0x0390, 0x007C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__IPU1_CSI0_DATA07, 0x0394, 0x0080, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__EIM_DATA05, 0x0394, 0x0080, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__ECSPI1_SS0, 0x0394, 0x0080, 2, 0x07E4, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__KEY_ROW6, 0x0394, 0x0080, 3, 0x08D0, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__AUD3_RXD, 0x0394, 0x0080, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__GPIO5_IO25, 0x0394, 0x0080, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__ARM_TRACE04, 0x0394, 0x0080, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__IPU1_CSI0_DATA08, 0x0398, 0x0084, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__EIM_DATA06, 0x0398, 0x0084, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__ECSPI2_SCLK, 0x0398, 0x0084, 2, 0x07F4, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__KEY_COL7, 0x0398, 0x0084, 3, 0x08C8, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__I2C1_SDA, 0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__GPIO5_IO26, 0x0398, 0x0084, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__ARM_TRACE05, 0x0398, 0x0084, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__IPU1_CSI0_DATA09, 0x039C, 0x0088, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__EIM_DATA07, 0x039C, 0x0088, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__ECSPI2_MOSI, 0x039C, 0x0088, 2, 0x07FC, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__KEY_ROW7, 0x039C, 0x0088, 3, 0x08D4, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__I2C1_SCL, 0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__GPIO5_IO27, 0x039C, 0x0088, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__ARM_TRACE06, 0x039C, 0x0088, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__IPU1_CSI0_DATA_EN, 0x03A0, 0x008C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__EIM_DATA00, 0x03A0, 0x008C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__GPIO5_IO20, 0x03A0, 0x008C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__ARM_TRACE_CLK, 0x03A0, 0x008C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__IPU1_CSI0_HSYNC, 0x03A4, 0x0090, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__CCM_CLKO1, 0x03A4, 0x0090, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__GPIO5_IO19, 0x03A4, 0x0090, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__ARM_TRACE_CTL, 0x03A4, 0x0090, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK, 0x03A8, 0x0094, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__GPIO5_IO18, 0x03A8, 0x0094, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__ARM_EVENTO, 0x03A8, 0x0094, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__IPU1_CSI0_VSYNC, 0x03AC, 0x0098, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__EIM_DATA01, 0x03AC, 0x0098, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__GPIO5_IO21, 0x03AC, 0x0098, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__ARM_TRACE00, 0x03AC, 0x0098, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, 0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_DISP_CLK__LCD_CLK, 0x03B0, 0x009C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__GPIO4_IO16, 0x03B0, 0x009C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__LCD_WR_RWN, 0x03B0, 0x009C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__IPU1_DI0_PIN15, 0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN15__LCD_ENABLE, 0x03B4, 0x00A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__AUD6_TXC, 0x03B4, 0x00A0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__GPIO4_IO17, 0x03B4, 0x00A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__LCD_RD_E, 0x03B4, 0x00A0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__IPU1_DI0_PIN02, 0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN2__LCD_HSYNC, 0x03B8, 0x00A4, 1, 0x08D8, 0, 0) +MX6_PAD_DECL(DI0_PIN2__AUD6_TXD, 0x03B8, 0x00A4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__GPIO4_IO18, 0x03B8, 0x00A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__LCD_RS, 0x03B8, 0x00A4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__IPU1_DI0_PIN03, 0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN3__LCD_VSYNC, 0x03BC, 0x00A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__AUD6_TXFS, 0x03BC, 0x00A8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__GPIO4_IO19, 0x03BC, 0x00A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__LCD_CS, 0x03BC, 0x00A8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__IPU1_DI0_PIN04, 0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN4__LCD_BUSY, 0x03C0, 0x00AC, 1, 0x08D8, 1, 0) +MX6_PAD_DECL(DI0_PIN4__AUD6_RXD, 0x03C0, 0x00AC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__SD1_WP, 0x03C0, 0x00AC, 3, 0x092C, 0, 0) +MX6_PAD_DECL(DI0_PIN4__GPIO4_IO20, 0x03C0, 0x00AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__LCD_RESET, 0x03C0, 0x00AC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__IPU1_DISP0_DATA00, 0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT0__LCD_DATA00, 0x03C4, 0x00B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__ECSPI3_SCLK, 0x03C4, 0x00B0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__GPIO4_IO21, 0x03C4, 0x00B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01, 0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT1__LCD_DATA01, 0x03C8, 0x00B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI, 0x03C8, 0x00B4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22, 0x03C8, 0x00B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10, 0x03CC, 0x00B8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT10__LCD_DATA10, 0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31, 0x03CC, 0x00B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11, 0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT11__LCD_DATA11, 0x03D0, 0x00BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT11__GPIO5_IO05, 0x03D0, 0x00BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT12__IPU1_DISP0_DATA12, 0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT12__LCD_DATA12, 0x03D4, 0x00C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT12__GPIO5_IO06, 0x03D4, 0x00C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__IPU1_DISP0_DATA13, 0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT13__LCD_DATA13, 0x03D8, 0x00C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__AUD5_RXFS, 0x03D8, 0x00C4, 3, 0x07BC, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__GPIO5_IO07, 0x03D8, 0x00C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__IPU1_DISP0_DATA14, 0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT14__LCD_DATA14, 0x03DC, 0x00C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__AUD5_RXC, 0x03DC, 0x00C8, 3, 0x07B8, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__GPIO5_IO08, 0x03DC, 0x00C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__IPU1_DISP0_DATA15, 0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT15__LCD_DATA15, 0x03E0, 0x00CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__ECSPI1_SS1, 0x03E0, 0x00CC, 2, 0x07E8, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__ECSPI2_SS1, 0x03E0, 0x00CC, 3, 0x0804, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__GPIO5_IO09, 0x03E0, 0x00CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__IPU1_DISP0_DATA16, 0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT16__LCD_DATA16, 0x03E4, 0x00D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__ECSPI2_MOSI, 0x03E4, 0x00D0, 2, 0x07FC, 1, 0) +MX6_PAD_DECL(DISP0_DAT16__AUD5_TXC, 0x03E4, 0x00D0, 3, 0x07C0, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__SDMA_EXT_EVENT0, 0x03E4, 0x00D0, 4, 0x08E8, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__GPIO5_IO10, 0x03E4, 0x00D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__IPU1_DISP0_DATA17, 0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT17__LCD_DATA17, 0x03E8, 0x00D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__ECSPI2_MISO, 0x03E8, 0x00D4, 2, 0x07F8, 1, 0) +MX6_PAD_DECL(DISP0_DAT17__AUD5_TXD, 0x03E8, 0x00D4, 3, 0x07B4, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__SDMA_EXT_EVENT1, 0x03E8, 0x00D4, 4, 0x08EC, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__GPIO5_IO11, 0x03E8, 0x00D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__IPU1_DISP0_DATA18, 0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT18__LCD_DATA18, 0x03EC, 0x00D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__ECSPI2_SS0, 0x03EC, 0x00D8, 2, 0x0800, 1, 0) +MX6_PAD_DECL(DISP0_DAT18__AUD5_TXFS, 0x03EC, 0x00D8, 3, 0x07C4, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__AUD4_RXFS, 0x03EC, 0x00D8, 4, 0x07A4, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__GPIO5_IO12, 0x03EC, 0x00D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__EIM_CS2_B, 0x03EC, 0x00D8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__IPU1_DISP0_DATA19, 0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT19__LCD_DATA19, 0x03F0, 0x00DC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__ECSPI2_SCLK, 0x03F0, 0x00DC, 2, 0x07F4, 1, 0) +MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD, 0x03F0, 0x00DC, 3, 0x07B0, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC, 0x03F0, 0x00DC, 4, 0x07A0, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13, 0x03F0, 0x00DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B, 0x03F0, 0x00DC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02, 0x03F4, 0x00E0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__LCD_DATA02, 0x03F4, 0x00E0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO, 0x03F4, 0x00E0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23, 0x03F4, 0x00E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__IPU1_DISP0_DATA20, 0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT20__LCD_DATA20, 0x03F8, 0x00E4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__ECSPI1_SCLK, 0x03F8, 0x00E4, 2, 0x07D8, 1, 0) +MX6_PAD_DECL(DISP0_DAT20__AUD4_TXC, 0x03F8, 0x00E4, 3, 0x07A8, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__GPIO5_IO14, 0x03F8, 0x00E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__IPU1_DISP0_DATA21, 0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT21__LCD_DATA21, 0x03FC, 0x00E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__ECSPI1_MOSI, 0x03FC, 0x00E8, 2, 0x07E0, 1, 0) +MX6_PAD_DECL(DISP0_DAT21__AUD4_TXD, 0x03FC, 0x00E8, 3, 0x079C, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__GPIO5_IO15, 0x03FC, 0x00E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__IPU1_DISP0_DATA22, 0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT22__LCD_DATA22, 0x0400, 0x00EC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__ECSPI1_MISO, 0x0400, 0x00EC, 2, 0x07DC, 1, 0) +MX6_PAD_DECL(DISP0_DAT22__AUD4_TXFS, 0x0400, 0x00EC, 3, 0x07AC, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__GPIO5_IO16, 0x0400, 0x00EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__IPU1_DISP0_DATA23, 0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT23__LCD_DATA23, 0x0404, 0x00F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__ECSPI1_SS0, 0x0404, 0x00F0, 2, 0x07E4, 1, 0) +MX6_PAD_DECL(DISP0_DAT23__AUD4_RXD, 0x0404, 0x00F0, 3, 0x0798, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__GPIO5_IO17, 0x0404, 0x00F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__IPU1_DISP0_DATA03, 0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT3__LCD_DATA03, 0x0408, 0x00F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__ECSPI3_SS0, 0x0408, 0x00F4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__GPIO4_IO24, 0x0408, 0x00F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__IPU1_DISP0_DATA04, 0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT4__LCD_DATA04, 0x040C, 0x00F8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__ECSPI3_SS1, 0x040C, 0x00F8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__GPIO4_IO25, 0x040C, 0x00F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__IPU1_DISP0_DATA05, 0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT5__LCD_DATA05, 0x0410, 0x00FC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__ECSPI3_SS2, 0x0410, 0x00FC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__AUD6_RXFS, 0x0410, 0x00FC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__GPIO4_IO26, 0x0410, 0x00FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__IPU1_DISP0_DATA06, 0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT6__LCD_DATA06, 0x0414, 0x0100, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__ECSPI3_SS3, 0x0414, 0x0100, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__AUD6_RXC, 0x0414, 0x0100, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__GPIO4_IO27, 0x0414, 0x0100, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__IPU1_DISP0_DATA07, 0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT7__LCD_DATA07, 0x0418, 0x0104, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__ECSPI3_RDY, 0x0418, 0x0104, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__GPIO4_IO28, 0x0418, 0x0104, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__IPU1_DISP0_DATA08, 0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT8__LCD_DATA08, 0x041C, 0x0108, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__PWM1_OUT, 0x041C, 0x0108, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__WDOG1_B, 0x041C, 0x0108, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__GPIO4_IO29, 0x041C, 0x0108, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__IPU1_DISP0_DATA09, 0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT9__LCD_DATA09, 0x0420, 0x010C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__PWM2_OUT, 0x0420, 0x010C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__WDOG2_B, 0x0420, 0x010C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__GPIO4_IO30, 0x0420, 0x010C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__EIM_ADDR16, 0x04E0, 0x0110, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__IPU1_DI1_DISP_CLK, 0x04E0, 0x0110, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__IPU1_CSI1_PIXCLK, 0x04E0, 0x0110, 2, 0x08B8, 0, 0) +MX6_PAD_DECL(EIM_A16__GPIO2_IO22, 0x04E0, 0x0110, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__SRC_BOOT_CFG16, 0x04E0, 0x0110, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__EPDC_DATA00, 0x04E0, 0x0110, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__EIM_ADDR17, 0x04E4, 0x0114, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__IPU1_DISP1_DATA12, 0x04E4, 0x0114, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__IPU1_CSI1_DATA12, 0x04E4, 0x0114, 2, 0x0890, 0, 0) +MX6_PAD_DECL(EIM_A17__GPIO2_IO21, 0x04E4, 0x0114, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__SRC_BOOT_CFG17, 0x04E4, 0x0114, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__EPDC_PWR_STAT, 0x04E4, 0x0114, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__EIM_ADDR18, 0x04E8, 0x0118, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__IPU1_DISP1_DATA13, 0x04E8, 0x0118, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__IPU1_CSI1_DATA13, 0x04E8, 0x0118, 2, 0x0894, 0, 0) +MX6_PAD_DECL(EIM_A18__GPIO2_IO20, 0x04E8, 0x0118, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__SRC_BOOT_CFG18, 0x04E8, 0x0118, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__EPDC_PWR_CTRL0, 0x04E8, 0x0118, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__EIM_ADDR19, 0x04EC, 0x011C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__IPU1_DISP1_DATA14, 0x04EC, 0x011C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__IPU1_CSI1_DATA14, 0x04EC, 0x011C, 2, 0x0898, 0, 0) +MX6_PAD_DECL(EIM_A19__GPIO2_IO19, 0x04EC, 0x011C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__SRC_BOOT_CFG19, 0x04EC, 0x011C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__EPDC_PWR_CTRL1, 0x04EC, 0x011C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__EIM_ADDR20, 0x04F0, 0x0120, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__IPU1_DISP1_DATA15, 0x04F0, 0x0120, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__IPU1_CSI1_DATA15, 0x04F0, 0x0120, 2, 0x089C, 0, 0) +MX6_PAD_DECL(EIM_A20__GPIO2_IO18, 0x04F0, 0x0120, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__SRC_BOOT_CFG20, 0x04F0, 0x0120, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__EPDC_PWR_CTRL2, 0x04F0, 0x0120, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__EIM_ADDR21, 0x04F4, 0x0124, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__IPU1_DISP1_DATA16, 0x04F4, 0x0124, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__IPU1_CSI1_DATA16, 0x04F4, 0x0124, 2, 0x08A0, 0, 0) +MX6_PAD_DECL(EIM_A21__GPIO2_IO17, 0x04F4, 0x0124, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__SRC_BOOT_CFG21, 0x04F4, 0x0124, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__EPDC_GDCLK, 0x04F4, 0x0124, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__EIM_ADDR22, 0x04F8, 0x0128, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__IPU1_DISP1_DATA17, 0x04F8, 0x0128, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__IPU1_CSI1_DATA17, 0x04F8, 0x0128, 2, 0x08A4, 0, 0) +MX6_PAD_DECL(EIM_A22__GPIO2_IO16, 0x04F8, 0x0128, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__SRC_BOOT_CFG22, 0x04F8, 0x0128, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__EPDC_GDSP, 0x04F8, 0x0128, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__EIM_ADDR23, 0x04FC, 0x012C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_DISP1_DATA18, 0x04FC, 0x012C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_CSI1_DATA18, 0x04FC, 0x012C, 2, 0x08A8, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_SISG3, 0x04FC, 0x012C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__GPIO6_IO06, 0x04FC, 0x012C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__SRC_BOOT_CFG23, 0x04FC, 0x012C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__EPDC_GDOE, 0x04FC, 0x012C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__EIM_ADDR24, 0x0500, 0x0130, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_DISP1_DATA19, 0x0500, 0x0130, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_CSI1_DATA19, 0x0500, 0x0130, 2, 0x08AC, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_SISG2, 0x0500, 0x0130, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__GPIO5_IO04, 0x0500, 0x0130, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__SRC_BOOT_CFG24, 0x0500, 0x0130, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__EPDC_GDRL, 0x0500, 0x0130, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__EIM_ADDR25, 0x0504, 0x0134, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__ECSPI4_SS1, 0x0504, 0x0134, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__ECSPI2_RDY, 0x0504, 0x0134, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__IPU1_DI1_PIN12, 0x0504, 0x0134, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__IPU1_DI0_D1_CS, 0x0504, 0x0134, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__GPIO5_IO02, 0x0504, 0x0134, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__HDMI_TX_CEC_LINE, 0x0504, 0x0134, 6, 0x085C, 0, 0) +MX6_PAD_DECL(EIM_A25__EPDC_DATA15, 0x0504, 0x0134, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__EIM_ACLK_FREERUN, 0x0504, 0x0134, 9, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__EIM_BCLK, 0x0508, 0x0138, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__IPU1_DI1_PIN16, 0x0508, 0x0138, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__GPIO6_IO31, 0x0508, 0x0138, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__EPDC_SDCE9, 0x0508, 0x0138, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__EIM_CS0_B, 0x050C, 0x013C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__IPU1_DI1_PIN05, 0x050C, 0x013C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__ECSPI2_SCLK, 0x050C, 0x013C, 2, 0x07F4, 2, 0) +MX6_PAD_DECL(EIM_CS0__GPIO2_IO23, 0x050C, 0x013C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__EPDC_DATA06, 0x050C, 0x013C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__EIM_CS1_B, 0x0510, 0x0140, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__IPU1_DI1_PIN06, 0x0510, 0x0140, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__ECSPI2_MOSI, 0x0510, 0x0140, 2, 0x07FC, 2, 0) +MX6_PAD_DECL(EIM_CS1__GPIO2_IO24, 0x0510, 0x0140, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__EPDC_DATA08, 0x0510, 0x0140, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__EIM_DATA16, 0x0514, 0x0144, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__ECSPI1_SCLK, 0x0514, 0x0144, 1, 0x07D8, 2, 0) +MX6_PAD_DECL(EIM_D16__IPU1_DI0_PIN05, 0x0514, 0x0144, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__IPU1_CSI1_DATA18, 0x0514, 0x0144, 3, 0x08A8, 1, 0) +MX6_PAD_DECL(EIM_D16__HDMI_TX_DDC_SDA, 0x0514, 0x0144, 4, 0x0864, 0, 0) +MX6_PAD_DECL(EIM_D16__GPIO3_IO16, 0x0514, 0x0144, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__I2C2_SDA, 0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, 0) +MX6_PAD_DECL(EIM_D16__EPDC_DATA10, 0x0514, 0x0144, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__EIM_DATA17, 0x0518, 0x0148, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__ECSPI1_MISO, 0x0518, 0x0148, 1, 0x07DC, 2, 0) +MX6_PAD_DECL(EIM_D17__IPU1_DI0_PIN06, 0x0518, 0x0148, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__IPU1_CSI1_PIXCLK, 0x0518, 0x0148, 3, 0x08B8, 1, 0) +MX6_PAD_DECL(EIM_D17__DCIC1_OUT, 0x0518, 0x0148, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__GPIO3_IO17, 0x0518, 0x0148, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__I2C3_SCL, 0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, 0) +MX6_PAD_DECL(EIM_D17__EPDC_VCOM0, 0x0518, 0x0148, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__EIM_DATA18, 0x051C, 0x014C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__ECSPI1_MOSI, 0x051C, 0x014C, 1, 0x07E0, 2, 0) +MX6_PAD_DECL(EIM_D18__IPU1_DI0_PIN07, 0x051C, 0x014C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__IPU1_CSI1_DATA17, 0x051C, 0x014C, 3, 0x08A4, 1, 0) +MX6_PAD_DECL(EIM_D18__IPU1_DI1_D0_CS, 0x051C, 0x014C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__GPIO3_IO18, 0x051C, 0x014C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__I2C3_SDA, 0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0) +MX6_PAD_DECL(EIM_D18__EPDC_VCOM1, 0x051C, 0x014C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__EIM_DATA19, 0x0520, 0x0150, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__ECSPI1_SS1, 0x0520, 0x0150, 1, 0x07E8, 1, 0) +MX6_PAD_DECL(EIM_D19__IPU1_DI0_PIN08, 0x0520, 0x0150, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__IPU1_CSI1_DATA16, 0x0520, 0x0150, 3, 0x08A0, 1, 0) +MX6_PAD_DECL(EIM_D19__UART1_CTS_B, 0x0520, 0x0150, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__UART1_RTS_B, 0x0520, 0x0150, 4, 0x08F8, 0, 0) +MX6_PAD_DECL(EIM_D19__GPIO3_IO19, 0x0520, 0x0150, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__EPIT1_OUT, 0x0520, 0x0150, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__EPDC_DATA12, 0x0520, 0x0150, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__EIM_DATA20, 0x0524, 0x0154, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__ECSPI4_SS0, 0x0524, 0x0154, 1, 0x0808, 0, 0) +MX6_PAD_DECL(EIM_D20__IPU1_DI0_PIN16, 0x0524, 0x0154, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__IPU1_CSI1_DATA15, 0x0524, 0x0154, 3, 0x089C, 1, 0) +MX6_PAD_DECL(EIM_D20__UART1_CTS_B, 0x0524, 0x0154, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__UART1_RTS_B, 0x0524, 0x0154, 4, 0x08F8, 1, 0) +MX6_PAD_DECL(EIM_D20__GPIO3_IO20, 0x0524, 0x0154, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__EPIT2_OUT, 0x0524, 0x0154, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__EIM_DATA21, 0x0528, 0x0158, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__ECSPI4_SCLK, 0x0528, 0x0158, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__IPU1_DI0_PIN17, 0x0528, 0x0158, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__IPU1_CSI1_DATA11, 0x0528, 0x0158, 3, 0x088C, 0, 0) +MX6_PAD_DECL(EIM_D21__USB_OTG_OC, 0x0528, 0x0158, 4, 0x0920, 0, 0) +MX6_PAD_DECL(EIM_D21__GPIO3_IO21, 0x0528, 0x0158, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__I2C1_SCL, 0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0) +MX6_PAD_DECL(EIM_D21__SPDIF_IN, 0x0528, 0x0158, 7, 0x08F0, 0, 0) +MX6_PAD_DECL(EIM_D22__EIM_DATA22, 0x052C, 0x015C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__ECSPI4_MISO, 0x052C, 0x015C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__IPU1_DI0_PIN01, 0x052C, 0x015C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__IPU1_CSI1_DATA10, 0x052C, 0x015C, 3, 0x0888, 0, 0) +MX6_PAD_DECL(EIM_D22__USB_OTG_PWR, 0x052C, 0x015C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__GPIO3_IO22, 0x052C, 0x015C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__SPDIF_OUT, 0x052C, 0x015C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__EPDC_SDCE6, 0x052C, 0x015C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__EIM_DATA23, 0x0530, 0x0160, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI0_D0_CS, 0x0530, 0x0160, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__UART3_CTS_B, 0x0530, 0x0160, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__UART3_RTS_B, 0x0530, 0x0160, 2, 0x0908, 0, 0) +MX6_PAD_DECL(EIM_D23__UART1_DCD_B, 0x0530, 0x0160, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_CSI1_DATA_EN, 0x0530, 0x0160, 4, 0x08B0, 0, 0) +MX6_PAD_DECL(EIM_D23__GPIO3_IO23, 0x0530, 0x0160, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN02, 0x0530, 0x0160, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN14, 0x0530, 0x0160, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__EPDC_DATA11, 0x0530, 0x0160, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__EIM_DATA24, 0x0534, 0x0164, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI4_SS2, 0x0534, 0x0164, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__UART3_TX_DATA, 0x0534, 0x0164, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__UART3_RX_DATA, 0x0534, 0x0164, 2, 0x090C, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI1_SS2, 0x0534, 0x0164, 3, 0x07EC, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI2_SS2, 0x0534, 0x0164, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__GPIO3_IO24, 0x0534, 0x0164, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__AUD5_RXFS, 0x0534, 0x0164, 6, 0x07BC, 1, 0) +MX6_PAD_DECL(EIM_D24__UART1_DTR_B, 0x0534, 0x0164, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__EPDC_SDCE7, 0x0534, 0x0164, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__EIM_DATA25, 0x0538, 0x0168, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__ECSPI4_SS3, 0x0538, 0x0168, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__UART3_TX_DATA, 0x0538, 0x0168, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__UART3_RX_DATA, 0x0538, 0x0168, 2, 0x090C, 1, 0) +MX6_PAD_DECL(EIM_D25__ECSPI1_SS3, 0x0538, 0x0168, 3, 0x07F0, 0, 0) +MX6_PAD_DECL(EIM_D25__ECSPI2_SS3, 0x0538, 0x0168, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__GPIO3_IO25, 0x0538, 0x0168, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__AUD5_RXC, 0x0538, 0x0168, 6, 0x07B8, 1, 0) +MX6_PAD_DECL(EIM_D25__UART1_DSR_B, 0x0538, 0x0168, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__EPDC_SDCE8, 0x0538, 0x0168, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__EIM_DATA26, 0x053C, 0x016C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_DI1_PIN11, 0x053C, 0x016C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_CSI0_DATA01, 0x053C, 0x016C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_CSI1_DATA14, 0x053C, 0x016C, 3, 0x0898, 1, 0) +MX6_PAD_DECL(EIM_D26__UART2_TX_DATA, 0x053C, 0x016C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__UART2_RX_DATA, 0x053C, 0x016C, 4, 0x0904, 0, 0) +MX6_PAD_DECL(EIM_D26__GPIO3_IO26, 0x053C, 0x016C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_SISG2, 0x053C, 0x016C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_DISP1_DATA22, 0x053C, 0x016C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__EPDC_SDOED, 0x053C, 0x016C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__EIM_DATA27, 0x0540, 0x0170, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_DI1_PIN13, 0x0540, 0x0170, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_CSI0_DATA00, 0x0540, 0x0170, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_CSI1_DATA13, 0x0540, 0x0170, 3, 0x0894, 1, 0) +MX6_PAD_DECL(EIM_D27__UART2_TX_DATA, 0x0540, 0x0170, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__UART2_RX_DATA, 0x0540, 0x0170, 4, 0x0904, 1, 0) +MX6_PAD_DECL(EIM_D27__GPIO3_IO27, 0x0540, 0x0170, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_SISG3, 0x0540, 0x0170, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_DISP1_DATA23, 0x0540, 0x0170, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__EPDC_SDOE, 0x0540, 0x0170, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__EIM_DATA28, 0x0544, 0x0174, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__I2C1_SDA, 0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0) +MX6_PAD_DECL(EIM_D28__ECSPI4_MOSI, 0x0544, 0x0174, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_CSI1_DATA12, 0x0544, 0x0174, 3, 0x0890, 1, 0) +MX6_PAD_DECL(EIM_D28__UART2_DTE_RTS_B, 0x0544, 0x0174, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__UART2_DTE_CTS_B, 0x0544, 0x0174, 4, 0x0900, 0, 0) +MX6_PAD_DECL(EIM_D28__GPIO3_IO28, 0x0544, 0x0174, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_EXT_TRIG, 0x0544, 0x0174, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_DI0_PIN13, 0x0544, 0x0174, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__EPDC_PWR_CTRL3, 0x0544, 0x0174, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__EIM_DATA29, 0x0548, 0x0178, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_DI1_PIN15, 0x0548, 0x0178, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__ECSPI4_SS0, 0x0548, 0x0178, 2, 0x0808, 1, 0) +MX6_PAD_DECL(EIM_D29__UART2_CTS_B, 0x0548, 0x0178, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__UART2_RTS_B, 0x0548, 0x0178, 4, 0x0900, 1, 0) +MX6_PAD_DECL(EIM_D29__GPIO3_IO29, 0x0548, 0x0178, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_CSI1_VSYNC, 0x0548, 0x0178, 6, 0x08BC, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_DI0_PIN14, 0x0548, 0x0178, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__EPDC_PWR_WAKE, 0x0548, 0x0178, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__EIM_DATA30, 0x054C, 0x017C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_DISP1_DATA21, 0x054C, 0x017C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_DI0_PIN11, 0x054C, 0x017C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_CSI0_DATA03, 0x054C, 0x017C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__UART3_CTS_B, 0x054C, 0x017C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__UART3_RTS_B, 0x054C, 0x017C, 4, 0x0908, 1, 0) +MX6_PAD_DECL(EIM_D30__GPIO3_IO30, 0x054C, 0x017C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__USB_H1_OC, 0x054C, 0x017C, 6, 0x0924, 0, 0) +MX6_PAD_DECL(EIM_D30__EPDC_SDOEZ, 0x054C, 0x017C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__EIM_DATA31, 0x0550, 0x0180, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_DISP1_DATA20, 0x0550, 0x0180, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_DI0_PIN12, 0x0550, 0x0180, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_CSI0_DATA02, 0x0550, 0x0180, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__UART3_CTS_B, 0x0550, 0x0180, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__UART3_RTS_B, 0x0550, 0x0180, 4, 0x0908, 2, 0) +MX6_PAD_DECL(EIM_D31__GPIO3_IO31, 0x0550, 0x0180, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__USB_H1_PWR, 0x0550, 0x0180, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__EPDC_SDCLK_P, 0x0550, 0x0180, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__EIM_ACLK_FREERUN, 0x0550, 0x0180, 9, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__EIM_AD00, 0x0554, 0x0184, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__IPU1_DISP1_DATA09, 0x0554, 0x0184, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__IPU1_CSI1_DATA09, 0x0554, 0x0184, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__GPIO3_IO00, 0x0554, 0x0184, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__SRC_BOOT_CFG00, 0x0554, 0x0184, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__EPDC_SDCLK_N, 0x0554, 0x0184, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__EIM_AD01, 0x0558, 0x0188, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__IPU1_DISP1_DATA08, 0x0558, 0x0188, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__IPU1_CSI1_DATA08, 0x0558, 0x0188, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__GPIO3_IO01, 0x0558, 0x0188, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__SRC_BOOT_CFG01, 0x0558, 0x0188, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__EPDC_SDLE, 0x0558, 0x0188, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__EIM_AD10, 0x055C, 0x018C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__IPU1_DI1_PIN15, 0x055C, 0x018C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__IPU1_CSI1_DATA_EN, 0x055C, 0x018C, 2, 0x08B0, 1, 0) +MX6_PAD_DECL(EIM_DA10__GPIO3_IO10, 0x055C, 0x018C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__SRC_BOOT_CFG10, 0x055C, 0x018C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__EPDC_DATA01, 0x055C, 0x018C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__EIM_AD11, 0x0560, 0x0190, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__IPU1_DI1_PIN02, 0x0560, 0x0190, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__IPU1_CSI1_HSYNC, 0x0560, 0x0190, 2, 0x08B4, 0, 0) +MX6_PAD_DECL(EIM_DA11__GPIO3_IO11, 0x0560, 0x0190, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__SRC_BOOT_CFG11, 0x0560, 0x0190, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__EPDC_DATA03, 0x0560, 0x0190, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__EIM_AD12, 0x0564, 0x0194, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__IPU1_DI1_PIN03, 0x0564, 0x0194, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__IPU1_CSI1_VSYNC, 0x0564, 0x0194, 2, 0x08BC, 1, 0) +MX6_PAD_DECL(EIM_DA12__GPIO3_IO12, 0x0564, 0x0194, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__SRC_BOOT_CFG12, 0x0564, 0x0194, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__EPDC_DATA02, 0x0564, 0x0194, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__EIM_AD13, 0x0568, 0x0198, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__IPU1_DI1_D0_CS, 0x0568, 0x0198, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__GPIO3_IO13, 0x0568, 0x0198, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__SRC_BOOT_CFG13, 0x0568, 0x0198, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__EPDC_DATA13, 0x0568, 0x0198, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__EIM_AD14, 0x056C, 0x019C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__IPU1_DI1_D1_CS, 0x056C, 0x019C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__GPIO3_IO14, 0x056C, 0x019C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__SRC_BOOT_CFG14, 0x056C, 0x019C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__EPDC_DATA14, 0x056C, 0x019C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__EIM_AD15, 0x0570, 0x01A0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN01, 0x0570, 0x01A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN04, 0x0570, 0x01A0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__GPIO3_IO15, 0x0570, 0x01A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__SRC_BOOT_CFG15, 0x0570, 0x01A0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__EPDC_DATA09, 0x0570, 0x01A0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__EIM_AD02, 0x0574, 0x01A4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__IPU1_DISP1_DATA07, 0x0574, 0x01A4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__IPU1_CSI1_DATA07, 0x0574, 0x01A4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__GPIO3_IO02, 0x0574, 0x01A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__SRC_BOOT_CFG02, 0x0574, 0x01A4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__EPDC_BDR0, 0x0574, 0x01A4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__EIM_AD03, 0x0578, 0x01A8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__IPU1_DISP1_DATA06, 0x0578, 0x01A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__IPU1_CSI1_DATA06, 0x0578, 0x01A8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__GPIO3_IO03, 0x0578, 0x01A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__SRC_BOOT_CFG03, 0x0578, 0x01A8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__EPDC_BDR1, 0x0578, 0x01A8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__EIM_AD04, 0x057C, 0x01AC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__IPU1_DISP1_DATA05, 0x057C, 0x01AC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__IPU1_CSI1_DATA05, 0x057C, 0x01AC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__GPIO3_IO04, 0x057C, 0x01AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__SRC_BOOT_CFG04, 0x057C, 0x01AC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__EPDC_SDCE0, 0x057C, 0x01AC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__EIM_AD05, 0x0580, 0x01B0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__IPU1_DISP1_DATA04, 0x0580, 0x01B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__IPU1_CSI1_DATA04, 0x0580, 0x01B0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__GPIO3_IO05, 0x0580, 0x01B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__SRC_BOOT_CFG05, 0x0580, 0x01B0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__EPDC_SDCE1, 0x0580, 0x01B0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__EIM_AD06, 0x0584, 0x01B4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__IPU1_DISP1_DATA03, 0x0584, 0x01B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__IPU1_CSI1_DATA03, 0x0584, 0x01B4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__GPIO3_IO06, 0x0584, 0x01B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__SRC_BOOT_CFG06, 0x0584, 0x01B4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__EPDC_SDCE2, 0x0584, 0x01B4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__EIM_AD07, 0x0588, 0x01B8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__IPU1_DISP1_DATA02, 0x0588, 0x01B8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__IPU1_CSI1_DATA02, 0x0588, 0x01B8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__GPIO3_IO07, 0x0588, 0x01B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__SRC_BOOT_CFG07, 0x0588, 0x01B8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__EPDC_SDCE3, 0x0588, 0x01B8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__EIM_AD08, 0x058C, 0x01BC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__IPU1_DISP1_DATA01, 0x058C, 0x01BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__IPU1_CSI1_DATA01, 0x058C, 0x01BC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__GPIO3_IO08, 0x058C, 0x01BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__SRC_BOOT_CFG08, 0x058C, 0x01BC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__EPDC_SDCE4, 0x058C, 0x01BC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__EIM_AD09, 0x0590, 0x01C0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__IPU1_DISP1_DATA00, 0x0590, 0x01C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__IPU1_CSI1_DATA00, 0x0590, 0x01C0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__GPIO3_IO09, 0x0590, 0x01C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__SRC_BOOT_CFG09, 0x0590, 0x01C0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__EPDC_SDCE5, 0x0590, 0x01C0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__EIM_EB0_B, 0x0594, 0x01C4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__IPU1_DISP1_DATA11, 0x0594, 0x01C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__IPU1_CSI1_DATA11, 0x0594, 0x01C4, 2, 0x088C, 1, 0) +MX6_PAD_DECL(EIM_EB0__CCM_PMIC_READY, 0x0594, 0x01C4, 4, 0x07D4, 0, 0) +MX6_PAD_DECL(EIM_EB0__GPIO2_IO28, 0x0594, 0x01C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__SRC_BOOT_CFG27, 0x0594, 0x01C4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__EPDC_PWR_COM, 0x0594, 0x01C4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__EIM_EB1_B, 0x0598, 0x01C8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__IPU1_DISP1_DATA10, 0x0598, 0x01C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__IPU1_CSI1_DATA10, 0x0598, 0x01C8, 2, 0x0888, 1, 0) +MX6_PAD_DECL(EIM_EB1__GPIO2_IO29, 0x0598, 0x01C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__SRC_BOOT_CFG28, 0x0598, 0x01C8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__EPDC_SDSHR, 0x0598, 0x01C8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__EIM_EB2_B, 0x059C, 0x01CC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__ECSPI1_SS0, 0x059C, 0x01CC, 1, 0x07E4, 2, 0) +MX6_PAD_DECL(EIM_EB2__IPU1_CSI1_DATA19, 0x059C, 0x01CC, 3, 0x08AC, 1, 0) +MX6_PAD_DECL(EIM_EB2__HDMI_TX_DDC_SCL, 0x059C, 0x01CC, 4, 0x0860, 0, 0) +MX6_PAD_DECL(EIM_EB2__GPIO2_IO30, 0x059C, 0x01CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__I2C2_SCL, 0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, 0) +MX6_PAD_DECL(EIM_EB2__SRC_BOOT_CFG30, 0x059C, 0x01CC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__EPDC_DATA05, 0x059C, 0x01CC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__EIM_EB3_B, 0x05A0, 0x01D0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__ECSPI4_RDY, 0x05A0, 0x01D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__UART3_CTS_B, 0x05A0, 0x01D0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__UART3_RTS_B, 0x05A0, 0x01D0, 2, 0x0908, 3, 0) +MX6_PAD_DECL(EIM_EB3__UART1_RI_B, 0x05A0, 0x01D0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__IPU1_CSI1_HSYNC, 0x05A0, 0x01D0, 4, 0x08B4, 1, 0) +MX6_PAD_DECL(EIM_EB3__GPIO2_IO31, 0x05A0, 0x01D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__IPU1_DI1_PIN03, 0x05A0, 0x01D0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__SRC_BOOT_CFG31, 0x05A0, 0x01D0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__EPDC_SDCE0, 0x05A0, 0x01D0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__EIM_ACLK_FREERUN, 0x05A0, 0x01D0, 9, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__EIM_LBA_B, 0x05A4, 0x01D4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__IPU1_DI1_PIN17, 0x05A4, 0x01D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__ECSPI2_SS1, 0x05A4, 0x01D4, 2, 0x0804, 1, 0) +MX6_PAD_DECL(EIM_LBA__GPIO2_IO27, 0x05A4, 0x01D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__SRC_BOOT_CFG26, 0x05A4, 0x01D4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__EPDC_DATA04, 0x05A4, 0x01D4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__EIM_OE_B, 0x05A8, 0x01D8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__IPU1_DI1_PIN07, 0x05A8, 0x01D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__ECSPI2_MISO, 0x05A8, 0x01D8, 2, 0x07F8, 2, 0) +MX6_PAD_DECL(EIM_OE__GPIO2_IO25, 0x05A8, 0x01D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__EPDC_PWR_IRQ, 0x05A8, 0x01D8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__EIM_RW, 0x05AC, 0x01DC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__IPU1_DI1_PIN08, 0x05AC, 0x01DC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__ECSPI2_SS0, 0x05AC, 0x01DC, 2, 0x0800, 2, 0) +MX6_PAD_DECL(EIM_RW__GPIO2_IO26, 0x05AC, 0x01DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__SRC_BOOT_CFG29, 0x05AC, 0x01DC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__EPDC_DATA07, 0x05AC, 0x01DC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__EIM_WAIT_B, 0x05B0, 0x01E0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__EIM_DTACK_B, 0x05B0, 0x01E0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__GPIO5_IO00, 0x05B0, 0x01E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__SRC_BOOT_CFG25, 0x05B0, 0x01E0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__ENET_RX_EN, 0x05B4, 0x01E4, 1, 0x0828, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__ESAI_TX_CLK, 0x05B4, 0x01E4, 2, 0x0840, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__SPDIF_EXT_CLK, 0x05B4, 0x01E4, 3, 0x08F4, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__GPIO1_IO25, 0x05B4, 0x01E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__MLB_DATA, 0x05B8, 0x01E8, 0, 0x08E0, 0, 0) +MX6_PAD_DECL(ENET_MDC__ENET_MDC, 0x05B8, 0x01E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__ESAI_TX5_RX0, 0x05B8, 0x01E8, 2, 0x0858, 0, 0) +MX6_PAD_DECL(ENET_MDC__ENET_1588_EVENT1_IN, 0x05B8, 0x01E8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__GPIO1_IO31, 0x05B8, 0x01E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ENET_MDIO, 0x05BC, 0x01EC, 1, 0x0810, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK, 0x05BC, 0x01EC, 2, 0x083C, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT, 0x05BC, 0x01EC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22, 0x05BC, 0x01EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK, 0x05BC, 0x01EC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x05C0, 0x01F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS, 0x05C0, 0x01F0, 2, 0x082C, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23, 0x05C0, 0x01F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK, 0x05C0, 0x01F0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__USB_OTG_ID, 0x05C4, 0x01F4, 0, 0x0790, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__ENET_RX_ER, 0x05C4, 0x01F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__ESAI_RX_HF_CLK, 0x05C4, 0x01F4, 2, 0x0834, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__SPDIF_IN, 0x05C4, 0x01F4, 3, 0x08F0, 1, 0) +MX6_PAD_DECL(ENET_RX_ER__ENET_1588_EVENT2_OUT, 0x05C4, 0x01F4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__GPIO1_IO24, 0x05C4, 0x01F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD0__ENET_RX_DATA0, 0x05C8, 0x01F8, 1, 0x0818, 0, 0) +MX6_PAD_DECL(ENET_RXD0__ESAI_TX_HF_CLK, 0x05C8, 0x01F8, 2, 0x0838, 0, 0) +MX6_PAD_DECL(ENET_RXD0__SPDIF_OUT, 0x05C8, 0x01F8, 3, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD0__GPIO1_IO27, 0x05C8, 0x01F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD1__MLB_SIG, 0x05CC, 0x01FC, 0, 0x08E4, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ENET_RX_DATA1, 0x05CC, 0x01FC, 1, 0x081C, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ESAI_TX_FS, 0x05CC, 0x01FC, 2, 0x0830, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ENET_1588_EVENT3_OUT, 0x05CC, 0x01FC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD1__GPIO1_IO26, 0x05CC, 0x01FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__ENET_TX_EN, 0x05D0, 0x0200, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__ESAI_TX3_RX2, 0x05D0, 0x0200, 2, 0x0850, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__GPIO1_IO28, 0x05D0, 0x0200, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__I2C4_SCL, 0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, 0) +MX6_PAD_DECL(ENET_TXD0__ENET_TX_DATA0, 0x05D4, 0x0204, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD0__ESAI_TX4_RX1, 0x05D4, 0x0204, 2, 0x0854, 0, 0) +MX6_PAD_DECL(ENET_TXD0__GPIO1_IO30, 0x05D4, 0x0204, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__MLB_CLK, 0x05D8, 0x0208, 0, 0x08DC, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ENET_TX_DATA1, 0x05D8, 0x0208, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ESAI_TX2_RX3, 0x05D8, 0x0208, 2, 0x084C, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ENET_1588_EVENT0_IN, 0x05D8, 0x0208, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__GPIO1_IO29, 0x05D8, 0x0208, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__I2C4_SDA, 0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, 0) +MX6_PAD_DECL(GPIO_0__CCM_CLKO1, 0x05DC, 0x020C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__KEY_COL5, 0x05DC, 0x020C, 2, 0x08C0, 1, 0) +MX6_PAD_DECL(GPIO_0__ASRC_EXT_CLK, 0x05DC, 0x020C, 3, 0x0794, 0, 0) +MX6_PAD_DECL(GPIO_0__EPIT1_OUT, 0x05DC, 0x020C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__GPIO1_IO00, 0x05DC, 0x020C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__USB_H1_PWR, 0x05DC, 0x020C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__SNVS_VIO_5, 0x05DC, 0x020C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__ESAI_RX_CLK, 0x05E0, 0x0210, 0, 0x083C, 1, 0) +MX6_PAD_DECL(GPIO_1__WDOG2_B, 0x05E0, 0x0210, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__KEY_ROW5, 0x05E0, 0x0210, 2, 0x08CC, 1, 0) +MX6_PAD_DECL(GPIO_1__USB_OTG_ID, 0x05E0, 0x0210, 3, 0x0790, 1, 0) +MX6_PAD_DECL(GPIO_1__PWM2_OUT, 0x05E0, 0x0210, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__GPIO1_IO01, 0x05E0, 0x0210, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__SD1_CD_B, 0x05E0, 0x0210, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2, 0x05E4, 0x0214, 0, 0x0850, 1, 0) +MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x05E4, 0x0214, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x05E4, 0x0214, 2, 0x080C, 0, 0) +MX6_PAD_DECL(GPIO_16__SD1_LCTL, 0x05E4, 0x0214, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__SPDIF_IN, 0x05E4, 0x0214, 4, 0x08F0, 2, 0) +MX6_PAD_DECL(GPIO_16__GPIO7_IO11, 0x05E4, 0x0214, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__I2C3_SDA, 0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0) +MX6_PAD_DECL(GPIO_16__JTAG_DE_B, 0x05E4, 0x0214, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__ESAI_TX0, 0x05E8, 0x0218, 0, 0x0844, 0, 0) +MX6_PAD_DECL(GPIO_17__ENET_1588_EVENT3_IN, 0x05E8, 0x0218, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__CCM_PMIC_READY, 0x05E8, 0x0218, 2, 0x07D4, 1, 0) +MX6_PAD_DECL(GPIO_17__SDMA_EXT_EVENT0, 0x05E8, 0x0218, 3, 0x08E8, 1, 0) +MX6_PAD_DECL(GPIO_17__SPDIF_OUT, 0x05E8, 0x0218, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__GPIO7_IO12, 0x05E8, 0x0218, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__ESAI_TX1, 0x05EC, 0x021C, 0, 0x0848, 0, 0) +MX6_PAD_DECL(GPIO_18__ENET_RX_CLK, 0x05EC, 0x021C, 1, 0x0814, 0, 0) +MX6_PAD_DECL(GPIO_18__SD3_VSELECT, 0x05EC, 0x021C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__SDMA_EXT_EVENT1, 0x05EC, 0x021C, 3, 0x08EC, 1, 0) +MX6_PAD_DECL(GPIO_18__ASRC_EXT_CLK, 0x05EC, 0x021C, 4, 0x0794, 1, 0) +MX6_PAD_DECL(GPIO_18__GPIO7_IO13, 0x05EC, 0x021C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__SNVS_VIO_5_CTL, 0x05EC, 0x021C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__KEY_COL5, 0x05F0, 0x0220, 0, 0x08C0, 2, 0) +MX6_PAD_DECL(GPIO_19__ENET_1588_EVENT0_OUT, 0x05F0, 0x0220, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__SPDIF_OUT, 0x05F0, 0x0220, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__CCM_CLKO1, 0x05F0, 0x0220, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__ECSPI1_RDY, 0x05F0, 0x0220, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__GPIO4_IO05, 0x05F0, 0x0220, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__ENET_TX_ER, 0x05F0, 0x0220, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__ESAI_TX_FS, 0x05F4, 0x0224, 0, 0x0830, 1, 0) +MX6_PAD_DECL(GPIO_2__KEY_ROW6, 0x05F4, 0x0224, 2, 0x08D0, 1, 0) +MX6_PAD_DECL(GPIO_2__GPIO1_IO02, 0x05F4, 0x0224, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__SD2_WP, 0x05F4, 0x0224, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__MLB_DATA, 0x05F4, 0x0224, 7, 0x08E0, 1, 0) +MX6_PAD_DECL(GPIO_3__ESAI_RX_HF_CLK, 0x05F8, 0x0228, 0, 0x0834, 1, 0) +MX6_PAD_DECL(GPIO_3__I2C3_SCL, 0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, 0) +MX6_PAD_DECL(GPIO_3__XTALOSC_REF_CLK_24M, 0x05F8, 0x0228, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__CCM_CLKO2, 0x05F8, 0x0228, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__GPIO1_IO03, 0x05F8, 0x0228, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__USB_H1_OC, 0x05F8, 0x0228, 6, 0x0924, 1, 0) +MX6_PAD_DECL(GPIO_3__MLB_CLK, 0x05F8, 0x0228, 7, 0x08DC, 1, 0) +MX6_PAD_DECL(GPIO_4__ESAI_TX_HF_CLK, 0x05FC, 0x022C, 0, 0x0838, 1, 0) +MX6_PAD_DECL(GPIO_4__KEY_COL7, 0x05FC, 0x022C, 2, 0x08C8, 1, 0) +MX6_PAD_DECL(GPIO_4__GPIO1_IO04, 0x05FC, 0x022C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_4__SD2_CD_B, 0x05FC, 0x022C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__ESAI_TX2_RX3, 0x0600, 0x0230, 0, 0x084C, 1, 0) +MX6_PAD_DECL(GPIO_5__KEY_ROW7, 0x0600, 0x0230, 2, 0x08D4, 1, 0) +MX6_PAD_DECL(GPIO_5__CCM_CLKO1, 0x0600, 0x0230, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__GPIO1_IO05, 0x0600, 0x0230, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__I2C3_SCL, 0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0) +MX6_PAD_DECL(GPIO_5__ARM_EVENTI, 0x0600, 0x0230, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__ESAI_TX_CLK, 0x0604, 0x0234, 0, 0x0840, 1, 0) +MX6_PAD_DECL(GPIO_6__I2C3_SDA, 0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0) +MX6_PAD_DECL(GPIO_6__GPIO1_IO06, 0x0604, 0x0234, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__SD2_LCTL, 0x0604, 0x0234, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__MLB_SIG, 0x0604, 0x0234, 7, 0x08E4, 1, 0) +MX6_PAD_DECL(GPIO_7__ESAI_TX4_RX1, 0x0608, 0x0238, 0, 0x0854, 1, 0) +MX6_PAD_DECL(GPIO_7__EPIT1_OUT, 0x0608, 0x0238, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__FLEXCAN1_TX, 0x0608, 0x0238, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__UART2_TX_DATA, 0x0608, 0x0238, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__UART2_RX_DATA, 0x0608, 0x0238, 4, 0x0904, 2, 0) +MX6_PAD_DECL(GPIO_7__GPIO1_IO07, 0x0608, 0x0238, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__SPDIF_LOCK, 0x0608, 0x0238, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__USB_OTG_HOST_MODE, 0x0608, 0x0238, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__I2C4_SCL, 0x0608, 0x0238, 8 | IOMUX_CONFIG_SION, 0x0880, 1, 0) +MX6_PAD_DECL(GPIO_8__ESAI_TX5_RX0, 0x060C, 0x023C, 0, 0x0858, 1, 0) +MX6_PAD_DECL(GPIO_8__XTALOSC_REF_CLK_32K, 0x060C, 0x023C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__EPIT2_OUT, 0x060C, 0x023C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__FLEXCAN1_RX, 0x060C, 0x023C, 3, 0x07C8, 0, 0) +MX6_PAD_DECL(GPIO_8__UART2_TX_DATA, 0x060C, 0x023C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__UART2_RX_DATA, 0x060C, 0x023C, 4, 0x0904, 3, 0) +MX6_PAD_DECL(GPIO_8__GPIO1_IO08, 0x060C, 0x023C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK, 0x060C, 0x023C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE, 0x060C, 0x023C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__I2C4_SDA, 0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, 0) +MX6_PAD_DECL(GPIO_9__ESAI_RX_FS, 0x0610, 0x0240, 0, 0x082C, 1, 0) +MX6_PAD_DECL(GPIO_9__WDOG1_B, 0x0610, 0x0240, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__KEY_COL6, 0x0610, 0x0240, 2, 0x08C4, 1, 0) +MX6_PAD_DECL(GPIO_9__CCM_REF_EN_B, 0x0610, 0x0240, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__PWM1_OUT, 0x0610, 0x0240, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__GPIO1_IO09, 0x0610, 0x0240, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__SD1_WP, 0x0610, 0x0240, 6, 0x092C, 1, 0) +MX6_PAD_DECL(KEY_COL0__ECSPI1_SCLK, 0x062C, 0x0244, 0, 0x07D8, 3, 0) +MX6_PAD_DECL(KEY_COL0__ENET_RX_DATA3, 0x062C, 0x0244, 1, 0x0824, 0, 0) +MX6_PAD_DECL(KEY_COL0__AUD5_TXC, 0x062C, 0x0244, 2, 0x07C0, 1, 0) +MX6_PAD_DECL(KEY_COL0__KEY_COL0, 0x062C, 0x0244, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__UART4_TX_DATA, 0x062C, 0x0244, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__UART4_RX_DATA, 0x062C, 0x0244, 4, 0x0914, 2, 0) +MX6_PAD_DECL(KEY_COL0__GPIO4_IO06, 0x062C, 0x0244, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__DCIC1_OUT, 0x062C, 0x0244, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__ECSPI1_MISO, 0x0630, 0x0248, 0, 0x07DC, 3, 0) +MX6_PAD_DECL(KEY_COL1__ENET_MDIO, 0x0630, 0x0248, 1, 0x0810, 1, 0) +MX6_PAD_DECL(KEY_COL1__AUD5_TXFS, 0x0630, 0x0248, 2, 0x07C4, 1, 0) +MX6_PAD_DECL(KEY_COL1__KEY_COL1, 0x0630, 0x0248, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__UART5_TX_DATA, 0x0630, 0x0248, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__UART5_RX_DATA, 0x0630, 0x0248, 4, 0x091C, 2, 0) +MX6_PAD_DECL(KEY_COL1__GPIO4_IO08, 0x0630, 0x0248, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__SD1_VSELECT, 0x0630, 0x0248, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__ECSPI1_SS1, 0x0634, 0x024C, 0, 0x07E8, 2, 0) +MX6_PAD_DECL(KEY_COL2__ENET_RX_DATA2, 0x0634, 0x024C, 1, 0x0820, 0, 0) +MX6_PAD_DECL(KEY_COL2__FLEXCAN1_TX, 0x0634, 0x024C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__KEY_COL2, 0x0634, 0x024C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__ENET_MDC, 0x0634, 0x024C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__GPIO4_IO10, 0x0634, 0x024C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__USB_H1_PWR_CTL_WAKE, 0x0634, 0x024C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__ECSPI1_SS3, 0x0638, 0x0250, 0, 0x07F0, 1, 0) +MX6_PAD_DECL(KEY_COL3__ENET_CRS, 0x0638, 0x0250, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__HDMI_TX_DDC_SCL, 0x0638, 0x0250, 2, 0x0860, 1, 0) +MX6_PAD_DECL(KEY_COL3__KEY_COL3, 0x0638, 0x0250, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__I2C2_SCL, 0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0) +MX6_PAD_DECL(KEY_COL3__GPIO4_IO12, 0x0638, 0x0250, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__SPDIF_IN, 0x0638, 0x0250, 6, 0x08F0, 3, 0) +MX6_PAD_DECL(KEY_COL4__FLEXCAN2_TX, 0x063C, 0x0254, 0, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__IPU1_SISG4, 0x063C, 0x0254, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__USB_OTG_OC, 0x063C, 0x0254, 2, 0x0920, 1, 0) +MX6_PAD_DECL(KEY_COL4__KEY_COL4, 0x063C, 0x0254, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__UART5_CTS_B, 0x063C, 0x0254, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__UART5_RTS_B, 0x063C, 0x0254, 4, 0x0918, 2, 0) +MX6_PAD_DECL(KEY_COL4__GPIO4_IO14, 0x063C, 0x0254, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__ECSPI1_MOSI, 0x0640, 0x0258, 0, 0x07E0, 3, 0) +MX6_PAD_DECL(KEY_ROW0__ENET_TX_DATA3, 0x0640, 0x0258, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__AUD5_TXD, 0x0640, 0x0258, 2, 0x07B4, 1, 0) +MX6_PAD_DECL(KEY_ROW0__KEY_ROW0, 0x0640, 0x0258, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__UART4_TX_DATA, 0x0640, 0x0258, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__UART4_RX_DATA, 0x0640, 0x0258, 4, 0x0914, 3, 0) +MX6_PAD_DECL(KEY_ROW0__GPIO4_IO07, 0x0640, 0x0258, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__DCIC2_OUT, 0x0640, 0x0258, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__ECSPI1_SS0, 0x0644, 0x025C, 0, 0x07E4, 3, 0) +MX6_PAD_DECL(KEY_ROW1__ENET_COL, 0x0644, 0x025C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__AUD5_RXD, 0x0644, 0x025C, 2, 0x07B0, 1, 0) +MX6_PAD_DECL(KEY_ROW1__KEY_ROW1, 0x0644, 0x025C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__UART5_TX_DATA, 0x0644, 0x025C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__UART5_RX_DATA, 0x0644, 0x025C, 4, 0x091C, 3, 0) +MX6_PAD_DECL(KEY_ROW1__GPIO4_IO09, 0x0644, 0x025C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__SD2_VSELECT, 0x0644, 0x025C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__ECSPI1_SS2, 0x0648, 0x0260, 0, 0x07EC, 1, 0) +MX6_PAD_DECL(KEY_ROW2__ENET_TX_DATA2, 0x0648, 0x0260, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__FLEXCAN1_RX, 0x0648, 0x0260, 2, 0x07C8, 1, 0) +MX6_PAD_DECL(KEY_ROW2__KEY_ROW2, 0x0648, 0x0260, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__SD2_VSELECT, 0x0648, 0x0260, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__GPIO4_IO11, 0x0648, 0x0260, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__HDMI_TX_CEC_LINE, 0x0648, 0x0260, 6, 0x085C, 1, 0) +MX6_PAD_DECL(KEY_ROW3__ASRC_EXT_CLK, 0x064C, 0x0264, 1, 0x0794, 2, 0) +MX6_PAD_DECL(KEY_ROW3__HDMI_TX_DDC_SDA, 0x064C, 0x0264, 2, 0x0864, 1, 0) +MX6_PAD_DECL(KEY_ROW3__KEY_ROW3, 0x064C, 0x0264, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW3__I2C2_SDA, 0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0) +MX6_PAD_DECL(KEY_ROW3__GPIO4_IO13, 0x064C, 0x0264, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW3__SD1_VSELECT, 0x064C, 0x0264, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__FLEXCAN2_RX, 0x0650, 0x0268, 0, 0x07CC, 0, 0) +MX6_PAD_DECL(KEY_ROW4__IPU1_SISG5, 0x0650, 0x0268, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__USB_OTG_PWR, 0x0650, 0x0268, 2, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__KEY_ROW4, 0x0650, 0x0268, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__UART5_CTS_B, 0x0650, 0x0268, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__UART5_RTS_B, 0x0650, 0x0268, 4, 0x0918, 3, 0) +MX6_PAD_DECL(KEY_ROW4__GPIO4_IO15, 0x0650, 0x0268, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__NAND_ALE, 0x0654, 0x026C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__SD4_RESET, 0x0654, 0x026C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__GPIO6_IO08, 0x0654, 0x026C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__NAND_CLE, 0x0658, 0x0270, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__GPIO6_IO07, 0x0658, 0x0270, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS0__NAND_CE0_B, 0x065C, 0x0274, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS0__GPIO6_IO11, 0x065C, 0x0274, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__NAND_CE1_B, 0x0660, 0x0278, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__SD4_VSELECT, 0x0660, 0x0278, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__SD3_VSELECT, 0x0660, 0x0278, 2, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__GPIO6_IO14, 0x0660, 0x0278, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__NAND_CE2_B, 0x0664, 0x027C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__IPU1_SISG0, 0x0664, 0x027C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__ESAI_TX0, 0x0664, 0x027C, 2, 0x0844, 1, 0) +MX6_PAD_DECL(NANDF_CS2__EIM_CRE, 0x0664, 0x027C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__CCM_CLKO2, 0x0664, 0x027C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__GPIO6_IO15, 0x0664, 0x027C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__NAND_CE3_B, 0x0668, 0x0280, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__IPU1_SISG1, 0x0668, 0x0280, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__ESAI_TX1, 0x0668, 0x0280, 2, 0x0848, 1, 0) +MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26, 0x0668, 0x0280, 3, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16, 0x0668, 0x0280, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__I2C4_SDA, 0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, 0) +MX6_PAD_DECL(NANDF_D0__NAND_DATA00, 0x066C, 0x0284, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__SD1_DATA4, 0x066C, 0x0284, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__GPIO2_IO00, 0x066C, 0x0284, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__NAND_DATA01, 0x0670, 0x0288, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__SD1_DATA5, 0x0670, 0x0288, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__GPIO2_IO01, 0x0670, 0x0288, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__NAND_DATA02, 0x0674, 0x028C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__SD1_DATA6, 0x0674, 0x028C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__GPIO2_IO02, 0x0674, 0x028C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__NAND_DATA03, 0x0678, 0x0290, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__SD1_DATA7, 0x0678, 0x0290, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__GPIO2_IO03, 0x0678, 0x0290, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__NAND_DATA04, 0x067C, 0x0294, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__SD2_DATA4, 0x067C, 0x0294, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__GPIO2_IO04, 0x067C, 0x0294, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__NAND_DATA05, 0x0680, 0x0298, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__SD2_DATA5, 0x0680, 0x0298, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__GPIO2_IO05, 0x0680, 0x0298, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__NAND_DATA06, 0x0684, 0x029C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__SD2_DATA6, 0x0684, 0x029C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__GPIO2_IO06, 0x0684, 0x029C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__NAND_DATA07, 0x0688, 0x02A0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__SD2_DATA7, 0x0688, 0x02A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__GPIO2_IO07, 0x0688, 0x02A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__NAND_READY_B, 0x068C, 0x02A4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__GPIO6_IO10, 0x068C, 0x02A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__NAND_WP_B, 0x0690, 0x02A8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__GPIO6_IO09, 0x0690, 0x02A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__I2C4_SCL, 0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0) +MX6_PAD_DECL(RGMII_RD0__HSI_RX_READY, 0x0694, 0x02AC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD0__RGMII_RD0, 0x0694, 0x02AC, 1, 0x0818, 1, 0) +MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25, 0x0694, 0x02AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG, 0x0698, 0x02B0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD1__RGMII_RD1, 0x0698, 0x02B0, 1, 0x081C, 1, 0) +MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27, 0x0698, 0x02B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD2__HSI_TX_DATA, 0x069C, 0x02B4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD2__RGMII_RD2, 0x069C, 0x02B4, 1, 0x0820, 1, 0) +MX6_PAD_DECL(RGMII_RD2__GPIO6_IO28, 0x069C, 0x02B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD3__HSI_TX_WAKE, 0x06A0, 0x02B8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD3__RGMII_RD3, 0x06A0, 0x02B8, 1, 0x0824, 1, 0) +MX6_PAD_DECL(RGMII_RD3__GPIO6_IO29, 0x06A0, 0x02B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__USB_H3_DATA, 0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__RGMII_RX_CTL, 0x06A4, 0x02BC, 1, 0x0828, 1, 0) +MX6_PAD_DECL(RGMII_RX_CTL__GPIO6_IO24, 0x06A4, 0x02BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RXC__USBOH3_H3_STROBE, 0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RXC__USB_H3_STROBE, 0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP) +MX6_PAD_DECL(RGMII_RXC__RGMII_RXC, 0x06A8, 0x02C0, 1, 0x0814, 1, 0) +MX6_PAD_DECL(RGMII_RXC__GPIO6_IO30, 0x06A8, 0x02C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__HSI_TX_READY, 0x06AC, 0x02C4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__RGMII_TD0, 0x06AC, 0x02C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__GPIO6_IO20, 0x06AC, 0x02C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__HSI_RX_FLAG, 0x06B0, 0x02C8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__RGMII_TD1, 0x06B0, 0x02C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__GPIO6_IO21, 0x06B0, 0x02C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__HSI_RX_DATA, 0x06B4, 0x02CC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__RGMII_TD2, 0x06B4, 0x02CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__GPIO6_IO22, 0x06B4, 0x02CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__HSI_RX_WAKE, 0x06B8, 0x02D0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__RGMII_TD3, 0x06B8, 0x02D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__GPIO6_IO23, 0x06B8, 0x02D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__USBOH3_H2_STROBE, 0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE, 0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP) +MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL, 0x06BC, 0x02D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26, 0x06BC, 0x02D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x06BC, 0x02D4, 7, 0x080C, 1, 0) +MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA, 0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__RGMII_TXC, 0x06C0, 0x02D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK, 0x06C0, 0x02D8, 2, 0x08F4, 1, 0) +MX6_PAD_DECL(RGMII_TXC__GPIO6_IO19, 0x06C0, 0x02D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__XTALOSC_REF_CLK_24M, 0x06C0, 0x02D8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__SD1_CLK, 0x06C4, 0x02DC, 0, 0x0928, 1, 0) +MX6_PAD_DECL(SD1_CLK__GPT_CLKIN, 0x06C4, 0x02DC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__GPIO1_IO20, 0x06C4, 0x02DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__PWM4_OUT, 0x06C8, 0x02E0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1, 0x06C8, 0x02E0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__GPIO1_IO18, 0x06C8, 0x02E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__SD1_DATA0, 0x06CC, 0x02E4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__GPT_CAPTURE1, 0x06CC, 0x02E4, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__GPIO1_IO16, 0x06CC, 0x02E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__SD1_DATA1, 0x06D0, 0x02E8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__PWM3_OUT, 0x06D0, 0x02E8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__GPT_CAPTURE2, 0x06D0, 0x02E8, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__GPIO1_IO17, 0x06D0, 0x02E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__SD1_DATA2, 0x06D4, 0x02EC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__GPT_COMPARE2, 0x06D4, 0x02EC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__PWM2_OUT, 0x06D4, 0x02EC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__WDOG1_B, 0x06D4, 0x02EC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__GPIO1_IO19, 0x06D4, 0x02EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__WDOG1_RESET_B_DEB, 0x06D4, 0x02EC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__SD1_DATA3, 0x06D8, 0x02F0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__GPT_COMPARE3, 0x06D8, 0x02F0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__PWM1_OUT, 0x06D8, 0x02F0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__WDOG2_B, 0x06D8, 0x02F0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21, 0x06D8, 0x02F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB, 0x06D8, 0x02F0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CLK__SD2_CLK, 0x06DC, 0x02F4, 0, 0x0930, 1, 0) +MX6_PAD_DECL(SD2_CLK__KEY_COL5, 0x06DC, 0x02F4, 2, 0x08C0, 3, 0) +MX6_PAD_DECL(SD2_CLK__AUD4_RXFS, 0x06DC, 0x02F4, 3, 0x07A4, 1, 0) +MX6_PAD_DECL(SD2_CLK__GPIO1_IO10, 0x06DC, 0x02F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CMD__KEY_ROW5, 0x06E0, 0x02F8, 2, 0x08CC, 2, 0) +MX6_PAD_DECL(SD2_CMD__AUD4_RXC, 0x06E0, 0x02F8, 3, 0x07A0, 1, 0) +MX6_PAD_DECL(SD2_CMD__GPIO1_IO11, 0x06E0, 0x02F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__SD2_DATA0, 0x06E4, 0x02FC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__AUD4_RXD, 0x06E4, 0x02FC, 3, 0x0798, 1, 0) +MX6_PAD_DECL(SD2_DAT0__KEY_ROW7, 0x06E4, 0x02FC, 4, 0x08D4, 2, 0) +MX6_PAD_DECL(SD2_DAT0__GPIO1_IO15, 0x06E4, 0x02FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__DCIC2_OUT, 0x06E4, 0x02FC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__SD2_DATA1, 0x06E8, 0x0300, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__EIM_CS2_B, 0x06E8, 0x0300, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__AUD4_TXFS, 0x06E8, 0x0300, 3, 0x07AC, 1, 0) +MX6_PAD_DECL(SD2_DAT1__KEY_COL7, 0x06E8, 0x0300, 4, 0x08C8, 2, 0) +MX6_PAD_DECL(SD2_DAT1__GPIO1_IO14, 0x06E8, 0x0300, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__SD2_DATA2, 0x06EC, 0x0304, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__EIM_CS3_B, 0x06EC, 0x0304, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__AUD4_TXD, 0x06EC, 0x0304, 3, 0x079C, 1, 0) +MX6_PAD_DECL(SD2_DAT2__KEY_ROW6, 0x06EC, 0x0304, 4, 0x08D0, 2, 0) +MX6_PAD_DECL(SD2_DAT2__GPIO1_IO13, 0x06EC, 0x0304, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__SD2_DATA3, 0x06F0, 0x0308, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__KEY_COL6, 0x06F0, 0x0308, 2, 0x08C4, 2, 0) +MX6_PAD_DECL(SD2_DAT3__AUD4_TXC, 0x06F0, 0x0308, 3, 0x07A8, 1, 0) +MX6_PAD_DECL(SD2_DAT3__GPIO1_IO12, 0x06F0, 0x0308, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__SD3_CLK, 0x06F4, 0x030C, 0, 0x0934, 1, 0) +MX6_PAD_DECL(SD3_CLK__UART2_CTS_B, 0x06F4, 0x030C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__UART2_RTS_B, 0x06F4, 0x030C, 1, 0x0900, 2, 0) +MX6_PAD_DECL(SD3_CLK__FLEXCAN1_RX, 0x06F4, 0x030C, 2, 0x07C8, 2, 0) +MX6_PAD_DECL(SD3_CLK__GPIO7_IO03, 0x06F4, 0x030C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__UART2_CTS_B, 0x06F8, 0x0310, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__UART2_RTS_B, 0x06F8, 0x0310, 1, 0x0900, 3, 0) +MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX, 0x06F8, 0x0310, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__GPIO7_IO02, 0x06F8, 0x0310, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__SD3_DATA0, 0x06FC, 0x0314, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__UART1_CTS_B, 0x06FC, 0x0314, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__UART1_RTS_B, 0x06FC, 0x0314, 1, 0x08F8, 2, 0) +MX6_PAD_DECL(SD3_DAT0__FLEXCAN2_TX, 0x06FC, 0x0314, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__GPIO7_IO04, 0x06FC, 0x0314, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__SD3_DATA1, 0x0700, 0x0318, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__UART1_CTS_B, 0x0700, 0x0318, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__UART1_RTS_B, 0x0700, 0x0318, 1, 0x08F8, 3, 0) +MX6_PAD_DECL(SD3_DAT1__FLEXCAN2_RX, 0x0700, 0x0318, 2, 0x07CC, 1, 0) +MX6_PAD_DECL(SD3_DAT1__GPIO7_IO05, 0x0700, 0x0318, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT2__SD3_DATA2, 0x0704, 0x031C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT2__GPIO7_IO06, 0x0704, 0x031C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__SD3_DATA3, 0x0708, 0x0320, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__UART3_CTS_B, 0x0708, 0x0320, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__UART3_RTS_B, 0x0708, 0x0320, 1, 0x0908, 4, 0) +MX6_PAD_DECL(SD3_DAT3__GPIO7_IO07, 0x0708, 0x0320, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__SD3_DATA4, 0x070C, 0x0324, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA, 0x070C, 0x0324, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA, 0x070C, 0x0324, 1, 0x0904, 4, 0) +MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01, 0x070C, 0x0324, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__SD3_DATA5, 0x0710, 0x0328, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__UART2_TX_DATA, 0x0710, 0x0328, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__UART2_RX_DATA, 0x0710, 0x0328, 1, 0x0904, 5, 0) +MX6_PAD_DECL(SD3_DAT5__GPIO7_IO00, 0x0710, 0x0328, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__SD3_DATA6, 0x0714, 0x032C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__UART1_TX_DATA, 0x0714, 0x032C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__UART1_RX_DATA, 0x0714, 0x032C, 1, 0x08FC, 2, 0) +MX6_PAD_DECL(SD3_DAT6__GPIO6_IO18, 0x0714, 0x032C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__SD3_DATA7, 0x0718, 0x0330, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__UART1_TX_DATA, 0x0718, 0x0330, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__UART1_RX_DATA, 0x0718, 0x0330, 1, 0x08FC, 3, 0) +MX6_PAD_DECL(SD3_DAT7__GPIO6_IO17, 0x0718, 0x0330, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__SD3_RESET, 0x071C, 0x0334, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__UART3_CTS_B, 0x071C, 0x0334, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__UART3_RTS_B, 0x071C, 0x0334, 1, 0x0908, 5, 0) +MX6_PAD_DECL(SD3_RST__GPIO7_IO08, 0x071C, 0x0334, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__SD4_CLK, 0x0720, 0x0338, 0, 0x0938, 1, 0) +MX6_PAD_DECL(SD4_CLK__NAND_WE_B, 0x0720, 0x0338, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__UART3_TX_DATA, 0x0720, 0x0338, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__UART3_RX_DATA, 0x0720, 0x0338, 2, 0x090C, 2, 0) +MX6_PAD_DECL(SD4_CLK__GPIO7_IO10, 0x0720, 0x0338, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__NAND_RE_B, 0x0724, 0x033C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA, 0x0724, 0x033C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA, 0x0724, 0x033C, 2, 0x090C, 3, 0) +MX6_PAD_DECL(SD4_CMD__GPIO7_IO09, 0x0724, 0x033C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__SD4_DATA0, 0x0728, 0x0340, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__NAND_DQS, 0x0728, 0x0340, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__GPIO2_IO08, 0x0728, 0x0340, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__SD4_DATA1, 0x072C, 0x0344, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__PWM3_OUT, 0x072C, 0x0344, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__GPIO2_IO09, 0x072C, 0x0344, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__SD4_DATA2, 0x0730, 0x0348, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__PWM4_OUT, 0x0730, 0x0348, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__GPIO2_IO10, 0x0730, 0x0348, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT3__SD4_DATA3, 0x0734, 0x034C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT3__GPIO2_IO11, 0x0734, 0x034C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__SD4_DATA4, 0x0738, 0x0350, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__UART2_TX_DATA, 0x0738, 0x0350, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__UART2_RX_DATA, 0x0738, 0x0350, 2, 0x0904, 6, 0) +MX6_PAD_DECL(SD4_DAT4__GPIO2_IO12, 0x0738, 0x0350, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__SD4_DATA5, 0x073C, 0x0354, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__UART2_CTS_B, 0x073C, 0x0354, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__UART2_RTS_B, 0x073C, 0x0354, 2, 0x0900, 4, 0) +MX6_PAD_DECL(SD4_DAT5__GPIO2_IO13, 0x073C, 0x0354, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__SD4_DATA6, 0x0740, 0x0358, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__UART2_CTS_B, 0x0740, 0x0358, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__UART2_RTS_B, 0x0740, 0x0358, 2, 0x0900, 5, 0) +MX6_PAD_DECL(SD4_DAT6__GPIO2_IO14, 0x0740, 0x0358, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__SD4_DATA7, 0x0744, 0x035C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__UART2_TX_DATA, 0x0744, 0x035C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__UART2_RX_DATA, 0x0744, 0x035C, 2, 0x0904, 7, 0) +MX6_PAD_DECL(SD4_DAT7__GPIO2_IO15, 0x0744, 0x035C, 5, 0x0000, 0, 0) -enum { - MX6_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__AUD3_RXC = IOMUX_PAD(0x0360, 0x004C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0360, 0x004C, 2, 0x07F8, 0, 0), - MX6_PAD_CSI0_DAT10__UART1_TX_DATA = IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__UART1_RX_DATA = IOMUX_PAD(0x0360, 0x004C, 3, 0x08FC, 0, 0), - MX6_PAD_CSI0_DAT10__GPIO5_IO28 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__ARM_TRACE07 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__AUD3_RXFS = IOMUX_PAD(0x0364, 0x0050, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0800, 0, 0), - MX6_PAD_CSI0_DAT11__UART1_TX_DATA = IOMUX_PAD(0x0364, 0x0050, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__UART1_RX_DATA = IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0), - MX6_PAD_CSI0_DAT11__GPIO5_IO29 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__ARM_TRACE08 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__EIM_DATA08 = IOMUX_PAD(0x0368, 0x0054, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_TX_DATA = IOMUX_PAD(0x0368, 0x0054, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_RX_DATA = IOMUX_PAD(0x0368, 0x0054, 3, 0x0914, 0, 0), - MX6_PAD_CSI0_DAT12__GPIO5_IO30 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__ARM_TRACE09 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__EIM_DATA09 = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_TX_DATA = IOMUX_PAD(0x036C, 0x0058, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_RX_DATA = IOMUX_PAD(0x036C, 0x0058, 3, 0x0914, 1, 0), - MX6_PAD_CSI0_DAT13__GPIO5_IO31 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__ARM_TRACE10 = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__EIM_DATA10 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_TX_DATA = IOMUX_PAD(0x0370, 0x005C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_RX_DATA = IOMUX_PAD(0x0370, 0x005C, 3, 0x091C, 0, 0), - MX6_PAD_CSI0_DAT14__GPIO6_IO00 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__ARM_TRACE11 = IOMUX_PAD(0x0370, 0x005C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__EIM_DATA11 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_TX_DATA = IOMUX_PAD(0x0374, 0x0060, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_RX_DATA = IOMUX_PAD(0x0374, 0x0060, 3, 0x091C, 1, 0), - MX6_PAD_CSI0_DAT15__GPIO6_IO01 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__ARM_TRACE12 = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__EIM_DATA12 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_CTS_B = IOMUX_PAD(0x0378, 0x0064, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_RTS_B = IOMUX_PAD(0x0378, 0x0064, 3, 0x0910, 0, 0), - MX6_PAD_CSI0_DAT16__GPIO6_IO02 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__ARM_TRACE13 = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__EIM_DATA13 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__UART4_CTS_B = IOMUX_PAD(0x037C, 0x0068, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__UART4_RTS_B = IOMUX_PAD(0x037C, 0x0068, 3, 0x0910, 1, 0), - MX6_PAD_CSI0_DAT17__GPIO6_IO03 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__ARM_TRACE14 = IOMUX_PAD(0x037C, 0x0068, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__EIM_DATA14 = IOMUX_PAD(0x0380, 0x006C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_CTS_B = IOMUX_PAD(0x0380, 0x006C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_RTS_B = IOMUX_PAD(0x0380, 0x006C, 3, 0x0918, 0, 0), - MX6_PAD_CSI0_DAT18__GPIO6_IO04 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__ARM_TRACE15 = IOMUX_PAD(0x0380, 0x006C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__EIM_DATA15 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__UART5_CTS_B = IOMUX_PAD(0x0384, 0x0070, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__UART5_RTS_B = IOMUX_PAD(0x0384, 0x0070, 3, 0x0918, 1, 0), - MX6_PAD_CSI0_DAT19__GPIO6_IO05 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__EIM_DATA02 = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0388, 0x0074, 2, 0x07D8, 0, 0), - MX6_PAD_CSI0_DAT4__KEY_COL5 = IOMUX_PAD(0x0388, 0x0074, 3, 0x08C0, 0, 0), - MX6_PAD_CSI0_DAT4__AUD3_TXC = IOMUX_PAD(0x0388, 0x0074, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__GPIO5_IO22 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__ARM_TRACE01 = IOMUX_PAD(0x0388, 0x0074, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__EIM_DATA03 = IOMUX_PAD(0x038C, 0x0078, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x038C, 0x0078, 2, 0x07E0, 0, 0), - MX6_PAD_CSI0_DAT5__KEY_ROW5 = IOMUX_PAD(0x038C, 0x0078, 3, 0x08CC, 0, 0), - MX6_PAD_CSI0_DAT5__AUD3_TXD = IOMUX_PAD(0x038C, 0x0078, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__GPIO5_IO23 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__ARM_TRACE02 = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__EIM_DATA04 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0390, 0x007C, 2, 0x07DC, 0, 0), - MX6_PAD_CSI0_DAT6__KEY_COL6 = IOMUX_PAD(0x0390, 0x007C, 3, 0x08C4, 0, 0), - MX6_PAD_CSI0_DAT6__AUD3_TXFS = IOMUX_PAD(0x0390, 0x007C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__GPIO5_IO24 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__ARM_TRACE03 = IOMUX_PAD(0x0390, 0x007C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__EIM_DATA05 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0394, 0x0080, 2, 0x07E4, 0, 0), - MX6_PAD_CSI0_DAT7__KEY_ROW6 = IOMUX_PAD(0x0394, 0x0080, 3, 0x08D0, 0, 0), - MX6_PAD_CSI0_DAT7__AUD3_RXD = IOMUX_PAD(0x0394, 0x0080, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__GPIO5_IO25 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__ARM_TRACE04 = IOMUX_PAD(0x0394, 0x0080, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__EIM_DATA06 = IOMUX_PAD(0x0398, 0x0084, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0398, 0x0084, 2, 0x07F4, 0, 0), - MX6_PAD_CSI0_DAT8__KEY_COL7 = IOMUX_PAD(0x0398, 0x0084, 3, 0x08C8, 0, 0), - MX6_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0), - MX6_PAD_CSI0_DAT8__GPIO5_IO26 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__ARM_TRACE05 = IOMUX_PAD(0x0398, 0x0084, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__EIM_DATA07 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x039C, 0x0088, 2, 0x07FC, 0, 0), - MX6_PAD_CSI0_DAT9__KEY_ROW7 = IOMUX_PAD(0x039C, 0x0088, 3, 0x08D4, 0, 0), - MX6_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0), - MX6_PAD_CSI0_DAT9__GPIO5_IO27 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__ARM_TRACE06 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__EIM_DATA00 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__ARM_TRACE_CLK = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__CCM_CLKO1 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__GPIO5_IO19 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__ARM_TRACE_CTL = IOMUX_PAD(0x03A4, 0x0090, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__ARM_EVENTO = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__EIM_DATA01 = IOMUX_PAD(0x03AC, 0x0098, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__GPIO5_IO21 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__ARM_TRACE00 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_DISP_CLK__LCD_CLK = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__GPIO4_IO16 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__LCD_WR_RWN = IOMUX_PAD(0x03B0, 0x009C, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN15__LCD_ENABLE = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__AUD6_TXC = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__GPIO4_IO17 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__LCD_RD_E = IOMUX_PAD(0x03B4, 0x00A0, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN2__LCD_HSYNC = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x08D8, 0, 0), - MX6_PAD_DI0_PIN2__AUD6_TXD = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__GPIO4_IO18 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__LCD_RS = IOMUX_PAD(0x03B8, 0x00A4, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN3__LCD_VSYNC = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__AUD6_TXFS = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__GPIO4_IO19 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__LCD_CS = IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN4__LCD_BUSY = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, 0), - MX6_PAD_DI0_PIN4__AUD6_RXD = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__SD1_WP = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x092C, 0, 0), - MX6_PAD_DI0_PIN4__GPIO4_IO20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__LCD_RESET = IOMUX_PAD(0x03C0, 0x00AC, 8, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT0__LCD_DATA00 = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__GPIO4_IO21 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT1__LCD_DATA01 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__GPIO4_IO22 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__LCD_DATA10 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT10__GPIO4_IO31 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT11__LCD_DATA11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__GPIO5_IO05 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT12__LCD_DATA12 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__GPIO5_IO06 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT13__LCD_DATA13 = IOMUX_PAD(0x03D8, 0x00C4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__AUD5_RXFS = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x07BC, 0, 0), - MX6_PAD_DISP0_DAT13__GPIO5_IO07 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT14__LCD_DATA14 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__AUD5_RXC = IOMUX_PAD(0x03DC, 0x00C8, 3, 0x07B8, 0, 0), - MX6_PAD_DISP0_DAT14__GPIO5_IO08 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT15__LCD_DATA15 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x07E8, 0, 0), - MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0804, 0, 0), - MX6_PAD_DISP0_DAT15__GPIO5_IO09 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT16__LCD_DATA16 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x07FC, 1, 0), - MX6_PAD_DISP0_DAT16__AUD5_TXC = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x07C0, 0, 0), - MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x08E8, 0, 0), - MX6_PAD_DISP0_DAT16__GPIO5_IO10 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT17__LCD_DATA17 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x07F8, 1, 0), - MX6_PAD_DISP0_DAT17__AUD5_TXD = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x07B4, 0, 0), - MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x08EC, 0, 0), - MX6_PAD_DISP0_DAT17__GPIO5_IO11 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT18__LCD_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x0800, 1, 0), - MX6_PAD_DISP0_DAT18__AUD5_TXFS = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x07C4, 0, 0), - MX6_PAD_DISP0_DAT18__AUD4_RXFS = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x07A4, 0, 0), - MX6_PAD_DISP0_DAT18__GPIO5_IO12 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__EIM_CS2_B = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT19__LCD_DATA19 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x07F4, 1, 0), - MX6_PAD_DISP0_DAT19__AUD5_RXD = IOMUX_PAD(0x03F0, 0x00DC, 3, 0x07B0, 0, 0), - MX6_PAD_DISP0_DAT19__AUD4_RXC = IOMUX_PAD(0x03F0, 0x00DC, 4, 0x07A0, 0, 0), - MX6_PAD_DISP0_DAT19__GPIO5_IO13 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__EIM_CS3_B = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__LCD_DATA02 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__GPIO4_IO23 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT20__LCD_DATA20 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x07D8, 1, 0), - MX6_PAD_DISP0_DAT20__AUD4_TXC = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x07A8, 0, 0), - MX6_PAD_DISP0_DAT20__GPIO5_IO14 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT21__LCD_DATA21 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x07E0, 1, 0), - MX6_PAD_DISP0_DAT21__AUD4_TXD = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x079C, 0, 0), - MX6_PAD_DISP0_DAT21__GPIO5_IO15 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT22__LCD_DATA22 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x0400, 0x00EC, 2, 0x07DC, 1, 0), - MX6_PAD_DISP0_DAT22__AUD4_TXFS = IOMUX_PAD(0x0400, 0x00EC, 3, 0x07AC, 0, 0), - MX6_PAD_DISP0_DAT22__GPIO5_IO16 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT23__LCD_DATA23 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x07E4, 1, 0), - MX6_PAD_DISP0_DAT23__AUD4_RXD = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0798, 0, 0), - MX6_PAD_DISP0_DAT23__GPIO5_IO17 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT3__LCD_DATA03 = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0408, 0x00F4, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__GPIO4_IO24 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT4__LCD_DATA04 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__GPIO4_IO25 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT5__LCD_DATA05 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__AUD6_RXFS = IOMUX_PAD(0x0410, 0x00FC, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__GPIO4_IO26 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT6__LCD_DATA06 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x0414, 0x0100, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__AUD6_RXC = IOMUX_PAD(0x0414, 0x0100, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__GPIO4_IO27 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT7__LCD_DATA07 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x0418, 0x0104, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__GPIO4_IO28 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT8__LCD_DATA08 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__PWM1_OUT = IOMUX_PAD(0x041C, 0x0108, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__WDOG1_B = IOMUX_PAD(0x041C, 0x0108, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__GPIO4_IO29 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT9__LCD_DATA09 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__PWM2_OUT = IOMUX_PAD(0x0420, 0x010C, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__WDOG2_B = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__GPIO4_IO30 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A16__EIM_ADDR16 = IOMUX_PAD(0x04E0, 0x0110, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x04E0, 0x0110, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A16__IPU1_CSI1_PIXCLK = IOMUX_PAD(0x04E0, 0x0110, 2, 0x08B8, 0, 0), - MX6_PAD_EIM_A16__GPIO2_IO22 = IOMUX_PAD(0x04E0, 0x0110, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A16__SRC_BOOT_CFG16 = IOMUX_PAD(0x04E0, 0x0110, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A16__EPDC_DATA00 = IOMUX_PAD(0x04E0, 0x0110, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A17__EIM_ADDR17 = IOMUX_PAD(0x04E4, 0x0114, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 = IOMUX_PAD(0x04E4, 0x0114, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU1_CSI1_DATA12 = IOMUX_PAD(0x04E4, 0x0114, 2, 0x0890, 0, 0), - MX6_PAD_EIM_A17__GPIO2_IO21 = IOMUX_PAD(0x04E4, 0x0114, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A17__SRC_BOOT_CFG17 = IOMUX_PAD(0x04E4, 0x0114, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A17__EPDC_PWR_STAT = IOMUX_PAD(0x04E4, 0x0114, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A18__EIM_ADDR18 = IOMUX_PAD(0x04E8, 0x0118, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 = IOMUX_PAD(0x04E8, 0x0118, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU1_CSI1_DATA13 = IOMUX_PAD(0x04E8, 0x0118, 2, 0x0894, 0, 0), - MX6_PAD_EIM_A18__GPIO2_IO20 = IOMUX_PAD(0x04E8, 0x0118, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A18__SRC_BOOT_CFG18 = IOMUX_PAD(0x04E8, 0x0118, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A18__EPDC_PWR_CTRL0 = IOMUX_PAD(0x04E8, 0x0118, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A19__EIM_ADDR19 = IOMUX_PAD(0x04EC, 0x011C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 = IOMUX_PAD(0x04EC, 0x011C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU1_CSI1_DATA14 = IOMUX_PAD(0x04EC, 0x011C, 2, 0x0898, 0, 0), - MX6_PAD_EIM_A19__GPIO2_IO19 = IOMUX_PAD(0x04EC, 0x011C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A19__SRC_BOOT_CFG19 = IOMUX_PAD(0x04EC, 0x011C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A19__EPDC_PWR_CTRL1 = IOMUX_PAD(0x04EC, 0x011C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A20__EIM_ADDR20 = IOMUX_PAD(0x04F0, 0x0120, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 = IOMUX_PAD(0x04F0, 0x0120, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU1_CSI1_DATA15 = IOMUX_PAD(0x04F0, 0x0120, 2, 0x089C, 0, 0), - MX6_PAD_EIM_A20__GPIO2_IO18 = IOMUX_PAD(0x04F0, 0x0120, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A20__SRC_BOOT_CFG20 = IOMUX_PAD(0x04F0, 0x0120, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A20__EPDC_PWR_CTRL2 = IOMUX_PAD(0x04F0, 0x0120, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A21__EIM_ADDR21 = IOMUX_PAD(0x04F4, 0x0124, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 = IOMUX_PAD(0x04F4, 0x0124, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU1_CSI1_DATA16 = IOMUX_PAD(0x04F4, 0x0124, 2, 0x08A0, 0, 0), - MX6_PAD_EIM_A21__GPIO2_IO17 = IOMUX_PAD(0x04F4, 0x0124, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A21__SRC_BOOT_CFG21 = IOMUX_PAD(0x04F4, 0x0124, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A21__EPDC_GDCLK = IOMUX_PAD(0x04F4, 0x0124, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A22__EIM_ADDR22 = IOMUX_PAD(0x04F8, 0x0128, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 = IOMUX_PAD(0x04F8, 0x0128, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU1_CSI1_DATA17 = IOMUX_PAD(0x04F8, 0x0128, 2, 0x08A4, 0, 0), - MX6_PAD_EIM_A22__GPIO2_IO16 = IOMUX_PAD(0x04F8, 0x0128, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A22__SRC_BOOT_CFG22 = IOMUX_PAD(0x04F8, 0x0128, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A22__EPDC_GDSP = IOMUX_PAD(0x04F8, 0x0128, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A23__EIM_ADDR23 = IOMUX_PAD(0x04FC, 0x012C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 = IOMUX_PAD(0x04FC, 0x012C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_CSI1_DATA18 = IOMUX_PAD(0x04FC, 0x012C, 2, 0x08A8, 0, 0), - MX6_PAD_EIM_A23__IPU1_SISG3 = IOMUX_PAD(0x04FC, 0x012C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A23__GPIO6_IO06 = IOMUX_PAD(0x04FC, 0x012C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A23__SRC_BOOT_CFG23 = IOMUX_PAD(0x04FC, 0x012C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A23__EPDC_GDOE = IOMUX_PAD(0x04FC, 0x012C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A24__EIM_ADDR24 = IOMUX_PAD(0x0500, 0x0130, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 = IOMUX_PAD(0x0500, 0x0130, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_CSI1_DATA19 = IOMUX_PAD(0x0500, 0x0130, 2, 0x08AC, 0, 0), - MX6_PAD_EIM_A24__IPU1_SISG2 = IOMUX_PAD(0x0500, 0x0130, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A24__GPIO5_IO04 = IOMUX_PAD(0x0500, 0x0130, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A24__SRC_BOOT_CFG24 = IOMUX_PAD(0x0500, 0x0130, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A24__EPDC_GDRL = IOMUX_PAD(0x0500, 0x0130, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A25__EIM_ADDR25 = IOMUX_PAD(0x0504, 0x0134, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x0504, 0x0134, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x0504, 0x0134, 2, 0x0000, 0, 0), - MX6_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x0504, 0x0134, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x0504, 0x0134, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A25__GPIO5_IO02 = IOMUX_PAD(0x0504, 0x0134, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x0504, 0x0134, 6, 0x085C, 0, 0), - MX6_PAD_EIM_A25__EPDC_DATA15 = IOMUX_PAD(0x0504, 0x0134, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A25__EIM_ACLK_FREERUN = IOMUX_PAD(0x0504, 0x0134, 9, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__EIM_BCLK = IOMUX_PAD(0x0508, 0x0138, 0, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x0508, 0x0138, 1, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__GPIO6_IO31 = IOMUX_PAD(0x0508, 0x0138, 5, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__EPDC_SDCE9 = IOMUX_PAD(0x0508, 0x0138, 8, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__EIM_CS0_B = IOMUX_PAD(0x050C, 0x013C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__IPU1_DI1_PIN05 = IOMUX_PAD(0x050C, 0x013C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x050C, 0x013C, 2, 0x07F4, 2, 0), - MX6_PAD_EIM_CS0__GPIO2_IO23 = IOMUX_PAD(0x050C, 0x013C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__EPDC_DATA06 = IOMUX_PAD(0x050C, 0x013C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__EIM_CS1_B = IOMUX_PAD(0x0510, 0x0140, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__IPU1_DI1_PIN06 = IOMUX_PAD(0x0510, 0x0140, 1, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0510, 0x0140, 2, 0x07FC, 2, 0), - MX6_PAD_EIM_CS1__GPIO2_IO24 = IOMUX_PAD(0x0510, 0x0140, 5, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__EPDC_DATA08 = IOMUX_PAD(0x0510, 0x0140, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D16__EIM_DATA16 = IOMUX_PAD(0x0514, 0x0144, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0), - MX6_PAD_EIM_D16__IPU1_DI0_PIN05 = IOMUX_PAD(0x0514, 0x0144, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D16__IPU1_CSI1_DATA18 = IOMUX_PAD(0x0514, 0x0144, 3, 0x08A8, 1, 0), - MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x0514, 0x0144, 4, 0x0864, 0, 0), - MX6_PAD_EIM_D16__GPIO3_IO16 = IOMUX_PAD(0x0514, 0x0144, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, 0), - MX6_PAD_EIM_D16__EPDC_DATA10 = IOMUX_PAD(0x0514, 0x0144, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D17__EIM_DATA17 = IOMUX_PAD(0x0518, 0x0148, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0), - MX6_PAD_EIM_D17__IPU1_DI0_PIN06 = IOMUX_PAD(0x0518, 0x0148, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D17__IPU1_CSI1_PIXCLK = IOMUX_PAD(0x0518, 0x0148, 3, 0x08B8, 1, 0), - MX6_PAD_EIM_D17__DCIC1_OUT = IOMUX_PAD(0x0518, 0x0148, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D17__GPIO3_IO17 = IOMUX_PAD(0x0518, 0x0148, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, 0), - MX6_PAD_EIM_D17__EPDC_VCOM0 = IOMUX_PAD(0x0518, 0x0148, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D18__EIM_DATA18 = IOMUX_PAD(0x051C, 0x014C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0), - MX6_PAD_EIM_D18__IPU1_DI0_PIN07 = IOMUX_PAD(0x051C, 0x014C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D18__IPU1_CSI1_DATA17 = IOMUX_PAD(0x051C, 0x014C, 3, 0x08A4, 1, 0), - MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x051C, 0x014C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D18__GPIO3_IO18 = IOMUX_PAD(0x051C, 0x014C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0), - MX6_PAD_EIM_D18__EPDC_VCOM1 = IOMUX_PAD(0x051C, 0x014C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D19__EIM_DATA19 = IOMUX_PAD(0x0520, 0x0150, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x0520, 0x0150, 1, 0x07E8, 1, 0), - MX6_PAD_EIM_D19__IPU1_DI0_PIN08 = IOMUX_PAD(0x0520, 0x0150, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D19__IPU1_CSI1_DATA16 = IOMUX_PAD(0x0520, 0x0150, 3, 0x08A0, 1, 0), - MX6_PAD_EIM_D19__UART1_CTS_B = IOMUX_PAD(0x0520, 0x0150, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D19__UART1_RTS_B = IOMUX_PAD(0x0520, 0x0150, 4, 0x08F8, 0, 0), - MX6_PAD_EIM_D19__GPIO3_IO19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D19__EPIT1_OUT = IOMUX_PAD(0x0520, 0x0150, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D19__EPDC_DATA12 = IOMUX_PAD(0x0520, 0x0150, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D20__EIM_DATA20 = IOMUX_PAD(0x0524, 0x0154, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x0524, 0x0154, 1, 0x0808, 0, 0), - MX6_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x0524, 0x0154, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D20__IPU1_CSI1_DATA15 = IOMUX_PAD(0x0524, 0x0154, 3, 0x089C, 1, 0), - MX6_PAD_EIM_D20__UART1_CTS_B = IOMUX_PAD(0x0524, 0x0154, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D20__UART1_RTS_B = IOMUX_PAD(0x0524, 0x0154, 4, 0x08F8, 1, 0), - MX6_PAD_EIM_D20__GPIO3_IO20 = IOMUX_PAD(0x0524, 0x0154, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D20__EPIT2_OUT = IOMUX_PAD(0x0524, 0x0154, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D21__EIM_DATA21 = IOMUX_PAD(0x0528, 0x0158, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x0528, 0x0158, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x0528, 0x0158, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D21__IPU1_CSI1_DATA11 = IOMUX_PAD(0x0528, 0x0158, 3, 0x088C, 0, 0), - MX6_PAD_EIM_D21__USB_OTG_OC = IOMUX_PAD(0x0528, 0x0158, 4, 0x0920, 0, 0), - MX6_PAD_EIM_D21__GPIO3_IO21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0), - MX6_PAD_EIM_D21__SPDIF_IN = IOMUX_PAD(0x0528, 0x0158, 7, 0x08F0, 0, 0), - MX6_PAD_EIM_D22__EIM_DATA22 = IOMUX_PAD(0x052C, 0x015C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x052C, 0x015C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU1_DI0_PIN01 = IOMUX_PAD(0x052C, 0x015C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU1_CSI1_DATA10 = IOMUX_PAD(0x052C, 0x015C, 3, 0x0888, 0, 0), - MX6_PAD_EIM_D22__USB_OTG_PWR = IOMUX_PAD(0x052C, 0x015C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D22__GPIO3_IO22 = IOMUX_PAD(0x052C, 0x015C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D22__SPDIF_OUT = IOMUX_PAD(0x052C, 0x015C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D22__EPDC_SDCE6 = IOMUX_PAD(0x052C, 0x015C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D23__EIM_DATA23 = IOMUX_PAD(0x0530, 0x0160, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x0530, 0x0160, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D23__UART3_CTS_B = IOMUX_PAD(0x0530, 0x0160, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D23__UART3_RTS_B = IOMUX_PAD(0x0530, 0x0160, 2, 0x0908, 0, 0), - MX6_PAD_EIM_D23__UART1_DCD_B = IOMUX_PAD(0x0530, 0x0160, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_CSI1_DATA_EN = IOMUX_PAD(0x0530, 0x0160, 4, 0x08B0, 0, 0), - MX6_PAD_EIM_D23__GPIO3_IO23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI1_PIN02 = IOMUX_PAD(0x0530, 0x0160, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x0530, 0x0160, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D23__EPDC_DATA11 = IOMUX_PAD(0x0530, 0x0160, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D24__EIM_DATA24 = IOMUX_PAD(0x0534, 0x0164, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x0534, 0x0164, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_TX_DATA = IOMUX_PAD(0x0534, 0x0164, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_RX_DATA = IOMUX_PAD(0x0534, 0x0164, 2, 0x090C, 0, 0), - MX6_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x0534, 0x0164, 3, 0x07EC, 0, 0), - MX6_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x0534, 0x0164, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D24__GPIO3_IO24 = IOMUX_PAD(0x0534, 0x0164, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D24__AUD5_RXFS = IOMUX_PAD(0x0534, 0x0164, 6, 0x07BC, 1, 0), - MX6_PAD_EIM_D24__UART1_DTR_B = IOMUX_PAD(0x0534, 0x0164, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D24__EPDC_SDCE7 = IOMUX_PAD(0x0534, 0x0164, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D25__EIM_DATA25 = IOMUX_PAD(0x0538, 0x0168, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x0538, 0x0168, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D25__UART3_TX_DATA = IOMUX_PAD(0x0538, 0x0168, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D25__UART3_RX_DATA = IOMUX_PAD(0x0538, 0x0168, 2, 0x090C, 1, 0), - MX6_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x0538, 0x0168, 3, 0x07F0, 0, 0), - MX6_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x0538, 0x0168, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D25__GPIO3_IO25 = IOMUX_PAD(0x0538, 0x0168, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D25__AUD5_RXC = IOMUX_PAD(0x0538, 0x0168, 6, 0x07B8, 1, 0), - MX6_PAD_EIM_D25__UART1_DSR_B = IOMUX_PAD(0x0538, 0x0168, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D25__EPDC_SDCE8 = IOMUX_PAD(0x0538, 0x0168, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D26__EIM_DATA26 = IOMUX_PAD(0x053C, 0x016C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x053C, 0x016C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_CSI0_DATA01 = IOMUX_PAD(0x053C, 0x016C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_CSI1_DATA14 = IOMUX_PAD(0x053C, 0x016C, 3, 0x0898, 1, 0), - MX6_PAD_EIM_D26__UART2_TX_DATA = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D26__UART2_RX_DATA = IOMUX_PAD(0x053C, 0x016C, 4, 0x0904, 0, 0), - MX6_PAD_EIM_D26__GPIO3_IO26 = IOMUX_PAD(0x053C, 0x016C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_SISG2 = IOMUX_PAD(0x053C, 0x016C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 = IOMUX_PAD(0x053C, 0x016C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D26__EPDC_SDOED = IOMUX_PAD(0x053C, 0x016C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D27__EIM_DATA27 = IOMUX_PAD(0x0540, 0x0170, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x0540, 0x0170, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_CSI0_DATA00 = IOMUX_PAD(0x0540, 0x0170, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_CSI1_DATA13 = IOMUX_PAD(0x0540, 0x0170, 3, 0x0894, 1, 0), - MX6_PAD_EIM_D27__UART2_TX_DATA = IOMUX_PAD(0x0540, 0x0170, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D27__UART2_RX_DATA = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0), - MX6_PAD_EIM_D27__GPIO3_IO27 = IOMUX_PAD(0x0540, 0x0170, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_SISG3 = IOMUX_PAD(0x0540, 0x0170, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 = IOMUX_PAD(0x0540, 0x0170, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D27__EPDC_SDOE = IOMUX_PAD(0x0540, 0x0170, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D28__EIM_DATA28 = IOMUX_PAD(0x0544, 0x0174, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0), - MX6_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x0544, 0x0174, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU1_CSI1_DATA12 = IOMUX_PAD(0x0544, 0x0174, 3, 0x0890, 1, 0), - MX6_PAD_EIM_D28__UART2_DTE_RTS_B = IOMUX_PAD(0x0544, 0x0174, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D28__UART2_DTE_CTS_B = IOMUX_PAD(0x0544, 0x0174, 4, 0x0900, 0, 0), - MX6_PAD_EIM_D28__GPIO3_IO28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x0544, 0x0174, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x0544, 0x0174, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D28__EPDC_PWR_CTRL3 = IOMUX_PAD(0x0544, 0x0174, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D29__EIM_DATA29 = IOMUX_PAD(0x0548, 0x0178, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x0548, 0x0178, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D29__ECSPI4_SS0 = IOMUX_PAD(0x0548, 0x0178, 2, 0x0808, 1, 0), - MX6_PAD_EIM_D29__UART2_CTS_B = IOMUX_PAD(0x0548, 0x0178, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D29__UART2_RTS_B = IOMUX_PAD(0x0548, 0x0178, 4, 0x0900, 1, 0), - MX6_PAD_EIM_D29__GPIO3_IO29 = IOMUX_PAD(0x0548, 0x0178, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D29__IPU1_CSI1_VSYNC = IOMUX_PAD(0x0548, 0x0178, 6, 0x08BC, 0, 0), - MX6_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x0548, 0x0178, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D29__EPDC_PWR_WAKE = IOMUX_PAD(0x0548, 0x0178, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D30__EIM_DATA30 = IOMUX_PAD(0x054C, 0x017C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 = IOMUX_PAD(0x054C, 0x017C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x054C, 0x017C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_CSI0_DATA03 = IOMUX_PAD(0x054C, 0x017C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D30__UART3_CTS_B = IOMUX_PAD(0x054C, 0x017C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D30__UART3_RTS_B = IOMUX_PAD(0x054C, 0x017C, 4, 0x0908, 1, 0), - MX6_PAD_EIM_D30__GPIO3_IO30 = IOMUX_PAD(0x054C, 0x017C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D30__USB_H1_OC = IOMUX_PAD(0x054C, 0x017C, 6, 0x0924, 0, 0), - MX6_PAD_EIM_D30__EPDC_SDOEZ = IOMUX_PAD(0x054C, 0x017C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D31__EIM_DATA31 = IOMUX_PAD(0x0550, 0x0180, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 = IOMUX_PAD(0x0550, 0x0180, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x0550, 0x0180, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_CSI0_DATA02 = IOMUX_PAD(0x0550, 0x0180, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_CTS_B = IOMUX_PAD(0x0550, 0x0180, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_RTS_B = IOMUX_PAD(0x0550, 0x0180, 4, 0x0908, 2, 0), - MX6_PAD_EIM_D31__GPIO3_IO31 = IOMUX_PAD(0x0550, 0x0180, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D31__USB_H1_PWR = IOMUX_PAD(0x0550, 0x0180, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D31__EPDC_SDCLK_P = IOMUX_PAD(0x0550, 0x0180, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D31__EIM_ACLK_FREERUN = IOMUX_PAD(0x0550, 0x0180, 9, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__EIM_AD00 = IOMUX_PAD(0x0554, 0x0184, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 = IOMUX_PAD(0x0554, 0x0184, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU1_CSI1_DATA09 = IOMUX_PAD(0x0554, 0x0184, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__GPIO3_IO00 = IOMUX_PAD(0x0554, 0x0184, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__SRC_BOOT_CFG00 = IOMUX_PAD(0x0554, 0x0184, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__EPDC_SDCLK_N = IOMUX_PAD(0x0554, 0x0184, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__EIM_AD01 = IOMUX_PAD(0x0558, 0x0188, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 = IOMUX_PAD(0x0558, 0x0188, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU1_CSI1_DATA08 = IOMUX_PAD(0x0558, 0x0188, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__GPIO3_IO01 = IOMUX_PAD(0x0558, 0x0188, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__SRC_BOOT_CFG01 = IOMUX_PAD(0x0558, 0x0188, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__EPDC_SDLE = IOMUX_PAD(0x0558, 0x0188, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__EIM_AD10 = IOMUX_PAD(0x055C, 0x018C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x055C, 0x018C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__IPU1_CSI1_DATA_EN = IOMUX_PAD(0x055C, 0x018C, 2, 0x08B0, 1, 0), - MX6_PAD_EIM_DA10__GPIO3_IO10 = IOMUX_PAD(0x055C, 0x018C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x055C, 0x018C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__EPDC_DATA01 = IOMUX_PAD(0x055C, 0x018C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__EIM_AD11 = IOMUX_PAD(0x0560, 0x0190, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 = IOMUX_PAD(0x0560, 0x0190, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__IPU1_CSI1_HSYNC = IOMUX_PAD(0x0560, 0x0190, 2, 0x08B4, 0, 0), - MX6_PAD_EIM_DA11__GPIO3_IO11 = IOMUX_PAD(0x0560, 0x0190, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0560, 0x0190, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__EPDC_DATA03 = IOMUX_PAD(0x0560, 0x0190, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__EIM_AD12 = IOMUX_PAD(0x0564, 0x0194, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 = IOMUX_PAD(0x0564, 0x0194, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__IPU1_CSI1_VSYNC = IOMUX_PAD(0x0564, 0x0194, 2, 0x08BC, 1, 0), - MX6_PAD_EIM_DA12__GPIO3_IO12 = IOMUX_PAD(0x0564, 0x0194, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0564, 0x0194, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__EPDC_DATA02 = IOMUX_PAD(0x0564, 0x0194, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__EIM_AD13 = IOMUX_PAD(0x0568, 0x0198, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x0568, 0x0198, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__GPIO3_IO13 = IOMUX_PAD(0x0568, 0x0198, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x0568, 0x0198, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__EPDC_DATA13 = IOMUX_PAD(0x0568, 0x0198, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__EIM_AD14 = IOMUX_PAD(0x056C, 0x019C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x056C, 0x019C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__GPIO3_IO14 = IOMUX_PAD(0x056C, 0x019C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x056C, 0x019C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__EPDC_DATA14 = IOMUX_PAD(0x056C, 0x019C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__EIM_AD15 = IOMUX_PAD(0x0570, 0x01A0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN01 = IOMUX_PAD(0x0570, 0x01A0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN04 = IOMUX_PAD(0x0570, 0x01A0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__GPIO3_IO15 = IOMUX_PAD(0x0570, 0x01A0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0570, 0x01A0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__EPDC_DATA09 = IOMUX_PAD(0x0570, 0x01A0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__EIM_AD02 = IOMUX_PAD(0x0574, 0x01A4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 = IOMUX_PAD(0x0574, 0x01A4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU1_CSI1_DATA07 = IOMUX_PAD(0x0574, 0x01A4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__GPIO3_IO02 = IOMUX_PAD(0x0574, 0x01A4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__SRC_BOOT_CFG02 = IOMUX_PAD(0x0574, 0x01A4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__EPDC_BDR0 = IOMUX_PAD(0x0574, 0x01A4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__EIM_AD03 = IOMUX_PAD(0x0578, 0x01A8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 = IOMUX_PAD(0x0578, 0x01A8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU1_CSI1_DATA06 = IOMUX_PAD(0x0578, 0x01A8, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__GPIO3_IO03 = IOMUX_PAD(0x0578, 0x01A8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__SRC_BOOT_CFG03 = IOMUX_PAD(0x0578, 0x01A8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__EPDC_BDR1 = IOMUX_PAD(0x0578, 0x01A8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__EIM_AD04 = IOMUX_PAD(0x057C, 0x01AC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 = IOMUX_PAD(0x057C, 0x01AC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU1_CSI1_DATA05 = IOMUX_PAD(0x057C, 0x01AC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__GPIO3_IO04 = IOMUX_PAD(0x057C, 0x01AC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__SRC_BOOT_CFG04 = IOMUX_PAD(0x057C, 0x01AC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__EPDC_SDCE0 = IOMUX_PAD(0x057C, 0x01AC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__EIM_AD05 = IOMUX_PAD(0x0580, 0x01B0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 = IOMUX_PAD(0x0580, 0x01B0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU1_CSI1_DATA04 = IOMUX_PAD(0x0580, 0x01B0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__GPIO3_IO05 = IOMUX_PAD(0x0580, 0x01B0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__SRC_BOOT_CFG05 = IOMUX_PAD(0x0580, 0x01B0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__EPDC_SDCE1 = IOMUX_PAD(0x0580, 0x01B0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__EIM_AD06 = IOMUX_PAD(0x0584, 0x01B4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 = IOMUX_PAD(0x0584, 0x01B4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU1_CSI1_DATA03 = IOMUX_PAD(0x0584, 0x01B4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__GPIO3_IO06 = IOMUX_PAD(0x0584, 0x01B4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__SRC_BOOT_CFG06 = IOMUX_PAD(0x0584, 0x01B4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__EPDC_SDCE2 = IOMUX_PAD(0x0584, 0x01B4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__EIM_AD07 = IOMUX_PAD(0x0588, 0x01B8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 = IOMUX_PAD(0x0588, 0x01B8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU1_CSI1_DATA02 = IOMUX_PAD(0x0588, 0x01B8, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__GPIO3_IO07 = IOMUX_PAD(0x0588, 0x01B8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__SRC_BOOT_CFG07 = IOMUX_PAD(0x0588, 0x01B8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__EPDC_SDCE3 = IOMUX_PAD(0x0588, 0x01B8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__EIM_AD08 = IOMUX_PAD(0x058C, 0x01BC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 = IOMUX_PAD(0x058C, 0x01BC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU1_CSI1_DATA01 = IOMUX_PAD(0x058C, 0x01BC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__GPIO3_IO08 = IOMUX_PAD(0x058C, 0x01BC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__SRC_BOOT_CFG08 = IOMUX_PAD(0x058C, 0x01BC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__EPDC_SDCE4 = IOMUX_PAD(0x058C, 0x01BC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__EIM_AD09 = IOMUX_PAD(0x0590, 0x01C0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 = IOMUX_PAD(0x0590, 0x01C0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU1_CSI1_DATA00 = IOMUX_PAD(0x0590, 0x01C0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__GPIO3_IO09 = IOMUX_PAD(0x0590, 0x01C0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__SRC_BOOT_CFG09 = IOMUX_PAD(0x0590, 0x01C0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__EPDC_SDCE5 = IOMUX_PAD(0x0590, 0x01C0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__EIM_EB0_B = IOMUX_PAD(0x0594, 0x01C4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 = IOMUX_PAD(0x0594, 0x01C4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU1_CSI1_DATA11 = IOMUX_PAD(0x0594, 0x01C4, 2, 0x088C, 1, 0), - MX6_PAD_EIM_EB0__CCM_PMIC_READY = IOMUX_PAD(0x0594, 0x01C4, 4, 0x07D4, 0, 0), - MX6_PAD_EIM_EB0__GPIO2_IO28 = IOMUX_PAD(0x0594, 0x01C4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__SRC_BOOT_CFG27 = IOMUX_PAD(0x0594, 0x01C4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__EPDC_PWR_COM = IOMUX_PAD(0x0594, 0x01C4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__EIM_EB1_B = IOMUX_PAD(0x0598, 0x01C8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 = IOMUX_PAD(0x0598, 0x01C8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU1_CSI1_DATA10 = IOMUX_PAD(0x0598, 0x01C8, 2, 0x0888, 1, 0), - MX6_PAD_EIM_EB1__GPIO2_IO29 = IOMUX_PAD(0x0598, 0x01C8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__SRC_BOOT_CFG28 = IOMUX_PAD(0x0598, 0x01C8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__EPDC_SDSHR = IOMUX_PAD(0x0598, 0x01C8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__EIM_EB2_B = IOMUX_PAD(0x059C, 0x01CC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x059C, 0x01CC, 1, 0x07E4, 2, 0), - MX6_PAD_EIM_EB2__IPU1_CSI1_DATA19 = IOMUX_PAD(0x059C, 0x01CC, 3, 0x08AC, 1, 0), - MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x059C, 0x01CC, 4, 0x0860, 0, 0), - MX6_PAD_EIM_EB2__GPIO2_IO30 = IOMUX_PAD(0x059C, 0x01CC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, 0), - MX6_PAD_EIM_EB2__SRC_BOOT_CFG30 = IOMUX_PAD(0x059C, 0x01CC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__EPDC_DATA05 = IOMUX_PAD(0x059C, 0x01CC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__EIM_EB3_B = IOMUX_PAD(0x05A0, 0x01D0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__ECSPI4_RDY = IOMUX_PAD(0x05A0, 0x01D0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_CTS_B = IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_RTS_B = IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0908, 3, 0), - MX6_PAD_EIM_EB3__UART1_RI_B = IOMUX_PAD(0x05A0, 0x01D0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__IPU1_CSI1_HSYNC = IOMUX_PAD(0x05A0, 0x01D0, 4, 0x08B4, 1, 0), - MX6_PAD_EIM_EB3__GPIO2_IO31 = IOMUX_PAD(0x05A0, 0x01D0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__IPU1_DI1_PIN03 = IOMUX_PAD(0x05A0, 0x01D0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__SRC_BOOT_CFG31 = IOMUX_PAD(0x05A0, 0x01D0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__EPDC_SDCE0 = IOMUX_PAD(0x05A0, 0x01D0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__EIM_ACLK_FREERUN = IOMUX_PAD(0x05A0, 0x01D0, 9, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__EIM_LBA_B = IOMUX_PAD(0x05A4, 0x01D4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x05A4, 0x01D4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x05A4, 0x01D4, 2, 0x0804, 1, 0), - MX6_PAD_EIM_LBA__GPIO2_IO27 = IOMUX_PAD(0x05A4, 0x01D4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__SRC_BOOT_CFG26 = IOMUX_PAD(0x05A4, 0x01D4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__EPDC_DATA04 = IOMUX_PAD(0x05A4, 0x01D4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_OE__EIM_OE_B = IOMUX_PAD(0x05A8, 0x01D8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_OE__IPU1_DI1_PIN07 = IOMUX_PAD(0x05A8, 0x01D8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x05A8, 0x01D8, 2, 0x07F8, 2, 0), - MX6_PAD_EIM_OE__GPIO2_IO25 = IOMUX_PAD(0x05A8, 0x01D8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_OE__EPDC_PWR_IRQ = IOMUX_PAD(0x05A8, 0x01D8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_RW__EIM_RW = IOMUX_PAD(0x05AC, 0x01DC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_RW__IPU1_DI1_PIN08 = IOMUX_PAD(0x05AC, 0x01DC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x05AC, 0x01DC, 2, 0x0800, 2, 0), - MX6_PAD_EIM_RW__GPIO2_IO26 = IOMUX_PAD(0x05AC, 0x01DC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_RW__SRC_BOOT_CFG29 = IOMUX_PAD(0x05AC, 0x01DC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_RW__EPDC_DATA07 = IOMUX_PAD(0x05AC, 0x01DC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__EIM_WAIT_B = IOMUX_PAD(0x05B0, 0x01E0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__EIM_DTACK_B = IOMUX_PAD(0x05B0, 0x01E0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__GPIO5_IO00 = IOMUX_PAD(0x05B0, 0x01E0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__SRC_BOOT_CFG25 = IOMUX_PAD(0x05B0, 0x01E0, 7, 0x0000, 0, 0), - MX6_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x05B4, 0x01E4, 1, 0x0828, 0, 0), - MX6_PAD_ENET_CRS_DV__ESAI_TX_CLK = IOMUX_PAD(0x05B4, 0x01E4, 2, 0x0840, 0, 0), - MX6_PAD_ENET_CRS_DV__SPDIF_EXT_CLK = IOMUX_PAD(0x05B4, 0x01E4, 3, 0x08F4, 0, 0), - MX6_PAD_ENET_CRS_DV__GPIO1_IO25 = IOMUX_PAD(0x05B4, 0x01E4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__MLB_DATA = IOMUX_PAD(0x05B8, 0x01E8, 0, 0x08E0, 0, 0), - MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__ESAI_TX5_RX0 = IOMUX_PAD(0x05B8, 0x01E8, 2, 0x0858, 0, 0), - MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x05B8, 0x01E8, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__GPIO1_IO31 = IOMUX_PAD(0x05B8, 0x01E8, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0), - MX6_PAD_ENET_MDIO__ESAI_RX_CLK = IOMUX_PAD(0x05BC, 0x01EC, 2, 0x083C, 0, 0), - MX6_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x05BC, 0x01EC, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__GPIO1_IO22 = IOMUX_PAD(0x05BC, 0x01EC, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__SPDIF_LOCK = IOMUX_PAD(0x05BC, 0x01EC, 6, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__ESAI_RX_FS = IOMUX_PAD(0x05C0, 0x01F0, 2, 0x082C, 0, 0), - MX6_PAD_ENET_REF_CLK__GPIO1_IO23 = IOMUX_PAD(0x05C0, 0x01F0, 5, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__SPDIF_SR_CLK = IOMUX_PAD(0x05C0, 0x01F0, 6, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__USB_OTG_ID = IOMUX_PAD(0x05C4, 0x01F4, 0, 0x0790, 0, 0), - MX6_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x05C4, 0x01F4, 1, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ESAI_RX_HF_CLK = IOMUX_PAD(0x05C4, 0x01F4, 2, 0x0834, 0, 0), - MX6_PAD_ENET_RX_ER__SPDIF_IN = IOMUX_PAD(0x05C4, 0x01F4, 3, 0x08F0, 1, 0), - MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT= IOMUX_PAD(0x05C4, 0x01F4, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__GPIO1_IO24 = IOMUX_PAD(0x05C4, 0x01F4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__ENET_RX_DATA0 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0818, 0, 0), - MX6_PAD_ENET_RXD0__ESAI_TX_HF_CLK = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x0838, 0, 0), - MX6_PAD_ENET_RXD0__SPDIF_OUT = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__GPIO1_IO27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__MLB_SIG = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x08E4, 0, 0), - MX6_PAD_ENET_RXD1__ENET_RX_DATA1 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x081C, 0, 0), - MX6_PAD_ENET_RXD1__ESAI_TX_FS = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x0830, 0, 0), - MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__GPIO1_IO26 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__ESAI_TX3_RX2 = IOMUX_PAD(0x05D0, 0x0200, 2, 0x0850, 0, 0), - MX6_PAD_ENET_TX_EN__GPIO1_IO28 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__I2C4_SCL = IOMUX_PAD(0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, 0), - MX6_PAD_ENET_TXD0__ENET_TX_DATA0 = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__ESAI_TX4_RX1 = IOMUX_PAD(0x05D4, 0x0204, 2, 0x0854, 0, 0), - MX6_PAD_ENET_TXD0__GPIO1_IO30 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__MLB_CLK = IOMUX_PAD(0x05D8, 0x0208, 0, 0x08DC, 0, 0), - MX6_PAD_ENET_TXD1__ENET_TX_DATA1 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__ESAI_TX2_RX3 = IOMUX_PAD(0x05D8, 0x0208, 2, 0x084C, 0, 0), - MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__GPIO1_IO29 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__I2C4_SDA = IOMUX_PAD(0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, 0), - MX6_PAD_GPIO_0__CCM_CLKO1 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0000, 0, 0), - MX6_PAD_GPIO_0__KEY_COL5 = IOMUX_PAD(0x05DC, 0x020C, 2, 0x08C0, 1, 0), - MX6_PAD_GPIO_0__ASRC_EXT_CLK = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0794, 0, 0), - MX6_PAD_GPIO_0__EPIT1_OUT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_0__GPIO1_IO00 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_0__USB_H1_PWR = IOMUX_PAD(0x05DC, 0x020C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_0__SNVS_VIO_5 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_1__ESAI_RX_CLK = IOMUX_PAD(0x05E0, 0x0210, 0, 0x083C, 1, 0), - MX6_PAD_GPIO_1__WDOG2_B = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_1__KEY_ROW5 = IOMUX_PAD(0x05E0, 0x0210, 2, 0x08CC, 1, 0), - MX6_PAD_GPIO_1__USB_OTG_ID = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0), - MX6_PAD_GPIO_1__PWM2_OUT = IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_1__GPIO1_IO01 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_1__SD1_CD_B = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ESAI_TX3_RX2 = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0850, 1, 0), - MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x05E4, 0x0214, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ENET_REF_CLK = IOMUX_PAD(0x05E4, 0x0214, 2, 0x080C, 0, 0), - MX6_PAD_GPIO_16__SD1_LCTL = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_16__SPDIF_IN = IOMUX_PAD(0x05E4, 0x0214, 4, 0x08F0, 2, 0), - MX6_PAD_GPIO_16__GPIO7_IO11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0), - MX6_PAD_GPIO_16__JTAG_DE_B = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_17__ESAI_TX0 = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0844, 0, 0), - MX6_PAD_GPIO_17__ENET_1588_EVENT3_IN = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_17__CCM_PMIC_READY = IOMUX_PAD(0x05E8, 0x0218, 2, 0x07D4, 1, 0), - MX6_PAD_GPIO_17__SDMA_EXT_EVENT0 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x08E8, 1, 0), - MX6_PAD_GPIO_17__SPDIF_OUT = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_17__GPIO7_IO12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_18__ESAI_TX1 = IOMUX_PAD(0x05EC, 0x021C, 0, 0x0848, 0, 0), - MX6_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0814, 0, 0), - MX6_PAD_GPIO_18__SD3_VSELECT = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SDMA_EXT_EVENT1 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x08EC, 1, 0), - MX6_PAD_GPIO_18__ASRC_EXT_CLK = IOMUX_PAD(0x05EC, 0x021C, 4, 0x0794, 1, 0), - MX6_PAD_GPIO_18__GPIO7_IO13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SNVS_VIO_5_CTL = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_19__KEY_COL5 = IOMUX_PAD(0x05F0, 0x0220, 0, 0x08C0, 2, 0), - MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x05F0, 0x0220, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_19__SPDIF_OUT = IOMUX_PAD(0x05F0, 0x0220, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_19__CCM_CLKO1 = IOMUX_PAD(0x05F0, 0x0220, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_19__GPIO4_IO05 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_2__ESAI_TX_FS = IOMUX_PAD(0x05F4, 0x0224, 0, 0x0830, 1, 0), - MX6_PAD_GPIO_2__KEY_ROW6 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08D0, 1, 0), - MX6_PAD_GPIO_2__GPIO1_IO02 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_2__SD2_WP = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_2__MLB_DATA = IOMUX_PAD(0x05F4, 0x0224, 7, 0x08E0, 1, 0), - MX6_PAD_GPIO_3__ESAI_RX_HF_CLK = IOMUX_PAD(0x05F8, 0x0228, 0, 0x0834, 1, 0), - MX6_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, 0), - MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_3__GPIO1_IO03 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_3__USB_H1_OC = IOMUX_PAD(0x05F8, 0x0228, 6, 0x0924, 1, 0), - MX6_PAD_GPIO_3__MLB_CLK = IOMUX_PAD(0x05F8, 0x0228, 7, 0x08DC, 1, 0), - MX6_PAD_GPIO_4__ESAI_TX_HF_CLK = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0838, 1, 0), - MX6_PAD_GPIO_4__KEY_COL7 = IOMUX_PAD(0x05FC, 0x022C, 2, 0x08C8, 1, 0), - MX6_PAD_GPIO_4__GPIO1_IO04 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_4__SD2_CD_B = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_5__ESAI_TX2_RX3 = IOMUX_PAD(0x0600, 0x0230, 0, 0x084C, 1, 0), - MX6_PAD_GPIO_5__KEY_ROW7 = IOMUX_PAD(0x0600, 0x0230, 2, 0x08D4, 1, 0), - MX6_PAD_GPIO_5__CCM_CLKO1 = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_5__GPIO1_IO05 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0), - MX6_PAD_GPIO_5__ARM_EVENTI = IOMUX_PAD(0x0600, 0x0230, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_6__ESAI_TX_CLK = IOMUX_PAD(0x0604, 0x0234, 0, 0x0840, 1, 0), - MX6_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0), - MX6_PAD_GPIO_6__GPIO1_IO06 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_6__SD2_LCTL = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_6__MLB_SIG = IOMUX_PAD(0x0604, 0x0234, 7, 0x08E4, 1, 0), - MX6_PAD_GPIO_7__ESAI_TX4_RX1 = IOMUX_PAD(0x0608, 0x0238, 0, 0x0854, 1, 0), - MX6_PAD_GPIO_7__EPIT1_OUT = IOMUX_PAD(0x0608, 0x0238, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_7__FLEXCAN1_TX = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_TX_DATA = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_RX_DATA = IOMUX_PAD(0x0608, 0x0238, 4, 0x0904, 2, 0), - MX6_PAD_GPIO_7__GPIO1_IO07 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_7__SPDIF_LOCK = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_7__USB_OTG_HOST_MODE = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_7__I2C4_SCL = IOMUX_PAD(0x0608, 0x0238, 8 | IOMUX_CONFIG_SION, 0x0880, 1, 0), - MX6_PAD_GPIO_8__ESAI_TX5_RX0 = IOMUX_PAD(0x060C, 0x023C, 0, 0x0858, 1, 0), - MX6_PAD_GPIO_8__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_8__EPIT2_OUT = IOMUX_PAD(0x060C, 0x023C, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_8__FLEXCAN1_RX = IOMUX_PAD(0x060C, 0x023C, 3, 0x07C8, 0, 0), - MX6_PAD_GPIO_8__UART2_TX_DATA = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_8__UART2_RX_DATA = IOMUX_PAD(0x060C, 0x023C, 4, 0x0904, 3, 0), - MX6_PAD_GPIO_8__GPIO1_IO08 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_8__SPDIF_SR_CLK = IOMUX_PAD(0x060C, 0x023C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_8__I2C4_SDA = IOMUX_PAD(0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, 0), - MX6_PAD_GPIO_9__ESAI_RX_FS = IOMUX_PAD(0x0610, 0x0240, 0, 0x082C, 1, 0), - MX6_PAD_GPIO_9__WDOG1_B = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_9__KEY_COL6 = IOMUX_PAD(0x0610, 0x0240, 2, 0x08C4, 1, 0), - MX6_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_9__PWM1_OUT = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_9__GPIO1_IO09 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_9__SD1_WP = IOMUX_PAD(0x0610, 0x0240, 6, 0x092C, 1, 0), - MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x062C, 0x0244, 0, 0x07D8, 3, 0), - MX6_PAD_KEY_COL0__ENET_RX_DATA3 = IOMUX_PAD(0x062C, 0x0244, 1, 0x0824, 0, 0), - MX6_PAD_KEY_COL0__AUD5_TXC = IOMUX_PAD(0x062C, 0x0244, 2, 0x07C0, 1, 0), - MX6_PAD_KEY_COL0__KEY_COL0 = IOMUX_PAD(0x062C, 0x0244, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_TX_DATA = IOMUX_PAD(0x062C, 0x0244, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_RX_DATA = IOMUX_PAD(0x062C, 0x0244, 4, 0x0914, 2, 0), - MX6_PAD_KEY_COL0__GPIO4_IO06 = IOMUX_PAD(0x062C, 0x0244, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__DCIC1_OUT = IOMUX_PAD(0x062C, 0x0244, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x0630, 0x0248, 0, 0x07DC, 3, 0), - MX6_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x0630, 0x0248, 1, 0x0810, 1, 0), - MX6_PAD_KEY_COL1__AUD5_TXFS = IOMUX_PAD(0x0630, 0x0248, 2, 0x07C4, 1, 0), - MX6_PAD_KEY_COL1__KEY_COL1 = IOMUX_PAD(0x0630, 0x0248, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_TX_DATA = IOMUX_PAD(0x0630, 0x0248, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_RX_DATA = IOMUX_PAD(0x0630, 0x0248, 4, 0x091C, 2, 0), - MX6_PAD_KEY_COL1__GPIO4_IO08 = IOMUX_PAD(0x0630, 0x0248, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__SD1_VSELECT = IOMUX_PAD(0x0630, 0x0248, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x0634, 0x024C, 0, 0x07E8, 2, 0), - MX6_PAD_KEY_COL2__ENET_RX_DATA2 = IOMUX_PAD(0x0634, 0x024C, 1, 0x0820, 0, 0), - MX6_PAD_KEY_COL2__FLEXCAN1_TX = IOMUX_PAD(0x0634, 0x024C, 2, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__KEY_COL2 = IOMUX_PAD(0x0634, 0x024C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x0634, 0x024C, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__GPIO4_IO10 = IOMUX_PAD(0x0634, 0x024C, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE = IOMUX_PAD(0x0634, 0x024C, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x0638, 0x0250, 0, 0x07F0, 1, 0), - MX6_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x0638, 0x0250, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x0638, 0x0250, 2, 0x0860, 1, 0), - MX6_PAD_KEY_COL3__KEY_COL3 = IOMUX_PAD(0x0638, 0x0250, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0), - MX6_PAD_KEY_COL3__GPIO4_IO12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__SPDIF_IN = IOMUX_PAD(0x0638, 0x0250, 6, 0x08F0, 3, 0), - MX6_PAD_KEY_COL4__FLEXCAN2_TX = IOMUX_PAD(0x063C, 0x0254, 0, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__IPU1_SISG4 = IOMUX_PAD(0x063C, 0x0254, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__USB_OTG_OC = IOMUX_PAD(0x063C, 0x0254, 2, 0x0920, 1, 0), - MX6_PAD_KEY_COL4__KEY_COL4 = IOMUX_PAD(0x063C, 0x0254, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_CTS_B = IOMUX_PAD(0x063C, 0x0254, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_RTS_B = IOMUX_PAD(0x063C, 0x0254, 4, 0x0918, 2, 0), - MX6_PAD_KEY_COL4__GPIO4_IO14 = IOMUX_PAD(0x063C, 0x0254, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x0640, 0x0258, 0, 0x07E0, 3, 0), - MX6_PAD_KEY_ROW0__ENET_TX_DATA3 = IOMUX_PAD(0x0640, 0x0258, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__AUD5_TXD = IOMUX_PAD(0x0640, 0x0258, 2, 0x07B4, 1, 0), - MX6_PAD_KEY_ROW0__KEY_ROW0 = IOMUX_PAD(0x0640, 0x0258, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__UART4_TX_DATA = IOMUX_PAD(0x0640, 0x0258, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__UART4_RX_DATA = IOMUX_PAD(0x0640, 0x0258, 4, 0x0914, 3, 0), - MX6_PAD_KEY_ROW0__GPIO4_IO07 = IOMUX_PAD(0x0640, 0x0258, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__DCIC2_OUT = IOMUX_PAD(0x0640, 0x0258, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x025C, 0, 0x07E4, 3, 0), - MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x0644, 0x025C, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__AUD5_RXD = IOMUX_PAD(0x0644, 0x025C, 2, 0x07B0, 1, 0), - MX6_PAD_KEY_ROW1__KEY_ROW1 = IOMUX_PAD(0x0644, 0x025C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__UART5_TX_DATA = IOMUX_PAD(0x0644, 0x025C, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__UART5_RX_DATA = IOMUX_PAD(0x0644, 0x025C, 4, 0x091C, 3, 0), - MX6_PAD_KEY_ROW1__GPIO4_IO09 = IOMUX_PAD(0x0644, 0x025C, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__SD2_VSELECT = IOMUX_PAD(0x0644, 0x025C, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x0648, 0x0260, 0, 0x07EC, 1, 0), - MX6_PAD_KEY_ROW2__ENET_TX_DATA2 = IOMUX_PAD(0x0648, 0x0260, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__FLEXCAN1_RX = IOMUX_PAD(0x0648, 0x0260, 2, 0x07C8, 1, 0), - MX6_PAD_KEY_ROW2__KEY_ROW2 = IOMUX_PAD(0x0648, 0x0260, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__SD2_VSELECT = IOMUX_PAD(0x0648, 0x0260, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__GPIO4_IO11 = IOMUX_PAD(0x0648, 0x0260, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x0648, 0x0260, 6, 0x085C, 1, 0), - MX6_PAD_KEY_ROW3__ASRC_EXT_CLK = IOMUX_PAD(0x064C, 0x0264, 1, 0x0794, 2, 0), - MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x064C, 0x0264, 2, 0x0864, 1, 0), - MX6_PAD_KEY_ROW3__KEY_ROW3 = IOMUX_PAD(0x064C, 0x0264, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0), - MX6_PAD_KEY_ROW3__GPIO4_IO13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__SD1_VSELECT = IOMUX_PAD(0x064C, 0x0264, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__FLEXCAN2_RX = IOMUX_PAD(0x0650, 0x0268, 0, 0x07CC, 0, 0), - MX6_PAD_KEY_ROW4__IPU1_SISG5 = IOMUX_PAD(0x0650, 0x0268, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__USB_OTG_PWR = IOMUX_PAD(0x0650, 0x0268, 2, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__KEY_ROW4 = IOMUX_PAD(0x0650, 0x0268, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__UART5_CTS_B = IOMUX_PAD(0x0650, 0x0268, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__UART5_RTS_B = IOMUX_PAD(0x0650, 0x0268, 4, 0x0918, 3, 0), - MX6_PAD_KEY_ROW4__GPIO4_IO15 = IOMUX_PAD(0x0650, 0x0268, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__NAND_ALE = IOMUX_PAD(0x0654, 0x026C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__SD4_RESET = IOMUX_PAD(0x0654, 0x026C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__GPIO6_IO08 = IOMUX_PAD(0x0654, 0x026C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__NAND_CLE = IOMUX_PAD(0x0658, 0x0270, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__GPIO6_IO07 = IOMUX_PAD(0x0658, 0x0270, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__NAND_CE0_B = IOMUX_PAD(0x065C, 0x0274, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__GPIO6_IO11 = IOMUX_PAD(0x065C, 0x0274, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__NAND_CE1_B = IOMUX_PAD(0x0660, 0x0278, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__SD4_VSELECT = IOMUX_PAD(0x0660, 0x0278, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__SD3_VSELECT = IOMUX_PAD(0x0660, 0x0278, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__GPIO6_IO14 = IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__NAND_CE2_B = IOMUX_PAD(0x0664, 0x027C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__IPU1_SISG0 = IOMUX_PAD(0x0664, 0x027C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__ESAI_TX0 = IOMUX_PAD(0x0664, 0x027C, 2, 0x0844, 1, 0), - MX6_PAD_NANDF_CS2__EIM_CRE = IOMUX_PAD(0x0664, 0x027C, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x0664, 0x027C, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__GPIO6_IO15 = IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__NAND_CE3_B = IOMUX_PAD(0x0668, 0x0280, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__IPU1_SISG1 = IOMUX_PAD(0x0668, 0x0280, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__ESAI_TX1 = IOMUX_PAD(0x0668, 0x0280, 2, 0x0848, 1, 0), - MX6_PAD_NANDF_CS3__EIM_ADDR26 = IOMUX_PAD(0x0668, 0x0280, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__GPIO6_IO16 = IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__I2C4_SDA = IOMUX_PAD(0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, 0), - MX6_PAD_NANDF_D0__NAND_DATA00 = IOMUX_PAD(0x066C, 0x0284, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__SD1_DATA4 = IOMUX_PAD(0x066C, 0x0284, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__GPIO2_IO00 = IOMUX_PAD(0x066C, 0x0284, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__NAND_DATA01 = IOMUX_PAD(0x0670, 0x0288, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__SD1_DATA5 = IOMUX_PAD(0x0670, 0x0288, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__GPIO2_IO01 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__NAND_DATA02 = IOMUX_PAD(0x0674, 0x028C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__SD1_DATA6 = IOMUX_PAD(0x0674, 0x028C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__GPIO2_IO02 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__NAND_DATA03 = IOMUX_PAD(0x0678, 0x0290, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__SD1_DATA7 = IOMUX_PAD(0x0678, 0x0290, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__GPIO2_IO03 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__NAND_DATA04 = IOMUX_PAD(0x067C, 0x0294, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__SD2_DATA4 = IOMUX_PAD(0x067C, 0x0294, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__GPIO2_IO04 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__NAND_DATA05 = IOMUX_PAD(0x0680, 0x0298, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__SD2_DATA5 = IOMUX_PAD(0x0680, 0x0298, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__GPIO2_IO05 = IOMUX_PAD(0x0680, 0x0298, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__NAND_DATA06 = IOMUX_PAD(0x0684, 0x029C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__SD2_DATA6 = IOMUX_PAD(0x0684, 0x029C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__GPIO2_IO06 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__NAND_DATA07 = IOMUX_PAD(0x0688, 0x02A0, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__SD2_DATA7 = IOMUX_PAD(0x0688, 0x02A0, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__GPIO2_IO07 = IOMUX_PAD(0x0688, 0x02A0, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__NAND_READY_B = IOMUX_PAD(0x068C, 0x02A4, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__GPIO6_IO10 = IOMUX_PAD(0x068C, 0x02A4, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__NAND_WP_B = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__GPIO6_IO09 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__I2C4_SCL = IOMUX_PAD(0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0), - MX6_PAD_RGMII_RD0__HSI_RX_READY = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0), - MX6_PAD_RGMII_RD0__GPIO6_IO25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__HSI_TX_FLAG = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0), - MX6_PAD_RGMII_RD1__GPIO6_IO27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__HSI_TX_DATA = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0), - MX6_PAD_RGMII_RD2__GPIO6_IO28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__HSI_TX_WAKE = IOMUX_PAD(0x06A0, 0x02B8, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0), - MX6_PAD_RGMII_RD3__GPIO6_IO29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__USB_H3_DATA = IOMUX_PAD(0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0), - MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE = IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__USB_H3_STROBE = IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP), - MX6_PAD_RGMII_RXC__RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0), - MX6_PAD_RGMII_RXC__GPIO6_IO30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__HSI_TX_READY = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__GPIO6_IO20 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__HSI_RX_FLAG = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__GPIO6_IO21 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__HSI_RX_DATA = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__GPIO6_IO22 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__HSI_RX_WAKE = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__GPIO6_IO23 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__USB_H2_STROBE = IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__GPIO6_IO26 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__ENET_REF_CLK = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x080C, 1, 0), - MX6_PAD_RGMII_TXC__USB_H2_DATA = IOMUX_PAD(0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__SPDIF_EXT_CLK = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x08F4, 1, 0), - MX6_PAD_RGMII_TXC__GPIO6_IO19 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, 0), - MX6_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__GPIO1_IO20 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__PWM4_OUT = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPT_COMPARE1 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPIO1_IO18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__SD1_DATA0 = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__GPT_CAPTURE1 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__GPIO1_IO16 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__SD1_DATA1 = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__PWM3_OUT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPT_CAPTURE2 = IOMUX_PAD(0x06D0, 0x02E8, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPIO1_IO17 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__SD1_DATA2 = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__GPT_COMPARE2 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__PWM2_OUT = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_B = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__GPIO1_IO19 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_RESET_B_DEB = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__SD1_DATA3 = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPT_COMPARE3 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__PWM1_OUT = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_B = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPIO1_IO21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_RESET_B_DEB = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x06DC, 0x02F4, 0, 0x0930, 1, 0), - MX6_PAD_SD2_CLK__KEY_COL5 = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x08C0, 3, 0), - MX6_PAD_SD2_CLK__AUD4_RXFS = IOMUX_PAD(0x06DC, 0x02F4, 3, 0x07A4, 1, 0), - MX6_PAD_SD2_CLK__GPIO1_IO10 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__KEY_ROW5 = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x08CC, 2, 0), - MX6_PAD_SD2_CMD__AUD4_RXC = IOMUX_PAD(0x06E0, 0x02F8, 3, 0x07A0, 1, 0), - MX6_PAD_SD2_CMD__GPIO1_IO11 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__SD2_DATA0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__AUD4_RXD = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0798, 1, 0), - MX6_PAD_SD2_DAT0__KEY_ROW7 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x08D4, 2, 0), - MX6_PAD_SD2_DAT0__GPIO1_IO15 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__DCIC2_OUT = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__SD2_DATA1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__EIM_CS2_B = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__AUD4_TXFS = IOMUX_PAD(0x06E8, 0x0300, 3, 0x07AC, 1, 0), - MX6_PAD_SD2_DAT1__KEY_COL7 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x08C8, 2, 0), - MX6_PAD_SD2_DAT1__GPIO1_IO14 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__SD2_DATA2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__EIM_CS3_B = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__AUD4_TXD = IOMUX_PAD(0x06EC, 0x0304, 3, 0x079C, 1, 0), - MX6_PAD_SD2_DAT2__KEY_ROW6 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x08D0, 2, 0), - MX6_PAD_SD2_DAT2__GPIO1_IO13 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__SD2_DATA3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__KEY_COL6 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x08C4, 2, 0), - MX6_PAD_SD2_DAT3__AUD4_TXC = IOMUX_PAD(0x06F0, 0x0308, 3, 0x07A8, 1, 0), - MX6_PAD_SD2_DAT3__GPIO1_IO12 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0), - MX6_PAD_SD3_CLK__UART2_CTS_B = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__UART2_RTS_B = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0900, 2, 0), - MX6_PAD_SD3_CLK__FLEXCAN1_RX = IOMUX_PAD(0x06F4, 0x030C, 2, 0x07C8, 2, 0), - MX6_PAD_SD3_CLK__GPIO7_IO03 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__UART2_CTS_B = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__UART2_RTS_B = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0900, 3, 0), - MX6_PAD_SD3_CMD__FLEXCAN1_TX = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__GPIO7_IO02 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__SD3_DATA0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__UART1_CTS_B = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__UART1_RTS_B = IOMUX_PAD(0x06FC, 0x0314, 1, 0x08F8, 2, 0), - MX6_PAD_SD3_DAT0__FLEXCAN2_TX = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__GPIO7_IO04 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__SD3_DATA1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_CTS_B = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_RTS_B = IOMUX_PAD(0x0700, 0x0318, 1, 0x08F8, 3, 0), - MX6_PAD_SD3_DAT1__FLEXCAN2_RX = IOMUX_PAD(0x0700, 0x0318, 2, 0x07CC, 1, 0), - MX6_PAD_SD3_DAT1__GPIO7_IO05 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__SD3_DATA2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__GPIO7_IO06 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__SD3_DATA3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__UART3_CTS_B = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__UART3_RTS_B = IOMUX_PAD(0x0708, 0x0320, 1, 0x0908, 4, 0), - MX6_PAD_SD3_DAT3__GPIO7_IO07 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__SD3_DATA4 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__UART2_TX_DATA = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__UART2_RX_DATA = IOMUX_PAD(0x070C, 0x0324, 1, 0x0904, 4, 0), - MX6_PAD_SD3_DAT4__GPIO7_IO01 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__SD3_DATA5 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_TX_DATA = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_RX_DATA = IOMUX_PAD(0x0710, 0x0328, 1, 0x0904, 5, 0), - MX6_PAD_SD3_DAT5__GPIO7_IO00 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__SD3_DATA6 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__UART1_TX_DATA = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__UART1_RX_DATA = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0), - MX6_PAD_SD3_DAT6__GPIO6_IO18 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__SD3_DATA7 = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_TX_DATA = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_RX_DATA = IOMUX_PAD(0x0718, 0x0330, 1, 0x08FC, 3, 0), - MX6_PAD_SD3_DAT7__GPIO6_IO17 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0), - MX6_PAD_SD3_RST__SD3_RESET = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_CTS_B = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_RTS_B = IOMUX_PAD(0x071C, 0x0334, 1, 0x0908, 5, 0), - MX6_PAD_SD3_RST__GPIO7_IO08 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__SD4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0), - MX6_PAD_SD4_CLK__NAND_WE_B = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__UART3_TX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__UART3_RX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x090C, 2, 0), - MX6_PAD_SD4_CLK__GPIO7_IO10 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__SD4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__NAND_RE_B = IOMUX_PAD(0x0724, 0x033C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_TX_DATA = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_RX_DATA = IOMUX_PAD(0x0724, 0x033C, 2, 0x090C, 3, 0), - MX6_PAD_SD4_CMD__GPIO7_IO09 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__SD4_DATA0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__NAND_DQS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__GPIO2_IO08 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__SD4_DATA1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__PWM3_OUT = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__GPIO2_IO09 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__SD4_DATA2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__PWM4_OUT = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__GPIO2_IO10 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__SD4_DATA3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__GPIO2_IO11 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__SD4_DATA4 = IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__UART2_TX_DATA = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__UART2_RX_DATA = IOMUX_PAD(0x0738, 0x0350, 2, 0x0904, 6, 0), - MX6_PAD_SD4_DAT4__GPIO2_IO12 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__SD4_DATA5 = IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_CTS_B = IOMUX_PAD(0x073C, 0x0354, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_RTS_B = IOMUX_PAD(0x073C, 0x0354, 2, 0x0900, 4, 0), - MX6_PAD_SD4_DAT5__GPIO2_IO13 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__SD4_DATA6 = IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__UART2_CTS_B = IOMUX_PAD(0x0740, 0x0358, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__UART2_RTS_B = IOMUX_PAD(0x0740, 0x0358, 2, 0x0900, 5, 0), - MX6_PAD_SD4_DAT6__GPIO2_IO14 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__SD4_DATA7 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_TX_DATA = IOMUX_PAD(0x0744, 0x035C, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_RX_DATA = IOMUX_PAD(0x0744, 0x035C, 2, 0x0904, 7, 0), - MX6_PAD_SD4_DAT7__GPIO2_IO15 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), -}; #endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h index f01f2e0e05b..ad31c3391ad 100644 --- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h @@ -9,1032 +9,1028 @@ #ifndef __ASM_ARCH_MX6_MX6Q_PINS_H__ #define __ASM_ARCH_MX6_MX6Q_PINS_H__ -#include - -enum { - MX6_PAD_SD2_DAT1__SD2_DATA1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0), - MX6_PAD_SD2_DAT1__EIM_CS2_B = IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__AUD4_TXFS = IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0), - MX6_PAD_SD2_DAT1__KEY_COL7 = IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0), - MX6_PAD_SD2_DAT1__GPIO1_IO14 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__SD2_DATA2 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0), - MX6_PAD_SD2_DAT2__EIM_CS3_B = IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__AUD4_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0), - MX6_PAD_SD2_DAT2__KEY_ROW6 = IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0), - MX6_PAD_SD2_DAT2__GPIO1_IO13 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__SD2_DATA0 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0), - MX6_PAD_SD2_DAT0__AUD4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0), - MX6_PAD_SD2_DAT0__KEY_ROW7 = IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0), - MX6_PAD_SD2_DAT0__GPIO1_IO15 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__DCIC2_OUT = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__USB_H2_DATA = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__RGMII_TXC = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__SPDIF_EXT_CLK = IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0), - MX6_PAD_RGMII_TXC__GPIO6_IO19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__HSI_TX_READY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__GPIO6_IO20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__HSI_RX_FLAG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__GPIO6_IO21 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__HSI_RX_DATA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__GPIO6_IO22 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__HSI_RX_WAKE = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__GPIO6_IO23 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__USB_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0), - MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__HSI_RX_READY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0), - MX6_PAD_RGMII_RD0__GPIO6_IO25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__USB_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__GPIO6_IO26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__ENET_REF_CLK = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0), - MX6_PAD_RGMII_RD1__HSI_TX_FLAG = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0), - MX6_PAD_RGMII_RD1__GPIO6_IO27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__HSI_TX_DATA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0), - MX6_PAD_RGMII_RD2__GPIO6_IO28 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__HSI_TX_WAKE = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0), - MX6_PAD_RGMII_RD3__GPIO6_IO29 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__USB_H3_STROBE = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__RGMII_RXC = IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0), - MX6_PAD_RGMII_RXC__GPIO6_IO30 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A25__EIM_ADDR25 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0), - MX6_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A25__GPIO5_IO02 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0), - MX6_PAD_EIM_EB2__EIM_EB2_B = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0), - MX6_PAD_EIM_EB2__IPU2_CSI1_DATA19 = IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0), - MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0), - MX6_PAD_EIM_EB2__GPIO2_IO30 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x03A0, 0x008C, 22, 0x08A0, 0, 0), - MX6_PAD_EIM_EB2__SRC_BOOT_CFG30 = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D16__EIM_DATA16 = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0), - MX6_PAD_EIM_D16__IPU1_DI0_PIN05 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D16__IPU2_CSI1_DATA18 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0), - MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0), - MX6_PAD_EIM_D16__GPIO3_IO16 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0090, 22, 0x08A4, 0, 0), - MX6_PAD_EIM_D17__EIM_DATA17 = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0), - MX6_PAD_EIM_D17__IPU1_DI0_PIN06 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D17__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0), - MX6_PAD_EIM_D17__DCIC1_OUT = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D17__GPIO3_IO17 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x03A8, 0x0094, 22, 0x08A8, 0, 0), - MX6_PAD_EIM_D18__EIM_DATA18 = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0), - MX6_PAD_EIM_D18__IPU1_DI0_PIN07 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D18__IPU2_CSI1_DATA17 = IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0), - MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D18__GPIO3_IO18 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x03AC, 0x0098, 22, 0x08AC, 0, 0), - MX6_PAD_EIM_D19__EIM_DATA19 = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0), - MX6_PAD_EIM_D19__IPU1_DI0_PIN08 = IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D19__IPU2_CSI1_DATA16 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0), - MX6_PAD_EIM_D19__UART1_CTS_B = IOMUX_PAD(0x03B0, 0x009C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D19__UART1_RTS_B = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0), - MX6_PAD_EIM_D19__GPIO3_IO19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D19__EPIT1_OUT = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D20__EIM_DATA20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0), - MX6_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D20__IPU2_CSI1_DATA15 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0), - MX6_PAD_EIM_D20__UART1_CTS_B = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D20__UART1_RTS_B = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0), - MX6_PAD_EIM_D20__GPIO3_IO20 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D20__EPIT2_OUT = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D21__EIM_DATA21 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D21__IPU2_CSI1_DATA11 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0), - MX6_PAD_EIM_D21__USB_OTG_OC = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0), - MX6_PAD_EIM_D21__GPIO3_IO21 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x03B8, 0x00A4, 22, 0x0898, 0, 0), - MX6_PAD_EIM_D21__SPDIF_IN = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0), - MX6_PAD_EIM_D22__EIM_DATA22 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU1_DI0_PIN01 = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU2_CSI1_DATA10 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0), - MX6_PAD_EIM_D22__USB_OTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D22__GPIO3_IO22 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D22__SPDIF_OUT = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D23__EIM_DATA23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D23__UART3_CTS_B = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D23__UART3_RTS_B = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0), - MX6_PAD_EIM_D23__UART1_DCD_B = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0), - MX6_PAD_EIM_D23__GPIO3_IO23 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI1_PIN02 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__EIM_EB3_B = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__ECSPI4_RDY = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_CTS_B = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_RTS_B = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0), - MX6_PAD_EIM_EB3__UART1_RI_B = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__IPU2_CSI1_HSYNC = IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0), - MX6_PAD_EIM_EB3__GPIO2_IO31 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__IPU1_DI1_PIN03 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__SRC_BOOT_CFG31 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D24__EIM_DATA24 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_TX_DATA = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_RX_DATA = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0), - MX6_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0), - MX6_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D24__GPIO3_IO24 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D24__AUD5_RXFS = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0), - MX6_PAD_EIM_D24__UART1_DTR_B = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D25__EIM_DATA25 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D25__UART3_TX_DATA = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D25__UART3_RX_DATA = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0), - MX6_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0), - MX6_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D25__GPIO3_IO25 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D25__AUD5_RXC = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0), - MX6_PAD_EIM_D25__UART1_DSR_B = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D26__EIM_DATA26 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_CSI0_DATA01 = IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU2_CSI1_DATA14 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0), - MX6_PAD_EIM_D26__UART2_TX_DATA = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D26__UART2_RX_DATA = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0), - MX6_PAD_EIM_D26__GPIO3_IO26 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_SISG2 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D27__EIM_DATA27 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_CSI0_DATA00 = IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU2_CSI1_DATA13 = IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0), - MX6_PAD_EIM_D27__UART2_TX_DATA = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D27__UART2_RX_DATA = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0), - MX6_PAD_EIM_D27__GPIO3_IO27 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_SISG3 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D28__EIM_DATA28 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x03D8, 0x00C4, 17, 0x089C, 0, 0), - MX6_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU2_CSI1_DATA12 = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0), - MX6_PAD_EIM_D28__UART2_DTE_CTS_B = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0), - MX6_PAD_EIM_D28__UART2_DTE_RTS_B = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D28__GPIO3_IO28 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D29__EIM_DATA29 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D29__ECSPI4_SS0 = IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0), - MX6_PAD_EIM_D29__UART2_CTS_B = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D29__UART2_RTS_B = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0), - MX6_PAD_EIM_D29__GPIO3_IO29 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D29__IPU2_CSI1_VSYNC = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0), - MX6_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D30__EIM_DATA30 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_CSI0_DATA03 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D30__UART3_CTS_B = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D30__UART3_RTS_B = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0), - MX6_PAD_EIM_D30__GPIO3_IO30 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D30__USB_H1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0), - MX6_PAD_EIM_D31__EIM_DATA31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_CSI0_DATA02 = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_CTS_B = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_RTS_B = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0), - MX6_PAD_EIM_D31__GPIO3_IO31 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D31__USB_H1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A24__EIM_ADDR24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU2_CSI1_DATA19 = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0), - MX6_PAD_EIM_A24__IPU2_SISG2 = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_SISG2 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A24__GPIO5_IO04 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A24__SRC_BOOT_CFG24 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A23__EIM_ADDR23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU2_CSI1_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0), - MX6_PAD_EIM_A23__IPU2_SISG3 = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_SISG3 = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A23__GPIO6_IO06 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A23__SRC_BOOT_CFG23 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A22__EIM_ADDR22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU2_CSI1_DATA17 = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0), - MX6_PAD_EIM_A22__GPIO2_IO16 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A22__SRC_BOOT_CFG22 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A21__EIM_ADDR21 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU2_CSI1_DATA16 = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0), - MX6_PAD_EIM_A21__GPIO2_IO17 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A21__SRC_BOOT_CFG21 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A20__EIM_ADDR20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU2_CSI1_DATA15 = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0), - MX6_PAD_EIM_A20__GPIO2_IO18 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A20__SRC_BOOT_CFG20 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A19__EIM_ADDR19 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU2_CSI1_DATA14 = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0), - MX6_PAD_EIM_A19__GPIO2_IO19 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A19__SRC_BOOT_CFG19 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A18__EIM_ADDR18 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU2_CSI1_DATA13 = IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0), - MX6_PAD_EIM_A18__GPIO2_IO20 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A18__SRC_BOOT_CFG18 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A17__EIM_ADDR17 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU2_CSI1_DATA12 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0), - MX6_PAD_EIM_A17__GPIO2_IO21 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A17__SRC_BOOT_CFG17 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A16__EIM_ADDR16 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A16__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0), - MX6_PAD_EIM_A16__GPIO2_IO22 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A16__SRC_BOOT_CFG16 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__EIM_CS0_B = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__IPU1_DI1_PIN05 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0), - MX6_PAD_EIM_CS0__GPIO2_IO23 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__EIM_CS1_B = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__IPU1_DI1_PIN06 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0), - MX6_PAD_EIM_CS1__GPIO2_IO24 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_OE__EIM_OE_B = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0), - MX6_PAD_EIM_OE__IPU1_DI1_PIN07 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), - MX6_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0), - MX6_PAD_EIM_OE__GPIO2_IO25 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), - MX6_PAD_EIM_RW__EIM_RW = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0), - MX6_PAD_EIM_RW__IPU1_DI1_PIN08 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), - MX6_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0), - MX6_PAD_EIM_RW__GPIO2_IO26 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), - MX6_PAD_EIM_RW__SRC_BOOT_CFG29 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__EIM_LBA_B = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0), - MX6_PAD_EIM_LBA__GPIO2_IO27 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__SRC_BOOT_CFG26 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__EIM_EB0_B = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU2_CSI1_DATA11 = IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0), - MX6_PAD_EIM_EB0__CCM_PMIC_READY = IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0), - MX6_PAD_EIM_EB0__GPIO2_IO28 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__SRC_BOOT_CFG27 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__EIM_EB1_B = IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 = IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU2_CSI1_DATA10 = IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0), - MX6_PAD_EIM_EB1__GPIO2_IO29 = IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__SRC_BOOT_CFG28 = IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__EIM_AD00 = IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 = IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU2_CSI1_DATA09 = IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__GPIO3_IO00 = IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__SRC_BOOT_CFG00 = IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__EIM_AD01 = IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 = IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU2_CSI1_DATA08 = IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__GPIO3_IO01 = IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__SRC_BOOT_CFG01 = IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__EIM_AD02 = IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 = IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU2_CSI1_DATA07 = IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__GPIO3_IO02 = IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__SRC_BOOT_CFG02 = IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__EIM_AD03 = IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 = IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU2_CSI1_DATA06 = IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__GPIO3_IO03 = IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__SRC_BOOT_CFG03 = IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__EIM_AD04 = IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 = IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU2_CSI1_DATA05 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__GPIO3_IO04 = IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__SRC_BOOT_CFG04 = IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__EIM_AD05 = IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 = IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU2_CSI1_DATA04 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__GPIO3_IO05 = IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__SRC_BOOT_CFG05 = IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__EIM_AD06 = IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 = IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU2_CSI1_DATA03 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__GPIO3_IO06 = IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__SRC_BOOT_CFG06 = IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__EIM_AD07 = IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 = IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU2_CSI1_DATA02 = IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__GPIO3_IO07 = IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__SRC_BOOT_CFG07 = IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__EIM_AD08 = IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 = IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU2_CSI1_DATA01 = IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__GPIO3_IO08 = IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__SRC_BOOT_CFG08 = IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__EIM_AD09 = IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 = IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU2_CSI1_DATA00 = IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__GPIO3_IO09 = IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__SRC_BOOT_CFG09 = IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__EIM_AD10 = IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0), - MX6_PAD_EIM_DA10__GPIO3_IO10 = IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__EIM_AD11 = IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 = IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__IPU2_CSI1_HSYNC = IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0), - MX6_PAD_EIM_DA11__GPIO3_IO11 = IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__EIM_AD12 = IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 = IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__IPU2_CSI1_VSYNC = IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0), - MX6_PAD_EIM_DA12__GPIO3_IO12 = IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__EIM_AD13 = IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__GPIO3_IO13 = IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__EIM_AD14 = IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__GPIO3_IO14 = IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__EIM_AD15 = IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN01 = IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN04 = IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__GPIO3_IO15 = IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__EIM_WAIT_B = IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__EIM_DTACK_B = IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__GPIO5_IO00 = IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__SRC_BOOT_CFG25 = IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__EIM_BCLK = IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__GPIO6_IO31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__GPIO4_IO16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__GPIO4_IO17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN2__IPU2_DI0_PIN02 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__GPIO4_IO18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN3__IPU2_DI0_PIN03 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__GPIO4_IO19 = IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 = IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU2_DI0_PIN04 = IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__SD1_WP = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0), - MX6_PAD_DI0_PIN4__GPIO4_IO20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__GPIO4_IO21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__GPIO4_IO22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__GPIO4_IO23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__GPIO4_IO24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__GPIO4_IO25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__GPIO4_IO26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__GPIO4_IO27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__GPIO4_IO28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__PWM1_OUT = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__WDOG1_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__GPIO4_IO29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__PWM2_OUT = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__WDOG2_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__GPIO4_IO30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__GPIO4_IO31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__GPIO5_IO05 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__GPIO5_IO06 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0), - MX6_PAD_DISP0_DAT13__GPIO5_IO07 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0), - MX6_PAD_DISP0_DAT14__GPIO5_IO08 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0), - MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0), - MX6_PAD_DISP0_DAT15__GPIO5_IO09 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0), - MX6_PAD_DISP0_DAT16__AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0), - MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0), - MX6_PAD_DISP0_DAT16__GPIO5_IO10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0), - MX6_PAD_DISP0_DAT17__AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0), - MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0), - MX6_PAD_DISP0_DAT17__GPIO5_IO11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0), - MX6_PAD_DISP0_DAT18__AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0), - MX6_PAD_DISP0_DAT18__AUD4_RXFS = IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0), - MX6_PAD_DISP0_DAT18__GPIO5_IO12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__EIM_CS2_B = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0), - MX6_PAD_DISP0_DAT19__AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0), - MX6_PAD_DISP0_DAT19__AUD4_RXC = IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0), - MX6_PAD_DISP0_DAT19__GPIO5_IO13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__EIM_CS3_B = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0), - MX6_PAD_DISP0_DAT20__AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0), - MX6_PAD_DISP0_DAT20__GPIO5_IO14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0), - MX6_PAD_DISP0_DAT21__AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0), - MX6_PAD_DISP0_DAT21__GPIO5_IO15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0), - MX6_PAD_DISP0_DAT22__AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0), - MX6_PAD_DISP0_DAT22__GPIO5_IO16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0), - MX6_PAD_DISP0_DAT23__AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0), - MX6_PAD_DISP0_DAT23__GPIO5_IO17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0), - MX6_PAD_ENET_MDIO__ESAI_RX_CLK = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0), - MX6_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__GPIO1_IO22 = IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__SPDIF_LOCK = IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__ESAI_RX_FS = IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0), - MX6_PAD_ENET_REF_CLK__GPIO1_IO23 = IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__SPDIF_SR_CLK = IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__USB_OTG_ID = IOMUX_PAD(0x04EC, 0x01D8, 0, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ESAI_RX_HF_CLK = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0), - MX6_PAD_ENET_RX_ER__SPDIF_IN = IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0), - MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT= IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__GPIO1_IO24 = IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0), - MX6_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0), - MX6_PAD_ENET_CRS_DV__ESAI_TX_CLK = IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0), - MX6_PAD_ENET_CRS_DV__SPDIF_EXT_CLK = IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0), - MX6_PAD_ENET_CRS_DV__GPIO1_IO25 = IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__MLB_SIG = IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0), - MX6_PAD_ENET_RXD1__ENET_RX_DATA1 = IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0), - MX6_PAD_ENET_RXD1__ESAI_TX_FS = IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0), - MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT = IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__GPIO1_IO26 = IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__ENET_RX_DATA0 = IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0), - MX6_PAD_ENET_RXD0__ESAI_TX_HF_CLK = IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0), - MX6_PAD_ENET_RXD0__SPDIF_OUT = IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__GPIO1_IO27 = IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__ESAI_TX3_RX2 = IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0), - MX6_PAD_ENET_TX_EN__GPIO1_IO28 = IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__MLB_CLK = IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0), - MX6_PAD_ENET_TXD1__ENET_TX_DATA1 = IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__ESAI_TX2_RX3 = IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0), - MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__GPIO1_IO29 = IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__ENET_TX_DATA0 = IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__ESAI_TX4_RX1 = IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0), - MX6_PAD_ENET_TXD0__GPIO1_IO30 = IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__MLB_DATA = IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0), - MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__ESAI_TX5_RX0 = IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0), - MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__GPIO1_IO31 = IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0), - MX6_PAD_KEY_COL0__ENET_RX_DATA3 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0), - MX6_PAD_KEY_COL0__AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0), - MX6_PAD_KEY_COL0__KEY_COL0 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_TX_DATA = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_RX_DATA = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0), - MX6_PAD_KEY_COL0__GPIO4_IO06 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__DCIC1_OUT = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0), - MX6_PAD_KEY_ROW0__ENET_TX_DATA3 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0), - MX6_PAD_KEY_ROW0__KEY_ROW0 = IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__UART4_TX_DATA = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__UART4_RX_DATA = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0), - MX6_PAD_KEY_ROW0__GPIO4_IO07 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__DCIC2_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0), - MX6_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0), - MX6_PAD_KEY_COL1__AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0), - MX6_PAD_KEY_COL1__KEY_COL1 = IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_TX_DATA = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_RX_DATA = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0), - MX6_PAD_KEY_COL1__GPIO4_IO08 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__SD1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0), - MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0), - MX6_PAD_KEY_ROW1__KEY_ROW1 = IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__UART5_TX_DATA = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__UART5_RX_DATA = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0), - MX6_PAD_KEY_ROW1__GPIO4_IO09 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__SD2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0), - MX6_PAD_KEY_COL2__ENET_RX_DATA2 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0), - MX6_PAD_KEY_COL2__FLEXCAN1_TX = IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__KEY_COL2 = IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__GPIO4_IO10 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0), - MX6_PAD_KEY_ROW2__ENET_TX_DATA2 = IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__FLEXCAN1_RX = IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0), - MX6_PAD_KEY_ROW2__KEY_ROW2 = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__SD2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__GPIO4_IO11 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0), - MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0), - MX6_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0), - MX6_PAD_KEY_COL3__KEY_COL3 = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x05E0, 0x0210, 20, 0x08A0, 1, 0), - MX6_PAD_KEY_COL3__GPIO4_IO12 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__SPDIF_IN = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0), - MX6_PAD_KEY_ROW3__ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0), - MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0), - MX6_PAD_KEY_ROW3__KEY_ROW3 = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x05E4, 0x0214, 20, 0x08A4, 1, 0), - MX6_PAD_KEY_ROW3__GPIO4_IO13 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__SD1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__FLEXCAN2_TX = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__IPU1_SISG4 = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__USB_OTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0), - MX6_PAD_KEY_COL4__KEY_COL4 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_CTS_B = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_RTS_B = IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0), - MX6_PAD_KEY_COL4__GPIO4_IO14 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__FLEXCAN2_RX = IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0), - MX6_PAD_KEY_ROW4__IPU1_SISG5 = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__USB_OTG_PWR = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__KEY_ROW4 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__UART5_CTS_B = IOMUX_PAD(0x05EC, 0x021C, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__UART5_RTS_B = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0), - MX6_PAD_KEY_ROW4__GPIO4_IO15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_0__CCM_CLKO1 = IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0), - MX6_PAD_GPIO_0__KEY_COL5 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0), - MX6_PAD_GPIO_0__ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0), - MX6_PAD_GPIO_0__EPIT1_OUT = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_0__GPIO1_IO00 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_0__USB_H1_PWR = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_0__SNVS_VIO_5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_1__ESAI_RX_CLK = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0), - MX6_PAD_GPIO_1__WDOG2_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_1__KEY_ROW5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0), - MX6_PAD_GPIO_1__USB_OTG_ID = IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_1__PWM2_OUT = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_1__GPIO1_IO01 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_1__SD1_CD_B = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_9__ESAI_RX_FS = IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0), - MX6_PAD_GPIO_9__WDOG1_B = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_9__KEY_COL6 = IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0), - MX6_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_9__PWM1_OUT = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_9__GPIO1_IO09 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_9__SD1_WP = IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0), - MX6_PAD_GPIO_3__ESAI_RX_HF_CLK = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0), - MX6_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05FC, 0x022C, 18, 0x08A8, 1, 0), - MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_3__GPIO1_IO03 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_3__USB_H1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0), - MX6_PAD_GPIO_3__MLB_CLK = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0), - MX6_PAD_GPIO_6__ESAI_TX_CLK = IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0), - MX6_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0600, 0x0230, 18, 0x08AC, 1, 0), - MX6_PAD_GPIO_6__GPIO1_IO06 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_6__SD2_LCTL = IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_6__MLB_SIG = IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0), - MX6_PAD_GPIO_2__ESAI_TX_FS = IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0), - MX6_PAD_GPIO_2__KEY_ROW6 = IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0), - MX6_PAD_GPIO_2__GPIO1_IO02 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_2__SD2_WP = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_2__MLB_DATA = IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0), - MX6_PAD_GPIO_4__ESAI_TX_HF_CLK = IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0), - MX6_PAD_GPIO_4__KEY_COL7 = IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0), - MX6_PAD_GPIO_4__GPIO1_IO04 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_4__SD2_CD_B = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_5__ESAI_TX2_RX3 = IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0), - MX6_PAD_GPIO_5__KEY_ROW7 = IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0), - MX6_PAD_GPIO_5__CCM_CLKO1 = IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_5__GPIO1_IO05 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x060C, 0x023C, 22, 0x08A8, 2, 0), - MX6_PAD_GPIO_5__ARM_EVENTI = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_7__ESAI_TX4_RX1 = IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0), - MX6_PAD_GPIO_7__ECSPI5_RDY = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_7__EPIT1_OUT = IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_7__FLEXCAN1_TX = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_TX_DATA = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_RX_DATA = IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0), - MX6_PAD_GPIO_7__GPIO1_IO07 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_7__SPDIF_LOCK = IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_7__USB_OTG_HOST_MODE = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_8__ESAI_TX5_RX0 = IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0), - MX6_PAD_GPIO_8__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_8__EPIT2_OUT = IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_8__FLEXCAN1_RX = IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0), - MX6_PAD_GPIO_8__UART2_TX_DATA = IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_8__UART2_RX_DATA = IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0), - MX6_PAD_GPIO_8__GPIO1_IO08 = IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_8__SPDIF_SR_CLK = IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE = IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ESAI_TX3_RX2 = IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0), - MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ENET_REF_CLK = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0), - MX6_PAD_GPIO_16__SD1_LCTL = IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_16__SPDIF_IN = IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0), - MX6_PAD_GPIO_16__GPIO7_IO11 = IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x0618, 0x0248, 22, 0x08AC, 2, 0), - MX6_PAD_GPIO_16__JTAG_DE_B = IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_17__ESAI_TX0 = IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0), - MX6_PAD_GPIO_17__ENET_1588_EVENT3_IN = IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_17__CCM_PMIC_READY = IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0), - MX6_PAD_GPIO_17__SDMA_EXT_EVENT0 = IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0), - MX6_PAD_GPIO_17__SPDIF_OUT = IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_17__GPIO7_IO12 = IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_18__ESAI_TX1 = IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0), - MX6_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0), - MX6_PAD_GPIO_18__SD3_VSELECT = IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0), - MX6_PAD_GPIO_18__ASRC_EXT_CLK = IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0), - MX6_PAD_GPIO_18__GPIO7_IO13 = IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SNVS_VIO_5_CTL = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_19__KEY_COL5 = IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0), - MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_19__SPDIF_OUT = IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_19__CCM_CLKO1 = IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_19__GPIO4_IO05 = IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__ARM_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__CCM_CLKO1 = IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__GPIO5_IO19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__ARM_TRACE_CTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__EIM_DATA00 = IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__ARM_TRACE_CLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__EIM_DATA01 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__GPIO5_IO21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__ARM_TRACE00 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 = IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__EIM_DATA02 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0), - MX6_PAD_CSI0_DAT4__KEY_COL5 = IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0), - MX6_PAD_CSI0_DAT4__AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__GPIO5_IO22 = IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__ARM_TRACE01 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 = IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__EIM_DATA03 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0), - MX6_PAD_CSI0_DAT5__KEY_ROW5 = IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0), - MX6_PAD_CSI0_DAT5__AUD3_TXD = IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__GPIO5_IO23 = IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__ARM_TRACE02 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 = IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__EIM_DATA04 = IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0), - MX6_PAD_CSI0_DAT6__KEY_COL6 = IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0), - MX6_PAD_CSI0_DAT6__AUD3_TXFS = IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__GPIO5_IO24 = IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__ARM_TRACE03 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 = IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__EIM_DATA05 = IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0), - MX6_PAD_CSI0_DAT7__KEY_ROW6 = IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0), - MX6_PAD_CSI0_DAT7__AUD3_RXD = IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__GPIO5_IO25 = IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__ARM_TRACE04 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 = IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__EIM_DATA06 = IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0), - MX6_PAD_CSI0_DAT8__KEY_COL7 = IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0), - MX6_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0648, 0x0278, 20, 0x089C, 1, 0), - MX6_PAD_CSI0_DAT8__GPIO5_IO26 = IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__ARM_TRACE05 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 = IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__EIM_DATA07 = IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0), - MX6_PAD_CSI0_DAT9__KEY_ROW7 = IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0), - MX6_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x064C, 0x027C, 20, 0x0898, 1, 0), - MX6_PAD_CSI0_DAT9__GPIO5_IO27 = IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__ARM_TRACE06 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 = IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0), - MX6_PAD_CSI0_DAT10__UART1_TX_DATA = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__UART1_RX_DATA = IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0), - MX6_PAD_CSI0_DAT10__GPIO5_IO28 = IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__ARM_TRACE07 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0), - MX6_PAD_CSI0_DAT11__UART1_TX_DATA = IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__UART1_RX_DATA = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0), - MX6_PAD_CSI0_DAT11__GPIO5_IO29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__ARM_TRACE08 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 = IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__EIM_DATA08 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_TX_DATA = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_RX_DATA = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0), - MX6_PAD_CSI0_DAT12__GPIO5_IO30 = IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__ARM_TRACE09 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__EIM_DATA09 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_TX_DATA = IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_RX_DATA = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0), - MX6_PAD_CSI0_DAT13__GPIO5_IO31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__ARM_TRACE10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 = IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__EIM_DATA10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_TX_DATA = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_RX_DATA = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0), - MX6_PAD_CSI0_DAT14__GPIO6_IO00 = IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__ARM_TRACE11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__EIM_DATA11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_TX_DATA = IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_RX_DATA = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0), - MX6_PAD_CSI0_DAT15__GPIO6_IO01 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__ARM_TRACE12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 = IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__EIM_DATA12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_CTS_B = IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_RTS_B = IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0), - MX6_PAD_CSI0_DAT16__GPIO6_IO02 = IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__ARM_TRACE13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__EIM_DATA13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__UART4_CTS_B = IOMUX_PAD(0x066C, 0x029C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__UART4_RTS_B = IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0), - MX6_PAD_CSI0_DAT17__GPIO6_IO03 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__ARM_TRACE14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 = IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__EIM_DATA14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_CTS_B = IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_RTS_B = IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0), - MX6_PAD_CSI0_DAT18__GPIO6_IO04 = IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__ARM_TRACE15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__EIM_DATA15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__UART5_CTS_B = IOMUX_PAD(0x0674, 0x02A4, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__UART5_RTS_B = IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0), - MX6_PAD_CSI0_DAT19__GPIO6_IO05 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__SD3_DATA7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_TX_DATA = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_RX_DATA = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0), - MX6_PAD_SD3_DAT7__GPIO6_IO17 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__SD3_DATA6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__UART1_TX_DATA = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__UART1_RX_DATA = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0), - MX6_PAD_SD3_DAT6__GPIO6_IO18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__SD3_DATA5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_TX_DATA = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_RX_DATA = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0), - MX6_PAD_SD3_DAT5__GPIO7_IO00 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__SD3_DATA4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__UART2_TX_DATA = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__UART2_RX_DATA = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0), - MX6_PAD_SD3_DAT4__GPIO7_IO01 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__UART2_CTS_B = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__UART2_RTS_B = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0), - MX6_PAD_SD3_CMD__FLEXCAN1_TX = IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__GPIO7_IO02 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__UART2_CTS_B = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__UART2_RTS_B = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0), - MX6_PAD_SD3_CLK__FLEXCAN1_RX = IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0), - MX6_PAD_SD3_CLK__GPIO7_IO03 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__SD3_DATA0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__UART1_CTS_B = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__UART1_RTS_B = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0), - MX6_PAD_SD3_DAT0__FLEXCAN2_TX = IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__GPIO7_IO04 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__SD3_DATA1 = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_CTS_B = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_RTS_B = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0), - MX6_PAD_SD3_DAT1__FLEXCAN2_RX = IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0), - MX6_PAD_SD3_DAT1__GPIO7_IO05 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__SD3_DATA2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__GPIO7_IO06 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__SD3_DATA3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__UART3_CTS_B = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__UART3_RTS_B = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0), - MX6_PAD_SD3_DAT3__GPIO7_IO07 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), - MX6_PAD_SD3_RST__SD3_RESET = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_CTS_B = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_RTS_B = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0), - MX6_PAD_SD3_RST__GPIO7_IO08 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__NAND_CLE = IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__IPU2_SISG4 = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__GPIO6_IO07 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__NAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__SD4_RESET = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__GPIO6_IO08 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__NAND_WP_B = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__IPU2_SISG5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__GPIO6_IO09 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__NAND_READY_B = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__IPU2_DI0_PIN01 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__GPIO6_IO10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__NAND_CE0_B = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__GPIO6_IO11 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__NAND_CE1_B = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__SD4_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__SD3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__GPIO6_IO14 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__NAND_CE2_B = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__IPU1_SISG0 = IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__ESAI_TX0 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0), - MX6_PAD_NANDF_CS2__EIM_CRE = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__GPIO6_IO15 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__IPU2_SISG0 = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__NAND_CE3_B = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__IPU1_SISG1 = IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__ESAI_TX1 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0), - MX6_PAD_NANDF_CS3__EIM_ADDR26 = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__GPIO6_IO16 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__IPU2_SISG1 = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__SD4_CMD = IOMUX_PAD(0x06DC, 0x02F4, 16, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__NAND_RE_B = IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_TX_DATA = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_RX_DATA = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0), - MX6_PAD_SD4_CMD__GPIO7_IO09 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__SD4_CLK = IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__NAND_WE_B = IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__UART3_TX_DATA = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__UART3_RX_DATA = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0), - MX6_PAD_SD4_CLK__GPIO7_IO10 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__NAND_DATA00 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__SD1_DATA4 = IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__GPIO2_IO00 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__NAND_DATA01 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__SD1_DATA5 = IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__GPIO2_IO01 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__NAND_DATA02 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__SD1_DATA6 = IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__GPIO2_IO02 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__NAND_DATA03 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__SD1_DATA7 = IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__GPIO2_IO03 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__NAND_DATA04 = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__SD2_DATA4 = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__GPIO2_IO04 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__NAND_DATA05 = IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__SD2_DATA5 = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__GPIO2_IO05 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__NAND_DATA06 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__SD2_DATA6 = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__GPIO2_IO06 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__NAND_DATA07 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__SD2_DATA7 = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__GPIO2_IO07 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__SD4_DATA0 = IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__NAND_DQS = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__GPIO2_IO08 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__SD4_DATA1 = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__PWM3_OUT = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__GPIO2_IO09 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__SD4_DATA2 = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__PWM4_OUT = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__GPIO2_IO10 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__SD4_DATA3 = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__GPIO2_IO11 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__SD4_DATA4 = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__UART2_TX_DATA = IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__UART2_RX_DATA = IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0), - MX6_PAD_SD4_DAT4__GPIO2_IO12 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__SD4_DATA5 = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_CTS_B = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_RTS_B = IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0), - MX6_PAD_SD4_DAT5__GPIO2_IO13 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__SD4_DATA6 = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__UART2_CTS_B = IOMUX_PAD(0x071C, 0x0334, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__UART2_RTS_B = IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0), - MX6_PAD_SD4_DAT6__GPIO2_IO14 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__SD4_DATA7 = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_TX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_RX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0), - MX6_PAD_SD4_DAT7__GPIO2_IO15 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__SD1_DATA1 = IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0), - MX6_PAD_SD1_DAT1__PWM3_OUT = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPT_CAPTURE2 = IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPIO1_IO17 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__SD1_DATA0 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0), - MX6_PAD_SD1_DAT0__GPT_CAPTURE1 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__GPIO1_IO16 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__SD1_DATA3 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__ECSPI5_SS2 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPT_COMPARE3 = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__PWM1_OUT = IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_B = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPIO1_IO21 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_RESET_B_DEB = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x0730, 0x0348, 16, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0), - MX6_PAD_SD1_CMD__PWM4_OUT = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPT_COMPARE1 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPIO1_IO18 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__SD1_DATA2 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0), - MX6_PAD_SD1_DAT2__GPT_COMPARE2 = IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__PWM2_OUT = IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_B = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__GPIO1_IO19 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_RESET_B_DEB = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__ECSPI5_SCLK = IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0), - MX6_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__GPIO1_IO20 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__ECSPI5_SCLK = IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0), - MX6_PAD_SD2_CLK__KEY_COL5 = IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0), - MX6_PAD_SD2_CLK__AUD4_RXFS = IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0), - MX6_PAD_SD2_CLK__GPIO1_IO10 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x0740, 0x0358, 16, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0), - MX6_PAD_SD2_CMD__KEY_ROW5 = IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0), - MX6_PAD_SD2_CMD__AUD4_RXC = IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0), - MX6_PAD_SD2_CMD__GPIO1_IO11 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__SD2_DATA3 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__ECSPI5_SS3 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__KEY_COL6 = IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0), - MX6_PAD_SD2_DAT3__AUD4_TXC = IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0), - MX6_PAD_SD2_DAT3__GPIO1_IO12 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), -}; +MX6_PAD_DECL(SD2_DAT1__SD2_DATA1, 0x0360, 0x004C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__ECSPI5_SS0, 0x0360, 0x004C, 1, 0x0834, 0, 0) +MX6_PAD_DECL(SD2_DAT1__EIM_CS2_B, 0x0360, 0x004C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__AUD4_TXFS, 0x0360, 0x004C, 3, 0x07C8, 0, 0) +MX6_PAD_DECL(SD2_DAT1__KEY_COL7, 0x0360, 0x004C, 4, 0x08F0, 0, 0) +MX6_PAD_DECL(SD2_DAT1__GPIO1_IO14, 0x0360, 0x004C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__SD2_DATA2, 0x0364, 0x0050, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__ECSPI5_SS1, 0x0364, 0x0050, 1, 0x0838, 0, 0) +MX6_PAD_DECL(SD2_DAT2__EIM_CS3_B, 0x0364, 0x0050, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__AUD4_TXD, 0x0364, 0x0050, 3, 0x07B8, 0, 0) +MX6_PAD_DECL(SD2_DAT2__KEY_ROW6, 0x0364, 0x0050, 4, 0x08F8, 0, 0) +MX6_PAD_DECL(SD2_DAT2__GPIO1_IO13, 0x0364, 0x0050, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__SD2_DATA0, 0x0368, 0x0054, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__ECSPI5_MISO, 0x0368, 0x0054, 1, 0x082C, 0, 0) +MX6_PAD_DECL(SD2_DAT0__AUD4_RXD, 0x0368, 0x0054, 3, 0x07B4, 0, 0) +MX6_PAD_DECL(SD2_DAT0__KEY_ROW7, 0x0368, 0x0054, 4, 0x08FC, 0, 0) +MX6_PAD_DECL(SD2_DAT0__GPIO1_IO15, 0x0368, 0x0054, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__DCIC2_OUT, 0x0368, 0x0054, 6, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA, 0x036C, 0x0058, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__RGMII_TXC, 0x036C, 0x0058, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK, 0x036C, 0x0058, 2, 0x0918, 0, 0) +MX6_PAD_DECL(RGMII_TXC__GPIO6_IO19, 0x036C, 0x0058, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__XTALOSC_REF_CLK_24M, 0x036C, 0x0058, 7, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__HSI_TX_READY, 0x0370, 0x005C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__RGMII_TD0, 0x0370, 0x005C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__GPIO6_IO20, 0x0370, 0x005C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__HSI_RX_FLAG, 0x0374, 0x0060, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__RGMII_TD1, 0x0374, 0x0060, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__GPIO6_IO21, 0x0374, 0x0060, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__HSI_RX_DATA, 0x0378, 0x0064, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__RGMII_TD2, 0x0378, 0x0064, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__GPIO6_IO22, 0x0378, 0x0064, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__HSI_RX_WAKE, 0x037C, 0x0068, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__RGMII_TD3, 0x037C, 0x0068, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__GPIO6_IO23, 0x037C, 0x0068, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__USB_H3_DATA, 0x0380, 0x006C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__RGMII_RX_CTL, 0x0380, 0x006C, 1, 0x0858, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__GPIO6_IO24, 0x0380, 0x006C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD0__HSI_RX_READY, 0x0384, 0x0070, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD0__RGMII_RD0, 0x0384, 0x0070, 1, 0x0848, 0, 0) +MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25, 0x0384, 0x0070, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE, 0x0388, 0x0074, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26, 0x0388, 0x0074, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x0388, 0x0074, 7, 0x083C, 0, 0) +MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG, 0x038C, 0x0078, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD1__RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0, 0) +MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27, 0x038C, 0x0078, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD2__HSI_TX_DATA, 0x0390, 0x007C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD2__RGMII_RD2, 0x0390, 0x007C, 1, 0x0850, 0, 0) +MX6_PAD_DECL(RGMII_RD2__GPIO6_IO28, 0x0390, 0x007C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD3__HSI_TX_WAKE, 0x0394, 0x0080, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD3__RGMII_RD3, 0x0394, 0x0080, 1, 0x0854, 0, 0) +MX6_PAD_DECL(RGMII_RD3__GPIO6_IO29, 0x0394, 0x0080, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RXC__USB_H3_STROBE, 0x0398, 0x0084, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RXC__RGMII_RXC, 0x0398, 0x0084, 1, 0x0844, 0, 0) +MX6_PAD_DECL(RGMII_RXC__GPIO6_IO30, 0x0398, 0x0084, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__EIM_ADDR25, 0x039C, 0x0088, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__ECSPI4_SS1, 0x039C, 0x0088, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__ECSPI2_RDY, 0x039C, 0x0088, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__IPU1_DI1_PIN12, 0x039C, 0x0088, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__IPU1_DI0_D1_CS, 0x039C, 0x0088, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__GPIO5_IO02, 0x039C, 0x0088, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__HDMI_TX_CEC_LINE, 0x039C, 0x0088, 6, 0x088C, 0, 0) +MX6_PAD_DECL(EIM_EB2__EIM_EB2_B, 0x03A0, 0x008C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__ECSPI1_SS0, 0x03A0, 0x008C, 1, 0x0800, 0, 0) +MX6_PAD_DECL(EIM_EB2__IPU2_CSI1_DATA19, 0x03A0, 0x008C, 3, 0x08D4, 0, 0) +MX6_PAD_DECL(EIM_EB2__HDMI_TX_DDC_SCL, 0x03A0, 0x008C, 4, 0x0890, 0, 0) +MX6_PAD_DECL(EIM_EB2__GPIO2_IO30, 0x03A0, 0x008C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__I2C2_SCL, 0x03A0, 0x008C, 22, 0x08A0, 0, 0) +MX6_PAD_DECL(EIM_EB2__SRC_BOOT_CFG30, 0x03A0, 0x008C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__EIM_DATA16, 0x03A4, 0x0090, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__ECSPI1_SCLK, 0x03A4, 0x0090, 1, 0x07F4, 0, 0) +MX6_PAD_DECL(EIM_D16__IPU1_DI0_PIN05, 0x03A4, 0x0090, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__IPU2_CSI1_DATA18, 0x03A4, 0x0090, 3, 0x08D0, 0, 0) +MX6_PAD_DECL(EIM_D16__HDMI_TX_DDC_SDA, 0x03A4, 0x0090, 4, 0x0894, 0, 0) +MX6_PAD_DECL(EIM_D16__GPIO3_IO16, 0x03A4, 0x0090, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__I2C2_SDA, 0x03A4, 0x0090, 22, 0x08A4, 0, 0) +MX6_PAD_DECL(EIM_D17__EIM_DATA17, 0x03A8, 0x0094, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__ECSPI1_MISO, 0x03A8, 0x0094, 1, 0x07F8, 0, 0) +MX6_PAD_DECL(EIM_D17__IPU1_DI0_PIN06, 0x03A8, 0x0094, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__IPU2_CSI1_PIXCLK, 0x03A8, 0x0094, 3, 0x08E0, 0, 0) +MX6_PAD_DECL(EIM_D17__DCIC1_OUT, 0x03A8, 0x0094, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__GPIO3_IO17, 0x03A8, 0x0094, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__I2C3_SCL, 0x03A8, 0x0094, 22, 0x08A8, 0, 0) +MX6_PAD_DECL(EIM_D18__EIM_DATA18, 0x03AC, 0x0098, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__ECSPI1_MOSI, 0x03AC, 0x0098, 1, 0x07FC, 0, 0) +MX6_PAD_DECL(EIM_D18__IPU1_DI0_PIN07, 0x03AC, 0x0098, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__IPU2_CSI1_DATA17, 0x03AC, 0x0098, 3, 0x08CC, 0, 0) +MX6_PAD_DECL(EIM_D18__IPU1_DI1_D0_CS, 0x03AC, 0x0098, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__GPIO3_IO18, 0x03AC, 0x0098, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__I2C3_SDA, 0x03AC, 0x0098, 22, 0x08AC, 0, 0) +MX6_PAD_DECL(EIM_D19__EIM_DATA19, 0x03B0, 0x009C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__ECSPI1_SS1, 0x03B0, 0x009C, 1, 0x0804, 0, 0) +MX6_PAD_DECL(EIM_D19__IPU1_DI0_PIN08, 0x03B0, 0x009C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__IPU2_CSI1_DATA16, 0x03B0, 0x009C, 3, 0x08C8, 0, 0) +MX6_PAD_DECL(EIM_D19__UART1_CTS_B, 0x03B0, 0x009C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__UART1_RTS_B, 0x03B0, 0x009C, 4, 0x091C, 0, 0) +MX6_PAD_DECL(EIM_D19__GPIO3_IO19, 0x03B0, 0x009C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__EPIT1_OUT, 0x03B0, 0x009C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__EIM_DATA20, 0x03B4, 0x00A0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__ECSPI4_SS0, 0x03B4, 0x00A0, 1, 0x0824, 0, 0) +MX6_PAD_DECL(EIM_D20__IPU1_DI0_PIN16, 0x03B4, 0x00A0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__IPU2_CSI1_DATA15, 0x03B4, 0x00A0, 3, 0x08C4, 0, 0) +MX6_PAD_DECL(EIM_D20__UART1_CTS_B, 0x03B4, 0x00A0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__UART1_RTS_B, 0x03B4, 0x00A0, 4, 0x091C, 1, 0) +MX6_PAD_DECL(EIM_D20__GPIO3_IO20, 0x03B4, 0x00A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__EPIT2_OUT, 0x03B4, 0x00A0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__EIM_DATA21, 0x03B8, 0x00A4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__ECSPI4_SCLK, 0x03B8, 0x00A4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__IPU1_DI0_PIN17, 0x03B8, 0x00A4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__IPU2_CSI1_DATA11, 0x03B8, 0x00A4, 3, 0x08B4, 0, 0) +MX6_PAD_DECL(EIM_D21__USB_OTG_OC, 0x03B8, 0x00A4, 4, 0x0944, 0, 0) +MX6_PAD_DECL(EIM_D21__GPIO3_IO21, 0x03B8, 0x00A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__I2C1_SCL, 0x03B8, 0x00A4, 22, 0x0898, 0, 0) +MX6_PAD_DECL(EIM_D21__SPDIF_IN, 0x03B8, 0x00A4, 7, 0x0914, 0, 0) +MX6_PAD_DECL(EIM_D22__EIM_DATA22, 0x03BC, 0x00A8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__ECSPI4_MISO, 0x03BC, 0x00A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__IPU1_DI0_PIN01, 0x03BC, 0x00A8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__IPU2_CSI1_DATA10, 0x03BC, 0x00A8, 3, 0x08B0, 0, 0) +MX6_PAD_DECL(EIM_D22__USB_OTG_PWR, 0x03BC, 0x00A8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__GPIO3_IO22, 0x03BC, 0x00A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__SPDIF_OUT, 0x03BC, 0x00A8, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__EIM_DATA23, 0x03C0, 0x00AC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI0_D0_CS, 0x03C0, 0x00AC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__UART3_CTS_B, 0x03C0, 0x00AC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__UART3_RTS_B, 0x03C0, 0x00AC, 2, 0x092C, 0, 0) +MX6_PAD_DECL(EIM_D23__UART1_DCD_B, 0x03C0, 0x00AC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU2_CSI1_DATA_EN, 0x03C0, 0x00AC, 4, 0x08D8, 0, 0) +MX6_PAD_DECL(EIM_D23__GPIO3_IO23, 0x03C0, 0x00AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN02, 0x03C0, 0x00AC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN14, 0x03C0, 0x00AC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__EIM_EB3_B, 0x03C4, 0x00B0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__ECSPI4_RDY, 0x03C4, 0x00B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__UART3_CTS_B, 0x03C4, 0x00B0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__UART3_RTS_B, 0x03C4, 0x00B0, 2, 0x092C, 1, 0) +MX6_PAD_DECL(EIM_EB3__UART1_RI_B, 0x03C4, 0x00B0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__IPU2_CSI1_HSYNC, 0x03C4, 0x00B0, 4, 0x08DC, 0, 0) +MX6_PAD_DECL(EIM_EB3__GPIO2_IO31, 0x03C4, 0x00B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__IPU1_DI1_PIN03, 0x03C4, 0x00B0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__SRC_BOOT_CFG31, 0x03C4, 0x00B0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__EIM_DATA24, 0x03C8, 0x00B4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI4_SS2, 0x03C8, 0x00B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__UART3_TX_DATA, 0x03C8, 0x00B4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__UART3_RX_DATA, 0x03C8, 0x00B4, 2, 0x0930, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI1_SS2, 0x03C8, 0x00B4, 3, 0x0808, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI2_SS2, 0x03C8, 0x00B4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__GPIO3_IO24, 0x03C8, 0x00B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__AUD5_RXFS, 0x03C8, 0x00B4, 6, 0x07D8, 0, 0) +MX6_PAD_DECL(EIM_D24__UART1_DTR_B, 0x03C8, 0x00B4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__EIM_DATA25, 0x03CC, 0x00B8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__ECSPI4_SS3, 0x03CC, 0x00B8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__UART3_TX_DATA, 0x03CC, 0x00B8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__UART3_RX_DATA, 0x03CC, 0x00B8, 2, 0x0930, 1, 0) +MX6_PAD_DECL(EIM_D25__ECSPI1_SS3, 0x03CC, 0x00B8, 3, 0x080C, 0, 0) +MX6_PAD_DECL(EIM_D25__ECSPI2_SS3, 0x03CC, 0x00B8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__GPIO3_IO25, 0x03CC, 0x00B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__AUD5_RXC, 0x03CC, 0x00B8, 6, 0x07D4, 0, 0) +MX6_PAD_DECL(EIM_D25__UART1_DSR_B, 0x03CC, 0x00B8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__EIM_DATA26, 0x03D0, 0x00BC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_DI1_PIN11, 0x03D0, 0x00BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_CSI0_DATA01, 0x03D0, 0x00BC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU2_CSI1_DATA14, 0x03D0, 0x00BC, 3, 0x08C0, 0, 0) +MX6_PAD_DECL(EIM_D26__UART2_TX_DATA, 0x03D0, 0x00BC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__UART2_RX_DATA, 0x03D0, 0x00BC, 4, 0x0928, 0, 0) +MX6_PAD_DECL(EIM_D26__GPIO3_IO26, 0x03D0, 0x00BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_SISG2, 0x03D0, 0x00BC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_DISP1_DATA22, 0x03D0, 0x00BC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__EIM_DATA27, 0x03D4, 0x00C0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_DI1_PIN13, 0x03D4, 0x00C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_CSI0_DATA00, 0x03D4, 0x00C0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU2_CSI1_DATA13, 0x03D4, 0x00C0, 3, 0x08BC, 0, 0) +MX6_PAD_DECL(EIM_D27__UART2_TX_DATA, 0x03D4, 0x00C0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__UART2_RX_DATA, 0x03D4, 0x00C0, 4, 0x0928, 1, 0) +MX6_PAD_DECL(EIM_D27__GPIO3_IO27, 0x03D4, 0x00C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_SISG3, 0x03D4, 0x00C0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_DISP1_DATA23, 0x03D4, 0x00C0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__EIM_DATA28, 0x03D8, 0x00C4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__I2C1_SDA, 0x03D8, 0x00C4, 17, 0x089C, 0, 0) +MX6_PAD_DECL(EIM_D28__ECSPI4_MOSI, 0x03D8, 0x00C4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU2_CSI1_DATA12, 0x03D8, 0x00C4, 3, 0x08B8, 0, 0) +MX6_PAD_DECL(EIM_D28__UART2_DTE_CTS_B, 0x03D8, 0x00C4, 4, 0x0924, 0, 0) +MX6_PAD_DECL(EIM_D28__UART2_DTE_RTS_B, 0x03D8, 0x00C4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__GPIO3_IO28, 0x03D8, 0x00C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_EXT_TRIG, 0x03D8, 0x00C4, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_DI0_PIN13, 0x03D8, 0x00C4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__EIM_DATA29, 0x03DC, 0x00C8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_DI1_PIN15, 0x03DC, 0x00C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__ECSPI4_SS0, 0x03DC, 0x00C8, 2, 0x0824, 1, 0) +MX6_PAD_DECL(EIM_D29__UART2_CTS_B, 0x03DC, 0x00C8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__UART2_RTS_B, 0x03DC, 0x00C8, 4, 0x0924, 1, 0) +MX6_PAD_DECL(EIM_D29__GPIO3_IO29, 0x03DC, 0x00C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU2_CSI1_VSYNC, 0x03DC, 0x00C8, 6, 0x08E4, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_DI0_PIN14, 0x03DC, 0x00C8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__EIM_DATA30, 0x03E0, 0x00CC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_DISP1_DATA21, 0x03E0, 0x00CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_DI0_PIN11, 0x03E0, 0x00CC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_CSI0_DATA03, 0x03E0, 0x00CC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__UART3_CTS_B, 0x03E0, 0x00CC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__UART3_RTS_B, 0x03E0, 0x00CC, 4, 0x092C, 2, 0) +MX6_PAD_DECL(EIM_D30__GPIO3_IO30, 0x03E0, 0x00CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__USB_H1_OC, 0x03E0, 0x00CC, 6, 0x0948, 0, 0) +MX6_PAD_DECL(EIM_D31__EIM_DATA31, 0x03E4, 0x00D0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_DISP1_DATA20, 0x03E4, 0x00D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_DI0_PIN12, 0x03E4, 0x00D0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_CSI0_DATA02, 0x03E4, 0x00D0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__UART3_CTS_B, 0x03E4, 0x00D0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__UART3_RTS_B, 0x03E4, 0x00D0, 4, 0x092C, 3, 0) +MX6_PAD_DECL(EIM_D31__GPIO3_IO31, 0x03E4, 0x00D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__USB_H1_PWR, 0x03E4, 0x00D0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__EIM_ADDR24, 0x03E8, 0x00D4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_DISP1_DATA19, 0x03E8, 0x00D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU2_CSI1_DATA19, 0x03E8, 0x00D4, 2, 0x08D4, 1, 0) +MX6_PAD_DECL(EIM_A24__IPU2_SISG2, 0x03E8, 0x00D4, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_SISG2, 0x03E8, 0x00D4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__GPIO5_IO04, 0x03E8, 0x00D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__SRC_BOOT_CFG24, 0x03E8, 0x00D4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__EIM_ADDR23, 0x03EC, 0x00D8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_DISP1_DATA18, 0x03EC, 0x00D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU2_CSI1_DATA18, 0x03EC, 0x00D8, 2, 0x08D0, 1, 0) +MX6_PAD_DECL(EIM_A23__IPU2_SISG3, 0x03EC, 0x00D8, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_SISG3, 0x03EC, 0x00D8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__GPIO6_IO06, 0x03EC, 0x00D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__SRC_BOOT_CFG23, 0x03EC, 0x00D8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__EIM_ADDR22, 0x03F0, 0x00DC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__IPU1_DISP1_DATA17, 0x03F0, 0x00DC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__IPU2_CSI1_DATA17, 0x03F0, 0x00DC, 2, 0x08CC, 1, 0) +MX6_PAD_DECL(EIM_A22__GPIO2_IO16, 0x03F0, 0x00DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__SRC_BOOT_CFG22, 0x03F0, 0x00DC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__EIM_ADDR21, 0x03F4, 0x00E0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__IPU1_DISP1_DATA16, 0x03F4, 0x00E0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__IPU2_CSI1_DATA16, 0x03F4, 0x00E0, 2, 0x08C8, 1, 0) +MX6_PAD_DECL(EIM_A21__GPIO2_IO17, 0x03F4, 0x00E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__SRC_BOOT_CFG21, 0x03F4, 0x00E0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__EIM_ADDR20, 0x03F8, 0x00E4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__IPU1_DISP1_DATA15, 0x03F8, 0x00E4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__IPU2_CSI1_DATA15, 0x03F8, 0x00E4, 2, 0x08C4, 1, 0) +MX6_PAD_DECL(EIM_A20__GPIO2_IO18, 0x03F8, 0x00E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__SRC_BOOT_CFG20, 0x03F8, 0x00E4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__EIM_ADDR19, 0x03FC, 0x00E8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__IPU1_DISP1_DATA14, 0x03FC, 0x00E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__IPU2_CSI1_DATA14, 0x03FC, 0x00E8, 2, 0x08C0, 1, 0) +MX6_PAD_DECL(EIM_A19__GPIO2_IO19, 0x03FC, 0x00E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__SRC_BOOT_CFG19, 0x03FC, 0x00E8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__EIM_ADDR18, 0x0400, 0x00EC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__IPU1_DISP1_DATA13, 0x0400, 0x00EC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__IPU2_CSI1_DATA13, 0x0400, 0x00EC, 2, 0x08BC, 1, 0) +MX6_PAD_DECL(EIM_A18__GPIO2_IO20, 0x0400, 0x00EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__SRC_BOOT_CFG18, 0x0400, 0x00EC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__EIM_ADDR17, 0x0404, 0x00F0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__IPU1_DISP1_DATA12, 0x0404, 0x00F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__IPU2_CSI1_DATA12, 0x0404, 0x00F0, 2, 0x08B8, 1, 0) +MX6_PAD_DECL(EIM_A17__GPIO2_IO21, 0x0404, 0x00F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__SRC_BOOT_CFG17, 0x0404, 0x00F0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__EIM_ADDR16, 0x0408, 0x00F4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__IPU1_DI1_DISP_CLK, 0x0408, 0x00F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__IPU2_CSI1_PIXCLK, 0x0408, 0x00F4, 2, 0x08E0, 1, 0) +MX6_PAD_DECL(EIM_A16__GPIO2_IO22, 0x0408, 0x00F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__SRC_BOOT_CFG16, 0x0408, 0x00F4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__EIM_CS0_B, 0x040C, 0x00F8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__IPU1_DI1_PIN05, 0x040C, 0x00F8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__ECSPI2_SCLK, 0x040C, 0x00F8, 2, 0x0810, 0, 0) +MX6_PAD_DECL(EIM_CS0__GPIO2_IO23, 0x040C, 0x00F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__EIM_CS1_B, 0x0410, 0x00FC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__IPU1_DI1_PIN06, 0x0410, 0x00FC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__ECSPI2_MOSI, 0x0410, 0x00FC, 2, 0x0818, 0, 0) +MX6_PAD_DECL(EIM_CS1__GPIO2_IO24, 0x0410, 0x00FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__EIM_OE_B, 0x0414, 0x0100, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__IPU1_DI1_PIN07, 0x0414, 0x0100, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__ECSPI2_MISO, 0x0414, 0x0100, 2, 0x0814, 0, 0) +MX6_PAD_DECL(EIM_OE__GPIO2_IO25, 0x0414, 0x0100, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__EIM_RW, 0x0418, 0x0104, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__IPU1_DI1_PIN08, 0x0418, 0x0104, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__ECSPI2_SS0, 0x0418, 0x0104, 2, 0x081C, 0, 0) +MX6_PAD_DECL(EIM_RW__GPIO2_IO26, 0x0418, 0x0104, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__SRC_BOOT_CFG29, 0x0418, 0x0104, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__EIM_LBA_B, 0x041C, 0x0108, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__IPU1_DI1_PIN17, 0x041C, 0x0108, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__ECSPI2_SS1, 0x041C, 0x0108, 2, 0x0820, 0, 0) +MX6_PAD_DECL(EIM_LBA__GPIO2_IO27, 0x041C, 0x0108, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__SRC_BOOT_CFG26, 0x041C, 0x0108, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__EIM_EB0_B, 0x0420, 0x010C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__IPU1_DISP1_DATA11, 0x0420, 0x010C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__IPU2_CSI1_DATA11, 0x0420, 0x010C, 2, 0x08B4, 1, 0) +MX6_PAD_DECL(EIM_EB0__CCM_PMIC_READY, 0x0420, 0x010C, 4, 0x07F0, 0, 0) +MX6_PAD_DECL(EIM_EB0__GPIO2_IO28, 0x0420, 0x010C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__SRC_BOOT_CFG27, 0x0420, 0x010C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__EIM_EB1_B, 0x0424, 0x0110, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__IPU1_DISP1_DATA10, 0x0424, 0x0110, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__IPU2_CSI1_DATA10, 0x0424, 0x0110, 2, 0x08B0, 1, 0) +MX6_PAD_DECL(EIM_EB1__GPIO2_IO29, 0x0424, 0x0110, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__SRC_BOOT_CFG28, 0x0424, 0x0110, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__EIM_AD00, 0x0428, 0x0114, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__IPU1_DISP1_DATA09, 0x0428, 0x0114, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__IPU2_CSI1_DATA09, 0x0428, 0x0114, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__GPIO3_IO00, 0x0428, 0x0114, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__SRC_BOOT_CFG00, 0x0428, 0x0114, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__EIM_AD01, 0x042C, 0x0118, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__IPU1_DISP1_DATA08, 0x042C, 0x0118, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__IPU2_CSI1_DATA08, 0x042C, 0x0118, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__GPIO3_IO01, 0x042C, 0x0118, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__SRC_BOOT_CFG01, 0x042C, 0x0118, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__EIM_AD02, 0x0430, 0x011C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__IPU1_DISP1_DATA07, 0x0430, 0x011C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__IPU2_CSI1_DATA07, 0x0430, 0x011C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__GPIO3_IO02, 0x0430, 0x011C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__SRC_BOOT_CFG02, 0x0430, 0x011C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__EIM_AD03, 0x0434, 0x0120, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__IPU1_DISP1_DATA06, 0x0434, 0x0120, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__IPU2_CSI1_DATA06, 0x0434, 0x0120, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__GPIO3_IO03, 0x0434, 0x0120, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__SRC_BOOT_CFG03, 0x0434, 0x0120, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__EIM_AD04, 0x0438, 0x0124, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__IPU1_DISP1_DATA05, 0x0438, 0x0124, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__IPU2_CSI1_DATA05, 0x0438, 0x0124, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__GPIO3_IO04, 0x0438, 0x0124, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__SRC_BOOT_CFG04, 0x0438, 0x0124, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__EIM_AD05, 0x043C, 0x0128, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__IPU1_DISP1_DATA04, 0x043C, 0x0128, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__IPU2_CSI1_DATA04, 0x043C, 0x0128, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__GPIO3_IO05, 0x043C, 0x0128, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__SRC_BOOT_CFG05, 0x043C, 0x0128, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__EIM_AD06, 0x0440, 0x012C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__IPU1_DISP1_DATA03, 0x0440, 0x012C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__IPU2_CSI1_DATA03, 0x0440, 0x012C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__GPIO3_IO06, 0x0440, 0x012C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__SRC_BOOT_CFG06, 0x0440, 0x012C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__EIM_AD07, 0x0444, 0x0130, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__IPU1_DISP1_DATA02, 0x0444, 0x0130, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__IPU2_CSI1_DATA02, 0x0444, 0x0130, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__GPIO3_IO07, 0x0444, 0x0130, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__SRC_BOOT_CFG07, 0x0444, 0x0130, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__EIM_AD08, 0x0448, 0x0134, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__IPU1_DISP1_DATA01, 0x0448, 0x0134, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__IPU2_CSI1_DATA01, 0x0448, 0x0134, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__GPIO3_IO08, 0x0448, 0x0134, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__SRC_BOOT_CFG08, 0x0448, 0x0134, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__EIM_AD09, 0x044C, 0x0138, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__IPU1_DISP1_DATA00, 0x044C, 0x0138, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__IPU2_CSI1_DATA00, 0x044C, 0x0138, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__GPIO3_IO09, 0x044C, 0x0138, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__SRC_BOOT_CFG09, 0x044C, 0x0138, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__EIM_AD10, 0x0450, 0x013C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__IPU1_DI1_PIN15, 0x0450, 0x013C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__IPU2_CSI1_DATA_EN, 0x0450, 0x013C, 2, 0x08D8, 1, 0) +MX6_PAD_DECL(EIM_DA10__GPIO3_IO10, 0x0450, 0x013C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__SRC_BOOT_CFG10, 0x0450, 0x013C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__EIM_AD11, 0x0454, 0x0140, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__IPU1_DI1_PIN02, 0x0454, 0x0140, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__IPU2_CSI1_HSYNC, 0x0454, 0x0140, 2, 0x08DC, 1, 0) +MX6_PAD_DECL(EIM_DA11__GPIO3_IO11, 0x0454, 0x0140, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__SRC_BOOT_CFG11, 0x0454, 0x0140, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__EIM_AD12, 0x0458, 0x0144, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__IPU1_DI1_PIN03, 0x0458, 0x0144, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__IPU2_CSI1_VSYNC, 0x0458, 0x0144, 2, 0x08E4, 1, 0) +MX6_PAD_DECL(EIM_DA12__GPIO3_IO12, 0x0458, 0x0144, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__SRC_BOOT_CFG12, 0x0458, 0x0144, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__EIM_AD13, 0x045C, 0x0148, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__IPU1_DI1_D0_CS, 0x045C, 0x0148, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__GPIO3_IO13, 0x045C, 0x0148, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__SRC_BOOT_CFG13, 0x045C, 0x0148, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__EIM_AD14, 0x0460, 0x014C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__IPU1_DI1_D1_CS, 0x0460, 0x014C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__GPIO3_IO14, 0x0460, 0x014C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__SRC_BOOT_CFG14, 0x0460, 0x014C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__EIM_AD15, 0x0464, 0x0150, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN01, 0x0464, 0x0150, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN04, 0x0464, 0x0150, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__GPIO3_IO15, 0x0464, 0x0150, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__SRC_BOOT_CFG15, 0x0464, 0x0150, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__EIM_WAIT_B, 0x0468, 0x0154, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__EIM_DTACK_B, 0x0468, 0x0154, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__GPIO5_IO00, 0x0468, 0x0154, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__SRC_BOOT_CFG25, 0x0468, 0x0154, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__EIM_BCLK, 0x046C, 0x0158, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__IPU1_DI1_PIN16, 0x046C, 0x0158, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__GPIO6_IO31, 0x046C, 0x0158, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, 0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_DISP_CLK__IPU2_DI0_DISP_CLK, 0x0470, 0x015C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__GPIO4_IO16, 0x0470, 0x015C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__IPU1_DI0_PIN15, 0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN15__IPU2_DI0_PIN15, 0x0474, 0x0160, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__AUD6_TXC, 0x0474, 0x0160, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__GPIO4_IO17, 0x0474, 0x0160, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__IPU1_DI0_PIN02, 0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN2__IPU2_DI0_PIN02, 0x0478, 0x0164, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__AUD6_TXD, 0x0478, 0x0164, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__GPIO4_IO18, 0x0478, 0x0164, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__IPU1_DI0_PIN03, 0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN3__IPU2_DI0_PIN03, 0x047C, 0x0168, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__AUD6_TXFS, 0x047C, 0x0168, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__GPIO4_IO19, 0x047C, 0x0168, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__IPU1_DI0_PIN04, 0x0480, 0x016C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__IPU2_DI0_PIN04, 0x0480, 0x016C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__AUD6_RXD, 0x0480, 0x016C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__SD1_WP, 0x0480, 0x016C, 3, 0x094C, 0, 0) +MX6_PAD_DECL(DI0_PIN4__GPIO4_IO20, 0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT0__IPU1_DISP0_DATA00, 0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT0__IPU2_DISP0_DATA00, 0x0484, 0x0170, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__ECSPI3_SCLK, 0x0484, 0x0170, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__GPIO4_IO21, 0x0484, 0x0170, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01, 0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT1__IPU2_DISP0_DATA01, 0x0488, 0x0174, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI, 0x0488, 0x0174, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22, 0x0488, 0x0174, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02, 0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT2__IPU2_DISP0_DATA02, 0x048C, 0x0178, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO, 0x048C, 0x0178, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23, 0x048C, 0x0178, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__IPU1_DISP0_DATA03, 0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT3__IPU2_DISP0_DATA03, 0x0490, 0x017C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__ECSPI3_SS0, 0x0490, 0x017C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__GPIO4_IO24, 0x0490, 0x017C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__IPU1_DISP0_DATA04, 0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT4__IPU2_DISP0_DATA04, 0x0494, 0x0180, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__ECSPI3_SS1, 0x0494, 0x0180, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__GPIO4_IO25, 0x0494, 0x0180, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__IPU1_DISP0_DATA05, 0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT5__IPU2_DISP0_DATA05, 0x0498, 0x0184, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__ECSPI3_SS2, 0x0498, 0x0184, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__AUD6_RXFS, 0x0498, 0x0184, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__GPIO4_IO26, 0x0498, 0x0184, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__IPU1_DISP0_DATA06, 0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT6__IPU2_DISP0_DATA06, 0x049C, 0x0188, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__ECSPI3_SS3, 0x049C, 0x0188, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__AUD6_RXC, 0x049C, 0x0188, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__GPIO4_IO27, 0x049C, 0x0188, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__IPU1_DISP0_DATA07, 0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT7__IPU2_DISP0_DATA07, 0x04A0, 0x018C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__ECSPI3_RDY, 0x04A0, 0x018C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__GPIO4_IO28, 0x04A0, 0x018C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__IPU1_DISP0_DATA08, 0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT8__IPU2_DISP0_DATA08, 0x04A4, 0x0190, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__PWM1_OUT, 0x04A4, 0x0190, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__WDOG1_B, 0x04A4, 0x0190, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__GPIO4_IO29, 0x04A4, 0x0190, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__IPU1_DISP0_DATA09, 0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT9__IPU2_DISP0_DATA09, 0x04A8, 0x0194, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__PWM2_OUT, 0x04A8, 0x0194, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__WDOG2_B, 0x04A8, 0x0194, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__GPIO4_IO30, 0x04A8, 0x0194, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10, 0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT10__IPU2_DISP0_DATA10, 0x04AC, 0x0198, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31, 0x04AC, 0x0198, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11, 0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT11__IPU2_DISP0_DATA11, 0x04B0, 0x019C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT11__GPIO5_IO05, 0x04B0, 0x019C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT12__IPU1_DISP0_DATA12, 0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT12__IPU2_DISP0_DATA12, 0x04B4, 0x01A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT12__GPIO5_IO06, 0x04B4, 0x01A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__IPU1_DISP0_DATA13, 0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT13__IPU2_DISP0_DATA13, 0x04B8, 0x01A4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__AUD5_RXFS, 0x04B8, 0x01A4, 3, 0x07D8, 1, 0) +MX6_PAD_DECL(DISP0_DAT13__GPIO5_IO07, 0x04B8, 0x01A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__IPU1_DISP0_DATA14, 0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT14__IPU2_DISP0_DATA14, 0x04BC, 0x01A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__AUD5_RXC, 0x04BC, 0x01A8, 3, 0x07D4, 1, 0) +MX6_PAD_DECL(DISP0_DAT14__GPIO5_IO08, 0x04BC, 0x01A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__IPU1_DISP0_DATA15, 0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT15__IPU2_DISP0_DATA15, 0x04C0, 0x01AC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__ECSPI1_SS1, 0x04C0, 0x01AC, 2, 0x0804, 1, 0) +MX6_PAD_DECL(DISP0_DAT15__ECSPI2_SS1, 0x04C0, 0x01AC, 3, 0x0820, 1, 0) +MX6_PAD_DECL(DISP0_DAT15__GPIO5_IO09, 0x04C0, 0x01AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__IPU1_DISP0_DATA16, 0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT16__IPU2_DISP0_DATA16, 0x04C4, 0x01B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__ECSPI2_MOSI, 0x04C4, 0x01B0, 2, 0x0818, 1, 0) +MX6_PAD_DECL(DISP0_DAT16__AUD5_TXC, 0x04C4, 0x01B0, 3, 0x07DC, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__SDMA_EXT_EVENT0, 0x04C4, 0x01B0, 4, 0x090C, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__GPIO5_IO10, 0x04C4, 0x01B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__IPU1_DISP0_DATA17, 0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT17__IPU2_DISP0_DATA17, 0x04C8, 0x01B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__ECSPI2_MISO, 0x04C8, 0x01B4, 2, 0x0814, 1, 0) +MX6_PAD_DECL(DISP0_DAT17__AUD5_TXD, 0x04C8, 0x01B4, 3, 0x07D0, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__SDMA_EXT_EVENT1, 0x04C8, 0x01B4, 4, 0x0910, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__GPIO5_IO11, 0x04C8, 0x01B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__IPU1_DISP0_DATA18, 0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT18__IPU2_DISP0_DATA18, 0x04CC, 0x01B8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__ECSPI2_SS0, 0x04CC, 0x01B8, 2, 0x081C, 1, 0) +MX6_PAD_DECL(DISP0_DAT18__AUD5_TXFS, 0x04CC, 0x01B8, 3, 0x07E0, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__AUD4_RXFS, 0x04CC, 0x01B8, 4, 0x07C0, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__GPIO5_IO12, 0x04CC, 0x01B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__EIM_CS2_B, 0x04CC, 0x01B8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__IPU1_DISP0_DATA19, 0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT19__IPU2_DISP0_DATA19, 0x04D0, 0x01BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__ECSPI2_SCLK, 0x04D0, 0x01BC, 2, 0x0810, 1, 0) +MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD, 0x04D0, 0x01BC, 3, 0x07CC, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC, 0x04D0, 0x01BC, 4, 0x07BC, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13, 0x04D0, 0x01BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B, 0x04D0, 0x01BC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__IPU1_DISP0_DATA20, 0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT20__IPU2_DISP0_DATA20, 0x04D4, 0x01C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__ECSPI1_SCLK, 0x04D4, 0x01C0, 2, 0x07F4, 1, 0) +MX6_PAD_DECL(DISP0_DAT20__AUD4_TXC, 0x04D4, 0x01C0, 3, 0x07C4, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__GPIO5_IO14, 0x04D4, 0x01C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__IPU1_DISP0_DATA21, 0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT21__IPU2_DISP0_DATA21, 0x04D8, 0x01C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__ECSPI1_MOSI, 0x04D8, 0x01C4, 2, 0x07FC, 1, 0) +MX6_PAD_DECL(DISP0_DAT21__AUD4_TXD, 0x04D8, 0x01C4, 3, 0x07B8, 1, 0) +MX6_PAD_DECL(DISP0_DAT21__GPIO5_IO15, 0x04D8, 0x01C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__IPU1_DISP0_DATA22, 0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT22__IPU2_DISP0_DATA22, 0x04DC, 0x01C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__ECSPI1_MISO, 0x04DC, 0x01C8, 2, 0x07F8, 1, 0) +MX6_PAD_DECL(DISP0_DAT22__AUD4_TXFS, 0x04DC, 0x01C8, 3, 0x07C8, 1, 0) +MX6_PAD_DECL(DISP0_DAT22__GPIO5_IO16, 0x04DC, 0x01C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__IPU1_DISP0_DATA23, 0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT23__IPU2_DISP0_DATA23, 0x04E0, 0x01CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__ECSPI1_SS0, 0x04E0, 0x01CC, 2, 0x0800, 1, 0) +MX6_PAD_DECL(DISP0_DAT23__AUD4_RXD, 0x04E0, 0x01CC, 3, 0x07B4, 1, 0) +MX6_PAD_DECL(DISP0_DAT23__GPIO5_IO17, 0x04E0, 0x01CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ENET_MDIO, 0x04E4, 0x01D0, 1, 0x0840, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK, 0x04E4, 0x01D0, 2, 0x086C, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT, 0x04E4, 0x01D0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22, 0x04E4, 0x01D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK, 0x04E4, 0x01D0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x04E8, 0x01D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS, 0x04E8, 0x01D4, 2, 0x085C, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23, 0x04E8, 0x01D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__USB_OTG_ID, 0x04EC, 0x01D8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__ENET_RX_ER, 0x04EC, 0x01D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__ESAI_RX_HF_CLK, 0x04EC, 0x01D8, 2, 0x0864, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__SPDIF_IN, 0x04EC, 0x01D8, 3, 0x0914, 1, 0) +MX6_PAD_DECL(ENET_RX_ER__ENET_1588_EVENT2_OUT, 0x04EC, 0x01D8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__GPIO1_IO24, 0x04EC, 0x01D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__ENET_RX_EN, 0x04F0, 0x01DC, 1, 0x0858, 1, 0) +MX6_PAD_DECL(ENET_CRS_DV__ESAI_TX_CLK, 0x04F0, 0x01DC, 2, 0x0870, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__SPDIF_EXT_CLK, 0x04F0, 0x01DC, 3, 0x0918, 1, 0) +MX6_PAD_DECL(ENET_CRS_DV__GPIO1_IO25, 0x04F0, 0x01DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD1__MLB_SIG, 0x04F4, 0x01E0, 0, 0x0908, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ENET_RX_DATA1, 0x04F4, 0x01E0, 1, 0x084C, 1, 0) +MX6_PAD_DECL(ENET_RXD1__ESAI_TX_FS, 0x04F4, 0x01E0, 2, 0x0860, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ENET_1588_EVENT3_OUT, 0x04F4, 0x01E0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD1__GPIO1_IO26, 0x04F4, 0x01E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD0__ENET_RX_DATA0, 0x04F8, 0x01E4, 1, 0x0848, 1, 0) +MX6_PAD_DECL(ENET_RXD0__ESAI_TX_HF_CLK, 0x04F8, 0x01E4, 2, 0x0868, 0, 0) +MX6_PAD_DECL(ENET_RXD0__SPDIF_OUT, 0x04F8, 0x01E4, 3, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD0__GPIO1_IO27, 0x04F8, 0x01E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__ENET_TX_EN, 0x04FC, 0x01E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__ESAI_TX3_RX2, 0x04FC, 0x01E8, 2, 0x0880, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__GPIO1_IO28, 0x04FC, 0x01E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__MLB_CLK, 0x0500, 0x01EC, 0, 0x0900, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ENET_TX_DATA1, 0x0500, 0x01EC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ESAI_TX2_RX3, 0x0500, 0x01EC, 2, 0x087C, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ENET_1588_EVENT0_IN, 0x0500, 0x01EC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__GPIO1_IO29, 0x0500, 0x01EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD0__ENET_TX_DATA0, 0x0504, 0x01F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD0__ESAI_TX4_RX1, 0x0504, 0x01F0, 2, 0x0884, 0, 0) +MX6_PAD_DECL(ENET_TXD0__GPIO1_IO30, 0x0504, 0x01F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__MLB_DATA, 0x0508, 0x01F4, 0, 0x0904, 0, 0) +MX6_PAD_DECL(ENET_MDC__ENET_MDC, 0x0508, 0x01F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__ESAI_TX5_RX0, 0x0508, 0x01F4, 2, 0x0888, 0, 0) +MX6_PAD_DECL(ENET_MDC__ENET_1588_EVENT1_IN, 0x0508, 0x01F4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__GPIO1_IO31, 0x0508, 0x01F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__ECSPI1_SCLK, 0x05C8, 0x01F8, 0, 0x07F4, 2, 0) +MX6_PAD_DECL(KEY_COL0__ENET_RX_DATA3, 0x05C8, 0x01F8, 1, 0x0854, 1, 0) +MX6_PAD_DECL(KEY_COL0__AUD5_TXC, 0x05C8, 0x01F8, 2, 0x07DC, 1, 0) +MX6_PAD_DECL(KEY_COL0__KEY_COL0, 0x05C8, 0x01F8, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__UART4_TX_DATA, 0x05C8, 0x01F8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__UART4_RX_DATA, 0x05C8, 0x01F8, 4, 0x0938, 0, 0) +MX6_PAD_DECL(KEY_COL0__GPIO4_IO06, 0x05C8, 0x01F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__DCIC1_OUT, 0x05C8, 0x01F8, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__ECSPI1_MOSI, 0x05CC, 0x01FC, 0, 0x07FC, 2, 0) +MX6_PAD_DECL(KEY_ROW0__ENET_TX_DATA3, 0x05CC, 0x01FC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__AUD5_TXD, 0x05CC, 0x01FC, 2, 0x07D0, 1, 0) +MX6_PAD_DECL(KEY_ROW0__KEY_ROW0, 0x05CC, 0x01FC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__UART4_TX_DATA, 0x05CC, 0x01FC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__UART4_RX_DATA, 0x05CC, 0x01FC, 4, 0x0938, 1, 0) +MX6_PAD_DECL(KEY_ROW0__GPIO4_IO07, 0x05CC, 0x01FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__DCIC2_OUT, 0x05CC, 0x01FC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__ECSPI1_MISO, 0x05D0, 0x0200, 0, 0x07F8, 2, 0) +MX6_PAD_DECL(KEY_COL1__ENET_MDIO, 0x05D0, 0x0200, 1, 0x0840, 1, 0) +MX6_PAD_DECL(KEY_COL1__AUD5_TXFS, 0x05D0, 0x0200, 2, 0x07E0, 1, 0) +MX6_PAD_DECL(KEY_COL1__KEY_COL1, 0x05D0, 0x0200, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__UART5_TX_DATA, 0x05D0, 0x0200, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__UART5_RX_DATA, 0x05D0, 0x0200, 4, 0x0940, 0, 0) +MX6_PAD_DECL(KEY_COL1__GPIO4_IO08, 0x05D0, 0x0200, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__SD1_VSELECT, 0x05D0, 0x0200, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__ECSPI1_SS0, 0x05D4, 0x0204, 0, 0x0800, 2, 0) +MX6_PAD_DECL(KEY_ROW1__ENET_COL, 0x05D4, 0x0204, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__AUD5_RXD, 0x05D4, 0x0204, 2, 0x07CC, 1, 0) +MX6_PAD_DECL(KEY_ROW1__KEY_ROW1, 0x05D4, 0x0204, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__UART5_TX_DATA, 0x05D4, 0x0204, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__UART5_RX_DATA, 0x05D4, 0x0204, 4, 0x0940, 1, 0) +MX6_PAD_DECL(KEY_ROW1__GPIO4_IO09, 0x05D4, 0x0204, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__SD2_VSELECT, 0x05D4, 0x0204, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__ECSPI1_SS1, 0x05D8, 0x0208, 0, 0x0804, 2, 0) +MX6_PAD_DECL(KEY_COL2__ENET_RX_DATA2, 0x05D8, 0x0208, 1, 0x0850, 1, 0) +MX6_PAD_DECL(KEY_COL2__FLEXCAN1_TX, 0x05D8, 0x0208, 2, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__KEY_COL2, 0x05D8, 0x0208, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__ENET_MDC, 0x05D8, 0x0208, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__GPIO4_IO10, 0x05D8, 0x0208, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__USB_H1_PWR_CTL_WAKE, 0x05D8, 0x0208, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__ECSPI1_SS2, 0x05DC, 0x020C, 0, 0x0808, 1, 0) +MX6_PAD_DECL(KEY_ROW2__ENET_TX_DATA2, 0x05DC, 0x020C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__FLEXCAN1_RX, 0x05DC, 0x020C, 2, 0x07E4, 0, 0) +MX6_PAD_DECL(KEY_ROW2__KEY_ROW2, 0x05DC, 0x020C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__SD2_VSELECT, 0x05DC, 0x020C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__GPIO4_IO11, 0x05DC, 0x020C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__HDMI_TX_CEC_LINE, 0x05DC, 0x020C, 6, 0x088C, 1, 0) +MX6_PAD_DECL(KEY_COL3__ECSPI1_SS3, 0x05E0, 0x0210, 0, 0x080C, 1, 0) +MX6_PAD_DECL(KEY_COL3__ENET_CRS, 0x05E0, 0x0210, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__HDMI_TX_DDC_SCL, 0x05E0, 0x0210, 2, 0x0890, 1, 0) +MX6_PAD_DECL(KEY_COL3__KEY_COL3, 0x05E0, 0x0210, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__I2C2_SCL, 0x05E0, 0x0210, 20, 0x08A0, 1, 0) +MX6_PAD_DECL(KEY_COL3__GPIO4_IO12, 0x05E0, 0x0210, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__SPDIF_IN, 0x05E0, 0x0210, 6, 0x0914, 2, 0) +MX6_PAD_DECL(KEY_ROW3__ASRC_EXT_CLK, 0x05E4, 0x0214, 1, 0x07B0, 0, 0) +MX6_PAD_DECL(KEY_ROW3__HDMI_TX_DDC_SDA, 0x05E4, 0x0214, 2, 0x0894, 1, 0) +MX6_PAD_DECL(KEY_ROW3__KEY_ROW3, 0x05E4, 0x0214, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW3__I2C2_SDA, 0x05E4, 0x0214, 20, 0x08A4, 1, 0) +MX6_PAD_DECL(KEY_ROW3__GPIO4_IO13, 0x05E4, 0x0214, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW3__SD1_VSELECT, 0x05E4, 0x0214, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__FLEXCAN2_TX, 0x05E8, 0x0218, 0, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__IPU1_SISG4, 0x05E8, 0x0218, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__USB_OTG_OC, 0x05E8, 0x0218, 2, 0x0944, 1, 0) +MX6_PAD_DECL(KEY_COL4__KEY_COL4, 0x05E8, 0x0218, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__UART5_CTS_B, 0x05E8, 0x0218, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__UART5_RTS_B, 0x05E8, 0x0218, 4, 0x093C, 0, 0) +MX6_PAD_DECL(KEY_COL4__GPIO4_IO14, 0x05E8, 0x0218, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__FLEXCAN2_RX, 0x05EC, 0x021C, 0, 0x07E8, 0, 0) +MX6_PAD_DECL(KEY_ROW4__IPU1_SISG5, 0x05EC, 0x021C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__USB_OTG_PWR, 0x05EC, 0x021C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__KEY_ROW4, 0x05EC, 0x021C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__UART5_CTS_B, 0x05EC, 0x021C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__UART5_RTS_B, 0x05EC, 0x021C, 4, 0x093C, 1, 0) +MX6_PAD_DECL(KEY_ROW4__GPIO4_IO15, 0x05EC, 0x021C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__CCM_CLKO1, 0x05F0, 0x0220, 0, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__KEY_COL5, 0x05F0, 0x0220, 2, 0x08E8, 0, 0) +MX6_PAD_DECL(GPIO_0__ASRC_EXT_CLK, 0x05F0, 0x0220, 3, 0x07B0, 1, 0) +MX6_PAD_DECL(GPIO_0__EPIT1_OUT, 0x05F0, 0x0220, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__GPIO1_IO00, 0x05F0, 0x0220, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__USB_H1_PWR, 0x05F0, 0x0220, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__SNVS_VIO_5, 0x05F0, 0x0220, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__ESAI_RX_CLK, 0x05F4, 0x0224, 0, 0x086C, 1, 0) +MX6_PAD_DECL(GPIO_1__WDOG2_B, 0x05F4, 0x0224, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__KEY_ROW5, 0x05F4, 0x0224, 2, 0x08F4, 0, 0) +MX6_PAD_DECL(GPIO_1__USB_OTG_ID, 0x05F4, 0x0224, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__PWM2_OUT, 0x05F4, 0x0224, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__GPIO1_IO01, 0x05F4, 0x0224, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__SD1_CD_B, 0x05F4, 0x0224, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__ESAI_RX_FS, 0x05F8, 0x0228, 0, 0x085C, 1, 0) +MX6_PAD_DECL(GPIO_9__WDOG1_B, 0x05F8, 0x0228, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__KEY_COL6, 0x05F8, 0x0228, 2, 0x08EC, 0, 0) +MX6_PAD_DECL(GPIO_9__CCM_REF_EN_B, 0x05F8, 0x0228, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__PWM1_OUT, 0x05F8, 0x0228, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__GPIO1_IO09, 0x05F8, 0x0228, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__SD1_WP, 0x05F8, 0x0228, 6, 0x094C, 1, 0) +MX6_PAD_DECL(GPIO_3__ESAI_RX_HF_CLK, 0x05FC, 0x022C, 0, 0x0864, 1, 0) +MX6_PAD_DECL(GPIO_3__I2C3_SCL, 0x05FC, 0x022C, 18, 0x08A8, 1, 0) +MX6_PAD_DECL(GPIO_3__XTALOSC_REF_CLK_24M, 0x05FC, 0x022C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__CCM_CLKO2, 0x05FC, 0x022C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__GPIO1_IO03, 0x05FC, 0x022C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__USB_H1_OC, 0x05FC, 0x022C, 6, 0x0948, 1, 0) +MX6_PAD_DECL(GPIO_3__MLB_CLK, 0x05FC, 0x022C, 7, 0x0900, 1, 0) +MX6_PAD_DECL(GPIO_6__ESAI_TX_CLK, 0x0600, 0x0230, 0, 0x0870, 1, 0) +MX6_PAD_DECL(GPIO_6__I2C3_SDA, 0x0600, 0x0230, 18, 0x08AC, 1, 0) +MX6_PAD_DECL(GPIO_6__GPIO1_IO06, 0x0600, 0x0230, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__SD2_LCTL, 0x0600, 0x0230, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__MLB_SIG, 0x0600, 0x0230, 7, 0x0908, 1, 0) +MX6_PAD_DECL(GPIO_2__ESAI_TX_FS, 0x0604, 0x0234, 0, 0x0860, 1, 0) +MX6_PAD_DECL(GPIO_2__KEY_ROW6, 0x0604, 0x0234, 2, 0x08F8, 1, 0) +MX6_PAD_DECL(GPIO_2__GPIO1_IO02, 0x0604, 0x0234, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__SD2_WP, 0x0604, 0x0234, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__MLB_DATA, 0x0604, 0x0234, 7, 0x0904, 1, 0) +MX6_PAD_DECL(GPIO_4__ESAI_TX_HF_CLK, 0x0608, 0x0238, 0, 0x0868, 1, 0) +MX6_PAD_DECL(GPIO_4__KEY_COL7, 0x0608, 0x0238, 2, 0x08F0, 1, 0) +MX6_PAD_DECL(GPIO_4__GPIO1_IO04, 0x0608, 0x0238, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_4__SD2_CD_B, 0x0608, 0x0238, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__ESAI_TX2_RX3, 0x060C, 0x023C, 0, 0x087C, 1, 0) +MX6_PAD_DECL(GPIO_5__KEY_ROW7, 0x060C, 0x023C, 2, 0x08FC, 1, 0) +MX6_PAD_DECL(GPIO_5__CCM_CLKO1, 0x060C, 0x023C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__GPIO1_IO05, 0x060C, 0x023C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__I2C3_SCL, 0x060C, 0x023C, 22, 0x08A8, 2, 0) +MX6_PAD_DECL(GPIO_5__ARM_EVENTI, 0x060C, 0x023C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__ESAI_TX4_RX1, 0x0610, 0x0240, 0, 0x0884, 1, 0) +MX6_PAD_DECL(GPIO_7__ECSPI5_RDY, 0x0610, 0x0240, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__EPIT1_OUT, 0x0610, 0x0240, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__FLEXCAN1_TX, 0x0610, 0x0240, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__UART2_TX_DATA, 0x0610, 0x0240, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__UART2_RX_DATA, 0x0610, 0x0240, 4, 0x0928, 2, 0) +MX6_PAD_DECL(GPIO_7__GPIO1_IO07, 0x0610, 0x0240, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__SPDIF_LOCK, 0x0610, 0x0240, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__USB_OTG_HOST_MODE, 0x0610, 0x0240, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__ESAI_TX5_RX0, 0x0614, 0x0244, 0, 0x0888, 1, 0) +MX6_PAD_DECL(GPIO_8__XTALOSC_REF_CLK_32K, 0x0614, 0x0244, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__EPIT2_OUT, 0x0614, 0x0244, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__FLEXCAN1_RX, 0x0614, 0x0244, 3, 0x07E4, 1, 0) +MX6_PAD_DECL(GPIO_8__UART2_TX_DATA, 0x0614, 0x0244, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__UART2_RX_DATA, 0x0614, 0x0244, 4, 0x0928, 3, 0) +MX6_PAD_DECL(GPIO_8__GPIO1_IO08, 0x0614, 0x0244, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK, 0x0614, 0x0244, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE, 0x0614, 0x0244, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2, 0x0618, 0x0248, 0, 0x0880, 1, 0) +MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x0618, 0x0248, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x0618, 0x0248, 2, 0x083C, 1, 0) +MX6_PAD_DECL(GPIO_16__SD1_LCTL, 0x0618, 0x0248, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__SPDIF_IN, 0x0618, 0x0248, 4, 0x0914, 3, 0) +MX6_PAD_DECL(GPIO_16__GPIO7_IO11, 0x0618, 0x0248, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__I2C3_SDA, 0x0618, 0x0248, 22, 0x08AC, 2, 0) +MX6_PAD_DECL(GPIO_16__JTAG_DE_B, 0x0618, 0x0248, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__ESAI_TX0, 0x061C, 0x024C, 0, 0x0874, 0, 0) +MX6_PAD_DECL(GPIO_17__ENET_1588_EVENT3_IN, 0x061C, 0x024C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__CCM_PMIC_READY, 0x061C, 0x024C, 2, 0x07F0, 1, 0) +MX6_PAD_DECL(GPIO_17__SDMA_EXT_EVENT0, 0x061C, 0x024C, 3, 0x090C, 1, 0) +MX6_PAD_DECL(GPIO_17__SPDIF_OUT, 0x061C, 0x024C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__GPIO7_IO12, 0x061C, 0x024C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__ESAI_TX1, 0x0620, 0x0250, 0, 0x0878, 0, 0) +MX6_PAD_DECL(GPIO_18__ENET_RX_CLK, 0x0620, 0x0250, 1, 0x0844, 1, 0) +MX6_PAD_DECL(GPIO_18__SD3_VSELECT, 0x0620, 0x0250, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__SDMA_EXT_EVENT1, 0x0620, 0x0250, 3, 0x0910, 1, 0) +MX6_PAD_DECL(GPIO_18__ASRC_EXT_CLK, 0x0620, 0x0250, 4, 0x07B0, 2, 0) +MX6_PAD_DECL(GPIO_18__GPIO7_IO13, 0x0620, 0x0250, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__SNVS_VIO_5_CTL, 0x0620, 0x0250, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__KEY_COL5, 0x0624, 0x0254, 0, 0x08E8, 1, 0) +MX6_PAD_DECL(GPIO_19__ENET_1588_EVENT0_OUT, 0x0624, 0x0254, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__SPDIF_OUT, 0x0624, 0x0254, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__CCM_CLKO1, 0x0624, 0x0254, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__ECSPI1_RDY, 0x0624, 0x0254, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__GPIO4_IO05, 0x0624, 0x0254, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__ENET_TX_ER, 0x0624, 0x0254, 6, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK, 0x0628, 0x0258, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__GPIO5_IO18, 0x0628, 0x0258, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__ARM_EVENTO, 0x0628, 0x0258, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__IPU1_CSI0_HSYNC, 0x062C, 0x025C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__CCM_CLKO1, 0x062C, 0x025C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__GPIO5_IO19, 0x062C, 0x025C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__ARM_TRACE_CTL, 0x062C, 0x025C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__IPU1_CSI0_DATA_EN, 0x0630, 0x0260, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__EIM_DATA00, 0x0630, 0x0260, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__GPIO5_IO20, 0x0630, 0x0260, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__ARM_TRACE_CLK, 0x0630, 0x0260, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__IPU1_CSI0_VSYNC, 0x0634, 0x0264, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__EIM_DATA01, 0x0634, 0x0264, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__GPIO5_IO21, 0x0634, 0x0264, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__ARM_TRACE00, 0x0634, 0x0264, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__IPU1_CSI0_DATA04, 0x0638, 0x0268, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__EIM_DATA02, 0x0638, 0x0268, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__ECSPI1_SCLK, 0x0638, 0x0268, 2, 0x07F4, 3, 0) +MX6_PAD_DECL(CSI0_DAT4__KEY_COL5, 0x0638, 0x0268, 3, 0x08E8, 2, 0) +MX6_PAD_DECL(CSI0_DAT4__AUD3_TXC, 0x0638, 0x0268, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__GPIO5_IO22, 0x0638, 0x0268, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__ARM_TRACE01, 0x0638, 0x0268, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__IPU1_CSI0_DATA05, 0x063C, 0x026C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__EIM_DATA03, 0x063C, 0x026C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__ECSPI1_MOSI, 0x063C, 0x026C, 2, 0x07FC, 3, 0) +MX6_PAD_DECL(CSI0_DAT5__KEY_ROW5, 0x063C, 0x026C, 3, 0x08F4, 1, 0) +MX6_PAD_DECL(CSI0_DAT5__AUD3_TXD, 0x063C, 0x026C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__GPIO5_IO23, 0x063C, 0x026C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__ARM_TRACE02, 0x063C, 0x026C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__IPU1_CSI0_DATA06, 0x0640, 0x0270, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__EIM_DATA04, 0x0640, 0x0270, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__ECSPI1_MISO, 0x0640, 0x0270, 2, 0x07F8, 3, 0) +MX6_PAD_DECL(CSI0_DAT6__KEY_COL6, 0x0640, 0x0270, 3, 0x08EC, 1, 0) +MX6_PAD_DECL(CSI0_DAT6__AUD3_TXFS, 0x0640, 0x0270, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__GPIO5_IO24, 0x0640, 0x0270, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__ARM_TRACE03, 0x0640, 0x0270, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__IPU1_CSI0_DATA07, 0x0644, 0x0274, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__EIM_DATA05, 0x0644, 0x0274, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__ECSPI1_SS0, 0x0644, 0x0274, 2, 0x0800, 3, 0) +MX6_PAD_DECL(CSI0_DAT7__KEY_ROW6, 0x0644, 0x0274, 3, 0x08F8, 2, 0) +MX6_PAD_DECL(CSI0_DAT7__AUD3_RXD, 0x0644, 0x0274, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__GPIO5_IO25, 0x0644, 0x0274, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__ARM_TRACE04, 0x0644, 0x0274, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__IPU1_CSI0_DATA08, 0x0648, 0x0278, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__EIM_DATA06, 0x0648, 0x0278, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__ECSPI2_SCLK, 0x0648, 0x0278, 2, 0x0810, 2, 0) +MX6_PAD_DECL(CSI0_DAT8__KEY_COL7, 0x0648, 0x0278, 3, 0x08F0, 2, 0) +MX6_PAD_DECL(CSI0_DAT8__I2C1_SDA, 0x0648, 0x0278, 20, 0x089C, 1, 0) +MX6_PAD_DECL(CSI0_DAT8__GPIO5_IO26, 0x0648, 0x0278, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__ARM_TRACE05, 0x0648, 0x0278, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__IPU1_CSI0_DATA09, 0x064C, 0x027C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__EIM_DATA07, 0x064C, 0x027C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__ECSPI2_MOSI, 0x064C, 0x027C, 2, 0x0818, 2, 0) +MX6_PAD_DECL(CSI0_DAT9__KEY_ROW7, 0x064C, 0x027C, 3, 0x08FC, 2, 0) +MX6_PAD_DECL(CSI0_DAT9__I2C1_SCL, 0x064C, 0x027C, 20, 0x0898, 1, 0) +MX6_PAD_DECL(CSI0_DAT9__GPIO5_IO27, 0x064C, 0x027C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__ARM_TRACE06, 0x064C, 0x027C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__IPU1_CSI0_DATA10, 0x0650, 0x0280, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__AUD3_RXC, 0x0650, 0x0280, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__ECSPI2_MISO, 0x0650, 0x0280, 2, 0x0814, 2, 0) +MX6_PAD_DECL(CSI0_DAT10__UART1_TX_DATA, 0x0650, 0x0280, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__UART1_RX_DATA, 0x0650, 0x0280, 3, 0x0920, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__GPIO5_IO28, 0x0650, 0x0280, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__ARM_TRACE07, 0x0650, 0x0280, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__IPU1_CSI0_DATA11, 0x0654, 0x0284, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__AUD3_RXFS, 0x0654, 0x0284, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__ECSPI2_SS0, 0x0654, 0x0284, 2, 0x081C, 2, 0) +MX6_PAD_DECL(CSI0_DAT11__UART1_TX_DATA, 0x0654, 0x0284, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__UART1_RX_DATA, 0x0654, 0x0284, 3, 0x0920, 1, 0) +MX6_PAD_DECL(CSI0_DAT11__GPIO5_IO29, 0x0654, 0x0284, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__ARM_TRACE08, 0x0654, 0x0284, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__IPU1_CSI0_DATA12, 0x0658, 0x0288, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__EIM_DATA08, 0x0658, 0x0288, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__UART4_TX_DATA, 0x0658, 0x0288, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__UART4_RX_DATA, 0x0658, 0x0288, 3, 0x0938, 2, 0) +MX6_PAD_DECL(CSI0_DAT12__GPIO5_IO30, 0x0658, 0x0288, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__ARM_TRACE09, 0x0658, 0x0288, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__IPU1_CSI0_DATA13, 0x065C, 0x028C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__EIM_DATA09, 0x065C, 0x028C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__UART4_TX_DATA, 0x065C, 0x028C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__UART4_RX_DATA, 0x065C, 0x028C, 3, 0x0938, 3, 0) +MX6_PAD_DECL(CSI0_DAT13__GPIO5_IO31, 0x065C, 0x028C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__ARM_TRACE10, 0x065C, 0x028C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__IPU1_CSI0_DATA14, 0x0660, 0x0290, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__EIM_DATA10, 0x0660, 0x0290, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__UART5_TX_DATA, 0x0660, 0x0290, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__UART5_RX_DATA, 0x0660, 0x0290, 3, 0x0940, 2, 0) +MX6_PAD_DECL(CSI0_DAT14__GPIO6_IO00, 0x0660, 0x0290, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__ARM_TRACE11, 0x0660, 0x0290, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__IPU1_CSI0_DATA15, 0x0664, 0x0294, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__EIM_DATA11, 0x0664, 0x0294, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__UART5_TX_DATA, 0x0664, 0x0294, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__UART5_RX_DATA, 0x0664, 0x0294, 3, 0x0940, 3, 0) +MX6_PAD_DECL(CSI0_DAT15__GPIO6_IO01, 0x0664, 0x0294, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__ARM_TRACE12, 0x0664, 0x0294, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__IPU1_CSI0_DATA16, 0x0668, 0x0298, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__EIM_DATA12, 0x0668, 0x0298, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__UART4_CTS_B, 0x0668, 0x0298, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__UART4_RTS_B, 0x0668, 0x0298, 3, 0x0934, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__GPIO6_IO02, 0x0668, 0x0298, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__ARM_TRACE13, 0x0668, 0x0298, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__IPU1_CSI0_DATA17, 0x066C, 0x029C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__EIM_DATA13, 0x066C, 0x029C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__UART4_CTS_B, 0x066C, 0x029C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__UART4_RTS_B, 0x066C, 0x029C, 3, 0x0934, 1, 0) +MX6_PAD_DECL(CSI0_DAT17__GPIO6_IO03, 0x066C, 0x029C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__ARM_TRACE14, 0x066C, 0x029C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__IPU1_CSI0_DATA18, 0x0670, 0x02A0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__EIM_DATA14, 0x0670, 0x02A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__UART5_CTS_B, 0x0670, 0x02A0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__UART5_RTS_B, 0x0670, 0x02A0, 3, 0x093C, 2, 0) +MX6_PAD_DECL(CSI0_DAT18__GPIO6_IO04, 0x0670, 0x02A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__ARM_TRACE15, 0x0670, 0x02A0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__IPU1_CSI0_DATA19, 0x0674, 0x02A4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__EIM_DATA15, 0x0674, 0x02A4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__UART5_CTS_B, 0x0674, 0x02A4, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__UART5_RTS_B, 0x0674, 0x02A4, 3, 0x093C, 3, 0) +MX6_PAD_DECL(CSI0_DAT19__GPIO6_IO05, 0x0674, 0x02A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__SD3_DATA7, 0x0690, 0x02A8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__UART1_TX_DATA, 0x0690, 0x02A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__UART1_RX_DATA, 0x0690, 0x02A8, 1, 0x0920, 2, 0) +MX6_PAD_DECL(SD3_DAT7__GPIO6_IO17, 0x0690, 0x02A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__SD3_DATA6, 0x0694, 0x02AC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__UART1_TX_DATA, 0x0694, 0x02AC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__UART1_RX_DATA, 0x0694, 0x02AC, 1, 0x0920, 3, 0) +MX6_PAD_DECL(SD3_DAT6__GPIO6_IO18, 0x0694, 0x02AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__SD3_DATA5, 0x0698, 0x02B0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__UART2_TX_DATA, 0x0698, 0x02B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__UART2_RX_DATA, 0x0698, 0x02B0, 1, 0x0928, 4, 0) +MX6_PAD_DECL(SD3_DAT5__GPIO7_IO00, 0x0698, 0x02B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__SD3_DATA4, 0x069C, 0x02B4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA, 0x069C, 0x02B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA, 0x069C, 0x02B4, 1, 0x0928, 5, 0) +MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01, 0x069C, 0x02B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06A0, 0x02B8, 16, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__UART2_CTS_B, 0x06A0, 0x02B8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__UART2_RTS_B, 0x06A0, 0x02B8, 1, 0x0924, 2, 0) +MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX, 0x06A0, 0x02B8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__GPIO7_IO02, 0x06A0, 0x02B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__SD3_CLK, 0x06A4, 0x02BC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__UART2_CTS_B, 0x06A4, 0x02BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__UART2_RTS_B, 0x06A4, 0x02BC, 1, 0x0924, 3, 0) +MX6_PAD_DECL(SD3_CLK__FLEXCAN1_RX, 0x06A4, 0x02BC, 2, 0x07E4, 2, 0) +MX6_PAD_DECL(SD3_CLK__GPIO7_IO03, 0x06A4, 0x02BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__SD3_DATA0, 0x06A8, 0x02C0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__UART1_CTS_B, 0x06A8, 0x02C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__UART1_RTS_B, 0x06A8, 0x02C0, 1, 0x091C, 2, 0) +MX6_PAD_DECL(SD3_DAT0__FLEXCAN2_TX, 0x06A8, 0x02C0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__GPIO7_IO04, 0x06A8, 0x02C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__SD3_DATA1, 0x06AC, 0x02C4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__UART1_CTS_B, 0x06AC, 0x02C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__UART1_RTS_B, 0x06AC, 0x02C4, 1, 0x091C, 3, 0) +MX6_PAD_DECL(SD3_DAT1__FLEXCAN2_RX, 0x06AC, 0x02C4, 2, 0x07E8, 1, 0) +MX6_PAD_DECL(SD3_DAT1__GPIO7_IO05, 0x06AC, 0x02C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT2__SD3_DATA2, 0x06B0, 0x02C8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT2__GPIO7_IO06, 0x06B0, 0x02C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__SD3_DATA3, 0x06B4, 0x02CC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__UART3_CTS_B, 0x06B4, 0x02CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__UART3_RTS_B, 0x06B4, 0x02CC, 1, 0x092C, 4, 0) +MX6_PAD_DECL(SD3_DAT3__GPIO7_IO07, 0x06B4, 0x02CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__SD3_RESET, 0x06B8, 0x02D0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__UART3_CTS_B, 0x06B8, 0x02D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__UART3_RTS_B, 0x06B8, 0x02D0, 1, 0x092C, 5, 0) +MX6_PAD_DECL(SD3_RST__GPIO7_IO08, 0x06B8, 0x02D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__NAND_CLE, 0x06BC, 0x02D4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__IPU2_SISG4, 0x06BC, 0x02D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__GPIO6_IO07, 0x06BC, 0x02D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__NAND_ALE, 0x06C0, 0x02D8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__SD4_RESET, 0x06C0, 0x02D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__GPIO6_IO08, 0x06C0, 0x02D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__NAND_WP_B, 0x06C4, 0x02DC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__IPU2_SISG5, 0x06C4, 0x02DC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__GPIO6_IO09, 0x06C4, 0x02DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__NAND_READY_B, 0x06C8, 0x02E0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__IPU2_DI0_PIN01, 0x06C8, 0x02E0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__GPIO6_IO10, 0x06C8, 0x02E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS0__NAND_CE0_B, 0x06CC, 0x02E4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS0__GPIO6_IO11, 0x06CC, 0x02E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__NAND_CE1_B, 0x06D0, 0x02E8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__SD4_VSELECT, 0x06D0, 0x02E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__SD3_VSELECT, 0x06D0, 0x02E8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__GPIO6_IO14, 0x06D0, 0x02E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__NAND_CE2_B, 0x06D4, 0x02EC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__IPU1_SISG0, 0x06D4, 0x02EC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__ESAI_TX0, 0x06D4, 0x02EC, 2, 0x0874, 1, 0) +MX6_PAD_DECL(NANDF_CS2__EIM_CRE, 0x06D4, 0x02EC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__CCM_CLKO2, 0x06D4, 0x02EC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__GPIO6_IO15, 0x06D4, 0x02EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__IPU2_SISG0, 0x06D4, 0x02EC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__NAND_CE3_B, 0x06D8, 0x02F0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__IPU1_SISG1, 0x06D8, 0x02F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__ESAI_TX1, 0x06D8, 0x02F0, 2, 0x0878, 1, 0) +MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26, 0x06D8, 0x02F0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16, 0x06D8, 0x02F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__IPU2_SISG1, 0x06D8, 0x02F0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x06DC, 0x02F4, 16, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__NAND_RE_B, 0x06DC, 0x02F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA, 0x06DC, 0x02F4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA, 0x06DC, 0x02F4, 2, 0x0930, 2, 0) +MX6_PAD_DECL(SD4_CMD__GPIO7_IO09, 0x06DC, 0x02F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__SD4_CLK, 0x06E0, 0x02F8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__NAND_WE_B, 0x06E0, 0x02F8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__UART3_TX_DATA, 0x06E0, 0x02F8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__UART3_RX_DATA, 0x06E0, 0x02F8, 2, 0x0930, 3, 0) +MX6_PAD_DECL(SD4_CLK__GPIO7_IO10, 0x06E0, 0x02F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__NAND_DATA00, 0x06E4, 0x02FC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__SD1_DATA4, 0x06E4, 0x02FC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__GPIO2_IO00, 0x06E4, 0x02FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__NAND_DATA01, 0x06E8, 0x0300, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__SD1_DATA5, 0x06E8, 0x0300, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__GPIO2_IO01, 0x06E8, 0x0300, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__NAND_DATA02, 0x06EC, 0x0304, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__SD1_DATA6, 0x06EC, 0x0304, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__GPIO2_IO02, 0x06EC, 0x0304, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__NAND_DATA03, 0x06F0, 0x0308, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__SD1_DATA7, 0x06F0, 0x0308, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__GPIO2_IO03, 0x06F0, 0x0308, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__NAND_DATA04, 0x06F4, 0x030C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__SD2_DATA4, 0x06F4, 0x030C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__GPIO2_IO04, 0x06F4, 0x030C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__NAND_DATA05, 0x06F8, 0x0310, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__SD2_DATA5, 0x06F8, 0x0310, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__GPIO2_IO05, 0x06F8, 0x0310, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__NAND_DATA06, 0x06FC, 0x0314, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__SD2_DATA6, 0x06FC, 0x0314, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__GPIO2_IO06, 0x06FC, 0x0314, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__NAND_DATA07, 0x0700, 0x0318, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__SD2_DATA7, 0x0700, 0x0318, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__GPIO2_IO07, 0x0700, 0x0318, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__SD4_DATA0, 0x0704, 0x031C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__NAND_DQS, 0x0704, 0x031C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__GPIO2_IO08, 0x0704, 0x031C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__SD4_DATA1, 0x0708, 0x0320, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__PWM3_OUT, 0x0708, 0x0320, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__GPIO2_IO09, 0x0708, 0x0320, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__SD4_DATA2, 0x070C, 0x0324, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__PWM4_OUT, 0x070C, 0x0324, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__GPIO2_IO10, 0x070C, 0x0324, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT3__SD4_DATA3, 0x0710, 0x0328, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT3__GPIO2_IO11, 0x0710, 0x0328, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__SD4_DATA4, 0x0714, 0x032C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__UART2_TX_DATA, 0x0714, 0x032C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__UART2_RX_DATA, 0x0714, 0x032C, 2, 0x0928, 6, 0) +MX6_PAD_DECL(SD4_DAT4__GPIO2_IO12, 0x0714, 0x032C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__SD4_DATA5, 0x0718, 0x0330, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__UART2_CTS_B, 0x0718, 0x0330, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__UART2_RTS_B, 0x0718, 0x0330, 2, 0x0924, 4, 0) +MX6_PAD_DECL(SD4_DAT5__GPIO2_IO13, 0x0718, 0x0330, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__SD4_DATA6, 0x071C, 0x0334, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__UART2_CTS_B, 0x071C, 0x0334, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__UART2_RTS_B, 0x071C, 0x0334, 2, 0x0924, 5, 0) +MX6_PAD_DECL(SD4_DAT6__GPIO2_IO14, 0x071C, 0x0334, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__SD4_DATA7, 0x0720, 0x0338, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__UART2_TX_DATA, 0x0720, 0x0338, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__UART2_RX_DATA, 0x0720, 0x0338, 2, 0x0928, 7, 0) +MX6_PAD_DECL(SD4_DAT7__GPIO2_IO15, 0x0720, 0x0338, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__SD1_DATA1, 0x0724, 0x033C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__ECSPI5_SS0, 0x0724, 0x033C, 1, 0x0834, 1, 0) +MX6_PAD_DECL(SD1_DAT1__PWM3_OUT, 0x0724, 0x033C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__GPT_CAPTURE2, 0x0724, 0x033C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__GPIO1_IO17, 0x0724, 0x033C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__SD1_DATA0, 0x0728, 0x0340, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__ECSPI5_MISO, 0x0728, 0x0340, 1, 0x082C, 1, 0) +MX6_PAD_DECL(SD1_DAT0__GPT_CAPTURE1, 0x0728, 0x0340, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__GPIO1_IO16, 0x0728, 0x0340, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__SD1_DATA3, 0x072C, 0x0344, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__ECSPI5_SS2, 0x072C, 0x0344, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__GPT_COMPARE3, 0x072C, 0x0344, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__PWM1_OUT, 0x072C, 0x0344, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__WDOG2_B, 0x072C, 0x0344, 4, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21, 0x072C, 0x0344, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB, 0x072C, 0x0344, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x0730, 0x0348, 16, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__ECSPI5_MOSI, 0x0730, 0x0348, 1, 0x0830, 0, 0) +MX6_PAD_DECL(SD1_CMD__PWM4_OUT, 0x0730, 0x0348, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1, 0x0730, 0x0348, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__GPIO1_IO18, 0x0730, 0x0348, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__SD1_DATA2, 0x0734, 0x034C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__ECSPI5_SS1, 0x0734, 0x034C, 1, 0x0838, 1, 0) +MX6_PAD_DECL(SD1_DAT2__GPT_COMPARE2, 0x0734, 0x034C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__PWM2_OUT, 0x0734, 0x034C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__WDOG1_B, 0x0734, 0x034C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__GPIO1_IO19, 0x0734, 0x034C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__WDOG1_RESET_B_DEB, 0x0734, 0x034C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__SD1_CLK, 0x0738, 0x0350, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__ECSPI5_SCLK, 0x0738, 0x0350, 1, 0x0828, 0, 0) +MX6_PAD_DECL(SD1_CLK__GPT_CLKIN, 0x0738, 0x0350, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__GPIO1_IO20, 0x0738, 0x0350, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CLK__SD2_CLK, 0x073C, 0x0354, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CLK__ECSPI5_SCLK, 0x073C, 0x0354, 1, 0x0828, 1, 0) +MX6_PAD_DECL(SD2_CLK__KEY_COL5, 0x073C, 0x0354, 2, 0x08E8, 3, 0) +MX6_PAD_DECL(SD2_CLK__AUD4_RXFS, 0x073C, 0x0354, 3, 0x07C0, 1, 0) +MX6_PAD_DECL(SD2_CLK__GPIO1_IO10, 0x073C, 0x0354, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x0740, 0x0358, 16, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CMD__ECSPI5_MOSI, 0x0740, 0x0358, 1, 0x0830, 1, 0) +MX6_PAD_DECL(SD2_CMD__KEY_ROW5, 0x0740, 0x0358, 2, 0x08F4, 2, 0) +MX6_PAD_DECL(SD2_CMD__AUD4_RXC, 0x0740, 0x0358, 3, 0x07BC, 1, 0) +MX6_PAD_DECL(SD2_CMD__GPIO1_IO11, 0x0740, 0x0358, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__SD2_DATA3, 0x0744, 0x035C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__ECSPI5_SS3, 0x0744, 0x035C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__KEY_COL6, 0x0744, 0x035C, 2, 0x08EC, 2, 0) +MX6_PAD_DECL(SD2_DAT3__AUD4_TXC, 0x0744, 0x035C, 3, 0x07C4, 1, 0) +MX6_PAD_DECL(SD2_DAT3__GPIO1_IO12, 0x0744, 0x035C, 5, 0x0000, 0, 0) #endif /* __ASM_ARCH_MX6_MX6Q_PINS_H__ */ diff --git a/board/barco/titanium/titanium.c b/board/barco/titanium/titanium.c index c3775ef7b3b..6db44882fe1 100644 --- a/board/barco/titanium/titanium.c +++ b/board/barco/titanium/titanium.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index 1b4791c8a41..e0634078407 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 1cf649ceeb0..fc75eae565c 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include -- cgit v1.3.1 From 8d7b3638e97bb1393b4ecf835efead38ea5c1a34 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Tue, 17 Dec 2013 17:34:43 +0800 Subject: arm: atmel: at91sam9x5: cleanup cs configure for spi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As the cs for spi is worked in gpio mode, so no need to configure it as peripheral and then configure to gpio. Configure it to gpio directly. Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann --- board/atmel/at91sam9x5ek/at91sam9x5ek.c | 1 - 1 file changed, 1 deletion(-) (limited to 'board') diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 6f67c34a538..17a2a40b4b3 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -271,7 +271,6 @@ int board_init(void) #endif #ifdef CONFIG_ATMEL_SPI - at91_spi0_hw_init(1 << 0); at91_spi0_hw_init(1 << 4); #endif -- cgit v1.3.1 From 164d98466103a46b7c881149e92ec2a28a6375be Mon Sep 17 00:00:00 2001 From: Giuseppe Pagano Date: Thu, 28 Nov 2013 12:32:48 +0100 Subject: nitrogen6x: Move setup_sata to common part Move setup_sata function definition from platform file nitrogen6x.c to arch/arm/imx-common/sata.c to avoid code duplication. Signed-off-by: Giuseppe Pagano CC: Stefano Babic CC: Fabio Estevam CC: Eric Nelson --- arch/arm/imx-common/Makefile | 3 +++ arch/arm/imx-common/sata.c | 33 +++++++++++++++++++++++++++++++++ arch/arm/include/asm/imx-common/sata.h | 16 ++++++++++++++++ board/boundary/nitrogen6x/nitrogen6x.c | 27 +-------------------------- 4 files changed, 53 insertions(+), 26 deletions(-) create mode 100644 arch/arm/imx-common/sata.c create mode 100644 arch/arm/include/asm/imx-common/sata.h (limited to 'board') diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 2c804411674..68f0f5276ae 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -17,6 +17,9 @@ endif ifeq ($(SOC),$(filter $(SOC),mx6 mxs)) obj-y += misc.o endif +ifeq ($(SOC),$(filter $(SOC),mx6)) +objs-$(CONFIG_CMD_SATA) += sata.o +endif obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c new file mode 100644 index 00000000000..1b4c5029afb --- /dev/null +++ b/arch/arm/imx-common/sata.c @@ -0,0 +1,33 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int setup_sata(void) +{ + struct iomuxc_base_regs *const iomuxc_regs + = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; + + int ret = enable_sata_clock(); + if (ret) + return ret; + + clrsetbits_le32(&iomuxc_regs->gpr[13], + IOMUXC_GPR13_SATA_MASK, + IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB + |IOMUXC_GPR13_SATA_PHY_7_SATA2M + |IOMUXC_GPR13_SATA_SPEED_3G + |(3< #include #include +#include #include #include #include @@ -401,32 +402,6 @@ static void setup_buttons(void) ARRAY_SIZE(button_pads)); } -#ifdef CONFIG_CMD_SATA - -int setup_sata(void) -{ - struct iomuxc_base_regs *const iomuxc_regs - = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR; - int ret = enable_sata_clock(); - if (ret) - return ret; - - clrsetbits_le32(&iomuxc_regs->gpr[13], - IOMUXC_GPR13_SATA_MASK, - IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB - |IOMUXC_GPR13_SATA_PHY_7_SATA2M - |IOMUXC_GPR13_SATA_SPEED_3G - |(3< Date: Thu, 28 Nov 2013 12:32:49 +0100 Subject: udoo: Add SATA support on uDoo Board. Add SATA support on uDoo Board. Signed-off-by: Giuseppe Pagano CC: Stefano Babic CC: Fabio Estevam --- board/udoo/udoo.c | 4 ++++ include/configs/udoo.h | 12 ++++++++++++ 2 files changed, 16 insertions(+) (limited to 'board') diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c index 081d517f53c..e9236d444c8 100644 --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -240,6 +241,9 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif return 0; } diff --git a/include/configs/udoo.h b/include/configs/udoo.h index b9a493cd1ee..a1a1750cfdd 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -34,6 +34,18 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE +/* SATA Configs */ + +#define CONFIG_CMD_SATA +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + /* Network support */ #define CONFIG_CMD_PING -- cgit v1.3.1 From 1230743731cb8a2e3348044e2535e890d16fb2e6 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Fri, 29 Nov 2013 22:38:39 +0800 Subject: MX6 SabreSD: Use readl() to read the CCM_CCGR3 register Align with the context to use readl() to read the CCM_CCGR3 register with memory barrier instead of __raw_readl(). Signed-off-by: Liu Ying Reviewed-by: Fabio Estevam --- board/freescale/mx6sabresd/mx6sabresd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 851cbe9b32d..3a1fb20fff5 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -390,7 +390,7 @@ static void setup_display(void) imx_setup_hdmi(); /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ - reg = __raw_readl(&mxc_ccm->CCGR3); + reg = readl(&mxc_ccm->CCGR3); reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; writel(reg, &mxc_ccm->CCGR3); -- cgit v1.3.1 From 502a710f5b54bbb966db4c4516abf5d82f46dd47 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 2 Dec 2013 17:01:42 +0100 Subject: ARM: mx53: video: Add IPUv3 LCD support for M53EVK This patch adds support for the AMPIRE 800x480 LCD panel that is available for M53EVK. Signed-off-by: Marek Vasut Cc: Stefano Babic --- board/denx/m53evk/m53evk.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++ include/configs/m53evk.h | 16 ++++++++++ 2 files changed, 89 insertions(+) (limited to 'board') diff --git a/board/denx/m53evk/m53evk.c b/board/denx/m53evk/m53evk.c index 32751704b12..0f71a168bdc 100644 --- a/board/denx/m53evk/m53evk.c +++ b/board/denx/m53evk/m53evk.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -22,6 +23,11 @@ #include #include #include +#include +#include + +/* Special MXCFB sync flags are here. */ +#include "../drivers/video/mxcfb.h" DECLARE_GLOBAL_DATA_PTR; @@ -166,6 +172,32 @@ int board_mmc_init(bd_t *bis) } #endif +#ifdef CONFIG_VIDEO +static struct fb_videomode const ampire_wvga = { + .name = "Ampire", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 29851, /* picosecond (33.5 MHz) */ + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = FB_SYNC_CLK_LAT_FALL, +}; + +int board_video_skip(void) +{ + int ret; + ret = ipuv3_fb_init(&ire_wvga, 1, IPU_PIX_FMT_RGB666); + if (ret) + printf("Ampire LCD cannot be configured: %d\n", ret); + return ret; +} +#endif + #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) @@ -179,6 +211,46 @@ static void setup_iomux_i2c(void) imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); } +static void setup_iomux_video(void) +{ + static const iomux_v3_cfg_t lcd_pads[] = { + MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0, + MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1, + MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2, + MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3, + MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4, + MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5, + MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6, + MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7, + MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8, + MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9, + MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10, + MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11, + MX53_PAD_EIM_A17__IPU_DISP1_DAT_12, + MX53_PAD_EIM_A18__IPU_DISP1_DAT_13, + MX53_PAD_EIM_A19__IPU_DISP1_DAT_14, + MX53_PAD_EIM_A20__IPU_DISP1_DAT_15, + MX53_PAD_EIM_A21__IPU_DISP1_DAT_16, + MX53_PAD_EIM_A22__IPU_DISP1_DAT_17, + MX53_PAD_EIM_A23__IPU_DISP1_DAT_18, + MX53_PAD_EIM_A24__IPU_DISP1_DAT_19, + MX53_PAD_EIM_D31__IPU_DISP1_DAT_20, + MX53_PAD_EIM_D30__IPU_DISP1_DAT_21, + MX53_PAD_EIM_D26__IPU_DISP1_DAT_22, + MX53_PAD_EIM_D27__IPU_DISP1_DAT_23, + MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK, + MX53_PAD_EIM_DA13__IPU_DI1_D0_CS, + MX53_PAD_EIM_DA14__IPU_DI1_D1_CS, + MX53_PAD_EIM_DA15__IPU_DI1_PIN1, + MX53_PAD_EIM_DA11__IPU_DI1_PIN2, + MX53_PAD_EIM_DA12__IPU_DI1_PIN3, + MX53_PAD_EIM_A25__IPU_DI1_PIN12, + MX53_PAD_EIM_DA10__IPU_DI1_PIN15, + }; + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); +} + static void setup_iomux_nand(void) { static const iomux_v3_cfg_t nand_pads[] = { @@ -269,6 +341,7 @@ int board_early_init_f(void) setup_iomux_fec(); setup_iomux_i2c(); setup_iomux_nand(); + setup_iomux_video(); m53_set_clock(); diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index 8c54549fc26..a344af45739 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -37,6 +37,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_SATA #define CONFIG_CMD_USB +#define CONFIG_VIDEO /* * Memory configurations @@ -200,6 +201,21 @@ #define CONFIG_LIBATA #endif +/* + * LCD + */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_IPUV3_CLK 200000000 +#endif + /* * Boot Linux */ -- cgit v1.3.1 From be4ab3dd05504e771fb743d39f88186c4d8b1165 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 4 Dec 2013 01:08:16 -0200 Subject: mx6sabresd: Allow probing HSYNC, VSYNC and DISP_CLK signals HSYNC, VSYNC and DISP_CLK are very useful display signals for debugging. Configure them as active pins. Signed-off-by: Fabio Estevam --- board/freescale/mx6sabresd/mx6sabresd.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'board') diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 3a1fb20fff5..ecd2eabc9c8 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -135,6 +135,12 @@ static void setup_spi(void) imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); } +iomux_v3_cfg_t const di0_pads[] = { + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */ + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */ + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */ +}; + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); @@ -386,6 +392,9 @@ static void setup_display(void) struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; int reg; + /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ + imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads)); + enable_ipu_clock(); imx_setup_hdmi(); -- cgit v1.3.1 From 119e9909869ee3e2a994a01130014b93fade3bcc Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 4 Dec 2013 01:08:17 -0200 Subject: mx6sabresd: Fix LVDS width and color format mx6sabresd boards have a 18-bit LVDS data width and the correct color format is RGB666. Suggested-by: Liu Ying Signed-off-by: Fabio Estevam --- board/freescale/mx6sabresd/mx6sabresd.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index ecd2eabc9c8..2ffc3b80894 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -294,15 +294,15 @@ static void enable_lvds(struct display_info_t const *dev) struct iomuxc *iomux = (struct iomuxc *) IOMUXC_BASE_ADDR; u32 reg = readl(&iomux->gpr[2]); - reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | - IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT; + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | + IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT; writel(reg, &iomux->gpr[2]); } static struct display_info_t const displays[] = {{ .bus = -1, .addr = 0, - .pixfmt = IPU_PIX_FMT_LVDS666, + .pixfmt = IPU_PIX_FMT_RGB666, .detect = NULL, .enable = enable_lvds, .mode = { -- cgit v1.3.1 From 23565c6bccf098418a03405bedda6f7d3e68da36 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Sun, 20 Oct 2013 20:28:24 +0900 Subject: arm: lager: Add support Ethernet The lager board has one sh-ether device. This supports sh-ether. Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/lager/lager.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ include/configs/lager.h | 19 ++++++++++++ 2 files changed, 89 insertions(+) (limited to 'board') diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index 5c99fc9b58c..ba923d520f2 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "qos.h" DECLARE_GLOBAL_DATA_PTR; @@ -207,6 +208,10 @@ void s_init(void) #define SMSTPCR7 0xE615014C #define SCIF0_MSTP721 (1 << 21) +#define MSTPSR8 0xE61509A0 +#define SMSTPCR8 0xE6150990 +#define ETHER_MSTP813 (1 << 13) + #define PMMR 0xE6060000 #define GPSR4 0xE6060014 #define IPSR14 0xE6060058 @@ -242,6 +247,9 @@ int board_early_init_f(void) mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); + /* ETHER */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + return 0; } @@ -256,6 +264,68 @@ int board_init(void) /* Init PFC controller */ r8a7790_pinmux_init(); + /* ETHER Enable */ + gpio_request(GPIO_FN_ETH_CRS_DV, NULL); + gpio_request(GPIO_FN_ETH_RX_ER, NULL); + gpio_request(GPIO_FN_ETH_RXD0, NULL); + gpio_request(GPIO_FN_ETH_RXD1, NULL); + gpio_request(GPIO_FN_ETH_LINK, NULL); + gpio_request(GPIO_FN_ETH_REF_CLK, NULL); + gpio_request(GPIO_FN_ETH_MDIO, NULL); + gpio_request(GPIO_FN_ETH_TXD1, NULL); + gpio_request(GPIO_FN_ETH_TX_EN, NULL); + gpio_request(GPIO_FN_ETH_MAGIC, NULL); + gpio_request(GPIO_FN_ETH_TXD0, NULL); + gpio_request(GPIO_FN_ETH_MDC, NULL); + gpio_request(GPIO_FN_IRQ0, NULL); + + gpio_request(GPIO_GP_5_31, NULL); /* PHY_RST */ + gpio_direction_output(GPIO_GP_5_31, 0); + mdelay(20); + gpio_set_value(GPIO_GP_5_31, 1); + udelay(1); + + return 0; +} + +#define CXR24 0xEE7003C0 /* MAC address high register */ +#define CXR25 0xEE7003C8 /* MAC address low register */ +int board_eth_init(bd_t *bis) +{ + int ret = -ENODEV; + +#ifdef CONFIG_SH_ETHER + u32 val; + unsigned char enetaddr[6]; + + ret = sh_eth_initialize(bis); + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + return ret; + + /* Set Mac address */ + val = enetaddr[0] << 24 | enetaddr[1] << 16 | + enetaddr[2] << 8 | enetaddr[3]; + writel(val, CXR24); + + val = enetaddr[4] << 8 | enetaddr[5]; + writel(val, CXR25); + +#endif + + return ret; +} + +/* lager has KSZ8041NL/RNL */ +#define PHY_CONTROL1 0x1E +#define PHY_LED_MODE 0xC0000 +#define PHY_LED_MODE_ACK 0x4000 +int board_phy_config(struct phy_device *phydev) +{ + int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); + ret &= ~PHY_LED_MODE; + ret |= PHY_LED_MODE_ACK; + ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); + return 0; } diff --git a/include/configs/lager.h b/include/configs/lager.h index 7819edddc6c..e4a5cca40ab 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -28,6 +28,11 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_RUN #define CONFIG_CMD_LOADS +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS #define CONFIG_CMD_BOOTZ #define CONFIG_CMD_FLASH @@ -127,6 +132,20 @@ #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) +/* SH Ether */ +#define CONFIG_NET_MULTI +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + /* Board Clock */ #define CONFIG_BASE_CLK_FREQ 20000000u #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */ -- cgit v1.3.1 From b9986be0840d7945f760204bfb1a4b565ba235ff Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 10 Oct 2013 09:13:41 +0900 Subject: arm: lager: Add support reset function The lager board uses I2C for reset. ned-off-by: Nobuhiro Iwamatsu --- board/renesas/lager/lager.c | 8 ++++++++ include/configs/lager.h | 2 ++ 2 files changed, 10 insertions(+) (limited to 'board') diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index ba923d520f2..cdd5b321357 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "qos.h" DECLARE_GLOBAL_DATA_PTR; @@ -354,4 +355,11 @@ int board_late_init(void) void reset_cpu(ulong addr) { + u8 val; + + i2c_set_bus_num(3); /* PowerIC connected to ch3 */ + i2c_init(400000, 0); + i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + val |= 0x02; + i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); } diff --git a/include/configs/lager.h b/include/configs/lager.h index dd61ca0dc90..893282540e3 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -159,6 +159,8 @@ #define CONFIG_SYS_RCAR_I2C3_SPEED 400000 #define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ + /* Board Clock */ #define CONFIG_BASE_CLK_FREQ 20000000u #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */ -- cgit v1.3.1 From 90362c0c04a9b7ec7d251ddf208ec411be456b6c Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Sun, 20 Oct 2013 20:37:17 +0900 Subject: arm: koelsch: Add support Ethernet The koelsch board has one sh-ether device. This supports sh-ether. Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/koelsch/koelsch.c | 77 +++++++++++++++++++++++++++++++++++++++++ include/configs/koelsch.h | 23 ++++++++++-- 2 files changed, 98 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 7153f652b53..73cad66f1ed 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include #include "qos.h" @@ -207,6 +209,10 @@ void s_init(void) #define SMSTPCR7 0xE615014C #define SCIF0_MSTP721 (1 << 21) +#define MSTPSR8 0xE61509A0 +#define SMSTPCR8 0xE6150990 +#define ETHER_MSTP813 (1 << 13) + #define PMMR 0xE6060000 #define GPSR4 0xE6060014 #define IPSR14 0xE6060058 @@ -241,9 +247,16 @@ int board_early_init_f(void) mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); + /* ETHER */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + return 0; } +/* LSI pin pull-up control */ +#define PUPR5 0xe6060114 +#define PUPR5_ETH 0x3FFC0000 +#define PUPR5_ETH_MAGIC (1 << 27) int board_init(void) { /* adress of boot parameters */ @@ -252,7 +265,57 @@ int board_init(void) /* Init PFC controller */ r8a7791_pinmux_init(); + /* ETHER Enable */ + gpio_request(GPIO_FN_ETH_CRS_DV, NULL); + gpio_request(GPIO_FN_ETH_RX_ER, NULL); + gpio_request(GPIO_FN_ETH_RXD0, NULL); + gpio_request(GPIO_FN_ETH_RXD1, NULL); + gpio_request(GPIO_FN_ETH_LINK, NULL); + gpio_request(GPIO_FN_ETH_REFCLK, NULL); + gpio_request(GPIO_FN_ETH_MDIO, NULL); + gpio_request(GPIO_FN_ETH_TXD1, NULL); + gpio_request(GPIO_FN_ETH_TX_EN, NULL); + gpio_request(GPIO_FN_ETH_TXD0, NULL); + gpio_request(GPIO_FN_ETH_MDC, NULL); + gpio_request(GPIO_FN_IRQ0, NULL); + + mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); + gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ + mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); + + gpio_direction_output(GPIO_GP_5_22, 0); + mdelay(20); + gpio_set_value(GPIO_GP_5_22, 1); + udelay(1); + + return 0; +} + +#define CXR24 0xEE7003C0 /* MAC address high register */ +#define CXR25 0xEE7003C8 /* MAC address low register */ +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SH_ETHER + int ret = -ENODEV; + u32 val; + unsigned char enetaddr[6]; + + ret = sh_eth_initialize(bis); + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + return ret; + + /* Set Mac address */ + val = enetaddr[0] << 24 | enetaddr[1] << 16 | + enetaddr[2] << 8 | enetaddr[3]; + writel(val, CXR24); + + val = enetaddr[4] << 8 | enetaddr[5]; + writel(val, CXR25); + + return ret; +#else return 0; +#endif } int dram_init(void) @@ -263,6 +326,20 @@ int dram_init(void) return 0; } +/* koelsch has KSZ8041NL/RNL */ +#define PHY_CONTROL1 0x1E +#define PHY_LED_MODE 0xC0000 +#define PHY_LED_MODE_ACK 0x4000 +int board_phy_config(struct phy_device *phydev) +{ + int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); + ret &= ~PHY_LED_MODE; + ret |= PHY_LED_MODE_ACK; + ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); + + return 0; +} + const struct rmobile_sysinfo sysinfo = { CONFIG_RMOBILE_BOARD_STRING }; diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 59c494854be..32ceff3d7cb 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -18,13 +18,18 @@ #include -#define CONFIG_CMD_EDITENV -#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_EDITENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_MEMORY #define CONFIG_CMD_DFL #define CONFIG_CMD_SDRAM #define CONFIG_CMD_RUN #define CONFIG_CMD_LOADS +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS #define CONFIG_CMD_BOOTZ #define CONFIG_CMD_FLASH @@ -123,6 +128,20 @@ #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) +/* SH Ether */ +#define CONFIG_NET_MULTI +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 + /* Board Clock */ #define CONFIG_SYS_CLK_FREQ 10000000 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ -- cgit v1.3.1 From b8f383b86bc748382cc7cb5b3602c0c2ff9cb60c Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 10 Oct 2013 10:48:20 +0900 Subject: arm: koelsch: Add support reset function Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/koelsch/koelsch.c | 6 ++++++ include/configs/koelsch.h | 2 ++ 2 files changed, 8 insertions(+) (limited to 'board') diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 73cad66f1ed..89f5c91c636 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -357,4 +357,10 @@ int board_late_init(void) void reset_cpu(ulong addr) { + u8 val; + + i2c_set_bus_num(2); /* PowerIC connected to ch2 */ + i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + val |= 0x02; + i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); } diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index f410a8f79f5..f8cca5b2810 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -165,4 +165,6 @@ #define CONFIG_SH_I2C_DATA_LOW 5 #define CONFIG_SH_I2C_CLOCK 10000000 +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ + #endif /* __KOELSCH_H */ -- cgit v1.3.1 From a3d6ca432303bc19926a885c83149401abc24d0d Mon Sep 17 00:00:00 2001 From: Sergei Ianovich Date: Wed, 18 Dec 2013 20:19:20 +0400 Subject: arm: pxa: fix LP-8x4x USB support Signed-off-by: Sergei Ianovich CC: Marek Vasut --- board/icpdas/lp8x4x/lp8x4x.c | 38 ++++++++++++++++++++++++-------------- include/configs/lp8x4x.h | 3 +-- 2 files changed, 25 insertions(+), 16 deletions(-) (limited to 'board') diff --git a/board/icpdas/lp8x4x/lp8x4x.c b/board/icpdas/lp8x4x/lp8x4x.c index 92dd4ff97a7..5eee18af7ba 100644 --- a/board/icpdas/lp8x4x/lp8x4x.c +++ b/board/icpdas/lp8x4x/lp8x4x.c @@ -61,15 +61,24 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_CMD_USB int board_usb_init(int index, enum usb_init_type init) { - writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) & - ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), - UHCHR); + if (index !=0 || init != USB_INIT_HOST) + return -1; + + writel(readl(CKEN) | CKEN10_USBHOST, CKEN); + + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); + udelay(11); + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); while (readl(UHCHR) & UHCHR_FSBIR) continue; /* required by checkpath.pl */ + writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR); + writel(readl(UHCRHDA) & ~(0x1000), UHCRHDA); + writel(readl(UHCRHDA) | 0x800, UHCRHDA); + writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); @@ -83,19 +92,10 @@ int board_usb_init(int index, enum usb_init_type init) /* Set port power control mask bits, only 3 ports. */ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); - /* enable port 2 */ - writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | - UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); - return 0; } -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} - -void usb_board_stop(void) +int usb_board_stop(void) { writel(readl(UHCHR) | UHCHR_FHR, UHCHR); udelay(11); @@ -104,9 +104,19 @@ void usb_board_stop(void) writel(readl(UHCCOMS) | 1, UHCCOMS); udelay(10); + writel(readl(UHCHR) | UHCHR_SSEP0 | UHCHR_SSE, UHCHR); + writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); - return; + return 0; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + if (index !=0 || init != USB_INIT_HOST) + return -1; + + return usb_board_stop(); } #endif diff --git a/include/configs/lp8x4x.h b/include/configs/lp8x4x.h index 68e1a974dd0..324cc4d1b08 100644 --- a/include/configs/lp8x4x.h +++ b/include/configs/lp8x4x.h @@ -184,7 +184,7 @@ #define CONFIG_SYS_GAFR1_L_VAL 0x999a955a #define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a00a #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x55f0a402 +#define CONFIG_SYS_GAFR2_U_VAL 0x55f9a402 #define CONFIG_SYS_GAFR3_L_VAL 0x540a950c #define CONFIG_SYS_GAFR3_U_VAL 0x00001599 @@ -232,7 +232,6 @@ */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_BOARD_INIT #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 -- cgit v1.3.1 From 914f2bd1f07fba93639ad1273d4cd458b0ee99cc Mon Sep 17 00:00:00 2001 From: Sergei Ianovich Date: Tue, 17 Dec 2013 05:03:44 +0400 Subject: arm: pxa: init ethaddr for LP-8x4x using DT When DT define aliases for etherner0 and ethernet1, U-Boot automatically patched MAC addresses using ethaddr and eth1addr environment variables respectively. Custom initialization is no longer needed. Signed-off-by: Sergei Ianovich CC: Marek Vasut --- board/icpdas/lp8x4x/lp8x4x.c | 17 ----------------- 1 file changed, 17 deletions(-) (limited to 'board') diff --git a/board/icpdas/lp8x4x/lp8x4x.c b/board/icpdas/lp8x4x/lp8x4x.c index 5eee18af7ba..a136dc4c37a 100644 --- a/board/icpdas/lp8x4x/lp8x4x.c +++ b/board/icpdas/lp8x4x/lp8x4x.c @@ -121,25 +121,8 @@ int board_usb_cleanup(int index, enum usb_init_type init) #endif #ifdef CONFIG_DRIVER_DM9000 -void lp8x4x_eth1_mac_init(void) -{ - u8 eth1addr[8]; - int i; - u8 reg; - - eth_getenv_enetaddr_by_index("eth", 1, eth1addr); - if (!is_valid_ether_addr(eth1addr)) - return; - - for (i = 0, reg = 0x10; i < 6; i++, reg++) { - writeb(reg, (u8 *)(DM9000_IO_2)); - writeb(eth1addr[i], (u8 *)(DM9000_DATA_2)); - } -} - int board_eth_init(bd_t *bis) { - lp8x4x_eth1_mac_init(); return dm9000_initialize(bis); } #endif -- cgit v1.3.1 From 8f38038193752d3719f39ccd562f7ffdf83989d5 Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Thu, 14 Nov 2013 10:58:30 +0100 Subject: ARM: tegra: Add the Tamonten™ NG Evaluation Carrier board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for the new Tamonten™ NG platform from Avionic Design. Currently only I2C, MMC, USB and ethernet have been tested. Signed-off-by: Alban Bedel Reviewed-by: Stephen Warren Signed-off-by: Tom Warren --- .../common/pinmux-config-tamonten-ng.h | 385 +++++++++++++++++++++ board/avionic-design/common/tamonten-ng.c | 85 +++++ board/avionic-design/dts/tegra30-tamonten.dtsi | 69 ++++ board/avionic-design/dts/tegra30-tec-ng.dts | 18 + board/avionic-design/tec-ng/Makefile | 12 + boards.cfg | 1 + include/configs/tec-ng.h | 84 +++++ 7 files changed, 654 insertions(+) create mode 100644 board/avionic-design/common/pinmux-config-tamonten-ng.h create mode 100644 board/avionic-design/common/tamonten-ng.c create mode 100644 board/avionic-design/dts/tegra30-tamonten.dtsi create mode 100644 board/avionic-design/dts/tegra30-tec-ng.dts create mode 100644 board/avionic-design/tec-ng/Makefile create mode 100644 include/configs/tec-ng.h (limited to 'board') diff --git a/board/avionic-design/common/pinmux-config-tamonten-ng.h b/board/avionic-design/common/pinmux-config-tamonten-ng.h new file mode 100644 index 00000000000..39df73138a4 --- /dev/null +++ b/board/avionic-design/common/pinmux-config-tamonten-ng.h @@ -0,0 +1,385 @@ +/* + * (C) Copyright 2013 + * Avionic Design GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PINMUX_CONFIG_TAMONTEN_NG_H_ +#define _PINMUX_CONFIG_TAMONTEN_NG_H_ + +#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + } + +#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .padgrp = PDRIVE_PINGROUP_##_padgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PGRP_LPMD_##_lpmd, \ + .schmt = PGRP_SCHMT_##_schmt, \ + .hsm = PGRP_HSM_##_hsm, \ + } + +static struct pingroup_config tamonten_ng_pinmux_common[] = { + /* SDMMC1 pinmux */ + DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT), + + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT6, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS6_N, RSVD1, UP, NORMAL, INPUT), + + /* SDMMC4 pinmux */ + LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), + + /* I2C1 pinmux */ + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C2 pinmux */ + I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C3 pinmux */ + I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C4 pinmux */ + I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* Power I2C pinmux */ + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* UART1 */ + DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT), + + /* UART2 */ + DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT), + + /* UART3 */ + DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), + + /* UART4 */ + DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DIR, UARTD, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT), + + /* DAP */ + DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT), + + /* I2S1 */ + DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), + + /* SPDIF */ + DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT), + + /* I2S2 */ + DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), + + /* DAP4 */ + DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT), + + /* Tamonten GPIO */ + DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_CS1_N, RSVD1, NORMAL, NORMAL, INPUT), + + /* LCD */ + DEFAULT_PINMUX(LCD_PWR1, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR2, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDIN, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_WR_N, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC0, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SCK, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR0, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PCLK, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DE, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D0, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D1, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D2, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D4, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D8, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D9, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D10, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_M1, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC1, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT), + + /* BT656 */ + LV_PINMUX(VI_MCLK, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_PCLK, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_HSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_VSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D8, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D9, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D11, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + + /* GPIOs */ + DEFAULT_PINMUX(GPIO_PU5, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD12, RSVD1, NORMAL, NORMAL, INPUT), + + /* LCD BL */ + DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD10, RSVD4, NORMAL, NORMAL, OUTPUT), + + /* SPI4 */ + DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT), + + /* Video input GPIO */ + DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, NORMAL, INPUT), + + /* Sensor GPIO */ + DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, NORMAL, INPUT), + + /* JTAG */ + DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT), + + /* Power controls */ + DEFAULT_PINMUX(GMI_CS2_N, RSVD1, NORMAL, NORMAL, INPUT), + + /* SPI1 */ + DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT), + + /* PMU */ + DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK_32K_IN, SYSCLK, NORMAL, NORMAL, INPUT), + + /* PCI */ + DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), + + /* HDMI */ + DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT), +}; + +static struct pingroup_config unused_pins_lowpower[] = { + /* UART1 - NC */ + DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, INPUT), + + /* UART2 - NC */ + DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT), + + /* DAP - NC */ + DEFAULT_PINMUX(CLK1_REQ, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK3_OUT, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK3_REQ, RSVD1, NORMAL, NORMAL, INPUT), + + /* DAP4 - NC */ + DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT), + + /* Tamonten GPIO - NC */ + DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT), + + /* BT656 - NC */ + LV_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D1, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + + /* GPIO - NC */ + DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU4, RSVD1, NORMAL, NORMAL, INPUT), + + /* Video input - NC */ + DEFAULT_PINMUX(CAM_MCLK, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB5, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB6, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW11, RSVD1, NORMAL, NORMAL, INPUT), + + /* KBC keys - NC */ + DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT), + + /* PMU - NC */ + DEFAULT_PINMUX(CLK_32K_OUT, RSVD1, NORMAL, NORMAL, INPUT), + + /* Power rails GPIO - NC */ + DEFAULT_PINMUX(SPI2_SCK, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB4, RSVD1, NORMAL, NORMAL, INPUT), + + /* Others - NC */ + DEFAULT_PINMUX(GMI_WP_N, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT), +}; + +static struct padctrl_config tamonten_ng_padctrl[] = { + /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ + DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), +}; +#endif /* _PINMUX_CONFIG_TAMONTEN_NG_H_ */ diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c new file mode 100644 index 00000000000..9d395c676e0 --- /dev/null +++ b/board/avionic-design/common/tamonten-ng.c @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2013 + * Avionic Design GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "pinmux-config-tamonten-ng.h" +#include + +#define PMU_I2C_ADDRESS 0x2D + +#define PMU_REG_LDO5 0x32 + +#define PMU_REG_LDO_HIGH_POWER 1 + +/* Voltage selection for the LDOs with 100mV resolution */ +#define PMU_REG_LDO_SEL_100(mV) ((((mV - 1000) / 100) + 2) << 2) + +#define PMU_REG_LDO_100(st, mV) (PMU_REG_LDO_##st | PMU_REG_LDO_SEL_100(mV)) + +#define PMU_LDO5(st, mV) PMU_REG_LDO_100(st, mV) + +void pinmux_init(void) +{ + pinmux_config_table(tamonten_ng_pinmux_common, + ARRAY_SIZE(tamonten_ng_pinmux_common)); + pinmux_config_table(unused_pins_lowpower, + ARRAY_SIZE(unused_pins_lowpower)); + + /* Initialize any non-default pad configs (APB_MISC_GP regs) */ + padgrp_config_table(tamonten_ng_padctrl, + ARRAY_SIZE(tamonten_ng_padctrl)); +} + +void gpio_early_init(void) +{ + /* Turn on the alive signal */ + gpio_request(GPIO_PV2, "ALIVE"); + gpio_direction_output(GPIO_PV2, 1); + + /* Remove the reset on the external periph */ + gpio_request(GPIO_PI4, "nRST_PERIPH"); + gpio_direction_output(GPIO_PI4, 1); +} + +void pmu_write(uchar reg, uchar data) +{ + i2c_set_bus_num(4); /* PMU is on bus 4 */ + i2c_write(PMU_I2C_ADDRESS, reg, 1, &data, 1); +} + +/* + * Do I2C/PMU writes to bring up SD card bus power + * + */ +void board_sdmmc_voltage_init(void) +{ + /* Enable LDO5 with 3.3v for SDMMC3 */ + pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300)); + + /* Switch the power on */ + gpio_request(GPIO_PJ2, "EN_3V3_EMMC"); + gpio_direction_output(GPIO_PJ2, 1); +} + +/* + * Routine: pin_mux_mmc + * Description: setup the MMC muxes, power rails, etc. + */ +void pin_mux_mmc(void) +{ + /* + * NOTE: We don't do mmc-specific pin muxes here. + * They were done globally in pinmux_init(). + */ + + /* Bring up the SDIO1 power rail */ + board_sdmmc_voltage_init(); +} diff --git a/board/avionic-design/dts/tegra30-tamonten.dtsi b/board/avionic-design/dts/tegra30-tamonten.dtsi new file mode 100644 index 00000000000..50d5762311e --- /dev/null +++ b/board/avionic-design/dts/tegra30-tamonten.dtsi @@ -0,0 +1,69 @@ +#include "tegra30.dtsi" + +/ { + model = "Avionic Design Tamonten NG"; + compatible = "ad,tamonten-ng", "nvidia,tegra30"; + + memory { + reg = <0x80000000 0x40000000>; + }; + + aliases { + i2c0 = "/i2c@7000c000"; + i2c1 = "/i2c@7000c700"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000d000"; + sdhci0 = "/sdhci@78000600"; + sdhci1 = "/sdhci@78000400"; + sdhci2 = "/sdhci@78000000"; + usb0 = "/usb@7d008000"; + }; + + /* GEN1 */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* GEN2 */ + i2c@7000c400 { + clock-frequency = <100000>; + }; + + /* CAM */ + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* DDC */ + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* PWR */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* SD slot on the base board */ + sdhci@78000400 { + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + wp-gpios = <&gpio 67 0>; /* gpio PI3 */ + bus-width = <4>; + }; + + /* EMMC on the COM module */ + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + }; + + usb@7d008000 { + status = "okay"; + }; + +}; diff --git a/board/avionic-design/dts/tegra30-tec-ng.dts b/board/avionic-design/dts/tegra30-tec-ng.dts new file mode 100644 index 00000000000..8a69e818ca3 --- /dev/null +++ b/board/avionic-design/dts/tegra30-tec-ng.dts @@ -0,0 +1,18 @@ +/dts-v1/; + +#include "tegra30-tamonten.dtsi" + +/ { + model = "Avionic Design Tamonten™ NG Evaluation Carrier"; + compatible = "ad,tec-ng", "nvidia,tegra30"; + + /* GEN2 */ + i2c@7000c400 { + status = "okay"; + }; + + /* SD card slot */ + sdhci@78000400 { + status = "okay"; + }; +}; diff --git a/board/avionic-design/tec-ng/Makefile b/board/avionic-design/tec-ng/Makefile new file mode 100644 index 00000000000..f41eb307231 --- /dev/null +++ b/board/avionic-design/tec-ng/Makefile @@ -0,0 +1,12 @@ +# +# (C) Copyright 2013 +# Avionic Design GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) + +obj-y := ../common/tamonten-ng.o + +include ../../nvidia/common/common.mk diff --git a/boards.cfg b/boards.cfg index c99d6480303..152d85e80d1 100644 --- a/boards.cfg +++ b/boards.cfg @@ -362,6 +362,7 @@ Active arm armv7:arm720t tegra114 nvidia dalmore Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel Active arm armv7:arm720t tegra20 avionic-design tec tec - Alban Bedel +Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel Active arm armv7:arm720t tegra20 compal paz00 paz00 - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra20 compulab trimslice trimslice - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra20 nvidia harmony harmony - Tom Warren diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h new file mode 100644 index 00000000000..13baa76f915 --- /dev/null +++ b/include/configs/tec-ng.h @@ -0,0 +1,84 @@ +/* + * (C) Copyright 2013 + * Avionic Design GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra30-common.h" + +/* Enable fdt support for tec-ng. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra30-tec-ng +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* High-level configuration options */ +#define V_PROMPT "Tegra30 (TEC-NG) # " +#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTD +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 + +/* SPI */ +#define CONFIG_TEGRA20_SLINK +#define CONFIG_TEGRA_SLINK_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +/* Tag support */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +/* support the new (FDT-based) image format */ +#define CONFIG_FIT + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 369cbe1e1ec6e2f0761438e7cef717a78b8905b1 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:12 +0530 Subject: ARM: AM43xx: Adapt to ti_armv7_common.h config file Use ti_armv7_common.h config file to inclde the common configs. Signed-off-by: Lokesh Vutla --- arch/arm/include/asm/arch-am33xx/omap.h | 2 +- board/ti/am43xx/board.c | 2 +- include/configs/am43xx_evm.h | 129 +++++++------------------------- 3 files changed, 29 insertions(+), 104 deletions(-) (limited to 'board') diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 225072186db..cf5f8b2dd0e 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -26,6 +26,6 @@ #elif defined(CONFIG_AM43XX) #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40340000 -#define SRAM_SCRATCH_SPACE_ADDR 0x4033C000 +#define SRAM_SCRATCH_SPACE_ADDR 0x40337C00 #endif #endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 51b257683d3..dcd8cbbe2be 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -44,7 +44,7 @@ void sdram_init(void) int board_init(void) { - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index d9b6c16baac..cad6979e812 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -10,127 +10,52 @@ #define __CONFIG_AM43XX_EVM_H #define CONFIG_AM43XX -#define CONFIG_OMAP -#define CONFIG_OMAP_COMMON -#include - -#define CONFIG_DMA_COHERENT -#define CONFIG_DMA_COHERENT_SIZE (1 << 20) - -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "U-Boot# " -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_CACHELINE_SIZE 32 - -#define CONFIG_OF_LIBFDT -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* commands to include */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_VERSION_VARIABLE - -/* set to negative value for no autoboot */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_ENV_VARS_UBOOT_CONFIG -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#define CONFIG_CMD_ECHO - -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 64 - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 512 - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - - /* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) -/* Platform/Board specific defs */ -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ - #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +#include /* NS16550 Configuration */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_CLK 48000000 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ -4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } - -/* CPU */ -#define CONFIG_ARCH_CPU_INIT - -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_SYS_CONSOLE_INFO_QUIET - -#define CONFIG_ENV_IS_NOWHERE +/* SPL defines. */ +#define CONFIG_SPL_TEXT_BASE 0x40300350 +#define CONFIG_SPL_MAX_SIZE (0x40337C00 - CONFIG_SPL_TEXT_BASE) +#define CONFIG_SPL_YMODEM_SUPPORT /* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. */ -#define CONFIG_SYS_TEXT_BASE 0x80800000 - -#ifndef CONFIG_SPL_BUILD +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) #define CONFIG_SKIP_LOWLEVEL_INIT #endif -/* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_TEXT_BASE 0x402F0400 -#define CONFIG_SPL_MAX_SIZE (101 * 1024) -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +/* Now bring in the rest of the common code. */ +#include -#define CONFIG_SPL_BSS_START_ADDR 0x80a00000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ +/* Always 128 KiB env size */ +#define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_YMODEM_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SYS_SPL_MALLOC_START 0x80a08000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) -/* Unsupported features */ -#undef CONFIG_USE_IRQ +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ + +#define CONFIG_ENV_IS_NOWHERE + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_CMD_USB #define CONFIG_USB_HOST -- cgit v1.3.1 From 9f1a8cd33fec83c5e04c8d1103fb3ee2857ff2f0 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Tue, 10 Dec 2013 15:02:15 +0530 Subject: ARM: AM43XX: board: add support for reading onboard EEPROM Add support for reading onboard EEPROM to enable board detection. Signed-off-by: Sekhar Nori Signed-off-by: Lokesh Vutla --- arch/arm/include/asm/arch-am33xx/omap.h | 2 ++ board/ti/am43xx/board.c | 46 +++++++++++++++++++++++++++++++++ board/ti/am43xx/board.h | 32 +++++++++++++++++++++++ include/configs/am43xx_evm.h | 7 +++++ 4 files changed, 87 insertions(+) (limited to 'board') diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index cf5f8b2dd0e..7a7d91b7142 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -27,5 +27,7 @@ #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40340000 #define SRAM_SCRATCH_SPACE_ADDR 0x40337C00 +#define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR +#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC #endif #endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index dcd8cbbe2be..4fc1a40c048 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -9,6 +9,8 @@ */ #include +#include +#include #include #include #include @@ -17,6 +19,50 @@ DECLARE_GLOBAL_DATA_PTR; +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(struct am43xx_board_id *header) +{ + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + printf("Could not probe the EEPROM at 0x%x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return -ENODEV; + } + + /* read the eeprom using i2c */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, + sizeof(struct am43xx_board_id))) { + printf("Could not read the EEPROM\n"); + return -EIO; + } + + if (header->magic != 0xEE3355AA) { + /* + * read the eeprom using i2c again, + * but use only a 1 byte address + */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, + sizeof(struct am43xx_board_id))) { + printf("Could not read the EEPROM at 0x%x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return -EIO; + } + + if (header->magic != 0xEE3355AA) { + printf("Incorrect magic number (0x%x) in EEPROM\n", + header->magic); + return -EINVAL; + } + } + + strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name)); + am43xx_board_name[sizeof(header->name)] = 0; + + return 0; +} + #ifdef CONFIG_SPL_BUILD const struct dpll_params dpll_ddr = { diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h index 8ca098b82a9..92688956593 100644 --- a/board/ti/am43xx/board.h +++ b/board/ti/am43xx/board.h @@ -12,6 +12,38 @@ #ifndef _BOARD_H_ #define _BOARD_H_ +#include + +static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START; + +/* + * TI AM437x EVMs define a system EEPROM that defines certain sub-fields. + * We use these fields to in turn see what board we are on, and what + * that might require us to set or not set. + */ +#define HDR_NO_OF_MAC_ADDR 3 +#define HDR_ETH_ALEN 6 +#define HDR_NAME_LEN 8 + +struct am43xx_board_id { + unsigned int magic; + char name[HDR_NAME_LEN]; + char version[4]; + char serial[12]; + char config[32]; + char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; +}; + +static inline int board_is_eposevm(void) +{ + return !strncmp(am43xx_board_name, "AM43EPOS", HDR_NAME_LEN); +} + +static inline int board_is_gpevm(void) +{ + return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN); +} + void enable_uart0_pin_mux(void); void enable_board_pin_mux(void); #endif diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 0f340780cdc..4de495a15a2 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -25,6 +25,13 @@ #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK 48000000 +/* I2C Configuration */ +#define CONFIG_CMD_EEPROM +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_MULTI_EEPROMS + /* SPL defines. */ #define CONFIG_SPL_TEXT_BASE 0x40300350 #define CONFIG_SPL_MAX_SIZE (0x40337C00 - CONFIG_SPL_TEXT_BASE) -- cgit v1.3.1 From f4af163e6c8efbc768c2c0962c7823d6363e30fe Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Tue, 10 Dec 2013 15:02:16 +0530 Subject: ARM: AM43XX: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support CONFIG_ENV_VARS_UBOOT_CONFIG, CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and CONFIG_BOARD_LATE_INIT is already set. Adding support to detect the board. These variables are used by findfdt. Signed-off-by: Sekhar Nori Signed-off-by: Lokesh Vutla --- board/ti/am43xx/board.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'board') diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 4fc1a40c048..723d0ca3274 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -98,6 +98,22 @@ int board_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + char safe_string[HDR_NAME_LEN + 1]; + struct am43xx_board_id header; + + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + /* Now set variables based on the header. */ + strncpy(safe_string, (char *)header.name, sizeof(header.name)); + safe_string[sizeof(header.name)] = 0; + setenv("board_name", safe_string); + + strncpy(safe_string, (char *)header.version, sizeof(header.version)); + safe_string[sizeof(header.version)] = 0; + setenv("board_rev", safe_string); +#endif return 0; } #endif -- cgit v1.3.1 From 4892495e368da9462cd5c1c0d6498fe95b45192e Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:19 +0530 Subject: ARM: AM43xx: mux: Update mux data Updating the mux data for UART, adding data for i2c0 and mmc. And also updating pad_signals structure. Signed-off-by: Lokesh Vutla --- arch/arm/include/asm/arch-am33xx/mux_am43xx.h | 45 +++++++++++++++++++++++++++ board/ti/am43xx/mux.c | 22 +++++++++++-- 2 files changed, 65 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h index 0206912d541..98fc2b50dae 100644 --- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h @@ -137,6 +137,51 @@ struct pad_signals { int mcasp0_fsr; int mcasp0_axr1; int mcasp0_ahclkx; + int xdma_event_intr0; + int xdma_event_intr1; + int nresetin_out; + int porz; + int nnmi; + int osc0_in; + int osc0_out; + int rsvd1; + int tms; + int tdi; + int tdo; + int tck; + int ntrst; + int emu0; + int emu1; + int osc1_in; + int osc1_out; + int pmic_power_en; + int rtc_porz; + int rsvd2; + int ext_wakeup; + int enz_kaldo_1p8v; + int usb0_dm; + int usb0_dp; + int usb0_ce; + int usb0_id; + int usb0_vbus; + int usb0_drvvbus; + int usb1_dm; + int usb1_dp; + int usb1_ce; + int usb1_id; + int usb1_vbus; + int usb1_drvvbus; + int ddr_resetn; + int ddr_csn0; + int ddr_cke; + int ddr_ck; + int ddr_nck; + int ddr_casn; + int ddr_rasn; + int ddr_wen; + int ddr_ba0; + int ddr_ba1; + int ddr_ba2; }; #endif /* _MUX_AM43XX_H_ */ diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 700e9a76ad3..46bad0199d8 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -12,8 +12,24 @@ #include "board.h" static struct module_pin_mux uart0_pin_mux[] = { - {OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)}, /* UART0_RXD */ - {OFFSET(uart0_txd), (MODE(0))}, /* UART0_TXD */ + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_CMD */ + {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, {-1}, }; @@ -24,4 +40,6 @@ void enable_uart0_pin_mux(void) void enable_board_pin_mux(void) { + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(i2c0_pin_mux); } -- cgit v1.3.1 From cf04d0326bd1e24909cfe644c0c8676440a915b1 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:20 +0530 Subject: ARM: AM43xx: clocks: Update DPLL details Updating the Multiplier and Dividers value for all DPLLs. Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value returned the MPU DPLL is locked. At different OPPs follwoing are the MPU locked frequencies. OPP50 300MHz OPP100 600MHz OPP120 720MHz OPPTB 800MHz OPPNT 1000MHz According to the latest DM following is the OPP table dependencies: VDD_CORE VDD_MPU OPP50 OPP50 OPP50 OPP100 OPP100 OPP50 OPP100 OPP100 OPP100 OPP120 So at different OPPs of MPU it is safest to lock CORE at OPP_NOM. Following are the DPLL locking frequencies at OPP NOM: Core locks at 1000MHz Per locks at 960MHz LPDDR2 locks at 266MHz DDR3 locks at 400MHz Touching AM33xx files also to get DPLL values specific to board but no functionality difference. Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/am33xx/clock.c | 12 +- arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 15 +++ arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 8 +- arch/arm/include/asm/arch-am33xx/clock.h | 7 +- arch/arm/include/asm/arch-am33xx/cpu.h | 2 + arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 13 ++ board/ti/am43xx/board.c | 138 ++++++++++++++++++++- board/ti/am43xx/board.h | 4 + board/ti/am43xx/mux.c | 5 + 9 files changed, 187 insertions(+), 17 deletions(-) (limited to 'board') diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index 8e5f3c67150..0672798fe04 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -101,9 +101,15 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs, static void setup_dplls(void) { const struct dpll_params *params; - do_setup_dpll(&dpll_core_regs, &dpll_core); - do_setup_dpll(&dpll_mpu_regs, &dpll_mpu); - do_setup_dpll(&dpll_per_regs, &dpll_per); + + params = get_dpll_core_params(); + do_setup_dpll(&dpll_core_regs, params); + + params = get_dpll_mpu_params(); + do_setup_dpll(&dpll_mpu_regs, params); + + params = get_dpll_per_params(); + do_setup_dpll(&dpll_per_regs, params); writel(0x300, &cmwkup->clkdcoldodpllper); params = get_dpll_ddr_params(); diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c index fabe2595a33..92142c89344 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c @@ -62,6 +62,21 @@ const struct dpll_params dpll_core = { const struct dpll_params dpll_per = { 960, OSC-1, 5, -1, -1, -1, -1}; +const struct dpll_params *get_dpll_mpu_params(void) +{ + return &dpll_mpu; +} + +const struct dpll_params *get_dpll_core_params(void) +{ + return &dpll_core; +} + +const struct dpll_params *get_dpll_per_params(void) +{ + return &dpll_per; +} + void setup_clocks_for_console(void) { clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c index 22963b7f853..97c00b4925f 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -48,15 +48,9 @@ const struct dpll_regs dpll_ddr_regs = { .cm_idlest_dpll = CM_WKUP + 0x5A4, .cm_clksel_dpll = CM_WKUP + 0x5AC, .cm_div_m2_dpll = CM_WKUP + 0x5B0, + .cm_div_m4_dpll = CM_WKUP + 0x5B8, }; -const struct dpll_params dpll_mpu = { - -1, -1, -1, -1, -1, -1, -1}; -const struct dpll_params dpll_core = { - -1, -1, -1, -1, -1, -1, -1}; -const struct dpll_params dpll_per = { - -1, -1, -1, -1, -1, -1, -1}; - void setup_clocks_for_console(void) { /* Do not add any spl_debug prints in this function */ diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 519249e4af4..76374575496 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -98,13 +98,12 @@ extern const struct dpll_regs dpll_mpu_regs; extern const struct dpll_regs dpll_core_regs; extern const struct dpll_regs dpll_per_regs; extern const struct dpll_regs dpll_ddr_regs; -extern const struct dpll_params dpll_mpu; -extern const struct dpll_params dpll_core; -extern const struct dpll_params dpll_per; -extern const struct dpll_params dpll_ddr; extern struct cm_wkuppll *const cmwkup; +const struct dpll_params *get_dpll_mpu_params(void); +const struct dpll_params *get_dpll_core_params(void); +const struct dpll_params *get_dpll_per_params(void); const struct dpll_params *get_dpll_ddr_params(void); void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); void prcm_init(void); diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 19b84690a19..3ee37dc4e79 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -480,6 +480,8 @@ struct ctrl_stat { unsigned int statusreg; /* ofset 0x40 */ unsigned int resv2[51]; unsigned int secure_emif_sdram_config; /* offset 0x0110 */ + unsigned int resv3[319]; + unsigned int dev_attr; }; /* AM33XX GPIO registers */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 0a3f8ee32a8..468521bf34b 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -63,4 +63,17 @@ #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) #define USBPHYOCPSCP_MODULE_EN (1 << 1) +/* Control status register */ +#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) +#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31 +#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29) +#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29 +#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22) +#define CTRL_SYSBOOT_15_14_SHIFT 22 + +#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0 +#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1 + +#define NUM_CRYSTAL_FREQ 0x4 + #endif /* __AM43XX_HARDWARE_AM43XX_H */ diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 723d0ca3274..5c92ac7f30d 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -65,12 +65,144 @@ static int read_eeprom(struct am43xx_board_id *header) #ifdef CONFIG_SPL_BUILD -const struct dpll_params dpll_ddr = { - -1, -1, -1, -1, -1, -1, -1}; +#define NUM_OPPS 6 + +const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { + { /* 19.2 MHz */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */ + {-1, -1, -1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 24 MHz */ + {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 25 MHz */ + {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 26 MHz */ + {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ + }, +}; + +const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { + {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ + {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ + {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ +}; + +const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { + {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */ + {960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */ + {960, 25, 5, -1, -1, -1, -1} /* 26 MHz */ +}; + +const struct dpll_params epos_evm_dpll_ddr = { + 266, 24, 1, -1, 1, -1, -1}; + +const struct dpll_params gp_evm_dpll_ddr = { + 400, 23, 1, -1, 1, -1, -1}; const struct dpll_params *get_dpll_ddr_params(void) { - return &dpll_ddr; + struct am43xx_board_id header; + + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + if (board_is_eposevm()) + return &epos_evm_dpll_ddr; + else if (board_is_gpevm()) + return &gp_evm_dpll_ddr; + + puts(" Board not supported\n"); + return NULL; +} + +/* + * get_sys_clk_index : returns the index of the sys_clk read from + * ctrl status register. This value is either + * read from efuse or sysboot pins. + */ +static u32 get_sys_clk_index(void) +{ + struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; + u32 ind = readl(&ctrl->statusreg), src; + + src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT; + if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */ + return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >> + CTRL_CRYSTAL_FREQ_SELECTION_SHIFT); + else /* Value read from SYS BOOT pins */ + return ((ind & CTRL_SYSBOOT_15_14_MASK) >> + CTRL_SYSBOOT_15_14_SHIFT); +} + +/* + * get_opp_offset: + * Returns the index for safest OPP of the device to boot. + * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. + * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. + * This data is read from dev_attribute register which is e-fused. + * A'1' in bit indicates OPP disabled and not available, a '0' indicates + * OPP available. Lowest OPP starts with min_off. So returning the + * bit with rightmost '0'. + */ +static int get_opp_offset(int max_off, int min_off) +{ + struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; + int opp = readl(&ctrl->dev_attr), offset, i; + + for (i = max_off; i >= min_off; i--) { + offset = opp & (1 << i); + if (!offset) + return i; + } + + return min_off; +} + +const struct dpll_params *get_dpll_mpu_params(void) +{ + int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); + u32 ind = get_sys_clk_index(); + + return &dpll_mpu[ind][opp]; +} + +const struct dpll_params *get_dpll_core_params(void) +{ + int ind = get_sys_clk_index(); + + return &dpll_core[ind]; +} + +const struct dpll_params *get_dpll_per_params(void) +{ + int ind = get_sys_clk_index(); + + return &dpll_per[ind]; } void set_uart_mux_conf(void) diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h index 92688956593..091162ee20f 100644 --- a/board/ti/am43xx/board.h +++ b/board/ti/am43xx/board.h @@ -25,6 +25,9 @@ static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START; #define HDR_ETH_ALEN 6 #define HDR_NAME_LEN 8 +#define DEV_ATTR_MAX_OFFSET 5 +#define DEV_ATTR_MIN_OFFSET 0 + struct am43xx_board_id { unsigned int magic; char name[HDR_NAME_LEN]; @@ -46,4 +49,5 @@ static inline int board_is_gpevm(void) void enable_uart0_pin_mux(void); void enable_board_pin_mux(void); +void enable_i2c0_pin_mux(void); #endif diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 46bad0199d8..a2d72dde5f5 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -43,3 +43,8 @@ void enable_board_pin_mux(void) configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(i2c0_pin_mux); } + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} -- cgit v1.3.1 From 965de8b91bddd1f5967240d1d44005719b09dd5e Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:21 +0530 Subject: ARM: AM33xx+: Update ioregs to pass different values Currently same value is programmed for all ioregs. This is not the case for all SoC's like AM4372. So adding a structure for ioregs and updating in all board files. And also return from config_cmd_ctrl() and config_ddr_data() functions if data is not passed. Signed-off-by: Lokesh Vutla [trini: Fixup dxr2, cm_t335, adapt pcm051 rev3] Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/ddr.c | 27 ++++++++++++++++++++------ arch/arm/cpu/armv7/am33xx/emif4.c | 5 ++--- board/compulab/cm_t335/spl.c | 10 +++++++++- board/isee/igep0033/board.c | 10 +++++++++- board/phytec/pcm051/board.c | 20 ++++++++++++++++++-- board/siemens/dxr2/board.c | 12 +++++++++++- board/siemens/pxm2/board.c | 10 +++++++++- board/siemens/rut/board.c | 10 +++++++++- board/ti/am335x/board.c | 40 +++++++++++++++++++++++++++++++++++---- board/ti/ti814x/evm.c | 4 ++-- board/ti/ti816x/evm.c | 12 ++++++++---- 11 files changed, 134 insertions(+), 26 deletions(-) (limited to 'board') diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 5b0454c3eab..255f333b692 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -88,6 +88,9 @@ void config_ddr_phy(const struct emif_regs *regs, int nr) */ void config_cmd_ctrl(const struct cmd_control *cmd, int nr) { + if (!cmd) + return; + writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio); writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout); @@ -105,6 +108,9 @@ void config_ddr_data(const struct ddr_data *data, int nr) { int i; + if (!data) + return; + for (i = 0; i < DDR_DATA_REGS_NR; i++) { writel(data->datardsratio0, &(ddr_data_reg[nr]+i)->dt0rdsratio0); @@ -121,11 +127,20 @@ void config_ddr_data(const struct ddr_data *data, int nr) } } -void config_io_ctrl(unsigned long val) +void config_io_ctrl(const struct ctrl_ioregs *ioregs) { - writel(val, &ioctrl_reg->cm0ioctl); - writel(val, &ioctrl_reg->cm1ioctl); - writel(val, &ioctrl_reg->cm2ioctl); - writel(val, &ioctrl_reg->dt0ioctl); - writel(val, &ioctrl_reg->dt1ioctl); + if (!ioregs) + return; + + writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl); + writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl); + writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl); + writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl); + writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl); +#ifdef CONFIG_AM43XX + writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl); + writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl); + writel(ioregs->emif_sdram_config_ext, + &ioctrl_reg->emif_sdram_config_ext); +#endif } diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 59ad25c5b09..adda650fe8d 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -87,7 +87,7 @@ void __weak ddr_pll_config(unsigned int ddrpll_m) { } -void config_ddr(unsigned int pll, unsigned int ioctrl, +void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr) { @@ -99,12 +99,11 @@ void config_ddr(unsigned int pll, unsigned int ioctrl, config_ddr_data(data, nr); #ifdef CONFIG_AM33XX - config_io_ctrl(ioctrl); + config_io_ctrl(ioregs); /* Set CKE to be controlled by EMIF/DDR PHY */ writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); #endif - /* Program EMIF instance */ config_ddr_phy(regs, nr); set_sdram_timings(regs, nr); diff --git a/board/compulab/cm_t335/spl.c b/board/compulab/cm_t335/spl.c index 99f3a869bbc..b3b150a577a 100644 --- a/board/compulab/cm_t335/spl.c +++ b/board/compulab/cm_t335/spl.c @@ -20,6 +20,14 @@ #include #include +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, +}; + static const struct ddr_data ddr3_data = { .datardsratio0 = MT41J128MJT125_RD_DQS, .datawdsratio0 = MT41J128MJT125_WR_DQS, @@ -89,7 +97,7 @@ static void probe_sdram_size(long size) reset_cpu(0); } debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20); - config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, + config_ddr(303, &ioregs, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); } diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index 6a8ca2b4c39..089a835e0c6 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -77,9 +77,17 @@ void set_mux_conf_regs(void) enable_board_pin_mux(); } +const struct ctrl_ioregs ioregs = { + .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, + .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, + .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, + .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, + .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, +}; + void sdram_init(void) { - config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data, + config_ddr(400, &ioregs, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); } #endif diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 68463e78dbf..7e5e07ff232 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -50,6 +50,14 @@ const struct dpll_params *get_dpll_ddr_params(void) } #ifdef CONFIG_REV1 +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT41J256M8HX15E_IOCTRL_VALUE, + .cm1ioctl = MT41J256M8HX15E_IOCTRL_VALUE, + .cm2ioctl = MT41J256M8HX15E_IOCTRL_VALUE, + .dt0ioctl = MT41J256M8HX15E_IOCTRL_VALUE, + .dt1ioctl = MT41J256M8HX15E_IOCTRL_VALUE, +}; + static const struct ddr_data ddr3_data = { .datardsratio0 = MT41J256M8HX15E_RD_DQS, .datawdsratio0 = MT41J256M8HX15E_WR_DQS, @@ -81,10 +89,18 @@ static struct emif_regs ddr3_emif_reg_data = { void sdram_init(void) { - config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data, + config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); } #else +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + static const struct ddr_data ddr3_data = { .datardsratio0 = MT41K256M16HA125E_RD_DQS, .datawdsratio0 = MT41K256M16HA125E_WR_DQS, @@ -116,7 +132,7 @@ static struct emif_regs ddr3_emif_reg_data = { void sdram_init(void) { - config_ddr(DDR_CLK_MHZ, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_data, + config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); } #endif diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c index 3a5e11dc816..6c316faa8f1 100644 --- a/board/siemens/dxr2/board.c +++ b/board/siemens/dxr2/board.c @@ -144,6 +144,10 @@ struct ddr_data dxr2_ddr3_data = { struct cmd_control dxr2_ddr3_cmd_ctrl_data = { }; + +struct ctrl_ioregs dxr2_ddr3_ioregs = { +}; + /* pass values from eeprom */ dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1; dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2; @@ -165,7 +169,13 @@ struct cmd_control dxr2_ddr3_cmd_ctrl_data = { dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio; dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout; - config_ddr(DDR_PLL_FREQ, settings.ddr3.ioctr_val, &dxr2_ddr3_data, + dxr2_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val, + dxr2_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val, + dxr2_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val, + dxr2_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val, + dxr2_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val, + + config_ddr(DDR_PLL_FREQ, &dxr2_ddr3_ioregs, &dxr2_ddr3_data, &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0); } diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c index 0a25b4b40cc..ef3d6cc158d 100644 --- a/board/siemens/pxm2/board.c +++ b/board/siemens/pxm2/board.c @@ -69,7 +69,15 @@ struct cmd_control pxm2_ddr3_cmd_ctrl_data = { .cmd2iclkout = 0, }; - config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &pxm2_ddr3_data, +const struct ctrl_ioregs ioregs = { + .cm0ioctl = DXR2_IOCTRL_VAL, + .cm1ioctl = DXR2_IOCTRL_VAL, + .cm2ioctl = DXR2_IOCTRL_VAL, + .dt0ioctl = DXR2_IOCTRL_VAL, + .dt1ioctl = DXR2_IOCTRL_VAL, +}; + + config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data, &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0); } diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c index 77592dbba88..25ab54d9a2a 100644 --- a/board/siemens/rut/board.c +++ b/board/siemens/rut/board.c @@ -74,7 +74,15 @@ struct cmd_control rut_ddr3_cmd_ctrl_data = { .cmd2iclkout = 1, }; - config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data, +const struct ctrl_ioregs ioregs = { + .cm0ioctl = RUT_IOCTRL_VAL, + .cm1ioctl = RUT_IOCTRL_VAL, + .cm2ioctl = RUT_IOCTRL_VAL, + .dt0ioctl = RUT_IOCTRL_VAL, + .dt1ioctl = RUT_IOCTRL_VAL, +}; + + config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data, &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0); } diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 33693e4ead5..57217688d63 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -426,6 +426,38 @@ void set_mux_conf_regs(void) enable_board_pin_mux(&header); } +const struct ctrl_ioregs ioregs_evmsk = { + .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, +}; + +const struct ctrl_ioregs ioregs_bonelt = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +const struct ctrl_ioregs ioregs_evm15 = { + .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE, +}; + +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, +}; + void sdram_init(void) { __maybe_unused struct am335x_baseboard_id header; @@ -443,18 +475,18 @@ void sdram_init(void) } if (board_is_evm_sk(&header)) - config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, + config_ddr(303, &ioregs_evmsk, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); else if (board_is_bone_lt(&header)) - config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE, + config_ddr(400, &ioregs_bonelt, &ddr3_beagleblack_data, &ddr3_beagleblack_cmd_ctrl_data, &ddr3_beagleblack_emif_reg_data, 0); else if (board_is_evm_15_or_later(&header)) - config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data, + config_ddr(303, &ioregs_evm15, &ddr3_evm_data, &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); else - config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, + config_ddr(266, &ioregs, &ddr2_data, &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); } #endif diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index 0b76a779059..140ad7103ad 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -95,9 +95,9 @@ void sdram_init(void) { config_dmm(&evm_lisa_map_regs); - config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, + config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data, &evm_ddr2_emif0_regs, 0); - config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, + config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data, &evm_ddr2_emif1_regs, 1); } #endif diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c index a53859e52e4..b6bf16236f4 100644 --- a/board/ti/ti816x/evm.c +++ b/board/ti/ti816x/evm.c @@ -191,22 +191,26 @@ void sdram_init(void) if (CONFIG_TI816X_USE_EMIF0) { ddr2_emif0_regs.emif_ddr_phy_ctlr_1 = (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); - config_ddr(0, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, 0); + config_ddr(0, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, + 0); } if (CONFIG_TI816X_USE_EMIF1) { ddr2_emif1_regs.emif_ddr_phy_ctlr_1 = (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); - config_ddr(1, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, 1); + config_ddr(1, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, + 1); } #endif #ifdef CONFIG_TI816X_EVM_DDR3 if (CONFIG_TI816X_USE_EMIF0) - config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0); + config_ddr(0, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, + 0); if (CONFIG_TI816X_USE_EMIF1) - config_ddr(1, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, 1); + config_ddr(1, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, + 1); #endif } #endif /* CONFIG_SPL_BUILD */ -- cgit v1.3.1 From d3daba10f159cca7e9d24c6f154926a9b92c75e3 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:22 +0530 Subject: ARM: AM43xx: EPOS_EVM: Add support for LPDDR2 AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/am33xx/ddr.c | 117 +++++++++++++++++++++ arch/arm/cpu/armv7/am33xx/emif4.c | 22 +++- arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | 3 + arch/arm/include/asm/arch-am33xx/cpu.h | 5 + arch/arm/include/asm/arch-am33xx/ddr_defs.h | 33 +++++- arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 1 + arch/arm/include/asm/emif.h | 12 +++ board/ti/am43xx/board.c | 66 ++++++++++++ 8 files changed, 256 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 255f333b692..1abbb07c961 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -36,6 +36,71 @@ static struct ddr_data_regs *ddr_data_reg[2] = { static struct ddr_cmdtctrl *ioctrl_reg = { (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR}; +static inline u32 get_mr(int nr, u32 cs, u32 mr_addr) +{ + u32 mr; + + mr_addr |= cs << EMIF_REG_CS_SHIFT; + writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); + + mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data); + debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr); + if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && + ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && + ((mr & 0xff000000) >> 24) == (mr & 0xff)) + return mr & 0xff; + else + return mr; +} + +static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val) +{ + mr_addr |= cs << EMIF_REG_CS_SHIFT; + writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); + writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data); +} + +static void configure_mr(int nr, u32 cs) +{ + u32 mr_addr; + + while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) + ; + set_mr(nr, cs, LPDDR2_MR10, 0x56); + + set_mr(nr, cs, LPDDR2_MR1, 0x43); + set_mr(nr, cs, LPDDR2_MR2, 0x2); + + mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK; + set_mr(nr, cs, mr_addr, 0x2); +} + +/* + * Configure EMIF4D5 registers and MR registers + */ +void config_sdram_emif4d5(const struct emif_regs *regs, int nr) +{ + writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl); + writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw); + writel(0x1, &emif_reg[nr]->emif_iodft_tlgc); + writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); + + writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config); + writel(regs->emif_rd_wr_lvl_rmp_win, + &emif_reg[nr]->emif_rd_wr_lvl_rmp_win); + writel(regs->emif_rd_wr_lvl_rmp_ctl, + &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl); + writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl); + writel(regs->emif_rd_wr_exec_thresh, + &emif_reg[nr]->emif_rd_wr_exec_thresh); + + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); + + configure_mr(nr, 0); + configure_mr(nr, 1); +} + /** * Configure SDRAM */ @@ -72,15 +137,67 @@ void set_sdram_timings(const struct emif_regs *regs, int nr) writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw); } +void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) +{ +} + +/* + * Configure EXT PHY registers + */ +static void ext_phy_settings(const struct emif_regs *regs, int nr) +{ + u32 *ext_phy_ctrl_base = 0; + u32 *emif_ext_phy_ctrl_base = 0; + const u32 *ext_phy_ctrl_const_regs; + u32 i = 0; + u32 size; + + ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1); + emif_ext_phy_ctrl_base = + (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); + + /* Configure external phy control timing registers */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { + writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); + } + + /* + * external phy 6-24 registers do not change with + * ddr frequency + */ + emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size); + + if (!size) + return; + + for (i = 0; i < size; i++) { + writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); + } +} + /** * Configure DDR PHY */ void config_ddr_phy(const struct emif_regs *regs, int nr) { + /* + * disable initialization and refreshes for now until we + * finish programming EMIF regs. + */ + setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl, + EMIF_REG_INITREF_DIS_MASK); + writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1); writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw); + + if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) + ext_phy_settings(regs, nr); } /** diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index adda650fe8d..d28fceb75cf 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -48,6 +48,11 @@ static struct vtp_reg *vtpreg[2] = { #ifdef CONFIG_AM33XX static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; #endif +#ifdef CONFIG_AM43XX +static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; +static struct cm_device_inst *cm_device = + (struct cm_device_inst *)CM_DEVICE_INST; +#endif #ifdef CONFIG_TI81XX void config_dmm(const struct dmm_lisa_map_regs *regs) @@ -104,9 +109,24 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, /* Set CKE to be controlled by EMIF/DDR PHY */ writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); #endif +#ifdef CONFIG_AM43XX + writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl); + while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0) + ; + writel(0x0, &ddrctrl->ddrioctrl); + + config_io_ctrl(ioregs); + + /* Set CKE to be controlled by EMIF/DDR PHY */ + writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); +#endif + /* Program EMIF instance */ config_ddr_phy(regs, nr); set_sdram_timings(regs, nr); - config_sdram(regs, nr); + if (get_emif_rev(EMIF1_BASE) == EMIF_4D5) + config_sdram_emif4d5(regs, nr); + else + config_sdram(regs, nr); } #endif diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 02ed5957e98..4c9352a2ed7 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -28,6 +28,9 @@ #define UART_CLK_RUNNING_MASK 0x1 #define UART_SMART_IDLE_EN (0x1 << 0x3) +#define CM_DLL_CTRL_NO_OVERRIDE 0x0 +#define CM_DLL_READYST 0x4 + extern void enable_dmm_clocks(void); extern const struct dpll_params dpll_core_opp100; extern struct dpll_params dpll_mpu_opp100; diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 3ee37dc4e79..9febfa2719a 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -401,6 +401,11 @@ struct cm_perpll { unsigned int cpgmac0clkctrl; /* offset 0xB20 */ }; +struct cm_device_inst { + unsigned int cm_clkout1_ctrl; + unsigned int cm_dll_ctrl; +}; + struct cm_dpll { unsigned int resv1; unsigned int clktimer2clk; /* offset 0x04 */ diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 2278358ab20..6af4b84e568 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -18,7 +18,11 @@ #define VTP_CTRL_READY (0x1 << 5) #define VTP_CTRL_ENABLE (0x1 << 6) #define VTP_CTRL_START_EN (0x1) +#ifdef CONFIG_AM43XX +#define DDR_CKE_CTRL_NORMAL 0x3 +#else #define DDR_CKE_CTRL_NORMAL 0x1 +#endif #define PHY_EN_DYN_PWRDN (0x1 << 20) /* Micron MT47H128M16RT-25E */ @@ -124,6 +128,14 @@ #define K4B2G1646EBIH9_PHY_WR_DATA 0x76 #define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B +#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294 +#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 +#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 +#define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294 + /** * Configure DMM */ @@ -133,6 +145,7 @@ void config_dmm(const struct dmm_lisa_map_regs *regs); * Configure SDRAM */ void config_sdram(const struct emif_regs *regs, int nr); +void config_sdram_emif4d5(const struct emif_regs *regs, int nr); /** * Set SDRAM timings @@ -278,12 +291,27 @@ struct ddr_cmdtctrl { unsigned int resv2[12]; unsigned int dt0ioctl; unsigned int dt1ioctl; + unsigned int dt2ioctrl; + unsigned int dt3ioctrl; + unsigned int resv3[4]; + unsigned int emif_sdram_config_ext; +}; + +struct ctrl_ioregs { + unsigned int cm0ioctl; + unsigned int cm1ioctl; + unsigned int cm2ioctl; + unsigned int dt0ioctl; + unsigned int dt1ioctl; + unsigned int dt2ioctrl; + unsigned int dt3ioctrl; + unsigned int emif_sdram_config_ext; }; /** * Configure DDR io control registers */ -void config_io_ctrl(unsigned long val); +void config_io_ctrl(const struct ctrl_ioregs *ioregs); struct ddr_ctrl { unsigned int ddrioctrl; @@ -291,8 +319,9 @@ struct ddr_ctrl { unsigned int ddrckectrl; }; -void config_ddr(unsigned int pll, unsigned int ioctrl, +void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr); +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size); #endif /* _DDR_DEFS_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 468521bf34b..15399dcc747 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -62,6 +62,7 @@ #define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8) #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) #define USBPHYOCPSCP_MODULE_EN (1 << 1) +#define CM_DEVICE_INST 0x44df4100 /* Control status register */ #define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index d9d521a5150..e68c113e280 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -14,11 +14,15 @@ #define _EMIF_H_ #include #include +#include /* Base address */ #define EMIF1_BASE 0x4c000000 #define EMIF2_BASE 0x4d000000 +#define EMIF_4D 0x4 +#define EMIF_4D5 0x5 + /* Registers shifts, masks and values */ /* EMIF_MOD_ID_REV */ @@ -1148,6 +1152,14 @@ struct read_write_regs { u32 write_reg; }; +static inline u32 get_emif_rev(u32 base) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK) + >> EMIF_REG_MAJOR_REVISION_SHIFT; +} + /* assert macros */ #if defined(DEBUG) #define emif_assert(c) ({ if (!(c)) for (;;); }) diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 5c92ac7f30d..5a013e33845 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include "board.h" DECLARE_GLOBAL_DATA_PTR; @@ -122,6 +124,69 @@ const struct dpll_params epos_evm_dpll_ddr = { const struct dpll_params gp_evm_dpll_ddr = { 400, 23, 1, -1, 1, -1, -1}; +const struct ctrl_ioregs ioregs_lpddr2 = { + .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, + .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, + .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, + .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, + .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, + .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, + .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, + .emif_sdram_config_ext = 0x1, +}; + +const struct emif_regs emif_regs_lpddr2 = { + .sdram_config = 0x808012BA, + .ref_ctrl = 0x0000040D, + .sdram_tim1 = 0xEA86B411, + .sdram_tim2 = 0x103A094A, + .sdram_tim3 = 0x0F6BA37F, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_rd_wr_lvl_rmp_win = 0x0, + .emif_rd_wr_lvl_rmp_ctl = 0x0, + .emif_rd_wr_lvl_ctl = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E084006, + .emif_rd_wr_exec_thresh = 0x00000405, + .emif_ddr_ext_phy_ctrl_1 = 0x04010040, + .emif_ddr_ext_phy_ctrl_2 = 0x00500050, + .emif_ddr_ext_phy_ctrl_3 = 0x00500050, + .emif_ddr_ext_phy_ctrl_4 = 0x00500050, + .emif_ddr_ext_phy_ctrl_5 = 0x00500050 +}; + +const u32 ext_phy_ctrl_const_base_lpddr2[] = { + 0x00500050, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40001000, + 0x08102040 +}; + +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) +{ + *regs = ext_phy_ctrl_const_base_lpddr2; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); + + return; +} + const struct dpll_params *get_dpll_ddr_params(void) { struct am43xx_board_id header; @@ -217,6 +282,7 @@ void set_mux_conf_regs(void) void sdram_init(void) { + config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); } #endif -- cgit v1.3.1 From b5e01eecc89e3e5c2ed3c17b803529be3c3702fb Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:23 +0530 Subject: ARM: AM43xx: GP_EVM: Add support for DDR3 GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/am33xx/ddr.c | 6 +- arch/arm/cpu/armv7/omap-common/emif-common.c | 14 ----- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 8 +++ arch/arm/include/asm/arch-am33xx/gpio.h | 12 ++++ arch/arm/include/asm/emif.h | 14 +++++ board/ti/am43xx/board.c | 93 +++++++++++++++++++++++++++- board/ti/am43xx/mux.c | 8 +++ 7 files changed, 136 insertions(+), 19 deletions(-) (limited to 'board') diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 1abbb07c961..d05e666a742 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -97,8 +97,10 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); - configure_mr(nr, 0); - configure_mr(nr, 1); + if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) { + configure_mr(nr, 0); + configure_mr(nr, 1); + } } /** diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 5a3f2858cda..cd6289b4fca 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -50,20 +50,6 @@ inline u32 emif_num(u32 base) return 0; } -/* - * Get SDRAM type connected to EMIF. - * Assuming similar SDRAM parts are connected to both EMIF's - * which is typically the case. So it is sufficient to get - * SDRAM type from EMIF1. - */ -u32 emif_sdram_type() -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; - - return (readl(&emif->emif_sdram_config) & - EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT; -} - static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) { u32 mr; diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 6af4b84e568..c1777dfdc96 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -136,6 +136,14 @@ #define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 #define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294 +#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84 +#define DDR3_DATA0_IOCTRL_VALUE 0x84 +#define DDR3_DATA1_IOCTRL_VALUE 0x84 +#define DDR3_DATA2_IOCTRL_VALUE 0x84 +#define DDR3_DATA3_IOCTRL_VALUE 0x84 + /** * Configure DMM */ diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h b/arch/arm/include/asm/arch-am33xx/gpio.h index 13a047fd72e..a1ffd49f795 100644 --- a/arch/arm/include/asm/arch-am33xx/gpio.h +++ b/arch/arm/include/asm/arch-am33xx/gpio.h @@ -13,4 +13,16 @@ #define AM33XX_GPIO2_BASE 0x481AC000 #define AM33XX_GPIO3_BASE 0x481AE000 +#define GPIO_22 22 + +/* GPIO CTRL register */ +#define GPIO_CTRL_DISABLEMODULE_SHIFT 0 +#define GPIO_CTRL_DISABLEMODULE_MASK (1 << 0) +#define GPIO_CTRL_ENABLEMODULE GPIO_CTRL_DISABLEMODULE_MASK + +/* GPIO OUTPUT ENABLE register */ +#define GPIO_OE_ENABLE(x) (1 << x) + +/* GPIO SETDATAOUT register */ +#define GPIO_SETDATAOUT(x) (1 << x) #endif /* _GPIO_AM33xx_H */ diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index e68c113e280..45668ca4dd7 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -1160,6 +1160,20 @@ static inline u32 get_emif_rev(u32 base) >> EMIF_REG_MAJOR_REVISION_SHIFT; } +/* + * Get SDRAM type connected to EMIF. + * Assuming similar SDRAM parts are connected to both EMIF's + * which is typically the case. So it is sufficient to get + * SDRAM type from EMIF1. + */ +static inline u32 emif_sdram_type(void) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + + return (readl(&emif->emif_sdram_config) & + EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT; +} + /* assert macros */ #if defined(DEBUG) #define emif_assert(c) ({ if (!(c)) for (;;); }) diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 5a013e33845..ed87cd97b0d 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include "board.h" @@ -179,10 +180,70 @@ const u32 ext_phy_ctrl_const_base_lpddr2[] = { 0x08102040 }; +const struct ctrl_ioregs ioregs_ddr3 = { + .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, + .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, + .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, + .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .emif_sdram_config_ext = 0x0043, +}; + +const struct emif_regs ddr3_emif_regs_400Mhz = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E084008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00400040, + .emif_ddr_ext_phy_ctrl_3 = 0x00400040, + .emif_ddr_ext_phy_ctrl_4 = 0x00400040, + .emif_ddr_ext_phy_ctrl_5 = 0x00400040, + .emif_rd_wr_lvl_rmp_win = 0x0, + .emif_rd_wr_lvl_rmp_ctl = 0x0, + .emif_rd_wr_lvl_ctl = 0x0, + .emif_rd_wr_exec_thresh = 0x00000405 +}; + +const u32 ext_phy_ctrl_const_base_ddr3[] = { + 0x00400040, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00340034, + 0x00340034, + 0x00340034, + 0x00340034, + 0x00340034, + 0x0, + 0x0, + 0x40000000, + 0x08102040 +}; + void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) { - *regs = ext_phy_ctrl_const_base_lpddr2; - *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); + if (board_is_eposevm()) { + *regs = ext_phy_ctrl_const_base_lpddr2; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); + } else if (board_is_gpevm()) { + *regs = ext_phy_ctrl_const_base_ddr3; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); + } return; } @@ -280,9 +341,35 @@ void set_mux_conf_regs(void) enable_board_pin_mux(); } +static void enable_vtt_regulator(void) +{ + u32 temp; + + /* enable module */ + writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO0_BASE + OMAP_GPIO_CTRL); + + /* enable output for GPIO0_22 */ + writel(GPIO_SETDATAOUT(GPIO_22), + AM33XX_GPIO0_BASE + OMAP_GPIO_SETDATAOUT); + temp = readl(AM33XX_GPIO0_BASE + OMAP_GPIO_OE); + temp = temp & ~(GPIO_OE_ENABLE(GPIO_22)); + writel(temp, AM33XX_GPIO0_BASE + OMAP_GPIO_OE); +} + void sdram_init(void) { - config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); + /* + * EPOS EVM has 1GB LPDDR2 connected to EMIF. + * GP EMV has 1GB DDR3 connected to EMIF + * along with VTT regulator. + */ + if (board_is_eposevm()) { + config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); + } else if (board_is_gpevm()) { + enable_vtt_regulator(); + config_ddr(0, &ioregs_ddr3, NULL, NULL, + &ddr3_emif_regs_400Mhz, 0); + } } #endif diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index a2d72dde5f5..810b1941db9 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -33,6 +33,11 @@ static struct module_pin_mux i2c0_pin_mux[] = { {-1}, }; +static struct module_pin_mux gpio0_22_pin_mux[] = { + {OFFSET(ddr_ba2), (MODE(9) | PULLUP_EN)}, /* GPIO0_22 */ + {-1}, +}; + void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); @@ -42,6 +47,9 @@ void enable_board_pin_mux(void) { configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(i2c0_pin_mux); + + if (board_is_gpevm()) + configure_module_pin_mux(gpio0_22_pin_mux); } void enable_i2c0_pin_mux(void) -- cgit v1.3.1 From 71ebb33559696ca41fe0db5fa882112464ade9c0 Mon Sep 17 00:00:00 2001 From: Rajeshwari Birje Date: Thu, 26 Dec 2013 09:44:17 +0530 Subject: EXYNOS5: Create a common board file Create a common board.c file for all functions which are common across all EXYNOS5 platforms. exynos_init function is provided for platform specific code. Signed-off-by: Rajeshwari S Shinde Acked-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/include/asm/arch-exynos/board.h | 17 ++ board/samsung/common/Makefile | 4 + board/samsung/common/board.c | 409 +++++++++++++++++++++++++++++++ board/samsung/smdk5250/exynos5-dt.c | 350 +------------------------- board/samsung/smdk5250/smdk5250.c | 182 +------------- include/configs/exynos5250-dt.h | 2 + 6 files changed, 437 insertions(+), 527 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/board.h create mode 100644 board/samsung/common/board.c (limited to 'board') diff --git a/arch/arm/include/asm/arch-exynos/board.h b/arch/arm/include/asm/arch-exynos/board.h new file mode 100644 index 00000000000..243fb12b76c --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/board.h @@ -0,0 +1,17 @@ +/* + * (C) Copyright 2013 Samsung Electronics + * Rajeshwari Shinde + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _EXYNOS_BOARD_H +#define _EXYNOS_BOARD_H + +/* + * Exynos baord specific changes for + * board_init + */ +int exynos_init(void); + +#endif /* EXYNOS_BOARD_H */ diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile index 501d9744e4f..22bd6b197e5 100644 --- a/board/samsung/common/Makefile +++ b/board/samsung/common/Makefile @@ -8,3 +8,7 @@ obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o obj-$(CONFIG_THOR_FUNCTION) += thor.o obj-$(CONFIG_CMD_USB_MASS_STORAGE) += ums.o + +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_BOARD_COMMON) += board.o +endif diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c new file mode 100644 index 00000000000..dc68e3a8737 --- /dev/null +++ b/board/samsung/common/board.c @@ -0,0 +1,409 @@ +/* + * (C) Copyright 2013 SAMSUNG Electronics + * Rajeshwari Shinde + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct local_info { + struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */ + int cros_ec_err; /* Error for cros_ec, 0 if ok */ +}; + +static struct local_info local; + +#if defined CONFIG_EXYNOS_TMU +/* Boot Time Thermal Analysis for SoC temperature threshold breach */ +static void boot_temp_check(void) +{ + int temp; + + switch (tmu_monitor(&temp)) { + case TMU_STATUS_NORMAL: + break; + case TMU_STATUS_TRIPPED: + /* + * Status TRIPPED ans WARNING means corresponding threshold + * breach + */ + puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n"); + set_ps_hold_ctrl(); + hang(); + break; + case TMU_STATUS_WARNING: + puts("EXYNOS_TMU: WARNING! Temperature very high\n"); + break; + case TMU_STATUS_INIT: + /* + * TMU_STATUS_INIT means something is wrong with temperature + * sensing and TMU status was changed back from NORMAL to INIT. + */ + puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n"); + break; + default: + debug("EXYNOS_TMU: Unknown TMU state\n"); + } +} +#endif + +int board_init(void) +{ + gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); +#if defined CONFIG_EXYNOS_TMU + if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { + debug("%s: Failed to init TMU\n", __func__); + return -1; + } + boot_temp_check(); +#endif + +#ifdef CONFIG_EXYNOS_SPI + spi_init(); +#endif + return exynos_init(); +} + +int dram_init(void) +{ + int i; + u32 addr; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); + } + return 0; +} + +void dram_init_banksize(void) +{ + int i; + u32 addr, size; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); + + gd->bd->bi_dram[i].start = addr; + gd->bd->bi_dram[i].size = size; + } +} + +static int board_uart_init(void) +{ + int err, uart_id, ret = 0; + + for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { + err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); + if (err) { + debug("UART%d not configured\n", + (uart_id - PERIPH_ID_UART0)); + ret |= err; + } + } + return ret; +} + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + int err; + + err = board_uart_init(); + if (err) { + debug("UART init failed\n"); + return err; + } + +#ifdef CONFIG_SYS_I2C_INIT_BOARD + board_i2c_init(gd->fdt_blob); +#endif + + return err; +} +#endif + +struct cros_ec_dev *board_get_cros_ec_dev(void) +{ + return local.cros_ec_dev; +} + +static int board_init_cros_ec_devices(const void *blob) +{ + local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev); + if (local.cros_ec_err) + return -1; /* Will report in board_late_init() */ + + return 0; +} + +#if defined(CONFIG_POWER) +#ifdef CONFIG_POWER_MAX77686 +static int pmic_reg_update(struct pmic *p, int reg, uint regval) +{ + u32 val; + int ret = 0; + + ret = pmic_reg_read(p, reg, &val); + if (ret) { + debug("%s: PMIC %d register read failed\n", __func__, reg); + return -1; + } + val |= regval; + ret = pmic_reg_write(p, reg, val); + if (ret) { + debug("%s: PMIC %d register write failed\n", __func__, reg); + return -1; + } + return 0; +} + +static int max77686_init(void) +{ + struct pmic *p; + + if (pmic_init(I2C_PMIC)) + return -1; + + p = pmic_get("MAX77686_PMIC"); + if (!p) + return -ENODEV; + + if (pmic_probe(p)) + return -1; + + if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) + return -1; + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, + MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) + return -1; + + /* VDD_MIF */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, + MAX77686_BUCK1OUT_1V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK1OUT); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, + MAX77686_BUCK1CTRL_EN)) + return -1; + + /* VDD_ARM */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, + MAX77686_BUCK2DVS1_1_3V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK2DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, + MAX77686_BUCK2CTRL_ON)) + return -1; + + /* VDD_INT */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, + MAX77686_BUCK3DVS1_1_0125V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK3DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, + MAX77686_BUCK3CTRL_ON)) + return -1; + + /* VDD_G3D */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, + MAX77686_BUCK4DVS1_1_2V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK4DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, + MAX77686_BUCK3CTRL_ON)) + return -1; + + /* VDD_LDO2 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, + MAX77686_LD02CTRL1_1_5V | EN_LDO)) + return -1; + + /* VDD_LDO3 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, + MAX77686_LD03CTRL1_1_8V | EN_LDO)) + return -1; + + /* VDD_LDO5 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, + MAX77686_LD05CTRL1_1_8V | EN_LDO)) + return -1; + + /* VDD_LDO10 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, + MAX77686_LD10CTRL1_1_8V | EN_LDO)) + return -1; + + return 0; +} +#endif + +int power_init_board(void) +{ + int ret = 0; + + set_ps_hold_ctrl(); + +#ifdef CONFIG_POWER_MAX77686 + ret = max77686_init(); +#endif + + return ret; +} +#endif + +#ifdef CONFIG_OF_CONTROL +static int decode_sromc(const void *blob, struct fdt_sromc *config) +{ + int err; + int node; + + node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC); + if (node < 0) { + debug("Could not find SROMC node\n"); + return node; + } + + config->bank = fdtdec_get_int(blob, node, "bank", 0); + config->width = fdtdec_get_int(blob, node, "width", 2); + + err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing, + FDT_SROM_TIMING_COUNT); + if (err < 0) { + debug("Could not decode SROMC configuration Error: %s\n", + fdt_strerror(err)); + return -FDT_ERR_NOTFOUND; + } + return 0; +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SMC911X + u32 smc_bw_conf, smc_bc_conf; + struct fdt_sromc config; + fdt_addr_t base_addr; + int node; + + node = decode_sromc(gd->fdt_blob, &config); + if (node < 0) { + debug("%s: Could not find sromc configuration\n", __func__); + return 0; + } + node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215); + if (node < 0) { + debug("%s: Could not find lan9215 configuration\n", __func__); + return 0; + } + + /* We now have a node, so any problems from now on are errors */ + base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg"); + if (base_addr == FDT_ADDR_T_NONE) { + debug("%s: Could not find lan9215 address\n", __func__); + return -1; + } + + /* Ethernet needs data bus width of 16 bits */ + if (config.width != 2) { + debug("%s: Unsupported bus width %d\n", __func__, + config.width); + return -1; + } + smc_bw_conf = SROMC_DATA16_WIDTH(config.bank) + | SROMC_BYTE_ENABLE(config.bank); + + smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) | + SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) | + SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) | + SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) | + SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) | + SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) | + SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); + + /* Select and configure the SROMC bank */ + exynos_pinmux_config(PERIPH_ID_SROMC, config.bank); + s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf); + return smc911x_initialize(0, base_addr); +#endif + return 0; +} + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + int ret; + + /* dwmmc initializattion for available channels */ + ret = exynos_dwmmc_init(gd->fdt_blob); + if (ret) + debug("dwmmc init failed\n"); + + return ret; +} +#endif +#endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + stdio_print_current_devices(); + + if (local.cros_ec_err) { + /* Force console on */ + gd->flags &= ~GD_FLG_SILENT; + + printf("cros-ec communications failure %d\n", + local.cros_ec_err); + puts("\nPlease reset with Power+Refresh\n\n"); + panic("Cannot init cros-ec device"); + return -1; + } + return 0; +} +#endif + +int arch_early_init_r(void) +{ +#ifdef CONFIG_CROS_EC + if (board_init_cros_ec_devices(gd->fdt_blob)) { + printf("%s: Failed to init EC\n", __func__); + return 0; + } +#endif + + return 0; +} diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c index 6aa0509823c..5fb86649360 100644 --- a/board/samsung/smdk5250/exynos5-dt.c +++ b/board/samsung/smdk5250/exynos5-dt.c @@ -25,44 +25,8 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined CONFIG_EXYNOS_TMU -/* - * Boot Time Thermal Analysis for SoC temperature threshold breach - */ -static void boot_temp_check(void) -{ - int temp; - - switch (tmu_monitor(&temp)) { - /* Status TRIPPED ans WARNING means corresponding threshold breach */ - case TMU_STATUS_TRIPPED: - puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n"); - set_ps_hold_ctrl(); - hang(); - break; - case TMU_STATUS_WARNING: - puts("EXYNOS_TMU: WARNING! Temperature very high\n"); - break; - /* - * TMU_STATUS_INIT means something is wrong with temperature sensing - * and TMU status was changed back from NORMAL to INIT. - */ - case TMU_STATUS_INIT: - default: - debug("EXYNOS_TMU: Unknown TMU state\n"); - } -} -#endif - -struct local_info { - struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */ - int cros_ec_err; /* Error for cros_ec, 0 if ok */ -}; - -static struct local_info local; - #ifdef CONFIG_SOUND_MAX98095 -static void board_enable_audio_codec(void) +static void board_enable_audio_codec(void) { struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); @@ -73,261 +37,14 @@ static void board_enable_audio_codec(void) } #endif -struct cros_ec_dev *board_get_cros_ec_dev(void) -{ - return local.cros_ec_dev; -} - -static int board_init_cros_ec_devices(const void *blob) +int exynos_init(void) { - local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev); - if (local.cros_ec_err) - return -1; /* Will report in board_late_init() */ - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); - -#if defined CONFIG_EXYNOS_TMU - if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { - debug("%s: Failed to init TMU\n", __func__); - return -1; - } - boot_temp_check(); -#endif - -#ifdef CONFIG_EXYNOS_SPI - spi_init(); -#endif - - if (board_init_cros_ec_devices(gd->fdt_blob)) - return -1; - #ifdef CONFIG_SOUND_MAX98095 board_enable_audio_codec(); #endif return 0; } -int dram_init(void) -{ - int i; - u32 addr; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); - gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); - } - return 0; -} - -#if defined(CONFIG_POWER) -static int pmic_reg_update(struct pmic *p, int reg, uint regval) -{ - u32 val; - int ret = 0; - - ret = pmic_reg_read(p, reg, &val); - if (ret) { - debug("%s: PMIC %d register read failed\n", __func__, reg); - return -1; - } - val |= regval; - ret = pmic_reg_write(p, reg, val); - if (ret) { - debug("%s: PMIC %d register write failed\n", __func__, reg); - return -1; - } - return 0; -} - -int power_init_board(void) -{ - struct pmic *p; - - set_ps_hold_ctrl(); - - if (pmic_init(I2C_PMIC)) - return -1; - - p = pmic_get("MAX77686_PMIC"); - if (!p) - return -ENODEV; - - if (pmic_probe(p)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, - MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) - return -1; - - /* VDD_MIF */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, - MAX77686_BUCK1OUT_1V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK1OUT); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, - MAX77686_BUCK1CTRL_EN)) - return -1; - - /* VDD_ARM */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, - MAX77686_BUCK2DVS1_1_3V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK2DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, - MAX77686_BUCK2CTRL_ON)) - return -1; - - /* VDD_INT */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, - MAX77686_BUCK3DVS1_1_0125V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK3DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_G3D */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, - MAX77686_BUCK4DVS1_1_2V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK4DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_LDO2 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, - MAX77686_LD02CTRL1_1_5V | EN_LDO)) - return -1; - - /* VDD_LDO3 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, - MAX77686_LD03CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO5 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, - MAX77686_LD05CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO10 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, - MAX77686_LD10CTRL1_1_8V | EN_LDO)) - return -1; - - return 0; -} -#endif - -void dram_init_banksize(void) -{ - int i; - u32 addr, size; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); - size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); - - gd->bd->bi_dram[i].start = addr; - gd->bd->bi_dram[i].size = size; - } -} - -static int decode_sromc(const void *blob, struct fdt_sromc *config) -{ - int err; - int node; - - node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC); - if (node < 0) { - debug("Could not find SROMC node\n"); - return node; - } - - config->bank = fdtdec_get_int(blob, node, "bank", 0); - config->width = fdtdec_get_int(blob, node, "width", 2); - - err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing, - FDT_SROM_TIMING_COUNT); - if (err < 0) { - debug("Could not decode SROMC configuration Error: %s\n", - fdt_strerror(err)); - return -FDT_ERR_NOTFOUND; - } - return 0; -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_SMC911X - u32 smc_bw_conf, smc_bc_conf; - struct fdt_sromc config; - fdt_addr_t base_addr; - int node; - - node = decode_sromc(gd->fdt_blob, &config); - if (node < 0) { - debug("%s: Could not find sromc configuration\n", __func__); - return 0; - } - node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215); - if (node < 0) { - debug("%s: Could not find lan9215 configuration\n", __func__); - return 0; - } - - /* We now have a node, so any problems from now on are errors */ - base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg"); - if (base_addr == FDT_ADDR_T_NONE) { - debug("%s: Could not find lan9215 address\n", __func__); - return -1; - } - - /* Ethernet needs data bus width of 16 bits */ - if (config.width != 2) { - debug("%s: Unsupported bus width %d\n", __func__, - config.width); - return -1; - } - smc_bw_conf = SROMC_DATA16_WIDTH(config.bank) - | SROMC_BYTE_ENABLE(config.bank); - - smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) | - SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) | - SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) | - SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) | - SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) | - SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) | - SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); - - /* Select and configure the SROMC bank */ - exynos_pinmux_config(PERIPH_ID_SROMC, config.bank); - s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf); - return smc911x_initialize(0, base_addr); -#endif - return 0; -} - #ifdef CONFIG_DISPLAY_BOARDINFO int checkboard(void) { @@ -343,50 +60,6 @@ int checkboard(void) } #endif -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - int ret; - /* dwmmc initializattion for available channels */ - ret = exynos_dwmmc_init(gd->fdt_blob); - if (ret) - debug("dwmmc init failed\n"); - - return ret; -} -#endif - -static int board_uart_init(void) -{ - int err, uart_id, ret = 0; - - for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { - err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); - if (err) { - debug("UART%d not configured\n", - (uart_id - PERIPH_ID_UART0)); - ret |= err; - } - } - return ret; -} - -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - int err; - err = board_uart_init(); - if (err) { - debug("UART init failed\n"); - return err; - } -#ifdef CONFIG_SYS_I2C_INIT_BOARD - board_i2c_init(gd->fdt_blob); -#endif - return err; -} -#endif - #ifdef CONFIG_LCD void exynos_cfg_lcd_gpio(void) { @@ -410,22 +83,3 @@ void exynos_set_dp_phy(unsigned int onoff) set_dp_phy_ctrl(onoff); } #endif - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ - stdio_print_current_devices(); - - if (local.cros_ec_err) { - /* Force console on */ - gd->flags &= ~GD_FLG_SILENT; - - printf("cros-ec communications failure %d\n", - local.cros_ec_err); - puts("\nPlease reset with Power+Refresh\n\n"); - panic("Cannot init cros-ec device"); - return -1; - } - return 0; -} -#endif diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index 97fe0adf543..943c29a6988 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -26,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_USB_EHCI_EXYNOS -int board_usb_vbus_init(void) +static int board_usb_vbus_init(void) { struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); @@ -53,13 +54,8 @@ static void board_enable_audio_codec(void) } #endif -int board_init(void) +int exynos_init(void) { - gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); - -#ifdef CONFIG_EXYNOS_SPI - spi_init(); -#endif #ifdef CONFIG_USB_EHCI_EXYNOS board_usb_vbus_init(); #endif @@ -69,147 +65,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - u32 addr; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); - gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); - } - return 0; -} - -#if defined(CONFIG_POWER) -static int pmic_reg_update(struct pmic *p, int reg, uint regval) -{ - u32 val; - int ret = 0; - - ret = pmic_reg_read(p, reg, &val); - if (ret) { - debug("%s: PMIC %d register read failed\n", __func__, reg); - return -1; - } - val |= regval; - ret = pmic_reg_write(p, reg, val); - if (ret) { - debug("%s: PMIC %d register write failed\n", __func__, reg); - return -1; - } - return 0; -} - -int power_init_board(void) -{ - struct pmic *p; - - set_ps_hold_ctrl(); - - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - if (pmic_init(I2C_PMIC)) - return -1; - - p = pmic_get("MAX77686_PMIC"); - if (!p) - return -ENODEV; - - if (pmic_probe(p)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, - MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) - return -1; - - /* VDD_MIF */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, - MAX77686_BUCK1OUT_1_05V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK1OUT); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, - MAX77686_BUCK1CTRL_EN)) - return -1; - - /* VDD_ARM */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, - MAX77686_BUCK2DVS1_1_3V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK2DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, - MAX77686_BUCK2CTRL_ON)) - return -1; - - /* VDD_INT */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, - MAX77686_BUCK3DVS1_1_0125V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK3DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_G3D */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, - MAX77686_BUCK4DVS1_1_2V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK4DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_LDO2 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, - MAX77686_LD02CTRL1_1_5V | EN_LDO)) - return -1; - - /* VDD_LDO3 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, - MAX77686_LD03CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO5 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, - MAX77686_LD05CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO10 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, - MAX77686_LD10CTRL1_1_8V | EN_LDO)) - return -1; - - return 0; -} -#endif - -void dram_init_banksize(void) -{ - int i; - u32 addr, size; - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); - size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); - gd->bd->bi_dram[i].start = addr; - gd->bd->bi_dram[i].size = size; - } -} - int board_eth_init(bd_t *bis) { #ifdef CONFIG_SMC911X @@ -301,21 +156,6 @@ int board_mmc_init(bd_t *bis) } #endif -static int board_uart_init(void) -{ - int err, uart_id, ret = 0; - - for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { - err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); - if (err) { - debug("UART%d not configured\n", - (uart_id - PERIPH_ID_UART0)); - ret |= err; - } - } - return ret; -} - void board_i2c_init(const void *blob) { int i; @@ -326,22 +166,6 @@ void board_i2c_init(const void *blob) } } -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - int err; - err = board_uart_init(); - if (err) { - debug("UART init failed\n"); - return err; - } -#ifdef CONFIG_SYS_I2C_INIT_BOARD - board_i2c_init(NULL); -#endif - return err; -} -#endif - #ifdef CONFIG_LCD void exynos_cfg_lcd_gpio(void) { diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 8fb904cddf4..79e85dbc25b 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -21,6 +21,8 @@ #define CONFIG_ARCH_CPU_INIT #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_COMMON +#define CONFIG_ARCH_EARLY_INIT_R /* Enable fdt support for Exynos5250 */ #define CONFIG_OF_CONTROL -- cgit v1.3.1 From e106bd9b9d0c3ec429b2e85184738789b75ca247 Mon Sep 17 00:00:00 2001 From: Rajeshwari Birje Date: Thu, 26 Dec 2013 09:44:24 +0530 Subject: Exynos5420: Add base patch for SMDK5420 Adding the base patch for Exynos based SMDK5420. This shall enable compilation and basic boot support for SMDK5420. Signed-off-by: Rajeshwari S Shinde Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Signed-off-by: Minkyu Kang --- board/samsung/common/board.c | 2 + board/samsung/smdk5420/Makefile | 11 +++ board/samsung/smdk5420/smdk5420.c | 159 ++++++++++++++++++++++++++++++++++ board/samsung/smdk5420/smdk5420_spl.c | 52 +++++++++++ boards.cfg | 1 + include/configs/arndale.h | 1 + include/configs/exynos5250-dt.h | 1 + tools/Makefile | 3 +- 8 files changed, 229 insertions(+), 1 deletion(-) create mode 100644 board/samsung/smdk5420/Makefile create mode 100644 board/samsung/smdk5420/smdk5420.c create mode 100644 board/samsung/smdk5420/smdk5420_spl.c (limited to 'board') diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index dc68e3a8737..cd873bc56d6 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -149,6 +149,7 @@ struct cros_ec_dev *board_get_cros_ec_dev(void) return local.cros_ec_dev; } +#ifdef CONFIG_CROS_EC static int board_init_cros_ec_devices(const void *blob) { local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev); @@ -157,6 +158,7 @@ static int board_init_cros_ec_devices(const void *blob) return 0; } +#endif #if defined(CONFIG_POWER) #ifdef CONFIG_POWER_MAX77686 diff --git a/board/samsung/smdk5420/Makefile b/board/samsung/smdk5420/Makefile new file mode 100644 index 00000000000..c2f8886c99c --- /dev/null +++ b/board/samsung/smdk5420/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (C) 2013 Samsung Electronics +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += smdk5420_spl.o + +ifndef CONFIG_SPL_BUILD +obj-y += smdk5420.o +endif diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c new file mode 100644 index 00000000000..3ad2ad0e565 --- /dev/null +++ b/board/samsung/smdk5420/smdk5420.c @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_USB_EHCI_EXYNOS +static int board_usb_vbus_init(void) +{ + struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) + samsung_get_base_gpio_part1(); + + /* Enable VBUS power switch */ + s5p_gpio_direction_output(&gpio1->x2, 6, 1); + + /* VBUS turn ON time */ + mdelay(3); + + return 0; +} +#endif + +int exynos_init(void) +{ +#ifdef CONFIG_USB_EHCI_EXYNOS + board_usb_vbus_init(); +#endif + return 0; +} + +#ifdef CONFIG_LCD +void cfg_lcd_gpio(void) +{ + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1(); + + /* For Backlight */ + s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT); + s5p_gpio_set_value(&gpio1->b2, 0, 1); + + /* LCD power on */ + s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT); + s5p_gpio_set_value(&gpio1->x1, 5, 1); + + /* Set Hotplug detect for DP */ + s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); +} + +vidinfo_t panel_info = { + .vl_freq = 60, + .vl_col = 2560, + .vl_row = 1600, + .vl_width = 2560, + .vl_height = 1600, + .vl_clkp = CONFIG_SYS_LOW, + .vl_hsp = CONFIG_SYS_LOW, + .vl_vsp = CONFIG_SYS_LOW, + .vl_dp = CONFIG_SYS_LOW, + .vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */ + + /* wDP panel timing infomation */ + .vl_hspw = 32, + .vl_hbpd = 80, + .vl_hfpd = 48, + + .vl_vspw = 6, + .vl_vbpd = 37, + .vl_vfpd = 3, + .vl_cmd_allow_len = 0xf, + + .win_id = 3, + .cfg_gpio = cfg_lcd_gpio, + .backlight_on = NULL, + .lcd_power_on = NULL, + .reset_lcd = NULL, + .dual_lcd_enabled = 0, + + .init_delay = 0, + .power_on_delay = 0, + .reset_delay = 0, + .interface_mode = FIMD_RGB_INTERFACE, + .dp_enabled = 1, +}; + +static struct edp_device_info edp_info = { + .disp_info = { + .h_res = 2560, + .h_sync_width = 32, + .h_back_porch = 80, + .h_front_porch = 48, + .v_res = 1600, + .v_sync_width = 6, + .v_back_porch = 37, + .v_front_porch = 3, + .v_sync_rate = 60, + }, + .lt_info = { + .lt_status = DP_LT_NONE, + }, + .video_info = { + .master_mode = 0, + .bist_mode = DP_DISABLE, + .bist_pattern = NO_PATTERN, + .h_sync_polarity = 0, + .v_sync_polarity = 0, + .interlaced = 0, + .color_space = COLOR_RGB, + .dynamic_range = VESA, + .ycbcr_coeff = COLOR_YCBCR601, + .color_depth = COLOR_8, + }, +}; + +static struct exynos_dp_platform_data dp_platform_data = { + .phy_enable = set_dp_phy_ctrl, + .edp_dev_info = &edp_info, +}; + +void init_panel_info(vidinfo_t *vid) +{ + vid->rgb_mode = MODE_RGB_P; + + exynos_set_dp_platform_data(&dp_platform_data); +} +#endif + +int board_get_revision(void) +{ + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + const char *board_name; + + board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + if (board_name == NULL) + printf("\nUnknown Board\n"); + else + printf("\nBoard: %s\n", board_name); + + return 0; +} +#endif diff --git a/board/samsung/smdk5420/smdk5420_spl.c b/board/samsung/smdk5420/smdk5420_spl.c new file mode 100644 index 00000000000..73359f784ce --- /dev/null +++ b/board/samsung/smdk5420/smdk5420_spl.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2013 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define SIGNATURE 0xdeadbeef + +/* Parameters of early board initialization in SPL */ +static struct spl_machine_param machine_param + __attribute__((section(".machine_param"))) = { + .signature = SIGNATURE, + .version = 1, + .params = "vmubfasirM", + .size = sizeof(machine_param), + + .mem_iv_size = 0x1f, + .mem_type = DDR_MODE_DDR3, + + /* + * Set uboot_size to 0x100000 bytes. + * + * This is an overly conservative value chosen to accommodate all + * possible U-Boot image. You are advised to set this value to a + * smaller realistic size via scripts that modifies the .machine_param + * section of output U-Boot image. + */ + .uboot_size = 0x100000, + + .boot_source = BOOT_MODE_OM, + .frequency_mhz = 800, + .arm_freq_mhz = 900, + .serial_base = 0x12c30000, + .i2c_base = 0x12c60000, + .mem_manuf = MEM_MANUF_SAMSUNG, +}; + +struct spl_machine_param *spl_get_machine_params(void) +{ + if (machine_param.signature != SIGNATURE) { + /* Will hang if SIGNATURE dont match */ + while (1) + ; + } + + return &machine_param; +} diff --git a/boards.cfg b/boards.cfg index d85d4ddb936..bd018ffc9dc 100644 --- a/boards.cfg +++ b/boards.cfg @@ -276,6 +276,7 @@ Active arm armv7 exynos samsung arndale Active arm armv7 exynos samsung origen origen - Chander Kashyap Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap Active arm armv7 exynos samsung smdk5250 snow - Rajeshwari Shinde +Active arm armv7 exynos samsung smdk5420 smdk5420 - Rajeshwari Shinde Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap Active arm armv7 exynos samsung trats trats - Lukasz Majewski Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek diff --git a/include/configs/arndale.h b/include/configs/arndale.h index a3cb56b8bf2..b7fb29ea720 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -117,6 +117,7 @@ #define CONFIG_USB_STORAGE /* MMC SPL */ +#define CONFIG_EXYNOS_SPL #define CONFIG_SPL #define COPY_BL2_FNPTR_ADDR 0x02020030 diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 79e85dbc25b..3b989eb825e 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -155,6 +155,7 @@ #define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20 /* MMC SPL */ +#define CONFIG_EXYNOS_SPL #define CONFIG_SPL #define COPY_BL2_FNPTR_ADDR 0x02020030 diff --git a/tools/Makefile b/tools/Makefile index 14d94e39a0d..d4bc84d2789 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -53,6 +53,7 @@ BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX) BIN_FILES-y += mkenvimage$(SFX) BIN_FILES-y += mkimage$(SFX) BIN_FILES-$(CONFIG_EXYNOS5250) += mk$(BOARD)spl$(SFX) +BIN_FILES-$(CONFIG_EXYNOS5420) += mk$(BOARD)spl$(SFX) BIN_FILES-$(CONFIG_MX23) += mxsboot$(SFX) BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX) BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX) @@ -87,7 +88,7 @@ NOPED_OBJ_FILES-y += ublimage.o OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o -OBJ_FILES-$(CONFIG_EXYNOS5250) += mkexynosspl.o +OBJ_FILES-$(CONFIG_EXYNOS_SPL) += mkexynosspl.o OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o OBJ_FILES-$(CONFIG_MX23) += mxsboot.o -- cgit v1.3.1 From e2be3369c84f8b9a91ba904823ba70ed842019d3 Mon Sep 17 00:00:00 2001 From: Rajeshwari Birje Date: Thu, 26 Dec 2013 09:44:25 +0530 Subject: DTS: Add dts support for SMDK5420 This patch adds dts support for SMDK5420. exynos5.dtsi created is a common file which has the nodes common to both 5420 and 5250. Signed-off-by: Akshay Saraswat Signed-off-by: Rajeshwari S Shinde Acked-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/dts/exynos5.dtsi | 198 ++++++++++++++++++++++++++++++ arch/arm/dts/exynos5250.dtsi | 194 +---------------------------- arch/arm/dts/exynos5420.dtsi | 70 +++++++++++ board/samsung/dts/exynos5420-smdk5420.dts | 169 +++++++++++++++++++++++++ 4 files changed, 441 insertions(+), 190 deletions(-) create mode 100644 arch/arm/dts/exynos5.dtsi create mode 100644 arch/arm/dts/exynos5420.dtsi create mode 100644 board/samsung/dts/exynos5420-smdk5420.dts (limited to 'board') diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi new file mode 100644 index 00000000000..f8c87411b6b --- /dev/null +++ b/arch/arm/dts/exynos5.dtsi @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2013 The Chromium OS Authors + * SAMSUNG EXYNOS5 SoC device tree source + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "samsung,exynos5"; + + sromc@12250000 { + compatible = "samsung,exynos-sromc"; + reg = <0x12250000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@12c60000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C60000 0x100>; + interrupts = <0 56 0>; + }; + + i2c@12c70000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C70000 0x100>; + interrupts = <0 57 0>; + }; + + i2c@12c80000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C80000 0x100>; + interrupts = <0 58 0>; + }; + + i2c@12c90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C90000 0x100>; + interrupts = <0 59 0>; + }; + + spi@12d20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-spi"; + reg = <0x12d20000 0x30>; + interrupts = <0 68 0>; + }; + + spi@12d30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-spi"; + reg = <0x12d30000 0x30>; + interrupts = <0 69 0>; + }; + + spi@12d40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-spi"; + reg = <0x12d40000 0x30>; + clock-frequency = <50000000>; + interrupts = <0 70 0>; + }; + + spi@131a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-spi"; + reg = <0x131a0000 0x30>; + interrupts = <0 129 0>; + }; + + spi@131b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-spi"; + reg = <0x131b0000 0x30>; + interrupts = <0 130 0>; + }; + + ehci@12110000 { + compatible = "samsung,exynos-ehci"; + reg = <0x12110000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + + phy { + compatible = "samsung,exynos-usb-phy"; + reg = <0x12130000 0x100>; + }; + }; + + tmu@10060000 { + compatible = "samsung,exynos-tmu"; + reg = <0x10060000 0x10000>; + }; + + fimd@14400000 { + compatible = "samsung,exynos-fimd"; + reg = <0x14400000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + dp@145b0000 { + compatible = "samsung,exynos5-dp"; + reg = <0x145b0000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + xhci0: xhci@12000000 { + compatible = "samsung,exynos5250-xhci"; + reg = <0x12000000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + phy { + compatible = "samsung,exynos5250-usb3-phy"; + reg = <0x12100000 0x100>; + }; + }; + + mmc@12200000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5250-dwmmc"; + reg = <0x12200000 0x1000>; + interrupts = <0 75 0>; + }; + + mmc@12210000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5250-dwmmc"; + reg = <0x12210000 0x1000>; + interrupts = <0 76 0>; + }; + + mmc@12220000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5250-dwmmc"; + reg = <0x12220000 0x1000>; + interrupts = <0 77 0>; + }; + + mmc@12230000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5250-dwmmc"; + reg = <0x12230000 0x1000>; + interrupts = <0 78 0>; + }; + + serial@12C00000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C00000 0x100>; + interrupts = <0 51 0>; + id = <0>; + }; + + serial@12C10000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C10000 0x100>; + interrupts = <0 52 0>; + id = <1>; + }; + + serial@12C20000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C20000 0x100>; + interrupts = <0 53 0>; + id = <2>; + }; + + serial@12C30000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C30000 0x100>; + interrupts = <0 54 0>; + id = <3>; + }; + + gpio: gpio { + }; +}; diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi index 31880eb2305..0c644e7cac8 100644 --- a/arch/arm/dts/exynos5250.dtsi +++ b/arch/arm/dts/exynos5250.dtsi @@ -1,66 +1,13 @@ /* + * (C) Copyright 2012 SAMSUNG Electronics * SAMSUNG EXYNOS5250 SoC device tree source * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. - * EXYNOS5250 based board files can include this file and provide - * values for board specfic bindings. - * - * Note: This file does not include device nodes for all the controllers in - * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, - * additional nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + * SPDX-License-Identifier: GPL-2.0+ + */ -/include/ "skeleton.dtsi" +/include/ "exynos5.dtsi" / { - compatible = "samsung,exynos5250"; - - sromc@12250000 { - compatible = "samsung,exynos-sromc"; - reg = <0x12250000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c@12c60000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C60000 0x100>; - interrupts = <0 56 0>; - }; - - i2c@12c70000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C70000 0x100>; - interrupts = <0 57 0>; - }; - - i2c@12c80000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C80000 0x100>; - interrupts = <0 58 0>; - }; - - i2c@12c90000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C90000 0x100>; - interrupts = <0 59 0>; - }; - i2c@12ca0000 { #address-cells = <1>; #size-cells = <0>; @@ -117,46 +64,6 @@ samsung,i2s-id = <1>; }; - spi@12d20000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos-spi"; - reg = <0x12d20000 0x30>; - interrupts = <0 68 0>; - }; - - spi@12d30000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos-spi"; - reg = <0x12d30000 0x30>; - interrupts = <0 69 0>; - }; - - spi@12d40000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos-spi"; - reg = <0x12d40000 0x30>; - clock-frequency = <50000000>; - interrupts = <0 70 0>; - }; - - spi@131a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos-spi"; - reg = <0x131a0000 0x30>; - interrupts = <0 129 0>; - }; - - spi@131b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos-spi"; - reg = <0x131b0000 0x30>; - interrupts = <0 130 0>; - }; xhci@12000000 { compatible = "samsung,exynos5250-xhci"; @@ -170,97 +77,4 @@ }; }; - ehci@12110000 { - compatible = "samsung,exynos-ehci"; - reg = <0x12110000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - - phy { - compatible = "samsung,exynos-usb-phy"; - reg = <0x12130000 0x100>; - }; - }; - - tmu@10060000 { - compatible = "samsung,exynos-tmu"; - reg = <0x10060000 0x10000>; - }; - - fimd@14400000 { - compatible = "samsung,exynos-fimd"; - reg = <0x14400000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - dp@145b0000 { - compatible = "samsung,exynos5-dp"; - reg = <0x145b0000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - mmc@12200000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5250-dwmmc"; - reg = <0x12200000 0x1000>; - interrupts = <0 75 0>; - }; - - mmc@12210000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5250-dwmmc"; - reg = <0x12210000 0x1000>; - interrupts = <0 76 0>; - }; - - mmc@12220000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5250-dwmmc"; - reg = <0x12220000 0x1000>; - interrupts = <0 77 0>; - }; - - mmc@12230000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5250-dwmmc"; - reg = <0x12230000 0x1000>; - interrupts = <0 78 0>; - }; - - serial@12C00000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; - interrupts = <0 51 0>; - id = <0>; - }; - - serial@12C10000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C10000 0x100>; - interrupts = <0 52 0>; - id = <1>; - }; - - serial@12C20000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C20000 0x100>; - interrupts = <0 53 0>; - id = <2>; - }; - - serial@12C30000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C30000 0x100>; - interrupts = <0 54 0>; - id = <3>; - }; - - gpio: gpio { - }; }; diff --git a/arch/arm/dts/exynos5420.dtsi b/arch/arm/dts/exynos5420.dtsi new file mode 100644 index 00000000000..02ead61a496 --- /dev/null +++ b/arch/arm/dts/exynos5420.dtsi @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2013 SAMSUNG Electronics + * SAMSUNG EXYNOS5420 SoC device tree source + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "exynos5.dtsi" + +/ { + config { + machine-arch-id = <4151>; + }; + + i2c@12ca0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CA0000 0x100>; + interrupts = <0 60 0>; + }; + + i2c@12cb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CB0000 0x100>; + interrupts = <0 61 0>; + }; + + i2c@12cc0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CC0000 0x100>; + interrupts = <0 62 0>; + }; + + i2c@12cd0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CD0000 0x100>; + interrupts = <0 63 0>; + }; + + i2c@12e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E00000 0x100>; + interrupts = <0 87 0>; + }; + + i2c@12e10000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E10000 0x100>; + interrupts = <0 88 0>; + }; + + i2c@12e20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E20000 0x100>; + interrupts = <0 203 0>; + }; +}; diff --git a/board/samsung/dts/exynos5420-smdk5420.dts b/board/samsung/dts/exynos5420-smdk5420.dts new file mode 100644 index 00000000000..d73976356d3 --- /dev/null +++ b/board/samsung/dts/exynos5420-smdk5420.dts @@ -0,0 +1,169 @@ +/* + * SAMSUNG SMDK5420 board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "exynos5420.dtsi" + +/ { + model = "SAMSUNG SMDK5420 board based on EXYNOS5420"; + compatible = "samsung,smdk5420", "samsung,exynos5"; + + config { + hwid = "smdk5420 TEST A-A 9382"; + }; + + aliases { + i2c0 = "/i2c@12c60000"; + i2c1 = "/i2c@12c70000"; + i2c2 = "/i2c@12c80000"; + i2c3 = "/i2c@12c90000"; + i2c4 = "/i2c@12ca0000"; + i2c5 = "/i2c@12cb0000"; + i2c6 = "/i2c@12cc0000"; + i2c7 = "/i2c@12cd0000"; + i2c8 = "/i2c@12e00000"; + i2c9 = "/i2c@12e10000"; + i2c10 = "/i2c@12e20000"; + spi0 = "/spi@12d20000"; + spi1 = "/spi@12d30000"; + spi2 = "/spi@12d40000"; + spi3 = "/spi@131a0000"; + spi4 = "/spi@131b0000"; + mmc0 = "/mmc@12200000"; + mmc1 = "/mmc@12210000"; + mmc2 = "/mmc@12220000"; + xhci0 = "/xhci@12000000"; + xhci1 = "/xhci@12400000"; + serial0 = "/serial@12C30000"; + console = "/serial@12C30000"; + }; + + tmu@10060000 { + samsung,min-temp = <25>; + samsung,max-temp = <125>; + samsung,start-warning = <95>; + samsung,start-tripping = <105>; + samsung,hw-tripping = <110>; + samsung,efuse-min-value = <40>; + samsung,efuse-value = <55>; + samsung,efuse-max-value = <100>; + samsung,slope = <274761730>; + samsung,dc-value = <25>; + }; + + /* s2mps11 is on i2c bus 4 */ + i2c@12ca0000 { + #address-cells = <1>; + #size-cells = <0>; + pmic@66 { + reg = <0x66>; + compatible = "samsung,s2mps11-pmic"; + }; + }; + + spi@12d20000 { /* spi0 */ + spi-max-frequency = <50000000>; + firmware_storage_spi: flash@0 { + reg = <0>; + }; + }; + + fimd@14400000 { + samsung,vl-freq = <60>; + samsung,vl-col = <2560>; + samsung,vl-row = <1600>; + samsung,vl-width = <2560>; + samsung,vl-height = <1600>; + + samsung,vl-clkp; + samsung,vl-dp; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <32>; + samsung,vl-hbpd = <80>; + samsung,vl-hfpd = <48>; + samsung,vl-vspw = <6>; + samsung,vl-vbpd = <37>; + samsung,vl-vfpd = <3>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <3>; + samsung,interface-mode = <1>; + samsung,dp-enabled = <1>; + samsung,dual-lcd-enabled = <0>; + }; + + sound@3830000 { + samsung,codec-type = "wm8994"; + }; + + i2c@12c70000 { + soundcodec@1a { + reg = <0x1a>; + compatible = "wolfson,wm8994-codec"; + }; + }; + + mmc@12200000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + samsung,removable = <0>; + samsung,pre-init; + }; + + mmc@12210000 { + status = "disabled"; + }; + + mmc@12220000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + samsung,removable = <1>; + }; + + mmc@12230000 { + status = "disabled"; + }; + + fimd@14400000 { + /* sysmmu is not used in U-Boot */ + samsung,disable-sysmmu; + }; + + dp@145b0000 { + samsung,lt-status = <0>; + + samsung,master-mode = <0>; + samsung,bist-mode = <0>; + samsung,bist-pattern = <0>; + samsung,h-sync-polarity = <0>; + samsung,v-sync-polarity = <0>; + samsung,interlaced = <0>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + }; + + dmc { + mem-type = "ddr3"; + }; + + xhci1: xhci@12400000 { + compatible = "samsung,exynos5250-xhci"; + reg = <0x12400000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + phy { + compatible = "samsung,exynos5250-usb3-phy"; + reg = <0x12500000 0x100>; + }; + }; +}; -- cgit v1.3.1 From ef23b99607de0c0055e6f627c2d2be142a9ab4a6 Mon Sep 17 00:00:00 2001 From: Piotr Wilczek Date: Wed, 18 Dec 2013 15:43:37 +0100 Subject: board:trats1:trats2: fix adapter number This fix is necessary after increased by one the number of adapters in s3c24x0 driver. Tested on Trats and Trats2. Signed-off-by: Piotr Wilczek Signed-off-by: Kyungmin Park Cc: Minkyu Kang Cc: Lukasz Majewski Signed-off-by: Minkyu Kang --- board/samsung/trats/trats.c | 2 +- board/samsung/trats2/trats2.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 8aba51c009f..640a193dc21 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -295,7 +295,7 @@ int power_init_board(void) */ ret = pmic_init(I2C_5); ret |= pmic_init_max8997(); - ret |= power_fg_init(I2C_8); + ret |= power_fg_init(I2C_9); ret |= power_muic_init(I2C_5); ret |= power_bat_init(0); if (ret) diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index 147de179cc6..be15357e69f 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -195,9 +195,9 @@ int power_init_board(void) #endif pmic_init(I2C_7); /* I2C adapter 7 - bus name s3c24x0_7 */ pmic_init_max77686(); - pmic_init_max77693(I2C_9); /* I2C adapter 9 - bus name soft1 */ - power_muic_init(I2C_9); /* I2C adapter 9 - bus name soft1 */ - power_fg_init(I2C_8); /* I2C adapter 8 - bus name soft0 */ + pmic_init_max77693(I2C_10); /* I2C adapter 10 - bus name soft1 */ + power_muic_init(I2C_10); /* I2C adapter 10 - bus name soft1 */ + power_fg_init(I2C_9); /* I2C adapter 9 - bus name soft0 */ power_bat_init(0); p_chrg = pmic_get("MAX77693_PMIC"); -- cgit v1.3.1 From 456ccfdf0d5eefc153b143bd13731a59e2d71585 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 20 Dec 2013 11:19:33 -0500 Subject: TI:omap3: Drop omap3_zoom2 The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ and Tom Rix's email has long been bouncing. Signed-off-by: Tom Rini --- board/logicpd/zoom2/Makefile | 11 -- board/logicpd/zoom2/config.mk | 17 --- board/logicpd/zoom2/debug_board.c | 44 ------- board/logicpd/zoom2/led.c | 116 ------------------ board/logicpd/zoom2/zoom2.c | 183 ---------------------------- board/logicpd/zoom2/zoom2.h | 142 ---------------------- board/logicpd/zoom2/zoom2_serial.c | 130 -------------------- board/logicpd/zoom2/zoom2_serial.h | 59 --------- boards.cfg | 1 - drivers/serial/ns16550.c | 5 +- include/configs/omap3_zoom2.h | 237 ------------------------------------- 11 files changed, 2 insertions(+), 943 deletions(-) delete mode 100644 board/logicpd/zoom2/Makefile delete mode 100644 board/logicpd/zoom2/config.mk delete mode 100644 board/logicpd/zoom2/debug_board.c delete mode 100644 board/logicpd/zoom2/led.c delete mode 100644 board/logicpd/zoom2/zoom2.c delete mode 100644 board/logicpd/zoom2/zoom2.h delete mode 100644 board/logicpd/zoom2/zoom2_serial.c delete mode 100644 board/logicpd/zoom2/zoom2_serial.h delete mode 100644 include/configs/omap3_zoom2.h (limited to 'board') diff --git a/board/logicpd/zoom2/Makefile b/board/logicpd/zoom2/Makefile deleted file mode 100644 index 8ec5f256133..00000000000 --- a/board/logicpd/zoom2/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := zoom2.o -obj-y += debug_board.o -obj-y += zoom2_serial.o -obj-$(CONFIG_STATUS_LED) += led.o diff --git a/board/logicpd/zoom2/config.mk b/board/logicpd/zoom2/config.mk deleted file mode 100644 index 1c382f71893..00000000000 --- a/board/logicpd/zoom2/config.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# (C) Copyright 2009 -# Texas Instruments, -# -# Zoom II uses OMAP3 (ARM-CortexA8) CPU -# see http://www.ti.com/ for more information on Texas Instruments -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Physical Address: -# 0x80000000 (bank0) -# 0xA0000000 (bank1) -# Linux-Kernel is expected to be at 0x80008000, entry 0x80008000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/logicpd/zoom2/debug_board.c b/board/logicpd/zoom2/debug_board.c deleted file mode 100644 index 071f41074ba..00000000000 --- a/board/logicpd/zoom2/debug_board.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include - -#define DEBUG_BOARD_CONNECTED 1 -#define DEBUG_BOARD_NOT_CONNECTED 0 - -static int debug_board_connected = DEBUG_BOARD_CONNECTED; - -static void zoom2_debug_board_detect (void) -{ - int val = 0; - - if (!gpio_request(158, "")) { - /* - * GPIO to query for debug board - * 158 db board query - */ - gpio_direction_input(158); - val = gpio_get_value(158); - } - - if (!val) - debug_board_connected = DEBUG_BOARD_NOT_CONNECTED; -} - -int zoom2_debug_board_connected (void) -{ - static int first_time = 1; - - if (first_time) { - zoom2_debug_board_detect (); - first_time = 0; - } - return debug_board_connected; -} diff --git a/board/logicpd/zoom2/led.c b/board/logicpd/zoom2/led.c deleted file mode 100644 index 5d37ac15f2f..00000000000 --- a/board/logicpd/zoom2/led.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include - -static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF}; - -/* - * GPIO LEDs - * 173 red - * 154 blue - * 61 blue2 - */ -#define ZOOM2_LED_RED 173 -#define ZOOM2_LED_BLUE 154 -#define ZOOM2_LED_BLUE2 61 - -void red_led_off(void) -{ - /* red */ - if (!gpio_request(ZOOM2_LED_RED, "")) { - gpio_direction_output(ZOOM2_LED_RED, 0); - gpio_set_value(ZOOM2_LED_RED, 0); - } - saved_state[STATUS_LED_RED] = STATUS_LED_OFF; -} - -void blue_led_off(void) -{ - /* blue */ - if (!gpio_request(ZOOM2_LED_BLUE, "")) { - gpio_direction_output(ZOOM2_LED_BLUE, 0); - gpio_set_value(ZOOM2_LED_BLUE, 0); - } - - /* blue 2 */ - if (!gpio_request(ZOOM2_LED_BLUE2, "")) { - gpio_direction_output(ZOOM2_LED_BLUE2, 0); - gpio_set_value(ZOOM2_LED_BLUE2, 0); - } - saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF; -} - -void red_led_on(void) -{ - blue_led_off(); - - /* red */ - if (!gpio_request(ZOOM2_LED_RED, "")) { - gpio_direction_output(ZOOM2_LED_RED, 0); - gpio_set_value(ZOOM2_LED_RED, 1); - } - saved_state[STATUS_LED_RED] = STATUS_LED_ON; -} - -void blue_led_on(void) -{ - red_led_off(); - - /* blue */ - if (!gpio_request(ZOOM2_LED_BLUE, "")) { - gpio_direction_output(ZOOM2_LED_BLUE, 0); - gpio_set_value(ZOOM2_LED_BLUE, 1); - } - - /* blue 2 */ - if (!gpio_request(ZOOM2_LED_BLUE2, "")) { - gpio_direction_output(ZOOM2_LED_BLUE2, 0); - gpio_set_value(ZOOM2_LED_BLUE2, 1); - } - - saved_state[STATUS_LED_BLUE] = STATUS_LED_ON; -} - -void __led_init (led_id_t mask, int state) -{ - __led_set (mask, state); -} - -void __led_toggle (led_id_t mask) -{ - if (STATUS_LED_BLUE == mask) { - if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE]) - blue_led_off(); - else - blue_led_on(); - } else if (STATUS_LED_RED == mask) { - if (STATUS_LED_ON == saved_state[STATUS_LED_RED]) - red_led_off(); - else - red_led_on(); - } -} - -void __led_set (led_id_t mask, int state) -{ - if (STATUS_LED_BLUE == mask) { - if (STATUS_LED_ON == state) - blue_led_on(); - else - blue_led_off(); - } else if (STATUS_LED_RED == mask) { - if (STATUS_LED_ON == state) - red_led_on(); - else - red_led_off(); - } -} diff --git a/board/logicpd/zoom2/zoom2.c b/board/logicpd/zoom2/zoom2.c deleted file mode 100644 index e14de04695a..00000000000 --- a/board/logicpd/zoom2/zoom2.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * Derived from Zoom1 code by - * Nishanth Menon - * Sunil Kumar - * Shashi Ranjan - * Richard Woodruff - * Syed Mohammed Khasim - * - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#ifdef CONFIG_STATUS_LED -#include -#endif -#include -#include -#include -#include -#include -#include -#include -#include -#include "zoom2.h" -#include "zoom2_serial.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * This the the zoom2, board specific, gpmc configuration for the - * quad uart on the debug board. The more general gpmc configurations - * are setup at the cpu level in arch/arm/cpu/armv7/omap3/mem.c - * - * The details of the setting of the serial gpmc setup are not available. - * The values were provided by another party. - */ -static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = { - 0x00011000, - 0x001F1F01, - 0x00080803, - 0x1D091D09, - 0x041D1F1F, - 0x1D0904C4, 0 -}; - -/* Used to track the revision of the board */ -static zoom2_revision revision = ZOOM2_REVISION_UNKNOWN; - -/* - * Routine: zoom2_get_revision - * Description: Return the revision of the Zoom2 this code is running on. - */ -zoom2_revision zoom2_get_revision(void) -{ - return revision; -} - -/* - * Routine: zoom2_identify - * Description: Detect which version of Zoom2 we are running on. - */ -void zoom2_identify(void) -{ - /* - * To check for production board vs beta board, - * check if gpio 94 is clear. - * - * No way yet to check for alpha board identity. - * Alpha boards were produced in very limited quantities - * and they are not commonly used. They are mentioned here - * only for completeness. - */ - if (!gpio_request(94, "")) { - unsigned int val; - - gpio_direction_input(94); - val = gpio_get_value(94); - - if (val) - revision = ZOOM2_REVISION_BETA; - else - revision = ZOOM2_REVISION_PRODUCTION; - } - - printf("Board revision "); - switch (revision) { - case ZOOM2_REVISION_PRODUCTION: - printf("Production\n"); - break; - case ZOOM2_REVISION_BETA: - printf("Beta\n"); - break; - default: - printf("Unknown\n"); - break; - } -} - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init (void) -{ - u32 *gpmc_config; - - gpmc_init (); /* in SRAM or SDRAM, finish GPMC */ - - /* Configure console support on zoom2 */ - gpmc_config = gpmc_serial_TL16CP754C; - enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[3], - SERIAL_TL16CP754C_BASE, GPMC_SIZE_16M); - - /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM2; - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - -#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) - status_led_set (STATUS_LED_BOOT, STATUS_LED_ON); -#endif - return 0; -} - -/* - * Routine: misc_init_r - * Description: Configure zoom board specific configurations - */ -int misc_init_r(void) -{ - zoom2_identify(); - twl4030_power_init(); - twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); - dieid_num_r(); - - /* - * Board Reset - * The board is reset by holding the the large button - * on the top right side of the main board for - * eight seconds. - * - * There are reported problems of some beta boards - * continously resetting. For those boards, disable resetting. - */ - if (ZOOM2_REVISION_PRODUCTION <= zoom2_get_revision()) - twl4030_power_reset_init(); - - return 0; -} - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs (void) -{ - /* platform specific muxes */ - MUX_ZOOM2 (); -} - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/board/logicpd/zoom2/zoom2.h b/board/logicpd/zoom2/zoom2.h deleted file mode 100644 index 850c790a08d..00000000000 --- a/board/logicpd/zoom2/zoom2.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * Derived from: board/omap3/zoom1/zoom1.h - * Nishanth Menon - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _BOARD_ZOOM2_H_ -#define _BOARD_ZOOM2_H_ - -const omap3_sysinfo sysinfo = { - DDR_STACKED, - "OMAP3 Zoom2 ", - "NAND", -}; - -typedef enum { - ZOOM2_REVISION_UNKNOWN = 0, - ZOOM2_REVISION_ALPHA, - ZOOM2_REVISION_BETA, - ZOOM2_REVISION_PRODUCTION -} zoom2_revision; - -zoom2_revision zoom2_get_revision(void); - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_ZOOM2() \ - /* SDRC*/\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\ -/* GPMC */\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M7)) /* GPMC_nCS1 */\ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M7)) /* GPMC_nCS2 */\ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M7)) /* GPMC_nCS3 */\ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M7)) /* GPMC_nCS4 */\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M7)) /* GPMC_nCS5 */\ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /* GPMC_nCS6 */\ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M7)) /* GPMC_nCS7 */\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\ - MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | DIS | M0)) /* GPMC_nWP */\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | EN | M0)) /* GPMC_WAIT0 */\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /* GPMC_WAIT1 */\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /* GPMC_WAIT2 */\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /* GPMC_WAIT3 */\ -/* IDCC modem Power On */\ - MUX_VAL(CP(CAM_D11), (IEN | PTU | EN | M4)) /* GPIO_110 */\ - MUX_VAL(CP(CAM_D4), (IEN | PTU | EN | M4)) /* GPIO_103 */\ -/* GPMC CS7 has LAN9211 device */\ - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\ - MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M4)) /* LAN9221 */\ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M0)) /* MCSPI1_CS2 */\ -/* GPMC CS3 has Serial TL16CP754C device */\ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPMC_nCS3 */\ -/* Toggle Reset pin of TL16CP754C device */\ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTU | EN | M4)) /* GPIO_152 */\ - udelay(10);\ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | EN | M4)) /* GPIO_152 */\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */\ -/* LEDS */\ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M4)) /* GPIO_173 red */\ - MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | EN | M4)) /* GPIO_154 blue */\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | EN | M4)) /* GPIO_61 blue2 */ - -#endif /* _BOARD_ZOOM2_H_ */ diff --git a/board/logicpd/zoom2/zoom2_serial.c b/board/logicpd/zoom2/zoom2_serial.c deleted file mode 100644 index 29592761161..00000000000 --- a/board/logicpd/zoom2/zoom2_serial.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * SPDX-License-Identifier: GPL-2.0+ - * - * This file was adapted from arch/powerpc/cpu/mpc5xxx/serial.c - */ - -#include -#include -#include -#include -#include "zoom2_serial.h" - -int quad_init_dev (unsigned long base) -{ - /* - * The Quad UART is on the debug board. - * Check if the debug board is attached before using the UART - */ - if (zoom2_debug_board_connected ()) { - NS16550_t com_port = (NS16550_t) base; - int baud_divisor = CONFIG_SYS_NS16550_CLK / 16 / - CONFIG_BAUDRATE; - - /* - * Zoom2 has a board specific initialization of its UART. - * This generic initialization has been copied from - * drivers/serial/ns16550.c. The macros have been expanded. - * - * Do the following instead of - * - * NS16550_init (com_port, clock_divisor); - */ - com_port->ier = 0x00; - - /* - * On Zoom2 board Set pre-scalar to 1 - * CLKSEL is GND => MCR[7] is 1 => preslr is 4 - * So change the prescl to 1 - */ - com_port->lcr = 0xBF; - com_port->fcr |= 0x10; - com_port->mcr &= 0x7F; - - /* This is generic ns16550.c setup */ - com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1; - com_port->dll = 0; - com_port->dlm = 0; - com_port->lcr = UART_LCR_8N1; - com_port->mcr = UART_MCR_DTR | UART_MCR_RTS; - com_port->fcr = UART_FCR_FIFO_EN | UART_FCR_RXSR | - UART_FCR_TXSR; - com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1; - com_port->dll = baud_divisor & 0xff; - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = UART_LCR_8N1; - } - /* - * We have to lie here, otherwise the board init code will hang - * on the check - */ - return 0; -} - -void quad_putc_dev (unsigned long base, const char c) -{ - if (zoom2_debug_board_connected ()) { - - if (c == '\n') - quad_putc_dev (base, '\r'); - - NS16550_putc ((NS16550_t) base, c); - } else { - usbtty_putc(c); - } -} - -void quad_puts_dev (unsigned long base, const char *s) -{ - if (zoom2_debug_board_connected ()) { - while ((s != NULL) && (*s != '\0')) - quad_putc_dev (base, *s++); - } else { - usbtty_puts(s); - } -} - -int quad_getc_dev (unsigned long base) -{ - if (zoom2_debug_board_connected ()) - return NS16550_getc ((NS16550_t) base); - - return usbtty_getc(); -} - -int quad_tstc_dev (unsigned long base) -{ - if (zoom2_debug_board_connected ()) - return NS16550_tstc ((NS16550_t) base); - - return usbtty_tstc(); -} - -void quad_setbrg_dev (unsigned long base) -{ - if (zoom2_debug_board_connected ()) { - - int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / - CONFIG_BAUDRATE; - - NS16550_reinit ((NS16550_t) base, clock_divisor); - } -} - -QUAD_INIT (0) -QUAD_INIT (1) -QUAD_INIT (2) -QUAD_INIT (3) - -struct serial_device *default_serial_console(void) -{ - switch (ZOOM2_DEFAULT_SERIAL_DEVICE) { - case 0: return &zoom2_serial_device0; - case 1: return &zoom2_serial_device1; - case 2: return &zoom2_serial_device2; - case 3: return &zoom2_serial_device3; - } -} diff --git a/board/logicpd/zoom2/zoom2_serial.h b/board/logicpd/zoom2/zoom2_serial.h deleted file mode 100644 index 82244521ac5..00000000000 --- a/board/logicpd/zoom2/zoom2_serial.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef ZOOM2_SERIAL_H -#define ZOOM2_SERIAL_H - -#include - -extern int zoom2_debug_board_connected (void); - -#define SERIAL_TL16CP754C_BASE 0x10000000 /* Zoom2 Serial chip address */ - -#define QUAD_BASE_0 SERIAL_TL16CP754C_BASE -#define QUAD_BASE_1 (SERIAL_TL16CP754C_BASE + 0x100) -#define QUAD_BASE_2 (SERIAL_TL16CP754C_BASE + 0x200) -#define QUAD_BASE_3 (SERIAL_TL16CP754C_BASE + 0x300) - -#define QUAD_INIT(n) \ -int quad_init_##n(void) \ -{ \ - return quad_init_dev(QUAD_BASE_##n); \ -} \ -void quad_setbrg_##n(void) \ -{ \ - quad_setbrg_dev(QUAD_BASE_##n); \ -} \ -void quad_putc_##n(const char c) \ -{ \ - quad_putc_dev(QUAD_BASE_##n, c); \ -} \ -void quad_puts_##n(const char *s) \ -{ \ - quad_puts_dev(QUAD_BASE_##n, s); \ -} \ -int quad_getc_##n(void) \ -{ \ - return quad_getc_dev(QUAD_BASE_##n); \ -} \ -int quad_tstc_##n(void) \ -{ \ - return quad_tstc_dev(QUAD_BASE_##n); \ -} \ -struct serial_device zoom2_serial_device##n = \ -{ \ - .name = __stringify(n), \ - .start = quad_init_##n, \ - .stop = NULL, \ - .setbrg = quad_setbrg_##n, \ - .getc = quad_getc_##n, \ - .tstc = quad_tstc_##n, \ - .putc = quad_putc_##n, \ - .puts = quad_puts_##n, \ -}; - -#endif /* ZOOM2_SERIAL_H */ diff --git a/boards.cfg b/boards.cfg index 9949bb53672..a49fa660891 100644 --- a/boards.cfg +++ b/boards.cfg @@ -326,7 +326,6 @@ Active arm armv7 omap3 isee igep00x0 Active arm armv7 omap3 logicpd am3517evm am3517_evm - Vaibhav Hiremath Active arm armv7 omap3 logicpd omap3som omap3_logic - Peter Barada Active arm armv7 omap3 logicpd zoom1 omap3_zoom1 - Nishanth Menon -Active arm armv7 omap3 logicpd zoom2 omap3_zoom2 - Tom Rix Active arm armv7 omap3 matrix_vision mvblx omap3_mvblx - Michael Jones Active arm armv7 omap3 nokia rx51 nokia_rx51 - Pali Rohár Active arm armv7 omap3 technexion tao3530 omap3_ha tao3530:SYS_BOARD_OMAP3_HA Stefan Roese diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 181c81815ac..fbc37b27e8e 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -56,9 +56,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) ; serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); -#if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \ - defined(CONFIG_AM33XX) || defined(CONFIG_TI81XX) || \ - defined(CONFIG_AM43XX) +#if defined(CONFIG_OMAP) || defined(CONFIG_AM33XX) || \ + defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX) serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ #endif serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h deleted file mode 100644 index f7497408158..00000000000 --- a/include/configs/omap3_zoom2.h +++ /dev/null @@ -1,237 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Texas Instruments. - * Richard Woodruff - * Syed Mohammed Khasim - * Nishanth Menon - * Tom Rix - * - * Configuration settings for the TI OMAP3430 Zoom II board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */ -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON - -#define CONFIG_SDRC /* The chip has SDRC controller */ - -#include /* get chip and board defs */ -#include - -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -#define CONFIG_OF_LIBFDT 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - * Zoom2 uses the TL16CP754C on the debug board - */ -/* - * 0 - 1 : first USB with respect to the left edge of the debug board - * 2 - 3 : second USB with respect to the left edge of the debug board - */ -#define ZOOM2_DEFAULT_SERIAL_DEVICE 0 - -#define V_NS16550_CLK (1843200) /* 1.8432 Mhz */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_REG_SIZE (-2) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {115200} - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 - -/* Status LED */ -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED 1 -#define STATUS_LED_BLUE 0 -#define STATUS_LED_RED 1 -/* Blue */ -#define STATUS_LED_BIT STATUS_LED_BLUE -#define STATUS_LED_STATE STATUS_LED_ON -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -/* Red */ -#define STATUS_LED_BIT1 STATUS_LED_RED -#define STATUS_LED_STATE1 STATUS_LED_OFF -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) -/* Optional value */ -#define STATUS_LED_BOOT STATUS_LED_BIT - -/* GPIO banks */ -#ifdef CONFIG_STATUS_LED -#define CONFIG_OMAP3_GPIO_2 /* ZOOM2_LED_BLUE2 */ -#define CONFIG_OMAP3_GPIO_6 /* ZOOM2_LED_RED */ -#endif -#define CONFIG_OMAP3_GPIO_3 /* board revision */ -#define CONFIG_OMAP3_GPIO_5 /* debug board detection, ZOOM2_LED_BLUE */ - -/* USB */ -#define CONFIG_MUSB_UDC 1 -#define CONFIG_USB_OMAP3 1 -#define CONFIG_TWL4030_USB 1 - -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "Zoom2" - -/* commands to include */ -#include - -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_NAND /* NAND support */ -#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */ - -#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ -#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ -#undef CONFIG_CMD_IMI /* iminfo */ -#undef CONFIG_CMD_IMLS /* List all found images */ -#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ -#undef CONFIG_CMD_NFS /* NFS support */ - -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_I2C -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_OMAP34XX - -/* - * TWL4030 - */ -#define CONFIG_TWL4030_POWER 1 -#define CONFIG_TWL4030_LED 1 - -/* - * Board NAND Info. - */ -#define CONFIG_NAND_OMAP_GPMC -#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ - /* to access nand */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* Environment information */ -#define CONFIG_BOOTDELAY 10 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "usbtty=cdc_acm\0" \ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_PROMPT "OMAP3 Zoom2 # " -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) -/* Memtest from start of memory to 31MB */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000) -/* The default load address is the start of memory */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) -/* everything, incl board info, in Hz */ -#undef CONFIG_SYS_CLKS_IN_HZ -/* - * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by - * 32KHz clk, or from external sig. This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */ -#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV)) - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE -#endif - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_ENV_IS_IN_NAND 1 -#define SMNAND_ENV_OFFSET 0x0c0000 /* environment starts here */ - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET -#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET - -#define CONFIG_SYS_CACHELINE_SIZE 64 - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From e0a1d598ef0155f31589c42db17ff4784e84ca67 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Tue, 7 Jan 2014 19:57:38 +0530 Subject: ARM: dra7_evm: read mac address properly from e-fuse Byte offset of Ethernet mac address read from e-fuse are wrong so DHCP is not working on some boards, modifying the offset to read properly. Signed-off-by: Mugunthan V N --- board/ti/dra7xx/evm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 9ae88c57a41..1b60b8f672e 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -202,12 +202,12 @@ int board_eth_init(bd_t *bis) /* try reading mac address from efuse */ mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); - mac_addr[0] = mac_hi & 0xFF; + mac_addr[0] = (mac_hi & 0xFF0000) >> 16; mac_addr[1] = (mac_hi & 0xFF00) >> 8; - mac_addr[2] = (mac_hi & 0xFF0000) >> 16; - mac_addr[3] = mac_lo & 0xFF; + mac_addr[2] = mac_hi & 0xFF; + mac_addr[3] = (mac_lo & 0xFF0000) >> 16; mac_addr[4] = (mac_lo & 0xFF00) >> 8; - mac_addr[5] = (mac_lo & 0xFF0000) >> 16; + mac_addr[5] = mac_lo & 0xFF; if (!getenv("ethaddr")) { printf(" not set. Validating first E-fuse MAC\n"); -- cgit v1.3.1 From 129168290a9a21afb4cbb899cdc25580cbe5921c Mon Sep 17 00:00:00 2001 From: David Feng Date: Sat, 14 Dec 2013 11:47:37 +0800 Subject: arm64: board support of vexpress_aemv8a Signed-off-by: David Feng Signed-off-by: Bhupesh Sharma --- board/armltd/vexpress64/Makefile | 8 ++ board/armltd/vexpress64/vexpress64.c | 56 +++++++++++ boards.cfg | 1 + include/configs/vexpress_aemv8a.h | 189 +++++++++++++++++++++++++++++++++++ 4 files changed, 254 insertions(+) create mode 100644 board/armltd/vexpress64/Makefile create mode 100644 board/armltd/vexpress64/vexpress64.c create mode 100644 include/configs/vexpress_aemv8a.h (limited to 'board') diff --git a/board/armltd/vexpress64/Makefile b/board/armltd/vexpress64/Makefile new file mode 100644 index 00000000000..e009141a426 --- /dev/null +++ b/board/armltd/vexpress64/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := vexpress64.o diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c new file mode 100644 index 00000000000..2ec3bc9835c --- /dev/null +++ b/board/armltd/vexpress64/vexpress64.c @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2013 + * David Feng + * Sharma Bhupesh + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + /* + * Clear spin table so that secondary processors + * observe the correct value after waken up from wfe. + */ + *(unsigned long *)CPU_RELEASE_ADDR = 0; + + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +int timer_init(void) +{ + return 0; +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ +} + +/* + * Board specific ethernet initialization routine. + */ +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} diff --git a/boards.cfg b/boards.cfg index ba88c1d0447..e1685905720 100644 --- a/boards.cfg +++ b/boards.cfg @@ -397,6 +397,7 @@ Active arm pxa - - vpac270 Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich Active arm pxa - toradex - colibri_pxa270 - Marek Vasut Active arm sa1100 - - - jornada - Kristoffer Ericson +Active arm armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng Active avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas Bießmann Active avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h new file mode 100644 index 00000000000..ce5f3847760 --- /dev/null +++ b/include/configs/vexpress_aemv8a.h @@ -0,0 +1,189 @@ +/* + * Configuration for Versatile Express. Parts were derived from other ARM + * configurations. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __VEXPRESS_AEMV8A_H +#define __VEXPRESS_AEMV8A_H + +#define DEBUG + +#define CONFIG_REMAKE_ELF + +/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/ + +/*#define CONFIG_SYS_GENERIC_BOARD*/ + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SUPPORT_RAW_INITRD + +/* Cache Definitions */ +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_ICACHE_OFF + +#define CONFIG_IDENT_STRING " vexpress_aemv8a" +#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a" + +/* Link Definitions */ +#define CONFIG_SYS_TEXT_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_LIBFDT + +#define CONFIG_DEFAULT_DEVICE_TREE vexpress64 + +/* SMP Spin Table Definitions */ +#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + +/* CS register bases for the original memory map. */ +#define V2M_PA_CS0 0x00000000 +#define V2M_PA_CS1 0x14000000 +#define V2M_PA_CS2 0x18000000 +#define V2M_PA_CS3 0x1c000000 +#define V2M_PA_CS4 0x0c000000 +#define V2M_PA_CS5 0x10000000 + +#define V2M_PERIPH_OFFSET(x) (x << 16) +#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) +#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) +#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) + +#define V2M_BASE 0x80000000 + +/* + * Physical addresses, offset from V2M_PA_CS0-3 + */ +#define V2M_NOR0 (V2M_PA_CS0) +#define V2M_NOR1 (V2M_PA_CS4) +#define V2M_SRAM (V2M_PA_CS1) + +/* Common peripherals relative to CS7. */ +#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) +#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) +#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) +#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) + +#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) +#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) +#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) +#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) + +#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) + +#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) +#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) + +#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) +#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) + +#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) + +#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) + +/* System register offsets. */ +#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) +#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) +#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE (0x2C001000) +#define GICC_BASE (0x2C002000) + +#define CONFIG_SYS_MEMTEST_START V2M_BASE +#define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x80000000) + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) + +/* SMSC9115 Ethernet from SMSC9118 family */ +#define CONFIG_SMC9111 1 +#define CONFIG_SMC9111_BASE (0x1a000000) + +/* PL011 Serial Configuration */ +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK 24000000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1} +#define CONFIG_CONS_INDEX 0 + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_SERIAL0 V2M_UART0 +#define CONFIG_SYS_SERIAL1 V2M_UART1 + +/* Command line configuration */ +#define CONFIG_MENU +/*#define CONFIG_MENU_SHOW*/ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_BDI +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PXE +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMI +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_RUN +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_SOURCE +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2048 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr=0x200000\0" \ + "initrd_addr=0xa00000\0" \ + "initrd_size=0x2000000\0" \ + "fdt_addr=0x100000\0" \ + "fdt_high=0xa0000000\0" + +#define CONFIG_BOOTARGS "console=ttyAMA0 root=/dev/ram0" +#define CONFIG_BOOTCOMMAND "bootm $kernel_addr " \ + "$initrd_addr:$initrd_size $fdt_addr" +#define CONFIG_BOOTDELAY -1 + +/* Do not preserve environment */ +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE 0x1000 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "VExpress64# " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#endif /* __VEXPRESS_AEMV8A_H */ -- cgit v1.3.1 From b3de92495f23db58a2643fb9328edacbf9a17f1c Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:21 +0530 Subject: zynq: Add support to find bootmode Added support to find the bootmodes by reading slcr bootmode register. this can be helpful to autoboot the configurations w.r.t a specified bootmode. Added this functionality on board_late_init as it's not needed for normal initializtion part. Signed-off-by: Jagannadha Sutradharudu Teki --- arch/arm/cpu/armv7/zynq/slcr.c | 6 ++++++ arch/arm/include/asm/arch-zynq/sys_proto.h | 1 + board/xilinx/zynq/board.c | 25 +++++++++++++++++++++++++ doc/README.zynq | 25 +++++++++++++++++++++++-- include/configs/zynq-common.h | 1 + 5 files changed, 56 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 717ec65aeee..b4c11c324c0 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -101,6 +101,12 @@ void zynq_slcr_devcfg_enable(void) zynq_slcr_lock(); } +u32 zynq_slcr_get_boot_mode(void) +{ + /* Get the bootmode register value */ + return readl(&slcr_base->boot_mode); +} + u32 zynq_slcr_get_idcode(void) { return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >> diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index 110de909221..8f925af8a41 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -13,6 +13,7 @@ extern void zynq_slcr_cpu_reset(void); extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk); extern void zynq_slcr_devcfg_disable(void); extern void zynq_slcr_devcfg_enable(void); +extern u32 zynq_slcr_get_boot_mode(void); extern u32 zynq_slcr_get_idcode(void); extern void zynq_ddrc_init(void); diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 5119c09037e..a5b9bdef46a 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -12,6 +12,12 @@ DECLARE_GLOBAL_DATA_PTR; +/* Bootmode setting values */ +#define ZYNQ_BM_MASK 0x0F +#define ZYNQ_BM_NOR 0x02 +#define ZYNQ_BM_SD 0x05 +#define ZYNQ_BM_JTAG 0x0 + #ifdef CONFIG_FPGA Xilinx_desc fpga; @@ -59,6 +65,25 @@ int board_init(void) return 0; } +int board_late_init(void) +{ + switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { + case ZYNQ_BM_NOR: + setenv("modeboot", "norboot"); + break; + case ZYNQ_BM_SD: + setenv("modeboot", "sdboot"); + break; + case ZYNQ_BM_JTAG: + setenv("modeboot", "jtagboot"); + break; + default: + setenv("modeboot", ""); + break; + } + + return 0; +} #ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bis) diff --git a/doc/README.zynq b/doc/README.zynq index 56a74b4f1f0..ea1c8c14124 100644 --- a/doc/README.zynq +++ b/doc/README.zynq @@ -28,7 +28,27 @@ and I/O programmability. - zc770-xm012 (nor) - zc770-xm013 (dual parallel qspi, gem1) -3. Mainline status +3. Bootmode + +Zynq has a facility to read the bootmode from the slcr bootmode register +once user is setting through jumpers on the board - see page no:1546 on [5] + +All possible bootmode values are defined in Table 6-2:Boot_Mode MIO Pins +on [5]. + +board_late_init() will read the bootmode values using slcr bootmode register +at runtime and assign the modeboot variable to specific bootmode string which +is intern used in autoboot. + +SLCR bootmode register Bit[3:0] values +#define ZYNQ_BM_NOR 0x02 +#define ZYNQ_BM_SD 0x05 +#define ZYNQ_BM_JTAG 0x0 + +"modeboot" variable can assign any of "norboot", "sdboot" or "jtagboot" +bootmode strings at runtime. + +4. Mainline status - Added basic board configurations support. - Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq @@ -41,7 +61,7 @@ and I/O programmability. spi- drivers/spi/zynq_spi.c i2c - drivers/i2c/zynq_i2c.c -4. TODO +5. TODO - Add zynq boards support - zc70x, zed, microzed, zc770 - Add zynq qspi controller driver @@ -54,6 +74,7 @@ and I/O programmability. [2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm [3] http://zedboard.org/product/zedboard [4] http://zedboard.org/product/microzed +[5] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf -- Jagannadha Sutradharudu Teki diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index db47c421740..b1fa0cb8ea8 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -140,6 +140,7 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_AUTO_COMPLETE +#define CONFIG_BOARD_LATE_INIT #define CONFIG_SYS_LONGHELP #define CONFIG_SYS_MAXARGS 15 /* max number of command args */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -- cgit v1.3.1 From f8f36c5dda67c53c471d1fe65215b9124ef62d71 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:26 +0530 Subject: dts: zynq: Add basic fdt support This patch provides a basic fdt support for zynq u-boot. zynq-7000.dtsi-> initial arch dts file zynq-zed.dts -> initial zed board dts file more devices should be added in subsequent patches. u-boot build: once configuring of a board done for building dtb with zynq-zed.dts as an input zynq-uboot> make DEVICE_TREE=zynq-zed Enabled CONFIG_OF_SEPARATE for building dtb separately. There is a new binary called u-boot-dtb.bin which is a u-boot with devicetree supported. Signed-off-by: Jagannadha Sutradharudu Teki --- arch/arm/dts/zynq-7000.dtsi | 13 +++++++++++++ board/xilinx/dts/zynq-zed.dts | 14 ++++++++++++++ include/configs/zynq-common.h | 5 +++++ 3 files changed, 32 insertions(+) create mode 100644 arch/arm/dts/zynq-7000.dtsi create mode 100644 board/xilinx/dts/zynq-zed.dts (limited to 'board') diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi new file mode 100644 index 00000000000..f20b8bd604d --- /dev/null +++ b/arch/arm/dts/zynq-7000.dtsi @@ -0,0 +1,13 @@ +/* + * Xilinx Zynq 7000 DTSI + * Describes the hardware common to all Zynq 7000-based boards. + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/include/ "skeleton.dtsi" + +/ { + compatible = "xlnx,zynq-7000"; +}; diff --git a/board/xilinx/dts/zynq-zed.dts b/board/xilinx/dts/zynq-zed.dts new file mode 100644 index 00000000000..91a5deba4a9 --- /dev/null +++ b/board/xilinx/dts/zynq-zed.dts @@ -0,0 +1,14 @@ +/* + * Xilinx ZED board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZED Board"; + compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; +}; diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 184d4ba820b..8707bc00c01 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -212,6 +212,11 @@ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ +/* FDT support */ +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE +#define CONFIG_DISPLAY_BOARDINFO_LATE + /* Boot FreeBSD/vxWorks from an ELF image */ #if defined(CONFIG_ZYNQ_BOOT_FREEBSD) # define CONFIG_API -- cgit v1.3.1 From 9e0802bf821074a90d3bb5c9d4d9d3424d8c51aa Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:29 +0530 Subject: dts: zynq: Add more zynq dts files This patch adds initial dts support for supported zynq boards. Signed-off-by: Jagannadha Sutradharudu Teki --- board/xilinx/dts/zynq-microzed.dts | 14 ++++++++++++++ board/xilinx/dts/zynq-zc702.dts | 14 ++++++++++++++ board/xilinx/dts/zynq-zc706.dts | 14 ++++++++++++++ board/xilinx/dts/zynq-zc770-xm010.dts | 14 ++++++++++++++ board/xilinx/dts/zynq-zc770-xm012.dts | 14 ++++++++++++++ board/xilinx/dts/zynq-zc770-xm013.dts | 14 ++++++++++++++ 6 files changed, 84 insertions(+) create mode 100644 board/xilinx/dts/zynq-microzed.dts create mode 100644 board/xilinx/dts/zynq-zc702.dts create mode 100644 board/xilinx/dts/zynq-zc706.dts create mode 100644 board/xilinx/dts/zynq-zc770-xm010.dts create mode 100644 board/xilinx/dts/zynq-zc770-xm012.dts create mode 100644 board/xilinx/dts/zynq-zc770-xm013.dts (limited to 'board') diff --git a/board/xilinx/dts/zynq-microzed.dts b/board/xilinx/dts/zynq-microzed.dts new file mode 100644 index 00000000000..6da71c116d0 --- /dev/null +++ b/board/xilinx/dts/zynq-microzed.dts @@ -0,0 +1,14 @@ +/* + * Xilinx MicroZED board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq MicroZED Board"; + compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000"; +}; diff --git a/board/xilinx/dts/zynq-zc702.dts b/board/xilinx/dts/zynq-zc702.dts new file mode 100644 index 00000000000..667dc282563 --- /dev/null +++ b/board/xilinx/dts/zynq-zc702.dts @@ -0,0 +1,14 @@ +/* + * Xilinx ZC702 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC702 Board"; + compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; +}; diff --git a/board/xilinx/dts/zynq-zc706.dts b/board/xilinx/dts/zynq-zc706.dts new file mode 100644 index 00000000000..526fc8888ba --- /dev/null +++ b/board/xilinx/dts/zynq-zc706.dts @@ -0,0 +1,14 @@ +/* + * Xilinx ZC706 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC706 Board"; + compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; +}; diff --git a/board/xilinx/dts/zynq-zc770-xm010.dts b/board/xilinx/dts/zynq-zc770-xm010.dts new file mode 100644 index 00000000000..8b542a109be --- /dev/null +++ b/board/xilinx/dts/zynq-zc770-xm010.dts @@ -0,0 +1,14 @@ +/* + * Xilinx ZC770 XM010 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC770 XM010 Board"; + compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; +}; diff --git a/board/xilinx/dts/zynq-zc770-xm012.dts b/board/xilinx/dts/zynq-zc770-xm012.dts new file mode 100644 index 00000000000..0379a070681 --- /dev/null +++ b/board/xilinx/dts/zynq-zc770-xm012.dts @@ -0,0 +1,14 @@ +/* + * Xilinx ZC770 XM012 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC770 XM012 Board"; + compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; +}; diff --git a/board/xilinx/dts/zynq-zc770-xm013.dts b/board/xilinx/dts/zynq-zc770-xm013.dts new file mode 100644 index 00000000000..a4f9e05fc0e --- /dev/null +++ b/board/xilinx/dts/zynq-zc770-xm013.dts @@ -0,0 +1,14 @@ +/* + * Xilinx ZC770 XM013 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC770 XM013 Board"; + compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; +}; -- cgit v1.3.1