From 362635bd50e386770ebaa2d5d090eb8cbf96430b Mon Sep 17 00:00:00 2001 From: Benoît Thébaudeau Date: Tue, 18 Sep 2012 04:48:42 +0000 Subject: mx51evk: Add CONFIG_REVISION_TAG MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. If this data is not present, the kernel misconfigures the TZIC, which results in the timer interrupt handler never being called, so the kernel deadlocks while calibrating its delay. Suggested-by: Greg Topmiller Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic Cc: Fabio Estevam Acked-by: Fabio Estevam --- board/freescale/mx51evk/mx51evk.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'board') diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 7a0682a7e96..a94701cbf17 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -60,6 +60,14 @@ int dram_init(void) return 0; } +u32 get_board_rev(void) +{ + u32 rev = get_cpu_rev(); + if (!gpio_get_value(IMX_GPIO_NR(1, 22))) + rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET; + return rev; +} + static void setup_iomux_uart(void) { unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | -- cgit v1.3.1 From 5527024fdb10798d2975197f287457b29e2d4084 Mon Sep 17 00:00:00 2001 From: Benoît Thébaudeau Date: Wed, 8 Aug 2012 03:55:32 +0000 Subject: KARO TX25: Fix NAND Flash R/W cycle times MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The NAND Flash of the KARO TX25 board is a Samsung K9F1G08U0B with 25-ns R/W cycle times. However, the NFC clock for this board was set to 66.5 MHz, so using the NFC driver in symmetric mode (i.e. 1 NFC clock cycle = 1 NF R/W cycle) resulted in NF R/W cycle times of 15 ns, hence corrupted NF accesses. This patch fixes this issue by setting the NFC clock to the highest frequency complying to the 25-ns NF R/W cycle times specification, i.e. 33.25 MHz. Signed-off-by: Benoît Thébaudeau Cc: John Rigby Cc: Scott Wood Cc: Stefano Babic Cc: Daniel Gachet Acked-by: Stefano Babic --- board/karo/tx25/lowlevel_init.S | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'board') diff --git a/board/karo/tx25/lowlevel_init.S b/board/karo/tx25/lowlevel_init.S index 823df10701e..eb3f187806e 100644 --- a/board/karo/tx25/lowlevel_init.S +++ b/board/karo/tx25/lowlevel_init.S @@ -66,6 +66,14 @@ write32 0x53f80064, 0x45600000 write32 0x53f80008, 0x20034000 + /* + * PCDR2: NFC = 33.25 MHz + * This is required for the NAND Flash of this board, which is a Samsung + * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with + * the NFC driver in symmetric (i.e. one-cycle) mode. + */ + write32 0x53f80020, 0x01010103 + /* * enable all implemented clocks in all three * clock control registers -- cgit v1.3.1 From 5436eaeab9155633fd858e0a6b876d1077348d94 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 21 Sep 2012 10:00:53 +0000 Subject: mx28evk: Remove fecmxc_mii_postcall() fecmxc_mii_postcall() is specific to the KSZ9021 PHY on m28evk and should not be used on mx28evk, which has LAN8270 instead. Signed-off-by: Fabio Estevam Acked-by: Marek Vasut --- board/freescale/mx28evk/mx28evk.c | 25 ------------------------- 1 file changed, 25 deletions(-) (limited to 'board') diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c index d782aea61b8..6e719ffc39f 100644 --- a/board/freescale/mx28evk/mx28evk.c +++ b/board/freescale/mx28evk/mx28evk.c @@ -100,19 +100,6 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_CMD_NET -#define MII_OPMODE_STRAP_OVERRIDE 0x16 -#define MII_PHY_CTRL1 0x1e -#define MII_PHY_CTRL2 0x1f - -int fecmxc_mii_postcall(int phy) -{ - miiphy_write("FEC1", phy, MII_BMCR, 0x9000); - miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202); - if (phy == 3) - miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180); - return 0; -} - int board_eth_init(bd_t *bis) { struct mxs_clkctrl_regs *clkctrl_regs = @@ -152,24 +139,12 @@ int board_eth_init(bd_t *bis) return -EINVAL; } - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - puts("FEC MXS: Unable to register FEC0 mii postcall\n"); - return ret; - } - dev = eth_get_dev_by_name("FEC1"); if (!dev) { puts("FEC MXS: Unable to get FEC1 device entry\n"); return -EINVAL; } - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - puts("FEC MXS: Unable to register FEC1 mii postcall\n"); - return ret; - } - return ret; } -- cgit v1.3.1