From 64123e3f06f74dd09b86e2a41d77d31044f495fb Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Tue, 20 Apr 2010 08:11:40 -0400 Subject: Fix typos in Korat board console output Signed-off-by: Larry Johnson Signed-off-by: Stefan Roese --- board/korat/korat.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/korat/korat.c b/board/korat/korat.c index d5260dc232e..e5ec6947023 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007-2009 + * (C) Copyright 2007-2010 * Larry Johnson, lrj@acm.org * * (C) Copyright 2006-2007 @@ -417,7 +417,7 @@ int misc_init_r(void) * then connect the CompactFlash controller to the PowerPC USB * port. */ - printf("Attaching CompactFalsh controller to PPC USB\n"); + printf("Attaching CompactFlash controller to PPC USB\n"); out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02) | 0x10); } else { @@ -425,7 +425,7 @@ int misc_init_r(void) printf("Warning: \"korat_usbcf\" is not set to a legal " "value (\"ppc\" or \"pci\")\n"); - printf("Attaching CompactFalsh controller to PCI USB\n"); + printf("Attaching CompactFlash controller to PCI USB\n"); } if (act == NULL || strcmp(act, "hostdev") == 0) { /* SDR Setting */ -- cgit v1.3.1 From 029faf3e85e9406f32f133e6f2a114ed26b02fb4 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 27 Apr 2010 11:37:28 +0200 Subject: ppc4xx: Add support for ICON board (PPC440SPe) This patch adds support for the Mosaix Technologies, Inc. ICON board, based on the AppliedMicro (AMCC) PPC440SPe. It's equipped with an SODIMM (512MB standard) and 64MByte of NOR FLASH. Support for the onboard SM502 will be added later. Signed-off-by: Stefan Roese --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/mosaixtech/icon/Makefile | 53 ++++++ board/mosaixtech/icon/chip_config.c | 55 +++++++ board/mosaixtech/icon/config.mk | 34 ++++ board/mosaixtech/icon/icon.c | 319 ++++++++++++++++++++++++++++++++++++ board/mosaixtech/icon/init.S | 88 ++++++++++ include/configs/icon.h | 308 ++++++++++++++++++++++++++++++++++ 9 files changed, 862 insertions(+) create mode 100644 board/mosaixtech/icon/Makefile create mode 100644 board/mosaixtech/icon/chip_config.c create mode 100644 board/mosaixtech/icon/config.mk create mode 100644 board/mosaixtech/icon/icon.c create mode 100644 board/mosaixtech/icon/init.S create mode 100644 include/configs/icon.h (limited to 'board') diff --git a/MAINTAINERS b/MAINTAINERS index a5d5835d620..00e06b7c2c7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -368,6 +368,7 @@ Stefan Roese ebony PPC440GP glacier PPC460GT haleakala PPC405EXr + icon PPC440SPe katmai PPC440SPe kilauea PPC405EX lwmon5 PPC440EPx diff --git a/MAKEALL b/MAKEALL index 4f99ea49617..71ae6180e47 100755 --- a/MAKEALL +++ b/MAKEALL @@ -224,6 +224,7 @@ LIST_4xx=" \ hcu5 \ HH405 \ HUB405 \ + icon \ intip \ JSE \ KAREF \ diff --git a/Makefile b/Makefile index 25e3b8c51c7..5fcbbb24e09 100644 --- a/Makefile +++ b/Makefile @@ -1357,6 +1357,9 @@ HH405_config: unconfig HUB405_config: unconfig @$(MKCONFIG) $(@:_config=) powerpc ppc4xx hub405 esd +icon_config: unconfig + @$(MKCONFIG) $(@:_config=) powerpc ppc4xx icon mosaixtech + # Compact-Center(codename intip) & DevCon-Center use different U-Boot images intip_config \ devconcenter_config: unconfig diff --git a/board/mosaixtech/icon/Makefile b/board/mosaixtech/icon/Makefile new file mode 100644 index 00000000000..dad0457f6bb --- /dev/null +++ b/board/mosaixtech/icon/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2009-2010 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o +COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o +SOBJS = init.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/mosaixtech/icon/chip_config.c b/board/mosaixtech/icon/chip_config.c new file mode 100644 index 00000000000..b9dd4472459 --- /dev/null +++ b/board/mosaixtech/icon/chip_config.c @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2009-2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include + +struct ppc4xx_config ppc4xx_config_val[] = { + { + "400-133", "CPU: 400 PLB: 133 OPB: 66 EBC: 66", + { 0x86, 0x78, 0xc2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 } + }, + { + "500-166", "CPU: 500 PLB: 166 OPB: 83 EBC: 83", + { 0x87, 0x78, 0xf2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 } + }, + { + "533-133", "CPU: 533 PLB: 133 OPB: 66 EBC: 66", + { 0x87, 0x79, 0x02, 0x52, 0x05, 0xa5, 0x04, 0xe1 } + }, + { + "667-133", "CPU: 667 PLB: 133 OPB: 66 EBC: 66", + { 0x87, 0x79, 0x42, 0x56, 0x05, 0xa5, 0x04, 0xe1 } + }, + { + "667-166", "CPU: 667 PLB: 166 OPB: 83 EBC: 83", + { 0x87, 0x79, 0x42, 0x06, 0x05, 0xa5, 0x04, 0xe1 } + }, + { + "800-160", "CPU: 800 PLB: 160 OPB: 53 EBC: 17", + { 0x86, 0x79, 0x81, 0xa7, 0x07, 0xa5, 0x04, 0xe1 } + }, +}; + +int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/mosaixtech/icon/config.mk b/board/mosaixtech/icon/config.mk new file mode 100644 index 00000000000..b2748ceccef --- /dev/null +++ b/board/mosaixtech/icon/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2009-2010 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFFA0000 + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 +endif diff --git a/board/mosaixtech/icon/icon.c b/board/mosaixtech/icon/icon.c new file mode 100644 index 00000000000..fbace9efe95 --- /dev/null +++ b/board/mosaixtech/icon/icon.c @@ -0,0 +1,319 @@ +/* + * (C) Copyright 2009-2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + unsigned long mfr; + + /* + * Interrupt controller setup for the ICON 440SPe board. + * + *-------------------------------------------------------------------- + * IRQ | Source | Pol. | Sensi.| Crit. + *--------+-----------------------------------+-------+-------+------- + * IRQ 00 | UART0 | High | Level | Non + * IRQ 01 | UART1 | High | Level | Non + * IRQ 02 | IIC0 | High | Level | Non + * IRQ 03 | IIC1 | High | Level | Non + * IRQ 04 | PCI0X0 MSG IN | High | Level | Non + * IRQ 05 | PCI0X0 CMD Write | High | Level | Non + * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non + * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non + * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non + * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non + * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non + * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit + * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non + * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non + * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non + * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non + * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non + * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit + * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non + * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non + * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non + * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non + * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non + * IRQ 23 | I2O Inbound Doorbell | High | Level | Non + * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non + * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non + * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non + * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non + * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non + * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non + * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non + * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. + *-------------------------------------------------------------------- + * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non + * IRQ 33 | MAL Serr | High | Level | Non + * IRQ 34 | MAL Txde | High | Level | Non + * IRQ 35 | MAL Rxde | High | Level | Non + * IRQ 36 | DMC CE or DMC UE | High | Level | Non + * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non + * IRQ 38 | MAL TX EOB | High | Level | Non + * IRQ 39 | MAL RX EOB | High | Level | Non + * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non + * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non + * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non + * IRQ 43 | L2 Cache | Risin | Edge | Non + * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non + * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non + * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non + * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non + * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non + * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non + * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non + * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non + * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non + * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non + * IRQ 54 | DMA Error | High | Level | Non + * IRQ 55 | DMA I2O Error | High | Level | Non + * IRQ 56 | Serial ROM | High | Level | Non + * IRQ 57 | PCIX0 Error | High | Edge | Non + * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non + * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non + * IRQ 60 | EMAC0 Interrupt | High | Level | Non + * IRQ 61 | EMAC0 Wake-up | High | Level | Non + * IRQ 62 | Reserved | High | Level | Non + * IRQ 63 | XOR | High | Level | Non + *-------------------------------------------------------------------- + * IRQ 64 | PE0 AL | High | Level | Non + * IRQ 65 | PE0 VPD Access | Risin | Edge | Non + * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non + * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non + * IRQ 68 | PE0 TCR | High | Level | Non + * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non + * IRQ 70 | PE0 DCR Error | High | Level | Non + * IRQ 71 | Reserved | N/A | N/A | Non + * IRQ 72 | PE1 AL | High | Level | Non + * IRQ 73 | PE1 VPD Access | Risin | Edge | Non + * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non + * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non + * IRQ 76 | PE1 TCR | High | Level | Non + * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non + * IRQ 78 | PE1 DCR Error | High | Level | Non + * IRQ 79 | Reserved | N/A | N/A | Non + * IRQ 80 | PE2 AL | High | Level | Non + * IRQ 81 | PE2 VPD Access | Risin | Edge | Non + * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non + * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non + * IRQ 84 | PE2 TCR | High | Level | Non + * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non + * IRQ 86 | PE2 DCR Error | High | Level | Non + * IRQ 87 | Reserved | N/A | N/A | Non + * IRQ 88 | External IRQ(5) | Progr | Progr | Non + * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non + * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non + * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non + * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non + * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non + * IRQ 94 | Reserved | N/A | N/A | Non + * IRQ 95 | Reserved | N/A | N/A | Non + *-------------------------------------------------------------------- + * IRQ 96 | PE0 INTA | High | Level | Non + * IRQ 97 | PE0 INTB | High | Level | Non + * IRQ 98 | PE0 INTC | High | Level | Non + * IRQ 99 | PE0 INTD | High | Level | Non + * IRQ 100| PE1 INTA | High | Level | Non + * IRQ 101| PE1 INTB | High | Level | Non + * IRQ 102| PE1 INTC | High | Level | Non + * IRQ 103| PE1 INTD | High | Level | Non + * IRQ 104| PE2 INTA | High | Level | Non + * IRQ 105| PE2 INTB | High | Level | Non + * IRQ 106| PE2 INTC | High | Level | Non + * IRQ 107| PE2 INTD | Risin | Edge | Non + * IRQ 108| PCI Express MSI Level 4 | Risin | Edge | Non + * IRQ 109| PCI Express MSI Level 5 | Risin | Edge | Non + * IRQ 110| PCI Express MSI Level 6 | Risin | Edge | Non + * IRQ 111| PCI Express MSI Level 7 | Risin | Edge | Non + * IRQ 116| PCI Express MSI Level 12 | Risin | Edge | Non + * IRQ 112| PCI Express MSI Level 8 | Risin | Edge | Non + * IRQ 113| PCI Express MSI Level 9 | Risin | Edge | Non + * IRQ 114| PCI Express MSI Level 10 | Risin | Edge | Non + * IRQ 115| PCI Express MSI Level 11 | Risin | Edge | Non + * IRQ 117| PCI Express MSI Level 13 | Risin | Edge | Non + * IRQ 118| PCI Express MSI Level 14 | Risin | Edge | Non + * IRQ 119| PCI Express MSI Level 15 | Risin | Edge | Non + * IRQ 120| PCI Express MSI Level 16 | Risin | Edge | Non + * IRQ 121| PCI Express MSI Level 17 | Risin | Edge | Non + * IRQ 122| PCI Express MSI Level 18 | Risin | Edge | Non + * IRQ 123| PCI Express MSI Level 19 | Risin | Edge | Non + * IRQ 124| PCI Express MSI Level 20 | Risin | Edge | Non + * IRQ 125| PCI Express MSI Level 21 | Risin | Edge | Non + * IRQ 126| PCI Express MSI Level 22 | Risin | Edge | Non + * IRQ 127| PCI Express MSI Level 23 | Risin | Edge | Non + */ + + /* + * Put UICs in PowerPC 440SPe mode. + * Initialise UIC registers. Clear all interrupts. Disable all + * interrupts. Set critical interrupt values. Set interrupt polarities. + * Set interrupt trigger levels. Make bit 0 High priority. Clear all + * interrupts again. + */ + mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */ + mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical IRQs */ + mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/ + mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ + mtdcr(UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */ + mtdcr(UIC3SR, 0x00000000); /* clear all interrupts*/ + mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts*/ + + mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC2ER, 0x00000000); /* disable all interrupts*/ + mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical IRQs */ + mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/ + mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ + mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */ + mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */ + mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */ + + mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts*/ + mtdcr(UIC1ER, 0x00000000); /* disable all interrupts*/ + mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical IRQs */ + mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr(UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/ + mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */ + mtdcr(UIC1SR, 0x00000000); /* clear all interrupts*/ + mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts*/ + + mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC0ER, 0x00000000); /* disable all int. excepted cascade */ + mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical IRQs */ + mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/ + mtdcr(UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */ + mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */ + mtdcr(UIC0SR, 0x00000000); /* clear all interrupts*/ + mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts*/ + + mfsdr(SDR0_MFR, mfr); + mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ + mtsdr(SDR0_MFR, mfr); + + mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0); + + out_be32((void *)GPIO0_OR, CONFIG_SYS_GPIO_OR); + out_be32((void *)GPIO0_ODR, CONFIG_SYS_GPIO_ODR); + out_be32((void *)GPIO0_TCR, CONFIG_SYS_GPIO_TCR); + + return 0; +} + +int board_early_init_r(void) +{ + /* + * ICON has 64MBytes of NOR FLASH (Spansion 29GL512), but the + * boot EBC mapping only supports a maximum of 16MBytes + * (4.ff00.0000 - 4.ffff.ffff). + * To solve this problem, the FLASH has to get remapped to another + * EBC address which accepts bigger regions: + * + * 0xfc00.0000 -> 4.ec00.0000 + */ + + /* Remap the NOR FLASH to 0xec00.0000 ... 0xefff.ffff */ + mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); + + /* Remove TLB entry of boot EBC mapping */ + remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20); + + /* Add TLB entry for 0xfc00.0000 -> 0x4.ec00.0000 */ + program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE); + + /* + * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address + * 0xfc00.0000 is possible + */ + + /* + * Clear potential errors resulting from auto-calibration. + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + set_mcsr(get_mcsr()); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: ICON"); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +/* + * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with + * board specific values. + * + * Tested successfully with the following SODIMM: + * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank) + * + * Tests with Micron MT4HTF6464HZ-667H1 showed problems in "cold" state, + * directly after power-up. Only after running for more than 10 minutes + * real stable auto-calibration windows could be found. + */ +u32 ddr_wrdtr(u32 default_val) +{ + return SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV; +} + +u32 ddr_clktr(u32 default_val) +{ + return SDRAM_CLKTR_CLKP_180_DEG_ADV; +} + +/* + * Override the weak default implementation and return the + * last PCIe slot number (max number - 1). + */ +int board_pcie_last(void) +{ + /* Only 2 PCIe ports used on ICON, so the last one is 1 */ + return 1; +} diff --git a/board/mosaixtech/icon/init.S b/board/mosaixtech/icon/init.S new file mode 100644 index 00000000000..70ed6ce13b6 --- /dev/null +++ b/board/mosaixtech/icon/init.S @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2009-2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + */ + + .section .bootpg,"ax" + + .globl tlbtab +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to + * use the speed up boot process. It is patched after relocation to + * enable SA_I. + */ + tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, + 4, AC_RWX | SA_G) /* TLB 0 */ + + /* + * TLB entries for SDRAM are not needed on this platform. + * They are dynamically generated in the SPD DDR(2) detection + * routine. + */ + + tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, + AC_RWX | SA_I) + + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, + AC_RW | SA_IG) + + tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, + CONFIG_SYS_ACE_BASE_PHYS_L, CONFIG_SYS_ACE_BASE_PHYS_H, + AC_RW | SA_IG) + + tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, + AC_RW | SA_IG) + + tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, + AC_RW | SA_IG) + tlbtab_end diff --git a/include/configs/icon.h b/include/configs/icon.h new file mode 100644 index 00000000000..3a57d695f9e --- /dev/null +++ b/include/configs/icon.h @@ -0,0 +1,308 @@ +/* + * (C) Copyright 2009-2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * icon.h - configuration for Mosaixtech ICON (440SPe) + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ICON 1 /* Board is icon */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_440SPE 1 /* Specifc SPe support */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ + +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME icon +#include "amcc-common.h" + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* later mapped to this addr */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ +#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ + +#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ +#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE + +#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ +#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* incr for PCIe port */ +#define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ + +#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000 +#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000 +#define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000 +#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000 +#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000 +#define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000 + +/* base address of inbound PCIe window */ +#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) + +#define CONFIG_SYS_ACE_BASE 0xfb000000 /* Xilinx ACE CF */ +#define CONFIG_SYS_ACE_BASE_PHYS_H 0x4 +#define CONFIG_SYS_ACE_BASE_PHYS_L 0xfe000000 + +#define CONFIG_SYS_FLASH_SIZE (64 << 20) +#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */ +#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4 +#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xEC000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \ + (u64)CONFIG_SYS_FLASH_BASE_PHYS_L) + +/* + * Initial RAM & stack pointer (placed in internal SRAM) + */ +#define CONFIG_SYS_TEMP_STACK_OCM 1 +#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Init RAM */ +#define CONFIG_SYS_INIT_RAM_END 0x2000 /* end used area */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* sizeof init data */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR + +/* + * Serial Port + */ +#undef CONFIG_UART1_CONSOLE +#undef CONFIG_SYS_EXT_SERIAL_CLOCK + +/* + * DDR2 SDRAM + */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS { 0x51 } /* SPD I2C SPD addresses */ +#define CONFIG_DDR_ECC /* with ECC support */ +#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */ + +/* + * I2C + */ +#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ + +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */ + +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C bootstrap EEPROM */ +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 +#define CONFIG_4xx_CONFIG_BLOCKSIZE 8 + +/* I2C RTC */ +#define CONFIG_RTC_M41T11 +#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */ + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "kernel_addr=fc000000\0" \ + "fdt_addr=fc1e0000\0" \ + "ramdisk_addr=fc200000\0" \ + "pciconfighost=1\0" \ + "pcie_mode=RP:RP:RP\0" \ + "" + +/* + * Commands additional to the ones defined in amcc-common.h + */ +#define CONFIG_CMD_CHIP_CONFIG +#define CONFIG_CMD_DATE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP + +#define CONFIG_IBM_EMAC4_V4 /* 440SPe has this EMAC version */ +#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ +#define CONFIG_HAS_ETH0 +#define CONFIG_PHY_RESET /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 1000 +#define CONFIG_CIS8201_PHY /* Enable RGMII mode for Cicada phy */ +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex det. */ + +/* + * FLASH related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET /* Use AMD (Spansion) reset cmd */ +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */ + +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors*/ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector */ + +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Env Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +/* + * PCI stuff + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_PCI_BOOTDELAY 1000 /* enable pci bootdelay variable*/ + +/* Board-specific PCI */ +#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ +#undef CONFIG_SYS_PCI_MASTER_INIT + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + +/* + * Xilinx System ACE support + */ +#define CONFIG_SYSTEMACE /* Enable SystemACE support */ +#define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */ +#define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE +#define CONFIG_DOS_PARTITION + +/* + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash) initialization */ +#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(7) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(0) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ + EBC_BXCR_BS_64MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) + +/* Memory Bank 1 (Xilinx System ACE controller) initialization */ +#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(4) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(0) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_NONDELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE_PHYS_L) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) + +/* + * Initialize EBC CONFIG - + * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC + * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 + */ +#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \ + EBC_CFG_PTD_ENABLE | \ + EBC_CFG_RTC_16PERCLK | \ + EBC_CFG_ATC_PREVIOUS | \ + EBC_CFG_DTC_PREVIOUS | \ + EBC_CFG_CTC_PREVIOUS | \ + EBC_CFG_OEO_PREVIOUS | \ + EBC_CFG_EMC_DEFAULT | \ + EBC_CFG_PME_DISABLE | \ + EBC_CFG_PR_16) + +/* + * GPIO Setup + */ +#define CONFIG_SYS_GPIO_PCIE_PRESENT0 17 +#define CONFIG_SYS_GPIO_PCIE_PRESENT1 21 +#define CONFIG_SYS_GPIO_PCIE_PRESENT2 23 +#define CONFIG_SYS_GPIO_RS232_FORCEOFF 30 + +#define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \ + GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \ + GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \ + GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)) +#define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) +#define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) +#define CONFIG_SYS_GPIO_ODR 0 + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 7769c5bc06615293870d00fc81366cd43ba0623a Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Tue, 13 Apr 2010 14:47:32 +0200 Subject: mvsmr: fix link error MVSMR board support doesn't link since recent rework of U-Boot directory structure. Fix it now. Signed-off-by: Anatolij Gustschin Cc: Andre Schwarz Acked-by: Andre Schwarz Fixed merge conflict Signed-off-by: Wolfgang Denk --- board/matrix_vision/mvsmr/u-boot.lds | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'board') diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds index 3e917a99c2e..f9b103e6175 100644 --- a/board/matrix_vision/mvsmr/u-boot.lds +++ b/board/matrix_vision/mvsmr/u-boot.lds @@ -55,11 +55,11 @@ SECTIONS { /* WARNING - the following is hand-optimized to fit within */ /* the first two sectors (=8KB) of our S29GL flash chip */ - arch/powerpc/cpu/mpc5xxx/start.o (.text) - arch/powerpc/cpu/mpc5xxx/traps.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/cache.o (.text) - arch/powerpc/lib/time.o (.text) + arch/powerpc/cpu/mpc5xxx/start.o (.text) + arch/powerpc/cpu/mpc5xxx/traps.o (.text) + lib/crc32.o (.text) + arch/powerpc/lib/cache.o (.text) + arch/powerpc/lib/time.o (.text) /* This is only needed to force failure if size of above code will ever */ /* increase and grow into reserved space. */ -- cgit v1.3.1 From 87db58dca47f93f9fb3b4ed0196dd7a3f5df1cb9 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Wed, 21 Apr 2010 13:52:38 +0200 Subject: tx25: fix crash while booting Linux Currently booting Linux on TX25 board doesn't work since there is no correct mach-id and boot parameters setup for tx25 board. Fix it now. Signed-off-by: Anatolij Gustschin Cc: John Rigby Cc: Stefano Babic --- board/karo/tx25/tx25.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'board') diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c index 4d6a96d20e3..2608698e290 100644 --- a/board/karo/tx25/tx25.c +++ b/board/karo/tx25/tx25.c @@ -145,6 +145,9 @@ int board_init() mx25_uart_init_pins(); #endif + /* board id for linux */ + gd->bd->bi_arch_number = MACH_TYPE_TX25; + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; return 0; } -- cgit v1.3.1 From 68c07a0c215a64826ed13c2f9b00a6d3b298822e Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 18 Apr 2010 20:01:01 +0200 Subject: MX51evk: Removed warnings Changes reflect modifications in the fsl_esdhc driver (the clk_enable field war removed in the configuration structure). Signed-off-by: Stefano Babic --- board/freescale/mx51evk/mx51evk.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index f0b7abcf529..3d89be39f28 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -39,8 +39,8 @@ struct io_board_ctrl *mx51_io_board; #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC1_BASE_ADDR, 1, 1}, - {MMC_SDHC2_BASE_ADDR, 1, 1}, + {MMC_SDHC1_BASE_ADDR, 1}, + {MMC_SDHC2_BASE_ADDR, 1}, }; #endif -- cgit v1.3.1 From e98ecd71102de9d97bd82be247ed909260fb671b Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 16 Apr 2010 17:13:54 +0200 Subject: MX31: Add support for PMIC to the QONG module Add support for the PMIC (MC13783) controller and enables charging of the RTC battery. Signed-off-by: Stefano Babic --- board/davedenx/qong/qong.c | 20 ++++++++++++++++++++ include/configs/qong.h | 14 ++++++++++++++ 2 files changed, 34 insertions(+) (limited to 'board') diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index eb9218ec505..781333b8ceb 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "qong_fpga.h" DECLARE_GLOBAL_DATA_PTR; @@ -128,6 +129,13 @@ int board_init (void) mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); + /* setup pins for SPI (pmic) */ + mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); + mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); + mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); + mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); + mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); + /* board id for linux */ gd->bd->bi_arch_number = MACH_TYPE_QONG; gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ @@ -135,6 +143,18 @@ int board_init (void) return 0; } +int board_late_init(void) +{ + u32 val; + + /* Enable RTC battery */ + val = pmic_reg_read(REG_POWER_CTL0); + pmic_reg_write(REG_POWER_CTL0, val | COINCHEN); + pmic_reg_write(REG_INT_STATUS1, RTCRSTI); + + return 0; +} + int checkboard (void) { printf("Board: DAVE/DENX Qong\n"); diff --git a/include/configs/qong.h b/include/configs/qong.h index 1d63b33b9bd..eb4669ba716 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -54,6 +54,17 @@ #define CONFIG_MX31_GPIO +#define CONFIG_MXC_SPI +#define CONFIG_DEFAULT_SPI_BUS 1 +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_RTC_MC13783 + +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 1 +#define CONFIG_FSL_PMIC_CS 0 +#define CONFIG_FSL_PMIC_CLK 100000 +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) + /* FPGA */ #define CONFIG_QONG_FPGA 1 #define CONFIG_FPGA_BASE (CS1_BASE) @@ -98,6 +109,9 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_MII #define CONFIG_CMD_NAND +#define CONFIG_CMD_SPI +#define CONFIG_CMD_DATE +#define BOARD_LATE_INIT /* * You can compile in a MAC address and your custom net settings by using -- cgit v1.3.1 From b4377e12e9aa0b3bf2dcae0a0f02ec9086338506 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 16 Mar 2010 17:22:21 +0100 Subject: Add SPI support to mx51evk board The patch adds SPI devices to the mx51evk board. The MC13892 chip (PMIC) is supported. Signed-off-by: Stefano Babic --- board/freescale/mx51evk/mx51evk.c | 139 ++++++++++++++++++++++++++++++++++++++ include/configs/mx51evk.h | 15 ++++ 2 files changed, 154 insertions(+) (limited to 'board') diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 3d89be39f28..75d642bf423 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -27,9 +27,12 @@ #include #include #include +#include #include #include #include +#include +#include #include "mx51evk.h" DECLARE_GLOBAL_DATA_PTR; @@ -147,6 +150,130 @@ static void setup_iomux_fec(void) mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180); } +#ifdef CONFIG_MXC_SPI +static void setup_iomux_spi(void) +{ + /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */ + mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105); + + /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105); + + /* de-select SS1 of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85); + + /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */ + mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185); + + /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180); + + /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105); +} +#endif + +static void power_init(void) +{ + unsigned int val; + unsigned int reg; + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; + + /* Write needed to Power Gate 2 register */ + val = pmic_reg_read(REG_POWER_MISC); + val &= ~PWGT2SPIEN; + pmic_reg_write(REG_POWER_MISC, val); + + /* Write needed to update Charger 0 */ + pmic_reg_write(REG_CHARGE, VCHRG0 | VCHRG1 | VCHRG2 | + ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | ICHRGTR0 | + OVCTRL1 | UCHEN | CHRGLEDEN | CYCLB); + + /* power up the system first */ + pmic_reg_write(REG_POWER_MISC, PWUP); + + /* Set core voltage to 1.1V */ + val = pmic_reg_read(REG_SW_0); + val = (val & (~0x1F)) | 0x14; + pmic_reg_write(REG_SW_0, val); + + /* Setup VCC (SW2) to 1.25 */ + val = pmic_reg_read(REG_SW_1); + val = (val & (~0x1F)) | 0x1A; + pmic_reg_write(REG_SW_1, val); + + /* Setup 1V2_DIG1 (SW3) to 1.25 */ + val = pmic_reg_read(REG_SW_2); + val = (val & (~0x1F)) | 0x1A; + pmic_reg_write(REG_SW_2, val); + udelay(50); + + /* Raise the core frequency to 800MHz */ + writel(0x0, &mxc_ccm->cacrr); + + /* Set switchers in Auto in NORMAL mode & STANDBY mode */ + /* Setup the switcher mode for SW1 & SW2*/ + val = pmic_reg_read(REG_SW_4); + val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | + (SWMODE_MASK << SWMODE2_SHIFT))); + val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | + (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); + pmic_reg_write(REG_SW_4, val); + + /* Setup the switcher mode for SW3 & SW4 */ + val = pmic_reg_read(REG_SW_5); + val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) | + (SWMODE_MASK << SWMODE4_SHIFT))); + val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) | + (SWMODE_AUTO_AUTO << SWMODE4_SHIFT); + pmic_reg_write(REG_SW_5, val); + + /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */ + val = pmic_reg_read(REG_SETTING_0); + val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); + val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6; + pmic_reg_write(REG_SETTING_0, val); + + /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ + val = pmic_reg_read(REG_SETTING_1); + val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); + val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775; + pmic_reg_write(REG_SETTING_1, val); + + /* Configure VGEN3 and VCAM regulators to use external PNP */ + val = VGEN3CONFIG | VCAMCONFIG; + pmic_reg_write(REG_MODE_1, val); + udelay(200); + + reg = readl(GPIO2_BASE_ADDR + 0x0); + reg &= ~0x4000; /* Lower reset line */ + writel(reg, GPIO2_BASE_ADDR + 0x0); + + reg = readl(GPIO2_BASE_ADDR + 0x4); + reg |= 0x4000; /* configure GPIO lines as output */ + writel(reg, GPIO2_BASE_ADDR + 0x4); + + /* Reset the ethernet controller over GPIO */ + writel(0x1, IOMUXC_BASE_ADDR + 0x0AC); + + /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ + val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | + VVIDEOEN | VAUDIOEN | VSDEN; + pmic_reg_write(REG_MODE_1, val); + + udelay(500); + + reg = readl(GPIO2_BASE_ADDR + 0x0); + reg |= 0x4000; + writel(reg, GPIO2_BASE_ADDR + 0x0); +} + #ifdef CONFIG_FSL_ESDHC int board_mmc_getcd(u8 *cd, struct mmc *mmc) { @@ -284,9 +411,21 @@ int board_init(void) setup_iomux_uart(); setup_iomux_fec(); + return 0; } +#ifdef BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_MXC_SPI + setup_iomux_spi(); + power_init(); +#endif + return 0; +} +#endif + int checkboard(void) { puts("Board: MX51EVK "); diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 3626df73df7..86a4731a691 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -54,12 +54,27 @@ /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_SIZE 128 +#define BOARD_LATE_INIT + /* * Hardware drivers */ #define CONFIG_MXC_UART #define CONFIG_SYS_MX51_UART1 +/* + * SPI Configs + * */ +#define CONFIG_CMD_SPI + +#define CONFIG_MXC_SPI + +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 0 +#define CONFIG_FSL_PMIC_CS 0 +#define CONFIG_FSL_PMIC_CLK 2500000 +#define CONFIG_FSL_PMIC_MODE (SPI_CPOL | SPI_CS_HIGH) + /* * MMC Configs * */ -- cgit v1.3.1 From 64a0a4995e79ef9813bb51d5f1ff35ae5dabfc7e Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:37 +1000 Subject: x86: Fix MMCR Access Change sc520 MMCR Access to use memory accessor functions Signed-off-by: Graeme Russ --- arch/i386/cpu/sc520/sc520.c | 33 ++++++++------- arch/i386/cpu/sc520/sc520_pci.c | 24 +++++++---- arch/i386/cpu/sc520/sc520_ssi.c | 27 ++++++------ arch/i386/cpu/sc520/sc520_timer.c | 31 +++++++------- board/eNET/eNET.c | 86 +++++++++++++++++++-------------------- 5 files changed, 106 insertions(+), 95 deletions(-) (limited to 'board') diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c index 4b566a75ccd..519bfd8b0c2 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/i386/cpu/sc520/sc520.c @@ -44,24 +44,24 @@ void init_sc520(void) /* Set the UARTxCTL register at it's slower, * baud clock giving us a 1.8432 MHz reference */ - sc520_mmcr->uart1ctl = 0x07; - sc520_mmcr->uart2ctl = 0x07; + writeb(0x07, &sc520_mmcr->uart1ctl); + writeb(0x07, &sc520_mmcr->uart2ctl); /* first set the timer pin mapping */ - sc520_mmcr->clksel = 0x72; /* no clock frequency selected, use 1.1892MHz */ + writeb(0x72, &sc520_mmcr->clksel); /* no clock frequency selected, use 1.1892MHz */ /* enable PCI bus arbitrer */ - sc520_mmcr->sysarbctl = 0x02; /* enable concurrent mode */ + writeb(0x02, &sc520_mmcr->sysarbctl); /* enable concurrent mode */ - sc520_mmcr->sysarbmenb = 0x1f; /* enable external grants */ - sc520_mmcr->hbctl = 0x04; /* enable posted-writes */ + writeb(0x1f, &sc520_mmcr->sysarbmenb); /* enable external grants */ + writeb(0x04, &sc520_mmcr->hbctl); /* enable posted-writes */ if (CONFIG_SYS_SC520_HIGH_SPEED) { - sc520_mmcr->cpuctl = 0x02; /* set it to 133 MHz and write back */ + writeb(0x02, &sc520_mmcr->cpuctl); /* set it to 133 MHz and write back */ gd->cpu_clk = 133000000; printf("## CPU Speed set to 133MHz\n"); } else { - sc520_mmcr->cpuctl = 0x01; /* set it to 100 MHz and write back */ + writeb(0x01, &sc520_mmcr->cpuctl); /* set it to 100 MHz and write back */ printf("## CPU Speed set to 100MHz\n"); gd->cpu_clk = 100000000; } @@ -74,7 +74,7 @@ void init_sc520(void) "loop 0b\n": : : "ecx"); /* turn on the SDRAM write buffer */ - sc520_mmcr->dbctl = 0x11; + writeb(0x11, &sc520_mmcr->dbctl); /* turn on the cache and disable write through */ asm("movl %%cr0, %%eax\n" @@ -88,6 +88,7 @@ unsigned long init_sc520_dram(void) u32 dram_present=0; u32 dram_ctrl; + #ifdef CONFIG_SYS_SDRAM_DRCTMCTL /* these memory control registers are set up in the assember part, * in sc520_asm.S, during 'mem_init'. If we muck with them here, @@ -97,7 +98,8 @@ unsigned long init_sc520_dram(void) * simply dictates it. */ #else - int val; + u8 tmp; + u8 val; int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY; int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE; @@ -116,9 +118,10 @@ unsigned long init_sc520_dram(void) val = 3; /* 62.4us */ } - sc520_mmcr->drcctl = (sc520_mmcr->drcctl & 0xcf) | (val<<4); + tmp = (readb(&sc520_mmcr->drcctl) & 0xcf) | (val<<4); + writeb(tmp, &sc520_mmcr->drcctl); - val = sc520_mmcr->drctmctl & 0xf0; + val = readb(&sc520_mmcr->drctmctl) & 0xf0; if (cas_precharge_delay==3) { val |= 0x04; /* 3T */ @@ -133,12 +136,12 @@ unsigned long init_sc520_dram(void) } else { val |= 1; } - sc520_mmcr->drctmctl = val; + writeb(val, &c520_mmcr->drctmctl); #endif /* We read-back the configuration of the dram * controller that the assembly code wrote */ - dram_ctrl = sc520_mmcr->drcbendadr; + dram_ctrl = readl(&sc520_mmcr->drcbendadr); bd->bi_dram[0].start = 0; if (dram_ctrl & 0x80) { @@ -191,7 +194,7 @@ void reset_cpu(ulong addr) { printf("Resetting using SC520 MMCR\n"); /* Write a '1' to the SYS_RST of the RESCFG MMCR */ - sc520_mmcr->rescfg = 0x01; + writeb(0x01, &sc520_mmcr->rescfg); /* NOTREACHED */ } diff --git a/arch/i386/cpu/sc520/sc520_pci.c b/arch/i386/cpu/sc520/sc520_pci.c index f446c6d5927..ee7e720188d 100644 --- a/arch/i386/cpu/sc520/sc520_pci.c +++ b/arch/i386/cpu/sc520/sc520_pci.c @@ -25,6 +25,7 @@ #include #include +#include #include #include @@ -63,6 +64,8 @@ int sc520_pci_ints[15] = { int pci_sc520_set_irq(int pci_pin, int irq) { int i; + u8 tmpb; + u16 tmpw; # if 1 printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq); @@ -80,31 +83,34 @@ int pci_sc520_set_irq(int pci_pin, int irq) /* PCI interrupt mapping (A through D)*/ for (i=0; i<=3 ;i++) { - if (sc520_mmcr->pci_int_map[i] == sc520_irq[irq].priority) - sc520_mmcr->pci_int_map[i] = SC520_IRQ_DISABLED; + if (readb(&sc520_mmcr->pci_int_map[i]) == sc520_irq[irq].priority) + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]); } /* GP IRQ interrupt mapping */ for (i=0; i<=10 ;i++) { - if (sc520_mmcr->gp_int_map[i] == sc520_irq[irq].priority) - sc520_mmcr->gp_int_map[i] = SC520_IRQ_DISABLED; + if (readb(&sc520_mmcr->gp_int_map[i]) == sc520_irq[irq].priority) + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]); } /* Set the trigger to level */ - sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] = - sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] | sc520_irq[irq].level_bit; + tmpb = readb(&sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]); + tmpb |= sc520_irq[irq].level_bit; + writeb(tmpb, &sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]); if (pci_pin < 4) { /* PCI INTA-INTD */ /* route the interrupt */ - sc520_mmcr->pci_int_map[pci_pin] = sc520_irq[irq].priority; + writeb(sc520_irq[irq].priority, &sc520_mmcr->pci_int_map[pci_pin]); } else { /* GPIRQ0-GPIRQ10 used for additional PCI INTS */ - sc520_mmcr->gp_int_map[pci_pin - 4] = sc520_irq[irq].priority; + writeb(sc520_irq[irq].priority, &sc520_mmcr->gp_int_map[pci_pin - 4]); /* also set the polarity in this case */ - sc520_mmcr->intpinpol = sc520_mmcr->intpinpol | (1 << (pci_pin-4)); + tmpw = readw(&sc520_mmcr->intpinpol); + tmpw |= (1 << (pci_pin-4)); + writew(tmpw, &sc520_mmcr->intpinpol); } /* register the pin */ diff --git a/arch/i386/cpu/sc520/sc520_ssi.c b/arch/i386/cpu/sc520/sc520_ssi.c index 8dbe17aa60e..6e5e3463033 100644 --- a/arch/i386/cpu/sc520/sc520_ssi.c +++ b/arch/i386/cpu/sc520/sc520_ssi.c @@ -24,6 +24,7 @@ /* stuff specific for the sc520, but independent of implementation */ #include +#include #include #include @@ -61,34 +62,34 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase) temp |= PHS_INV_ENB; } - sc520_mmcr->ssictl = temp; + writeb(temp, &sc520_mmcr->ssictl); return 0; } u8 ssi_txrx_byte(u8 data) { - sc520_mmcr->ssixmit = data; - while (sc520_mmcr->ssista & SSISTA_BSY); - sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMITRCV; - while (sc520_mmcr->ssista & SSISTA_BSY); + writeb(data, &sc520_mmcr->ssixmit); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); - return sc520_mmcr->ssircv; + return readb(&sc520_mmcr->ssircv); } void ssi_tx_byte(u8 data) { - sc520_mmcr->ssixmit = data; - while (sc520_mmcr->ssista & SSISTA_BSY); - sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMIT; + writeb(data, &sc520_mmcr->ssixmit); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd); } u8 ssi_rx_byte(void) { - while (sc520_mmcr->ssista & SSISTA_BSY); - sc520_mmcr->ssicmd = SSICMD_CMD_SEL_RCV; - while (sc520_mmcr->ssista & SSISTA_BSY); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); - return sc520_mmcr->ssircv; + return readb(&sc520_mmcr->ssircv); } diff --git a/arch/i386/cpu/sc520/sc520_timer.c b/arch/i386/cpu/sc520/sc520_timer.c index 93b5b555c30..eca48e0c127 100644 --- a/arch/i386/cpu/sc520/sc520_timer.c +++ b/arch/i386/cpu/sc520/sc520_timer.c @@ -24,13 +24,14 @@ /* stuff specific for the sc520, but independent of implementation */ #include +#include #include #include void sc520_timer_isr(void) { /* Ack the GP Timer Interrupt */ - sc520_mmcr->gptmrsta = 0x02; + writeb(0x02, &sc520_mmcr->gptmrsta); } int timer_init(void) @@ -42,28 +43,28 @@ int timer_init(void) irq_install_handler (0, timer_isr, NULL); /* Map GP Timer 1 to Master PIC IR0 */ - sc520_mmcr->gp_tmr_int_map[1] = 0x01; + writeb(0x01, &sc520_mmcr->gp_tmr_int_map[1]); /* Disable GP Timers 1 & 2 - Allow configuration writes */ - sc520_mmcr->gptmr1ctl = 0x4000; - sc520_mmcr->gptmr2ctl = 0x4000; + writew(0x4000, &sc520_mmcr->gptmr1ctl); + writew(0x4000, &sc520_mmcr->gptmr2ctl); /* Reset GP Timers 1 & 2 */ - sc520_mmcr->gptmr1cnt = 0x0000; - sc520_mmcr->gptmr2cnt = 0x0000; + writew(0x0000, &sc520_mmcr->gptmr1cnt); + writew(0x0000, &sc520_mmcr->gptmr2cnt); /* Setup GP Timer 2 as a 100kHz (10us) prescaler */ - sc520_mmcr->gptmr2maxcmpa = 83; - sc520_mmcr->gptmr2ctl = 0xc001; + writew(83, &sc520_mmcr->gptmr2maxcmpa); + writew(0xc001, &sc520_mmcr->gptmr2ctl); /* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */ - sc520_mmcr->gptmr1maxcmpa = 100; - sc520_mmcr->gptmr1ctl = 0xe009; + writew(100, &sc520_mmcr->gptmr1maxcmpa); + writew(0xe009, &sc520_mmcr->gptmr1ctl); unmask_irq (0); /* Clear the GP Timer 1 status register to get the show rolling*/ - sc520_mmcr->gptmrsta = 0x02; + writeb(0x02, &sc520_mmcr->gptmrsta); return 0; } @@ -74,11 +75,11 @@ void __udelay(unsigned long usec) long u; long temp; - temp = sc520_mmcr->swtmrmilli; - temp = sc520_mmcr->swtmrmicro; + temp = readw(&sc520_mmcr->swtmrmilli); + temp = readw(&sc520_mmcr->swtmrmicro); do { - m += sc520_mmcr->swtmrmilli; - u = sc520_mmcr->swtmrmicro + (m * 1000); + m += readw(&sc520_mmcr->swtmrmilli); + u = readw(&sc520_mmcr->swtmrmicro) + (m * 1000); } while (u < usec); } diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 6d0b15a0fa2..f794bebc25a 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -46,7 +46,7 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; void init_sc520_enet (void) { /* Set CPU Speed to 100MHz */ - sc520_mmcr->cpuctl = 0x01; + writeb(0x01, &sc520_mmcr->cpuctl); /* wait at least one millisecond */ asm("movl $0x2000,%%ecx\n" @@ -55,7 +55,7 @@ void init_sc520_enet (void) "loop 0b\n": : : "ecx"); /* turn on the SDRAM write buffer */ - sc520_mmcr->dbctl = 0x11; + writeb(0x11, &sc520_mmcr->dbctl); /* turn on the cache and disable write through */ asm("movl %%cr0, %%eax\n" @@ -70,51 +70,51 @@ int board_early_init_f(void) { init_sc520_enet(); - sc520_mmcr->gpcsrt = 0x01; /* GP Chip Select Recovery Time */ - sc520_mmcr->gpcspw = 0x07; /* GP Chip Select Pulse Width */ - sc520_mmcr->gpcsoff = 0x00; /* GP Chip Select Offset */ - sc520_mmcr->gprdw = 0x05; /* GP Read pulse width */ - sc520_mmcr->gprdoff = 0x01; /* GP Read offset */ - sc520_mmcr->gpwrw = 0x05; /* GP Write pulse width */ - sc520_mmcr->gpwroff = 0x01; /* GP Write offset */ - - sc520_mmcr->piodata15_0 = 0x0630; /* PIO15_PIO0 Data */ - sc520_mmcr->piodata31_16 = 0x2000; /* PIO31_PIO16 Data */ - sc520_mmcr->piodir31_16 = 0x2000; /* GPIO Direction */ - sc520_mmcr->piodir15_0 = 0x87b5; /* GPIO Direction */ - sc520_mmcr->piopfs31_16 = 0x0dfe; /* GPIO pin function 31-16 reg */ - sc520_mmcr->piopfs15_0 = 0x200a; /* GPIO pin function 15-0 reg */ - sc520_mmcr->cspfs = 0x00f8; /* Chip Select Pin Function Select */ - - sc520_mmcr->par[2] = 0x200713f8; /* Uart A (GPCS0, 0x013f8, 8 Bytes) */ - sc520_mmcr->par[3] = 0x2c0712f8; /* Uart B (GPCS3, 0x012f8, 8 Bytes) */ - sc520_mmcr->par[4] = 0x300711f8; /* Uart C (GPCS4, 0x011f8, 8 Bytes) */ - sc520_mmcr->par[5] = 0x340710f8; /* Uart D (GPCS5, 0x010f8, 8 Bytes) */ - sc520_mmcr->par[6] = 0xe3ffc000; /* SDRAM (0x00000000, 128MB) */ - sc520_mmcr->par[7] = 0xaa3fd000; /* StrataFlash (ROMCS1, 0x10000000, 16MB) */ - sc520_mmcr->par[8] = 0xca3fd100; /* StrataFlash (ROMCS2, 0x11000000, 16MB) */ - sc520_mmcr->par[9] = 0x4203d900; /* SRAM (GPCS0, 0x19000000, 1MB) */ - sc520_mmcr->par[10] = 0x4e03d910; /* SRAM (GPCS3, 0x19100000, 1MB) */ - sc520_mmcr->par[11] = 0x50018100; /* DP-RAM (GPCS4, 0x18100000, 4kB) */ - sc520_mmcr->par[12] = 0x54020000; /* CFLASH1 (0x200000000, 4kB) */ - sc520_mmcr->par[13] = 0x5c020001; /* CFLASH2 (0x200010000, 4kB) */ -/* sc520_mmcr->par14 = 0x8bfff800; */ /* BOOTCS at 0x18000000 */ -/* sc520_mmcr->par15 = 0x38201000; */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */ + writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select Recovery Time */ + writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse Width */ + writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select Offset */ + writeb(0x05, &sc520_mmcr->gprdw); /* GP Read pulse width */ + writeb(0x01, &sc520_mmcr->gprdoff); /* GP Read offset */ + writeb(0x05, &sc520_mmcr->gpwrw); /* GP Write pulse width */ + writeb(0x01, &sc520_mmcr->gpwroff); /* GP Write offset */ + + writew(0x0630, &sc520_mmcr->piodata15_0); /* PIO15_PIO0 Data */ + writew(0x2000, &sc520_mmcr->piodata31_16); /* PIO31_PIO16 Data */ + writew(0x2000, &sc520_mmcr->piodir31_16); /* GPIO Direction */ + writew(0x87b5, &sc520_mmcr->piodir15_0); /* GPIO Direction */ + writew(0x0dfe, &sc520_mmcr->piopfs31_16); /* GPIO pin function 31-16 reg */ + writew(0x200a, &sc520_mmcr->piopfs15_0); /* GPIO pin function 15-0 reg */ + writeb(0xf8, &sc520_mmcr->cspfs); /* Chip Select Pin Function Select */ + + writel(0x200713f8, &sc520_mmcr->par[2]); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */ + writel(0x2c0712f8, &sc520_mmcr->par[3]); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */ + writel(0x300711f8, &sc520_mmcr->par[4]); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */ + writel(0x340710f8, &sc520_mmcr->par[5]); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */ + writel(0xe3ffc000, &sc520_mmcr->par[6]); /* SDRAM (0x00000000, 128MB) */ + writel(0xaa3fd000, &sc520_mmcr->par[7]); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */ + writel(0xca3fd100, &sc520_mmcr->par[8]); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */ + writel(0x4203d900, &sc520_mmcr->par[9]); /* SRAM (GPCS0, 0x19000000, 1MB) */ + writel(0x4e03d910, &sc520_mmcr->par[10]); /* SRAM (GPCS3, 0x19100000, 1MB) */ + writel(0x50018100, &sc520_mmcr->par[11]); /* DP-RAM (GPCS4, 0x18100000, 4kB) */ + writel(0x54020000, &sc520_mmcr->par[12]); /* CFLASH1 (0x200000000, 4kB) */ + writel(0x5c020001, &sc520_mmcr->par[13]); /* CFLASH2 (0x200010000, 4kB) */ +/* writel(0x8bfff800, &sc520_mmcr->par14); */ /* BOOTCS at 0x18000000 */ +/* writel(0x38201000, &sc520_mmcr->par15); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */ /* Disable Watchdog */ - sc520_mmcr->wdtmrctl = 0x3333; - sc520_mmcr->wdtmrctl = 0xcccc; - sc520_mmcr->wdtmrctl = 0x0000; + writew(0x3333, &sc520_mmcr->wdtmrctl); + writew(0xcccc, &sc520_mmcr->wdtmrctl); + writew(0x0000, &sc520_mmcr->wdtmrctl); /* Chip Select Configuration */ - sc520_mmcr->bootcsctl = 0x0033; - sc520_mmcr->romcs1ctl = 0x0615; - sc520_mmcr->romcs2ctl = 0x0615; - - sc520_mmcr->adddecctl = 0x02; - sc520_mmcr->uart1ctl = 0x07; - sc520_mmcr->sysarbctl = 0x06; - sc520_mmcr->sysarbmenb = 0x0003; + writew(0x0033, &sc520_mmcr->bootcsctl); + writew(0x0615, &sc520_mmcr->romcs1ctl); + writew(0x0615, &sc520_mmcr->romcs2ctl); + + writeb(0x02, &sc520_mmcr->adddecctl); + writeb(0x07, &sc520_mmcr->uart1ctl); + writeb(0x06, &sc520_mmcr->sysarbctl); + writew(0x0003, &sc520_mmcr->sysarbmenb); return 0; } -- cgit v1.3.1 From 077e1958ca4afe12d88043b123ded058c51b89f7 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:42 +1000 Subject: x86: Add RAM bootstrap functionality Add a parameter to the 32-bit entry to indicate if entry is from Real Mode or not. If entry is from Real Mode, execute the destructive 'sizer' routine to determine memory size as we are booting cold and running in Flash. If not entering from Real Mode, we are executing a U-Boot image from RAM and therefore the memory size is already known (and running 'sizer' will destroy the running image) There are now two 32-bit entry points. The first is the 'in RAM' entry point which exists at the start of the U-Boot binary image. As such, you can load u-boot.bin in RAM and jump directly to the load address without needing to calculate any offsets. The second entry point is used by the real-to-protected mode switch This patch also changes TEXT_BASE to 0x6000000 (in RAM). You can load the resulting image at 0x6000000 and simple go 0x6000000 from the u-boot prompt Hopefully a later patch will completely elliminate any dependency on TEXT_BASE like a relocatable linux kernel (perfect world) Signed-off-by: Graeme Russ --- arch/i386/cpu/start.S | 36 ++++++++++++++++++++++++++++++++++++ arch/i386/cpu/start16.S | 8 ++------ board/eNET/config.mk | 2 +- board/eNET/u-boot.lds | 9 ++++----- 4 files changed, 43 insertions(+), 12 deletions(-) (limited to 'board') diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index 1980f1a7b78..3cea04b4ce3 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -33,7 +33,27 @@ .type _start, @function .globl _i386boot_start _i386boot_start: + /* + * This is the fail safe 32-bit bootstrap entry point. The + * following code is not executed from a cold-reset (actually, a + * lot of it is, but from real-mode after cold reset. It is + * repeated here to put the board into a state as close to cold + * reset as necessary) + */ + cli + cld + + /* Turn of cache (this might require a 486-class CPU) */ + movl %cr0, %eax + orl $0x60000000,%eax + movl %eax, %cr0 + wbinvd + + /* Tell 32-bit code it is being entered from an in-RAM copy */ + movw $0x0000, %bx _start: + /* This is the 32-bit cold-reset entry point */ + movl $0x18,%eax /* Load our segement registes, the * gdt have already been loaded by start16.S */ movw %ax,%fs @@ -42,6 +62,18 @@ _start: movw %ax,%es movw %ax,%ss + /* Clear the interupt vectors */ + lidt blank_idt_ptr + + /* + * Skip low-level board and memory initialization if not starting + * from cold-reset. This allows us to do a fail safe boot-strap + * into a new build of U-Boot from a known-good boot flash + */ + movw $0x0001, %ax + cmpw %ax, %bx + jne mem_init_ret + /* We call a few functions in the board support package * since we have no stack yet we'll have to use %ebp * to store the return address */ @@ -138,3 +170,7 @@ stack_ok: die: hlt jmp die hlt + +blank_idt_ptr: + .word 0 /* limit */ + .long 0 /* base */ diff --git a/arch/i386/cpu/start16.S b/arch/i386/cpu/start16.S index 1ebb6bc8b63..5e33aa1069c 100644 --- a/arch/i386/cpu/start16.S +++ b/arch/i386/cpu/start16.S @@ -45,10 +45,8 @@ board_init16_ret: wbinvd /* load the descriptor tables */ -o32 cs lidt idt_ptr o32 cs lgdt gdt_ptr - /* Now, we enter protected mode */ movl %cr0, %eax orl $1,%eax @@ -57,6 +55,8 @@ o32 cs lgdt gdt_ptr /* Flush the prefetch queue */ jmp ff ff: + /* Tell 32-bit code it is being entered from hard-reset */ + movw $0x0001, %bx /* Finally jump to the 32bit initialization code */ movw $code32start, %ax @@ -68,10 +68,6 @@ code32start: .long _start /* offset */ .word 0x10 /* segment */ -idt_ptr: - .word 0 /* limit */ - .long 0 /* base */ - gdt_ptr: .word 0x30 /* limit (48 bytes = 6 GDT entries) */ .long BOOT_SEG + gdt /* base */ diff --git a/board/eNET/config.mk b/board/eNET/config.mk index dcde7fcedb2..63a58fdc501 100644 --- a/board/eNET/config.mk +++ b/board/eNET/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -TEXT_BASE = 0x38040000 +TEXT_BASE = 0x06000000 CFLAGS_common/dlmalloc.o += -Wa,--no-warn -fno-strict-aliasing PLATFORM_RELFLAGS += -fvisibility=hidden PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds index 0d740215ce9..7b0ffaa6cc8 100644 --- a/board/eNET/u-boot.lds +++ b/board/eNET/u-boot.lds @@ -27,7 +27,7 @@ ENTRY(_start) SECTIONS { - . = 0x38040000; /* Location of bootcode in flash */ + . = 0x06000000; /* Location of bootcode in flash */ _i386boot_text_start = .; .text : { *(.text); } @@ -97,14 +97,13 @@ SECTIONS * at reset and the code have to fit. * The fff0 offset of resetvec is important, however. */ - . = 0xfffffe00; - .start32 : AT (0x3807fe00) { *(.start32); } + .start32 : AT (0x0603fe00) { *(.start32); } . = 0xf800; - .start16 : AT (0x3807f800) { *(.start16); } + .start16 : AT (0x0603f800) { *(.start16); } . = 0xfff0; - .resetvec : AT (0x3807fff0) { *(.resetvec); } + .resetvec : AT (0x0603fff0) { *(.resetvec); } _i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) ); } -- cgit v1.3.1 From bf16500f79fdf2653a286b40bb601cb185ac4675 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:47 +1000 Subject: x86: Use CONFIG_SERIAL_MULTI Signed-off-by: Graeme Russ --- arch/i386/cpu/Makefile | 2 +- arch/i386/cpu/serial.c | 506 ------------------------------------------------- arch/i386/lib/board.c | 5 +- board/eNET/eNET.c | 3 +- common/serial.c | 3 +- include/configs/eNET.h | 26 ++- include/serial.h | 3 +- 7 files changed, 32 insertions(+), 516 deletions(-) delete mode 100644 arch/i386/cpu/serial.c (limited to 'board') diff --git a/arch/i386/cpu/Makefile b/arch/i386/cpu/Makefile index c658c6e4591..bb0a48f8643 100644 --- a/arch/i386/cpu/Makefile +++ b/arch/i386/cpu/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o start16.o resetvec.o -COBJS = serial.o interrupts.o cpu.o +COBJS = interrupts.o cpu.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/i386/cpu/serial.c b/arch/i386/cpu/serial.c deleted file mode 100644 index e7025a3cdc0..00000000000 --- a/arch/i386/cpu/serial.c +++ /dev/null @@ -1,506 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/*------------------------------------------------------------------------------+ */ - -/* - * This source code is dual-licensed. You may use it under the terms of the - * GNU General Public License version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - */ -/*------------------------------------------------------------------------------- */ - -#include -#include -#include -#include - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_RBR 0x00 -#define UART_THR 0x00 -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/*-----------------------------------------------------------------------------+ - | Line Status Register. - +-----------------------------------------------------------------------------*/ -#define asyncLSRDataReady1 0x01 -#define asyncLSROverrunError1 0x02 -#define asyncLSRParityError1 0x04 -#define asyncLSRFramingError1 0x08 -#define asyncLSRBreakInterrupt1 0x10 -#define asyncLSRTxHoldEmpty1 0x20 -#define asyncLSRTxShiftEmpty1 0x40 -#define asyncLSRRxFifoError1 0x80 - - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO -/*-----------------------------------------------------------------------------+ - | Fifo - +-----------------------------------------------------------------------------*/ -typedef struct { - char *rx_buffer; - ulong rx_put; - ulong rx_get; - int cts; -} serial_buffer_t; - -volatile serial_buffer_t buf_info; -static int serial_buffer_active=0; -#endif - - -static int serial_div(int baudrate) -{ - - switch (baudrate) { - case 1200: - return 96; - case 9600: - return 12; - case 19200: - return 6; - case 38400: - return 3; - case 57600: - return 2; - case 115200: - return 1; - } - - return 12; -} - - -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -int serial_init(void) -{ - volatile char val; - int bdiv = serial_div(gd->baudrate); - - outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */ - outb(bdiv, UART0_BASE + UART_DLL); /* set baudrate divisor */ - outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */ - outb(0x03, UART0_BASE + UART_LCR); /* clear DLAB; set 8 bits, no parity */ - outb(0x01, UART0_BASE + UART_FCR); /* enable FIFO */ - outb(0x0b, UART0_BASE + UART_MCR); /* Set DTR and RTS active */ - val = inb(UART0_BASE + UART_LSR); /* clear line status */ - val = inb(UART0_BASE + UART_RBR); /* read receive buffer */ - outb(0x00, UART0_BASE + UART_SCR); /* set scratchpad */ - outb(0x00, UART0_BASE + UART_IER); /* set interrupt enable reg */ - - return 0; -} - - -void serial_setbrg(void) -{ - unsigned short bdiv; - - bdiv = serial_div(gd->baudrate); - - outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */ - outb(bdiv&0xff, UART0_BASE + UART_DLL); /* set baudrate divisor */ - outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */ - outb(0x03, UART0_BASE + UART_LCR); /* clear DLAB; set 8 bits, no parity */ -} - - -void serial_putc(const char c) -{ - int i; - - if (c == '\n') - serial_putc ('\r'); - - /* check THRE bit, wait for transmiter available */ - for (i = 1; i < 3500; i++) { - if ((inb (UART0_BASE + UART_LSR) & 0x20) == 0x20) { - break; - } - udelay(100); - } - outb(c, UART0_BASE + UART_THR); /* put character out */ -} - - -void serial_puts(const char *s) -{ - while (*s) { - serial_putc(*s++); - } -} - - -int serial_getc(void) -{ - unsigned char status = 0; - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - if (serial_buffer_active) { - return serial_buffered_getc(); - } -#endif - - while (1) { -#if defined(CONFIG_HW_WATCHDOG) - WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */ -#endif /* CONFIG_HW_WATCHDOG */ - status = inb(UART0_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) { - break; - } - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - outb(asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR); - } - } - return (0x000000ff & (int) inb (UART0_BASE)); -} - - -int serial_tstc(void) -{ - unsigned char status; - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - if (serial_buffer_active) { - return serial_buffered_tstc(); - } -#endif - - status = inb(UART0_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) { - return (1); - } - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - outb(asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR); - } - return 0; -} - - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - -void serial_isr(void *arg) -{ - int space; - int c; - int rx_put = buf_info.rx_put; - - if (buf_info.rx_get <= rx_put) { - space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - buf_info.rx_get); - } else { - space = buf_info.rx_get - rx_put; - } - - while (inb(UART0_BASE + UART_LSR) & 1) { - c = inb(UART0_BASE); - if (space) { - buf_info.rx_buffer[rx_put++] = c; - space--; - - if (rx_put == buf_info.rx_get) { - buf_info.rx_get++; - if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) { - buf_info.rx_get = 0; - } - } - - if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) { - rx_put = 0; - if (0 == buf_info.rx_get) { - buf_info.rx_get = 1; - } - - } - - } - if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) { - /* Stop flow by setting RTS inactive */ - outb(inb(UART0_BASE + UART_MCR) & (0xFF ^ 0x02), - UART0_BASE + UART_MCR); - } - } - buf_info.rx_put = rx_put; -} - -void serial_buffered_init(void) -{ - serial_puts ("Switching to interrupt driven serial input mode.\n"); - buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO); - buf_info.rx_put = 0; - buf_info.rx_get = 0; - - if (inb (UART0_BASE + UART_MSR) & 0x10) { - serial_puts ("Check CTS signal present on serial port: OK.\n"); - buf_info.cts = 1; - } else { - serial_puts ("WARNING: CTS signal not present on serial port.\n"); - buf_info.cts = 0; - } - - irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ , - serial_isr /*interrupt_handler_t *handler */ , - (void *) &buf_info /*void *arg */ ); - - /* Enable "RX Data Available" Interrupt on UART */ - /* outb(inb(UART0_BASE + UART_IER) |0x01, UART0_BASE + UART_IER); */ - outb(0x01, UART0_BASE + UART_IER); - - /* Set DTR and RTS active, enable interrupts */ - outb(inb (UART0_BASE + UART_MCR) | 0x0b, UART0_BASE + UART_MCR); - - /* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */ - outb( /*(1 << 6) |*/ 1, UART0_BASE + UART_FCR); - - serial_buffer_active = 1; -} - -void serial_buffered_putc (const char c) -{ - int i; - /* Wait for CTS */ -#if defined(CONFIG_HW_WATCHDOG) - while (!(inb (UART0_BASE + UART_MSR) & 0x10)) - WATCHDOG_RESET (); -#else - if (buf_info.cts) { - for (i=0;i<1000;i++) { - if ((inb (UART0_BASE + UART_MSR) & 0x10)) { - break; - } - } - if (i!=1000) { - buf_info.cts = 0; - } - } else { - if ((inb (UART0_BASE + UART_MSR) & 0x10)) { - buf_info.cts = 1; - } - } - -#endif - serial_putc (c); -} - -void serial_buffered_puts(const char *s) -{ - serial_puts (s); -} - -int serial_buffered_getc(void) -{ - int space; - int c; - int rx_get = buf_info.rx_get; - int rx_put; - -#if defined(CONFIG_HW_WATCHDOG) - while (rx_get == buf_info.rx_put) - WATCHDOG_RESET (); -#else - while (rx_get == buf_info.rx_put); -#endif - c = buf_info.rx_buffer[rx_get++]; - if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO) { - rx_get = 0; - } - buf_info.rx_get = rx_get; - - rx_put = buf_info.rx_put; - if (rx_get <= rx_put) { - space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); - } else { - space = rx_get - rx_put; - } - if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) { - /* Start flow by setting RTS active */ - outb(inb (UART0_BASE + UART_MCR) | 0x02, UART0_BASE + UART_MCR); - } - - return c; -} - -int serial_buffered_tstc(void) -{ - return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0; -} - -#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ - - -#if defined(CONFIG_CMD_KGDB) -/* - AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port - number 0 or number 1 - - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 : - configuration has been already done - - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 : - configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE -*/ -#if (CONFIG_KGDB_SER_INDEX & 2) -void kgdb_serial_init(void) -{ - volatile char val; - bdiv = serial_div (CONFIG_KGDB_BAUDRATE); - - /* - * Init onboard 16550 UART - */ - outb(0x80, UART1_BASE + UART_LCR); /* set DLAB bit */ - outb((bdiv & 0xff), UART1_BASE + UART_DLL); /* set divisor for 9600 baud */ - outb((bdiv >> 8 ), UART1_BASE + UART_DLM); /* set divisor for 9600 baud */ - outb(0x03, UART1_BASE + UART_LCR); /* line control 8 bits no parity */ - outb(0x00, UART1_BASE + UART_FCR); /* disable FIFO */ - outb(0x00, UART1_BASE + UART_MCR); /* no modem control DTR RTS */ - val = inb(UART1_BASE + UART_LSR); /* clear line status */ - val = inb(UART1_BASE + UART_RBR); /* read receive buffer */ - outb(0x00, UART1_BASE + UART_SCR); /* set scratchpad */ - outb(0x00, UART1_BASE + UART_IER); /* set interrupt enable reg */ -} - - -void putDebugChar(const char c) -{ - if (c == '\n') - serial_putc ('\r'); - - outb(c, UART1_BASE + UART_THR); /* put character out */ - - /* check THRE bit, wait for transfer done */ - while ((inb(UART1_BASE + UART_LSR) & 0x20) != 0x20); -} - - -void putDebugStr(const char *s) -{ - while (*s) { - serial_putc(*s++); - } -} - - -int getDebugChar(void) -{ - unsigned char status = 0; - - while (1) { - status = inb(UART1_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) { - break; - } - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - outb(asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1, UART1_BASE + UART_LSR); - } - } - return (0x000000ff & (int) inb(UART1_BASE)); -} - - -void kgdb_interruptible(int yes) -{ - return; -} - -#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */ - -void kgdb_serial_init(void) -{ - serial_printf ("[on serial] "); -} - -void putDebugChar(int c) -{ - serial_putc (c); -} - -void putDebugStr(const char *str) -{ - serial_puts (str); -} - -int getDebugChar(void) -{ - return serial_getc (); -} - -void kgdb_interruptible(int yes) -{ - return; -} -#endif /* (CONFIG_KGDB_SER_INDEX & 2) */ -#endif diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 947a8ec474c..7115a2f39c3 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include @@ -149,7 +150,6 @@ static void display_flash_config (ulong size) typedef int (init_fnc_t) (void); init_fnc_t *init_sequence[] = { - serial_init, cpu_init_r, /* basic cpu dependent setup */ board_early_init_r, /* basic board dependent setup */ dram_init, /* configure available RAM banks */ @@ -277,6 +277,9 @@ void board_init_r(gd_t *id, ulong dest_addr) } show_boot_progress(0x23); +#ifdef CONFIG_SERIAL_MULTI + serial_initialize(); +#endif /* configure available FLASH banks */ size = flash_init(); display_flash_config(size); diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index f794bebc25a..52ea1407b5a 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -111,8 +111,9 @@ int board_early_init_f(void) writew(0x0615, &sc520_mmcr->romcs1ctl); writew(0x0615, &sc520_mmcr->romcs2ctl); - writeb(0x02, &sc520_mmcr->adddecctl); + writeb(0x00, &sc520_mmcr->adddecctl); writeb(0x07, &sc520_mmcr->uart1ctl); + writeb(0x07, &sc520_mmcr->uart2ctl); writeb(0x06, &sc520_mmcr->sysarbctl); writew(0x0003, &sc520_mmcr->sysarbmenb); diff --git a/common/serial.c b/common/serial.c index 0682faa9d1f..fceabfa1e7e 100644 --- a/common/serial.c +++ b/common/serial.c @@ -41,7 +41,8 @@ struct serial_device *__default_serial_console (void) #elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \ || defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) \ - || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) + || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \ + || defined(CONFIG_SYS_SC520) #if defined(CONFIG_CONS_INDEX) && defined(CONFIG_SYS_NS16550_SERIAL) #if (CONFIG_CONS_INDEX==1) return &eserial1_device; diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 6a68bf4938f..05d7db87b7f 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -21,6 +21,7 @@ * MA 02111-1307 USA */ +#include /* * board/config.h - configuration options, board specific */ @@ -54,6 +55,26 @@ #undef CONFIG_WATCHDOG #undef CONFIG_HW_WATCHDOG + /*----------------------------------------------------------------------- + * Serial Configuration + */ +#define CONFIG_SERIAL_MULTI +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK 1843200 +#define CONFIG_BAUDRATE 9600 +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CONFIG_SYS_NS16550_COM1 UART0_BASE +#define CONFIG_SYS_NS16550_COM2 UART1_BASE +#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE) +#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE) +#define CONFIG_SYS_NS16550_PORT_MAPPED + /*----------------------------------------------------------------------- * Video Configuration */ @@ -65,8 +86,6 @@ */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) -#define CONFIG_BAUDRATE 9600 - /*----------------------------------------------------------------------- * Command line configuration. */ @@ -123,9 +142,6 @@ #define CONFIG_SYS_HZ 1024 /* incrementer freq: 1kHz */ - /* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - /*----------------------------------------------------------------------- * SDRAM Configuration */ diff --git a/include/serial.h b/include/serial.h index 111edbec8fb..6513d8eeef9 100644 --- a/include/serial.h +++ b/include/serial.h @@ -26,7 +26,8 @@ extern struct serial_device * default_serial_console (void); #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) || \ - defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) + defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ + defined(CONFIG_SYS_SC520) extern struct serial_device serial0_device; extern struct serial_device serial1_device; #if defined(CONFIG_SYS_NS16550_SERIAL) -- cgit v1.3.1 From 21e67e796bb1d59a484dce2b4203d61bf1fd5be8 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:54 +1000 Subject: sc520: Board Specific PCI Init Signed-off-by: Graeme Russ --- arch/i386/cpu/sc520/sc520_pci.c | 39 ++------------------------------------- arch/i386/include/asm/ic/pci.h | 1 + board/eNET/eNET_pci.c | 33 +++++++++++++++++++++++++++++++++ 3 files changed, 36 insertions(+), 37 deletions(-) (limited to 'board') diff --git a/arch/i386/cpu/sc520/sc520_pci.c b/arch/i386/cpu/sc520/sc520_pci.c index ee7e720188d..b91773435e9 100644 --- a/arch/i386/cpu/sc520/sc520_pci.c +++ b/arch/i386/cpu/sc520/sc520_pci.c @@ -27,6 +27,7 @@ #include #include #include +#include #include static struct { @@ -124,43 +125,7 @@ void pci_sc520_init(struct pci_controller *hose) { hose->first_busno = 0; hose->last_busno = 0xff; - - /* System memory space */ - pci_set_region(hose->regions + 0, - SC520_PCI_MEMORY_BUS, - SC520_PCI_MEMORY_PHYS, - SC520_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - SC520_PCI_MEM_BUS, - SC520_PCI_MEM_PHYS, - SC520_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* ISA/PCI memory space */ - pci_set_region(hose->regions + 2, - SC520_ISA_MEM_BUS, - SC520_ISA_MEM_PHYS, - SC520_ISA_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region(hose->regions + 3, - SC520_PCI_IO_BUS, - SC520_PCI_IO_PHYS, - SC520_PCI_IO_SIZE, - PCI_REGION_IO); - - /* ISA/PCI I/O space */ - pci_set_region(hose->regions + 4, - SC520_ISA_IO_BUS, - SC520_ISA_IO_PHYS, - SC520_ISA_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 5; + hose->region_count = pci_set_regions(hose); pci_setup_type1(hose, SC520_REG_ADDR, diff --git a/arch/i386/include/asm/ic/pci.h b/arch/i386/include/asm/ic/pci.h index 1a35f3492d1..2e4376b9b03 100644 --- a/arch/i386/include/asm/ic/pci.h +++ b/arch/i386/include/asm/ic/pci.h @@ -73,6 +73,7 @@ extern int sc520_pci_ints[]; void pci_sc520_init(struct pci_controller *hose); +int pci_set_regions(struct pci_controller *hose); int pci_sc520_set_irq(int pci_pin, int irq); #endif diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c index e80a8feb162..fefb1a4fbeb 100644 --- a/board/eNET/eNET_pci.c +++ b/board/eNET/eNET_pci.c @@ -93,3 +93,36 @@ void pci_init_board(void) { pci_sc520_init(&enet_hose); } + +int pci_set_regions(struct pci_controller *hose) +{ + /* System memory space */ + pci_set_region(hose->regions + 0, + SC520_PCI_MEMORY_BUS, + SC520_PCI_MEMORY_PHYS, + SC520_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + /* ISA/PCI memory space */ + pci_set_region(hose->regions + 1, + SC520_ISA_MEM_BUS, + SC520_ISA_MEM_PHYS, + SC520_ISA_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(hose->regions + 2, + SC520_PCI_IO_BUS, + SC520_PCI_IO_PHYS, + SC520_PCI_IO_SIZE, + PCI_REGION_IO); + + /* ISA/PCI I/O space */ + pci_set_region(hose->regions + 3, + SC520_ISA_IO_BUS, + SC520_ISA_IO_PHYS, + SC520_ISA_IO_SIZE, + PCI_REGION_IO); + + return 4; +} -- cgit v1.3.1 From 8fd805632f95e5e834f312a51aa969bf1d99c41b Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:55 +1000 Subject: eNET: Add support for onboard RTL8100B (RTL8139) chips Signed-off-by: Graeme Russ --- board/eNET/eNET.c | 7 +++++++ include/configs/eNET.h | 9 ++++++++- 2 files changed, 15 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 52ea1407b5a..62f99ce94db 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -24,6 +24,8 @@ #include #include #include +#include +#include #ifdef CONFIG_HW_WATCHDOG #include @@ -173,3 +175,8 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) } else return 0; } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 0bfbd085e82..dac3ede68e1 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -105,9 +105,10 @@ #define CONFIG_CMD_LOADS /* loads */ #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ #define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ -#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_CMD_PCI /* PCI support */ +#define CONFIG_CMD_PING /* ICMP echo support */ #define CONFIG_CMD_RUN /* run command in env variable */ #define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ @@ -226,6 +227,12 @@ #define CONFIG_SYS_THIRD_PCI_IRQ 11 #define CONFIG_SYS_FORTH_PCI_IRQ 15 + /* + * Network device (TRL8100B) support + */ +#define CONFIG_NET_MULTI +#define CONFIG_RTL8139 + /*----------------------------------------------------------------------- * Hardware watchdog configuration */ -- cgit v1.3.1 From 4a4c31ae08d4dcabe348013e135de28b01c29bf0 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:56 +1000 Subject: eNET: Add PC/AT compatibility setup function The eNET uses the sc520 software timers rather than the PC/AT clones Set all interrupts and timers up to be PC/AT compatible Signed-off-by: Graeme Russ --- board/eNET/eNET.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'board') diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 62f99ce94db..ad71f7e5dcb 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -180,3 +180,41 @@ int board_eth_init(bd_t *bis) { return pci_eth_init(bis); } + +void setup_pcat_compatibility() +{ + /* disable global interrupt mode */ + writeb(0x40, &sc520_mmcr->picicr); + + /* set all irqs to edge */ + writeb(0x00, &sc520_mmcr->pic_mode[0]); + writeb(0x00, &sc520_mmcr->pic_mode[1]); + writeb(0x00, &sc520_mmcr->pic_mode[2]); + + /* + * active low polarity on PIC interrupt pins, + * active high polarity on all other irq pins + */ + writew(0x0000,&sc520_mmcr->intpinpol); + + /* Set PIT 0 -> IRQ0, RTC -> IRQ8, FP error -> IRQ13 */ + writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]); + writeb(SC520_IRQ8, &sc520_mmcr->rtcmap); + writeb(SC520_IRQ13, &sc520_mmcr->ferrmap); + + /* Disable all other interrupt sources */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[0]); /* disable PCI INT A */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[1]); /* disable PCI INT B */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[2]); /* disable PCI INT C */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[3]); /* disable PCI INT D */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->dmabcintmap); /* disable DMA INT */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap); +} -- cgit v1.3.1 From 880c59e5add3681bd4dca14d2fd20152bee7ad14 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:58 +1000 Subject: eNET: Implement eNET Watchdog Signed-off-by: Graeme Russ --- board/eNET/eNET.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ board/eNET/hardware.h | 1 + include/configs/eNET.h | 10 +--------- 3 files changed, 47 insertions(+), 9 deletions(-) (limited to 'board') diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index ad71f7e5dcb..7f0e2577f1b 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -45,6 +45,9 @@ DECLARE_GLOBAL_DATA_PTR; unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; +static void enet_timer_isr(void); +static void enet_toggle_run_led(void); + void init_sc520_enet (void) { /* Set CPU Speed to 100MHz */ @@ -160,6 +163,10 @@ int last_stage_init(void) major = minor = 0; + outb(0x00, LED_LATCH_ADDRESS); + + register_timer_isr (enet_timer_isr); + printf("Serck Controls eNET\n"); return 0; @@ -218,3 +225,41 @@ void setup_pcat_compatibility() writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap); writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap); } + +void enet_timer_isr(void) +{ + static long enet_ticks = 0; + + enet_ticks++; + + /* Toggle Watchdog every 100ms */ + if ((enet_ticks % 100) == 0) + hw_watchdog_reset(); + + /* Toggle Run LED every 500ms */ + if ((enet_ticks % 500) == 0) + enet_toggle_run_led(); +} + +void hw_watchdog_reset(void) +{ + /* Watchdog Reset must be atomic */ + long flag = disable_interrupts(); + + if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT) + sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT; + else + sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT; + + if (flag) + enable_interrupts(); +} + +void enet_toggle_run_led(void) +{ + unsigned char leds_state= inb(LED_LATCH_ADDRESS); + if (leds_state & LED_RUN_BITMASK) + outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS); + else + outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS); +} diff --git a/board/eNET/hardware.h b/board/eNET/hardware.h index 42474a62fab..dec2cd80406 100644 --- a/board/eNET/hardware.h +++ b/board/eNET/hardware.h @@ -31,5 +31,6 @@ #define LED_RX_BITMASK 0x08 #define LED_TX_BITMASK 0x10 #define LED_ERR_BITMASK 0x20 +#define WATCHDOG_PIO_BIT 0x8000 #endif /* HARDWARE_H_ */ diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 61897949dd9..361fe61b04f 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -53,7 +53,7 @@ * bottom (processor) board MUST be removed! */ #undef CONFIG_WATCHDOG -#undef CONFIG_HW_WATCHDOG +#define CONFIG_HW_WATCHDOG /*----------------------------------------------------------------------- * Serial Configuration @@ -233,14 +233,6 @@ #define CONFIG_NET_MULTI #define CONFIG_RTL8139 -/*----------------------------------------------------------------------- - * Hardware watchdog configuration - */ -#define CONFIG_SYS_WATCHDOG_PIO_BIT 0x8000 -#define CONFIG_SYS_WATCHDIG_PIO_DATA SC520_PIODATA15_0 -#define CONFIG_SYS_WATCHDIG_PIO_CLR SC520_PIOCLR15_0 -#define CONFIG_SYS_WATCHDIG_PIO_SET SC520_PIOSET15_0 - /*----------------------------------------------------------------------- * FPGA configuration */ -- cgit v1.3.1 From 0738e24e2c1d95bb94455d44485dc5d7b9c9d707 Mon Sep 17 00:00:00 2001 From: Reinhard Arlt Date: Tue, 13 Apr 2010 09:59:09 +0200 Subject: 74xx_7xx: CPCI750: Add ECC support on esd CPCI-CPU/750 board Add ECC support for DDR RAM for MV64360 on esd CPCI-CPU/750 board. This patch also adds the "pldver" command to display the CPLD revision. Signed-off-by: Reinhard Arlt Signed-off-by: Stefan Roese --- board/esd/cpci750/cpci750.c | 12 ++++ board/esd/cpci750/sdram_init.c | 151 +++++++++++++++++++++++++++++++++++++++-- include/configs/CPCI750.h | 4 +- 3 files changed, 159 insertions(+), 8 deletions(-) (limited to 'board') diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c index 2ae4cbd6c0b..a199d461827 100644 --- a/board/esd/cpci750/cpci750.c +++ b/board/esd/cpci750/cpci750.c @@ -1090,3 +1090,15 @@ U_BOOT_CMD( "Show Marvell strapping register", "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)" ); + +int do_pldver(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf("PLD version:0x%02x\n", in_8((void *)CONFIG_SYS_PLD_VER)); + + return 0; +} + +U_BOOT_CMD( + pldver, 1, 1, do_pldver, + "Show PLD version", + "Show PLD version)"); diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c index 4c03630fb57..53479580856 100644 --- a/board/esd/cpci750/sdram_init.c +++ b/board/esd/cpci750/sdram_init.c @@ -538,14 +538,14 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) break; /*------------------------------------------------------------------------------------------------------------------------------*/ -#ifdef CONFIG_ECC +#ifdef CONFIG_MV64360_ECC case 11: /* Error Check Type */ dimmInfo->errorCheckType = data[i]; DP (printf ("Error Check Type (0=NONE): %d\n", dimmInfo->errorCheckType)); break; -#endif +#endif /* of ifdef CONFIG_MV64360_ECC */ /*------------------------------------------------------------------------------------------------------------------------------*/ case 12: /* Refresh Interval */ @@ -1254,6 +1254,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) ulong tmp; ulong tmp_sdram_mode = 0; /* 0x141c */ ulong tmp_dunit_control_low = 0; /* 0x1404 */ + uint sdram_config_reg = CONFIG_SYS_SDRAM_CONFIG; int i; /* sanity checking */ @@ -1269,7 +1270,6 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) DP (printf ("Module is registered, but we do not support registered Modules !!!\n")); - /* delay line */ set_dfcdlInit (); /* may be its not needed */ DP (printf ("Delay line set done\n")); @@ -1281,8 +1281,16 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n")); } +#ifdef CONFIG_MV64360_ECC + if ((info->errorCheckType == 0x2) && (CPCI750_ECC_TEST)) { + /* DRAM has ECC, so turn it on */ + sdram_config_reg |= BIT18; + DP(printf("Enabling ECC\n")); + } +#endif /* of ifdef CONFIG_MV64360_ECC */ + /* SDRAM configuration */ - GT_REG_WRITE (SDRAM_CONFIG, 0x58200400); + GT_REG_WRITE(SDRAM_CONFIG, sdram_config_reg); DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG))); /* SDRAM open pages controll keep open as much as I can */ @@ -1598,7 +1606,84 @@ dram_size(long int *base, long int maxsize) return maxsize; } -/* ------------------------------------------------------------------------- */ +#ifdef CONFIG_MV64360_ECC +/* + * mv_dma_is_channel_active: + * Checks if a engine is busy. + */ +int mv_dma_is_channel_active(int engine) +{ + ulong data; + + data = GTREGREAD(MV64360_DMA_CHANNEL0_CONTROL + 4 * engine); + if (data & BIT14) /* activity status */ + return 1; + + return 0; +} + +/* + * mv_dma_set_memory_space: + * Set a DMA memory window for the DMA's address decoding map. + */ +int mv_dma_set_memory_space(ulong mem_space, ulong mem_space_target, + ulong mem_space_attr, ulong base_address, + ulong size) +{ + ulong temp; + + /* The base address must be aligned to the size. */ + if (base_address % size != 0) + return 0; + + if (size >= 0x10000) { + size &= 0xffff0000; + base_address = (base_address & 0xffff0000); + /* Set the new attributes */ + GT_REG_WRITE(MV64360_DMA_BASE_ADDR_REG0 + mem_space * 8, + (base_address | mem_space_target | + mem_space_attr)); + GT_REG_WRITE((MV64360_DMA_SIZE_REG0 + mem_space * 8), + (size - 1) & 0xffff0000); + temp = GTREGREAD(MV64360_DMA_BASE_ADDR_ENABLE_REG); + GT_REG_WRITE(DMA_BASE_ADDR_ENABLE_REG, + (temp & ~(BIT0 << mem_space))); + return 1; + } + + return 0; +} + + +/* + * mv_dma_transfer: + * Transfer data from source_addr to dest_addr on one of the 4 DMA channels. + */ +int mv_dma_transfer(int engine, ulong source_addr, + ulong dest_addr, ulong bytes, ulong command) +{ + ulong eng_off_reg; /* Engine Offset Register */ + + if (bytes > 0xffff) + command = command | BIT31; /* DMA_16M_DESCRIPTOR_MODE */ + + command = command | ((command >> 6) & 0x7); + eng_off_reg = engine * 4; + GT_REG_WRITE(MV64360_DMA_CHANNEL0_BYTE_COUNT + eng_off_reg, + bytes); + GT_REG_WRITE(MV64360_DMA_CHANNEL0_SOURCE_ADDR + eng_off_reg, + source_addr); + GT_REG_WRITE(MV64360_DMA_CHANNEL0_DESTINATION_ADDR + eng_off_reg, + dest_addr); + command |= BIT12 /* DMA_CHANNEL_ENABLE */ + | BIT9; /* DMA_NON_CHAIN_MODE */ + + /* Activate DMA engine By writting to mv_dma_control_register */ + GT_REG_WRITE(MV64360_DMA_CHANNEL0_CONTROL + eng_off_reg, command); + + return 1; +} +#endif /* of ifdef CONFIG_MV64360_ECC */ /* ppcboot interface function to SDRAM init - this is where all the * controlling logic happens */ @@ -1607,10 +1692,13 @@ initdram(int board_type) { int s0 = 0, s1 = 0; int checkbank[4] = { [0 ... 3] = 0 }; - ulong bank_no, realsize, total, check; + ulong realsize, total, check; AUX_MEM_DIMM_INFO dimmInfo1; AUX_MEM_DIMM_INFO dimmInfo2; - int nhr; + int bank_no, nhr; +#ifdef CONFIG_MV64360_ECC + ulong dest, mem_space_attr; +#endif /* of ifdef CONFIG_MV64360_ECC */ /* first, use the SPD to get info about the SDRAM/ DDRRAM */ @@ -1668,6 +1756,28 @@ initdram(int board_type) realsize = dram_size((long int *)total, check); memory_map_bank(bank_no, total, realsize); +#ifdef CONFIG_MV64360_ECC + if (((dimmInfo1.errorCheckType != 0) && + ((dimmInfo2.errorCheckType != 0) || + (dimmInfo2.numOfModuleBanks == 0))) && + (CPCI750_ECC_TEST)) { + printf("ECC Initialization of Bank %d:", bank_no); + mem_space_attr = ((~(BIT0 << bank_no)) & 0xf) << 8; + mv_dma_set_memory_space(0, 0, mem_space_attr, total, + realsize); + for (dest = total; dest < total + realsize; + dest += _8M) { + mv_dma_transfer(0, total, dest, _8M, + BIT8 | /* DMA_DTL_128BYTES */ + BIT3 | /* DMA_HOLD_SOURCE_ADDR */ + BIT11); /* DMA_BLOCK_TRANSFER_MODE */ + while (mv_dma_is_channel_active(0)) + ; + } + printf(" PASS\n"); + } +#endif /* of ifdef CONFIG_MV64360_ECC */ + total += realsize; } @@ -1700,3 +1810,30 @@ int set_dfcdlInit (void) return (0); } + +int do_show_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int ecc_counter; + unsigned int ecc_addr; + + GT_REG_READ(0x1458, &ecc_counter); + GT_REG_READ(0x1450, &ecc_addr); + GT_REG_WRITE(0x1450, 0); + + printf("Error Counter since Reset: %8d\n", ecc_counter); + printf("Last error address :0x%08x (" , ecc_addr & 0xfffffff8); + if (ecc_addr & 0x01) + printf("double"); + else + printf("single"); + printf(" bit) at DDR-RAM CS#%d\n", ((ecc_addr & 0x6) >> 1)); + + return 0; +} + + +U_BOOT_CMD( + show_ecc, 1, 1, do_show_ecc, + "Show Marvell MV64360 ECC Info", + "Show Marvell MV64360 ECC Counter and last error." +); diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index d516c3cb812..1c8c68b3e47 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -59,7 +59,7 @@ #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */ -#undef CONFIG_ECC /* enable ECC support */ +#define CONFIG_MV64360_ECC /* enable ECC support */ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ @@ -628,5 +628,7 @@ #define CONFIG_SYS_BOARD_ASM_INIT 1 #define CPCI750_SLAVE_TEST (((in8(0xf0300000) & 0x80) == 0) ? 0 : 1) +#define CPCI750_ECC_TEST (((in8(0xf0300000) & 0x02) == 0) ? 1 : 0) +#define CONFIG_SYS_PLD_VER 0xf0e00000 #endif /* __CONFIG_H */ -- cgit v1.3.1 From 5794619e29c5e22280b0b09b2ea6bc3d2e00da3f Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 5 May 2010 04:32:43 -0400 Subject: serial: punt unused serial_addr() Only one file apparently defines this function, and it merely stubs it out. So if no one is defining/calling it, punt it. Signed-off-by: Mike Frysinger --- board/barco/barco.c | 4 ---- include/common.h | 1 - 2 files changed, 5 deletions(-) (limited to 'board') diff --git a/board/barco/barco.c b/board/barco/barco.c index d7a00782b8b..c5fe8c47084 100644 --- a/board/barco/barco.c +++ b/board/barco/barco.c @@ -340,10 +340,6 @@ void serial_puts (const char *c) { return; } -void serial_addr (unsigned int i) -{ - return; -} int serial_getc (void) { return 0; diff --git a/include/common.h b/include/common.h index 5591e1d04b0..8bca04fdd74 100644 --- a/include/common.h +++ b/include/common.h @@ -470,7 +470,6 @@ void ft_pci_setup(void *blob, bd_t *bd); /* $(CPU)/serial.c */ int serial_init (void); void serial_exit (void); -void serial_addr (unsigned int); void serial_setbrg (void); void serial_putc (const char); void serial_putc_raw(const char); -- cgit v1.3.1 From 3b439792b0781921c599d8af9bed6a771d295b53 Mon Sep 17 00:00:00 2001 From: Ron Madrid Date: Wed, 28 Apr 2010 16:04:43 -0700 Subject: mpc83xx: Add UPMA configuration to SIMPC8313 Added UPM array table, upmconfig, and Local Bus configuration support for SIMPC8313 Signed-off-by: Ron Madrid Signed-off-by: Kim Phillips --- arch/powerpc/include/asm/fsl_lbc.h | 1 + board/sheldon/simpc8313/simpc8313.c | 35 +++++++++++++++++++++++++++++++++++ include/configs/SIMPC8313.h | 11 +++++++++++ 3 files changed, 47 insertions(+) (limited to 'board') diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index dfe8f793a30..03ae6a765b4 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -245,6 +245,7 @@ #define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */ #define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */ #define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */ +#define MxMR_UWPL 0x08000000 /* LUPWAIT Polarity Mask */ #define MxMR_OP_NORM 0x00000000 /* Normal Operation */ #define MxMR_OP_WARR 0x10000000 /* Write to Array */ #define MxMR_OP_RARR 0x20000000 /* Read from Array */ diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c index 1044de2a471..0235545ae47 100644 --- a/board/sheldon/simpc8313/simpc8313.c +++ b/board/sheldon/simpc8313/simpc8313.c @@ -29,6 +29,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -91,6 +92,40 @@ void pci_init_board(void) int misc_init_r(void) { int rc = 0; + immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + fsl_lbus_t *lbus = &immap->lbus; + u32 *mxmr = &lbus->mamr; /* Pointer to mamr */ + + /* UPM Table Configuration Code */ + static uint UPMATable[] = { + /* Read Single-Beat (RSS) */ + 0x0fff0c00, 0x0fffdc00, 0x0fff0c05, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + /* Read Burst (RBS) */ + 0x0fff0c00, 0x0ffcdc00, 0x0ffc0c00, 0x0ffc0f0c, + 0x0ffccf0c, 0x0ffc0f0c, 0x0ffcce0c, 0x3ffc0c05, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + /* Write Single-Beat (WSS) */ + 0x0ffc0c00, 0x0ffcdc00, 0x0ffc0c05, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + /* Write Burst (WBS) */ + 0x0ffc0c00, 0x0fffcc0c, 0x0fff0c00, 0x0fffcc00, + 0x0fff1c00, 0x0fffcf0c, 0x0fff0f0c, 0x0fffcf0c, + 0x0fff0c0c, 0x0fffcc0c, 0x0fff0c05, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + /* Refresh Timer (RTS) */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + /* Exception Condition (EXS) */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 + }; + + upmconfig(UPMA, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); + + /* Set LUPWAIT to be active low and enabled */ + out_be32(mxmr, MxMR_UWPL | MxMR_GPL_x4DIS); return rc; } diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 84af8df9c99..1a17323a517 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -126,6 +126,7 @@ #else #define CONFIG_SYS_NAND_BASE 0xE2800000 #endif +#define CONFIG_SYS_FPGA_BASE 0xFF000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 @@ -184,6 +185,16 @@ #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM +#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_FPGA_BASE \ + | BR_PS_16 \ + | BR_MS_UPMA \ + | BR_V ) +#define CONFIG_SYS_OR1_PRELIM ( OR_AM_2MB \ + | OR_UPM_BCTLD) + +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_2MB) + /* * JFFS2 configuration */ -- cgit v1.3.1 From fd194f82d1c30802f0597a3e359fdc03ed397367 Mon Sep 17 00:00:00 2001 From: Andre Schwarz Date: Mon, 3 May 2010 13:22:31 +0200 Subject: mpc83xx/mvBLM7: add usb commands and cleanup. Add USB commands. Rename autoscript to bootscript. Add automatic bootscript image generation to makefile. Signed-off-by: Andre Schwarz Signed-off-by: Kim Phillips --- board/matrix_vision/mvblm7/Makefile | 1 + board/matrix_vision/mvblm7/bootscript | 43 ++++++++++++++++++++++++++++ board/matrix_vision/mvblm7/mvblm7_autoscript | 43 ---------------------------- include/configs/MVBLM7.h | 6 ++++ 4 files changed, 50 insertions(+), 43 deletions(-) create mode 100644 board/matrix_vision/mvblm7/bootscript delete mode 100644 board/matrix_vision/mvblm7/mvblm7_autoscript (limited to 'board') diff --git a/board/matrix_vision/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile index 504935f3b64..b3e3e0bbf40 100644 --- a/board/matrix_vision/mvblm7/Makefile +++ b/board/matrix_vision/mvblm7/Makefile @@ -32,6 +32,7 @@ SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) + @mkimage -T script -C none -n M7_script -d bootscript bootscript.img clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/matrix_vision/mvblm7/bootscript b/board/matrix_vision/mvblm7/bootscript new file mode 100644 index 00000000000..dc385fde793 --- /dev/null +++ b/board/matrix_vision/mvblm7/bootscript @@ -0,0 +1,43 @@ +echo +echo "==== running autoscript ====" +echo +setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram} +setenv ramkernel setenv kernel_boot \${loadaddr} +setenv flashkernel setenv kernel_boot \${mv_kernel_addr} +setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length} +setenv bootfromflash run flashkernel cpird ramparam addcons bootdtb +setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name} +setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000 +setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup +setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel +if test ${console} = yes; +then +setenv addcons setenv bootargs \${bootargs} console=ttyS\${console_nr},\${baudrate}N8 +else +setenv addcons setenv bootargs \${bootargs} console=tty0 +fi +setenv set_static_ip setenv ipaddr \${static_ipaddr} +setenv set_static_nm setenv netmask \${static_netmask} +setenv set_static_gw setenv gatewayip \${static_gateway} +setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask} +setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs +if test ${autoscript_boot} != no; +then + if test ${netboot} = yes; + then + bootp + if test $? = 0; + then + echo "=== bootp succeeded -> netboot ===" + run set_ip + run getdtb rundtb bootfromnet ramparam addcons bootdtb + else + echo "=== netboot failed ===" + fi + fi + run set_static_ip set_static_nm set_static_gw set_ip + echo "=== bootfromflash ===" + run cpdtb rundtb bootfromflash +else + echo "=== boot stopped with autoscript_boot no ===" +fi diff --git a/board/matrix_vision/mvblm7/mvblm7_autoscript b/board/matrix_vision/mvblm7/mvblm7_autoscript deleted file mode 100644 index dc385fde793..00000000000 --- a/board/matrix_vision/mvblm7/mvblm7_autoscript +++ /dev/null @@ -1,43 +0,0 @@ -echo -echo "==== running autoscript ====" -echo -setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram} -setenv ramkernel setenv kernel_boot \${loadaddr} -setenv flashkernel setenv kernel_boot \${mv_kernel_addr} -setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length} -setenv bootfromflash run flashkernel cpird ramparam addcons bootdtb -setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name} -setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000 -setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup -setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel -if test ${console} = yes; -then -setenv addcons setenv bootargs \${bootargs} console=ttyS\${console_nr},\${baudrate}N8 -else -setenv addcons setenv bootargs \${bootargs} console=tty0 -fi -setenv set_static_ip setenv ipaddr \${static_ipaddr} -setenv set_static_nm setenv netmask \${static_netmask} -setenv set_static_gw setenv gatewayip \${static_gateway} -setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask} -setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs -if test ${autoscript_boot} != no; -then - if test ${netboot} = yes; - then - bootp - if test $? = 0; - then - echo "=== bootp succeeded -> netboot ===" - run set_ip - run getdtb rundtb bootfromnet ramparam addcons bootdtb - else - echo "=== netboot failed ===" - fi - fi - run set_static_ip set_static_nm set_static_gw set_ip - echo "=== bootfromflash ===" - run cpdtb rundtb bootfromflash -else - echo "=== boot stopped with autoscript_boot no ===" -fi diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 26897c69aff..c28eb64fb17 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -234,7 +234,11 @@ #define CONFIG_BOOTP_SEND_HOSTNAME /* USB */ +#define CONFIG_SYS_USB_HOST +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL #define CONFIG_HAS_FSL_DR_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* * Environment @@ -267,6 +271,8 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_I2C #define CONFIG_CMD_FPGA +#define CONFIG_CMD_USB +#define CONFIG_DOS_PARTITION #undef CONFIG_WATCHDOG -- cgit v1.3.1 From 15351855776f32d40d9c336c0dc6d22a7bcf40c2 Mon Sep 17 00:00:00 2001 From: Jerry Huang Date: Thu, 8 Apr 2010 15:56:07 +0800 Subject: fsl-diu: Using I/O accessor to CCSR space Using PPC I/O accessor to DIU I/O space instead of directly read/write. It will prevent the dozen of compiler order issue and PPC hardware order issue for accessing I/O space. Using the toolchain(tc-fsl-x86lnx-e500-dp-4.3.74-2.i386.rpm) can show up the order issue of DIU driver. Signed-off-by: Dave Liu Signed-off-by: Jerry Huang Signed-off-by: Kumar Gala --- board/freescale/common/fsl_diu_fb.c | 55 +++++++++++++++++++------------------ 1 file changed, 28 insertions(+), 27 deletions(-) (limited to 'board') diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c index cbee8fe0935..e7f077e0f7e 100644 --- a/board/freescale/common/fsl_diu_fb.c +++ b/board/freescale/common/fsl_diu_fb.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor, Inc. + * Copyright 2007, 2010 Freescale Semiconductor, Inc. * York Sun * * FSL DIU Framebuffer driver @@ -26,6 +26,7 @@ #include #include #include +#include #include "fsl_diu_fb.h" @@ -267,9 +268,9 @@ int fsl_diu_init(int xres, memset(info->screen_base, 0, info->smem_len); - dr.diu_reg->desc[0] = (unsigned int) &dummy_ad; - dr.diu_reg->desc[1] = (unsigned int) &dummy_ad; - dr.diu_reg->desc[2] = (unsigned int) &dummy_ad; + out_be32(&dr.diu_reg->desc[0], &dummy_ad); + out_be32(&dr.diu_reg->desc[1], &dummy_ad); + out_be32(&dr.diu_reg->desc[2], &dummy_ad); debug("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]); debug("dummy desc[0] = 0x%x\n", hw->desc[0]); @@ -331,26 +332,26 @@ int fsl_diu_init(int xres, /* Program DIU registers */ - hw->gamma = (unsigned int) gamma.paddr; - hw->cursor= (unsigned int) cursor.paddr; - hw->bgnd = 0x007F7F7F; /* BGND */ - hw->bgnd_wb = 0; /* BGND_WB */ - hw->disp_size = var->yres << 16 | var->xres; /* DISP SIZE */ - hw->wb_size = 0; /* WB SIZE */ - hw->wb_mem_addr = 0; /* WB MEM ADDR */ - hw->hsyn_para = var->left_margin << 22 | /* BP_H */ + out_be32(&hw->gamma, gamma.paddr); + out_be32(&hw->cursor, cursor.paddr); + out_be32(&hw->bgnd, 0x007F7F7F); + out_be32(&hw->bgnd_wb, 0); /* BGND_WB */ + out_be32(&hw->disp_size, var->yres << 16 | var->xres); /* DISP SIZE */ + out_be32(&hw->wb_size, 0); /* WB SIZE */ + out_be32(&hw->wb_mem_addr, 0); /* WB MEM ADDR */ + out_be32(&hw->hsyn_para, var->left_margin << 22 | /* BP_H */ var->hsync_len << 11 | /* PW_H */ - var->right_margin; /* FP_H */ - hw->vsyn_para = var->upper_margin << 22 | /* BP_V */ - var->vsync_len << 11 | /* PW_V */ - var->lower_margin; /* FP_V */ + var->right_margin); /* FP_H */ - hw->syn_pol = 0; /* SYNC SIGNALS POLARITY */ - hw->thresholds = 0x00037800; /* The Thresholds */ - hw->int_status = 0; /* INTERRUPT STATUS */ - hw->int_mask = 0; /* INT MASK */ - hw->plut = 0x01F5F666; + out_be32(&hw->vsyn_para, var->upper_margin << 22 | /* BP_V */ + var->vsync_len << 11 | /* PW_V */ + var->lower_margin); /* FP_V */ + out_be32(&hw->syn_pol, 0); /* SYNC SIGNALS POLARITY */ + out_be32(&hw->thresholds, 0x00037800); /* The Thresholds */ + out_be32(&hw->int_status, 0); /* INTERRUPT STATUS */ + out_be32(&hw->int_mask, 0); /* INT MASK */ + out_be32(&hw->plut, 0x01F5F666); /* Pixel Clock configuration */ debug("DIU pixclock in ps - %d\n", var->pixclock); diu_set_pixel_clock(var->pixclock); @@ -390,8 +391,8 @@ static int fsl_diu_enable_panel(struct fb_info *info) struct diu_ad *ad = &fsl_diu_fb_ad; debug("Entered: enable_panel\n"); - if (hw->desc[0] != (unsigned int)ad) - hw->desc[0] = (unsigned int)ad; + if (in_be32(&hw->desc[0]) != (u32)ad) + out_be32(&hw->desc[0], ad); debug("desc[0] = 0x%x\n", hw->desc[0]); return 0; } @@ -401,8 +402,8 @@ static int fsl_diu_disable_panel(struct fb_info *info) struct diu *hw = dr.diu_reg; debug("Entered: disable_panel\n"); - if (hw->desc[0] != (unsigned int)&dummy_ad) - hw->desc[0] = (unsigned int)&dummy_ad; + if (in_be32(&hw->desc[0]) != (u32)&dummy_ad) + out_be32(&hw->desc[0], &dummy_ad); return 0; } @@ -443,7 +444,7 @@ static void enable_lcdc(void) debug("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled); if (!fb_enabled) { - hw->diu_mode = dr.mode; + out_be32(&hw->diu_mode, dr.mode); fb_enabled++; } debug("diu_mode = %d\n", hw->diu_mode); @@ -455,7 +456,7 @@ static void disable_lcdc(void) debug("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled); if (fb_enabled) { - hw->diu_mode = 0; + out_be32(&hw->diu_mode, 0); fb_enabled = 0; } } -- cgit v1.3.1 From 54648985e2a64e29784e3ed37cd45b637305cd65 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 20 Apr 2010 10:21:12 -0500 Subject: 85xx/mpc8536ds: Use is_serdes_configured() to determine of PCIe enabled The new is_serdes_configured covers a broader range of devices than the PCI specific code. Use it instead as we convert away from the is_fsl_pci_cfg() code. Additionally move to setting LAWs for PCI based on if its configured. Also updated PCI FDT fixup code to remove PCI controllers from dtb if they are configured. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc8xxx/pci_cfg.c | 12 ------------ board/freescale/mpc8536ds/law.c | 8 -------- board/freescale/mpc8536ds/mpc8536ds.c | 33 +++++++++++++++++++++++++++++---- 3 files changed, 29 insertions(+), 24 deletions(-) (limited to 'board') diff --git a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c index 85995cac95e..186936f23e8 100644 --- a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c +++ b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c @@ -56,18 +56,6 @@ static struct pci_info pci_config_info[] = #elif defined(CONFIG_MPC8536) static struct pci_info pci_config_info[] = { - [LAW_TRGT_IF_PCI] = { - .cfg = 0, - }, - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 5) | (1 << 7), - }, - [LAW_TRGT_IF_PCIE_3] = { - .cfg = (1 << 7), - }, }; #elif defined(CONFIG_MPC8544) static struct pci_info pci_config_info[] = diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c index 1f11563f5a0..61b7454d9a8 100644 --- a/board/freescale/mpc8536ds/law.c +++ b/board/freescale/mpc8536ds/law.c @@ -28,15 +28,7 @@ #include struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3), - SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), }; diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 253ed181fcf..8daa0c359a6 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -219,9 +220,13 @@ void pci_init_board(void) puts("\n"); #ifdef CONFIG_PCIE3 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); + pcie_configured = is_serdes_configured(PCIE3); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ + set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, + LAW_TRGT_IF_PCIE_3); + set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCIE_3); SET_STD_PCIE_INFO(pci_info[num], 3); pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n", @@ -239,9 +244,13 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE1 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, + LAW_TRGT_IF_PCIE_1); + set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCIE_1); SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n", @@ -259,9 +268,13 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE2 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + pcie_configured = is_serdes_configured(PCIE2); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ + set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, + LAW_TRGT_IF_PCIE_2); + set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCIE_2); SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n", @@ -285,6 +298,10 @@ void pci_init_board(void) pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, + LAW_TRGT_IF_PCI); + set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCI); SET_STD_PCI_INFO(pci_info[num], 1); pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", @@ -540,15 +557,23 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_PCI1 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); +#else + ft_fsl_pci_setup(blob, "pci0", NULL); #endif #ifdef CONFIG_PCIE2 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); +#else + ft_fsl_pci_setup(blob, "pci1", NULL); #endif #ifdef CONFIG_PCIE2 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); +#else + ft_fsl_pci_setup(blob, "pci2", NULL); #endif #ifdef CONFIG_PCIE1 ft_fsl_pci_setup(blob, "pci3", &pcie3_hose); +#else + ft_fsl_pci_setup(blob, "pci3", NULL); #endif #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); -- cgit v1.3.1 From f54fe87acedbbad7d29ad18cab31d2b323717514 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 20 Apr 2010 10:21:25 -0500 Subject: 85xx/fsl-sata: Use is_serdes_configured() to determine if SATA is enabled On the MPC85xx platform if we have SATA its connected on SERDES. Determing if SATA is enabled via sata_initialize should not be board specific and thus we move it out of the MPC8536DS board code. Additionally, now that we have is_serdes_configured() we can determine if the given SATA port is enabled and error out if its not in the driver. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 14 +++++++++++++- board/freescale/mpc8536ds/mpc8536ds.c | 11 ----------- drivers/block/fsl_sata.c | 14 +++++++++++++- 3 files changed, 26 insertions(+), 13 deletions(-) (limited to 'board') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index e578b296dfa..99431dc1a76 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2003 Motorola Inc. * Modified by Xianghua Xiao, X.Xiao@motorola.com @@ -30,9 +30,11 @@ #include #include #include +#include #include #include #include +#include #include "mp.h" DECLARE_GLOBAL_DATA_PTR; @@ -418,3 +420,13 @@ void arch_preboot_os(void) setup_ivors(); } + +#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) +int sata_initialize(void) +{ + if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) + return __sata_initialize(); + + return 1; +} +#endif diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 8daa0c359a6..1968106711e 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -498,17 +498,6 @@ get_board_ddr_clk(ulong dummy) } #endif -int sata_initialize(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint sdrs2_io_sel = - (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; - if (sdrs2_io_sel & 0x04) - return 1; - - return __sata_initialize(); -} - int board_eth_init(bd_t *bis) { #ifdef CONFIG_TSEC_ENET diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c index 88785605fa7..4b97a0e226a 100644 --- a/drivers/block/fsl_sata.c +++ b/drivers/block/fsl_sata.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2008 Freescale Semiconductor, Inc. + * Copyright (C) 2008,2010 Freescale Semiconductor, Inc. * Dave Liu * * This program is free software; you can redistribute it and/or @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -129,6 +130,17 @@ int init_sata(int dev) return -1; } +#ifdef CONFIG_MPC85xx + if ((dev == 0) && (!is_serdes_configured(SATA1))) { + printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev); + return -1; + } + if ((dev == 1) && (!is_serdes_configured(SATA2))) { + printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev); + return -1; + } +#endif + /* Allocate SATA device driver struct */ sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t)); if (!sata) { -- cgit v1.3.1 From 2e4f35dbd8e11c3121af99ea8e04ce4fb39e9a4e Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 15 May 2010 20:22:21 +0200 Subject: MVBLM7, MVSMR: fix Makefile (cleanup bootscript.img) Fix MVBLM7 and MVSMR Makefiles for correct out-of-tree building (create "bootscript.img" in build directory instead of source directory) and cleanup (remove "bootscript.img" when cleaning up). Signed-off-by: Wolfgang Denk Cc: Andre Schwarz --- board/matrix_vision/mvblm7/Makefile | 4 ++-- board/matrix_vision/mvsmr/Makefile | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/board/matrix_vision/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile index b3e3e0bbf40..12c7cb6e6ee 100644 --- a/board/matrix_vision/mvblm7/Makefile +++ b/board/matrix_vision/mvblm7/Makefile @@ -32,13 +32,13 @@ SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) - @mkimage -T script -C none -n M7_script -d bootscript bootscript.img + @mkimage -T script -C none -n M7_script -d bootscript $(obj)bootscript.img clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak $(obj).depend $(obj)bootscript.img ######################################################################### diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile index b179e6d78f2..2817fe072c8 100644 --- a/board/matrix_vision/mvsmr/Makefile +++ b/board/matrix_vision/mvsmr/Makefile @@ -36,13 +36,13 @@ SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) - @mkimage -T script -C none -n mvSMR_Script -d bootscript bootscript.img + @mkimage -T script -C none -n mvSMR_Script -d bootscript $(obj)bootscript.img clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak $(obj).depend $(obj)bootscript.img ######################################################################### -- cgit v1.3.1 From 9c3f2d6670e6151f4f6329f572a62b0d2d6768ce Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Tue, 11 May 2010 09:54:00 +0200 Subject: ppc4xx: Fix building PLU405 board Due to some overlapping sections it's time to update TEXT_BASE for this board. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- board/esd/plu405/config.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/esd/plu405/config.mk b/board/esd/plu405/config.mk index 0fb4efab8d4..0a4dbaa54ab 100644 --- a/board/esd/plu405/config.mk +++ b/board/esd/plu405/config.mk @@ -25,4 +25,4 @@ # esd PLU405 boards # -TEXT_BASE = 0xFFFA0000 +TEXT_BASE = 0xFFF80000 -- cgit v1.3.1 From e74244c5a1c8bcea9b047217277dcd3235a285f4 Mon Sep 17 00:00:00 2001 From: Ron Madrid Date: Mon, 10 May 2010 15:23:20 -0700 Subject: Removal of checkboard from spl bootstrap build for SIMPC8313 This patch removes the checkboard function from the build of the 4k bootstrap section for the SIMPC8313 as it is not needed in the spl build. This will allow > 100 bytes of extra room for other uses. Signed-off-by: Ron Madrid Signed-off-by: Kim Phillips --- board/sheldon/simpc8313/simpc8313.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c index 0235545ae47..cb30b488597 100644 --- a/board/sheldon/simpc8313/simpc8313.c +++ b/board/sheldon/simpc8313/simpc8313.c @@ -33,13 +33,13 @@ DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_NAND_SPL int checkboard(void) { puts("Board: Sheldon Instruments SIMPC8313\n"); return 0; } -#ifndef CONFIG_NAND_SPL static struct pci_region pci_regions[] = { { bus_start: CONFIG_SYS_PCI1_MEM_BASE, -- cgit v1.3.1 From 2f05e394fccf62a4693c6b8323de725f90d1f003 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 17 May 2010 23:34:18 +0200 Subject: fsl_diu_fb.c: fix build warnings Commit 15351855 "fsl-diu: Using I/O accessor to CCSR space" caused a number of "passing argument 2 of 'out_be32' makes integer from pointer without a cast" warnings; fix these. Signed-off-by: Wolfgang Denk Cc: Dave Liu Cc: Jerry Huang Cc: Kumar Gala --- board/freescale/common/fsl_diu_fb.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'board') diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c index e7f077e0f7e..e740ad880be 100644 --- a/board/freescale/common/fsl_diu_fb.c +++ b/board/freescale/common/fsl_diu_fb.c @@ -268,9 +268,9 @@ int fsl_diu_init(int xres, memset(info->screen_base, 0, info->smem_len); - out_be32(&dr.diu_reg->desc[0], &dummy_ad); - out_be32(&dr.diu_reg->desc[1], &dummy_ad); - out_be32(&dr.diu_reg->desc[2], &dummy_ad); + out_be32(&dr.diu_reg->desc[0], (int)&dummy_ad); + out_be32(&dr.diu_reg->desc[1], (int)&dummy_ad); + out_be32(&dr.diu_reg->desc[2], (int)&dummy_ad); debug("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]); debug("dummy desc[0] = 0x%x\n", hw->desc[0]); @@ -332,8 +332,8 @@ int fsl_diu_init(int xres, /* Program DIU registers */ - out_be32(&hw->gamma, gamma.paddr); - out_be32(&hw->cursor, cursor.paddr); + out_be32(&hw->gamma, (int)gamma.paddr); + out_be32(&hw->cursor, (int)cursor.paddr); out_be32(&hw->bgnd, 0x007F7F7F); out_be32(&hw->bgnd_wb, 0); /* BGND_WB */ out_be32(&hw->disp_size, var->yres << 16 | var->xres); /* DISP SIZE */ @@ -391,8 +391,8 @@ static int fsl_diu_enable_panel(struct fb_info *info) struct diu_ad *ad = &fsl_diu_fb_ad; debug("Entered: enable_panel\n"); - if (in_be32(&hw->desc[0]) != (u32)ad) - out_be32(&hw->desc[0], ad); + if (in_be32(&hw->desc[0]) != (unsigned)ad) + out_be32(&hw->desc[0], (unsigned)ad); debug("desc[0] = 0x%x\n", hw->desc[0]); return 0; } @@ -402,8 +402,8 @@ static int fsl_diu_disable_panel(struct fb_info *info) struct diu *hw = dr.diu_reg; debug("Entered: disable_panel\n"); - if (in_be32(&hw->desc[0]) != (u32)&dummy_ad) - out_be32(&hw->desc[0], &dummy_ad); + if (in_be32(&hw->desc[0]) != (unsigned)&dummy_ad) + out_be32(&hw->desc[0], (unsigned)&dummy_ad); return 0; } -- cgit v1.3.1 From 3f786bb8542ee85ea898152b40b1f0d98f0801df Mon Sep 17 00:00:00 2001 From: Mahavir Jain <[mjain@marvell.com]> Date: Fri, 21 May 2010 14:37:48 +0530 Subject: bugfix: Guruplug: Use standard miiphy call to reset PHY chip. Current PHY Software Reset operation in guruplug does not poll reset bit in control register to go to 0(auto clearing) for making sure reset was successful.This patch uses standard miiphy call miiphy_reset to make sure proper PHY reset operation. Signed-off-by: Mahavir Jain --- board/Marvell/guruplug/guruplug.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) (limited to 'board') diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index ba47ca179f2..c028a53bcbf 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -146,14 +146,7 @@ void mv_phy_88e1121_init(char *name) miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0); /* reset the phy */ - if (miiphy_read (name, devadr, PHY_BMCR, ®) != 0) { - printf("Err..(%s) PHY status read failed\n", __FUNCTION__); - return; - } - if (miiphy_write (name, devadr, PHY_BMCR, reg | 0x8000) != 0) { - printf("Err..(%s) PHY reset failed\n", __FUNCTION__); - return; - } + miiphy_reset(name, devadr); printf("88E1121 Initialized on %s\n", name); } -- cgit v1.3.1 From 6ece2550d1c0c5c811b302b1639ea35c2e485203 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 21 May 2010 04:17:48 -0500 Subject: Convert Makefiles from COBJS-${} to COBJS-$() Match style we use almost everywhere else Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc512x/Makefile | 10 +++++----- board/freescale/common/Makefile | 22 +++++++++++----------- board/freescale/mpc8610hpcd/Makefile | 2 +- 3 files changed, 17 insertions(+), 17 deletions(-) (limited to 'board') diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile index 9cfdb0f35de..28926e0d24c 100644 --- a/arch/powerpc/cpu/mpc512x/Makefile +++ b/arch/powerpc/cpu/mpc512x/Makefile @@ -37,11 +37,11 @@ COBJS-y += interrupts.o COBJS-y += iopin.o COBJS-y += serial.o COBJS-y += speed.o -COBJS-${CONFIG_FSL_DIU_FB} += diu.o -COBJS-${CONFIG_FSL_DIU_FB} += ../../../../board/freescale/common/fsl_diu_fb.o -COBJS-${CONFIG_FSL_DIU_FB} += ../../../../board/freescale/common/fsl_logo_bmp.o -COBJS-${CONFIG_CMD_IDE} += ide.o -COBJS-${CONFIG_IIM} += iim.o +COBJS-$(CONFIG_FSL_DIU_FB) += diu.o +COBJS-$(CONFIG_FSL_DIU_FB) += ../../../../board/freescale/common/fsl_diu_fb.o +COBJS-$(CONFIG_FSL_DIU_FB) += ../../../../board/freescale/common/fsl_logo_bmp.o +COBJS-$(CONFIG_CMD_IDE) += ide.o +COBJS-$(CONFIG_IIM) += iim.o COBJS-$(CONFIG_PCI) += pci.o COBJS := $(COBJS-y) diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 620eb16d441..df289aa634a 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -29,18 +29,18 @@ endif LIB = $(obj)lib$(VENDOR).a -COBJS-${CONFIG_FSL_CADMUS} += cadmus.o -COBJS-${CONFIG_FSL_VIA} += cds_via.o -COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o -COBJS-${CONFIG_FSL_PIXIS} += pixis.o -COBJS-${CONFIG_FSL_NGPIXIS} += ngpixis.o -COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o -COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o -COBJS-${CONFIG_FSL_SGMII_RISER} += sgmii_riser.o +COBJS-$(CONFIG_FSL_CADMUS) += cadmus.o +COBJS-$(CONFIG_FSL_VIA) += cds_via.o +COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o fsl_logo_bmp.o +COBJS-$(CONFIG_FSL_PIXIS) += pixis.o +COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o +COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o +COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o +COBJS-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o -COBJS-${CONFIG_MPC8541CDS} += cds_pci_ft.o -COBJS-${CONFIG_MPC8548CDS} += cds_pci_ft.o -COBJS-${CONFIG_MPC8555CDS} += cds_pci_ft.o +COBJS-$(CONFIG_MPC8541CDS) += cds_pci_ft.o +COBJS-$(CONFIG_MPC8548CDS) += cds_pci_ft.o +COBJS-$(CONFIG_MPC8555CDS) += cds_pci_ft.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile index 930a2063abc..847edaf920f 100644 --- a/board/freescale/mpc8610hpcd/Makefile +++ b/board/freescale/mpc8610hpcd/Makefile @@ -27,7 +27,7 @@ COBJS-y += $(BOARD).o COBJS-$(CONFIG_FSL_DDR2) += ddr.o COBJS-y += law.o -COBJS-${CONFIG_FSL_DIU_FB} += mpc8610hpcd_diu.o +COBJS-$(CONFIG_FSL_DIU_FB) += mpc8610hpcd_diu.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) -- cgit v1.3.1