From e91617883ea50f6f67966f402f84a31ee47170d1 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Sat, 31 Jan 2015 11:52:38 +0100 Subject: edminiv2: switch to generic board support Signed-off-by: Albert ARIBAUD --- board/LaCie/edminiv2/config.mk | 12 ------------ 1 file changed, 12 deletions(-) delete mode 100644 board/LaCie/edminiv2/config.mk (limited to 'board') diff --git a/board/LaCie/edminiv2/config.mk b/board/LaCie/edminiv2/config.mk deleted file mode 100644 index dfa84f032e7..00000000000 --- a/board/LaCie/edminiv2/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (C) 2010 Albert ARIBAUD -# -# (C) Copyright 2009 -# Marvell Semiconductor -# Written-by: Prafulla Wadaskar -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# TEXT_BASE must equal the intended FLASH location of u-boot. -CONFIG_SYS_TEXT_BASE = 0xfff90000 -- cgit v1.3.1 From 9608e7de6ac13626e8a2809b0350add57c1343ac Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Sat, 31 Jan 2015 22:55:38 +0100 Subject: edminiv2: switch to SPL ED Mini V2 is based on Orion 5x which boots at fixed address 0xFFFF0000 in NOR Flash. Place SPL there, and switch U-Boot from .bin to .img format, stored in NOR Flash at 0xFFF90000. Note: this patch was tested on HW and works, i.e. it boots U-Boot properly, but SPL console output currently does not appear, due to GD being trashed by arch/arm/lib/spl.c. This trashing is soon to be removed, and then ED Mini V2 SPL console output will become visible. Signed-off-by: Albert ARIBAUD --- arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds | 61 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-orion5x/spl.h | 10 +++++ arch/arm/mach-orion5x/Kconfig | 1 + arch/arm/mach-orion5x/cpu.c | 2 + arch/arm/mach-orion5x/lowlevel_init.S | 14 +++++- board/LaCie/edminiv2/edminiv2.c | 20 +++++++++ configs/edminiv2_defconfig | 7 +-- include/configs/edminiv2.h | 23 +++++++++- 8 files changed, 132 insertions(+), 6 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds create mode 100644 arch/arm/include/asm/arch-orion5x/spl.h (limited to 'board') diff --git a/arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds new file mode 100644 index 00000000000..6f7fca07e37 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2014 Albert ARIBAUD + * + * Based on: + * + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * Based on omap-common/u-boot-spl.lds: + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2010 + * Texas Instruments, + * Aneesh V + * + * SPDX-License-Identifier: GPL-2.0+ + */ +MEMORY { .nor : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .bss : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + *(.vectors) + CPUDIR/start.o (.text) + *(.text*) + } > .nor + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.nor + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.nor + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } > .nor + + . = ALIGN(4); + __image_copy_end = .; + _end = .; + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } > .bss +} diff --git a/arch/arm/include/asm/arch-orion5x/spl.h b/arch/arm/include/asm/arch-orion5x/spl.h new file mode 100644 index 00000000000..23745bc1a54 --- /dev/null +++ b/arch/arm/include/asm/arch-orion5x/spl.h @@ -0,0 +1,10 @@ +/* + * (C) Copyright 2014 Albert ARIBAUD + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_ARCH_SPL_H_ + +#define BOOT_DEVICE_NOR 1 diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 5a542629c75..291c511ba85 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -5,6 +5,7 @@ choice config TARGET_EDMINIV2 bool "LaCie Ethernet Disk mini V2" + select SUPPORT_SPL endchoice diff --git a/arch/arm/mach-orion5x/cpu.c b/arch/arm/mach-orion5x/cpu.c index f88db3b1f96..2ecd3856780 100644 --- a/arch/arm/mach-orion5x/cpu.c +++ b/arch/arm/mach-orion5x/cpu.c @@ -234,7 +234,9 @@ int arch_cpu_init(void) /* Enable and invalidate L2 cache in write through mode */ invalidate_l2_cache(); +#ifdef CONFIG_SPL_BUILD orion5x_config_adr_windows(); +#endif return 0; } diff --git a/arch/arm/mach-orion5x/lowlevel_init.S b/arch/arm/mach-orion5x/lowlevel_init.S index 4dacc296e41..51a8b3c51b2 100644 --- a/arch/arm/mach-orion5x/lowlevel_init.S +++ b/arch/arm/mach-orion5x/lowlevel_init.S @@ -62,14 +62,16 @@ /* * Low-level init happens right after start.S has switched to SVC32, * flushed and disabled caches and disabled MMU. We're still running - * from the boot chip select, so the first thing we should do is set - * up RAM for us to relocate into. + * from the boot chip select, so the first thing SPL should do is to + * set up the RAM to copy U-Boot into. */ .globl lowlevel_init lowlevel_init: +#ifdef CONFIG_SPL_BUILD + /* Use 'r4 as the base for internal register accesses */ ldr r4, =ORION5X_REGS_PHY_BASE @@ -273,5 +275,13 @@ lowlevel_init: orr r2, r2, r6 str r2, [r3, #0x484] + /* enable for 2 GB DDR; detection should find out real amount */ + sub r6, r6, r6 + str r6, [r3, #0x500] + ldr r6, =0x7fff0001 + str r6, [r3, #0x504] + +#endif /* CONFIG_SPL_BUILD */ + /* Return to U-boot via saved link register */ mov pc, lr diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c index 80ec7faa049..29832018017 100644 --- a/board/LaCie/edminiv2/edminiv2.c +++ b/board/LaCie/edminiv2/edminiv2.c @@ -12,6 +12,8 @@ #include #include #include "../common/common.h" +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -83,3 +85,21 @@ void reset_phy(void) mv_phy_88e1116_init("egiga0", 8); } #endif /* CONFIG_RESET_PHY_R */ + +/* + * SPL serial setup and NOR boot device selection + */ + +#ifdef CONFIG_SPL_BUILD + +void spl_board_init(void) +{ + preloader_console_init(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_NOR; +} + +#endif /* CONFIG_SPL_BUILD */ diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig index 3b1a6c193a7..20c1c65e1ff 100644 --- a/configs/edminiv2_defconfig +++ b/configs/edminiv2_defconfig @@ -1,3 +1,4 @@ -CONFIG_ARM=y -CONFIG_ORION5X=y -CONFIG_TARGET_EDMINIV2=y +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ORION5X=y ++S:CONFIG_TARGET_EDMINIV2=y diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 47da4a91952..ee5f76b9ec5 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -13,9 +13,30 @@ #define _CONFIG_EDMINIV2_H /* general settings */ -#define CONFIG_SYS_TEXT_BASE 0xfff90000 #define CONFIG_SYS_GENERIC_BOARD +/* + * SPL + */ + +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NOR_SUPPORT +#define CONFIG_SPL_TEXT_BASE 0xffff0000 +#define CONFIG_SPL_MAX_SIZE 0x0000fff0 +#define CONFIG_SPL_STACK 0x00020000 +#define CONFIG_SPL_BSS_START_ADDR 0x00020000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff +#define CONFIG_SYS_SPL_MALLOC_START 0x00040000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds" +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_UBOOT_BASE 0xfff90000 +#define CONFIG_SYS_UBOOT_START 0x00800000 +#define CONFIG_SYS_TEXT_BASE 0x00800000 + /* * Version number information */ -- cgit v1.3.1 From 419fa9ae216716789e45f2b18cb975db35c6d669 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Sun, 1 Feb 2015 12:04:43 +0100 Subject: edminiv2: drop CONFIG_CFI_LEGACY Nowadays generic CFI code properly detects the ED Mini V2's Macronix MC29LV400CB flash chip, therefore we can drop the CONFIG_FLASH_CFI_LEGACY option and associated settings and code. Signed-off-by: Albert ARIBAUD --- board/LaCie/edminiv2/edminiv2.c | 50 ----------------------------------------- include/configs/edminiv2.h | 4 ---- 2 files changed, 54 deletions(-) (limited to 'board') diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c index 29832018017..edf6281797b 100644 --- a/board/LaCie/edminiv2/edminiv2.c +++ b/board/LaCie/edminiv2/edminiv2.c @@ -17,56 +17,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* - * The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH - * which CFI does not properly detect, hence the LEGACY config. - */ -#if defined(CONFIG_FLASH_CFI_LEGACY) -#include -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - int sectsz[] = CONFIG_SYS_FLASH_SECTSZ; - int sect; - - if (base != CONFIG_SYS_FLASH_BASE) - return 0; - - info->size = 0; - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - /* set each sector's start address and size based */ - for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) { - info->start[sect] = base+info->size; - info->size += sectsz[sect]; - } - /* This flash must be accessed in 8-bits mode, no buffer. */ - info->flash_id = 0x01000000; - info->portwidth = FLASH_CFI_8BIT; - info->chipwidth = FLASH_CFI_BY8; - info->buffer_size = 0; - /* timings are derived from the Macronix datasheet. */ - info->erase_blk_tout = 1000; - info->write_tout = 10; - info->buffer_write_tout = 300; - /* Commands and addresses are for AMD mode 8-bit access. */ - info->vendor = CFI_CMDSET_AMD_LEGACY; - info->cmd_reset = 0xF0; - info->interface = FLASH_CFI_X8; - info->legacy_unlock = 0; - info->ext_addr = 0; - info->addr_unlock1 = 0x00000aaa; - info->addr_unlock2 = 0x00000555; - /* Manufacturer Macronix, device MX29LV400CB, CFI 1.3. */ - info->manufacturer_id = 0x22; - info->device_id = 0xBA; - info->device_id2 = 0; - info->cfi_version = 0x3133; - info->cfi_offset = 0x0000; - info->name = "MX29LV400CB"; - - return 1; -} -#endif /* CONFIG_SYS_FLASH_CFI */ - int board_init(void) { /* arch number of board */ diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index ee5f76b9ec5..5ce01fb2aea 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -114,13 +114,9 @@ #define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_FLASH_CFI_LEGACY #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ #define CONFIG_SYS_FLASH_BASE 0xfff80000 -#define CONFIG_SYS_FLASH_SECTSZ \ - {16384, 8192, 8192, 32768, \ - 65536, 65536, 65536, 65536, 65536, 65536, 65536} /* auto boot */ #define CONFIG_BOOTDELAY 3 /* default enable autoboot */ -- cgit v1.3.1 From 73c38934daa10b518b20f2d21298fc8a8226843b Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 19 Jan 2015 16:25:52 -0700 Subject: ARM: tegra: support running in non-secure mode When the CPU is in non-secure (NS) mode (when running U-Boot under a secure monitor), certain actions cannot be taken, since they would need to write to secure-only registers. One example is configuring the ARM architectural timer's CNTFRQ register. We could support this in one of two ways: 1) Compile twice, once for secure mode (in which case anything goes) and once for non-secure mode (in which case certain actions are disabled). This complicates things, since everyone needs to keep track of different U-Boot binaries for different situations. 2) Detect NS mode at run-time, and optionally skip any impossible actions. This has the advantage of a single U-Boot binary working in all cases. (2) is not possible on ARM in general, since there's no architectural way to detect secure-vs-non-secure. However, there is a Tegra-specific way to detect this. This patches uses that feature to detect secure vs. NS mode on Tegra, and uses that to: * Skip the ARM arch timer initialization. * Set/clear an environment variable so that boot scripts can take different action depending on which mode the CPU is in. This might be something like: if CPU is secure: load secure monitor code into RAM. boot secure monitor. secure monitor will restart (a new copy of) U-Boot in NS mode. else: execute normal boot process Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- README | 7 +++++++ arch/arm/include/asm/arch-tegra/ap.h | 4 ++++ arch/arm/mach-tegra/board.c | 19 +++++++++++++++++++ arch/arm/mach-tegra/clock.c | 6 +++++- board/nvidia/common/board.c | 9 +++++++++ 5 files changed, 44 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/README b/README index ba57dc5617a..8a4c5a721e5 100644 --- a/README +++ b/README @@ -621,6 +621,13 @@ The following options need to be configured: exists, unlike the similar options in the Linux kernel. Do not set these options unless they apply! +- Tegra SoC options: + CONFIG_TEGRA_SUPPORT_NON_SECURE + + Support executing U-Boot in non-secure (NS) mode. Certain + impossible actions will be skipped if the CPU is in NS mode, + such as ARM architectural timer initialization. + - Driver Model Driver model is a new framework for devices in U-Boot introduced in early 2014. U-Boot is being progressively diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h index 5c8be94d977..ca40e4e0bce 100644 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ b/arch/arm/include/asm/arch-tegra/ap.h @@ -74,3 +74,7 @@ static inline void config_vpr(void) { } #endif + +#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) +bool tegra_cpu_is_non_secure(void); +#endif diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 87511a31df1..0ebaf193255 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -28,6 +29,24 @@ enum { UART_COUNT = 5, }; +#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) +#if !defined(CONFIG_TEGRA124) +#error tegra_cpu_is_non_secure has only been validated on Tegra124 +#endif +bool tegra_cpu_is_non_secure(void) +{ + /* + * This register reads 0xffffffff in non-secure mode. This register + * only implements bits 31:20, so the lower bits will always read 0 in + * secure mode. Thus, the lower bits are an indicator for secure vs. + * non-secure mode. + */ + struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; + uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0); + return (mc_s_cfg0 & 1) == 1; +} +#endif + /* Read the RAM size directly from the memory controller */ unsigned int query_sdram_size(void) { diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 11c7435505c..7c274b5f994 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -573,7 +574,10 @@ void clock_init(void) debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]); /* Do any special system timer/TSC setup */ - arch_timer_init(); +#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) + if (!tegra_cpu_is_non_secure()) +#endif + arch_timer_init(); } static void set_avp_clock_source(u32 src) diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 80ef8fdcb23..018dddba155 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -21,6 +21,7 @@ #include #endif #include +#include #include #include #include @@ -179,6 +180,14 @@ int board_late_init(void) #ifdef CONFIG_LCD /* Make sure we finish initing the LCD */ tegra_lcd_check_next_stage(gd->fdt_blob, 1); +#endif +#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) + if (tegra_cpu_is_non_secure()) { + printf("CPU is in NS mode\n"); + setenv("cpu_ns_mode", "1"); + } else { + setenv("cpu_ns_mode", ""); + } #endif return 0; } -- cgit v1.3.1 From c1fe92fe29c05fe5ba624a25c5d9b19824514294 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 18 Feb 2015 13:27:04 -0700 Subject: ARM: tegra: import latest Jetson TK1 pinmux Syseng has revamped the Jetson TK1 pinmux spreadsheet, basing the content completely on correct configuration for the board/schematic, rather than the previous version which was based on the bare minimum changes relative to another reference board. The new spreadsheet sets TRISTATE for any input-only pins. This only works correctly if the global CLAMP bit is not set, so the Jetson TK1 board code has been adjusted accordingly. Apparently syseng have changed their mind since the previous advice that this needed to be set:-/ This content comes from Jetson_TK1_customer_pinmux.xlsm (v09) downloaded from https://developer.nvidia.com/hardware-design-and-development. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- board/nvidia/jetson-tk1/jetson-tk1.c | 2 +- board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h | 303 +++++++++------------ 2 files changed, 136 insertions(+), 169 deletions(-) (limited to 'board') diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index daa74a4be02..52425a8f6de 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR; */ void pinmux_init(void) { - pinmux_set_tristate_input_clamping(); + pinmux_clear_tristate_input_clamping(); gpio_config_table(jetson_tk1_gpio_inits, ARRAY_SIZE(jetson_tk1_gpio_inits)); diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h index de4eb355982..863721b2a33 100644 --- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h +++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -15,77 +15,47 @@ static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = { /* gpio, init_val */ - GPIO_INIT(C7, IN), - GPIO_INIT(G0, OUT0), - GPIO_INIT(G1, OUT0), + GPIO_INIT(G0, IN), + GPIO_INIT(G1, IN), GPIO_INIT(G2, IN), GPIO_INIT(G3, IN), + GPIO_INIT(G4, IN), GPIO_INIT(H2, OUT0), - GPIO_INIT(H3, OUT0), GPIO_INIT(H4, IN), - GPIO_INIT(H5, OUT0), - GPIO_INIT(H6, IN), - GPIO_INIT(H7, OUT0), + GPIO_INIT(H7, IN), GPIO_INIT(I0, OUT0), - GPIO_INIT(I2, OUT0), - GPIO_INIT(I4, OUT0), - GPIO_INIT(I5, IN), + GPIO_INIT(I1, IN), GPIO_INIT(I6, IN), GPIO_INIT(J0, IN), - GPIO_INIT(J2, IN), GPIO_INIT(K1, OUT0), GPIO_INIT(K2, IN), - GPIO_INIT(K3, IN), GPIO_INIT(K4, OUT0), - GPIO_INIT(K5, OUT0), GPIO_INIT(K6, OUT0), GPIO_INIT(N7, IN), - GPIO_INIT(O0, IN), GPIO_INIT(O1, IN), - GPIO_INIT(O2, IN), - GPIO_INIT(O3, IN), GPIO_INIT(O4, IN), - GPIO_INIT(O5, IN), - GPIO_INIT(O6, OUT0), - GPIO_INIT(O7, IN), - GPIO_INIT(P0, OUT0), - GPIO_INIT(P1, OUT0), GPIO_INIT(P2, OUT0), GPIO_INIT(Q0, IN), - GPIO_INIT(Q1, IN), - GPIO_INIT(Q2, IN), + GPIO_INIT(Q3, IN), GPIO_INIT(Q5, IN), - GPIO_INIT(Q6, IN), - GPIO_INIT(Q7, IN), GPIO_INIT(R0, OUT0), - GPIO_INIT(R1, OUT0), GPIO_INIT(R2, OUT0), GPIO_INIT(R4, IN), - GPIO_INIT(R5, OUT0), GPIO_INIT(R7, IN), - GPIO_INIT(S0, IN), - GPIO_INIT(S3, OUT0), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S5, IN), - GPIO_INIT(S6, OUT0), + GPIO_INIT(S7, IN), GPIO_INIT(T0, OUT0), - GPIO_INIT(T1, OUT0), - GPIO_INIT(U0, OUT0), + GPIO_INIT(T1, IN), + GPIO_INIT(U0, IN), GPIO_INIT(U1, IN), GPIO_INIT(U2, IN), - GPIO_INIT(U3, OUT0), - GPIO_INIT(U4, OUT0), + GPIO_INIT(U3, IN), + GPIO_INIT(U4, IN), GPIO_INIT(U5, IN), GPIO_INIT(U6, IN), GPIO_INIT(V0, IN), GPIO_INIT(V1, IN), - GPIO_INIT(W2, IN), - GPIO_INIT(W3, IN), - GPIO_INIT(X1, OUT0), - GPIO_INIT(X3, IN), - GPIO_INIT(X4, OUT0), - GPIO_INIT(X5, IN), - GPIO_INIT(X6, IN), + GPIO_INIT(X1, IN), + GPIO_INIT(X4, IN), GPIO_INIT(X7, OUT0), GPIO_INIT(BB3, OUT0), GPIO_INIT(BB5, OUT0), @@ -93,10 +63,7 @@ static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = { GPIO_INIT(BB7, OUT0), GPIO_INIT(CC1, IN), GPIO_INIT(CC2, IN), - GPIO_INIT(CC5, OUT0), - GPIO_INIT(EE1, OUT0), - GPIO_INIT(FF1, OUT0), - GPIO_INIT(FF2, IN), + GPIO_INIT(EE2, OUT1), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ @@ -114,152 +81,152 @@ static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = { static const struct pmux_pingrp_config jetson_tk1_pingrps[] = { /* pingrp, mux, pull, tri, e_input, od, rcv_sel */ - PINCFG(CLK_32K_OUT_PA0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(UART3_CTS_N_PA1, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK_32K_OUT_PA0, SOC, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(UART3_CTS_N_PA1, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PB0, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PB1, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PB0, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PB1, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART3_RTS_N_PC0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(UART2_RXD_PC3, IRDA, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART2_RXD_PC3, IRDA, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), - PINCFG(PC7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PG0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PG1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PG2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PG3, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PG1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PG2, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PG3, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PG4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG7, SPI4, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PH2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PH4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PH5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PI1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PI4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PI5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PI6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI6, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PJ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(UART2_CTS_N_PJ5, UARTB, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PJ0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_CTS_N_PJ5, UARTB, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PK0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PK2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PK3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PK4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(SPDIF_OUT_PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(SPDIF_IN_PK6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PK7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(DAP1_FS_PN0, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DAP1_DIN_PN1, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(DAP1_DOUT_PN2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(DAP1_SCLK_PN3, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(USB_VBUS_EN0_PN4, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT), - PINCFG(USB_VBUS_EN1_PN5, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT), - PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL), - PINCFG(ULPI_DATA7_PO0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA0_PO1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA1_PO2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA2_PO3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA3_PO4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA4_PO5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA5_PO6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA6_PO7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DAP3_FS_PP0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(DAP3_DIN_PP1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, TRISTATE, INPUT, DEFAULT, NORMAL), + PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA0_PO1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA3_PO4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA4_PO5, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA5_PO6, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), - PINCFG(DAP4_FS_PP4, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DAP4_DIN_PP5, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DAP4_DOUT_PP6, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DAP4_SCLK_PP7, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL0_PQ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL1_PQ1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL2_PQ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL3_PQ3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL5_PQ5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL6_PQ6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL7_PQ7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL0_PQ0, DEFAULT, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL2_PQ2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL4_PQ4, SDMMC3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL5_PQ5, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL6_PQ6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL7_PQ7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW1_PR1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(KB_ROW2_PR2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW3_PR3, SYS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW4_PR4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW5_PR5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW7_PR7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW8_PS0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW9_PS1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW10_PS2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW13_PS5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW14_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW15_PS7, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW7_PR7, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW9_PS1, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW10_PS2, UARTA, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW11_PS3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW12_PS4, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(KB_ROW16_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PU0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PU1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PU2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PU3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PU4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PV0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PV1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU5, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PV0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PV1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), - PINCFG(GPIO_W2_AUD_PW2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(GPIO_W3_AUD_PW3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_W3_AUD_PW3, SPI6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART3_TXD_PW6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART3_RXD_PW7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(GPIO_X3_AUD_PX3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(GPIO_X5_AUD_PX5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(GPIO_X6_AUD_PX6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DIR_PY1, SPI1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT3_PY4, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT2_PY5, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT1_PY6, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT0_PY7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_CLK_PZ0, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_CMD_PZ1, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), @@ -279,30 +246,30 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = { PINCFG(PBB6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PBB7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PCC1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PCC2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PCC1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PCC2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK2_REQ_PCC5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PEX_L0_RST_N_PDD1, PE0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PEX_WAKE_N_PDD3, PE, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PEX_WAKE_N_PDD3, PE, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(PEX_L1_RST_N_PDD5, PE1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(CLK3_REQ_PEE1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(DAP_MCLK1_REQ_PEE2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP_MCLK1_REQ_PEE2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(USB_VBUS_EN2_PFF1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PFF2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DP_HPD_PFF0, DP, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(CPU_PWR_REQ, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PWR_INT_N, PMI, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL), - PINCFG(CLK_32K_IN, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT), }; -- cgit v1.3.1