From ca5f1e25e5cb1caacac3dc5ef6fb3bf00dbf9d30 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Sat, 22 Jul 2023 00:14:30 +0530 Subject: j7200: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img Support has been added for both HS-SE(SR 2.0), HS-FS(SR 2.0) and GP images. HS-SE: * tiboot3-j7200_sr2-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-j7200_sr2-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-j7200-gp-evm.bin * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by J7200 requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass [afd@ti.com: changed output binary names appropriately] Signed-off-by: Andrew Davis Signed-off-by: Neha Malcom Francis --- board/ti/j721e/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'board') diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig index 4a127c4a10e..e6cb21f77bd 100644 --- a/board/ti/j721e/Kconfig +++ b/board/ti/j721e/Kconfig @@ -33,6 +33,7 @@ config TARGET_J7200_A72_EVM select BOARD_LATE_INIT imply TI_I2C_BOARD_DETECT select SYS_DISABLE_DCACHE_OPS + select BINMAN config TARGET_J7200_R5_EVM bool "TI K3 based J7200 EVM running on R5" @@ -42,6 +43,7 @@ config TARGET_J7200_R5_EVM select RAM select SPL_RAM select K3_DDRSS + select BINMAN imply SYS_K3_SPL_ATF imply TI_I2C_BOARD_DETECT -- cgit v1.3.1