From 6761cb5bc203171cf88cdeedc54706a4e8080c24 Mon Sep 17 00:00:00 2001 From: Tom Fitzhenry Date: Tue, 24 Oct 2023 01:22:22 +1100 Subject: board: rockchip: add Pine64 QuartzPro64 RK3588 board QuartzPro64 is a Rockchip RK3588 based SBC by Pine64. UART and boot over SD/eMMC/RJ45 are tested to work. Linux commits from next-20231013: 8152d3d070a9 ("arm64: dts: rockchip: Add QuartzPro64 SBC device tree") Signed-off-by: Tom Fitzhenry Reviewed-by: Kever Yang Cc: Eugen Hristev Cc: Jonas Karlman Cc: Ondrej Jirman --- board/pine64/quartzpro64-rk3588/Kconfig | 15 +++++++++ board/pine64/quartzpro64-rk3588/MAINTAINERS | 8 +++++ board/pine64/quartzpro64-rk3588/Makefile | 3 ++ .../pine64/quartzpro64-rk3588/quartzpro64-rk3588.c | 39 ++++++++++++++++++++++ 4 files changed, 65 insertions(+) create mode 100644 board/pine64/quartzpro64-rk3588/Kconfig create mode 100644 board/pine64/quartzpro64-rk3588/MAINTAINERS create mode 100644 board/pine64/quartzpro64-rk3588/Makefile create mode 100644 board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c (limited to 'board') diff --git a/board/pine64/quartzpro64-rk3588/Kconfig b/board/pine64/quartzpro64-rk3588/Kconfig new file mode 100644 index 00000000000..96aa7921d32 --- /dev/null +++ b/board/pine64/quartzpro64-rk3588/Kconfig @@ -0,0 +1,15 @@ +if TARGET_QUARTZPRO64_RK3588 + +config SYS_BOARD + default "quartzpro64-rk3588" + +config SYS_VENDOR + default "pine64" + +config SYS_CONFIG_NAME + default "quartzpro64-rk3588" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/pine64/quartzpro64-rk3588/MAINTAINERS b/board/pine64/quartzpro64-rk3588/MAINTAINERS new file mode 100644 index 00000000000..a7e944b7478 --- /dev/null +++ b/board/pine64/quartzpro64-rk3588/MAINTAINERS @@ -0,0 +1,8 @@ +QUARTZPRO64-RK3588 +M: Tom Fitzhenry +S: Maintained +F: board/pine64/quartzpro64-rk3588 +F: include/configs/quartzpro64-rk3588.h +F: configs/quartzpro64-rk3588_defconfig +F: arch/arm/dts/rk3588-quartzpro64.dts +F: arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi diff --git a/board/pine64/quartzpro64-rk3588/Makefile b/board/pine64/quartzpro64-rk3588/Makefile new file mode 100644 index 00000000000..47819d9be93 --- /dev/null +++ b/board/pine64/quartzpro64-rk3588/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += quartzpro64-rk3588.o diff --git a/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c b/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c new file mode 100644 index 00000000000..bda804a89e2 --- /dev/null +++ b/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 Google, Inc + */ + +#include +#include + +#ifdef CONFIG_OF_BOARD_SETUP +int quartzpro64_add_reserved_memory_fdt_nodes(void *new_blob) +{ + struct fdt_memory gap1 = { + .start = 0x3fc000000, + .end = 0x3fc4fffff, + }; + struct fdt_memory gap2 = { + .start = 0x3fff00000, + .end = 0x3ffffffff, + }; + unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; + unsigned int ret; + + /* + * Inject the reserved-memory nodes into the DTS + */ + ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0, + NULL, flags); + if (ret) + return ret; + + return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0, + NULL, flags); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return quartzpro64_add_reserved_memory_fdt_nodes(blob); +} +#endif -- cgit v1.3.1 From 6acdd63e87714b6b0292788d7f1f39899119527a Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 3 Nov 2023 10:28:12 +0100 Subject: rockchip: ringneck-px30: always reset STM32 companion controller on boot It's happened that glitches on the STM32_RST and STM32_BOOT lines have put the STM32 companion microcontroller into DFU mode making it not boot its FW, rendering it useless for the user. Considering that the STM32 companion microcontroller is always reset on a reboot or power cycle, resetting it once again in U-Boot SPL isn't going to hurt it any more. For ATtiny companion microcontroller, the situation is a bit different because a reboot or power cycle doesn't reset it. Additionally, since it can only be reset with a UPDI reset on the STM32_RST line, and that is virtually impossible to mistakenly trigger, the ATtiny is unlikely to be in unwanted reset or enter reset because U-Boot toggles STM32_RST line. Cc: Quentin Schulz Signed-off-by: Quentin Schulz Reviewed-by: Heiko Stuebner Reviewed-by: Kever Yang --- .../ringneck_px30/ringneck-px30.c | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) (limited to 'board') diff --git a/board/theobroma-systems/ringneck_px30/ringneck-px30.c b/board/theobroma-systems/ringneck_px30/ringneck-px30.c index bb1bb4acf5c..537ce0d1d11 100644 --- a/board/theobroma-systems/ringneck_px30/ringneck-px30.c +++ b/board/theobroma-systems/ringneck_px30/ringneck-px30.c @@ -16,12 +16,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include #include @@ -169,3 +171,54 @@ int misc_init_r(void) return 0; } + +#define STM32_RST 100 /* GPIO3_A4 */ +#define STM32_BOOT 101 /* GPIO3_A5 */ + +void spl_board_init(void) +{ + /* + * Glitches on STM32_BOOT and STM32_RST lines during poweroff or power + * on may put the STM32 companion microcontroller into DFU mode, let's + * always reset it into normal mode instead. + * Toggling the STM32_RST line is safe to do with the ATtiny companion + * microcontroller variant because it will not trigger an MCU reset + * since only a UPDI reset command will. Since a UPDI reset is difficult + * to mistakenly trigger, glitches to the lines are theoretically also + * incapable of triggering an actual ATtiny reset. + */ + int ret; + + ret = gpio_request(STM32_RST, "STM32_RST"); + if (ret) { + debug("Failed to request STM32_RST\n"); + return; + } + + ret = gpio_request(STM32_BOOT, "STM32_BOOT"); + if (ret) { + debug("Failed to request STM32_BOOT\n"); + return; + } + + /* Rely on HW pull-down for inactive level */ + ret = gpio_direction_input(STM32_BOOT); + if (ret) { + debug("Failed to configure STM32_BOOT as input\n"); + return; + } + + ret = gpio_direction_output(STM32_RST, 0); + if (ret) { + debug("Failed to configure STM32_RST as output low\n"); + return; + } + + mdelay(1); + + ret = gpio_direction_output(STM32_RST, 1); + if (ret) { + debug("Failed to configure STM32_RST as output high\n"); + return; + } +} -- cgit v1.3.1