From a7e2dc9cf69538e0c75e7ab4d54d00b2edce64eb Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:04 +0100 Subject: imx6: remove aristainetos board remove not anymore used aristainetos board. Signed-off-by: Heiko Schocher --- configs/aristainetos_defconfig | 69 ------------------------------------------ 1 file changed, 69 deletions(-) delete mode 100644 configs/aristainetos_defconfig (limited to 'configs') diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig deleted file mode 100644 index 466205b96c1..00000000000 --- a/configs/aristainetos_defconfig +++ /dev/null @@ -1,69 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_TARGET_ARISTAINETOS=y -CONFIG_ENV_SIZE=0x3000 -CONFIG_ENV_OFFSET=0xD0000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL" -CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_UBI=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_OFFSET_REDUND=0xE0000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_BUS=3 -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ8XXX=y -CONFIG_MII=y -CONFIG_PWM_IMX=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO_IPUV3=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_IMX_WATCHDOG=y -CONFIG_OF_LIBFDT=y -- cgit v1.3.1 From 3882e6fc019697f511d644261ed2d827c1417480 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:06 +0100 Subject: imx6: aristainetos: move defines to Kconfig move defines, which are already moved to Kconfig out of board config. Signed-off-by: Heiko Schocher --- arch/arm/mach-imx/mx6/Kconfig | 9 +++++++++ board/aristainetos/Kconfig | 15 +++++++++++++- board/aristainetos/common/Kconfig | 38 +++++++++++++++++++++++++++++++++++ configs/aristainetos2_defconfig | 11 ++++++---- configs/aristainetos2b_defconfig | 2 +- include/configs/aristainetos-common.h | 10 --------- include/configs/aristainetos2.h | 4 ---- include/configs/aristainetos2b.h | 4 ---- 8 files changed, 69 insertions(+), 24 deletions(-) create mode 100644 board/aristainetos/common/Kconfig (limited to 'configs') diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 05ca45d2d2d..962409146b5 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -128,10 +128,19 @@ config TARGET_APALIS_IMX6 config TARGET_ARISTAINETOS2 bool "aristainetos2" select BOARD_LATE_INIT + select MX6DL + select SYS_I2C_MXC + select MXC_UART + select FEC_MXC + imply CMD_SATA config TARGET_ARISTAINETOS2B bool "Support aristainetos2-revB" select BOARD_LATE_INIT + select MX6DL + select SYS_I2C_MXC + select MXC_UART + select FEC_MXC config TARGET_CGTQMX6EVAL bool "cgtqmx6eval" diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index 0341bdfb283..60ad69fa5bc 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -1,19 +1,32 @@ if TARGET_ARISTAINETOS2 +source "board/aristainetos/common/Kconfig" + config SYS_BOARD default "aristainetos" -config SYS_CONFIG_NAME +config SYS_BOARD_VERSION + default 2 + +config BOARDNAME default "aristainetos2" endif if TARGET_ARISTAINETOS2B +source "board/aristainetos/common/Kconfig" + config SYS_BOARD default "aristainetos" config SYS_CONFIG_NAME default "aristainetos2b" +config SYS_BOARD_VERSION + default 3 + +config BOARDNAME + default "aristainetos2-revB" + endif diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig new file mode 100644 index 00000000000..53a3f4d5527 --- /dev/null +++ b/board/aristainetos/common/Kconfig @@ -0,0 +1,38 @@ +config BOARDNAME + string "name of the board" + help + set the name of the board. + +config SYS_BOARD_VERSION + int "select version of aristainetos board" + help + version of aristainetos board version + 2 version 2 + 3 version 2b + +config SYS_I2C_MXC_I2C1 + default y + +config SYS_I2C_MXC_I2C2 + default y + +config SYS_I2C_MXC_I2C3 + default y + +config SYS_I2C_MXC_I2C4 + default y + +config SYS_MALLOC_LEN + default 0x4000000 + +config ENV_SIZE + default 0x3000 + +config ENV_SECT_SIZE + default 0x10000 + +config ENV_OFFSET + default 0xd0000 + +config SYS_CONFIG_NAME + default "aristainetos2" diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index c548c0e423f..bc18786993e 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -7,7 +7,7 @@ CONFIG_ENV_OFFSET=0xD0000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -17,12 +17,16 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_SF=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -45,7 +49,6 @@ CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_MXS=y -CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=3 CONFIG_SF_DEFAULT_CS=1 CONFIG_SF_DEFAULT_MODE=0 @@ -67,4 +70,4 @@ CONFIG_VIDEO_IPUV3=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_IMX_WATCHDOG=y -CONFIG_OF_LIBFDT=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig index 26082bf4040..28bf87eac75 100644 --- a/configs/aristainetos2b_defconfig +++ b/configs/aristainetos2b_defconfig @@ -7,7 +7,7 @@ CONFIG_ENV_OFFSET=0xD0000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index 1d84db50983..ab14a1a3920 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -17,15 +17,9 @@ #define CONFIG_MACH_TYPE 4501 #define CONFIG_MMCROOT "/dev/mmcblk0p1" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M) - -#define CONFIG_MXC_UART - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_FEC_MXC #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 0 @@ -151,10 +145,6 @@ /* I2C */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 0x7f #define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} } diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index d8858559d8a..01998f02952 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -11,9 +11,7 @@ #ifndef __ARISTAINETOS2_CONFIG_H #define __ARISTAINETOS2_CONFIG_H -#define CONFIG_SYS_BOARD_VERSION 2 #define CONFIG_HOSTNAME "aristainetos2" -#define CONFIG_BOARDNAME "aristainetos2" #define CONFIG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV "ttymxc1" @@ -33,8 +31,6 @@ "ubifsload ${fit_addr_r} /boot/system.itb; " \ "imi ${fit_addr_r}\0 " -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ - #define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15) #define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(1, 0) #define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15) diff --git a/include/configs/aristainetos2b.h b/include/configs/aristainetos2b.h index cdeb7a3b032..a7ba48e3156 100644 --- a/include/configs/aristainetos2b.h +++ b/include/configs/aristainetos2b.h @@ -11,9 +11,7 @@ #ifndef __ARISTAINETOS2B_CONFIG_H #define __ARISTAINETOS2B_CONFIG_H -#define CONFIG_SYS_BOARD_VERSION 3 #define CONFIG_HOSTNAME "aristainetos2" -#define CONFIG_BOARDNAME "aristainetos2-revB" #define CONFIG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV "ttymxc1" @@ -33,8 +31,6 @@ "ubifsload ${fit_addr_r} /boot/system.itb; " \ "imi ${fit_addr_r}\0 " \ -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ - #define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15) #define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(1, 0) #define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15) -- cgit v1.3.1 From 1b857f1a92799ded10ea230ee96b6acb3285b562 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:07 +0100 Subject: imx6: aristainetos: remove 2b version remove 2b version of aristainetos board, as it is easier to make the DM / DTS port and introduce the 2b board version again (also some more board version). Signed-off-by: Heiko Schocher --- arch/arm/mach-imx/mx6/Kconfig | 8 ----- board/aristainetos/Kconfig | 18 ----------- board/aristainetos/MAINTAINERS | 1 - board/aristainetos/common/Kconfig | 1 - configs/aristainetos2b_defconfig | 68 --------------------------------------- include/configs/aristainetos2b.h | 46 -------------------------- 6 files changed, 142 deletions(-) delete mode 100644 configs/aristainetos2b_defconfig delete mode 100644 include/configs/aristainetos2b.h (limited to 'configs') diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 962409146b5..c78e91968b8 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -134,14 +134,6 @@ config TARGET_ARISTAINETOS2 select FEC_MXC imply CMD_SATA -config TARGET_ARISTAINETOS2B - bool "Support aristainetos2-revB" - select BOARD_LATE_INIT - select MX6DL - select SYS_I2C_MXC - select MXC_UART - select FEC_MXC - config TARGET_CGTQMX6EVAL bool "cgtqmx6eval" select BOARD_LATE_INIT diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index 60ad69fa5bc..2bb12fce755 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -12,21 +12,3 @@ config BOARDNAME default "aristainetos2" endif - -if TARGET_ARISTAINETOS2B - -source "board/aristainetos/common/Kconfig" - -config SYS_BOARD - default "aristainetos" - -config SYS_CONFIG_NAME - default "aristainetos2b" - -config SYS_BOARD_VERSION - default 3 - -config BOARDNAME - default "aristainetos2-revB" - -endif diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index c9e05285dfa..7e9f38d174a 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -4,4 +4,3 @@ S: Maintained F: board/aristainetos/ F: include/configs/aristainetos2.h F: configs/aristainetos2_defconfig -F: configs/aristainetos2b_defconfig diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig index 53a3f4d5527..16c13258891 100644 --- a/board/aristainetos/common/Kconfig +++ b/board/aristainetos/common/Kconfig @@ -8,7 +8,6 @@ config SYS_BOARD_VERSION help version of aristainetos board version 2 version 2 - 3 version 2b config SYS_I2C_MXC_I2C1 default y diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig deleted file mode 100644 index 28bf87eac75..00000000000 --- a/configs/aristainetos2b_defconfig +++ /dev/null @@ -1,68 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_TARGET_ARISTAINETOS2B=y -CONFIG_ENV_SIZE=0x3000 -CONFIG_ENV_OFFSET=0xD0000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" -CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_UBI=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_OFFSET_REDUND=0xE0000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_MII=y -CONFIG_PWM_IMX=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO_IPUV3=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_IMX_WATCHDOG=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/aristainetos2b.h b/include/configs/aristainetos2b.h deleted file mode 100644 index a7ba48e3156..00000000000 --- a/include/configs/aristainetos2b.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6DL aristainetos2 board. - */ -#ifndef __ARISTAINETOS2B_CONFIG_H -#define __ARISTAINETOS2B_CONFIG_H - -#define CONFIG_HOSTNAME "aristainetos2" - -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" - -#define CONFIG_FEC_XCV_TYPE RGMII - -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "board_type=aristainetos2_7@1\0" \ - "nor_bootdelay=-2\0" \ - "mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \ - "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ - "-(rescue-system);gpmi-nand:-(ubi)\0" \ - "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0\0" \ - "ubiargs=setenv bootargs console=${console},${baudrate} " \ - "ubi.mtd=0,4096 root=ubi0:rootfs rootfstype=ubifs\0 " \ - "ubifs_load_fit=sf probe;ubi part ubi 4096;ubifsmount ubi:rootfs;" \ - "ubifsload ${fit_addr_r} /boot/system.itb; " \ - "imi ${fit_addr_r}\0 " \ - -#define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15) -#define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(1, 0) -#define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15) - -/* Framebuffer */ -#define CONFIG_SYS_LDB_CLOCK 33246000 -#define CONFIG_LG4573 -#define CONFIG_LG4573_BUS 0 -#define CONFIG_LG4573_CS 1 - -#include "aristainetos-common.h" - -#endif /* __ARISTAINETOS2B_CONFIG_H */ -- cgit v1.3.1 From a053c8baad3cfed1a14d05421bde37651f5e903a Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:10 +0100 Subject: imx6: aristainetos: add thumb build add thumb build to aristainetos build to save binary space. Signed-off-by: Heiko Schocher --- configs/aristainetos2_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'configs') diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index bc18786993e..eda05a4618d 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_TARGET_ARISTAINETOS2=y -- cgit v1.3.1 From ccc7595a811c7ab52c7daebcf728b1c3cf0da4ad Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:12 +0100 Subject: imx6: aristainetos: prepare dts for other board versions as we switch to support DM and DTS, rework the existing DTS trees. Change also Linux specific Device trees, goal is to push this changes to linux. Collect U-Boot specific changes in separate "*u-boot*" dts files. Signed-off-by: Heiko Schocher --- arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi | 13 + arch/arm/dts/imx6dl-aristainetos2_4.dts | 79 +--- arch/arm/dts/imx6dl-aristainetos2_4.dtsi | 84 ++++ arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi | 19 + arch/arm/dts/imx6dl-aristainetos2_7.dts | 50 +-- arch/arm/dts/imx6dl-aristainetos2_7.dtsi | 58 +++ arch/arm/dts/imx6qdl-aristainetos2-common.dtsi | 492 ++++++++++++++++++++++++ arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi | 101 +++++ arch/arm/dts/imx6qdl-aristainetos2.dtsi | 487 +++-------------------- board/aristainetos/MAINTAINERS | 10 +- board/aristainetos/aristainetos.c | 68 ++++ configs/aristainetos2_defconfig | 7 + 12 files changed, 914 insertions(+), 554 deletions(-) create mode 100644 arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2_4.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2_7.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2-common.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi (limited to 'configs') diff --git a/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi new file mode 100644 index 00000000000..ac7052c7b76 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Heiko Schocher + */ + +#include + +&lcd_panel { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_4.dts b/arch/arm/dts/imx6dl-aristainetos2_4.dts index 0e28a70e788..0157e244ae4 100644 --- a/arch/arm/dts/imx6dl-aristainetos2_4.dts +++ b/arch/arm/dts/imx6dl-aristainetos2_4.dts @@ -1,46 +1,21 @@ // SPDX-License-Identifier: (GPL-2.0) /* * support for the imx6 based aristainetos2 board + * parts for 4.3 inch LG display on spi1 port0 * * Copyright (C) 2019 Heiko Schocher * Copyright (C) 2015 Heiko Schocher * */ /dts-v1/; -#include "imx6dl.dtsi" + +#include "imx6dl-aristainetos2_4.dtsi" #include "imx6qdl-aristainetos2.dtsi" / { model = "aristainetos2 i.MX6 Dual Lite Board 4"; compatible = "fsl,imx6dl"; - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - display0: disp0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - - port@0 { - reg = <0>; - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; }; &ecspi1 { @@ -74,51 +49,3 @@ }; }; }; - -&i2c3 { - touch: touch@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpio2>; - interrupts = <9 8>; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&iomuxc { - pinctrl_ipu_disp: ipudisp1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xE1 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xE1 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xE1 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xE1 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xE1 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xE1 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xE1 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xE1 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xE1 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xE1 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xE1 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xE1 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xE1 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xE1 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xE1 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xE1 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xE1 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xE1 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xE1 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xE1 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xE1 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xE1 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xE1 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xE1 - >; - }; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_4.dtsi b/arch/arm/dts/imx6dl-aristainetos2_4.dtsi new file mode 100644 index 00000000000..be4601b4b2b --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2_4.dtsi @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2 board + * parts for 4.3 inch LG display on the parallel port and atmel maxtouch + * + * Copyright (C) 2019 Heiko Schocher + * Copyright (C) 2015 Heiko Schocher + * + */ +/dts-v1/; +#include "imx6dl.dtsi" + +/ { + display0: disp0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + + port@0 { + reg = <0>; + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&i2c3 { + touch: touch@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + interrupt-parent = <&gpio2>; + interrupts = <9 8>; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&iomuxc { + pinctrl_ipu_disp: ipudisp1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xE1 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xE1 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xE1 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xE1 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xE1 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xE1 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xE1 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xE1 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xE1 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xE1 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xE1 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xE1 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xE1 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xE1 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xE1 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xE1 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xE1 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xE1 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xE1 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xE1 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xE1 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xE1 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xE1 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xE1 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi new file mode 100644 index 00000000000..25bc562064b --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Heiko Schocher + */ + +#include +/ { + vdd_panel_reg: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "panel_regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&panel0 { + power-supply = <&vdd_panel_reg>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_7.dts b/arch/arm/dts/imx6dl-aristainetos2_7.dts index 320dbcffafc..0d1e83cb686 100644 --- a/arch/arm/dts/imx6dl-aristainetos2_7.dts +++ b/arch/arm/dts/imx6dl-aristainetos2_7.dts @@ -7,58 +7,10 @@ * */ /dts-v1/; -#include "imx6dl.dtsi" +#include "imx6dl-aristainetos2_7.dtsi" #include "imx6qdl-aristainetos2.dtsi" / { model = "aristainetos2 i.MX6 Dual Lite Board 7"; compatible = "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - panel: panel { - compatible = "lg,lb070wv8"; - backlight = <&backlight>; - enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&i2c3 { - touch: touch@4d { - compatible = "atmel,maxtouch"; - reg = <0x4d>; - interrupt-parent = <&gpio2>; - interrupts = <9 8>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&ipu1_di0_lvds0>; - }; - }; - - port@4 { - reg = <4>; - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; }; diff --git a/arch/arm/dts/imx6dl-aristainetos2_7.dtsi b/arch/arm/dts/imx6dl-aristainetos2_7.dtsi new file mode 100644 index 00000000000..52d6a517a7f --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2_7.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2 board + * parts for 7 inch LG display connected to the LVDS port and atmel maxtouch + * + * Copyright (C) 2019 Heiko Schocher + * Copyright (C) 2015 Heiko Schocher + * + */ +/dts-v1/; +#include + +#include "imx6dl.dtsi" + +/ { + panel0: panel_lg { + compatible = "lg,lb070wv8"; + backlight = <&backlight>; + enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&i2c3 { + touch: touch@4d { + compatible = "atmel,maxtouch"; + reg = <0x4d>; + interrupt-parent = <&gpio2>; + interrupts = <9 8>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&ipu1_di0_lvds0>; + }; + }; + + port@4 { + reg = <4>; + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi b/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi new file mode 100644 index 00000000000..2aa531b1ab7 --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi @@ -0,0 +1,492 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2 board + * parts common to all versions + * + * Copyright (C) 2019 Heiko Schocher + * Copyright (C) 2015 Heiko Schocher + * + */ +#include +#include + +/ { + aliases { + eeprom0 = &i2c_eeprom0; + pmic0 = &i2c_pmic0; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + enable-gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aristainetos2_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbotg_vbus: regulator-usbotg-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aristainetos2_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH &gpio2 27 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + i2c_pmic0: pmic@58 { + compatible = "dlg,da9063"; + /* the pmic uses addr 0x58 and 0x59 */ + reg = <0x58>; + interrupt-parent = <&gpio1>; + interrupts = <04 0x8>; + + regulators { + bcore1 { + regulator-name = "bcore1"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bcore2 { + regulator-name = "bcore2"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bpro { + regulator-name = "bpro"; + regulator-always-on = <1>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + bprob { + regulator-name = "bprob"; + regulator-always-on = <1>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + bperi { + regulator-name = "bperi"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bmem { + regulator-name = "bmem"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo2 { + regulator-name = "ldo2"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1800000>; + }; + + ldo3 { + regulator-name = "ldo3"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo4 { + regulator-name = "ldo4"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5 { + regulator-name = "ldo5"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6 { + regulator-name = "ldo6"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "ldo7"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo8 { + regulator-name = "ldo8"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo9 { + regulator-name = "ldo9"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo10 { + regulator-name = "ldo10"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo11 { + regulator-name = "ldo11"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bio { + regulator-name = "bio"; + regulator-always-on = <1>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + + tmp103: tmp103@71 { + compatible = "ti,tmp103"; + reg = <0x71>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + expander: tca6416@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + + env_reset { + gpio-hog; + input; + gpios = <6 GPIO_ACTIVE_LOW>; + }; + boot_rescue { + gpio-hog; + input; + gpios = <7 GPIO_ACTIVE_LOW>; + }; + }; + + rtc@68 { + compatible = "st,m41t11"; + reg = <0x68>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + i2c_eeprom0: eeprom@50{ + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + i2c_eeprom1: eeprom@57{ + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; +}; + +&gpio6 { + spi_bus_ena { + gpio-hog; + output-high; + gpios = <6 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio7 { + bootsel0 { + gpio-hog; + input; + gpios = <6 GPIO_ACTIVE_HIGH>; + }; + bootsel1 { + gpio-hog; + input; + gpios = <7 GPIO_ACTIVE_HIGH>; + }; + bootsel2 { + gpio-hog; + input; + gpios = <1 GPIO_ACTIVE_HIGH>; + }; + + soft_reset { + gpio-hog; + output-high; + gpios = <13 GPIO_ACTIVE_HIGH>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + status = "okay"; +}; + +&pcie { + reset-gpio = <&gpio2 16 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "host"; /* fixed configuration, ID pin not checked */ + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; + + pinctrl_audmux: audmux { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 /* SS0# */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 /* SS1# */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x400100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + /* make sure pin is GPIO and not ENET_REF_CLK */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1a0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 + /* backlight enable */ + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_aristainetos2_usbh1_vbus: aristainetos-usbh1-vbus { + fsl,pins = ; + }; + + pinctrl_aristainetos2_usbotg_vbus: aristainetos-usbotg-vbus { + fsl,pins = ; + }; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi new file mode 100644 index 00000000000..c713efd84c7 --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Heiko Schocher + */ + +/ { + chosen { + u-boot,dm-pre-reloc; + stdout-path = &uart2; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + }; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_gpio { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart2 { + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-pre-reloc; +}; + +&backlight { + pwms = <&pwm1 0 300000>; + default-brightness-level = <2>; +}; + +/* + * allow switching write protect pin by gpio, + * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot + */ +&gpio2 { + u-boot,dm-pre-reloc; + + wp_spi_nor { + gpio-hog; + output-high; + gpios = <15 GPIO_ACTIVE_HIGH>; + }; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_gpio &pinctrl_gpio_fix>; + u-boot,dm-pre-reloc; + + pinctrl_gpio_fix: gpiofixgrp { + /* + * usdhc2 has a levelshifter on the carrier board Rev. DV1, + * that will automatically detect the driving direction. + * During initialisation this isn't working correctly, + * which causes DAT3 to be driven low towards the SD-card. + * This causes a SD-card enetring the SPI-Mode + * and therefore getting inaccessible until next power cycle. + * As workaround we drive the DAT3 line as GPIO and set it high. + * This makes usdhc2 unusable in u-boot, but works for the + * initialisation in Linux + */ + fsl,pins = < + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x20000 + >; + }; +}; + +&gpio1 { + usdhc_fix { + gpio-hog; + output-high; + gpios = <12 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&gpio5 { + u-boot,dm-pre-reloc; +}; + +&ecspi4 { + u-boot,dm-pre-reloc; +}; + +&flash { + u-boot,dm-pre-reloc; +}; + +&pinctrl_ecspi4 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/dts/imx6qdl-aristainetos2.dtsi index da6ab63808d..788e13edad0 100644 --- a/arch/arm/dts/imx6qdl-aristainetos2.dtsi +++ b/arch/arm/dts/imx6qdl-aristainetos2.dtsi @@ -9,73 +9,43 @@ #include #include -/ { - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - enable-gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; +#include "imx6qdl-aristainetos2-common.dtsi" - reg_usbh1_vbus: regulator-usbh1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; +/ { + leds { + compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos2_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; + pinctrl-0 = <&pinctrl_gpio>; - reg_usbotg_vbus: regulator-usbotg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos2_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; + LED_blue { + label = "led_blue"; + gpios = <&gpio2 29 GPIO_ACTIVE_LOW>; + }; -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; + LED_green { + label = "led_green"; + gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + }; -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; + LED_red { + label = "led_red"; + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + }; -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; + LED_yellow { + label = "led_yellow"; + gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; + }; + + LED_ena { + label = "led_ena"; + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + }; + }; }; &ecspi1 { + fsl,spi-num-chipselects = <3>; cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH &gpio4 10 GPIO_ACTIVE_HIGH &gpio4 11 GPIO_ACTIVE_HIGH>; @@ -84,18 +54,13 @@ status = "okay"; }; -&ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH &gpio2 27 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - &ecspi4 { + fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi4>; status = "okay"; + pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; flash: m25p80@1 { #address-cells = <1>; @@ -106,245 +71,29 @@ }; }; -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio1>; - interrupts = <04 0x8>; - - regulators { - bcore1 { - regulator-name = "bcore1"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bcore2 { - regulator-name = "bcore2"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bpro { - regulator-name = "bpro"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bperi { - regulator-name = "bperi"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bmem { - regulator-name = "bmem"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2 { - regulator-name = "ldo2"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1800000>; - }; - - ldo3 { - regulator-name = "ldo3"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo4 { - regulator-name = "ldo4"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5 { - regulator-name = "ldo5"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo6 { - regulator-name = "ldo6"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "ldo7"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo8 { - regulator-name = "ldo8"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo9 { - regulator-name = "ldo9"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo10 { - regulator-name = "ldo10"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo11 { - regulator-name = "ldo11"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bio { - regulator-name = "bio"; - regulator-always-on = <1>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - - tmp103: tmp103@71 { - compatible = "ti,tmp103"; - reg = <0x71>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - expander: tca6416@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - #gpio-cells = <2>; - gpio-controller; - }; - - rtc@68 { - compatible = "dallas,m41t00"; - reg = <0x68>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - eeprom@50{ - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - eeprom@57{ - compatible = "atmel,24c64"; - reg = <0x57>; +&gpio7 { + sd2_driver_ena { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; }; }; -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_LOW>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - status = "okay"; -}; - &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; status = "okay"; }; -&pcie { - reset-gpio = <&gpio2 16 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { +&can1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - dr_mode = "host"; + pinctrl-0 = <&pinctrl_flexcan1>; status = "okay"; }; -&usbotg { - vbus-supply = <®_usbotg_vbus>; +&can2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "host"; + pinctrl-0 = <&pinctrl_flexcan2>; status = "okay"; }; @@ -366,18 +115,6 @@ }; &iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio>; - - pinctrl_audmux: audmux { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 - >; - }; - pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 @@ -389,16 +126,6 @@ >; }; - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 /* SS0# */ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 /* SS1# */ - >; - }; - pinctrl_ecspi4: ecspi4grp { fsl,pins = < MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 @@ -406,72 +133,40 @@ MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 /* WP pin */ >; }; pinctrl_gpio: gpiogrp { fsl,pins = < /* led enable */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 /* LCD power enable */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 /* led yellow */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 /* led red */ - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 /* led green */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 /* led blue */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 /* Profibus IRQ */ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - /* FPGA IRQ */ + /* FPGA IRQ currently unused*/ MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 + /* Display reset because of clock failure */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 /* spi bus #2 SS driver enable */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 /* RST_LOC# PHY reset input (has pull-down!)*/ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 /* USB_OTG_ID = GPIO1_24*/ - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x80000000 + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x4001b0b0 /* Touchscreen IRQ */ MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* PCIe reset */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b0 + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 >; }; @@ -495,71 +190,17 @@ >; }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 - /* backlight enable */ - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { + pinctrl_flexcan1: flexcan1grp { fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 >; }; - pinctrl_uart4: uart4grp { + pinctrl_flexcan2: flexcan2grp { fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 >; }; @@ -569,14 +210,6 @@ >; }; - pinctrl_aristainetos2_usbh1_vbus: aristainetos-usbh1-vbus { - fsl,pins = ; - }; - - pinctrl_aristainetos2_usbotg_vbus: aristainetos-usbotg-vbus { - fsl,pins = ; - }; - pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 @@ -601,7 +234,7 @@ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 /* SD2 level shifter output enable */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 /* SD2 card detect input */ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 /* SD2 write protect input */ diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index 91c8ae0738e..2495cd4a370 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -4,6 +4,12 @@ S: Maintained F: board/aristainetos/ F: include/configs/aristainetos2.h F: configs/aristainetos2_defconfig -F: arch/arm/dts/imx6dl-aristainetos2_4.dts -F: arch/arm/dts/imx6dl-aristainetos2_7.dts F: arch/arm/dts/imx6qdl-aristainetos2.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2_7.dts +F: arch/arm/dts/imx6dl-aristainetos2_7.dtsi +F: arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2_4.dts +F: arch/arm/dts/imx6dl-aristainetos2_4.dtsi +F: arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 11b64d08bea..b296ea25226 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include @@ -82,6 +83,14 @@ DECLARE_GLOBAL_DATA_PTR; #define SOFT_RESET_GPIO IMX_GPIO_NR(7, 13) #define SD2_DRIVER_ENABLE IMX_GPIO_NR(7, 8) +enum { + BOARD_TYPE_4 = 4, + BOARD_TYPE_7 = 7, +}; + +#define ARI_BT_4 "aristainetos2_4@2" +#define ARI_BT_7 "aristainetos2_7@1" + struct i2c_pads_info i2c_pad_info3 = { .scl = { .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, @@ -617,6 +626,7 @@ static void set_gpr_register(void) &iomuxc_regs->gpr[12]); } +extern char __bss_start[], __bss_end[]; int board_early_init_f(void) { setup_iomux_uart(); @@ -626,6 +636,14 @@ int board_early_init_f(void) gpio_direction_output(SD2_DRIVER_ENABLE, 1); setup_display(); set_gpr_register(); + + /* + * clear bss here, so we can use spi driver + * before relocation and read Environment + * from spi flash. + */ + memset(__bss_start, 0x00, __bss_end - __bss_start); + return 0; } @@ -704,6 +722,12 @@ int board_late_init(void) CONFIG_LG4573_CS, 10000000, SPI_MODE_0); + /* set board_type */ + if (gd->board_type == BOARD_TYPE_4) + env_set("board_type", ARI_BT_4); + else + env_set("board_type", ARI_BT_7); + return 0; } @@ -962,6 +986,50 @@ int board_ehci_power(int port, int on) gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on); else gpio_set_value(ARISTAINETOS_USB_H1_PWR, on); + + return 0; +} +#endif + +int board_fit_config_name_match(const char *name) +{ + if (gd->board_type == BOARD_TYPE_4 && + strchr(name, 0x34)) + return 0; + + if (gd->board_type == BOARD_TYPE_7 && + strchr(name, 0x37)) + return 0; + + return -1; +} + +static void do_board_detect(void) +{ + int ret; + char s[30]; + + /* default use board type 7 */ + gd->board_type = BOARD_TYPE_7; + if (env_init()) + return; + + ret = env_get_f("panel", s, sizeof(s)); + if (ret < 0) + return; + + if (!strncmp("lg4573", s, 6)) + gd->board_type = BOARD_TYPE_4; +} + +#ifdef CONFIG_DTB_RESELECT +int embedded_dtb_select(void) +{ + int rescan; + + do_board_detect(); + fdtdec_resetup(&rescan); + return 0; } #endif diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index eda05a4618d..564c8c46d76 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_TYPES=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -42,7 +43,13 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2_4" +CONFIG_OF_LIST="imx6dl-aristainetos2_4 imx6dl-aristainetos2_7" +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SPI_EARLY=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_OFFSET_REDUND=0xE0000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y -- cgit v1.3.1 From f44b4ab3c88c92f44cff39189a37fd2da0574fbf Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:13 +0100 Subject: imx6: aristainetos: add DM_SERIAL support add DM_SERIAL support for the aristainetos board, and remove not used code from board code. remove CONSOLE_OVERWRITE_ROUTINE. Signed-off-by: Heiko Schocher --- arch/arm/mach-imx/mx6/Kconfig | 2 ++ board/aristainetos/aristainetos.c | 60 --------------------------------------- configs/aristainetos2_defconfig | 3 +- 3 files changed, 4 insertions(+), 61 deletions(-) (limited to 'configs') diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index c78e91968b8..6bc7405a1ca 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -132,7 +132,9 @@ config TARGET_ARISTAINETOS2 select SYS_I2C_MXC select MXC_UART select FEC_MXC + select DM imply CMD_SATA + imply CMD_DM config TARGET_CGTQMX6EVAL bool "cgtqmx6eval" diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index b296ea25226..00ffac8eb64 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -43,10 +43,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) @@ -117,30 +113,6 @@ struct i2c_pads_info i2c_pad_info4 = { } }; -iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D19__UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D20__UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart3_pads[] = { - MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - iomux_v3_cfg_t const gpio_pads[] = { /* LED enable*/ MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -312,28 +284,6 @@ static void setup_spi(void) #endif } -static void setup_iomux_uart(void) -{ - switch (CONFIG_MXC_UART_BASE) { - case UART1_BASE: - imx_iomux_v3_setup_multiple_pads(uart1_pads, - ARRAY_SIZE(uart1_pads)); - break; - case UART2_BASE: - imx_iomux_v3_setup_multiple_pads(uart2_pads, - ARRAY_SIZE(uart2_pads)); - break; - case UART3_BASE: - imx_iomux_v3_setup_multiple_pads(uart3_pads, - ARRAY_SIZE(uart3_pads)); - break; - case UART4_BASE: - imx_iomux_v3_setup_multiple_pads(uart4_pads, - ARRAY_SIZE(uart4_pads)); - break; - } -} - int board_phy_config(struct phy_device *phydev) { /* control data pad skew - devaddr = 0x02, register = 0x04 */ @@ -629,7 +579,6 @@ static void set_gpr_register(void) extern char __bss_start[], __bss_end[]; int board_early_init_f(void) { - setup_iomux_uart(); setup_iomux_gpio(); gpio_direction_output(SOFT_RESET_GPIO, 1); @@ -808,15 +757,6 @@ int board_mmc_init(bd_t *bis) } #endif -/* - * Do not overwrite the console - * Use always serial for U-Boot console - */ -int overwrite_console(void) -{ - return 1; -} - struct display_info_t const displays[] = { { .bus = -1, diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 564c8c46d76..65702c09050 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SYS_MALLOC_F_LEN=0xe000 CONFIG_TARGET_ARISTAINETOS2=y CONFIG_ENV_SIZE=0x3000 CONFIG_ENV_OFFSET=0xD0000 @@ -12,7 +13,6 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_TYPES=y @@ -70,6 +70,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_MII=y CONFIG_PWM_IMX=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y -- cgit v1.3.1 From 8664c485d9ebccc827935242e3b952c43c5950db Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:14 +0100 Subject: imx6: aristainetos: convert to DM_MMC Enable DM_MMC support. Signed-off-by: Heiko Schocher --- board/aristainetos/aristainetos.c | 53 --------------------------------------- configs/aristainetos2_defconfig | 1 + include/configs/aristainetos2.h | 2 +- 3 files changed, 2 insertions(+), 54 deletions(-) (limited to 'configs') diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 00ffac8eb64..6de71a46ede 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -19,8 +19,6 @@ #include #include #include -#include -#include #include #include #include @@ -43,10 +41,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) @@ -63,9 +57,6 @@ DECLARE_GLOBAL_DATA_PTR; #define ECSPI4_CS1 IMX_GPIO_NR(5, 2) -#define USDHC2_PAD_CTRL (PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - #if (CONFIG_SYS_BOARD_VERSION == 2) /* 4.3 display controller */ #define ECSPI1_CS0 IMX_GPIO_NR(4, 9) @@ -706,15 +697,6 @@ struct i2c_pads_info i2c_pad_info2 = { } }; -iomux_v3_cfg_t const usdhc1_pads[] = { - MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -722,41 +704,6 @@ int dram_init(void) return 0; } -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC1_BASE_ADDR}, - {USDHC2_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - return 1; -} - -int board_mmc_init(bd_t *bis) -{ - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); -#if (CONFIG_SYS_BOARD_VERSION == 2) - /* - * usdhc2 has a levelshifter on the carrier board Rev. DV1, - * that will automatically detect the driving direction. - * During initialisation this isn't working correctly, - * which causes DAT3 to be driven low towards the SD-card. - * This causes a SD-card enetring the SPI-Mode - * and therefore getting inaccessible until next power cycle. - * As workaround we drive the DAT3 line as GPIO and set it high. - * This makes usdhc2 unusable in u-boot, but works for the - * initialisation in Linux - */ - imx_iomux_v3_setup_pad(MX6_PAD_SD2_DAT3__GPIO1_IO12 | - MUX_PAD_CTRL(NO_PAD_CTRL)); - gpio_direction_output(IMX_GPIO_NR(1, 12) , 1); -#endif - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} -#endif - struct display_info_t const displays[] = { { .bus = -1, diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 65702c09050..52c28d977d6 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -53,6 +53,7 @@ CONFIG_ENV_SPI_EARLY=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_OFFSET_REDUND=0xE0000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 9291cfdffde..b008928c064 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -45,7 +45,7 @@ #define CONFIG_MMCROOT "/dev/mmcblk0p1" /* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_ETHPRIME "FEC" -- cgit v1.3.1 From fc7e3cc639c28e0e86af633e6f63902809e975dd Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:15 +0100 Subject: imx6: aristainetos: convert gpio pins to DM and DTS Enable DM_GPIO, GPIO_HOG, LED and LED_GPIO as gpio and LEDs are now defined in DTS. Enable also here the pinctrl driver, so pinmux setup is also done. Signed-off-by: Heiko Schocher --- board/aristainetos/aristainetos.c | 134 +++++++++++++++----------------------- configs/aristainetos2_defconfig | 8 +++ 2 files changed, 61 insertions(+), 81 deletions(-) (limited to 'configs') diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 6de71a46ede..5639eefa15c 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -38,6 +38,7 @@ #if defined(CONFIG_VIDEO_BMP_LOGO) #include #endif +#include DECLARE_GLOBAL_DATA_PTR; @@ -67,9 +68,6 @@ DECLARE_GLOBAL_DATA_PTR; #define ECSPI1_CS1 IMX_GPIO_NR(4, 10) #endif -#define SOFT_RESET_GPIO IMX_GPIO_NR(7, 13) -#define SD2_DRIVER_ENABLE IMX_GPIO_NR(7, 8) - enum { BOARD_TYPE_4 = 4, BOARD_TYPE_7 = 7, @@ -104,43 +102,6 @@ struct i2c_pads_info i2c_pad_info4 = { } }; -iomux_v3_cfg_t const gpio_pads[] = { - /* LED enable*/ - MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* LED yellow */ - MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* LED red */ -#if (CONFIG_SYS_BOARD_VERSION == 2) - MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), -#elif (CONFIG_SYS_BOARD_VERSION == 3) - MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), -#endif - /* LED green */ - MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* LED blue */ - MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* spi flash WP protect */ - MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* spi CS 0 */ - MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* spi bus #2 SS driver enable */ - MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* RST_LOC# PHY reset input (has pull-down!)*/ - MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* SD 2 level shifter output enable */ - MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* SD1 card detect input */ - MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* SD1 write protect input */ - MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* SD2 card detect input */ - MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* SD2 write protect input */ - MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* Touchscreen IRQ */ - MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - static iomux_v3_cfg_t const misc_pads[] = { /* USB_OTG_ID = GPIO1_24*/ MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -265,12 +226,16 @@ static void setup_spi(void) for (i = 0; i < 4; i++) enable_spi_clk(true, i); + gpio_request(ECSPI1_CS0, "spi1_cs0"); gpio_direction_output(ECSPI1_CS0, 1); #if (CONFIG_SYS_BOARD_VERSION == 2) + gpio_request(ECSPI4_CS1, "spi4_cs1"); gpio_direction_output(ECSPI4_CS1, 0); /* set cs0 to high (second device on spi bus #4) */ + gpio_request(ECSPI4_CS0, "spi4_cs0"); gpio_direction_output(ECSPI4_CS0, 1); #elif (CONFIG_SYS_BOARD_VERSION == 3) + gpio_request(ECSPI1_CS1, "spi1_cs1"); gpio_direction_output(ECSPI1_CS1, 1); #endif } @@ -359,9 +324,13 @@ static void enable_display_power(void) ARRAY_SIZE(backlight_pads)); /* backlight enable */ + gpio_request(IMX_GPIO_NR(6, 31), "backlight"); gpio_direction_output(IMX_GPIO_NR(6, 31), 1); + gpio_free(IMX_GPIO_NR(6, 31)); /* LCD power enable */ + gpio_request(IMX_GPIO_NR(6, 15), "LCD_power_enable"); gpio_direction_output(IMX_GPIO_NR(6, 15), 1); + gpio_free(IMX_GPIO_NR(6, 15)); /* enable backlight PWM 1 */ if (pwm_init(0, 0, 0)) @@ -547,11 +516,6 @@ static void setup_display(void) enable_display_power(); } -static void setup_iomux_gpio(void) -{ - imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); -} - static void set_gpr_register(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -570,10 +534,6 @@ static void set_gpr_register(void) extern char __bss_start[], __bss_end[]; int board_early_init_f(void) { - setup_iomux_gpio(); - - gpio_direction_output(SOFT_RESET_GPIO, 1); - gpio_direction_output(SD2_DRIVER_ENABLE, 1); setup_display(); set_gpr_register(); @@ -593,37 +553,30 @@ static void setup_i2c4(void) &i2c_pad_info4); } -static void setup_board_gpio(void) +static void setup_one_led(char *label, int state) { - /* enable all LEDs */ - gpio_request(IMX_GPIO_NR(2, 13), "LED ena"); /* 25 */ - gpio_direction_output(IMX_GPIO_NR(1, 25), 0); + struct udevice *dev; + int ret; + ret = led_get_by_label(label, &dev); + if (ret == 0) + led_set_state(dev, state); +} + +static void setup_board_gpio(void) +{ + setup_one_led("led_ena", LEDST_ON); /* switch off Status LEDs */ -#if (CONFIG_SYS_BOARD_VERSION == 2) - gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */ - gpio_direction_output(IMX_GPIO_NR(6, 16), 1); - gpio_request(IMX_GPIO_NR(2, 28), "LED red"); /* 60 */ - gpio_direction_output(IMX_GPIO_NR(2, 28), 1); - gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */ - gpio_direction_output(IMX_GPIO_NR(5, 4), 1); - gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */ - gpio_direction_output(IMX_GPIO_NR(2, 29), 1); -#elif (CONFIG_SYS_BOARD_VERSION == 3) - gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */ - gpio_direction_output(IMX_GPIO_NR(6, 16), 0); - gpio_request(IMX_GPIO_NR(5, 0), "LED red"); /* 128 */ - gpio_direction_output(IMX_GPIO_NR(5, 0), 0); - gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */ - gpio_direction_output(IMX_GPIO_NR(5, 4), 0); - gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */ - gpio_direction_output(IMX_GPIO_NR(2, 29), 0); -#endif + setup_one_led("led_yellow", LEDST_OFF); + setup_one_led("led_red", LEDST_OFF); + setup_one_led("led_green", LEDST_OFF); + setup_one_led("led_blue", LEDST_OFF); } static void setup_board_spi(void) { /* enable spi bus #2 SS drivers (and spi bus #4 SS1 for rev2b) */ + gpio_request(IMX_GPIO_NR(6, 6), "spi_ena"); gpio_direction_output(IMX_GPIO_NR(6, 6), 1); } @@ -632,20 +585,23 @@ int board_late_init(void) char *my_bootdelay; char bootmode = 0; char const *panel = env_get("panel"); + struct gpio_desc *desc; + int ret; + led_default_state(); /* * Check the boot-source. If booting from NOR Flash, * disable bootdelay */ - gpio_request(IMX_GPIO_NR(7, 6), "bootsel0"); - gpio_direction_input(IMX_GPIO_NR(7, 6)); - gpio_request(IMX_GPIO_NR(7, 7), "bootsel1"); - gpio_direction_input(IMX_GPIO_NR(7, 7)); - gpio_request(IMX_GPIO_NR(7, 1), "bootsel2"); - gpio_direction_input(IMX_GPIO_NR(7, 1)); - bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 6)) ? 1 : 0) << 0; - bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 7)) ? 1 : 0) << 1; - bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 1)) ? 1 : 0) << 2; + desc = gpio_hog_lookup_name("bootsel0"); + if (desc) + bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0; + desc = gpio_hog_lookup_name("bootsel1"); + if (desc) + bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1; + desc = gpio_hog_lookup_name("bootsel2"); + if (desc) + bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2; if (bootmode == 7) { my_bootdelay = env_get("nor_bootdelay"); @@ -655,6 +611,22 @@ int board_late_init(void) env_set("bootdelay", "-2"); } + /* read out some jumper values*/ + ret = gpio_hog_lookup_name("env_reset", &desc); + if (!ret) { + if (dm_gpio_get_value(desc)) { + printf("\nClear env (set back to defaults)\n"); + run_command("run default_env; saveenv; saveenv", 0); + } + } + ret = gpio_hog_lookup_name("boot_rescue", &desc); + if (!ret) { + if (dm_gpio_get_value(desc)) { + aristainetos_run_rescue_command(16); + run_command("run rescue_xload_boot", 0); + } + } + /* if we have the lg panel, we can initialze it now */ if (panel) if (!strcmp(panel, displays[1].mode.name)) diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 52c28d977d6..3d36f38e772 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y +# CONFIG_CMD_PINMUX is not set # CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y @@ -53,6 +54,11 @@ CONFIG_ENV_SPI_EARLY=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_OFFSET_REDUND=0xE0000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_GPIO=y +CONFIG_GPIO_HOG=y +CONFIG_DM_PCA953X=y +CONFIG_LED=y +CONFIG_LED_GPIO=y CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -70,6 +76,8 @@ CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y CONFIG_PWM_IMX=y CONFIG_DM_SERIAL=y CONFIG_SPI=y -- cgit v1.3.1 From 64679e2c80bb6002f85682af66a972cf8a20414c Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:16 +0100 Subject: imx6: aristainetos: convert to DM_USB Drop CONFIG_USB_MAX_CONTROLLER_COUNT and enable DM_USB in defconfig. Signed-off-by: Heiko Schocher --- board/aristainetos/aristainetos.c | 35 ----------------------------------- configs/aristainetos2_defconfig | 4 ++++ include/configs/aristainetos2.h | 3 --- 3 files changed, 4 insertions(+), 38 deletions(-) (limited to 'configs') diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 5639eefa15c..c2218cb5c26 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -102,15 +102,6 @@ struct i2c_pads_info i2c_pad_info4 = { } }; -static iomux_v3_cfg_t const misc_pads[] = { - /* USB_OTG_ID = GPIO1_24*/ - MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), - /* H1 Power enable = GPIO1_0*/ - MX6_PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - /* OTG Power enable = GPIO4_15*/ - MX6_PAD_KEY_ROW4__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), @@ -815,7 +806,6 @@ int board_init(void) /* GPIO_1 for USB_OTG_ID */ clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0); - imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); return 0; } @@ -825,31 +815,6 @@ int checkboard(void) return 0; } -#ifdef CONFIG_USB_EHCI_MX6 -int board_ehci_hcd_init(int port) -{ - int ret; - - ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr"); - if (!ret) - gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1); - ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr"); - if (!ret) - gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1); - return 0; -} - -int board_ehci_power(int port, int on) -{ - if (port) - gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on); - else - gpio_set_value(ARISTAINETOS_USB_H1_PWR, on); - - return 0; -} -#endif - int board_fit_config_name_match(const char *name) { if (gd->board_type == BOARD_TYPE_4 && diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 3d36f38e772..ea60e17804a 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -78,11 +78,15 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_IMX=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO_IPUV3=y CONFIG_VIDEO=y diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index b008928c064..269162eabfe 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -31,8 +31,6 @@ "ubifsload ${fit_addr_r} /boot/system.itb; " \ "imi ${fit_addr_r}\0 " -#define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15) -#define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(1, 0) #define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15) /* Framebuffer */ @@ -189,7 +187,6 @@ #define CONFIG_RTC_M41T11 /* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -- cgit v1.3.1 From cf8cbb0709e8556dc7f5b40ec8f2df3fce95938e Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:17 +0100 Subject: imx6: aristainetos: convert CONFIG_DM_SPI enable CONFIG_DM_SPI and CONFIG_DM_SPI_FLASH and get rid of build removal warnings. define CONFIG_GPIO_ENABLE_SPI_FLASH is not longer needed, so remove it from config_whitelist.txt Signed-off-by: Heiko Schocher --- board/aristainetos/aristainetos.c | 97 --------------------------------------- configs/aristainetos2_defconfig | 2 + include/configs/aristainetos2.h | 2 - scripts/config_whitelist.txt | 1 - 4 files changed, 2 insertions(+), 100 deletions(-) (limited to 'configs') diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index c2218cb5c26..5bb238b073c 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include <../drivers/video/imx/ipu.h> #if defined(CONFIG_VIDEO_BMP_LOGO) @@ -45,9 +44,6 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) @@ -56,18 +52,6 @@ DECLARE_GLOBAL_DATA_PTR; #define DISP_PAD_CTRL (0x10) -#define ECSPI4_CS1 IMX_GPIO_NR(5, 2) - -#if (CONFIG_SYS_BOARD_VERSION == 2) - /* 4.3 display controller */ - #define ECSPI1_CS0 IMX_GPIO_NR(4, 9) - #define ECSPI4_CS0 IMX_GPIO_NR(3, 29) -#elif (CONFIG_SYS_BOARD_VERSION == 3) - #define ECSPI1_CS0 IMX_GPIO_NR(2, 30) /* NOR flash */ - /* 4.3 display controller */ - #define ECSPI1_CS1 IMX_GPIO_NR(4, 10) -#endif - enum { BOARD_TYPE_4 = 4, BOARD_TYPE_7 = 7, @@ -129,33 +113,11 @@ static iomux_v3_cfg_t const backlight_pads[] = { MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -static iomux_v3_cfg_t const ecspi1_pads[] = { - MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), -#if (CONFIG_SYS_BOARD_VERSION == 2) - MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(SPI_PAD_CTRL), -#elif (CONFIG_SYS_BOARD_VERSION == 3) - MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), -#endif -}; - static void setup_iomux_enet(void) { imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); } -#if (CONFIG_SYS_BOARD_VERSION == 2) -iomux_v3_cfg_t const ecspi4_pads[] = { - MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; -#endif - static iomux_v3_cfg_t const display_pads[] = { MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL), MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, @@ -187,50 +149,6 @@ static iomux_v3_cfg_t const display_pads[] = { MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, }; -int board_spi_cs_gpio(unsigned int bus, unsigned int cs) -{ - if (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS) -#if (CONFIG_SYS_BOARD_VERSION == 2) - return IMX_GPIO_NR(5, 2); - - if (bus == 0 && cs == 0) - return IMX_GPIO_NR(4, 9); -#elif (CONFIG_SYS_BOARD_VERSION == 3) - return ECSPI1_CS0; - - if (bus == 0 && cs == 1) - return ECSPI1_CS1; -#endif - return -1; -} - -static void setup_spi(void) -{ - int i; - - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); - -#if (CONFIG_SYS_BOARD_VERSION == 2) - imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads)); -#endif - - for (i = 0; i < 4; i++) - enable_spi_clk(true, i); - - gpio_request(ECSPI1_CS0, "spi1_cs0"); - gpio_direction_output(ECSPI1_CS0, 1); -#if (CONFIG_SYS_BOARD_VERSION == 2) - gpio_request(ECSPI4_CS1, "spi4_cs1"); - gpio_direction_output(ECSPI4_CS1, 0); - /* set cs0 to high (second device on spi bus #4) */ - gpio_request(ECSPI4_CS0, "spi4_cs0"); - gpio_direction_output(ECSPI4_CS0, 1); -#elif (CONFIG_SYS_BOARD_VERSION == 3) - gpio_request(ECSPI1_CS1, "spi1_cs1"); - gpio_direction_output(ECSPI1_CS1, 1); -#endif -} - int board_phy_config(struct phy_device *phydev) { /* control data pad skew - devaddr = 0x02, register = 0x04 */ @@ -564,13 +482,6 @@ static void setup_board_gpio(void) setup_one_led("led_blue", LEDST_OFF); } -static void setup_board_spi(void) -{ - /* enable spi bus #2 SS drivers (and spi bus #4 SS1 for rev2b) */ - gpio_request(IMX_GPIO_NR(6, 6), "spi_ena"); - gpio_direction_output(IMX_GPIO_NR(6, 6), 1); -} - int board_late_init(void) { char *my_bootdelay; @@ -785,8 +696,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - setup_spi(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, &i2c_pad_info1); setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, @@ -795,14 +704,8 @@ int board_init(void) &i2c_pad_info3); setup_i2c4(); - /* SPI NOR Flash read only */ - gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor"); - gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0); - gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH); - setup_board_gpio(); setup_gpmi_nand(); - setup_board_spi(); /* GPIO_1 for USB_OTG_ID */ clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0); diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index ea60e17804a..0fa6bfb423c 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -64,6 +64,7 @@ CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_MXS=y +CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=3 CONFIG_SF_DEFAULT_CS=1 CONFIG_SF_DEFAULT_MODE=0 @@ -84,6 +85,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_IMX=y CONFIG_DM_SERIAL=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 269162eabfe..ced2bab2b5f 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -31,8 +31,6 @@ "ubifsload ${fit_addr_r} /boot/system.itb; " \ "imi ${fit_addr_r}\0 " -#define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15) - /* Framebuffer */ #define CONFIG_SYS_LDB_CLOCK 33246000 #define CONFIG_LG4573 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 1e2196f83d2..74b0005bacc 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -649,7 +649,6 @@ CONFIG_GLOBAL_DATA_NOT_REG10 CONFIG_GLOBAL_TIMER CONFIG_GMII CONFIG_GPCNTRL -CONFIG_GPIO_ENABLE_SPI_FLASH CONFIG_GPIO_LED_INVERTED_TABLE CONFIG_GPIO_LED_STUBS CONFIG_GREEN_LED -- cgit v1.3.1 From 5e65496d8059377f0abb1d0d52cf4bd1ab3a0aff Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:18 +0100 Subject: imx6: aristainetos: enable DM_ETH enable DM_ETH and remove unneeded board code. Signed-off-by: Heiko Schocher --- board/aristainetos/aristainetos.c | 35 +---------------------------------- configs/aristainetos2_defconfig | 2 ++ 2 files changed, 3 insertions(+), 34 deletions(-) (limited to 'configs') diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 5bb238b073c..f08f09e17f2 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -19,8 +19,6 @@ #include #include #include -#include -#include #include #include #include @@ -32,6 +30,7 @@ #include #include #include +#include #include #include <../drivers/video/imx/ipu.h> #if defined(CONFIG_VIDEO_BMP_LOGO) @@ -41,9 +40,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) @@ -86,24 +82,6 @@ struct i2c_pads_info i2c_pad_info4 = { } }; -iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - static iomux_v3_cfg_t const backlight_pads[] = { /* backlight PWM brightness control */ MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -113,11 +91,6 @@ static iomux_v3_cfg_t const backlight_pads[] = { MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -static void setup_iomux_enet(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); -} - static iomux_v3_cfg_t const display_pads[] = { MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL), MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, @@ -174,12 +147,6 @@ int board_phy_config(struct phy_device *phydev) return 0; } -int board_eth_init(bd_t *bis) -{ - setup_iomux_enet(); - return cpu_eth_init(bis); -} - static int rotate_logo_one(unsigned char *out, unsigned char *in) { int i, j; diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 0fa6bfb423c..92771555fa6 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -76,7 +76,9 @@ CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y CONFIG_MII=y +CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y -- cgit v1.3.1 From 621ff1363cba10281ba75f472c6731da48c3344d Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:19 +0100 Subject: imx6: aristainetos: add DM_VIDEO support add DM_VIDEO support and remove now unneeded board code. As we show a bmp logo on boot, call now bmp_display() from board code and do not use cfb_console anymore. Signed-off-by: Heiko Schocher --- board/aristainetos/aristainetos.c | 111 +++++--------------------------------- configs/aristainetos2_defconfig | 5 +- include/configs/aristainetos2.h | 9 ++-- 3 files changed, 19 insertions(+), 106 deletions(-) (limited to 'configs') diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index f08f09e17f2..8d07edd3e0f 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -19,24 +19,19 @@ #include #include #include -#include #include -#include -#include -#include #include #include +#include #include #include #include #include #include -#include -#include <../drivers/video/imx/ipu.h> -#if defined(CONFIG_VIDEO_BMP_LOGO) - #include -#endif +#include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -46,8 +41,6 @@ DECLARE_GLOBAL_DATA_PTR; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -#define DISP_PAD_CTRL (0x10) - enum { BOARD_TYPE_4 = 4, BOARD_TYPE_7 = 7, @@ -91,37 +84,6 @@ static iomux_v3_cfg_t const backlight_pads[] = { MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -static iomux_v3_cfg_t const display_pads[] = { - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL), - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, -}; - int board_phy_config(struct phy_device *phydev) { /* control data pad skew - devaddr = 0x02, register = 0x04 */ @@ -166,13 +128,15 @@ static int rotate_logo_one(unsigned char *out, unsigned char *in) void rotate_logo(int rotations) { unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT]; + struct bmp_header *header; unsigned char *in_logo; int i, j; if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT) return; - in_logo = bmp_logo_bitmap; + header = (struct bmp_header *)bmp_logo_bitmap; + in_logo = bmp_logo_bitmap + header->data_offset; /* one 90 degree rotation */ if (rotations == 1 || rotations == 2 || rotations == 3) @@ -194,34 +158,6 @@ void rotate_logo(int rotations) out_logo[i * BMP_LOGO_WIDTH + j]; } -static void enable_display_power(void) -{ - imx_iomux_v3_setup_multiple_pads(backlight_pads, - ARRAY_SIZE(backlight_pads)); - - /* backlight enable */ - gpio_request(IMX_GPIO_NR(6, 31), "backlight"); - gpio_direction_output(IMX_GPIO_NR(6, 31), 1); - gpio_free(IMX_GPIO_NR(6, 31)); - /* LCD power enable */ - gpio_request(IMX_GPIO_NR(6, 15), "LCD_power_enable"); - gpio_direction_output(IMX_GPIO_NR(6, 15), 1); - gpio_free(IMX_GPIO_NR(6, 15)); - - /* enable backlight PWM 1 */ - if (pwm_init(0, 0, 0)) - goto error; - /* duty cycle 500ns, period: 3000ns */ - if (pwm_config(0, 50000, 300000)) - goto error; - if (pwm_enable(0)) - goto error; - return; - -error: - puts("error init pwm for backlight\n"); -} - static void enable_lvds(struct display_info_t const *dev) { struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -304,15 +240,6 @@ static void enable_spi_display(struct display_info_t const *dev) rotate_logo(3); /* portrait display in landscape mode */ #endif - /* - * set ldb clock to 28341000 Hz calculated through the formula: - * (XRES + LEFT_M + RIGHT_M + HSYNC_LEN) * - * (YRES + UPPER_M + LOWER_M + VSYNC_LEN) * REFRESH) - * see: - * https://community.freescale.com/thread/308170 - */ - ipu_set_ldb_clock(28341000); - reg = readl(&ccm->cs2cdr); /* select pll 5 clock */ @@ -381,15 +308,11 @@ static void enable_spi_display(struct display_info_t const *dev) | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); writel(reg, &iomux->gpr[3]); - - imx_iomux_v3_setup_multiple_pads(display_pads, - ARRAY_SIZE(display_pads)); } static void setup_display(void) { enable_ipu_clock(); - enable_display_power(); } static void set_gpr_register(void) @@ -410,7 +333,7 @@ static void set_gpr_register(void) extern char __bss_start[], __bss_end[]; int board_early_init_f(void) { - setup_display(); + select_ldb_di_clock_source(MXC_PLL5_CLK); set_gpr_register(); /* @@ -453,11 +376,13 @@ int board_late_init(void) { char *my_bootdelay; char bootmode = 0; - char const *panel = env_get("panel"); struct gpio_desc *desc; + int x, y; int ret; led_default_state(); + splash_get_pos(&x, &y); + bmp_display((ulong)&bmp_logo_bitmap[0], x, y); /* * Check the boot-source. If booting from NOR Flash, * disable bootdelay @@ -496,13 +421,6 @@ int board_late_init(void) } } - /* if we have the lg panel, we can initialze it now */ - if (panel) - if (!strcmp(panel, displays[1].mode.name)) - lg4573_spi_startup(CONFIG_LG4573_BUS, - CONFIG_LG4573_CS, - 10000000, SPI_MODE_0); - /* set board_type */ if (gd->board_type == BOARD_TYPE_4) env_set("board_type", ARI_BT_4); @@ -596,12 +514,6 @@ struct display_info_t const displays[] = { }; size_t display_count = ARRAY_SIZE(displays); -/* no console on this board */ -int board_cfb_skip(void) -{ - return 1; -} - iomux_v3_cfg_t nfc_pads[] = { MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -673,6 +585,7 @@ int board_init(void) setup_board_gpio(); setup_gpmi_nand(); + setup_display(); /* GPIO_1 for USB_OTG_ID */ clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0); diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 92771555fa6..243b4ff5aa0 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -92,8 +92,9 @@ CONFIG_MXC_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_DISPLAY=y CONFIG_VIDEO_IPUV3=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set CONFIG_IMX_WATCHDOG=y # CONFIG_EFI_LOADER is not set diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index ced2bab2b5f..45699dc614e 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -32,7 +32,7 @@ "imi ${fit_addr_r}\0 " /* Framebuffer */ -#define CONFIG_SYS_LDB_CLOCK 33246000 +#define CONFIG_SYS_LDB_CLOCK 28341000 #define CONFIG_LG4573 #include "mx6_common.h" @@ -193,15 +193,14 @@ /* Framebuffer */ /* check this console not needed, after test remove it */ -#define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP +#define CONFIG_IMX_VIDEO_SKIP #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_IMX6_PWM_PER_CLK 66000000 - #endif /* __ARISTAINETOS2_CONFIG_H */ -- cgit v1.3.1 From b9d4b64e442dfe4e5b41abfb1db48cdc6a823bb3 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:20 +0100 Subject: imx6: aristainetos: add DM_I2C support enable DM_I2C in defconfig and remove i2c specific board code. Signed-off-by: Heiko Schocher --- board/aristainetos/aristainetos.c | 73 --------------------------------------- configs/aristainetos2_defconfig | 6 +++- include/configs/aristainetos2.h | 11 ------ 3 files changed, 5 insertions(+), 85 deletions(-) (limited to 'configs') diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 8d07edd3e0f..0d1c06da5d8 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -35,12 +34,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) - enum { BOARD_TYPE_4 = 4, BOARD_TYPE_7 = 7, @@ -49,32 +42,6 @@ enum { #define ARI_BT_4 "aristainetos2_4@2" #define ARI_BT_7 "aristainetos2_7@1" -struct i2c_pads_info i2c_pad_info3 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC, - .gp = IMX_GPIO_NR(1, 5) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, - .gp = IMX_GPIO_NR(1, 6) - } -}; - -struct i2c_pads_info i2c_pad_info4 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_7__I2C4_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_7__GPIO1_IO07 | PC, - .gp = IMX_GPIO_NR(1, 7) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_8__I2C4_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_8__GPIO1_IO08 | PC, - .gp = IMX_GPIO_NR(1, 8) - } -}; - static iomux_v3_cfg_t const backlight_pads[] = { /* backlight PWM brightness control */ MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -346,12 +313,6 @@ int board_early_init_f(void) return 0; } -static void setup_i2c4(void) -{ - setup_i2c(3, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, - &i2c_pad_info4); -} - static void setup_one_led(char *label, int state) { struct udevice *dev; @@ -430,32 +391,6 @@ int board_late_init(void) return 0; } -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC, - .gp = IMX_GPIO_NR(5, 27) - }, - .sda = { - .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, - .gp = IMX_GPIO_NR(5, 26) - } -}; - -struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } -}; - int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -575,14 +510,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, - &i2c_pad_info1); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, - &i2c_pad_info2); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, - &i2c_pad_info3); - setup_i2c4(); - setup_board_gpio(); setup_gpmi_nand(); setup_display(); diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 243b4ff5aa0..fd58aad4c26 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -36,7 +36,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -57,8 +56,11 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_GPIO=y CONFIG_GPIO_HOG=y CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -85,6 +87,8 @@ CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_IMX=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 45699dc614e..1999c5c6168 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -165,12 +165,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0x7f -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} } - /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 @@ -179,11 +173,6 @@ /* DMA stuff, needed for GPMI/MXS NAND support */ -/* RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_RTC_BUS_NUM 2 -#define CONFIG_RTC_M41T11 - /* USB Configs */ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -- cgit v1.3.1 From 87b687ad9dde05989c04074b13a04d466a3e94ce Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:21 +0100 Subject: imx6: aristainetos: convert to DM_PWM/DM_BACKLIGHT use DM_PWM and DM_BLACKLIGHT support and remove board code. Signed-off-by: Heiko Schocher --- board/aristainetos/aristainetos.c | 10 ---------- configs/aristainetos2_defconfig | 1 + 2 files changed, 1 insertion(+), 10 deletions(-) (limited to 'configs') diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 0d1c06da5d8..edaec5ee876 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include @@ -42,15 +41,6 @@ enum { #define ARI_BT_4 "aristainetos2_4@2" #define ARI_BT_7 "aristainetos2_7@1" -static iomux_v3_cfg_t const backlight_pads[] = { - /* backlight PWM brightness control */ - MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), - /* backlight enable */ - MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* LCD power enable */ - MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - int board_phy_config(struct phy_device *phydev) { /* control data pad skew - devaddr = 0x02, register = 0x04 */ diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index fd58aad4c26..b981b203b96 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -86,6 +86,7 @@ CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y CONFIG_PWM_IMX=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -- cgit v1.3.1 From 6a82579bdd40b4befb6ab4728a7d5fbf246f9705 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:24 +0100 Subject: imx6: aristainetos: add AUTOBOOT_KEYED add stop autobooting via SHA256 encrypted password. Signed-off-by: Heiko Schocher --- configs/aristainetos2_defconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'configs') diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index b981b203b96..dfaaf5dd8a4 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -18,6 +18,9 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_TYPES=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_ENCRYPTION=y +CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set -- cgit v1.3.1 From a450859af563ca19e3095dc3962ba383040fdcff Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:25 +0100 Subject: imx6: aristainetos: add version variable add VERSION_VARIABLE Signed-off-by: Heiko Schocher --- configs/aristainetos2_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'configs') diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index dfaaf5dd8a4..d2411c6070d 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -14,6 +14,7 @@ CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_VERSION_VARIABLE=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_TYPES=y CONFIG_BOARD_EARLY_INIT_F=y -- cgit v1.3.1 From 445c230814a99d51593e8f7a5c01339cc59beaf0 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:27 +0100 Subject: imx6: aristainetos: WDT DM conversion enable WDT reset enable config symbols: CONFIG_SYSRESET CONFIG_SYSRESET_WATCHDOG Signed-off-by: Heiko Schocher --- configs/aristainetos2_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'configs') diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index d2411c6070d..d7f24373d1e 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -98,6 +98,8 @@ CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -- cgit v1.3.1 From 70be2fcadc8f62c34c38dae8d42008adc8afd75b Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:28 +0100 Subject: imx6: aristainetos: cleanup default Environment sync defaut Envoronment with customer changes. Unfortunately they are not changeable, as already board is in production mode. Get rid of the big bootcommand and set bootcommand through Kconfig option. Signed-off-by: Heiko Schocher --- configs/aristainetos2_defconfig | 2 + include/configs/aristainetos2.h | 248 +++++++++++++++++++++++++++++++--------- 2 files changed, 195 insertions(+), 55 deletions(-) (limited to 'configs') diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index d7f24373d1e..cad9839f701 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -11,6 +11,8 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run ari_boot" # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SUPPORT_RAW_INITRD=y diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 1999c5c6168..fba26d01516 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -18,19 +18,6 @@ #define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "board_type=aristainetos2_7@1\0" \ - "nor_bootdelay=-2\0" \ - "mtdids=nand0=gpmi-nand,nor0=spi3.1\0" \ - "mtdparts=mtdparts=spi3.1:832k(u-boot),64k(env),64k(env-red)," \ - "-(rescue-system);gpmi-nand:-(ubi)\0" \ - "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0\0" \ - "ubiargs=setenv bootargs console=${console},${baudrate} " \ - "ubi.mtd=0,4096 root=ubi0:rootfs rootfstype=ubifs\0 " \ - "ubifs_load_fit=sf probe;ubi part ubi 4096;ubifsmount ubi:rootfs;" \ - "ubifsload ${fit_addr_r} /boot/system.itb; " \ - "imi ${fit_addr_r}\0 " - /* Framebuffer */ #define CONFIG_SYS_LDB_CLOCK 28341000 #define CONFIG_LG4573 @@ -49,49 +36,87 @@ #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN +#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ + "dead=led led_red on\0" \ + "mtdids=nand0=gpmi-nand,nor0=spi3.1\0" \ + "mtdparts=mtdparts=spi3.1:832k(u-boot),64k(env),64k(env-red)," \ + "-(ubi-nor);gpmi-nand:-(ubi)\0" \ + "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ + "bootmode=${bootmode} mmcpart=${mmcpart}\0" \ + "mainboot=echo Booting from SD-card ...; " \ + "run mainargs addmtd addmisc;" \ + "if test -n ${addmiscM}; then run addmiscM;fi;" \ + "if test -n ${addmiscC}; then run addmiscC;fi;" \ + "if test -n ${addmiscD}; then run addmiscD;fi;" \ + "run boot_board_type;" \ + "bootm ${fit_addr_r}\0" \ + "mainargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ + "${fit_file}\0" \ + "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ + "${fit_addr_r} ${rescue_fit_file}\0" + #define CONFIG_EXTRA_ENV_SETTINGS \ "disable_giga=yes\0" \ + "usb_pgood_delay=2000\0" \ + "nor_bootdelay=-2\0" \ "script=u-boot.scr\0" \ "fit_file=/boot/system.itb\0" \ + "rescue_fit_file=/boot/rescue.itb\0" \ "loadaddr=0x12000000\0" \ "fit_addr_r=0x14000000\0" \ "uboot=/boot/u-boot.imx\0" \ "uboot_sz=d0000\0" \ - "rescue_sys_addr=f0000\0" \ - "rescue_sys_length=f10000\0" \ "panel=lb07wv8\0" \ "splashpos=m,m\0" \ "console=" CONSOLE_DEV "\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \ - "default ${board_type}\0" \ + "boot_board_type=bootm ${fit_addr_r}#${board_type}\0" \ "get_env=mw ${loadaddr} 0 0x20000;" \ "mmc rescan;" \ - "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \ "env import -t ${loadaddr}\0" \ - "default_env=mw ${loadaddr} 0 0x20000;" \ - "env export -t ${loadaddr} serial# ethaddr eth1addr " \ - "board_type panel;" \ + "default_env=gpio set wp_spi_nor.gpio-hog;" \ + "sf probe;" \ + "sf protect unlock 0 0x1000000;" \ + "mw ${loadaddr} 0 0x20000;" \ + "env export -t ${loadaddr} serial# ethaddr " \ + "board_type panel addmisc addmiscM addmiscC addmiscD;" \ "env default -a;" \ "env import -t ${loadaddr}\0" \ "loadbootscript=" \ - "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${script};\0" \ + "loadbootscriptUSB=" \ + "ext4load usb 0 ${loadaddr} ${script};\0" \ + "loadbootscriptUSBf=" \ + "fatload usb 0 ${loadaddr} ${script};\0" \ + "bootscriptUSB=echo Running bootscript from usb-stick ...; " \ + "source\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ "mmcpart=1\0" \ + "mmcrescuepart=3\0" \ "mmcdev=0\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs addmtd addmisc set_fit_default;" \ + "run mmcargs addmtd addmisc;" \ + "if test -n ${addmiscM}; then run addmiscM;fi;" \ + "if test -n ${addmiscC}; then run addmiscC;fi;" \ + "if test -n ${addmiscD}; then run addmiscD;fi;" \ + "run boot_board_type;" \ "bootm ${fit_addr_r}\0" \ - "mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ + "mmc_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ "${fit_file}\0" \ - "mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "mmc_load_uboot=ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ "${uboot}\0" \ + "mmc_rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ + "${fit_addr_r} ${rescue_fit_file}\0" \ "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \ "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \ "setexpr uboot_maxsize ${uboot_sz} - 400;" \ @@ -100,50 +125,163 @@ "sf write ${loadaddr} 400 ${filesize};" \ "sf read ${cmp_buf} 400 ${uboot_sz};" \ "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \ - "ubiboot=echo Booting from ubi ...; " \ - "run ubiargs addmtd addmisc set_fit_default;" \ - "bootm ${fit_addr_r}\0" \ "rescueargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/ram rw\0 " \ - "rescueboot=echo Booting rescue system from NOR ...; " \ - "run rescueargs addmtd addmisc set_fit_default;" \ + "rescueboot=echo Booting rescue system ...; " \ + "run rescueargs addmtd addmisc;" \ + "if test -n ${rescue_reason}; then run rescue_reason;fi;" \ + "if test -n ${addmiscM}; then run addmiscM;fi;" \ + "if test -n ${addmiscC}; then run addmiscC;fi;" \ + "if test -n ${addmiscD}; then run addmiscD;fi;" \ + "run boot_board_type;" \ + "if bootm ${fit_addr_r}; then ; " \ + "else " \ + "run dead; " \ + "fi; \0" \ + "r_reason_syserr=setenv rescue_reason setenv bootargs " \ + "\\\\${bootargs} " \ + "rescueReason=18\0 " \ + "usb_load_fit=ext4load usb 0 ${fit_addr_r} ${fit_file}\0" \ + "usb_load_fitf=fatload usb 0 ${fit_addr_r} ${fit_file}\0" \ + "usb_load_rescuefit=ext4load usb 0 ${fit_addr_r} " \ + "${rescue_fit_file}\0" \ + "usb_load_rescuefitf=fatload usb 0 ${fit_addr_r} " \ + "${rescue_fit_file}\0" \ + "usbroot=/dev/sda1 rootwait rw\0" \ + "usbboot=echo Booting from usb-stick ...; " \ + "run usbargs addmtd addmisc;" \ + "if test -n ${addmiscM}; then run addmiscM;fi;" \ + "if test -n ${addmiscC}; then run addmiscC;fi;" \ + "if test -n ${addmiscD}; then run addmiscD;fi;" \ + "run boot_board_type;" \ "bootm ${fit_addr_r}\0" \ - "rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \ - "${rescue_sys_length}; imi ${fit_addr_r}\0" \ - CONFIG_EXTRA_ENV_BOARD_SETTINGS - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ + "usbargs=setenv bootargs console=${console},${baudrate} " \ + "root=${usbroot}\0" \ + "mmc_rescue_boot=" \ + "run r_reason_syserr;" \ + "if run mmc_rescue_load_fit hab_check_file_fit; then " \ + "run rescueboot; " \ "else " \ - "if run mmc_load_fit; then " \ - "run mmcboot; " \ + "run dead; " \ + "echo RESCUE SYSTEM FROM SD-CARD BOOT FAILURE;" \ + "fi;\0" \ + "main_rescue_boot=" \ + "if run main_load_fit hab_check_flash_fit; then " \ + "if run mainboot; then ; " \ "else " \ - "if run ubifs_load_fit; then " \ - "run ubiboot; " \ + "run r_reason_syserr;" \ + "if run rescue_load_fit hab_check_file_fit;" \ + "then run rescueboot; " \ "else " \ - "if run rescue_load_fit; then " \ - "run rescueboot; " \ - "else " \ - "echo RESCUE SYSTEM BOOT " \ - "FAILURE;" \ - "fi; " \ + "run dead; " \ + "echo RESCUE SYSTEM BOOT FAILURE;" \ "fi; " \ "fi; " \ - "fi; " \ - "else " \ - "if run ubifs_load_fit; then " \ - "run ubiboot; " \ "else " \ - "if run rescue_load_fit; then " \ + "run r_reason_syserr;" \ + "if run rescue_load_fit hab_check_file_fit; then " \ "run rescueboot; " \ "else " \ + "run dead; " \ "echo RESCUE SYSTEM BOOT FAILURE;" \ "fi; " \ + "fi;\0" \ + "usb_mmc_rescue_boot=" \ + "usb start;" \ + "if usb storage; then " \ + "if run loadbootscriptUSB " \ + "hab_check_file_bootscript;" \ + "then run bootscriptUSB; " \ + "fi; " \ + "if run loadbootscriptUSBf " \ + "hab_check_file_bootscript;" \ + "then run bootscriptUSB; " \ + "fi; " \ + "if run usb_load_fit hab_check_file_fit; then " \ + "run usbboot; " \ + "fi; " \ + "if run usb_load_fitf hab_check_file_fit; then " \ + "run usbboot; " \ + "fi; "\ + "if run usb_load_rescuefit hab_check_file_fit;" \ + "then run r_reason_syserr rescueboot;" \ + "fi; " \ + "if run usb_load_rescuefitf hab_check_file_fit;" \ + "then run r_reason_syserr rescueboot;" \ + "fi; " \ + "run mmc_rescue_boot;" \ + "fi; "\ + "run mmc_rescue_boot;\0" \ + "rescue_xload_boot=" \ + "run r_reason_syserr;" \ + "if test ${bootmode} -ne 0 ; then " \ + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run mmc_rescue_load_fit " \ + "hab_check_file_fit; then " \ + "run rescueboot; " \ + "else " \ + "usb start;" \ + "if usb storage; then " \ + "if run usb_load_rescuefit " \ + "hab_check_file_fit;"\ + "then " \ + "run rescueboot;" \ + "fi; " \ + "if run usb_load_rescuefitf "\ + "hab_check_file_fit;"\ + "then " \ + "run rescueboot;" \ + "fi; " \ + "fi;" \ + "fi;" \ + "run dead; " \ + "echo RESCUE SYSTEM ON SD OR " \ + "USB BOOT FAILURE;" \ + "else " \ + "usb start;" \ + "if usb storage; then " \ + "if run usb_load_rescuefit " \ + "hab_check_file_fit; then " \ + "run rescueboot;" \ + "fi; " \ + "if run usb_load_rescuefitf " \ + "hab_check_file_fit; then " \ + "run rescueboot;" \ + "fi; " \ + "fi;" \ + "run dead; " \ + "echo RESCUE SYSTEM ON USB BOOT FAILURE;" \ + "fi; " \ + "else "\ + "if run rescue_load_fit hab_check_file_fit; then " \ + "run rescueboot; " \ + "else " \ + "run dead; " \ + "echo RESCUE SYSTEM ON BOARD BOOT FAILURE;" \ + "fi; " \ + "fi;\0" \ + "ari_boot=if test ${bootmode} -ne 0 ; then " \ + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run loadbootscript hab_check_file_bootscript;" \ + "then run bootscript; " \ + "fi; " \ + "if run mmc_load_fit hab_check_file_fit; then " \ + "if run mmcboot; then ; " \ + "else " \ + "run mmc_rescue_boot;" \ + "fi; " \ + "else " \ + "run usb_mmc_rescue_boot;" \ + "fi; " \ + "else " \ + "run usb_mmc_rescue_boot;" \ "fi; " \ - "fi" + "else "\ + "run main_rescue_boot;" \ + "fi; \0"\ + CONFIG_EXTRA_ENV_BOARD_SETTINGS #define CONFIG_ARP_TIMEOUT 200UL -- cgit v1.3.1 From 1c9c4642c3c548678d96bba9f2ae7fb499324916 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:29 +0100 Subject: imx6: aristainetos: enable HAB boot enable IMX_HAB on aristianetos board Signed-off-by: Heiko Schocher --- board/aristainetos/aristainetos2.cfg | 3 +++ configs/aristainetos2_defconfig | 4 +++ include/configs/aristainetos2.h | 51 ++++++++++++++++++++++++++++++++++++ 3 files changed, 58 insertions(+) (limited to 'configs') diff --git a/board/aristainetos/aristainetos2.cfg b/board/aristainetos/aristainetos2.cfg index fbbc2e5e6d7..965ad64b496 100644 --- a/board/aristainetos/aristainetos2.cfg +++ b/board/aristainetos/aristainetos2.cfg @@ -23,6 +23,9 @@ BOOT_FROM spi #define __ASSEMBLY__ #include +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif #include "asm/arch/mx6-ddr.h" #include "asm/arch/iomux.h" #include "asm/arch/crm_regs.h" diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index cad9839f701..0c5c9fc18b0 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -8,6 +8,9 @@ CONFIG_ENV_SIZE=0x3000 CONFIG_ENV_OFFSET=0xD0000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_IMX_HAB=y +# CONFIG_CMD_DEKBLOB is not set +# CONFIG_CMD_NANDBCB is not set CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" CONFIG_BOOTDELAY=3 @@ -42,6 +45,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index fba26d01516..48cea2b4d06 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -36,6 +36,56 @@ #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN +#ifdef CONFIG_IMX_HAB +#define HAB_EXTRA_SETTINGS \ + "hab_check_addr=" \ + "if hab_auth_img ${check_addr} ${filesize} ; then " \ + "true;" \ + "else " \ + "echo \"HAB checks ${hab_check_filetype} " \ + "failed!\"; " \ + "false; " \ + "fi;\0" \ + "hab_check_file_fit=" \ + "if env exists enable_hab_check && test " \ + "${enable_hab_check} -eq 1 ; then " \ + "setenv hab_check_filetype \"FIT file on SD card " \ + "or eMMC\";" \ + "env set check_addr ${fit_addr_r};" \ + "run hab_check_addr;" \ + "else " \ + "true; "\ + "fi;\0" \ + "hab_check_file_bootscript=" \ + "if env exists enable_hab_check && test " \ + "${enable_hab_check} -eq 1 ; then " \ + "setenv hab_check_filetype \"Bootscript file\";" \ + "env set check_addr ${loadaddr};" \ + "run hab_check_addr;" \ + "else " \ + "true; "\ + "fi;\0" \ + "hab_check_flash_fit=" \ + "if env exists enable_hab_check && test " \ + "${enable_hab_check} -eq 1 ; then " \ + "setenv hab_check_filetype \"FIT files on flash\";" \ + "env set check_addr ${fit_addr_r};" \ + "run hab_check_addr;" \ + "else " \ + "true; "\ + "fi;\0" \ + "enable_hab_check=1\0" +#else +#define HAB_EXTRA_SETTINGS \ + "hab_check_file_fit=echo HAB check FIT file always returns " \ + "true;true\0" \ + "hab_check_flash_fit=echo HAB check flash FIT always returns " \ + "true;true\0" \ + "hab_check_file_bootscript=echo HAB check bootscript always " \ + "returns true;true\0" \ + "enable_hab_check=0\0" +#endif + #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ "dead=led led_red on\0" \ "mtdids=nand0=gpmi-nand,nor0=spi3.1\0" \ @@ -281,6 +331,7 @@ "else "\ "run main_rescue_boot;" \ "fi; \0"\ + HAB_EXTRA_SETTINGS \ CONFIG_EXTRA_ENV_BOARD_SETTINGS #define CONFIG_ARP_TIMEOUT 200UL -- cgit v1.3.1 From 1204b9675ed670da9317d87a5a29f06b6412745b Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:30 +0100 Subject: imx6: aristainetos: readd aristainetos 2b board readd aristainetos 2b board. Signed-off-by: Heiko Schocher --- arch/arm/dts/Makefile | 2 + arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi | 13 ++ arch/arm/dts/imx6dl-aristainetos2b_4.dts | 50 +++++ arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi | 19 ++ arch/arm/dts/imx6dl-aristainetos2b_7.dts | 16 ++ arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi | 77 +++++++ arch/arm/dts/imx6qdl-aristainetos2b.dtsi | 266 +++++++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 11 + board/aristainetos/Kconfig | 12 + board/aristainetos/MAINTAINERS | 7 + board/aristainetos/common/Kconfig | 1 + configs/aristainetos2b_defconfig | 115 ++++++++++ include/configs/aristainetos2.h | 23 ++ 13 files changed, 612 insertions(+) create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_4.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_7.dts create mode 100644 arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2b.dtsi create mode 100644 configs/aristainetos2b_defconfig (limited to 'configs') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d105d66d5b1..9d3fc778b2c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -578,6 +578,8 @@ ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),) dtb-y += \ imx6dl-aristainetos2_4.dtb \ imx6dl-aristainetos2_7.dtb \ + imx6dl-aristainetos2b_4.dtb \ + imx6dl-aristainetos2b_7.dtb \ imx6dl-brppt2.dtb \ imx6dl-dhcom-pdk2.dtb \ imx6dl-icore.dtb \ diff --git a/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi new file mode 100644 index 00000000000..ee02df39c15 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher + */ + +#include + +&lcd_panel { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_4.dts b/arch/arm/dts/imx6dl-aristainetos2b_4.dts new file mode 100644 index 00000000000..a48a25c1195 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_4.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2b board + * parts for 4.3 inch LG display on spi1 port1 + * + * Copyright (C) 2019 Heiko Schocher + * + */ +/dts-v1/; + +#include "imx6dl-aristainetos2_4.dtsi" +#include "imx6qdl-aristainetos2b.dtsi" + +/ { + model = "aristainetos2b i.MX6 Dual Lite Board 4"; + compatible = "fsl,imx6dl"; + +}; + +&ecspi1 { + lcd_panel: display@0 { + compatible = "lg,lg4573"; + spi-max-frequency = <10000000>; + reg = <1>; + power-on-delay = <10>; + + display-timings { + 480x800p57 { + native-mode; + clock-frequency = <27000027>; + hactive = <480>; + vactive = <800>; + hfront-porch = <10>; + hback-porch = <59>; + hsync-len = <10>; + vback-porch = <15>; + vfront-porch = <15>; + vsync-len = <15>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi new file mode 100644 index 00000000000..0cb4f1974b9 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher + */ + +#include +/ { + vdd_panel_reg: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "panel_regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&panel0 { + power-supply = <&vdd_panel_reg>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_7.dts b/arch/arm/dts/imx6dl-aristainetos2b_7.dts new file mode 100644 index 00000000000..f1496cbfdd9 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_7.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2 board + * + * Copyright (C) 2019 Heiko Schocher + * Copyright (C) 2015 Heiko Schocher + * + */ +/dts-v1/; +#include "imx6dl-aristainetos2_7.dtsi" +#include "imx6qdl-aristainetos2b.dtsi" + +/ { + model = "aristainetos2b i.MX6 Dual Lite Board 7"; + compatible = "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi new file mode 100644 index 00000000000..88826a2634c --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher + */ + +/ { + chosen { + u-boot,dm-pre-reloc; + stdout-path = &uart2; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + }; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_gpio { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart2 { + u-boot,dm-pre-reloc; +}; + +&iomuxc { + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-pre-reloc; +}; + +&backlight { + pwms = <&pwm1 0 300000>; + default-brightness-level = <2>; +}; + +/* + * allow switching write protect / reset pin by gpio, + * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot + */ +&gpio2 { + u-boot,dm-pre-reloc; + + wp_spi_nor { + gpio-hog; + output-high; + gpios = <15 GPIO_ACTIVE_HIGH>; + }; + + reset_spi_nor { + gpio-hog; + output-high; + gpios = <28 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio4 { + u-boot,dm-pre-reloc; +}; + +&ecspi1 { + u-boot,dm-pre-reloc; +}; + +&flash { + u-boot,dm-pre-reloc; +}; + +&pinctrl_ecspi1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b.dtsi new file mode 100644 index 00000000000..7d92ea2af7e --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2b.dtsi @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2b board + * + * Copyright (C) 2019 Heiko Schocher + * Copyright (C) 2015 Heiko Schocher + * + */ +#include +#include + +#include "imx6qdl-aristainetos2-common.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; + + LED_blue { + label = "led_blue"; + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + }; + + LED_green { + label = "led_green"; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + }; + + LED_red { + label = "led_red"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + }; + + LED_yellow { + label = "led_yellow"; + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + }; + + LED_ena { + label = "led_ena"; + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <3>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH + &gpio4 10 GPIO_ACTIVE_HIGH + &gpio4 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; +}; + +&i2c1 { + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; +}; + +&gpio7 { + sd2_driver_ena { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + /* + * comment out this line to make the WiFi Eval-Module work in + * SD-Slot2, and add line: + * broken-cd; + * causes 6% CPU load if no WiFi module installed (polling) + */ + cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* SS0# */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 + /* SS1# */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 + /* SS2# */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 + /* WP pin NOR Flash */ + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 + /* Flash nReset */ + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + /* led enable */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 + /* LCD power enable */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 + /* led yellow */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 + /* led red */ + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0 + /* led green */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 + /* led blue */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 + /* Profibus IRQ */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + /* FPGA IRQ currently unused*/ + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 + /* Display reset because of clock failure */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 + /* spi bus #2 SS driver enable */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 + /* RST_LOC# PHY reset input (has pull-down!)*/ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 + /* Touchscreen IRQ */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 + /* PCIe reset */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 + /* make sure pin is GPIO and not ENET_REF_CLK */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0 + /* SD2 level shifter output enable / SD2 Reset# */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 + >; + }; + + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + /* SD1 card detect input */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + /* SD1 write protect input */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 + /* SD2 card detect input */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + /* SD2 write protect input */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 6bc7405a1ca..95265e94212 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -136,6 +136,17 @@ config TARGET_ARISTAINETOS2 imply CMD_SATA imply CMD_DM +config TARGET_ARISTAINETOS2B + bool "Support aristainetos2-revB" + select BOARD_LATE_INIT + select MX6DL + select SYS_I2C_MXC + select MXC_UART + select FEC_MXC + select DM + imply CMD_SATA + imply CMD_DM + config TARGET_CGTQMX6EVAL bool "cgtqmx6eval" select BOARD_LATE_INIT diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index 6700f517f10..2e1d84d412e 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -9,3 +9,15 @@ config SYS_BOARD_VERSION default 2 endif + +if TARGET_ARISTAINETOS2B + +source "board/aristainetos/common/Kconfig" + +config SYS_BOARD + default "aristainetos" + +config SYS_BOARD_VERSION + default 3 + +endif diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index 2495cd4a370..4fa0ad2e985 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -4,6 +4,7 @@ S: Maintained F: board/aristainetos/ F: include/configs/aristainetos2.h F: configs/aristainetos2_defconfig +F: configs/aristainetos2b_defconfig F: arch/arm/dts/imx6qdl-aristainetos2.dtsi F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi @@ -13,3 +14,9 @@ F: arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi F: arch/arm/dts/imx6dl-aristainetos2_4.dts F: arch/arm/dts/imx6dl-aristainetos2_4.dtsi F: arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2b_4.dts +F: arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2b_7.dts +F: arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2b.dtsi diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig index 8f2561415be..a15993e2deb 100644 --- a/board/aristainetos/common/Kconfig +++ b/board/aristainetos/common/Kconfig @@ -3,6 +3,7 @@ config SYS_BOARD_VERSION help version of aristainetos board version 2 version 2 + 3 version 2b config SYS_I2C_MXC_I2C1 default y diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig new file mode 100644 index 00000000000..adfed9a3dca --- /dev/null +++ b/configs/aristainetos2b_defconfig @@ -0,0 +1,115 @@ +CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SYS_MALLOC_F_LEN=0xe000 +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xD0000 +CONFIG_TARGET_ARISTAINETOS2B=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_IMX_HAB=y +# CONFIG_CMD_DEKBLOB is not set +# CONFIG_CMD_NANDBCB is not set +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run ari_boot" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_VERSION_VARIABLE=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_TYPES=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_ENCRYPTION=y +CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND_TRIMFFS=y +# CONFIG_CMD_PINMUX is not set +# CONFIG_CMD_SATA is not set +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +# CONFIG_CMD_HASH is not set +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2b_4" +CONFIG_OF_LIST="imx6dl-aristainetos2b_4 imx6dl-aristainetos2b_7" +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SPI_EARLY=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_OFFSET_REDUND=0xE0000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_GPIO=y +CONFIG_GPIO_HOG=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_IMX=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_WATCHDOG=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 48cea2b4d06..d2646d26da8 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -86,6 +86,28 @@ "enable_hab_check=0\0" #endif +#if (CONFIG_SYS_BOARD_VERSION == 3) +#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ + "dead=led led_red on\0" \ + "mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \ + "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ + "-(ubi-nor);gpmi-nand:-(ubi)\0" \ + "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ + "bootmode=${bootmode} mmcpart=${mmcpart}\0" \ + "mainboot=echo Booting from SD-card ...; " \ + "run mainargs addmtd addmisc;" \ + "if test -n ${addmiscM}; then run addmiscM;fi;" \ + "if test -n ${addmiscC}; then run addmiscC;fi;" \ + "if test -n ${addmiscD}; then run addmiscD;fi;" \ + "run boot_board_type;" \ + "bootm ${fit_addr_r}\0" \ + "mainargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ + "${fit_file}\0" \ + "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ + "${fit_addr_r} ${rescue_fit_file}\0" +#else #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ "dead=led led_red on\0" \ "mtdids=nand0=gpmi-nand,nor0=spi3.1\0" \ @@ -106,6 +128,7 @@ "${fit_file}\0" \ "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ "${fit_addr_r} ${rescue_fit_file}\0" +#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "disable_giga=yes\0" \ -- cgit v1.3.1 From c08aa771735a79efa48b2422295d88ca044ce71d Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:31 +0100 Subject: imx6: aristainetos: add aristainetos 2b csl add aristainetso board version CSL. Signed-off-by: Heiko Schocher --- arch/arm/dts/Makefile | 2 + .../dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi | 13 ++ arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts | 50 +++++ .../dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi | 19 ++ arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts | 16 ++ .../arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi | 77 +++++++ arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi | 248 +++++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 11 + board/aristainetos/Kconfig | 12 + board/aristainetos/MAINTAINERS | 7 + board/aristainetos/aristainetos.c | 4 +- board/aristainetos/common/Kconfig | 1 + configs/aristainetos2bcsl_defconfig | 115 ++++++++++ include/configs/aristainetos2.h | 21 ++ 14 files changed, 595 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts create mode 100644 arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi create mode 100644 configs/aristainetos2bcsl_defconfig (limited to 'configs') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9d3fc778b2c..fb2e1d31a37 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -580,6 +580,8 @@ dtb-y += \ imx6dl-aristainetos2_7.dtb \ imx6dl-aristainetos2b_4.dtb \ imx6dl-aristainetos2b_7.dtb \ + imx6dl-aristainetos2b_csl_4.dtb \ + imx6dl-aristainetos2b_csl_7.dtb \ imx6dl-brppt2.dtb \ imx6dl-dhcom-pdk2.dtb \ imx6dl-icore.dtb \ diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi new file mode 100644 index 00000000000..654ac122a16 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher + */ + +#include + +&lcd_panel { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts b/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts new file mode 100644 index 00000000000..bfbb799f20c --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2b csl board + * parts for 4.3 inch LG display on spi1 port1 + * + * Copyright (C) 2019 Heiko Schocher + * + */ +/dts-v1/; + +#include "imx6dl-aristainetos2_4.dtsi" +#include "imx6qdl-aristainetos2b_csl.dtsi" + +/ { + model = "aristainetos2b csl i.MX6 Dual Lite Board 4"; + compatible = "fsl,imx6dl"; + +}; + +&ecspi1 { + lcd_panel: display@0 { + compatible = "lg,lg4573"; + spi-max-frequency = <10000000>; + reg = <1>; + power-on-delay = <10>; + + display-timings { + 480x800p57 { + native-mode; + clock-frequency = <27000027>; + hactive = <480>; + vactive = <800>; + hfront-porch = <10>; + hback-porch = <59>; + hsync-len = <10>; + vback-porch = <15>; + vfront-porch = <15>; + vsync-len = <15>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi new file mode 100644 index 00000000000..70d195ecbfe --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher + */ + +#include +/ { + vdd_panel_reg: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "panel_regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&panel0 { + power-supply = <&vdd_panel_reg>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts b/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts new file mode 100644 index 00000000000..ecf767da6ce --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2 board + * + * Copyright (C) 2019 Heiko Schocher + * Copyright (C) 2015 Heiko Schocher + * + */ +/dts-v1/; +#include "imx6dl-aristainetos2_7.dtsi" +#include "imx6qdl-aristainetos2b_csl.dtsi" + +/ { + model = "aristainetos2b csl i.MX6 Dual Lite Board 7"; + compatible = "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi new file mode 100644 index 00000000000..8c2ed700751 --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher + */ + +/ { + chosen { + u-boot,dm-pre-reloc; + stdout-path = &uart1; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + }; +}; + +&uart1 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_gpio { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; + +&iomuxc { + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-pre-reloc; +}; + +&backlight { + pwms = <&pwm1 0 300000>; + default-brightness-level = <2>; +}; + +/* + * allow switching write protect / reset pin by gpio, + * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot + */ +&gpio2 { + u-boot,dm-pre-reloc; + + wp_spi_nor { + gpio-hog; + output-high; + gpios = <15 GPIO_ACTIVE_HIGH>; + }; + + reset_spi_nor { + gpio-hog; + output-high; + gpios = <28 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio4 { + u-boot,dm-pre-reloc; +}; + +&ecspi1 { + u-boot,dm-pre-reloc; +}; + +&flash { + u-boot,dm-pre-reloc; +}; + +&pinctrl_ecspi1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi new file mode 100644 index 00000000000..fa4dadefb65 --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2b-csl board + * + * Copyright (C) 2019 Heiko Schocher + * Copyright (C) 2015 Heiko Schocher + * + */ +#include +#include + +#include "imx6qdl-aristainetos2-common.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; + + LED_blue { + label = "led_blue"; + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + }; + + LED_green { + label = "led_green"; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + }; + + LED_red { + label = "led_red"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + }; + + LED_yellow { + label = "led_yellow"; + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + }; + + LED_blue_2 { + label = "led_blue2"; + gpios = <&expander 15 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_green_2 { + label = "led_green2"; + gpios = <&expander 14 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_red_2 { + label = "led_red2"; + gpios = <&expander 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_yellow_2 { + label = "led_yellow2"; + gpios = <&expander 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_ena { + label = "led_ena"; + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <3>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH + &gpio4 10 GPIO_ACTIVE_HIGH + &gpio4 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; +}; + +&i2c1 { + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; +}; + +&gpio7 { + wlan_reset { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* SS0# */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 + /* SS1# */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 + /* SS2# */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 + /* WP pin NOR Flash */ + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 + /* Flash nReset */ + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + /* led enable */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 + /* LCD power enable */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 + /* led yellow */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 + /* led red */ + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0 + /* led green */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 + /* led blue */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 + /* Profibus IRQ */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + /* FPGA IRQ currently unused*/ + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 + /* Display reset because of clock failure */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 + /* spi bus #2 SS driver enable */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 + /* RST_LOC# PHY reset input (has pull-down!)*/ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 + /* Touchscreen IRQ */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 + /* PCIe reset */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 + /* make sure pin is GPIO and not ENET_REF_CLK */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0 + /* WLAN Module Reset# */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 + >; + }; + + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + /* SD1 card detect input */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 + >; + }; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 95265e94212..de71cd52b41 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -147,6 +147,17 @@ config TARGET_ARISTAINETOS2B imply CMD_SATA imply CMD_DM +config TARGET_ARISTAINETOS2BCSL + bool "Support aristainetos2-revB CSL" + select BOARD_LATE_INIT + select MX6DL + select SYS_I2C_MXC + select MXC_UART + select FEC_MXC + select DM + imply CMD_SATA + imply CMD_DM + config TARGET_CGTQMX6EVAL bool "cgtqmx6eval" select BOARD_LATE_INIT diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index 2e1d84d412e..9eb3c3b9d87 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -21,3 +21,15 @@ config SYS_BOARD_VERSION default 3 endif + +if TARGET_ARISTAINETOS2BCSL + +source "board/aristainetos/common/Kconfig" + +config SYS_BOARD + default "aristainetos" + +config SYS_BOARD_VERSION + default 4 + +endif diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index 4fa0ad2e985..9685c032abb 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -5,6 +5,7 @@ F: board/aristainetos/ F: include/configs/aristainetos2.h F: configs/aristainetos2_defconfig F: configs/aristainetos2b_defconfig +F: configs/aristainetos2bcsl_defconfig F: arch/arm/dts/imx6qdl-aristainetos2.dtsi F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi @@ -20,3 +21,9 @@ F: arch/arm/dts/imx6dl-aristainetos2b_7.dts F: arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi F: arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi F: arch/arm/dts/imx6qdl-aristainetos2b.dtsi +F: arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts +F: arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts +F: arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index ca6155947b3..88090799a6d 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -490,7 +490,9 @@ struct display_info_t const displays[] = { .vmode = FB_VMODE_NONINTERLACED } } -#if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3)) +#if ((CONFIG_SYS_BOARD_VERSION == 2) || \ + (CONFIG_SYS_BOARD_VERSION == 3) || \ + (CONFIG_SYS_BOARD_VERSION == 4)) , { .bus = -1, .addr = 0, diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig index a15993e2deb..6f1c825d80e 100644 --- a/board/aristainetos/common/Kconfig +++ b/board/aristainetos/common/Kconfig @@ -4,6 +4,7 @@ config SYS_BOARD_VERSION version of aristainetos board version 2 version 2 3 version 2b + 4 version 2bcsl config SYS_I2C_MXC_I2C1 default y diff --git a/configs/aristainetos2bcsl_defconfig b/configs/aristainetos2bcsl_defconfig new file mode 100644 index 00000000000..d83d52fbc68 --- /dev/null +++ b/configs/aristainetos2bcsl_defconfig @@ -0,0 +1,115 @@ +CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SYS_MALLOC_F_LEN=0xe000 +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xD0000 +CONFIG_TARGET_ARISTAINETOS2BCSL=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_IMX_HAB=y +# CONFIG_CMD_DEKBLOB is not set +# CONFIG_CMD_NANDBCB is not set +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run ari_boot" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_VERSION_VARIABLE=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_TYPES=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_ENCRYPTION=y +CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND_TRIMFFS=y +# CONFIG_CMD_PINMUX is not set +# CONFIG_CMD_SATA is not set +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +# CONFIG_CMD_HASH is not set +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2b_csl_4" +CONFIG_OF_LIST="imx6dl-aristainetos2b_csl_4 imx6dl-aristainetos2b_csl_7" +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SPI_EARLY=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_OFFSET_REDUND=0xE0000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_GPIO=y +CONFIG_GPIO_HOG=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_IMX=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_WATCHDOG=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index d2646d26da8..64a819df132 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -107,6 +107,27 @@ "${fit_file}\0" \ "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ "${fit_addr_r} ${rescue_fit_file}\0" +#elif (CONFIG_SYS_BOARD_VERSION == 4) +#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ + "dead=led led_red on;led led_red2 on;\0" \ + "mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \ + "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ + "-(ubi-nor);gpmi-nand:-(ubi)\0" \ + "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ + "bootmode=${bootmode} mmcpart=${mmcpart}\0" \ + "mainboot=echo Booting from SD-card ...; " \ + "run mainargs addmtd addmisc;" \ + "if test -n ${addmiscM}; then run addmiscM;fi;" \ + "if test -n ${addmiscC}; then run addmiscC;fi;" \ + "if test -n ${addmiscD}; then run addmiscD;fi;" \ + "run boot_board_type;" \ + "bootm ${fit_addr_r}\0" \ + "mainargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ + "${fit_file}\0" \ + "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ + "${fit_addr_r} ${rescue_fit_file}\0" #else #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ "dead=led led_red on\0" \ -- cgit v1.3.1 From 227cb30047b578873aa48b6b2a94de8260ba6e34 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 1 Dec 2019 11:23:32 +0100 Subject: imx6: aristainetos: add support for rev C board add support for revision C boards. This board has no longer a NAND. Signed-off-by: Heiko Schocher --- arch/arm/dts/Makefile | 2 + arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi | 13 ++ arch/arm/dts/imx6dl-aristainetos2c_4.dts | 50 +++++ arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi | 19 ++ arch/arm/dts/imx6dl-aristainetos2c_7.dts | 16 ++ arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi | 77 ++++++++ arch/arm/dts/imx6qdl-aristainetos2c.dtsi | 228 +++++++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 11 ++ board/aristainetos/Kconfig | 12 ++ board/aristainetos/MAINTAINERS | 7 + board/aristainetos/aristainetos.c | 9 +- board/aristainetos/common/Kconfig | 1 + configs/aristainetos2c_defconfig | 115 ++++++++++++ include/configs/aristainetos2.h | 27 +++ 14 files changed, 586 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_4.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_7.dts create mode 100644 arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2c.dtsi create mode 100644 configs/aristainetos2c_defconfig (limited to 'configs') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fb2e1d31a37..fd165844e4b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -582,6 +582,8 @@ dtb-y += \ imx6dl-aristainetos2b_7.dtb \ imx6dl-aristainetos2b_csl_4.dtb \ imx6dl-aristainetos2b_csl_7.dtb \ + imx6dl-aristainetos2c_4.dtb \ + imx6dl-aristainetos2c_7.dtb \ imx6dl-brppt2.dtb \ imx6dl-dhcom-pdk2.dtb \ imx6dl-icore.dtb \ diff --git a/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi new file mode 100644 index 00000000000..052d51852b9 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher + */ + +#include + +&lcd_panel { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2c_4.dts b/arch/arm/dts/imx6dl-aristainetos2c_4.dts new file mode 100644 index 00000000000..142b108acec --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2c_4.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2c board + * parts for 4.3 inch LG display on spi1 port1 + * + * Copyright (C) 2019 Heiko Schocher + * + */ +/dts-v1/; + +#include "imx6dl-aristainetos2_4.dtsi" +#include "imx6qdl-aristainetos2c.dtsi" + +/ { + model = "aristainetos2c i.MX6 Dual Lite Board 4"; + compatible = "fsl,imx6dl"; + +}; + +&ecspi1 { + lcd_panel: display@0 { + compatible = "lg,lg4573"; + spi-max-frequency = <10000000>; + reg = <1>; + power-on-delay = <10>; + + display-timings { + 480x800p57 { + native-mode; + clock-frequency = <27000027>; + hactive = <480>; + vactive = <800>; + hfront-porch = <10>; + hback-porch = <59>; + hsync-len = <10>; + vback-porch = <15>; + vfront-porch = <15>; + vsync-len = <15>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi new file mode 100644 index 00000000000..cb2181d9e2f --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher + */ + +#include +/ { + vdd_panel_reg: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "panel_regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&panel0 { + power-supply = <&vdd_panel_reg>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2c_7.dts b/arch/arm/dts/imx6dl-aristainetos2c_7.dts new file mode 100644 index 00000000000..35435e1c104 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2c_7.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2c board + * + * Copyright (C) 2019 Heiko Schocher + * Copyright (C) 2015 Heiko Schocher + * + */ +/dts-v1/; +#include "imx6dl-aristainetos2_7.dtsi" +#include "imx6qdl-aristainetos2c.dtsi" + +/ { + model = "aristainetos2c i.MX6 Dual Lite Board 7"; + compatible = "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi new file mode 100644 index 00000000000..88826a2634c --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher + */ + +/ { + chosen { + u-boot,dm-pre-reloc; + stdout-path = &uart2; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + }; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_gpio { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart2 { + u-boot,dm-pre-reloc; +}; + +&iomuxc { + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-pre-reloc; +}; + +&backlight { + pwms = <&pwm1 0 300000>; + default-brightness-level = <2>; +}; + +/* + * allow switching write protect / reset pin by gpio, + * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot + */ +&gpio2 { + u-boot,dm-pre-reloc; + + wp_spi_nor { + gpio-hog; + output-high; + gpios = <15 GPIO_ACTIVE_HIGH>; + }; + + reset_spi_nor { + gpio-hog; + output-high; + gpios = <28 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio4 { + u-boot,dm-pre-reloc; +}; + +&ecspi1 { + u-boot,dm-pre-reloc; +}; + +&flash { + u-boot,dm-pre-reloc; +}; + +&pinctrl_ecspi1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2c.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c.dtsi new file mode 100644 index 00000000000..ba13d55f419 --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2c.dtsi @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2c board + * + * Copyright (C) 2019 Heiko Schocher + * Copyright (C) 2015 Heiko Schocher + * + */ +#include +#include + +#include "imx6qdl-aristainetos2-common.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; + + LED_blue { + label = "led_blue"; + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + }; + + LED_green { + label = "led_green"; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + }; + + LED_red { + label = "led_red"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + }; + + LED_yellow { + label = "led_yellow"; + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + }; + + LED_ena { + label = "led_ena"; + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <3>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH + &gpio4 10 GPIO_ACTIVE_HIGH + &gpio4 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; +}; + +&i2c1 { + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* SS0# */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 + /* SS1# */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 + /* SS2# */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 + /* WP pin NOR Flash */ + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 + /* Flash nReset */ + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + /* led enable */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 + /* LCD power enable */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 + /* led yellow */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 + /* led red */ + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0 + /* led green */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 + /* led blue */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 + /* Profibus IRQ */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + /* FPGA IRQ currently unused*/ + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 + /* Display reset because of clock failure */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 + /* spi bus #2 SS driver enable */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 + /* RST_LOC# PHY reset input (has pull-down!)*/ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 + /* Touchscreen IRQ */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 + /* PCIe reset */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 + /* make sure pin is GPIO and not ENET_REF_CLK */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0 + /* TPM PP */ + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x4001b0b0 + /* TPM Reset */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + /* SD1 card detect input */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + /* SD1 write protect input */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 + >; + }; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index de71cd52b41..f1a1021f10c 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -158,6 +158,17 @@ config TARGET_ARISTAINETOS2BCSL imply CMD_SATA imply CMD_DM +config TARGET_ARISTAINETOS2C + bool "Support aristainetos2-revC" + select BOARD_LATE_INIT + select MX6DL + select SYS_I2C_MXC + select MXC_UART + select FEC_MXC + select DM + imply CMD_SATA + imply CMD_DM + config TARGET_CGTQMX6EVAL bool "cgtqmx6eval" select BOARD_LATE_INIT diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index 9eb3c3b9d87..2ad3dbd56cb 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -33,3 +33,15 @@ config SYS_BOARD_VERSION default 4 endif + +if TARGET_ARISTAINETOS2C + +source "board/aristainetos/common/Kconfig" + +config SYS_BOARD + default "aristainetos" + +config SYS_BOARD_VERSION + default 5 + +endif diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index 9685c032abb..b4ca7abb9c6 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -6,6 +6,7 @@ F: include/configs/aristainetos2.h F: configs/aristainetos2_defconfig F: configs/aristainetos2b_defconfig F: configs/aristainetos2bcsl_defconfig +F: configs/aristainetos2c_defconfig F: arch/arm/dts/imx6qdl-aristainetos2.dtsi F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi @@ -27,3 +28,9 @@ F: arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts F: arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi F: arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi F: arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2c_4.dts +F: arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2c_7.dts +F: arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2c.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 88090799a6d..c79ac1d3391 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -492,7 +492,8 @@ struct display_info_t const displays[] = { } #if ((CONFIG_SYS_BOARD_VERSION == 2) || \ (CONFIG_SYS_BOARD_VERSION == 3) || \ - (CONFIG_SYS_BOARD_VERSION == 4)) + (CONFIG_SYS_BOARD_VERSION == 4) || \ + (CONFIG_SYS_BOARD_VERSION == 5)) , { .bus = -1, .addr = 0, @@ -520,6 +521,7 @@ struct display_info_t const displays[] = { }; size_t display_count = ARRAY_SIZE(displays); +#if defined(CONFIG_NAND) iomux_v3_cfg_t nfc_pads[] = { MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -573,6 +575,11 @@ static void setup_gpmi_nand(void) /* enable apbh clock gating */ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); } +#else +static void setup_gpmi_nand(void) +{ +} +#endif int board_init(void) { diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig index 6f1c825d80e..e26de5144d6 100644 --- a/board/aristainetos/common/Kconfig +++ b/board/aristainetos/common/Kconfig @@ -5,6 +5,7 @@ config SYS_BOARD_VERSION 2 version 2 3 version 2b 4 version 2bcsl + 5 version 2c config SYS_I2C_MXC_I2C1 default y diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig new file mode 100644 index 00000000000..46a3cf72981 --- /dev/null +++ b/configs/aristainetos2c_defconfig @@ -0,0 +1,115 @@ +CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SYS_MALLOC_F_LEN=0xe000 +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xD0000 +CONFIG_TARGET_ARISTAINETOS2C=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_IMX_HAB=y +# CONFIG_CMD_DEKBLOB is not set +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run ari_boot" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_VERSION_VARIABLE=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_TYPES=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_ENCRYPTION=y +CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_PINMUX is not set +# CONFIG_CMD_SATA is not set +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +# CONFIG_CMD_HASH is not set +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_4" +CONFIG_OF_LIST="imx6dl-aristainetos2c_4 imx6dl-aristainetos2c_7" +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SPI_EARLY=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_OFFSET_REDUND=0xE0000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_APBH_DMA=y +CONFIG_APBH_DMA_BURST=y +CONFIG_APBH_DMA_BURST8=y +CONFIG_DM_GPIO=y +CONFIG_GPIO_HOG=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_MTD_DEVICE=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_IMX=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_WATCHDOG=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 64a819df132..5f4a4f854f9 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -128,6 +128,33 @@ "${fit_file}\0" \ "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ "${fit_addr_r} ${rescue_fit_file}\0" +#elif (CONFIG_SYS_BOARD_VERSION == 5) +#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ + "emmcpart=1\0" \ + "emmc_rescue_part=3\0" \ + "emmcdev=1\0" \ + "emmcroot=/dev/mmcblk1p1 rootwait rw\0" \ + "dead=led led_red on\0" \ + "mtdids=nor0=spi0.0\0" \ + "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ + "-(ubi-nor)\0" \ + "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ + "bootmode=${bootmode} mmcpart=${mmcpart} " \ + "emmcpart=${emmcpart}\0" \ + "mainboot=echo Booting from eMMC ...; " \ + "run mainargs addmtd addmisc;" \ + "if test -n ${addmiscM}; then run addmiscM;fi;" \ + "if test -n ${addmiscC}; then run addmiscC;fi;" \ + "if test -n ${addmiscD}; then run addmiscD;fi;" \ + "run boot_board_type;" \ + "bootm ${fit_addr_r}\0" \ + "mainargs=setenv bootargs console=${console},${baudrate} " \ + "root=${emmcroot} rootfstype=ext4\0 " \ + "main_load_fit=ext4load mmc ${emmcdev}:${emmcpart} ${fit_addr_r} " \ + "${fit_file}; " \ + "imi ${fit_addr_r}\0 " \ + "rescue_load_fit=ext4load mmc ${emmcdev}:${emmc_rescue_part} " \ + "${fit_addr_r} ${rescue_fit_file};imi ${fit_addr_r}\0" #else #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ "dead=led led_red on\0" \ -- cgit v1.3.1 From 010e58d448d5cb184fc53d6bbb87deee3ce5b223 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Sun, 8 Dec 2019 22:06:56 +0100 Subject: imx: Add support for i.MX28 based XEA board This patch introduces support for i.MX28 based XEA board. This board supports DM/DTS in U-Boot proper as well as DM aware drivers in SPL (u-boot.sb) by using OF_PLATDATA. More detailed information regarding usage of it can be found in ./board/liebherr/xea/README file. U-Boot SPL 2019.10-rc1-00233-g6aa549f05c (Aug 12 2019 - 09:23:36 +0200) Trying to boot from MMC1 MMC0: Command 8 timeout (status 0xf0344020) mmc_load_image_raw_sector: mmc block read error U-Boot 2019.10-rc1-00233-g6aa549f05c (Aug 12 2019 - 09:23:36 +0200) CPU: Freescale i.MX28 rev1.2 at 454 MHz BOOT: SSP SPI #3, master, 3V3 NOR Model: Liebherr (LWE) XEA i.MX28 Board DRAM: 128 MiB MMC: MXS MMC: 0 Loading Environment from SPI Flash... SF: Detected n25q128a13 with page size 256 Bytes, erase size 64 KiB, total 16 MiB OK In: serial Out: serial Err: serial Net: Warning: ethernet@800f0000 (eth0) using random MAC address - ce:e1:9e:46:f3:a2 eth0: ethernet@800f0000 Hit any key to stop autoboot: 0 Signed-off-by: Lukasz Majewski --- arch/arm/dts/Makefile | 3 + arch/arm/dts/imx28-xea-u-boot.dtsi | 46 ++++++ arch/arm/dts/imx28-xea.dts | 110 ++++++++++++++ arch/arm/mach-imx/mxs/Kconfig | 4 + board/liebherr/xea/Kconfig | 24 +++ board/liebherr/xea/MAINTAINERS | 6 + board/liebherr/xea/Makefile | 12 ++ board/liebherr/xea/README | 63 ++++++++ board/liebherr/xea/spl_xea.c | 303 +++++++++++++++++++++++++++++++++++++ board/liebherr/xea/xea.c | 153 +++++++++++++++++++ configs/imx28_xea_defconfig | 108 +++++++++++++ include/configs/xea.h | 196 ++++++++++++++++++++++++ 12 files changed, 1028 insertions(+) create mode 100644 arch/arm/dts/imx28-xea-u-boot.dtsi create mode 100644 arch/arm/dts/imx28-xea.dts create mode 100644 board/liebherr/xea/Kconfig create mode 100644 board/liebherr/xea/MAINTAINERS create mode 100644 board/liebherr/xea/Makefile create mode 100644 board/liebherr/xea/README create mode 100644 board/liebherr/xea/spl_xea.c create mode 100644 board/liebherr/xea/xea.c create mode 100644 configs/imx28_xea_defconfig create mode 100644 include/configs/xea.h (limited to 'configs') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fd165844e4b..9d51d10f77a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -570,6 +570,9 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ vf610-pcm052.dtb \ vf610-bk4r1.dtb +dtb-$(CONFIG_MX28) += \ + imx28-xea.dtb + dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \ imx53-kp.dtb \ imx53-m53menlo.dtb diff --git a/arch/arm/dts/imx28-xea-u-boot.dtsi b/arch/arm/dts/imx28-xea-u-boot.dtsi new file mode 100644 index 00000000000..cc2ced5d2d4 --- /dev/null +++ b/arch/arm/dts/imx28-xea-u-boot.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + */ + +/* + * The minimal augmentation DTS U-Boot file to allow eMMC driver + * configuration in SPL for falcon boot. + */ +#include "imx28-u-boot.dtsi" +/ { + apb@80000000 { + u-boot,dm-spl; + + apbh@80000000 { + u-boot,dm-spl; + }; + + apbx@80040000 { + u-boot,dm-spl; + }; + }; +}; + +&clks { + u-boot,dm-spl; +}; + +&gpio0 { + u-boot,dm-spl; +}; + +&pinctrl { + u-boot,dm-spl; +}; + +&ssp0 { + u-boot,dm-spl; +}; + +&ssp3 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx28-xea.dts b/arch/arm/dts/imx28-xea.dts new file mode 100644 index 00000000000..5de6774c5a4 --- /dev/null +++ b/arch/arm/dts/imx28-xea.dts @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + */ + +/dts-v1/; + +#include "imx28.dtsi" + +/ { + model = "Liebherr (LWE) XEA i.MX28 Board"; + compatible = "lwe,xea", "fsl,imx28"; + + aliases { + spi3 = &ssp3; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x10000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_fec_3v3: regulator-fec-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fec-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>; + }; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-supply = <®_fec_3v3>; + phy-reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + phy-reset-post-delay = <1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_8bit_pins_a>; + bus-width = <8>; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; + +&ssp3 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins_b>; + status = "okay"; + spi-max-frequency = <40000000>; + num-cs = <2>; + + flash0: s25fl256s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <40000000>; + reg = <0>; + + partition@0 { + label = "SPL (spi)"; + reg = <0x0 0x10000>; + read-only; + }; + partition@1 { + label = "u-boot (spi)"; + reg = <0x10000 0x70000>; + read-only; + }; + partition@2 { + label = "uboot-env (spi)"; + reg = <0x80000 0x20000>; + }; + partition@3 { + label = "kernel (spi)"; + reg = <0x100000 0x400000>; + }; + partition@4 { + label = "swupdate (spi)"; + reg = <0x50000 0x800000>; + }; + }; +}; diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index 68072d5a1f2..b90d7b6e417 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -60,6 +60,9 @@ config TARGET_SC_SPS_1 config TARGET_TS4600 bool "Support TS4600" +config TARGET_XEA + bool "Support XEA" + endchoice config SYS_SOC @@ -67,6 +70,7 @@ config SYS_SOC source "board/bluegiga/apx4devkit/Kconfig" source "board/freescale/mx28evk/Kconfig" +source "board/liebherr/xea/Kconfig" source "board/ppcag/bg0900/Kconfig" source "board/schulercontrol/sc_sps_1/Kconfig" source "board/technologic/ts4600/Kconfig" diff --git a/board/liebherr/xea/Kconfig b/board/liebherr/xea/Kconfig new file mode 100644 index 00000000000..5428de46468 --- /dev/null +++ b/board/liebherr/xea/Kconfig @@ -0,0 +1,24 @@ +if TARGET_XEA + +config SYS_BOARD + default "xea" + +config SYS_VENDOR + default "liebherr" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "xea" + +config ENV_SIZE + default 0x2000 + +config ENV_SECT_SIZE + default 0x10000 if ENV_IS_IN_SPI_FLASH + +config ENV_OFFSET + default 0x80000 if ENV_IS_IN_SPI_FLASH + +endif diff --git a/board/liebherr/xea/MAINTAINERS b/board/liebherr/xea/MAINTAINERS new file mode 100644 index 00000000000..623184d0f8f --- /dev/null +++ b/board/liebherr/xea/MAINTAINERS @@ -0,0 +1,6 @@ +XEA BOARD +M: Lukasz Majewski +S: Maintained +F: board/liebherr/xea/ +F: include/configs/xea.h +F: configs/imx28_xea_defconfig diff --git a/board/liebherr/xea/Makefile b/board/liebherr/xea/Makefile new file mode 100644 index 00000000000..abf500857f6 --- /dev/null +++ b/board/liebherr/xea/Makefile @@ -0,0 +1,12 @@ +# +# (C) Copyright 2019 +# Lukasz Majewski, DENX Software Engineering, lukma@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := xea.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl_xea.o +endif diff --git a/board/liebherr/xea/README b/board/liebherr/xea/README new file mode 100644 index 00000000000..3e55d3ea43e --- /dev/null +++ b/board/liebherr/xea/README @@ -0,0 +1,63 @@ +Building SPL/U-Boot for xea board +================================= + +Setup environment, configure and build, e.g. by: + + $ make imx28_xea_defconfig + $ make -j4 u-boot.sb u-boot.img + +Now you should see u-boot.sb and u-boot.img files in the build directory. + + +Booting +======= + +The boot ROM loads SPL from SPI NOR flash into SRAM. SPL configures +DRAM and loads either a Linux kernel (falcon mode) or, if the rescue +pin is asserted, the main U-Boot. Both kernel and U-Boot reside in +eMMC boot partition 0. For redundancy, a copy of U-Boot is also +stored in SPI flash. If a valid kernel image is not found, U-Boot is +loaded from eMMC or, if this fails, SPI flash. + +Boot area layout +---------------- + +SPI NOR +Offset Function File +------------------------------------------ +0x00000000 SPL u-boot.sb +0x00010000 U-Boot u-boot.img +0x00080000 Environment + +eMMC +Offset Function File +------------------------------------------ +0x00000000 U-Boot u-boot.img +0x00080000 Devicetree imx28-bttc.dtb +0x00100000 Kernel uImage + + +Falcon mode +=========== + +In falcon mode, the default, SPL loads the kernel and devicetree +directly. For this to work, the stored devicetree must include +correct "memory" and "chosen" nodes as these are not updated by SPL +before booting the kernel. + + +Updating from U-Boot +==================== + +The default U-Boot environment includes command sequences to update +SPL, U-Boot, and kernel over TFTP. These are as follows: + +- update_spl: writes u-boot.sb to SPI NOR +- update_uboot: writes u-boot.img to eMMC and SPI NOR +- update_kernel: writes kernel and devicetree to eMMC + +They can be invoked at the U-Boot prompt using the "run" command, +e.g. "run update_spl" to update the SPL. + +These update commands download the above-named files from the +${hostname} directory on the server provided by DHCP. diff --git a/board/liebherr/xea/spl_xea.c b/board/liebherr/xea/spl_xea.c new file mode 100644 index 00000000000..d88b75bb3a4 --- /dev/null +++ b/board/liebherr/xea/spl_xea.c @@ -0,0 +1,303 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * DENX M28 Boot setup + * + * Copyright (C) 2019 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * Copyright (C) 2018 DENX Software Engineering + * MÃ¥ns RullgÃ¥rd, DENX Software Engineering, mans@mansr.com + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ + +#include +#include +#include +#include +#include +#include + +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_BOOT (MXS_PAD_3V3 | MXS_PAD_PULLUP) +#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) + +const iomux_cfg_t iomux_setup[] = { + /* AUART0 IRDA */ + MX28_PAD_AUART0_RX__AUART0_RX, + MX28_PAD_AUART0_TX__AUART0_TX, + + /* AUART 4 RS422 */ + MX28_PAD_AUART0_CTS__AUART4_RX, + MX28_PAD_AUART0_RTS__AUART4_TX, + + /* USB0 */ + MX28_PAD_AUART1_CTS__USB0_OVERCURRENT, + MX28_PAD_AUART1_RTS__USB0_ID, + MX28_PAD_LCD_VSYNC__GPIO_1_28, /* PRW_On */ + + /* USB1 */ + MX28_PAD_PWM2__USB1_OVERCURRENT, + + /* eMMC */ + MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DETECT__GPIO_2_9, /* Reset for eMMC */ + MX28_PAD_SSP0_SCK__SSP0_SCK | MUX_CONFIG_SSP0, + + /* DIG Keys */ + MX28_PAD_GPMI_D00__GPIO_0_0, + MX28_PAD_GPMI_D01__GPIO_0_1, + MX28_PAD_GPMI_D02__GPIO_0_2, + MX28_PAD_GPMI_D03__GPIO_0_3, + MX28_PAD_GPMI_D04__GPIO_0_4, + MX28_PAD_GPMI_D05__GPIO_0_5, + MX28_PAD_GPMI_D06__GPIO_0_6, + MX28_PAD_GPMI_D07__GPIO_0_7, + + /* ADR_0-2 */ + MX28_PAD_GPMI_CE1N__GPIO_0_17, + MX28_PAD_GPMI_CE2N__GPIO_0_18, + MX28_PAD_GPMI_CE3N__GPIO_0_19, + + /* Read Keys */ + MX28_PAD_GPMI_RDY0__GPIO_0_20, + + /* LATCH_EN */ + MX28_PAD_GPMI_RDY1__GPIO_0_21, + + /* Power off */ + MX28_PAD_GPMI_RDN__GPIO_0_24, + + /* I2C1 Touch */ + MX28_PAD_AUART2_CTS__GPIO_3_10, + MX28_PAD_AUART2_RTS__GPIO_3_11, + MX28_PAD_GPMI_RDY2__GPIO_0_22, /* Touch Reset */ + + /* TIVA */ + MX28_PAD_AUART1_RX__SSP2_CARD_DETECT, + MX28_PAD_SSP2_MISO__SSP2_D0, + MX28_PAD_SSP2_MOSI__SSP2_CMD, + MX28_PAD_SSP2_SCK__SSP2_SCK, + MX28_PAD_SSP2_SS0__SSP2_D3, + MX28_PAD_SSP2_SS1__GPIO_2_20, + MX28_PAD_SSP2_SS2__GPIO_2_21, + + /* SPI3 NOR-Flash */ + MX28_PAD_AUART1_TX__SSP3_CARD_DETECT, + MX28_PAD_AUART2_RX__SSP3_D1, + MX28_PAD_AUART2_TX__SSP3_D2, + MX28_PAD_SSP3_MISO__SSP3_D0, + MX28_PAD_SSP3_MOSI__SSP3_CMD, + MX28_PAD_SSP3_SCK__SSP3_SCK, + MX28_PAD_SSP3_SS0__SSP3_D3, + + /* NOR-Flash CMD */ + MX28_PAD_LCD_RS__GPIO_1_26, /* Hold */ + MX28_PAD_LCD_WR_RWN__GPIO_1_25, /* write protect */ + + /* I2C0 Codec */ + MX28_PAD_I2C0_SCL__I2C0_SCL, + MX28_PAD_I2C0_SDA__I2C0_SDA, + + /* I2S Codec */ + MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK, + MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK, + MX28_PAD_SAIF0_MCLK__SAIF0_MCLK, + MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0, + MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0, + + /* PWR-Hold */ + MX28_PAD_SPDIF__GPIO_3_27, + + /* EMI */ + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, + + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + + /* Uart3 Bluetooth-Interface */ + MX28_PAD_AUART3_CTS__AUART3_CTS, + MX28_PAD_AUART3_RTS__AUART3_RTS, + MX28_PAD_AUART3_RX__AUART3_RX, + MX28_PAD_AUART3_TX__AUART3_TX, + + /* framebuffer */ + MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, + MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD, + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD, + MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, + MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD, + + /* DUART RS232 */ + MX28_PAD_PWM0__DUART_RX, + MX28_PAD_PWM1__DUART_TX, + + /* FEC Ethernet */ + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, + MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RX_CLK__GPIO_4_13, /* Phy Interrupt */ + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TX_CLK__GPIO_4_5, /* n.c. */ + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_SSP1_CMD__GPIO_2_13, /* PHY reset */ + + /* TIVA boot control */ + MX28_PAD_GPMI_RDY3__GPIO_0_23 | MUX_CONFIG_BOOT, /* TIVA0 */ + MX28_PAD_GPMI_WRN__GPIO_0_25 | MUX_CONFIG_BOOT, /* TIVA1 */ +}; + +u32 mxs_dram_vals[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010101, 0x01010101, + 0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101, + 0x00000100, 0x00000100, 0x00000000, 0x00000002, + 0x01010000, 0x07080403, 0x07005303, 0x0b0000c8, + 0x0200a0c1, 0x0002040c, 0x0038430a, 0x04290322, + 0x02040203, 0x00c8002b, 0x00000000, 0x00000000, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000612, 0x01000102, + 0x06120612, 0x00000200, 0x00020007, 0xf4004a27, + 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07400300, + 0x07400300, 0x07400300, 0x07400300, 0x00000005, + 0x00000000, 0x00000000, 0x01000000, 0x00000000, + 0x00000001, 0x000f1133, 0x00000000, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010000, 0x00030404, + 0x00000002, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x01010000, + 0x01000000, 0x03030000, 0x00010303, 0x01020202, + 0x00000000, 0x02040101, 0x21002103, 0x00061200, + 0x06120612, 0x00000642, 0x00000000, 0x00000004, + 0x00000000, 0x00000080, 0x00000000, 0x00000000, + 0x00000000, 0xffffffff +}; + +void lowlevel_init(void) +{ + struct mxs_pinctrl_regs *pinctrl_regs = + (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE; + + /* Set EMI drive strength */ + writel(0x00003fff, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_clr); + writel(0x00002aaa, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); + + mxs_common_spl_init(0, NULL, iomux_setup, ARRAY_SIZE(iomux_setup)); +} diff --git a/board/liebherr/xea/xea.c b/board/liebherr/xea/xea.c new file mode 100644 index 00000000000..1d47f67a7f9 --- /dev/null +++ b/board/liebherr/xea/xea.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * XEA iMX28 board + * + * Copyright (C) 2019 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * Copyright (C) 2018 DENX Software Engineering + * MÃ¥ns RullgÃ¥rd, DENX Software Engineering, mans@mansr.com + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SPL_BUILD +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ + +static void init_clocks(void) +{ + /* IO0 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK0, 480000); + /* IO1 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK1, 480000); + + /* SSP0 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); + /* SSP2 clock at 160MHz */ + mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); + /* SSP3 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK3, 96000, 0); +} + +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong arg) +{ + init_clocks(); + preloader_console_init(); +} + +static int boot_tiva0, boot_tiva1; + +/* Check if TIVAs request booting via U-Boot proper */ +void spl_board_init(void) +{ + struct gpio_desc btiva0, btiva1; + int ret; + + ret = dm_gpio_lookup_name("GPIO0_23", &btiva0); + if (ret) + printf("Cannot get GPIO0_23\n"); + + ret = dm_gpio_lookup_name("GPIO0_25", &btiva1); + if (ret) + printf("Cannot get GPIO0_25\n"); + + ret = dm_gpio_request(&btiva0, "boot-tiva0"); + if (ret) + printf("Cannot request GPIO0_23\n"); + + ret = dm_gpio_request(&btiva1, "boot-tiva1"); + if (ret) + printf("Cannot request GPIO0_25\n"); + + dm_gpio_set_dir_flags(&btiva0, GPIOD_IS_IN); + dm_gpio_set_dir_flags(&btiva1, GPIOD_IS_IN); + + udelay(1000); + + boot_tiva0 = dm_gpio_get_value(&btiva0); + boot_tiva1 = dm_gpio_get_value(&btiva1); +} + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = BOOT_DEVICE_MMC1; + spl_boot_list[1] = BOOT_DEVICE_SPI; +} + +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + debug("%s: btiva0: %d btiva1: %d\n", __func__, boot_tiva0, boot_tiva1); + return !boot_tiva0 || !boot_tiva1; +} +#else + +int board_early_init_f(void) +{ + init_clocks(); + + return 0; +} + +int board_init(void) +{ + struct gpio_desc phy_rst; + int ret; + + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + cpu_eth_init(NULL); + + /* PHY INT#/PWDN# */ + ret = dm_gpio_lookup_name("GPIO4_13", &phy_rst); + if (ret) { + printf("Cannot get GPIO4_13\n"); + return ret; + } + + ret = dm_gpio_request(&phy_rst, "phy-rst"); + if (ret) { + printf("Cannot request GPIO4_13\n"); + return ret; + } + + dm_gpio_set_dir_flags(&phy_rst, GPIOD_IS_IN); + udelay(1000); + + return 0; +} + +int dram_init(void) +{ + return mxs_dram_init(); +} + +#endif /* CONFIG_SPL_BUILD */ diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig new file mode 100644 index 00000000000..aaa7e31a932 --- /dev/null +++ b/configs/imx28_xea_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_THUMB_BUILD=y +CONFIG_ARCH_MX28=y +CONFIG_SYS_TEXT_BASE=0x40002000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x800 +CONFIG_SPL_DM_SPI=y +CONFIG_TARGET_XEA=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_TEXT_BASE=0x1000 +CONFIG_FIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0 +CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y +CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DM_GPIO=y +CONFIG_SPL_FORCE_MMC_BOOT=y +CONFIG_SPL_MMC_TINY=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_PAYLOAD="u-boot.img" +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_SPL=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +# CONFIG_CMD_PINMUX is not set +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi3.0" +CONFIG_MTDPARTS_DEFAULT="spi3.0:64k(SPL),448k(uboot),128k(envs),384k(unused1),4096k(kernel),8192k(swupdate),-(unused2)" +CONFIG_DOS_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx28-xea" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent interrupts" +CONFIG_SPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_ENV_SPI_BUS=y +CONFIG_ENV_SPI_BUS=3 +CONFIG_USE_ENV_SPI_CS=y +CONFIG_ENV_SPI_CS=0 +CONFIG_USE_ENV_SPI_MAX_HZ=y +CONFIG_ENV_SPI_MAX_HZ=40000000 +CONFIG_USE_ENV_SPI_MODE=y +CONFIG_ENV_SPI_MODE=0x0 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_DEVRES=y +CONFIG_DM_GPIO=y +CONFIG_MXS_GPIO=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_MXS=y +CONFIG_MTD=y +CONFIG_MTD_DEVICE=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=3 +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ADDR=1 +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MXS=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_CONS_INDEX=0 +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXS_SPI=y +CONFIG_FS_FAT=y +# CONFIG_SPL_OF_LIBFDT is not set +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/xea.h b/include/configs/xea.h new file mode 100644 index 00000000000..65109566d3b --- /dev/null +++ b/include/configs/xea.h @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * Copyright (C) 2018 DENX Software Engineering + * MÃ¥ns RullgÃ¥rd, DENX Software Engineering, mans@mansr.com + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ +#ifndef __CONFIGS_XEA_H__ +#define __CONFIGS_XEA_H__ + +#include + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* SPL */ +#define CONFIG_SPL_STACK 0x20000 + +#define CONFIG_SYS_SPL_ARGS_ADDR 0x44000000 + +#define CONFIG_SYS_SPI_KERNEL_OFFS SZ_1M +#define CONFIG_SYS_SPI_ARGS_OFFS SZ_512K +#define CONFIG_SYS_SPI_ARGS_SIZE SZ_32K + +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (SZ_512K / 0x200) +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (SZ_32K / 0x200) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (SZ_1M / 0x200) + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SPI_FLASH_MTD +#endif + +/* Memory configuration */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Environment */ +#define CONFIG_ENV_OVERWRITE + +/* Booting Linux */ +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " +#define CONFIG_BOOTCOMMAND "run ${bootpri} ; run ${bootsec}" +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Extra Environment */ +#define CONFIG_PREBOOT "run prebootcmd" +#define CONFIG_HOSTNAME "xea" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootmode=update\0" \ + "bootpri=mmc_mmc\0" \ + "bootsec=sf_swu\0" \ + "consdev=ttyAMA0\0" \ + "baudrate=115200\0" \ + "dtbaddr=0x44000000\0" \ + "dtbfile=imx28-xea.dtb\0" \ + "rootdev=/dev/mmcblk0p2\0" \ + "netdev=eth0\0" \ + "rdaddr=0x43000000\0" \ + "swufile=swupdate.img\0" \ + "sf_kernel_offset=0x100000\0" \ + "sf_kernel_size=0x400000\0" \ + "sf_swu_offset=0x500000\0" \ + "sf_swu_size=0x800000\0" \ + "rootpath=/opt/eldk-5.5/armv5te/rootfs-qte-sdk\0" \ + "do_update_mmc=" \ + "if mmc rescan ; then " \ + "mmc dev 0 ${update_mmc_part} ; " \ + "if dhcp ${hostname}/${update_filename} ; then " \ + "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ + "setexpr fw_sz ${fw_sz} + 1 ; " \ + "mmc write ${loadaddr} ${update_offset} ${fw_sz} ; " \ + "fi ; " \ + "fi\0" \ + "do_update_sf=" \ + "if sf probe ; then " \ + "if dhcp ${hostname}/${update_filename} ; then " \ + "sf erase ${update_offset} +${filesize} ; " \ + "sf write ${loadaddr} ${update_offset} ${filesize} ; " \ + "fi ; " \ + "fi\0" \ + "update_spl_filename=u-boot.sb\0" \ + "update_spl=" \ + "setenv update_filename ${update_spl_filename} ; " \ + "setenv update_offset 0 ; " \ + "run do_update_sf\0" \ + "update_uboot_filename=u-boot.img\0" \ + "update_uboot=" \ + "setenv update_filename ${update_uboot_filename} ; " \ + "setenv update_offset 0x10000 ; " \ + "run do_update_sf ; " \ + "setenv update_mmc_part 1 ; " \ + "setenv update_offset 0 ; " \ + "run do_update_mmc\0" \ + "update_kernel_filename=uImage\0" \ + "update_kernel=" \ + "setenv update_mmc_part 1 ; " \ + "setenv update_filename ${update_kernel_filename} ; " \ + "setenv update_offset 0x800 ; " \ + "run do_update_mmc ; " \ + "setenv update_filename ${dtbfile} ; " \ + "setenv update_offset 0x400 ; " \ + "run do_update_mmc\0" \ + "update_sfkernel=" \ + "setenv update_filename fitImage ; " \ + "setenv update_offset ${sf_kernel_offset} ; " \ + "run do_update_sf\0" \ + "update_swu=" \ + "setenv update_filename ${swufile} ; " \ + "setenv update_offset ${sf_swu_offset} ; " \ + "run do_update_sf\0" \ + "addcons=" \ + "setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "addip=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off\0" \ + "addmisc=" \ + "setenv bootargs ${bootargs} ${miscargs}\0" \ + "addargs=run addcons addmisc\0" \ + "mmcload=" \ + "mmc rescan ; " \ + "mmc dev 0 1 ; " \ + "mmc read ${loadaddr} 0x800 0x2000 ; " \ + "mmc read ${dtbaddr} 0x400 0x80\0" \ + "netload=" \ + "dhcp ${loadaddr} ${hostname}/${bootfile} ; " \ + "tftp ${dtbaddr} ${hostname}/${dtbfile}\0" \ + "sfload=" \ + "sf probe ; " \ + "sf read ${loadaddr} ${sf_kernel_offset} ${sf_kernel_size}\0" \ + "usbload=" \ + "usb start ; " \ + "load usb 0:1 ${loadaddr} ${bootfile}\0" \ + "miscargs=panic=1\0" \ + "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ + "nfsargs=" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ + "mmc_mmc=" \ + "if run mmcload mmcargs addargs ; then " \ + "bootm ${loadaddr} - ${dtbaddr} ; " \ + "fi\0" \ + "mmc_nfs=" \ + "if run mmcload nfsargs addip addargs ; then " \ + "bootm ${loadaddr} - ${dtbaddr} ; " \ + "fi\0" \ + "sf_mmc=" \ + "if run sfload mmcargs addargs ; then " \ + "bootm ${loadaddr} - ${dtbaddr} ; " \ + "fi\0" \ + "sf_swu=" \ + "if run sfload ; then " \ + "sf read ${rdaddr} ${sf_swu_offset} ${sf_swu_size} ; " \ + "setenv bootargs root=/dev/ram0 rw ; " \ + "run addargs ; " \ + "bootm ${loadaddr} ${rdaddr} ; " \ + "fi\0" \ + "net_mmc=" \ + "if run netload mmcargs addargs ; then " \ + "bootm ${loadaddr} - ${dtbaddr} ; " \ + "fi\0" \ + "net_nfs=" \ + "if run netload nfsargs addip addargs ; then " \ + "bootm ${loadaddr} - ${dtbaddr} ; " \ + "fi\0" \ + "prebootcmd=" \ + "if test \"${envsaved}\" != y ; then ; " \ + "setenv envsaved y ; " \ + "saveenv ; " \ + "fi ; " \ + "if test \"${bootmode}\" = normal ; then " \ + "setenv bootdelay 0 ; " \ + "setenv bootpri mmc_mmc ; " \ + "elif test \"${bootmode}\" = devel ; then " \ + "setenv bootdelay 3 ; " \ + "setenv bootpri net_mmc ; " \ + "else " \ + "if test \"${bootmode}\" != update ; then " \ + "echo Warning: unknown bootmode \"${bootmode}\" ; " \ + "fi ; " \ + "setenv bootdelay 1 ; " \ + "setenv bootpri sf_swu ; " \ + "fi\0" + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_XEA_H__ */ -- cgit v1.3.1 From 8c26739859c605d803b89f6ae202c6d29d2d2a54 Mon Sep 17 00:00:00 2001 From: Robert Beckett Date: Tue, 12 Nov 2019 19:15:11 +0000 Subject: board: ge: bx50v3: sync devicetrees from Linux Copy device trees from linux, keeping them as separate files for each board to ease future sync. Update board code to use generic bx50v3 dt initially, then select the specific dt based on board detection. Signed-off-by: Robert Beckett --- arch/arm/dts/Makefile | 7 +- arch/arm/dts/imx6q-b450v3.dts | 160 +++++++++++ arch/arm/dts/imx6q-b650v3.dts | 159 ++++++++++ arch/arm/dts/imx6q-b850v3.dts | 302 +++++++++++++++++++ arch/arm/dts/imx6q-ba16.dtsi | 640 +++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/imx6q-bx50v3.dts | 78 +---- arch/arm/dts/imx6q-bx50v3.dtsi | 380 ++++++++++++++++++++++++ board/ge/bx50v3/bx50v3.c | 34 ++- configs/ge_bx50v3_defconfig | 5 + 9 files changed, 1689 insertions(+), 76 deletions(-) create mode 100644 arch/arm/dts/imx6q-b450v3.dts create mode 100644 arch/arm/dts/imx6q-b650v3.dts create mode 100644 arch/arm/dts/imx6q-b850v3.dts create mode 100644 arch/arm/dts/imx6q-ba16.dtsi create mode 100644 arch/arm/dts/imx6q-bx50v3.dtsi (limited to 'configs') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9d51d10f77a..77608d2313b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -851,7 +851,12 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt8516-pumpkin.dtb \ mt8518-ap1-emmc.dtb -dtb-$(CONFIG_TARGET_GE_BX50V3) += imx6q-bx50v3.dtb +dtb-$(CONFIG_TARGET_GE_BX50V3) += \ + imx6q-bx50v3.dtb \ + imx6q-b850v3.dtb \ + imx6q-b650v3.dtb \ + imx6q-b450v3.dtb + dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb dtb-$(CONFIG_TARGET_VEXPRESS_CA5X2) += vexpress-v2p-ca5s.dtb diff --git a/arch/arm/dts/imx6q-b450v3.dts b/arch/arm/dts/imx6q-b450v3.dts new file mode 100644 index 00000000000..7fca833cbf9 --- /dev/null +++ b/arch/arm/dts/imx6q-b450v3.dts @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2015 Timesys Corporation. + * Copyright 2015 General Electric Company + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q-bx50v3.dtsi" + +/ { + model = "General Electric B450v3"; + compatible = "ge,imx6q-b450v3", "advantech,imx6q-ba16", "fsl,imx6q"; + + chosen { + stdout-path = &uart3; + }; + + panel-lvds0 { + compatible = "innolux,g121x1-l03"; + backlight = <&backlight_lvds>; + power-supply = <®_lvds>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&pca9539 { + P04 { + gpio-hog; + gpios = <4 0>; + output-low; + line-name = "PCA9539-P04"; + }; + + P07 { + gpio-hog; + gpios = <7 0>; + output-low; + line-name = "PCA9539-P07"; + }; +}; + +&pci_root { + /* Intel Corporation I210 Gigabit Network Connection */ + switch_nic: ethernet@3,0 { + compatible = "pci8086,1533"; + reg = <0x00010000 0 0 0 0>; + }; +}; + +&switch_ports { + port@0 { + reg = <0>; + label = "enacq"; + phy-handle = <&switchphy0>; + }; + + port@1 { + reg = <1>; + label = "eneport1"; + phy-handle = <&switchphy1>; + }; + + port@2 { + reg = <2>; + label = "enix"; + phy-handle = <&switchphy2>; + }; + + port@3 { + reg = <3>; + label = "enid"; + phy-handle = <&switchphy3>; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&switch_nic>; + phy-handle = <&switchphy4>; + }; + + port@5 { + reg = <5>; + label = "enembc"; + + /* connected to Ethernet MAC of AT91RM9200 in MII mode */ + fixed-link { + speed = <100>; + full-duplex; + }; + }; +}; diff --git a/arch/arm/dts/imx6q-b650v3.dts b/arch/arm/dts/imx6q-b650v3.dts new file mode 100644 index 00000000000..ba12e9be5fb --- /dev/null +++ b/arch/arm/dts/imx6q-b650v3.dts @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2015 Timesys Corporation. + * Copyright 2015 General Electric Company + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q-bx50v3.dtsi" + +/ { + model = "General Electric B650v3"; + compatible = "ge,imx6q-b650v3", "advantech,imx6q-ba16", "fsl,imx6q"; + + chosen { + stdout-path = &uart3; + }; + + panel-lvds0 { + compatible = "innolux,g121x1-l03"; + backlight = <&backlight_lvds>; + power-supply = <®_lvds>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&pca9539 { + P07 { + gpio-hog; + gpios = <7 0>; + output-low; + line-name = "PCA9539-P07"; + }; +}; + +&usbphy1 { + fsl,tx-cal-45-dn-ohms = <55>; + fsl,tx-cal-45-dp-ohms = <55>; + fsl,tx-d-cal = <100>; +}; + +&pci_root { + /* Intel Corporation I210 Gigabit Network Connection */ + switch_nic: ethernet@3,0 { + compatible = "pci8086,1533"; + reg = <0x00010000 0 0 0 0>; + }; +}; + +&switch_ports { + port@0 { + reg = <0>; + label = "enacq"; + phy-handle = <&switchphy0>; + }; + + port@1 { + reg = <1>; + label = "eneport1"; + phy-handle = <&switchphy1>; + }; + + port@2 { + reg = <2>; + label = "enix"; + phy-handle = <&switchphy2>; + }; + + port@3 { + reg = <3>; + label = "enid"; + phy-handle = <&switchphy3>; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&switch_nic>; + phy-handle = <&switchphy4>; + }; + + port@5 { + reg = <5>; + label = "enembc"; + + /* connected to Ethernet MAC of AT91RM9200 in MII mode */ + fixed-link { + speed = <100>; + full-duplex; + }; + }; +}; diff --git a/arch/arm/dts/imx6q-b850v3.dts b/arch/arm/dts/imx6q-b850v3.dts new file mode 100644 index 00000000000..0a985526912 --- /dev/null +++ b/arch/arm/dts/imx6q-b850v3.dts @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2015 Timesys Corporation. + * Copyright 2015 General Electric Company + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q-bx50v3.dtsi" + +/ { + model = "General Electric B850v3"; + compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q"; + + chosen { + stdout-path = &uart3; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; +}; + +&ldb { + fsl,dual-channel; + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&stdp4028_in>; + }; + }; + }; +}; + +&i2c2 { + pca9547_ddc: mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + mux2_i2c1: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + mux2_i2c2: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + mux2_i2c3: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + mux2_i2c4: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + mux2_i2c5: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + + mux2_i2c6: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + + mux2_i2c7: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + + mux2_i2c8: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&mux2_i2c1>; +}; + +&mux1_i2c1 { + ads7830@4a { + compatible = "ti,ads7830"; + reg = <0x4a>; + }; +}; + +&mux2_i2c2 { + clock-frequency = <100000>; + + stdp2690@72 { + compatible = "megachips,stdp2690-ge-b850v3-fw"; + reg = <0x72>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + stdp2690_in: endpoint { + remote-endpoint = <&stdp4028_out>; + }; + }; + + port@1 { + reg = <1>; + + stdp2690_out: endpoint { + /* Connector for external display */ + }; + }; + }; + }; + + stdp4028@73 { + compatible = "megachips,stdp4028-ge-b850v3-fw"; + reg = <0x73>; + interrupt-parent = <&gpio2>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + stdp4028_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@1 { + reg = <1>; + + stdp4028_out: endpoint { + remote-endpoint = <&stdp2690_in>; + }; + }; + }; + }; +}; + +&pca9539 { + P10 { + gpio-hog; + gpios = <8 0>; + output-low; + line-name = "PCA9539-P10"; + }; + + P11 { + gpio-hog; + gpios = <9 0>; + output-low; + line-name = "PCA9539-P11"; + }; +}; + +&pci_root { + /* PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch */ + bridge@1,0 { + compatible = "pci10b5,8605"; + reg = <0x00010000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + bridge@2,1 { + compatible = "pci10b5,8605"; + reg = <0x00020800 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + /* Intel Corporation I210 Gigabit Network Connection */ + ethernet@3,0 { + compatible = "pci8086,1533"; + reg = <0x00030000 0 0 0 0>; + }; + }; + + bridge@2,2 { + compatible = "pci10b5,8605"; + reg = <0x00021000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + /* Intel Corporation I210 Gigabit Network Connection */ + switch_nic: ethernet@4,0 { + compatible = "pci8086,1533"; + reg = <0x00040000 0 0 0 0>; + }; + }; + }; +}; + +&switch_ports { + port@0 { + reg = <0>; + label = "eneport1"; + phy-handle = <&switchphy0>; + }; + + port@1 { + reg = <1>; + label = "eneport2"; + phy-handle = <&switchphy1>; + }; + + port@2 { + reg = <2>; + label = "enix"; + phy-handle = <&switchphy2>; + }; + + port@3 { + reg = <3>; + label = "enid"; + phy-handle = <&switchphy3>; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&switch_nic>; + phy-handle = <&switchphy4>; + }; +}; diff --git a/arch/arm/dts/imx6q-ba16.dtsi b/arch/arm/dts/imx6q-ba16.dtsi new file mode 100644 index 00000000000..7d8f61f2fd7 --- /dev/null +++ b/arch/arm/dts/imx6q-ba16.dtsi @@ -0,0 +1,640 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Support for imx6 based Advantech DMS-BA16 Qseven module + * + * Copyright 2015 Timesys Corporation. + * Copyright 2015 General Electric Company + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx6q.dtsi" +#include + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + backlight_lvds: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_display>; + pwms = <&pwm1 0 5000000>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 101 102 103 104 105 106 107 108 109 + 110 111 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 128 129 + 130 131 132 133 134 135 136 137 138 139 + 140 141 142 143 144 145 146 147 148 149 + 150 151 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 168 169 + 170 171 172 173 174 175 176 177 178 179 + 180 181 182 183 184 185 186 187 188 189 + 190 191 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 208 209 + 210 211 212 213 214 215 216 217 218 219 + 220 221 222 223 224 225 226 227 228 229 + 230 231 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 248 249 + 250 251 252 253 254 255>; + default-brightness-level = <255>; + enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_lvds: regulator-lvds { + compatible = "regulator-fixed"; + regulator-name = "lvds_ppen"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_h1_vbus: regulator-usbh1vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg_vbus: regulator-usbotgvbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: n25q032@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0xc0000>; + }; + + partition@c0000 { + label = "env"; + reg = <0xc0000 0x10000>; + }; + + partition@d0000 { + label = "spare"; + reg = <0xd0000 0x320000>; + }; + + partition@3f0000 { + label = "mfg"; + reg = <0x3f0000 0x10000>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio7>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + + onkey { + compatible = "dlg,da9063-onkey"; + }; + + regulators { + vdd_bcore1: bcore1 { + regulator-min-microvolt = <1420000>; + regulator-max-microvolt = <1420000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_bcore2: bcore2 { + regulator-min-microvolt = <1420000>; + regulator-max-microvolt = <1420000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_bpro: bpro { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_bmem: bmem { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_bio: bio { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_bperi: bperi { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ldo1: ldo1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1860000>; + }; + + vdd_ldo2: ldo2 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1860000>; + }; + + vdd_ldo3: ldo3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3440000>; + }; + + vdd_ldo4: ldo4 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3440000>; + }; + + vdd_ldo5: ldo5 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + + vdd_ldo6: ldo6 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + + vdd_ldo7: ldo7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + + vdd_ldo8: ldo8 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + + vdd_ldo9: ldo9 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <3600000>; + }; + + vdd_ldo10: ldo10 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + + vdd_ldo11: ldo11 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + rtc@32 { + compatible = "epson,rx8010"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + reg = <0x32>; + interrupt-parent = <&gpio4>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + fsl,tx-swing-full = <103>; + fsl,tx-swing-low = <103>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "disabled"; +}; + +&sata { + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhub>; + vbus-supply = <®_usb_h1_vbus>; + reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>; + bus-width = <8>; + vmmc-supply = <&vdd_bperi>; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; + + pinctrl_display: dispgrp { + fsl,pins = < + /* BLEN_OUT */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + /* LVDS_PPEN_OUT */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* SPI1 CS */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; + + pinctrl_ecspi5: ecspi5grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b0b0 + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x1b0b0 + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x1b0b0 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + /* FEC Reset */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + /* AR8033 Interrupt */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* GPIO 0-7 */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b0 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 + /* SUS_S3_OUT to CPLD */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + /* PCIe Reset */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + /* PCIe Wake */ + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + /* PMIC Interrupt */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + /* RTC_INT */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbhub: usbhubgrp { + fsl,pins = < + /* HUB_RESET */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + /* uSDHC2 CD */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_reset: usdhc3grp-reset { + fsl,pins = < + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + /* uSDHC4 CD */ + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 + /* uSDHC4 SDIO PWR */ + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 + /* uSDHC4 SDIO WP */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 + /* uSDHC4 SDIO LED */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6q-bx50v3.dts b/arch/arm/dts/imx6q-bx50v3.dts index deaec635093..a44d7004cbe 100644 --- a/arch/arm/dts/imx6q-bx50v3.dts +++ b/arch/arm/dts/imx6q-bx50v3.dts @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR X11 */ +// SPDX-License-Identifier: GPL-2.0+ OR X11 /* * Copyright 2015 Timesys Corporation. * Copyright 2018 General Electric Company @@ -7,83 +7,13 @@ /dts-v1/; -#include "imx6q.dtsi" -#include +#include "imx6q-bx50v3.dtsi" / { model = "General Electric Bx50v3"; compatible = "ge,imx6q-bx50v3", "advantech,imx6q-ba16", "fsl,imx6q"; -}; - -&iomuxc { - pinctrl-names = "default"; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - /* SPI1 CS */ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3_reset: usdhc3grp-reset { - fsl,pins = < - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9 - >; - }; -}; - -&usdhc1 { - status = "disabled"; -}; - -&usdhc2 { - status = "disabled"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>; - bus-width = <8>; - non-removable; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc4 { - status = "disabled"; -}; - -/* SPI NOR */ -&ecspi1 { - cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - flash: n25q032@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <20000000>; - reg = <0>; + chosen { + stdout-path = &uart3; }; }; diff --git a/arch/arm/dts/imx6q-bx50v3.dtsi b/arch/arm/dts/imx6q-bx50v3.dtsi new file mode 100644 index 00000000000..009f88e305d --- /dev/null +++ b/arch/arm/dts/imx6q-bx50v3.dtsi @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2015 Timesys Corporation. + * Copyright 2015 General Electric Company + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx6q-ba16.dtsi" + +/ { + mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <22000000>; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + + reg_wl18xx_vmmc: regulator-wl18xx { + compatible = "regulator-fixed"; + regulator-name = "vwl1807"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9539 3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + reg_wlan: regulator-wlan { + compatible = "regulator-fixed"; + regulator-name = "3P3V_wlan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio6 14 GPIO_ACTIVE_HIGH>; + }; + + sound { + compatible = "fsl,imx6q-ba16-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-ba16-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; + + aliases { + mdio-gpio0 = &mdio0; + }; + + mdio0: mdio-gpio { + compatible = "virtual,mdio-gpio"; + gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>, /* mdc */ + <&gpio2 7 GPIO_ACTIVE_HIGH>; /* mdio */ + + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "marvell,mv88e6085"; /* 88e6240*/ + reg = <0>; + + switch_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switchphy0: switchphy@0 { + reg = <0>; + }; + + switchphy1: switchphy@1 { + reg = <1>; + }; + + switchphy2: switchphy@2 { + reg = <2>; + }; + + switchphy3: switchphy@3 { + reg = <3>; + }; + + switchphy4: switchphy@4 { + reg = <4>; + }; + }; + }; + }; +}; + +&ecspi5 { + cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5>; + status = "okay"; + + m25_eeprom: m25p80@0 { + compatible = "atmel,at25"; + spi-max-frequency = <10000000>; + size = <0x8000>; + pagesize = <64>; + reg = <0>; + address-width = <16>; + }; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; + + pca9547: mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + mux1_i2c1: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + ads7830: ads7830@48 { + compatible = "ti,ads7830"; + reg = <0x48>; + }; + + mma8453: mma8453@1c { + compatible = "fsl,mma8453"; + reg = <0x1c>; + }; + }; + + mux1_i2c2: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + + eeprom: eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + }; + + mpl3115: mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; + }; + + mux1_i2c3: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + mux1_i2c4: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&mclk>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_3p3v>; + }; + }; + + mux1_i2c5: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + + pca9539: pca9539@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio2>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + P12 { + gpio-hog; + gpios = <10 0>; + output-low; + line-name = "PCA9539-P12"; + }; + + P13 { + gpio-hog; + gpios = <11 0>; + output-low; + line-name = "PCA9539-P13"; + }; + + P14 { + gpio-hog; + gpios = <12 0>; + output-low; + line-name = "PCA9539-P14"; + }; + + P15 { + gpio-hog; + gpios = <13 0>; + output-low; + line-name = "PCA9539-P15"; + }; + + P16 { + gpio-hog; + gpios = <14 0>; + output-low; + line-name = "PCA9539-P16"; + }; + + P17 { + gpio-hog; + gpios = <15 0>; + output-low; + line-name = "PCA9539-P17"; + }; + }; + }; + + mux1_i2c6: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + + mux1_i2c7: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + + mux1_i2c8: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; +}; + +&iomuxc { + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 + >; + }; +}; + +&pmu { + secure-reg-access; +}; + +&usdhc2 { + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + vmmc-supply = <®_wl18xx_vmmc>; + no-1-8-v; + non-removable; + wakeup-source; + keep-power-in-suspend; + cap-power-off-card; + max-frequency = <25000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; + tcxo-clock-frequency = <26000000>; + }; +}; + +&pcie { + /* Synopsys, Inc. Device */ + pci_root: root@0,0 { + compatible = "pci16c3,abcd"; + reg = <0x00000000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + }; +}; diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 2f6747b70a3..5a5f6abb8e1 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -32,12 +32,13 @@ #include #include #include +#include #include "../common/ge_common.h" #include "../common/vpd_reader.h" #include "../../../drivers/net/e1000.h" DECLARE_GLOBAL_DATA_PTR; -static int confidx = 3; /* Default to b850v3. */ +static int confidx; /* Default to generic. */ static struct vpd_cache vpd; #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ @@ -553,8 +554,16 @@ int board_init(void) setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); if (!read_vpd(&vpd, vpd_callback)) { + int ret, rescan; + vpd.is_read = true; set_confidx(&vpd); + + ret = fdtdec_resetup(&rescan); + if (!ret && rescan) { + dm_uninit(); + dm_init_and_scan(false); + } } gpio_request(SUS_S3_OUT, "sus_s3_out"); @@ -729,3 +738,26 @@ U_BOOT_CMD( "enable Bx50 backlight", "" ); + +int board_fit_config_name_match(const char *name) +{ + if (!vpd.is_read) + return strcmp(name, "imx6q-bx50v3"); + + switch (vpd.product_id) { + case VPD_PRODUCT_B450: + return strcmp(name, "imx6q-b450v3"); + case VPD_PRODUCT_B650: + return strcmp(name, "imx6q-b650v3"); + case VPD_PRODUCT_B850: + return strcmp(name, "imx6q-b850v3"); + default: + return -1; + } +} + +int embedded_dtb_select(void) +{ + vpd.is_read = false; + return fdtdec_setup(); +} diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 6b2d6c173ad..d7350891512 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -16,6 +16,8 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=1 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SUPPORT_RAW_INITRD=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_LAST_STAGE_INIT=y @@ -36,6 +38,9 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_DOS_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-bx50v3" +CONFIG_OF_LIST="imx6q-bx50v3 imx6q-b850v3 imx6q-b650v3 imx6q-b450v3" +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y -- cgit v1.3.1 From 05de20082d93af63bad4deb72e883144f2010c53 Mon Sep 17 00:00:00 2001 From: Ian Ray Date: Tue, 12 Nov 2019 19:15:13 +0000 Subject: configs: bx50v3: Fix boot hang with video Fixes commit: 0b09f7b15052bb419e318e38da453be46e5a13e5, which converted to DM_VIDEO, but requires more memory. [Inspired by 9002e735e71754a90adbb9676c0ffb1964dbc288] Signed-off-by: Ian Ray Signed-off-by: Robert Beckett --- configs/ge_bx50v3_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'configs') diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index d7350891512..f5f471e0a8d 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -73,3 +73,4 @@ CONFIG_VIDEO_IPUV3=y CONFIG_WATCHDOG_TIMEOUT_MSECS=6000 CONFIG_IMX_WATCHDOG=y # CONFIG_EFI_LOADER is not set +CONFIG_SYS_MALLOC_F_LEN=0x4000 -- cgit v1.3.1 From c6b31ca1868c48bf06aed638822a34cd16f48fe0 Mon Sep 17 00:00:00 2001 From: Ian Ray Date: Tue, 12 Nov 2019 19:15:15 +0000 Subject: board: ge: bx50v3: Fix message output to video console Use vidconsole for output to the LCD, now that DM_VIDEO is used. Write white text on a black background, like before migrating to DM_VIDEO. Signed-off-by: Ian Ray Signed-off-by: Robert Beckett --- board/ge/bx50v3/bx50v3.c | 21 ++++++++++++++------- configs/ge_bx50v3_defconfig | 1 + include/configs/ge_bx50v3.h | 9 ++++----- 3 files changed, 19 insertions(+), 12 deletions(-) (limited to 'configs') diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 59ec9a0d240..df2d22b61fe 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -219,13 +219,6 @@ static void do_enable_hdmi(struct display_info_t const *dev) imx_enable_hdmi_phy(); } -int board_cfb_skip(void) -{ - gpio_direction_output(LVDS_POWER_GP, 1); - - return 0; -} - static int is_b850v3(void) { return confidx == 3; @@ -713,8 +706,14 @@ int ft_board_setup(void *blob, bd_t *bd) static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { +#if CONFIG_IS_ENABLED(DM_VIDEO) + int ret; + struct udevice *dev; + #ifdef CONFIG_VIDEO_IPUV3 if (!is_b850v3()) { + gpio_direction_output(LVDS_POWER_GP, 1); + /* We need at least 200ms between power on and backlight on * as per specifications from CHI MEI */ @@ -733,6 +732,14 @@ static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * cons } #endif + /* Probe, to find a video device to be used to show a message on + * the vidconsole. + */ + ret = uclass_get_device(UCLASS_VIDEO, 0, &dev); + if (ret) + return ret; +#endif + return 0; } diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index f5f471e0a8d..7d811f5f9b3 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -74,3 +74,4 @@ CONFIG_WATCHDOG_TIMEOUT_MSECS=6000 CONFIG_IMX_WATCHDOG=y # CONFIG_EFI_LOADER is not set CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 73cdc5b489f..9f8d388f522 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -114,12 +114,11 @@ "swappartitions=" \ "setexpr partnum 3 - ${partnum}\0" \ "failbootcmd=" \ + "echo reached failbootcmd; " \ "bx50_backlight_enable; " \ - "msg=\"Monitor failed to start. Try again, or contact GE Service for support.\"; " \ - "echo $msg; " \ - "setenv stdout vga; " \ - "echo \"\n\n\n\n \" $msg; " \ - "setenv stdout serial; " \ + "setcurs 5 4; " \ + "lcdputs \"Monitor failed to start. " \ + "Try again, or contact GE Service for support.\"; " \ "mw.b 0x7000A000 0xbc; " \ "mw.b 0x7000A001 0x00; " \ "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \ -- cgit v1.3.1 From 833dd6444bfeabc66cc1b0918fa2986d50c12a11 Mon Sep 17 00:00:00 2001 From: Denis Zalevskiy Date: Tue, 12 Nov 2019 19:15:16 +0000 Subject: configs: ppd: DM for USB and regulators PPD DM should be used for USB since 2019.07, it also requires DM for regulators. Signed-off-by: Denis Zalevskiy Signed-off-by: Robert Beckett --- configs/mx53ppd_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'configs') diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index f1057e3f391..47481eaf606 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -56,3 +56,5 @@ CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_WATCHDOG_TIMEOUT_MSECS=8000 CONFIG_IMX_WATCHDOG=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_USB=y -- cgit v1.3.1 From b565b18a294fe67e3463a990da9a1165ec82cf16 Mon Sep 17 00:00:00 2001 From: Denis Zalevskiy Date: Tue, 12 Nov 2019 19:15:17 +0000 Subject: board: ge: bx50v3: Enable DM for PCI and ethernet DM for PCI pulls DM for ethernet that also needs other changes described below to build u-boot and keep existing functionality - ability to update MAC addresses of FEC ethernet adapter and I210 adapter connected to the Marvell switch. - fec_mxc driver with DM needs PHYLIB; - configuration items are moved from ge_bx50v3.h to ge_bx50v3_defconfig; - FEC is marked as eth0 because it is always present, so indices changed: I210 are still probed in the same order; - board_eth_init() was used by legacy ethernet, setup for enet iomux and pcie is moved to the board_late_init(); - pci_init() is called from the board_late_init() to initiate PCI bus probing, so I210 devices are propagated to the device tree; Signed-off-by: Denis Zalevskiy [Describe PHY reset in device tree] Signed-off-by: Ian Ray Signed-off-by: Robert Beckett --- board/ge/bx50v3/bx50v3.c | 75 ++++++++------------------------------------- configs/ge_bx50v3_defconfig | 8 +++++ include/configs/ge_bx50v3.h | 12 -------- 3 files changed, 21 insertions(+), 74 deletions(-) (limited to 'configs') diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index df2d22b61fe..d3aaa2d96f4 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -36,6 +36,8 @@ #include "../common/ge_common.h" #include "../common/vpd_reader.h" #include "../../../drivers/net/e1000.h" +#include + DECLARE_GLOBAL_DATA_PTR; static int confidx; /* Default to generic. */ @@ -83,38 +85,6 @@ static iomux_v3_cfg_t const uart4_pads[] = { MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -static iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - /* AR8033 PHY Reset */ - MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_iomux_enet(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); - - /* Reset AR8033 PHY */ - gpio_request(IMX_GPIO_NR(1, 28), "fec_rst"); - gpio_direction_output(IMX_GPIO_NR(1, 28), 0); - mdelay(10); - gpio_set_value(IMX_GPIO_NR(1, 28), 1); - mdelay(1); -} - static struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD, @@ -154,16 +124,6 @@ static struct i2c_pads_info i2c_pad_info3 = { } }; -static iomux_v3_cfg_t const pcie_pads[] = { - MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_pcie(void) -{ - imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); -} - static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); @@ -455,7 +415,7 @@ static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type, static void process_vpd(struct vpd_cache *vpd) { - int fec_index = -1; + int fec_index = 0; int i210_index = -1; if (!vpd->is_read) { @@ -463,41 +423,30 @@ static void process_vpd(struct vpd_cache *vpd) return; } + if (vpd->has & VPD_HAS_MAC1) + eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1); + + env_set("ethact", "eth0"); + switch (vpd->product_id) { case VPD_PRODUCT_B450: env_set("confidx", "1"); - i210_index = 0; - fec_index = 1; + i210_index = 1; break; case VPD_PRODUCT_B650: env_set("confidx", "2"); - i210_index = 0; - fec_index = 1; + i210_index = 1; break; case VPD_PRODUCT_B850: env_set("confidx", "3"); - i210_index = 1; - fec_index = 2; + i210_index = 2; break; } - if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1)) - eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1); - if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2)) eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2); } -int board_eth_init(bd_t *bis) -{ - setup_iomux_enet(); - setup_pcie(); - - e1000_initialize(bis); - - return cpu_eth_init(bis); -} - static iomux_v3_cfg_t const misc_pads[] = { MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL), @@ -659,6 +608,8 @@ int board_late_init(void) check_time(); + pci_init(); + return 0; } diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 7d811f5f9b3..38ea981dd11 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -75,3 +75,11 @@ CONFIG_IMX_WATCHDOG=y # CONFIG_EFI_LOADER is not set CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_PNP=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_FEC_MXC=y +CONFIG_ETHPRIME="FEC" diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 9f8d388f522..1c7ba36c8ae 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -49,16 +49,6 @@ #define CONFIG_USB_GADGET_MASS_STORAGE #endif -/* Networking Configs */ -#ifdef CONFIG_NET -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 4 -#define CONFIG_PHY_ATHEROS -#endif - /* Serial Flash */ /* allow to overwrite serial and ethaddr */ @@ -194,8 +184,6 @@ #define CONFIG_IMX6_PWM_PER_CLK 66000000 -#define CONFIG_PCI -#define CONFIG_PCI_PNP #define CONFIG_PCI_SCAN_SHOW #define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) -- cgit v1.3.1 From d494aeca4688a8040362fd968d0aa9a5b8e0bf55 Mon Sep 17 00:00:00 2001 From: Robert Beckett Date: Tue, 12 Nov 2019 19:15:19 +0000 Subject: board: ge: bx50v3: use imx wdt Enable DM imx WDT Enable SYSRESET_WATCHDOG to maintain WDT based reset ability Signed-off-by: Robert Beckett --- arch/arm/dts/imx6q-bx50v3-uboot.dtsi | 12 ++++++++++++ arch/arm/dts/imx6q-bx50v3.dtsi | 1 + configs/ge_bx50v3_defconfig | 3 +++ 3 files changed, 16 insertions(+) create mode 100644 arch/arm/dts/imx6q-bx50v3-uboot.dtsi (limited to 'configs') diff --git a/arch/arm/dts/imx6q-bx50v3-uboot.dtsi b/arch/arm/dts/imx6q-bx50v3-uboot.dtsi new file mode 100644 index 00000000000..88dd7e29393 --- /dev/null +++ b/arch/arm/dts/imx6q-bx50v3-uboot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Collabora Ltd + * Copyright 2019 General Electric Company + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + }; +}; diff --git a/arch/arm/dts/imx6q-bx50v3.dtsi b/arch/arm/dts/imx6q-bx50v3.dtsi index 009f88e305d..bb8f5623079 100644 --- a/arch/arm/dts/imx6q-bx50v3.dtsi +++ b/arch/arm/dts/imx6q-bx50v3.dtsi @@ -42,6 +42,7 @@ */ #include "imx6q-ba16.dtsi" +#include "imx6q-bx50v3-uboot.dtsi" / { mclk: clock-mclk { diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 38ea981dd11..81e450c8545 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -72,6 +72,9 @@ CONFIG_VIDEO_BPP16=y CONFIG_VIDEO_IPUV3=y CONFIG_WATCHDOG_TIMEOUT_MSECS=6000 CONFIG_IMX_WATCHDOG=y +CONFIG_WDT=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y # CONFIG_EFI_LOADER is not set CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_SYS_WHITE_ON_BLACK=y -- cgit v1.3.1 From 7915e150d6d070172f5e280373c7955d69012f16 Mon Sep 17 00:00:00 2001 From: Robert Beckett Date: Tue, 12 Nov 2019 19:15:20 +0000 Subject: board: ge: mx53ppd: use imx wdt Enable DM imx WDT Enable SYSRESET_WATCHDOG to maintain WDT based reset ability Signed-off-by: Robert Beckett --- arch/arm/dts/imx53-ppd-uboot.dtsi | 12 ++++++++++++ arch/arm/dts/imx53-ppd.dts | 1 + board/ge/mx53ppd/mx53ppd.c | 1 - configs/mx53ppd_defconfig | 3 +++ 4 files changed, 16 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx53-ppd-uboot.dtsi (limited to 'configs') diff --git a/arch/arm/dts/imx53-ppd-uboot.dtsi b/arch/arm/dts/imx53-ppd-uboot.dtsi new file mode 100644 index 00000000000..88dd7e29393 --- /dev/null +++ b/arch/arm/dts/imx53-ppd-uboot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Collabora Ltd + * Copyright 2019 General Electric Company + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + }; +}; diff --git a/arch/arm/dts/imx53-ppd.dts b/arch/arm/dts/imx53-ppd.dts index 8f3864998ce..ae98361f9ab 100644 --- a/arch/arm/dts/imx53-ppd.dts +++ b/arch/arm/dts/imx53-ppd.dts @@ -43,6 +43,7 @@ /dts-v1/; #include "imx53.dtsi" +#include "imx53-ppd-uboot.dtsi" #include / { diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index bfcee441c50..105edd24cb6 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -297,7 +297,6 @@ int board_late_init(void) return res; print_cpuinfo(); - hw_watchdog_init(); check_time(); diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 47481eaf606..7c44ea9be0d 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -56,5 +56,8 @@ CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_WATCHDOG_TIMEOUT_MSECS=8000 CONFIG_IMX_WATCHDOG=y +CONFIG_WDT=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_REGULATOR=y CONFIG_DM_USB=y -- cgit v1.3.1 From eb9124f5748c96ffd548e50fd6989c3b5395b353 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Sun, 10 Nov 2019 14:38:07 +0200 Subject: mx6cuboxi: enable OF_CONTROL with DM_MMC and DM_USB Make first step in DT/DM migration. Enable OF_CONTROL only for the main U-Boot image for now. Remove mmc_init_main() because board_mmc_init() is not called when DM_MMC is enabled. DM_MMC requires DM_GPIO for card-detect to work. That in turn makes gpio request mandatory. Add code to request/free gpios in platform code. MMC devices are now numbered according to DT. The SD card is 1, and eMMC is 2. Account for that in board_mmc_get_env_dev(), BOOT_TARGET_DEVICES, and has_emmc(). DM_MMC requires BLK. However, the (BLK && !DM_USB) combination disables USB_STORAGE. Enable DM_USB to preserve USB functionality. Add also DM_REGULATORS for the USB power controller. This allows us to drop board_ehci_hcd_init() and setup_usb(). Runtime selection of DT is necessary because of the i.MX6QD vs i.MX6SDL incompatibility. DT selection does not rely on GPIOs, since DM_GPIO depends on DT. Instead, we take one "fully featured" DT of each variant. That should be enough to boot from both SD card and eMMC. Since we don't select the exact DT, override the generic show_board_info() that shows the selected DT 'model' field. Signed-off-by: Baruch Siach Reviewed-by: Fabio Estevam --- board/solidrun/mx6cuboxi/mx6cuboxi.c | 119 +++++++++++++++++++++-------------- configs/mx6cuboxi_defconfig | 16 ++++- include/configs/mx6cuboxi.h | 6 +- 3 files changed, 89 insertions(+), 52 deletions(-) (limited to 'configs') diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index d6e0c83e0d2..6a96f9ecdb5 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -66,6 +66,8 @@ enum board_type { UNKNOWN = 0x03, }; +static struct gpio_desc board_detect_desc[5]; + #define MEM_STRIDE 0x4000000 static u32 get_ram_size_stride_test(u32 *base, u32 maxsize) { @@ -155,10 +157,6 @@ static iomux_v3_cfg_t const som_rev_detect[] = { IOMUX_PADS(PAD_CSI0_DAT18__GPIO6_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)), }; -static iomux_v3_cfg_t const usb_pads[] = { - IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - static void setup_iomux_uart(void) { SETUP_IOMUX_PADS(uart1_pads); @@ -176,7 +174,7 @@ static struct fsl_esdhc_cfg emmc_cfg = { int board_mmc_get_env_dev(int devno) { - return devno - 1; + return devno; } #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) @@ -198,27 +196,6 @@ int board_mmc_getcd(struct mmc *mmc) return ret; } -static int mmc_init_main(bd_t *bis) -{ - int ret; - - /* - * Following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 Carrier board MicroSD - * mmc1 SOM eMMC - */ - SETUP_IOMUX_PADS(usdhc2_pads); - usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - ret = fsl_esdhc_initialize(bis, &usdhc_cfg); - if (ret) - return ret; - - SETUP_IOMUX_PADS(usdhc3_pads); - emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - return fsl_esdhc_initialize(bis, &emmc_cfg); -} - static int mmc_init_spl(bd_t *bis) { struct src *psrc = (struct src *)SRC_BASE_ADDR; @@ -252,7 +229,7 @@ int board_mmc_init(bd_t *bis) if (IS_ENABLED(CONFIG_SPL_BUILD)) return mmc_init_spl(bis); - return mmc_init_main(bis); + return 0; } static iomux_v3_cfg_t const enet_pads[] = { @@ -284,12 +261,29 @@ static iomux_v3_cfg_t const enet_pads[] = { static void setup_iomux_enet(void) { + struct gpio_desc desc; + int ret; + SETUP_IOMUX_PADS(enet_pads); + ret = dm_gpio_lookup_name("GPIO4_15", &desc); + if (ret) { + printf("%s: phy reset lookup failed\n", __func__); + return; + } + + ret = dm_gpio_request(&desc, "phy-reset"); + if (ret) { + printf("%s: phy reset request failed\n", __func__); + return; + } + gpio_direction_output(ETH_PHY_RESET, 0); mdelay(10); gpio_set_value(ETH_PHY_RESET, 1); udelay(100); + + gpio_free_list_nodev(&desc, 1); } int board_phy_config(struct phy_device *phydev) @@ -434,21 +428,6 @@ static int setup_display(void) } #endif /* CONFIG_VIDEO_IPUV3 */ -#ifdef CONFIG_USB_EHCI_MX6 -static void setup_usb(void) -{ - SETUP_IOMUX_PADS(usb_pads); -} - -int board_ehci_hcd_init(int port) -{ - if (port == 1) - gpio_direction_output(USB_H1_VBUS, 1); - - return 0; -} -#endif - int board_early_init_f(void) { setup_iomux_uart(); @@ -456,10 +435,6 @@ int board_early_init_f(void) #ifdef CONFIG_CMD_SATA setup_sata(); #endif - -#ifdef CONFIG_USB_EHCI_MX6 - setup_usb(); -#endif return 0; } @@ -477,6 +452,29 @@ int board_init(void) return ret; } +static int request_detect_gpios(void) +{ + int node; + int ret; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, + "solidrun,hummingboard-detect"); + if (node < 0) + return -ENODEV; + + ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node), + "detect-gpios", board_detect_desc, + ARRAY_SIZE(board_detect_desc), GPIOD_IS_IN); + + return ret; +} + +static int free_detect_gpios(void) +{ + return gpio_free_list_nodev(board_detect_desc, + ARRAY_SIZE(board_detect_desc)); +} + static enum board_type board_type(void) { int val1, val2, val3; @@ -532,7 +530,7 @@ static bool is_rev_15_som(void) static bool has_emmc(void) { struct mmc *mmc; - mmc = find_mmc_device(1); + mmc = find_mmc_device(2); if (!mmc) return 0; return (mmc_get_op_cond(mmc) < 0) ? 0 : 1; @@ -540,6 +538,8 @@ static bool has_emmc(void) int checkboard(void) { + request_detect_gpios(); + switch (board_type()) { case CUBOXI: puts("Board: MX6 Cubox-i"); @@ -561,13 +561,22 @@ int checkboard(void) else puts("\n"); + free_detect_gpios(); out: return 0; } +/* Override the default implementation, DT model is not accurate */ +int show_board_info(void) +{ + return checkboard(); +} + int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + request_detect_gpios(); + switch (board_type()) { case CUBOXI: env_set("board_name", "CUBOXI"); @@ -594,11 +603,27 @@ int board_late_init(void) if (has_emmc()) env_set("has_emmc", "yes"); + free_detect_gpios(); #endif return 0; } +/* + * This is not a perfect match. Avoid dependency on the DM GPIO driver needed + * for accurate board detection. Hummingboard2 DT is good enough for U-Boot on + * all Hummingboard/Cubox-i platforms. + */ +int board_fit_config_name_match(const char *name) +{ + char tmp_name[36]; + + snprintf(tmp_name, sizeof(tmp_name), "%s-hummingboard2-emmc-som-v15", + is_mx6dq() ? "imx6q" : "imx6dl"); + + return strcmp(name, tmp_name); +} + #ifdef CONFIG_SPL_BUILD #include static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = { diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 0692f31f0ae..23ce485f43f 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -14,8 +14,10 @@ CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set CONFIG_CMD_HDMIDETECT=y +CONFIG_AHCI=y CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_USE_PREBOOT=y @@ -27,23 +29,35 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_SATA=y CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_PARTITION_UUIDS is not set +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-hummingboard2-emmc-som-v15" +CONFIG_OF_LIST="imx6dl-hummingboard2-emmc-som-v15 imx6q-hummingboard2-emmc-som-v15" +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_DWC_AHSATA=y +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_THERMAL=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_KEYBOARD=y CONFIG_VIDEO_IPUV3=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_OF_LIBFDT=y diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index c8d91dcfa05..6d47e28fc72 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -45,10 +45,7 @@ #define CONFIG_IMX_VIDEO_SKIP /* USB */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Command definition */ @@ -108,7 +105,8 @@ BOOTENV #define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ func(SATA, sata, 0) \ func(USB, usb, 0) \ func(PXE, pxe, na) \ -- cgit v1.3.1 From 04886b36eb72f9deda5deaf21b31777fda828af9 Mon Sep 17 00:00:00 2001 From: Claudius Heine Date: Fri, 29 Nov 2019 08:59:03 +0100 Subject: ARM: imx6: DHCOM i.MX6 PDK: Enable sysreset driver and wdt command The SPL does not have DM enabled and therefor still needs to use the hardware watchdog interface provided by the imx-watchdog driver. Fixes: broken reset command after f2929d11a639 ("watchdog: imx: Use immediate reset bits for expire_now") Signed-off-by: Claudius Heine --- configs/dh_imx6_defconfig | 3 +++ include/configs/dh_imx6.h | 5 +++++ 2 files changed, 8 insertions(+) (limited to 'configs') diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 0a38da619a8..db5152dd164 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_SATA=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y @@ -83,6 +84,8 @@ CONFIG_DM_SCSI=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_GADGET=y diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index d762d2cb19b..087d020cdd3 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -87,6 +87,11 @@ #endif /* Watchdog */ +#if defined(CONFIG_SPL_BUILD) +#undef CONFIG_WDT +#undef CONFIG_WATCHDOG +#define CONFIG_HW_WATCHDOG +#endif /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -- cgit v1.3.1 From 7f681b3d75e99b7f64ee7906f2827e22fbadda65 Mon Sep 17 00:00:00 2001 From: Suniel Mahesh Date: Wed, 20 Nov 2019 15:25:00 +0530 Subject: board: cm_fx6: Enable DM support for video, fix build error Enable driver model for Video to remove the following compile warning on CM-FX6 SOM based target: ===================== WARNING ====================== This board does not use CONFIG_DM_VIDEO Please update the board to use CONFIG_DM_VIDEO before the v2019.07 release. ==================================================== This change introduced build error as shown: LD u-boot drivers/built-in.o: In function ipu_displays_init' arm-linux-ld.bfd: BFD (GNU Binutils) 2.29.1 assertion fail elf32-arm.c:9509 Makefile:1621: recipe for target 'u-boot' failed make: *** [u-boot] Error 1 The DM converted video driver calls ipu_displays_init in its probe, which inturn calls relevant board_video_skip. Defining ipu_displays_init in the board file fixes build error. Target was compile tested, build was clean. Signed-off-by: Suniel Mahesh --- board/compulab/cm_fx6/cm_fx6.c | 5 +++++ configs/cm_fx6_defconfig | 1 + 2 files changed, 6 insertions(+) (limited to 'configs') diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index b20ca168dfb..3e185ad82a2 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -147,6 +147,11 @@ int board_video_skip(void) static inline void cm_fx6_setup_display(void) {} #endif /* CONFIG_VIDEO_IPUV3 */ +int ipu_displays_init(void) +{ + return board_video_skip(); +} + #ifdef CONFIG_DWC_AHSATA static int cm_fx6_issd_gpios[] = { /* The order of the GPIOs in the array is important! */ diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 316cb5725db..ce78cf89317 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -90,4 +90,5 @@ CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y CONFIG_VIDEO_IPUV3=y CONFIG_VIDEO=y +CONFIG_DM_VIDEO=y CONFIG_FDT_FIXUP_PARTITIONS=y -- cgit v1.3.1 From 26d926d616f388accff45e9845e11f1de60674e9 Mon Sep 17 00:00:00 2001 From: Suniel Mahesh Date: Wed, 20 Nov 2019 15:25:01 +0530 Subject: board: cm_fx6: Enable CONFIG_DM_ETH Enable CONFIG_DM_ETH to remove compile warning on CM-FX6 SOM based target: ===================== WARNING ====================== This board does not use CONFIG_DM_ETH (Driver Model for Ethernet drivers). Please update the board to use CONFIG_DM_ETH before the v2020.07 release. ==================================================== Signed-off-by: Suniel Mahesh --- configs/cm_fx6_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'configs') diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index ce78cf89317..9bf6da1bed8 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -84,6 +84,7 @@ CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_SPI=y CONFIG_MXC_SPI=y +CONFIG_DM_ETH=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_KEYBOARD=y -- cgit v1.3.1 From 1699f0e59272ee3d42cdcd16c3501b4b71af6943 Mon Sep 17 00:00:00 2001 From: Suniel Mahesh Date: Wed, 27 Nov 2019 16:17:48 +0530 Subject: arm: imx6: cm_fx6: Enable DM SPI and SPI_FLASH, fix SPL build errors Enable driver model for SPI and SPI_FLASH to remove the following compile warning on CM-FX6 SOM: ===================== WARNING ====================== This board does not use CONFIG_DM_SPI_FLASH. Please update the board to use CONFIG_SPI_FLASH before the v2019.07 release. ==================================================== This change introduced SPL build error as shown: In file included from include/common.h:47:0, from drivers/mtd/spi/sf_probe.c:10: drivers/mtd/spi/sf_probe.c: In function 'spi_flash_std_probe': drivers/mtd/spi/sf_probe.c:149:54: error: dereferencing pointer to incomplete type 'struct dm_spi_slave_platdata' scripts/Makefile.build:278: recipe for target 'spl/drivers/mtd/spi/sf_probe.o' failed make[3]: *** [spl/drivers/mtd/spi/sf_probe.o] Error 1 scripts/Makefile.build:432: recipe for target 'spl/drivers/mtd/spi' failed make[2]: *** [spl/drivers/mtd/spi] Error 2 Disabling DM for SPI support(SPI and SF) in SPL resolves the issue. Target was compile tested, build was clean. Signed-off-by: Suniel Mahesh --- configs/cm_fx6_defconfig | 2 ++ include/configs/cm_fx6.h | 7 +++++++ 2 files changed, 9 insertions(+) (limited to 'configs') diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 9bf6da1bed8..a4191607515 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -67,6 +67,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y +CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPI_FLASH_ATMEL=y @@ -83,6 +84,7 @@ CONFIG_MII=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_ETH=y CONFIG_USB=y diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index eb29f07032b..53ae5f08ebd 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -153,6 +153,13 @@ /* APBH DMA is required for NAND support */ #endif +/* SPI Flash Configs */ +#if defined(CONFIG_SPL_BUILD) +#undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH +#undef CONFIG_SPI_FLASH_MTD +#endif + /* Ethernet */ #define CONFIG_FEC_MXC #define CONFIG_FEC_MXC_PHYADDR 0 -- cgit v1.3.1 From d98929d63681be6e76653ca05297f3ca46121da1 Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Mon, 4 Nov 2019 19:50:07 +0100 Subject: imx: sync with kernel device tree for Phycore SoM Sync the Linux Kernel 5.4-rc6 device tree for Phytec Phycore SoM and Segin board based on imx6UL and imx6ULL. Changes includes Phytec naming convention for the devicetree files. Signed-off-by: Parthiban Nallathambi Acked-by: Peng Fan --- arch/arm/dts/Makefile | 4 +- arch/arm/dts/imx6ul-phycore-segin.dts | 81 ----- arch/arm/dts/imx6ul-phytec-phycore-som.dtsi | 167 ++++++++++ arch/arm/dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 93 ++++++ arch/arm/dts/imx6ul-phytec-segin-peb-eval-01.dtsi | 57 ++++ arch/arm/dts/imx6ul-phytec-segin.dtsi | 346 +++++++++++++++++++++ arch/arm/dts/imx6ull-phycore-segin.dts | 70 ----- arch/arm/dts/imx6ull-phytec-phycore-som.dtsi | 24 ++ arch/arm/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts | 93 ++++++ arch/arm/dts/imx6ull-phytec-segin-peb-eval-01.dtsi | 19 ++ arch/arm/dts/imx6ull-phytec-segin.dtsi | 38 +++ arch/arm/dts/pcl063-common.dtsi | 197 ------------ board/phytec/pcl063/MAINTAINERS | 12 +- configs/phycore_pcl063_defconfig | 2 +- configs/phycore_pcl063_ull_defconfig | 2 +- 15 files changed, 849 insertions(+), 356 deletions(-) delete mode 100644 arch/arm/dts/imx6ul-phycore-segin.dts create mode 100644 arch/arm/dts/imx6ul-phytec-phycore-som.dtsi create mode 100644 arch/arm/dts/imx6ul-phytec-segin-ff-rdk-nand.dts create mode 100644 arch/arm/dts/imx6ul-phytec-segin-peb-eval-01.dtsi create mode 100644 arch/arm/dts/imx6ul-phytec-segin.dtsi delete mode 100644 arch/arm/dts/imx6ull-phycore-segin.dts create mode 100644 arch/arm/dts/imx6ull-phytec-phycore-som.dtsi create mode 100644 arch/arm/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts create mode 100644 arch/arm/dts/imx6ull-phytec-segin-peb-eval-01.dtsi create mode 100644 arch/arm/dts/imx6ull-phytec-segin.dtsi delete mode 100644 arch/arm/dts/pcl063-common.dtsi (limited to 'configs') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 97504e36a81..88b2bf452a2 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -663,14 +663,14 @@ dtb-$(CONFIG_MX6UL) += \ imx6ul-9x9-evk.dtb \ imx6ul-9x9-evk.dtb \ imx6ul-liteboard.dtb \ - imx6ul-phycore-segin.dtb \ + imx6ul-phytec-segin-ff-rdk-nand.dtb \ imx6ul-pico-hobbit.dtb \ imx6ul-pico-pi.dtb dtb-$(CONFIG_MX6ULL) += \ imx6ull-14x14-evk.dtb \ imx6ull-colibri.dtb \ - imx6ull-phycore-segin.dtb \ + imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-dart-6ul.dtb \ imx6ulz-14x14-evk.dtb diff --git a/arch/arm/dts/imx6ul-phycore-segin.dts b/arch/arm/dts/imx6ul-phycore-segin.dts deleted file mode 100644 index 7d68bf84305..00000000000 --- a/arch/arm/dts/imx6ul-phycore-segin.dts +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Collabora Ltd. - * - * Based on dts[i] from Phytec barebox port: - * Copyright (C) 2016 PHYTEC Messtechnik GmbH - * Author: Christian Hemp - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; - -#include "imx6ul.dtsi" -#include "pcl063-common.dtsi" - -/ { - model = "Phytec phyBOARD-i.MX6UL-Segin SBC"; - compatible = "phytec,phyboard-imx6ul-segin", "phytec,imx6ul-pcl063", - "fsl,imx6ul"; -}; - -&gpmi { - status = "okay"; -}; - -&i2c1 { - i2c_rtc: rtc@68 { - compatible = "microcrystal,rv4162"; - reg = <0x68>; - status = "okay"; - }; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_id>; - dr_mode = "otg"; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 - MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 - MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 - MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 - >; - }; - -}; diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi new file mode 100644 index 00000000000..c2a7c787794 --- /dev/null +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +#include +#include +#include + +/ { + model = "PHYTEC phyCORE-i.MX6 UltraLite"; + compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + gpio_leds_som: leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioleds_som>; + compatible = "gpio-leds"; + + phycore-green { + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + status = "disabled"; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; + + eeprom@52 { + compatible = "catalyst,24c32", "atmel,24c32"; + reg = <0x52>; + }; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "disabled"; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10010 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10010 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059 + >; + }; + + pinctrl_gpioleds_som: gpioledssomgrp { + fsl,pins = ; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_i2c1: i2cgrp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; + +}; diff --git a/arch/arm/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/dts/imx6ul-phytec-segin-ff-rdk-nand.dts new file mode 100644 index 00000000000..699dfcbf9a6 --- /dev/null +++ b/arch/arm/dts/imx6ul-phytec-segin-ff-rdk-nand.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +/dts-v1/; +#include "imx6ul.dtsi" +#include "imx6ul-phytec-phycore-som.dtsi" +#include "imx6ul-phytec-segin.dtsi" +#include "imx6ul-phytec-segin-peb-eval-01.dtsi" + +/ { + model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND"; + compatible = "phytec,imx6ul-pbacd10-nand", "phytec,imx6ul-pbacd10", + "phytec,imx6ul-pcl063", "fsl,imx6ul"; +}; + +&adc1 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&tlv320 { + status = "okay"; +}; + +&ecspi3 { + status = "okay"; +}; + +ðphy1 { + status = "okay"; +}; + +ðphy2 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +®_can1_en { + status = "okay"; +}; + +®_sound_1v8 { + status = "okay"; +}; + +®_sound_3v3 { + status = "okay"; +}; + +&sai2 { + status = "okay"; +}; + +&sound { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ul-phytec-segin-peb-eval-01.dtsi b/arch/arm/dts/imx6ul-phytec-segin-peb-eval-01.dtsi new file mode 100644 index 00000000000..2f3fd32a116 --- /dev/null +++ b/arch/arm/dts/imx6ul-phytec-segin-peb-eval-01.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 PHYTEC Messtechnik + * Author: Christian Hemp + */ + +#include + +/ { + gpio_keys: gpio-keys { + compatible = "gpio-key"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + status = "disabled"; + + power { + label = "Power Button"; + gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + user_leds: user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_leds>; + status = "disabled"; + + user-led1 { + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + + user-led2 { + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + }; +}; + +&iomuxc { + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79 + >; + }; + + pinctrl_user_leds: user_ledsgrp { + fsl,pins = < + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x79 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79 + >; + }; +}; diff --git a/arch/arm/dts/imx6ul-phytec-segin.dtsi b/arch/arm/dts/imx6ul-phytec-segin.dtsi new file mode 100644 index 00000000000..8d5f8dc6ad5 --- /dev/null +++ b/arch/arm/dts/imx6ul-phytec-segin.dtsi @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +/ { + model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite"; + compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul"; + + aliases { + rtc0 = &i2c_rtc; + rtc1 = &snvs_rtc; + }; + + reg_sound_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "i2s-audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "disabled"; + }; + + reg_sound_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "i2s-audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; + + reg_can1_en: regulator-can1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&princtrl_flexcan1_en>; + regulator-name = "Can"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_adc1_vref_3v3: regulator-vref-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "Speaker", "SPOP", + "Speaker", "SPOM", + "LINE1L", "Line In", + "LINE1R", "Line In"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&tlv320>; + clocks = <&clks IMX6UL_CLK_SAI2>; + }; + }; + +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + vref-supply = <®_adc1_vref_3v3>; + /* + * driver can not separate a specific channel so we request 4 channels + * here - we need only the fourth channel + */ + num-channels = <4>; + status = "disabled"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_en>; + status = "disabled"; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + status = "disabled"; +}; + +&i2c1 { + tlv320: codec@18 { + compatible = "ti,tlv320aic3007"; + #sound-dai-cells = <0>; + reg = <0x18>; + AVDD-supply = <®_sound_3v3>; + IOVDD-supply = <®_sound_3v3>; + DRVDD-supply = <®_sound_3v3>; + DVDD-supply = <®_sound_1v8>; + status = "disabled"; + }; + + stmpe: touchscreen@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_stmpe>; + status = "disabled"; + + touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <1>; + st,touch-det-delay = <2>; + st,settling = <2>; + st,fraction-z = <7>; + st,i-drive = <1>; + touchscreen-inverted-x = <1>; + touchscreen-inverted-y = <1>; + }; + }; + + i2c_rtc: rtc@68 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + compatible = "microcrystal,rv4162"; + reg = <0x68>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + status = "disabled"; + }; +}; + +&mdio { + ethphy2: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + status = "disabled"; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "disabled"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <19200000>; + fsl,sai-mclk-direction-output; + status = "disabled"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "disabled"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + status = "disabled"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "disabled"; +}; + +&iomuxc { + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 + >; + }; + + pinctrl_flexcan1: flexcan1 { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 + >; + }; + + princtrl_flexcan1_en: flexcan1engrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 + >; + }; + + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; +}; diff --git a/arch/arm/dts/imx6ull-phycore-segin.dts b/arch/arm/dts/imx6ull-phycore-segin.dts deleted file mode 100644 index 6df3ad2e4a4..00000000000 --- a/arch/arm/dts/imx6ull-phycore-segin.dts +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2019 Parthiban Nallathambi - */ - -/dts-v1/; - -#include "imx6ull.dtsi" -#include "pcl063-common.dtsi" - -/ { - model = "Phytec phyBOARD-i.MX6ULL-Segin SBC"; - compatible = "phytec,phyboard-imx6ull-segin", "phytec,imx6ull-pcl063", - "fsl,imx6ull"; -}; - -&i2c1 { - i2c_rtc: rtc@68 { - compatible = "microcrystal,rv4162"; - reg = <0x68>; - status = "okay"; - }; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; -}; - -&usdhc2 { - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_id>; - dr_mode = "otg"; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 - MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 - MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 - MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 - >; - }; - -}; diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ull-phytec-phycore-som.dtsi new file mode 100644 index 00000000000..56cd16e5a77 --- /dev/null +++ b/arch/arm/dts/imx6ull-phytec-phycore-som.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 PHYTEC Messtechnik GmbH + * Author: Stefan Riedmueller + */ + +#include "imx6ul-phytec-phycore-som.dtsi" + +/ { + model = "PHYTEC phyCORE-i.MX6 ULL"; + compatible = "phytec,imx6ull-pcl063", "fsl,imx6ull"; +}; + +&iomuxc { + /delete-node/ gpioledssomgrp; +}; + +&iomuxc_snvs { + pinctrl_gpioleds_som: gpioledssomgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts b/arch/arm/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts new file mode 100644 index 00000000000..9648d4ecaf5 --- /dev/null +++ b/arch/arm/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 PHYTEC Messtechnik GmbH + * Author: Stefan Riedmueller + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-phytec-phycore-som.dtsi" +#include "imx6ull-phytec-segin.dtsi" +#include "imx6ull-phytec-segin-peb-eval-01.dtsi" + +/ { + model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with eMMC"; + compatible = "phytec,imx6ull-pbacd10-emmc", "phytec,imx6ull-pbacd10", + "phytec,imx6ull-pcl063","fsl,imx6ull"; +}; + +&adc1 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&tlv320 { + status = "okay"; +}; + +&ecspi3 { + status = "okay"; +}; + +ðphy1 { + status = "okay"; +}; + +ðphy2 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +®_can1_en { + status = "okay"; +}; + +®_sound_1v8 { + status = "okay"; +}; + +®_sound_3v3 { + status = "okay"; +}; + +&sai2 { + status = "okay"; +}; + +&sound { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull-phytec-segin-peb-eval-01.dtsi b/arch/arm/dts/imx6ull-phytec-segin-peb-eval-01.dtsi new file mode 100644 index 00000000000..ff08d95a1aa --- /dev/null +++ b/arch/arm/dts/imx6ull-phytec-segin-peb-eval-01.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 PHYTEC Messtechnik GmbH + * Author: Stefan Riedmueller + */ + +#include "imx6ul-phytec-segin-peb-eval-01.dtsi" + +&iomuxc { + /delete-node/ gpio_keysgrp; +}; + +&iomuxc_snvs { + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79 + >; + }; +}; diff --git a/arch/arm/dts/imx6ull-phytec-segin.dtsi b/arch/arm/dts/imx6ull-phytec-segin.dtsi new file mode 100644 index 00000000000..c1595fc785f --- /dev/null +++ b/arch/arm/dts/imx6ull-phytec-segin.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 PHYTEC Messtechnik GmbH + * Author: Stefan Riedmueller + */ + +#include "imx6ul-phytec-segin.dtsi" + +/ { + model = "PHYTEC phyBOARD-Segin i.MX6 ULL"; + compatible = "phytec,imx6ull-pbacd-10", "phytec,imx6ull-pcl063","fsl,imx6ull"; +}; + +&iomuxc { + /delete-node/ flexcan1engrp; + /delete-node/ rtcintgrp; + /delete-node/ stmpegrp; +}; + +&iomuxc_snvs { + princtrl_flexcan1_en: flexcan1engrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 + >; + }; + + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; +}; diff --git a/arch/arm/dts/pcl063-common.dtsi b/arch/arm/dts/pcl063-common.dtsi deleted file mode 100644 index b88dde2fb02..00000000000 --- a/arch/arm/dts/pcl063-common.dtsi +++ /dev/null @@ -1,197 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Collabora Ltd. - * - * Based on dts[i] from Phytec barebox port: - * Copyright (C) 2016 PHYTEC Messtechnik GmbH - * Author: Christian Hemp - */ - -/ { - model = "Phytec phyCORE-i.MX6 Ultra Lite SOM"; - compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul"; - - memory { - reg = <0x80000000 0x20000000>; - }; - - chosen { - stdout-path = &uart1; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - reg = <1>; - micrel,led-mode = <1>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - fsl,no-blockmark-swap; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x400000>; - }; - - partition@400000 { - label = "uboot-env"; - reg = <0x400000 0x100000>; - }; - - partition@500000 { - label = "root"; - reg = <0x500000 0x0>; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - status = "okay"; - - eeprom@52 { - compatible = "cat,24c32"; - reg = <0x52>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - bus-width = <0x4>; - pinctrl-0 = <&pinctrl_usdhc1>; - no-1-8-v; - status = "okay"; -}; - -&usdhc2 { - u-boot,dm-spl; - u-boot,dm-pre-reloc; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <8>; - no-1-8-v; - non-removable; - keep-power-in-suspend; - status = "disabled"; -}; - -&iomuxc { - pinctrl-names = "default"; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 - MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 - >; - }; - - pinctrl_i2c1: i2cgrp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c1_gpio: i2c1grp_gpio { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 - MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 - - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 - MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170f9 - >; - }; -}; diff --git a/board/phytec/pcl063/MAINTAINERS b/board/phytec/pcl063/MAINTAINERS index 710b9680d41..02be541cc0d 100644 --- a/board/phytec/pcl063/MAINTAINERS +++ b/board/phytec/pcl063/MAINTAINERS @@ -2,10 +2,14 @@ PCL063 BOARD M: Martyn Welch M: Parthiban Nallathambi S: Maintained -F: arch/arm/dts/imx6ul-pcl063.dtsi -F: arch/arm/dts/imx6ul-phycore-segin.dts -F: arch/arm/dts/imx6ull-phycore-segin.dts -F: arch/arm/dts/pcl063-common.dtsi +F: arch/arm/dts/imx6ul-phytec-phycore-som.dtsi +F: arch/arm/dts/imx6ul-phytec-segin-peb-eval-01.dtsi +F: arch/arm/dts/imx6ul-phytec-segin.dtsi +F: arch/arm/dts/imx6ul-phytec-segin-ff-rdk-nand.dts +F: arch/arm/dts/imx6ull-phytec-phycore-som.dtsi +F: arch/arm/dts/imx6ull-phytec-segin-peb-eval-01.dtsi +F: arch/arm/dts/imx6ull-phytec-segin.dtsi +F: arch/arm/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts F: arch/arm/dts/imx6ull-u-boot.dtsi F: board/phytec/pcl063/ F: configs/phycore_pcl063_defconfig diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig index b9c9a798688..b9e725b6f55 100644 --- a/configs/phycore_pcl063_defconfig +++ b/configs/phycore_pcl063_defconfig @@ -33,7 +33,7 @@ CONFIG_MTDPARTS_DEFAULT="gpmi-nand:4m(uboot),1m(env),-(root)" CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="imx6ul-phycore-segin" +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-phytec-segin-ff-rdk-nand" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_MXC=y diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig index f2635ce4498..879ac788647 100644 --- a/configs/phycore_pcl063_ull_defconfig +++ b/configs/phycore_pcl063_ull_defconfig @@ -29,7 +29,7 @@ CONFIG_CMD_USB_SDP=y CONFIG_CMD_CACHE=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="imx6ull-phycore-segin" +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-phytec-segin-ff-rdk-emmc" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_MXC=y -- cgit v1.3.1 From 9c2b1b0f0390bb680e43197fd2ba2369d21ab4f7 Mon Sep 17 00:00:00 2001 From: Steffen Dirkwinkel Date: Wed, 23 Oct 2019 07:40:40 +0200 Subject: imx: cx9020: migrate cx9020 to CONFIG_DM_ETH Acked-by: Patrick Bruenn Signed-off-by: Steffen Dirkwinkel --- arch/arm/dts/imx53-cx9020.dts | 31 ++++++++++++++++++++----------- configs/mx53cx9020_defconfig | 2 ++ include/configs/mx53cx9020.h | 4 ---- 3 files changed, 22 insertions(+), 15 deletions(-) (limited to 'configs') diff --git a/arch/arm/dts/imx53-cx9020.dts b/arch/arm/dts/imx53-cx9020.dts index 36ceae36aa9..2b7f7288088 100644 --- a/arch/arm/dts/imx53-cx9020.dts +++ b/arch/arm/dts/imx53-cx9020.dts @@ -99,17 +99,6 @@ MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 - MX53_PAD_FEC_MDC__FEC_MDC 0x4 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 - MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec @@ -148,6 +137,21 @@ >; }; + pinctrl_fec0: fec0grp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x4 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 + >; + }; + pinctrl_esdhc1: esdhc1grp { fsl,pins = < MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 @@ -209,5 +213,10 @@ pinctrl-names = "default"; phy-mode = "rmii"; phy-reset-gpios = <&gpio7 6 0>; + pinctrl-0 = <&pinctrl_fec0>; status = "okay"; + fixed-link { /* RMII fixed link to KZ8863 */ + speed = <100>; + full-duplex; + }; }; diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig index da61691706f..5ed3e13272a 100644 --- a/configs/mx53cx9020_defconfig +++ b/configs/mx53cx9020_defconfig @@ -31,8 +31,10 @@ CONFIG_FPGA_CYCLON2=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_ETH=y CONFIG_MTD=y CONFIG_FEC_MXC=y +CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX5=y diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index af23762396f..cae49e8793a 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -35,10 +35,6 @@ /* bootz: zImage/initrd.img support */ -/* Eth Configs */ -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_ETHPRIME "FEC0" -#define CONFIG_FEC_MXC_PHYADDR 0x1F /* USB Configs */ #define CONFIG_MXC_USB_PORT 1 -- cgit v1.3.1 From ba1444eab6c51550b2c992fc228d5f29774366bf Mon Sep 17 00:00:00 2001 From: Steffen Dirkwinkel Date: Wed, 23 Oct 2019 07:40:41 +0200 Subject: imx: cx9020: migrate cx9020 to CONFIG_DM_USB Note: gpio7_8 was never used for usb power regulator so we remove it here Acked-by: Patrick Bruenn Signed-off-by: Steffen Dirkwinkel --- arch/arm/dts/imx53-cx9020.dts | 11 ++++++++++- board/beckhoff/mx53cx9020/mx53cx9020.c | 10 ---------- configs/mx53cx9020_defconfig | 6 ++++++ 3 files changed, 16 insertions(+), 11 deletions(-) (limited to 'configs') diff --git a/arch/arm/dts/imx53-cx9020.dts b/arch/arm/dts/imx53-cx9020.dts index 2b7f7288088..e08850999b1 100644 --- a/arch/arm/dts/imx53-cx9020.dts +++ b/arch/arm/dts/imx53-cx9020.dts @@ -36,7 +36,6 @@ MX53_PAD_GPIO_1__GPIO1_1 0x80000000 MX53_PAD_GPIO_4__GPIO1_4 0x80000000 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 - MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 MX53_PAD_GPIO_16__GPIO7_11 0x80000000 MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000 @@ -220,3 +219,13 @@ full-duplex; }; }; + +&usbh1 { + phy_type = "utmi"; + status = "okay"; +}; + +&usbotg { + dr_mode = "host"; + status = "okay"; +}; diff --git a/board/beckhoff/mx53cx9020/mx53cx9020.c b/board/beckhoff/mx53cx9020/mx53cx9020.c index 63a54f59b88..398e4ed7202 100644 --- a/board/beckhoff/mx53cx9020/mx53cx9020.c +++ b/board/beckhoff/mx53cx9020/mx53cx9020.c @@ -129,16 +129,6 @@ static void setup_gpio_leds(void) gpio_direction_output(GPIO_LED_PWR_G, 0); } -#ifdef CONFIG_USB_EHCI_MX5 -int board_ehci_hcd_init(int port) -{ - /* request VBUS power enable pin, GPIO7_8 */ - gpio_direction_output(IMX_GPIO_NR(7, 8), 1); - return 0; -} -#endif - - static int power_init(void) { /* nothing to do on CX9020 */ diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig index 5ed3e13272a..dee7c37913a 100644 --- a/configs/mx53cx9020_defconfig +++ b/configs/mx53cx9020_defconfig @@ -21,7 +21,13 @@ CONFIG_CMD_PXE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y +CONFIG_CMD_USB=y CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_MX5=y +CONFIG_USB_STORAGE=y +CONFIG_DM_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx53-cx9020" CONFIG_ENV_IS_IN_MMC=y -- cgit v1.3.1 From dd7e7feb4430accb73a140c9539253ec1e11276b Mon Sep 17 00:00:00 2001 From: Steffen Dirkwinkel Date: Wed, 23 Oct 2019 07:40:42 +0200 Subject: imx: cx9020: enable vidconsole by default Acked-by: Patrick Bruenn Signed-off-by: Steffen Dirkwinkel --- configs/mx53cx9020_defconfig | 1 + include/configs/mx53cx9020.h | 3 +++ 2 files changed, 4 insertions(+) (limited to 'configs') diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig index dee7c37913a..e1126c53e1f 100644 --- a/configs/mx53cx9020_defconfig +++ b/configs/mx53cx9020_defconfig @@ -48,3 +48,4 @@ CONFIG_MXC_UART=y CONFIG_DM_VIDEO=y CONFIG_VIDEO_BPP16=y CONFIG_VIDEO_IPUV3=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index cae49e8793a..a9dc73dd2f4 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -53,6 +53,9 @@ "pxefile_addr_r=0x73000000\0" \ "ramdisk_addr_r=0x72000000\0" \ "console=ttymxc1,115200\0" \ + "stdin=serial\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" \ "uenv=/boot/uEnv.txt\0" \ "optargs=\0" \ "cmdline=\0" \ -- cgit v1.3.1 From 943be15974013a7fdd833cd4efd75705976a9f33 Mon Sep 17 00:00:00 2001 From: Steffen Dirkwinkel Date: Wed, 23 Oct 2019 07:40:43 +0200 Subject: imx: cx9020: use distro boot We switch from custom boot commands relying on uEnv.txt to distro boot. This removes the automatic fpga bitstream loading in favor of loading bitstreams via custom bootscripts (boot.scr) or after booting the kernel. Acked-by: Patrick Bruenn Signed-off-by: Steffen Dirkwinkel --- configs/mx53cx9020_defconfig | 1 + include/configs/mx53cx9020.h | 88 ++++++++------------------------------------ 2 files changed, 17 insertions(+), 72 deletions(-) (limited to 'configs') diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig index e1126c53e1f..cccafc5afca 100644 --- a/configs/mx53cx9020_defconfig +++ b/configs/mx53cx9020_defconfig @@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/beckhoff/mx53cx9020/imximage.cfg" CONFIG_BOOTDELAY=1 CONFIG_USE_PREBOOT=y +CONFIG_DISTRO_DEFAULTS=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index a9dc73dd2f4..0ebff26ba09 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -21,7 +21,7 @@ #define CONFIG_SYS_FSL_CLK /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) #define CONFIG_REVISION_TAG @@ -48,83 +48,27 @@ #define CONFIG_LOADADDR 0x70010000 /* loadaddr env var */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) + +#include + #define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_addr_r=0x71ff0000\0" \ + "fdt_addr_r=0x75000000\0" \ "pxefile_addr_r=0x73000000\0" \ - "ramdisk_addr_r=0x72000000\0" \ + "scriptaddr=0x74000000\0" \ + "ramdisk_addr_r=0x80000000\0" \ + "kernel_addr_r=0x72000000\0" \ + "fdt_high=0xffffffff\0" \ "console=ttymxc1,115200\0" \ "stdin=serial\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" \ - "uenv=/boot/uEnv.txt\0" \ - "optargs=\0" \ - "cmdline=\0" \ - "mmcdev=0\0" \ - "mmcpart=1\0" \ - "mmcrootfstype=ext4 rootwait fixrtc\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=/dev/mmcblk${mmcdev}p${mmcpart} ro " \ - "rootfstype=${mmcrootfstype} " \ - "${cmdline}\0" \ - "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loadpxe=dhcp;setenv kernel_addr_r ${loadaddr};pxe get;pxe boot;\0" \ - "loadrd=load mmc ${bootpart} ${ramdisk_addr_r} ${bootdir}/${rdfile};" \ - "setenv rdsize ${filesize}\0" \ - "loadfdt=echo loading ${fdt_path} ...;" \ - "load mmc ${bootpart} ${fdt_addr_r} ${fdt_path}\0" \ - "mmcboot=mmc dev ${mmcdev}; " \ - "if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "echo Checking for: ${uenv} ...;" \ - "setenv bootpart ${mmcdev}:${mmcpart};" \ - "if test -e mmc ${bootpart} ${uenv}; then " \ - "load mmc ${bootpart} ${loadaddr} ${uenv};" \ - "env import -t ${loadaddr} ${filesize};" \ - "echo Loaded environment from ${uenv};" \ - "if test -n ${dtb}; then " \ - "setenv fdt_file ${dtb};" \ - "echo Using: dtb=${fdt_file} ...;" \ - "fi;" \ - "echo Checking for uname_r in ${uenv}...;" \ - "if test -n ${uname_r}; then " \ - "echo Running uname_boot ...;" \ - "run uname_boot;" \ - "fi;" \ - "fi;" \ - "fi;\0" \ - "uname_boot="\ - "setenv bootdir /boot; " \ - "setenv bootfile vmlinuz-${uname_r}; " \ - "setenv ccatfile /boot/ccat.rbf; " \ - "echo loading CCAT firmware from ${ccatfile}; " \ - "load mmc ${bootpart} ${loadaddr} ${ccatfile}; " \ - "fpga load 0 ${loadaddr} ${filesize}; " \ - "if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \ - "echo loading ${bootdir}/${bootfile} ...; " \ - "run loadimage;" \ - "setenv fdt_path /boot/dtbs/${uname_r}/${fdt_file}; " \ - "if test -e mmc ${bootpart} ${fdt_path}; then " \ - "run loadfdt;" \ - "else " \ - "echo; echo unable to find ${fdt_file} ...;" \ - "echo booting legacy ...;"\ - "run mmcargs;" \ - "echo debug: [${bootargs}] ... ;" \ - "echo debug: [bootz ${loadaddr}] ... ;" \ - "bootz ${loadaddr}; " \ - "fi;" \ - "run mmcargs;" \ - "echo debug: [${bootargs}] ... ;" \ - "echo debug: [bootz ${loadaddr} - ${fdt_addr_r}];" \ - "bootz ${loadaddr} - ${fdt_addr_r}; " \ - "else " \ - "echo loading from dhcp ...; " \ - "run loadpxe; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "run mmcboot;" + "fdtfile=imx53-cx9020.dtb\0" \ + BOOTENV #define CONFIG_ARP_TIMEOUT 200UL -- cgit v1.3.1 From 0417ef17ac1d164f09d12cab0b8e3da03ffb5da3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 9 Dec 2019 10:43:03 -0300 Subject: mx7ulp: Add support for Embedded Artists COM board The Embedded Artists COM board is based on NXP i.MX7ULP. It has a BD70528 PMIC from Rohm with discrete DCDC powering option and improved current observability (compared to the existing NXP i.MX7ULP EVK). Add the initial support for the board. Signed-off-by: Fabio Estevam --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx7ulp-com.dts | 90 +++++++++++++++++++++++++ arch/arm/mach-imx/mx7ulp/Kconfig | 6 ++ board/ea/mx7ulp_com/Kconfig | 12 ++++ board/ea/mx7ulp_com/MAINTAINERS | 6 ++ board/ea/mx7ulp_com/Makefile | 6 ++ board/ea/mx7ulp_com/imximage.cfg | 137 +++++++++++++++++++++++++++++++++++++++ board/ea/mx7ulp_com/mx7ulp_com.c | 48 ++++++++++++++ configs/mx7ulp_com_defconfig | 60 +++++++++++++++++ include/configs/mx7ulp_com.h | 103 +++++++++++++++++++++++++++++ 10 files changed, 470 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx7ulp-com.dts create mode 100644 board/ea/mx7ulp_com/Kconfig create mode 100644 board/ea/mx7ulp_com/MAINTAINERS create mode 100644 board/ea/mx7ulp_com/Makefile create mode 100644 board/ea/mx7ulp_com/imximage.cfg create mode 100644 board/ea/mx7ulp_com/mx7ulp_com.c create mode 100644 configs/mx7ulp_com_defconfig create mode 100644 include/configs/mx7ulp_com.h (limited to 'configs') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 88b2bf452a2..afe38e10b13 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -688,7 +688,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ imx7d-pico-hobbit.dtb -dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb +dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \ + imx7ulp-evk.dtb dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qm-apalis.dtb \ diff --git a/arch/arm/dts/imx7ulp-com.dts b/arch/arm/dts/imx7ulp-com.dts new file mode 100644 index 00000000000..c01e03dd061 --- /dev/null +++ b/arch/arm/dts/imx7ulp-com.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2019 NXP +// Author: Fabio Estevam + +/dts-v1/; + +#include "imx7ulp.dtsi" + +/ { + model = "Embedded Artists i.MX7ULP COM"; + compatible = "ea,imx7ulp-com", "fsl,imx7ulp"; + + chosen { + stdout-path = &lpuart4; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x8000000>; + }; +}; + +&lpuart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart4>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <88>; +}; + +&usdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc0>; + non-removable; + bus-width = <8>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + IMX7ULP_PAD_PTC1__PTC1 0x20000 + >; + }; + + pinctrl_lpuart4: lpuart4grp { + fsl,pins = < + IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 + IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 + IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042 + IMX7ULP_PAD_PTD3__SDHC0_D7 0x43 + IMX7ULP_PAD_PTD4__SDHC0_D6 0x43 + IMX7ULP_PAD_PTD5__SDHC0_D5 0x43 + IMX7ULP_PAD_PTD6__SDHC0_D4 0x43 + IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 + IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 + IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 + IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 + IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42 + >; + }; + + pinctrl_usbotg1_id: otg1idgrp { + fsl,pins = < + IMX7ULP_PAD_PTC13__USB0_ID 0x10003 + >; + }; +}; diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig index 138c58363f5..6680f856c5b 100644 --- a/arch/arm/mach-imx/mx7ulp/Kconfig +++ b/arch/arm/mach-imx/mx7ulp/Kconfig @@ -15,6 +15,11 @@ choice prompt "MX7ULP board select" optional +config TARGET_MX7ULP_COM + bool "Support MX7ULP COM board" + select MX7ULP + select SYS_ARCH_TIMER + config TARGET_MX7ULP_EVK bool "Support mx7ulp EVK board" select MX7ULP @@ -22,6 +27,7 @@ config TARGET_MX7ULP_EVK endchoice +source "board/ea/mx7ulp_com/Kconfig" source "board/freescale/mx7ulp_evk/Kconfig" endif diff --git a/board/ea/mx7ulp_com/Kconfig b/board/ea/mx7ulp_com/Kconfig new file mode 100644 index 00000000000..90883aced45 --- /dev/null +++ b/board/ea/mx7ulp_com/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX7ULP_COM + +config SYS_BOARD + default "mx7ulp_com" + +config SYS_VENDOR + default "ea" + +config SYS_CONFIG_NAME + default "mx7ulp_com" + +endif diff --git a/board/ea/mx7ulp_com/MAINTAINERS b/board/ea/mx7ulp_com/MAINTAINERS new file mode 100644 index 00000000000..3f69511b1a1 --- /dev/null +++ b/board/ea/mx7ulp_com/MAINTAINERS @@ -0,0 +1,6 @@ +MX7ULPCOM BOARD +M: Fabio Estevam +S: Maintained +F: board/ea/mx7ulp_com/ +F: include/configs/mx7ulp_com.h +F: configs/mx7ulp_com_defconfig diff --git a/board/ea/mx7ulp_com/Makefile b/board/ea/mx7ulp_com/Makefile new file mode 100644 index 00000000000..b3b230b1727 --- /dev/null +++ b/board/ea/mx7ulp_com/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx7ulp_com.o diff --git a/board/ea/mx7ulp_com/imximage.cfg b/board/ea/mx7ulp_com/imximage.cfg new file mode 100644 index 00000000000..d298d17c1e9 --- /dev/null +++ b/board/ea/mx7ulp_com/imximage.cfg @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7ulp_evk/plugin.bin 0x2F020000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x403f00dc 0x00000000 +DATA 4 0x403e0040 0x01000020 +DATA 4 0x403e0500 0x01000000 +DATA 4 0x403e050c 0x80808080 +DATA 4 0x403e0508 0x00160002 +DATA 4 0x403E0510 0x00000001 +DATA 4 0x403E0514 0x00000014 +DATA 4 0x403e0500 0x00000001 +CHECK_BITS_SET 4 0x403e0500 0x01000000 +/* + * Default PFD0 divide is 27, which generates: + * PFD0 Freq = A7 APLL (528MHz) * 18 / 27 = 352MHz + * + * i.MX7ULP COM board can not run DDR at 352MHz, so + * use a divider of 30 (0x1E), which gives: + * + * PFD0 Freq = A7 APLL (528MHz) * 18 / 30 = 316.8MHz + */ +DATA 4 0x403e050c 0x8080801E +CHECK_BITS_SET 4 0x403e050c 0x00000040 +DATA 4 0x403E0030 0x00000001 +DATA 4 0x403e0040 0x11000020 +DATA 4 0x403f00dc 0x42000000 + +DATA 4 0x40B300AC 0x40000000 + +DATA 4 0x40AD0128 0x00040000 +DATA 4 0x40AD00F8 0x00000000 +DATA 4 0x40AD00D8 0x00000180 +DATA 4 0x40AD0104 0x00000180 +DATA 4 0x40AD0108 0x00000180 +DATA 4 0x40AD0124 0x00010000 +DATA 4 0x40AD0080 0x0000018C +DATA 4 0x40AD0084 0x0000018C +DATA 4 0x40AD0088 0x0000018C +DATA 4 0x40AD008C 0x0000018C + +DATA 4 0x40AD0120 0x00010000 +DATA 4 0x40AD010C 0x00000180 +DATA 4 0x40AD0110 0x00000180 +DATA 4 0x40AD0114 0x00000180 +DATA 4 0x40AD0118 0x00000180 +DATA 4 0x40AD0090 0x00000180 +DATA 4 0x40AD0094 0x00000180 +DATA 4 0x40AD0098 0x00000180 +DATA 4 0x40AD009C 0x00000180 + +DATA 4 0x40AD00E0 0x00040000 +DATA 4 0x40AD00E4 0x00040000 + +DATA 4 0x40AB001C 0x00008000 +DATA 4 0x40AB085C 0x0D3900A0 +DATA 4 0x40AB0800 0xA1390003 +DATA 4 0x40AB0890 0x00400000 +DATA 4 0x40AB081C 0x33333333 +DATA 4 0x40AB0820 0x33333333 +DATA 4 0x40AB0824 0x33333333 +DATA 4 0x40AB0828 0x33333333 +DATA 4 0x40AB08C0 0x24922492 +DATA 4 0x40AB0848 0x3A3E3838 +DATA 4 0x40AB0850 0x28282C2A +DATA 4 0x40AB083C 0x20000000 +DATA 4 0x40AB0840 0x00000000 +DATA 4 0x40AB08B8 0x00000800 +DATA 4 0x40AB000C 0x292C40F5 +DATA 4 0x40AB0004 0x00020064 +DATA 4 0x40AB0010 0xB6AD0A83 +DATA 4 0x40AB0014 0x00C70093 +DATA 4 0x40AB0018 0x00211708 +DATA 4 0x40AB002C 0x0F9F26D2 +DATA 4 0x40AB0030 0x009F0E10 +DATA 4 0x40AB0038 0x00130556 +DATA 4 0x40AB0008 0x12272000 +DATA 4 0x40AB0040 0x0000003F +DATA 4 0x40AB0000 0xC3110000 +DATA 4 0x40AB001C 0x00008010 +DATA 4 0x40AB001C 0x00008018 +DATA 4 0x40AB001C 0x003F8030 +DATA 4 0x40AB001C 0xFF0A8030 +DATA 4 0x40AB001C 0x82018030 +DATA 4 0x40AB001C 0x06028030 +DATA 4 0x40AB001C 0x01038030 +DATA 4 0x40AB001C 0x003F8038 +DATA 4 0x40AB001C 0xFF0A8038 +DATA 4 0x40AB001C 0x82018038 +DATA 4 0x40AB001C 0x06028038 +DATA 4 0x40AB001C 0x01038038 +DATA 4 0x40AB083C 0xA0000000 +DATA 4 0x40AB083C 0xA0000000 +DATA 4 0x40AB0020 0x00001800 +DATA 4 0x40AB0800 0xA1310003 +DATA 4 0x40AB001C 0x00000000 +#endif diff --git a/board/ea/mx7ulp_com/mx7ulp_com.c b/board/ea/mx7ulp_com/mx7ulp_com.c new file mode 100644 index 00000000000..6fc1631bf72 --- /dev/null +++ b/board/ea/mx7ulp_com/mx7ulp_com.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_UP) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_cfg_t const lpuart4_pads[] = { + MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + mx7ulp_iomux_setup_multiple_pads(lpuart4_pads, + ARRAY_SIZE(lpuart4_pads)); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} diff --git a/configs/mx7ulp_com_defconfig b/configs/mx7ulp_com_defconfig new file mode 100644 index 00000000000..b6b0cca5417 --- /dev/null +++ b/configs/mx7ulp_com_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7ULP=y +CONFIG_SYS_TEXT_BASE=0x67800000 +CONFIG_LDO_ENABLED_MODE=y +CONFIG_TARGET_MX7ULP_COM=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xC0000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ea/mx7ulp_com/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7ulp-com" +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_READ=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-com" +CONFIG_ENV_IS_IN_MMC=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_IMX_RGPIO2P=y +# CONFIG_MXC_GPIO is not set +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7ULP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_ULP_WATCHDOG=y diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h new file mode 100644 index 00000000000..bccfea812d4 --- /dev/null +++ b/include/configs/mx7ulp_com.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Embedded Artists i.MX7ULP COM board. + */ + +#ifndef __MX7ULP_COM_CONFIG_H +#define __MX7ULP_COM_CONFIG_H + +#include +#include + +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_SYS_BOOTM_LEN 0x1000000 + +#define SRC_BASE_ADDR CMC1_RBASE +#define IRAM_BASE_ADDR OCRAM_0_BASE +#define IOMUXC_BASE_ADDR IOMUXC1_RBASE + +/* + * Detect overlap between U-Boot image and environment area in build-time + * + * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot-dtb.imx offset + * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408 + * + * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so + * write the direct value here + */ +#define CONFIG_BOARD_SIZE_LIMIT 785408 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_MMCROOT "/dev/mmcblk0p2" +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG1_RBASE + +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */ + +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) + +/* UART */ +#define LPUART_BASE LPUART4_RBASE + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Physical Memory Map */ + +#define PHYS_SDRAM 0x60000000 +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM + +#define CONFIG_LOADADDR 0x60800000 + +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_512M) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "image=zImage\0" \ + "console=ttyLP0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx7ulp-com.dtb\0" \ + "fdt_addr=0x63000000\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if run loadimage; then " \ + "run mmcboot; " \ + "fi; " \ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) +#define CONFIG_CMD_CACHE +#endif + +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 0d52bab4621cd666a98f42b1e632f76662835b5f Mon Sep 17 00:00:00 2001 From: Joris Offouga Date: Sun, 8 Dec 2019 18:02:30 +0100 Subject: mx7dsabre: Enable DM_ETH Also sync device tree with v5.5-rc1 Signed-off-by: Joris Offouga --- arch/arm/dts/imx7d-sdb-u-boot.dtsi | 3 + arch/arm/dts/imx7d-sdb.dts | 785 ++++++++++++++++++++++-------- board/freescale/mx7dsabresd/mx7dsabresd.c | 62 --- configs/mx7dsabresd_defconfig | 6 + configs/mx7dsabresd_qspi_defconfig | 6 + include/configs/mx7dsabresd.h | 10 - 6 files changed, 589 insertions(+), 283 deletions(-) create mode 100644 arch/arm/dts/imx7d-sdb-u-boot.dtsi (limited to 'configs') diff --git a/arch/arm/dts/imx7d-sdb-u-boot.dtsi b/arch/arm/dts/imx7d-sdb-u-boot.dtsi new file mode 100644 index 00000000000..05dd74eee10 --- /dev/null +++ b/arch/arm/dts/imx7d-sdb-u-boot.dtsi @@ -0,0 +1,3 @@ +&fec2 { + status = "disable"; +}; diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts index 76aa69a35b3..8191ac7c334 100644 --- a/arch/arm/dts/imx7d-sdb.dts +++ b/arch/arm/dts/imx7d-sdb.dts @@ -11,253 +11,244 @@ model = "Freescale i.MX7 SabreSD Board"; compatible = "fsl,imx7d-sdb", "fsl,imx7d"; - aliases { - spi5 = &soft_spi; + chosen { + stdout-path = &uart1; }; - memory { + memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x80000000>; }; - soft_spi: soft-spi { + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + volume-up { + label = "Volume Up"; + gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + spi4 { compatible = "spi-gpio"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - status = "okay"; - gpio-sck = <&gpio1 13 0>; - gpio-mosi = <&gpio1 9 0>; - cs-gpios = <&gpio1 12 0>; + pinctrl-0 = <&pinctrl_spi4>; + gpio-sck = <&gpio1 13 GPIO_ACTIVE_LOW>; + gpio-mosi = <&gpio1 9 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; num-chipselects = <1>; #address-cells = <1>; #size-cells = <0>; - gpio_spi: gpio_spi@0 { + extended_io: gpio-expander@0 { compatible = "fairchild,74hc595"; gpio-controller; #gpio-cells = <2>; reg = <0>; registers-number = <1>; - registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/ spi-max-frequency = <100000>; }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_usb_otg1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_usb_otg2_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_sd1_vmmc: regulator@3 { - compatible = "regulator-fixed"; - regulator-name = "VDD_SD1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; - startup-delay-us = <200000>; - enable-active-high; - }; + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; -}; -&iomuxc { - imx7d-sdb { - pinctrl_spi1: spi1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 - MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 - >; - }; + reg_brcm: regulator-brcm { + compatible = "regulator-fixed"; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "brcm_reg"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f - >; - }; + reg_lcd_3v3: regulator-lcd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "lcd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&extended_io 7 GPIO_ACTIVE_LOW>; + }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; + reg_can2_3v3: regulator-can2-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can2-3v3"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f - MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f - >; - }; + reg_fec2_3v3: regulator-fec2-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fec2-3v3"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f - MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f - >; - }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; - pinctrl_usdhc1_gpio: usdhc1_gpiogrp { - fsl,pins = < - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ - MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ - >; - }; + panel { + compatible = "innolux,at043tn24"; + backlight = <&backlight>; + power-supply = <®_lcd_3v3>; - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - >; + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; }; + }; +}; - pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a - MX7D_PAD_SD1_CLK__SD1_CLK 0x1a - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a - >; - }; +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; - pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5b - MX7D_PAD_SD1_CLK__SD1_CLK 0x1b - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b - >; - }; +&adc2 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x19 - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 - MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x19 /* WL_REG_ON */ - MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */ - >; - }; +&cpu0 { + cpu-supply = <&sw1a_reg>; +}; - pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x5a - MX7D_PAD_SD2_CLK__SD2_CLK 0x1a - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a - >; - }; +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + status = "okay"; - pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x5b - MX7D_PAD_SD2_CLK__SD2_CLK 0x1b - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b - >; - }; + tsc2046@0 { + compatible = "ti,tsc2046"; + reg = <0>; + spi-max-frequency = <1000000>; + pinctrl-names ="default"; + pinctrl-0 = <&pinctrl_tsc2046_pendown>; + interrupt-parent = <&gpio2>; + interrupts = <29 0>; + pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; + ti,x-min = /bits/ 16 <0>; + ti,x-max = /bits/ 16 <0>; + ti,y-min = /bits/ 16 <0>; + ti,y-max = /bits/ 16 <0>; + ti,pressure-max = /bits/ 16 <0>; + ti,x-plate-ohms = /bits/ 16 <400>; + wakeup-source; + }; +}; - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 - >; - }; +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>; + status = "okay"; - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a - >; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; }; - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x1b - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b - >; + ethphy1: ethernet-phy@1 { + reg = <1>; }; }; }; +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_3v3>; + fsl,magic-packet; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "okay"; +}; + &i2c1 { - clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@08 { + pmic: pfuze3000@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; regulators { sw1a_reg: sw1a { regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <1475000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <6250>; @@ -273,8 +264,8 @@ }; sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; @@ -312,7 +303,6 @@ vgen2_reg: vldo2 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <1550000>; - regulator-always-on; }; vgen3_reg: vccsd { @@ -334,8 +324,8 @@ }; vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; regulator-always-on; }; }; @@ -343,36 +333,87 @@ }; &i2c2 { - clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; }; &i2c3 { - clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; }; &i2c4 { - clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clock-names = "mclk"; + wlf,shared-lrclk; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; }; &usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_sd1_vmmc>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + wakeup-source; + keep-power-in-suspend; status = "okay"; }; @@ -381,9 +422,11 @@ pinctrl-0 = <&pinctrl_usdhc2>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + wakeup-source; + keep-power-in-suspend; non-removable; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + vmmc-supply = <®_brcm>; + fsl,tuning-step = <2>; status = "okay"; }; @@ -392,9 +435,329 @@ pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; bus-width = <8>; + fsl,tuning-step = <2>; non-removable; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; status = "okay"; }; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx7d-sdb { + pinctrl_brcm_reg: brcmreggrp { + fsl,pins = < + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 + MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 + MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_enet2_reg: enet2reggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 + >; + }; + + pinctrl_flexcan2_reg: flexcan2reggrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */ + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 + MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + MX7D_PAD_LCD_RESET__LCD_RESET 0x79 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 + >; + }; + + pinctrl_tsc2046_pendown: tsc2046_pendown { + fsl,pins = < + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 + MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 + MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 + MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 + MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 + MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 + MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + >; + }; + + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&iomuxc_lpsr { + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 + >; + }; + + pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; +}; diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index f1120d67e37..70490ba68e3 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include "../common/pfuze.h" @@ -29,11 +28,6 @@ DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) -#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) -#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) - #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ PAD_CTL_DSE_3P3V_49OHM) @@ -170,30 +164,6 @@ static int setup_lcd(void) } #endif -#ifdef CONFIG_FEC_MXC -static iomux_v3_cfg_t const fec1_pads[] = { - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), - MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), -}; - -static void setup_iomux_fec(void) -{ - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); -} -#endif - static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); @@ -216,37 +186,6 @@ int mmc_map_to_kernel_blk(int dev_no) } #ifdef CONFIG_FEC_MXC -int board_eth_init(bd_t *bis) -{ - int ret; - unsigned int gpio; - - ret = gpio_lookup_name("gpio_spi@0_5", NULL, NULL, &gpio); - if (ret) { - printf("GPIO: 'gpio_spi@0_5' not found\n"); - return -ENODEV; - } - - ret = gpio_request(gpio, "fec_rst"); - if (ret && ret != -EBUSY) { - printf("gpio: requesting pin %u failed\n", gpio); - return ret; - } - - gpio_direction_output(gpio, 0); - udelay(500); - gpio_direction_output(gpio, 1); - - setup_iomux_fec(); - - ret = fecmxc_initialize_multi(bis, 0, - CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); - if (ret) - printf("FEC1 MXC: %s:failed\n", __func__); - - return ret; -} - static int setup_fec(void) { struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs @@ -260,7 +199,6 @@ static int setup_fec(void) return set_clk_enet(ENET_125MHZ); } - int board_phy_config(struct phy_device *phydev) { /* enable rgmii rxc skew and phy mode select to RGMII copper */ diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 2a9fdac338a..a85db33a14d 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -59,6 +59,12 @@ CONFIG_MTD=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y CONFIG_PHYLIB=y +CONFIG_PHY_BROADCOM=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig index 865ce30dc26..c1055603050 100644 --- a/configs/mx7dsabresd_qspi_defconfig +++ b/configs/mx7dsabresd_qspi_defconfig @@ -61,6 +61,12 @@ CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_PHYLIB=y +CONFIG_PHY_BROADCOM=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 745507571dd..f574669644c 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -17,16 +17,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) -/* Network */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_PHY_BROADCOM -/* ENET1 */ -#define IMX_FEC_BASE ENET_IPS_BASE_ADDR - /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -- cgit v1.3.1 From 80e62e3a70db8f619f23de50eb2d47541f880d3f Mon Sep 17 00:00:00 2001 From: Joris Offouga Date: Sun, 8 Dec 2019 18:02:31 +0100 Subject: mx7dsabre: Convert to distroboot support Signed-off-by: Joris Offouga --- configs/mx7dsabresd_defconfig | 13 ++---- configs/mx7dsabresd_qspi_defconfig | 14 +++---- include/configs/mx7dsabresd.h | 84 ++++++++------------------------------ 3 files changed, 25 insertions(+), 86 deletions(-) (limited to 'configs') diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index a85db33a14d..883f21f1bc1 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -9,13 +9,13 @@ CONFIG_ARMV7_BOOT_SEC_DEFAULT=y # CONFIG_ARMV7_VIRT is not set CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y +CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" +CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOUNCE_BUFFER=y -CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTD is not set -CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set @@ -30,17 +30,13 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -81,7 +77,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig index c1055603050..b2d5dc1c222 100644 --- a/configs/mx7dsabresd_qspi_defconfig +++ b/configs/mx7dsabresd_qspi_defconfig @@ -4,17 +4,18 @@ CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_TARGET_MX7DSABRESD=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 +CONFIG_NR_DRAM_BANKS=1 CONFIG_ARMV7_BOOT_SEC_DEFAULT=y # CONFIG_ARMV7_VIRT is not set CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y +CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" +CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOUNCE_BUFFER=y -CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTD is not set -CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set @@ -29,17 +30,13 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-qspi" CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -84,7 +81,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index f574669644c..b1726b1d88c 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -74,76 +74,25 @@ "image=zImage\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ + "finduuid=part uuid mmc 0:1 uuid\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx7d-sdb.dtb\0" \ + "fdtfile=imx7d-sdb.dtb\0" \ "fdt_addr=0x83000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ + "fdt_addr_r=0x83000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_addr_r=0x83000000\0" \ + "ramdiskaddr=0x83000000\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) \ + func(PXE, pxe, na) + +#include #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) @@ -187,7 +136,6 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ -#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -- cgit v1.3.1 From 87271ed8ebf0217471ea5f785402488f5fb7a26d Mon Sep 17 00:00:00 2001 From: Joris Offouga Date: Sun, 8 Dec 2019 18:02:28 +0100 Subject: mx7dsabre: Remove warning about DM_SPI_FLASH This defconfig doesn't need it. Signed-off-by: Joris Offouga --- configs/mx7dsabresd_defconfig | 3 --- 1 file changed, 3 deletions(-) (limited to 'configs') diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 883f21f1bc1..d15de386fcc 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -51,9 +51,6 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_EON=y CONFIG_PHYLIB=y CONFIG_PHY_BROADCOM=y CONFIG_DM_ETH=y -- cgit v1.3.1 From 431cd76dd8032a0df3afa9a3e82b67500841d4cb Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Mon, 4 Nov 2019 11:12:00 +0100 Subject: colibri_imx6: migrate to DM_ETH Migrate to DM_ETH and remove hardcoded pinmux configuration. Signed-off-by: Igor Opaniuk Reviewed-by: Oleksandr Suvorov --- board/toradex/colibri_imx6/colibri_imx6.c | 59 +++---------------------------- configs/colibri_imx6_defconfig | 3 ++ include/configs/colibri_imx6.h | 8 ----- 3 files changed, 7 insertions(+), 63 deletions(-) (limited to 'configs') diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index a5cd8587dad..7db9d25544c 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -51,9 +51,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_SRE_SLOW) @@ -112,24 +109,6 @@ iomux_v3_cfg_t const usdhc3_pads[] = { }; #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */ -iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -static void setup_iomux_enet(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); -} - /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */ iomux_v3_cfg_t const gpio_pads[] = { /* ADDRESS[17:18] [25] used as GPIO */ @@ -371,12 +350,8 @@ int board_phy_config(struct phy_device *phydev) return 0; } -int board_eth_init(bd_t *bis) +int setup_fec(void) { - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - uint32_t base = IMX_FEC_BASE; - struct mii_dev *bus = NULL; - struct phy_device *phydev = NULL; int ret; /* provide the PHY clock from the i.MX 6 */ @@ -384,34 +359,6 @@ int board_eth_init(bd_t *bis) if (ret) return ret; - /* set gpr1[ENET_CLK_SEL] */ - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); - - setup_iomux_enet(); - -#ifdef CONFIG_FEC_MXC - bus = fec_get_miibus(base, -1); - if (!bus) - return 0; - - /* scan PHY 1..7 */ - phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII); - if (!phydev) { - free(bus); - puts("no PHY found\n"); - return 0; - } - - phy_reset(phydev); - printf("using PHY at %d\n", phydev->addr); - ret = fec_probe(bis, -1, base, bus, phydev); - if (ret) { - printf("FEC MXC: %s:failed\n", __func__); - free(phydev); - free(bus); - } -#endif /* CONFIG_FEC_MXC */ - return 0; } @@ -633,7 +580,9 @@ int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - +#if defined(CONFIG_FEC_MXC) + setup_fec(); +#endif #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index bc5d5bf6a23..8535aaecee7 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -65,6 +65,9 @@ CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 750463ef47c..cbc7501bcc1 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -43,14 +43,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 -/* Network */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 1 -#define CONFIG_TFTP_TSIZE - /* USB Configs */ /* Host */ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -- cgit v1.3.1 From a781ed271e6707c90180091b9d7b6d43d8ef8c40 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Mon, 4 Nov 2019 11:12:02 +0100 Subject: apalis_imx6: migrate to DM_ETH Migrate to DM_ETH and remove hardcoded pinmux configuration. Signed-off-by: Igor Opaniuk Reviewed-by: Oleksandr Suvorov --- board/toradex/apalis_imx6/apalis_imx6.c | 51 --------------------------------- configs/apalis_imx6_defconfig | 3 ++ include/configs/apalis_imx6.h | 6 ---- 3 files changed, 3 insertions(+), 57 deletions(-) (limited to 'configs') diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index d4d6eed11a3..d569782a192 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -177,22 +177,6 @@ iomux_v3_cfg_t const enet_pads[] = { # define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25) }; -static void setup_iomux_enet(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); -} - -static int reset_enet_phy(struct mii_dev *bus) -{ - /* Reset KSZ9031 PHY */ - gpio_request(GPIO_ENET_PHY_RESET, "ETH_RESET#"); - gpio_direction_output(GPIO_ENET_PHY_RESET, 0); - mdelay(10); - gpio_set_value(GPIO_ENET_PHY_RESET, 1); - - return 0; -} - /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */ iomux_v3_cfg_t const gpio_pads[] = { /* Apalis GPIO1 - GPIO8 */ @@ -367,41 +351,6 @@ int board_phy_config(struct phy_device *phydev) return 0; } -int board_eth_init(bd_t *bis) -{ - uint32_t base = IMX_FEC_BASE; - struct mii_dev *bus = NULL; - struct phy_device *phydev = NULL; - int ret; - - setup_iomux_enet(); - -#ifdef CONFIG_FEC_MXC - bus = fec_get_miibus(base, -1); - if (!bus) - return 0; - - bus->reset = reset_enet_phy; - /* scan PHY 4,5,6,7 */ - phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); - if (!phydev) { - free(bus); - puts("no PHY found\n"); - return 0; - } - - printf("using PHY at %d\n", phydev->addr); - ret = fec_probe(bis, -1, base, bus, phydev); - if (ret) { - printf("FEC MXC: %s:failed\n", __func__); - free(phydev); - free(bus); - } -#endif /* CONFIG_FEC_MXC */ - - return 0; -} - static iomux_v3_cfg_t const pwr_intb_pads[] = { /* * the bootrom sets the iomux to vselect, potentially connecting diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index 0d11ab53d66..cd9090621b4 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -66,6 +66,9 @@ CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 800f27ccbbb..d2ff7e95345 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -53,13 +53,7 @@ #endif /* Network */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" #define PHY_ANEG_TIMEOUT 15000 /* PHY needs longer aneg time */ -#define CONFIG_FEC_MXC_PHYADDR 6 -#define CONFIG_TFTP_TSIZE /* USB Configs */ /* Host */ -- cgit v1.3.1 From ebabbf1169b1948625762800346876d196974ecb Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Mon, 4 Nov 2019 11:12:04 +0100 Subject: colibri_imx7: migrate to DM_ETH Migrate to DM_ETH and remove hardcoded pinmux configuration. Signed-off-by: Igor Opaniuk Reviewed-by: Oleksandr Suvorov --- board/toradex/colibri_imx7/colibri_imx7.c | 44 ------------------------------- configs/colibri_imx7_defconfig | 3 +++ configs/colibri_imx7_emmc_defconfig | 3 +++ include/configs/colibri_imx7.h | 11 -------- 4 files changed, 6 insertions(+), 55 deletions(-) (limited to 'configs') diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index b0914a9ead5..77197e0fbb0 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -159,50 +159,12 @@ void board_preboot_os(void) gpio_direction_output(GPIO_BL_ON, 0); } -#ifdef CONFIG_FEC_MXC -static iomux_v3_cfg_t const fec1_pads[] = { -#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK - MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION, -#else - MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL), -#endif - MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), - MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -static void setup_iomux_fec(void) -{ - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); -} -#endif - static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } #ifdef CONFIG_FEC_MXC -int board_eth_init(bd_t *bis) -{ - int ret; - - setup_iomux_fec(); - - ret = fecmxc_initialize_multi(bis, 0, - CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); - if (ret) - printf("FEC1 MXC: %s:failed\n", __func__); - - return ret; -} - static int setup_fec(void) { struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs @@ -226,12 +188,6 @@ static int setup_fec(void) return set_clk_enet(ENET_50MHZ); } -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - return 0; -} #endif int board_early_init_f(void) diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 29ddd7d3e9c..75051c584d0 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -66,6 +66,9 @@ CONFIG_MTD_UBI_FASTMAP=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index ac2fa0e1e4e..9b42a5b466a 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -62,6 +62,9 @@ CONFIG_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 88e1be1ef58..603ea3a053a 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -16,17 +16,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) -/* Network */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_TFTP_TSIZE - -/* ENET1 */ -#define IMX_FEC_BASE ENET_IPS_BASE_ADDR - /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND -- cgit v1.3.1 From 32efcbc09f2f34e92c88bc54996e550ba3aa6ba9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 16 Dec 2019 16:09:22 -0300 Subject: imx8mm_evk: Adjust the environment for booting a mainline kernel Adjust the environment for booting a mainline kernel by default. Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan --- configs/imx8mm_evk_defconfig | 1 - include/configs/imx8mm_evk.h | 8 ++++---- 2 files changed, 4 insertions(+), 5 deletions(-) (limited to 'configs') diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index 87560ef989c..e007766e849 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -21,7 +21,6 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" -CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 991fe0056c4..7da2b900529 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -38,12 +38,12 @@ /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "image=Image.itb\0" \ + "image=Image\0" \ "console=ttymxc1,115200\0" \ "fdt_addr=0x43000000\0" \ "fdt_high=0xffffffffffffffff\0" \ - "boot_fit=try\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "boot_fit=no\0" \ + "fdt_file=imx8mm-evk.dtb\0" \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffffffffffff\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ @@ -113,7 +113,7 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */ +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ /* Size of malloc() pool */ -- cgit v1.3.1