From 137d5b9137e0eb4f543311cd1cf4a84ad913b409 Mon Sep 17 00:00:00 2001 From: Vikas Manocha Date: Thu, 2 Jul 2015 18:29:37 -0700 Subject: stv0991: enable saving enrironment in spi flash Signed-off-by: Vikas Manocha Reviewed-by: Jagannadh Teki --- configs/stv0991_defconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'configs') diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index 8e8ce9fb2d8..731ede11251 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -7,7 +7,6 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SAVEENV is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_NETDEVICES=y -- cgit v1.3.1 From 5160faf8cd99b9f0b0f844760164b1eb8689c0c5 Mon Sep 17 00:00:00 2001 From: Vikas Manocha Date: Thu, 2 Jul 2015 18:29:38 -0700 Subject: stv0991: move OF_CONTROL config to defconfig Signed-off-by: Vikas Manocha Reviewed-by: Jagannadh Teki --- configs/stv0991_defconfig | 1 + include/configs/stv0991.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'configs') diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index 731ede11251..3bdb1fc101d 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -11,3 +11,4 @@ CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_SETEXPR is not set CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y +CONFIG_OF_CONTROL=y diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index d498c1276ac..ff82afc7172 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -75,6 +75,5 @@ #define CONFIG_BOOTCOMMAND "go 0x40040000" #define CONFIG_OF_SEPARATE -#define CONFIG_OF_CONTROL #define CONFIG_OF_LIBFDT #endif /* __CONFIG_H */ -- cgit v1.3.1 From e619c79ea60f9d16c62aca05cb513e2f244d0dc5 Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Mon, 22 Jun 2015 17:57:37 -0500 Subject: blackfin: Fix build regression due to image size bf533-stamp, bf538f-ezkit, and cm-bf548 are very space limited. This was introduced by: 6e0d26c0502e (net: Handle ethaddr changes as an env callback) by enabling CONFIG_REGEX, which is too big for these boards. This patch disables CONFIG_REGEX at the expense of working with more than the first ethaddr. Signed-off-by: Joe Hershberger --- configs/bf533-stamp_defconfig | 1 + configs/bf538f-ezkit_defconfig | 1 + configs/cm-bf548_defconfig | 1 + 3 files changed, 3 insertions(+) (limited to 'configs') diff --git a/configs/bf533-stamp_defconfig b/configs/bf533-stamp_defconfig index 154dc26909f..4956078e615 100644 --- a/configs/bf533-stamp_defconfig +++ b/configs/bf533-stamp_defconfig @@ -2,4 +2,5 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_BF533_STAMP=y # CONFIG_CMD_SETEXPR is not set CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +# CONFIG_REGEX is not set CONFIG_LIB_RAND=y diff --git a/configs/bf538f-ezkit_defconfig b/configs/bf538f-ezkit_defconfig index 6cb6c6bf31b..668f9cb85d0 100644 --- a/configs/bf538f-ezkit_defconfig +++ b/configs/bf538f-ezkit_defconfig @@ -2,4 +2,5 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_BF538F_EZKIT=y # CONFIG_CMD_SETEXPR is not set CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +# CONFIG_REGEX is not set CONFIG_LIB_RAND=y diff --git a/configs/cm-bf548_defconfig b/configs/cm-bf548_defconfig index 949612d0539..49d59dd07dc 100644 --- a/configs/cm-bf548_defconfig +++ b/configs/cm-bf548_defconfig @@ -2,4 +2,5 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_CM_BF548=y # CONFIG_CMD_SETEXPR is not set CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +# CONFIG_REGEX is not set CONFIG_LIB_RAND=y -- cgit v1.3.1 From 5833521b38c014b5afffad3a70480ed4b7e00e6d Mon Sep 17 00:00:00 2001 From: Yegor Yefremov Date: Mon, 6 Jul 2015 17:28:34 +0200 Subject: arm: baltos: enable CMD_NET and FIT support in defconfig Signed-off-by: Yegor Yefremov Reviewed-by: Simon Glass --- configs/am335x_baltos_defconfig | 4 ++-- include/configs/baltos.h | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'configs') diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index bf73919c067..8e8a897ef89 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -3,9 +3,9 @@ CONFIG_TARGET_AM335X_BALTOS=y CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="NAND" -CONFIG_CONS_INDEX=1 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set diff --git a/include/configs/baltos.h b/include/configs/baltos.h index 68bfee5e8c2..632523e9652 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -39,8 +39,6 @@ #define CONFIG_CMD_PART /* FIT support */ -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ #define CONFIG_OF_BOARD_SETUP /* UBI Support */ -- cgit v1.3.1 From 990acd0d5165c3ca36716e01c5c182423bdfc16a Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 17 Jun 2015 11:15:39 +0800 Subject: x86: crownbay: Add MP initialization Intel Crown Bay board has a TunnelCreek processor which supports hyper-threading. Add /cpus node in the crownbay.dts and enable the MP initialization. Signed-off-by: Bin Meng Acked-by: Simon Glass Signed-off-by: Simon Glass (modified to remove error: overriding the value of OF_CONTROL. Old value: "y", new value: "y") --- arch/x86/dts/crownbay.dts | 20 ++++++++++++++++++++ configs/crownbay_defconfig | 4 ++++ 2 files changed, 24 insertions(+) (limited to 'configs') diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index d68efda8dfd..1ec90cda184 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -23,6 +23,26 @@ silent_console = <0>; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <1>; + intel,apic-id = <1>; + }; + + }; + gpioa { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index f3fb206b0e2..93f921638d2 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -2,7 +2,10 @@ CONFIG_X86=y CONFIG_VENDOR_INTEL=y CONFIG_DEFAULT_DEVICE_TREE="crownbay" CONFIG_TARGET_CROWNBAY=y +CONFIG_SMP=y +CONFIG_MAX_CPUS=2 CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_CMD_CPU=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set @@ -11,6 +14,7 @@ CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y +CONFIG_CPU=y CONFIG_SPI_FLASH=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_VSNPRINTF=y -- cgit v1.3.1 From b0014b6423574780cdcb9a76478be0c1f83f7990 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Tue, 23 Jun 2015 12:18:43 +0800 Subject: x86: crownbay: Enable DM RTC support Add a RTC node in the device tree to enable DM RTC support. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/dts/crownbay.dts | 1 + arch/x86/dts/rtc.dtsi | 6 ++++++ configs/crownbay_defconfig | 1 + 3 files changed, 8 insertions(+) create mode 100644 arch/x86/dts/rtc.dtsi (limited to 'configs') diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index 1ec90cda184..87ed0f4f195 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -10,6 +10,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "rtc.dtsi" / { model = "Intel Crown Bay"; diff --git a/arch/x86/dts/rtc.dtsi b/arch/x86/dts/rtc.dtsi new file mode 100644 index 00000000000..93dacd7307c --- /dev/null +++ b/arch/x86/dts/rtc.dtsi @@ -0,0 +1,6 @@ +/ { + rtc { + compatible = "motorola,mc146818"; + reg = <0x70 2>; + }; +}; diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 93f921638d2..6c385042b2a 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -18,3 +18,4 @@ CONFIG_CPU=y CONFIG_SPI_FLASH=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_VSNPRINTF=y +CONFIG_DM_RTC=y -- cgit v1.3.1 From 07a52865fe4a2e8bce16d9d8f8a61c66b3afa9ee Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Tue, 23 Jun 2015 12:18:54 +0800 Subject: x86: crownbay: Enable writing MP table Enable writing MP table for Intel Crown Bay board. Signed-off-by: Bin Meng Acked-by: Simon Glass --- configs/crownbay_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'configs') diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 6c385042b2a..2af93bc4118 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -18,4 +18,5 @@ CONFIG_CPU=y CONFIG_SPI_FLASH=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_VSNPRINTF=y +CONFIG_GENERATE_MP_TABLE=y CONFIG_DM_RTC=y -- cgit v1.3.1 From 786a08e0dd3d0505e10cc93622ce5db696c627e9 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 6 Jul 2015 16:31:33 +0800 Subject: x86: Move VGA option rom macros to Kconfig Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on HAVE_VGA_BIOS. The new names are consistent with other x86 binary blob options like HAVE_FSP/FSP_FILE/FSP_ADDR. Signed-off-by: Bin Meng Acked-by: Simon Glass --- Makefile | 4 ++-- arch/x86/Kconfig | 22 ++++++++++++++++++++++ configs/chromebook_link_defconfig | 1 + configs/chromebox_panther_defconfig | 1 + configs/minnowmax_defconfig | 1 + doc/README.x86 | 2 +- drivers/pci/pci_rom.c | 4 ++-- include/configs/minnowmax.h | 3 --- include/configs/x86-chromebook.h | 3 --- 9 files changed, 30 insertions(+), 11 deletions(-) (limited to 'configs') diff --git a/Makefile b/Makefile index a7dce064081..b6f83a55305 100644 --- a/Makefile +++ b/Makefile @@ -1035,8 +1035,8 @@ ifneq ($(CONFIG_HAVE_CMC),) IFDTOOL_FLAGS += -w $(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE) endif -ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),) -IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILE) +ifneq ($(CONFIG_HAVE_VGA_BIOS),) +IFDTOOL_FLAGS += -w $(CONFIG_VGA_BIOS_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_VGA_BIOS_FILE) endif quiet_cmd_ifdtool = IFDTOOL $@ diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index b52a80e1c20..8381a3be6e8 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -287,6 +287,28 @@ config TSC_FREQ_IN_MHZ help The running frequency in MHz of Time-Stamp Counter (TSC). +config HAVE_VGA_BIOS + bool "Add a VGA BIOS image" + help + Select this option if you have a VGA BIOS image that you would + like to add to your ROM. + +config VGA_BIOS_FILE + string "VGA BIOS image filename" + depends on HAVE_VGA_BIOS + default "vga.bin" + help + The filename of the VGA BIOS image in the board directory. + +config VGA_BIOS_ADDR + hex "VGA BIOS image location" + depends on HAVE_VGA_BIOS + default 0xfff90000 + help + The location of VGA BIOS image in the SPI flash. For example, base + address of 0xfff90000 indicates that the image will be put at offset + 0x90000 from the beginning of a 1MB flash device. + menu "System tables" config GENERATE_PIRQ_TABLE diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 018fe91e89c..9931d65dc2e 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -3,6 +3,7 @@ CONFIG_VENDOR_GOOGLE=y CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" CONFIG_TARGET_CHROMEBOOK_LINK=y CONFIG_HAVE_MRC=y +CONFIG_HAVE_VGA_BIOS=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index 2ac23ed97f6..b3a5f28be91 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -3,6 +3,7 @@ CONFIG_VENDOR_GOOGLE=y CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther" CONFIG_TARGET_CHROMEBOX_PANTHER=y CONFIG_HAVE_MRC=y +CONFIG_HAVE_VGA_BIOS=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index e0a9216d896..b5788052c7c 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -3,6 +3,7 @@ CONFIG_VENDOR_INTEL=y CONFIG_DEFAULT_DEVICE_TREE="minnowmax" CONFIG_TARGET_MINNOWMAX=y CONFIG_HAVE_INTEL_ME=y +CONFIG_HAVE_VGA_BIOS=y CONFIG_SMP=y CONFIG_GENERATE_SFI_TABLE=y CONFIG_CMD_CPU=y diff --git a/doc/README.x86 b/doc/README.x86 index 49d6e830460..7f3914fee13 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -79,7 +79,7 @@ Find the following files: * ./northbridge/intel/sandybridge/systemagent-r6.bin The 3rd one should be renamed to mrc.bin. -As for the video ROM, you can get it here [3]. +As for the video ROM, you can get it here [3] and rename it to vga.bin. Make sure all these binary blobs are put in the board directory. Now you can build U-Boot and obtain u-boot.rom: diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 0a644a9bc5b..dd7fd953caf 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -79,8 +79,8 @@ static int pci_rom_probe(pci_dev_t dev, uint class, if (vendev != mapped_vendev) debug("Device ID mapped to %#08x\n", mapped_vendev); -#ifdef CONFIG_X86_OPTION_ROM_ADDR - rom_address = CONFIG_X86_OPTION_ROM_ADDR; +#ifdef CONFIG_VGA_BIOS_ADDR + rom_address = CONFIG_VGA_BIOS_ADDR; #else if (pciauto_setup_rom(pci_bus_to_hose(PCI_BUS(dev)), dev)) { diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 547765d1376..8ee84a604c0 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -52,9 +52,6 @@ #undef CONFIG_USB_MAX_CONTROLLER_COUNT #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_X86_OPTION_ROM_FILE vga.bin -#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 - #define VIDEO_IO_OFFSET 0 #define CONFIG_X86EMU_RAW_IO #define CONFIG_VGA_AS_SINGLE_DEVICE diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index e0e7fca9f86..408cbb19577 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -26,9 +26,6 @@ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI} -#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin -#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 - #define CONFIG_PCI_MEM_BUS 0xe0000000 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS #define CONFIG_PCI_MEM_SIZE 0x10000000 -- cgit v1.3.1 From 7aaff9bf81b17b7920826f99a17eae7659292f5c Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 6 Jul 2015 16:31:35 +0800 Subject: x86: crownbay: Enable graphics support Enable graphics support on Intel Crown Bay board With the help of vgabios for Intel TunnelCreek IGD. Tested with an external LVDS panel connected to X4 connector and SDVO adapter connected to X9 connector on the board. Signed-off-by: Jian Luo Signed-off-by: Bin Meng Acked-by: Simon Glass --- configs/crownbay_defconfig | 3 +++ doc/README.x86 | 20 +++++++++++++------- include/configs/crownbay.h | 14 +++++++------- 3 files changed, 23 insertions(+), 14 deletions(-) (limited to 'configs') diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 2af93bc4118..379b88198c7 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -18,5 +18,8 @@ CONFIG_CPU=y CONFIG_SPI_FLASH=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_VSNPRINTF=y +CONFIG_HAVE_VGA_BIOS=y CONFIG_GENERATE_MP_TABLE=y +CONFIG_VIDEO_VESA=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_DM_RTC=y diff --git a/doc/README.x86 b/doc/README.x86 index 7f3914fee13..646eff1355f 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -113,6 +113,10 @@ binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP binary, change the following five bytes values from orginally E8 42 FF FF FF to B8 00 80 0B 00. +As for the video ROM, you need manually extract it from the Intel provided +BIOS for Crown Bay here [6], using the AMI MMTool [7]. Check PCI option ROM +ID 8086:4108, extract and save it as vga.bin in the board directory. + Now you can build U-Boot and obtain u-boot.rom $ make crownbay_defconfig @@ -254,7 +258,7 @@ If you want to check both consoles, use '-serial stdio'. CPU Microcode ------------- -Modern CPUs usually require a special bit stream called microcode [6] to be +Modern CPUs usually require a special bit stream called microcode [8] to be loaded on the processor after power up in order to function properly. U-Boot has already integrated these as hex dumps in the source tree. @@ -265,9 +269,9 @@ Additional application processors (AP) can be brought up by U-Boot. In order to have an SMP kernel to discover all of the available processors, U-Boot needs to prepare configuration tables which contain the multi-CPUs information before loading the OS kernel. Currently U-Boot supports generating two types of tables -for SMP, called Simple Firmware Interface (SFI) [7] and Multi-Processor (MP) [8] -tables. The writing of these two tables are controlled by two Kconfig options -GENERATE_SFI_TABLE and GENERATE_MP_TABLE. +for SMP, called Simple Firmware Interface (SFI) [9] and Multi-Processor (MP) +[10] tables. The writing of these two tables are controlled by two Kconfig +options GENERATE_SFI_TABLE and GENERATE_MP_TABLE. Driver Model ------------ @@ -372,6 +376,8 @@ References [3] http://www.coreboot.org/~stepan/pci8086,0166.rom [4] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html [5] http://www.intel.com/fsp -[6] http://en.wikipedia.org/wiki/Microcode -[7] http://simplefirmware.org -[8] http://www.intel.com/design/archives/processors/pro/docs/242016.htm +[6] http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/e6xx-35-b1-cmc22211.html +[7] http://www.ami.com/products/bios-uefi-tools-and-utilities/bios-uefi-utilities/ +[8] http://en.wikipedia.org/wiki/Microcode +[9] http://simplefirmware.org +[10] http://www.intel.com/design/archives/processors/pro/docs/242016.htm diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index 0e1f0467c78..6cf53a3e42a 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -32,15 +32,16 @@ #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS #define CONFIG_PCI_IO_SIZE 0xe000 +#define CONFIG_PCI_CONFIG_HOST_BRIDGE #define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP #define CONFIG_E1000 -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" -#define CONFIG_SCSI_DEV_LIST \ +#define CONFIG_SCSI_DEV_LIST \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA} #define CONFIG_SPI_FLASH_SST @@ -55,9 +56,8 @@ #define CONFIG_PCH_GBE #define CONFIG_PHYLIB -/* Video is not supported */ -#undef CONFIG_VIDEO -#undef CONFIG_CFB_CONSOLE +/* TunnelCreek IGD support */ +#define CONFIG_VGA_AS_SINGLE_DEVICE /* Environment configuration */ #define CONFIG_ENV_SECT_SIZE 0x1000 -- cgit v1.3.1 From b71f9dca89013b8b100006029c98d04b495ebdf7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 3 Jul 2015 18:28:26 -0600 Subject: dm: x86: minnowmax: Move PCI to use driver model Adjust minnowmax to use driver model for PCI. This requires adding a device tree node to specify the ranges, removing the board-specific PCI code and ensuring that the host bridge is configured. Reviewed-by: Bin Meng Signed-off-by: Simon Glass --- arch/x86/cpu/baytrail/Makefile | 1 - arch/x86/cpu/baytrail/pci.c | 46 ------------------------------------------ arch/x86/dts/minnowmax.dts | 10 +++++++++ configs/minnowmax_defconfig | 1 + include/configs/minnowmax.h | 1 + 5 files changed, 12 insertions(+), 47 deletions(-) delete mode 100644 arch/x86/cpu/baytrail/pci.c (limited to 'configs') diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile index c78b644eb71..5be5491643b 100644 --- a/arch/x86/cpu/baytrail/Makefile +++ b/arch/x86/cpu/baytrail/Makefile @@ -7,5 +7,4 @@ obj-y += cpu.o obj-y += early_uart.o obj-y += fsp_configs.o -obj-y += pci.o obj-y += valleyview.o diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c deleted file mode 100644 index 48409de5c4d..00000000000 --- a/arch/x86/cpu/baytrail/pci.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (C) 2014, Bin Meng - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void board_pci_setup_hose(struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->last_busno = 0; - - /* PCI memory space */ - pci_set_region(hose->regions + 0, - CONFIG_PCI_MEM_BUS, - CONFIG_PCI_MEM_PHYS, - CONFIG_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 1, - CONFIG_PCI_IO_BUS, - CONFIG_PCI_IO_PHYS, - CONFIG_PCI_IO_SIZE, - PCI_REGION_IO); - - pci_set_region(hose->regions + 2, - CONFIG_PCI_PREF_BUS, - CONFIG_PCI_PREF_PHYS, - CONFIG_PCI_PREF_SIZE, - PCI_REGION_PREFETCH); - - pci_set_region(hose->regions + 3, - 0, - 0, - gd->ram_size < 0x80000000 ? gd->ram_size : 0x80000000, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose->region_count = 4; -} diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index bd21bfb0b4f..0e59b18d340 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -111,6 +111,16 @@ }; + pci { + compatible = "intel,pci-baytrail", "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0 0x10000000 + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x10000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + }; + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index b5788052c7c..45f666c41e5 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -22,3 +22,4 @@ CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_VSNPRINTF=y +CONFIG_DM_PCI=y diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index e0f6f8a35c1..af36ac5cafe 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -32,6 +32,7 @@ #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS #define CONFIG_PCI_IO_SIZE 0xe000 +#define CONFIG_PCI_CONFIG_HOST_BRIDGE #define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP #define CONFIG_RTL8169 -- cgit v1.3.1 From aeda4ab664d50a7b620c8b8a4075f9512110e180 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 9 Jul 2015 18:37:40 +0800 Subject: x86: Adjust config option order in defconfig for Crown Bay and Minnowmax Update crownbay_defconfig and minnowmax_defconfig with 'savedefconfig' result so that the config option order matches Kconfig. Signed-off-by: Bin Meng Acked-by: Simon Glass --- configs/crownbay_defconfig | 8 ++++---- configs/minnowmax_defconfig | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'configs') diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 379b88198c7..17e6a72c9d9 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -4,7 +4,9 @@ CONFIG_DEFAULT_DEVICE_TREE="crownbay" CONFIG_TARGET_CROWNBAY=y CONFIG_SMP=y CONFIG_MAX_CPUS=2 +CONFIG_HAVE_VGA_BIOS=y CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_MP_TABLE=y CONFIG_CMD_CPU=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set @@ -16,10 +18,8 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y CONFIG_CPU=y CONFIG_SPI_FLASH=y -CONFIG_USE_PRIVATE_LIBGCC=y -CONFIG_SYS_VSNPRINTF=y -CONFIG_HAVE_VGA_BIOS=y -CONFIG_GENERATE_MP_TABLE=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_DM_RTC=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_SYS_VSNPRINTF=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 45f666c41e5..29dd44b4009 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -3,8 +3,8 @@ CONFIG_VENDOR_INTEL=y CONFIG_DEFAULT_DEVICE_TREE="minnowmax" CONFIG_TARGET_MINNOWMAX=y CONFIG_HAVE_INTEL_ME=y -CONFIG_HAVE_VGA_BIOS=y CONFIG_SMP=y +CONFIG_HAVE_VGA_BIOS=y CONFIG_GENERATE_SFI_TABLE=y CONFIG_CMD_CPU=y # CONFIG_CMD_IMLS is not set @@ -16,10 +16,10 @@ CONFIG_BOOTSTAGE_REPORT=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y CONFIG_CPU=y +CONFIG_DM_PCI=y CONFIG_SPI_FLASH=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_VSNPRINTF=y -CONFIG_DM_PCI=y -- cgit v1.3.1