From a439680019e06171d4a5694b7992accce87f590e Mon Sep 17 00:00:00 2001 From: Grant Erickson Date: Wed, 21 May 2008 13:28:30 -0700 Subject: PPC4xx: Simplified post_word_{load, store} This patch simplifies post_word_{load,store} by using the preprocessor to eliminate redundant, copy-and-pasted code. Signed-off-by: Grant Erickson --- cpu/ppc4xx/commproc.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/commproc.c b/cpu/ppc4xx/commproc.c index 22156dd9ded..8b2954c16cc 100644 --- a/cpu/ppc4xx/commproc.c +++ b/cpu/ppc4xx/commproc.c @@ -30,29 +30,25 @@ #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) -#if defined(CFG_POST_ALT_WORD_ADDR) -void post_word_store (ulong a) -{ - out_be32((void *)CFG_POST_ALT_WORD_ADDR, a); -} +#if defined(CFG_POST_WORD_ADDR) +# define _POST_ADDR ((CFG_OCM_DATA_ADDR) + (CFG_POST_WORD_ADDR)) +#elif defined(CFG_POST_ALT_WORD_ADDR) +# define _POST_ADDR (CFG_POST_ALT_WORD_ADDR) +#endif -ulong post_word_load (void) -{ - return in_be32((void *)CFG_POST_ALT_WORD_ADDR); -} -#else /* CFG_POST_ALT_WORD_ADDR */ void post_word_store (ulong a) { - volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR); - *(volatile ulong *) save_addr = a; + volatile void *save_addr = (volatile void *)(_POST_ADDR); + + out_be32(save_addr, a); } ulong post_word_load (void) { - volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR); - return *(volatile ulong *) save_addr; + volatile void *save_addr = (volatile void *)(_POST_ADDR); + + return in_be32(save_addr); } -#endif /* CFG_POST_ALT_WORD_ADDR */ #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ -- cgit v1.3.1 From c821b5f120bedf73867513466412587c6912a8f8 Mon Sep 17 00:00:00 2001 From: Grant Erickson Date: Thu, 22 May 2008 14:44:14 -0700 Subject: ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling This patch (Part 1 of 2): * Rolls up a suite of changes to enable correct primordial stack and global data handling when the data cache is used for such a purpose for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). * Related to the first, unifies DDR2 SDRAM and ECC initialization by eliminating redundant ECC initialization implementations and moving redundant SDRAM initialization out of board code into shared 4xx code. * Enables MCSR visibility on the 405EX(r). * Enables the use of the data cache for initial RAM on both AMCC's Kilauea and Makalu and removes a redundant CFG_POST_MEMORY flag from each board's CONFIG_POST value. - Removed, per Stefan Roese's request, defunct memory.c file for Makalu and rolled sdram_init from it into makalu.c. With respect to the 4xx DDR initialization and ECC unification, there is certainly more work that can and should be done (file renaming, etc.). However, that can be handled at a later date on a second or third pass. As it stands, this patch moves things forward in an incremental yet positive way for those platforms that utilize this code and the features associated with it. Signed-off-by: Grant Erickson Signed-off-by: Stefan Roese --- cpu/ppc4xx/44x_spd_ddr.c | 49 +------ cpu/ppc4xx/44x_spd_ddr2.c | 120 ++++++++++++++++- cpu/ppc4xx/Makefile | 1 + cpu/ppc4xx/cpu_init.c | 85 ------------ cpu/ppc4xx/ecc.c | 121 +++++++++++++++++ cpu/ppc4xx/ecc.h | 42 ++++++ cpu/ppc4xx/sdram.c | 44 +------ cpu/ppc4xx/start.S | 314 +++++++++++++++++++++++++++++++++----------- cpu/ppc4xx/traps.c | 9 +- include/asm-ppc/processor.h | 6 +- include/ppc405.h | 191 +++++++++++++++++++++++++-- include/ppc4xx.h | 15 +++ 12 files changed, 723 insertions(+), 274 deletions(-) create mode 100644 cpu/ppc4xx/ecc.c create mode 100644 cpu/ppc4xx/ecc.h (limited to 'cpu') diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index b9cf5cbfcca..b7eeaf2fe26 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -53,6 +53,8 @@ #include #include +#include "ecc.h" + #if defined(CONFIG_SPD_EEPROM) && \ (defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR)) @@ -296,10 +298,6 @@ static void program_tr0(unsigned long *dimm_populated, unsigned long num_dimm_banks); static void program_tr1(void); -#ifdef CONFIG_DDR_ECC -static void program_ecc(unsigned long num_bytes); -#endif - static unsigned long program_bxcr(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks); @@ -418,7 +416,7 @@ long int spd_sdram(void) { /* * If ecc is enabled, initialize the parity bits. */ - program_ecc(total_size); + ecc_init(CFG_SDRAM_BASE, total_size); #endif return total_size; @@ -1402,45 +1400,4 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, return(bank_base_addr); } - -#ifdef CONFIG_DDR_ECC -static void program_ecc(unsigned long num_bytes) -{ - unsigned long bank_base_addr; - unsigned long current_address; - unsigned long end_address; - unsigned long address_increment; - unsigned long cfg0; - - /* - * get Memory Controller Options 0 data - */ - mfsdram(mem_cfg0, cfg0); - - /* - * reset the bank_base address - */ - bank_base_addr = CFG_SDRAM_BASE; - - if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) { - mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_GEN); - - if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) - address_increment = 4; - else - address_increment = 8; - - current_address = (unsigned long)(bank_base_addr); - end_address = (unsigned long)(bank_base_addr) + num_bytes; - - while (current_address < end_address) { - *((unsigned long*)current_address) = 0x00000000; - current_address += address_increment; - } - - mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | - SDRAM_CFG0_MCHK_CHK); - } -} -#endif /* CONFIG_DDR_ECC */ #endif /* CONFIG_SPD_EEPROM */ diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index ec76b718bcc..aa4a5302e0d 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -3,9 +3,12 @@ * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a * DDR2 controller (non Denali Core). Those currently are: * - * 405: 405EX + * 405: 405EX(r) * 440/460: 440SP/440SPe/460EX/460GT * + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * @@ -45,6 +48,8 @@ #include #include +#include "ecc.h" + #if defined(CONFIG_SPD_EEPROM) && \ (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT)) @@ -3064,9 +3069,116 @@ static void ppc440sp_sdram_register_dump(void) dcr_data = mfdcr(SDRAM_R3BAS); printf(" MQ3_B0BAS = 0x%08X\n", dcr_data); } -#else +#else /* !defined(DEBUG) */ static void ppc440sp_sdram_register_dump(void) { } -#endif -#endif /* CONFIG_SPD_EEPROM */ +#endif /* defined(DEBUG) */ +#elif defined(CONFIG_405EX) +/*----------------------------------------------------------------------------- + * Function: initdram + * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory + * banks. The configuration is performed using static, compile- + * time parameters. + *---------------------------------------------------------------------------*/ +long initdram(int board_type) +{ + unsigned long val; + + /* Set Memory Bank Configuration Registers */ + + mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF); + mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF); + mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF); + mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF); + + /* Set Memory Clock Timing Register */ + + mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR); + + /* Set Refresh Time Register */ + + mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR); + + /* Set SDRAM Timing Registers */ + + mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1); + mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2); + mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3); + + /* Set Mode and Extended Mode Registers */ + + mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE); + mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE); + + /* Set Memory Controller Options 1 Register */ + + mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1); + + /* Set Manual Initialization Control Registers */ + + mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0); + mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1); + mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2); + mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3); + mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4); + mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5); + mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6); + mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7); + mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8); + mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9); + mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10); + mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11); + mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12); + mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13); + mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14); + mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15); + + /* Set On-Die Termination Registers */ + + mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT); + mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0); + mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1); + + /* Set Write Timing Register */ + + mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR); + + /* + * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and + * SDRAM0_MCOPT2[IPTR] = 1 + */ + + mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT | + SDRAM_MCOPT2_IPTR_EXECUTE)); + + /* + * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the + * completion of initialization. + */ + + do { + mfsdram(SDRAM_MCSTAT, val); + } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP); + + /* Set Delay Control Registers */ + + mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR); + mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC); + mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC); + mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC); + + /* + * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1: + */ + + mfsdram(SDRAM_MCOPT2, val); + mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE); + +#if defined(CONFIG_DDR_ECC) + ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20); +#endif /* defined(CONFIG_DDR_ECC) */ + + return (CFG_MBYTES_SDRAM << 20); +} +#endif /* defined(CONFIG_SPD_EEPROM) && defined(CONFIG_440SP) || ... */ diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 178c5c67425..800bb41d014 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -45,6 +45,7 @@ COBJS += cpu.o COBJS += cpu_init.o COBJS += denali_data_eye.o COBJS += denali_spd_ddr2.o +COBJS += ecc.o COBJS += fdt.o COBJS += gpio.o COBJS += i2c.o diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 42eabfe568a..1e9423a89bf 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -32,73 +32,6 @@ DECLARE_GLOBAL_DATA_PTR; #endif -#ifdef CFG_INIT_DCACHE_CS -# if (CFG_INIT_DCACHE_CS == 0) -# define PBxAP pb0ap -# define PBxCR pb0cr -# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) -# define PBxAP_VAL CFG_EBC_PB0AP -# define PBxCR_VAL CFG_EBC_PB0CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 1) -# define PBxAP pb1ap -# define PBxCR pb1cr -# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR)) -# define PBxAP_VAL CFG_EBC_PB1AP -# define PBxCR_VAL CFG_EBC_PB1CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 2) -# define PBxAP pb2ap -# define PBxCR pb2cr -# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR)) -# define PBxAP_VAL CFG_EBC_PB2AP -# define PBxCR_VAL CFG_EBC_PB2CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 3) -# define PBxAP pb3ap -# define PBxCR pb3cr -# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR)) -# define PBxAP_VAL CFG_EBC_PB3AP -# define PBxCR_VAL CFG_EBC_PB3CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 4) -# define PBxAP pb4ap -# define PBxCR pb4cr -# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR)) -# define PBxAP_VAL CFG_EBC_PB4AP -# define PBxCR_VAL CFG_EBC_PB4CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 5) -# define PBxAP pb5ap -# define PBxCR pb5cr -# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR)) -# define PBxAP_VAL CFG_EBC_PB5AP -# define PBxCR_VAL CFG_EBC_PB5CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 6) -# define PBxAP pb6ap -# define PBxCR pb6cr -# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR)) -# define PBxAP_VAL CFG_EBC_PB6AP -# define PBxCR_VAL CFG_EBC_PB6CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 7) -# define PBxAP pb7ap -# define PBxCR pb7cr -# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR)) -# define PBxAP_VAL CFG_EBC_PB7AP -# define PBxCR_VAL CFG_EBC_PB7CR -# endif -# endif -#endif /* CFG_INIT_DCACHE_CS */ - #ifndef CFG_PLL_RECONFIG #define CFG_PLL_RECONFIG 0 #endif @@ -353,24 +286,6 @@ int cpu_init_r (void) uint pvr = get_pvr(); #endif -#ifdef CFG_INIT_DCACHE_CS - /* - * Flush and invalidate dcache, then disable CS for temporary stack. - * Afterwards, this CS can be used for other purposes - */ - dcache_disable(); /* flush and invalidate dcache */ - mtebc(PBxAP, 0); - mtebc(PBxCR, 0); /* disable CS for temporary stack */ - -#if (defined(PBxAP_VAL) && defined(PBxCR_VAL)) - /* - * Write new value into CS register - */ - mtebc(PBxAP, PBxAP_VAL); - mtebc(PBxCR, PBxCR_VAL); -#endif -#endif /* CFG_INIT_DCACHE_CS */ - /* * Write Ethernetaddress into on-chip register */ diff --git a/cpu/ppc4xx/ecc.c b/cpu/ppc4xx/ecc.c new file mode 100644 index 00000000000..95b941dabbb --- /dev/null +++ b/cpu/ppc4xx/ecc.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson + * + * (C) Copyright 2005-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2002 + * Jun Gu, Artesyn Technology, jung@artesyncp.com + * + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will abe useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Description: + * This file implements generic DRAM ECC initialization for + * PowerPC processors using a SDRAM DDR/DDR2 controller, + * including the 405EX(r), 440GP/GX/EP/GR, 440SP(E), and + * 460EX/GT. + */ + +#include +#include +#include +#include +#include +#include + +#include "ecc.h" + +#if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) +#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) +/* + * void ecc_init() + * + * Description: + * This routine initializes a range of DRAM ECC memory with known + * data and enables ECC checking. + * + * TO DO: + * - Improve performance by utilizing cache. + * - Further generalize to make usable by other 4xx variants (e.g. + * 440EPx, et al). + * + * Input(s): + * start - A pointer to the start of memory covered by ECC requiring + * initialization. + * size - The size, in bytes, of the memory covered by ECC requiring + * initialization. + * + * Output(s): + * start - A pointer to the start of memory covered by ECC with + * CFG_ECC_PATTERN written to all locations and ECC data + * primed. + * + * Returns: + * N/A + */ +void ecc_init(unsigned long * const start, unsigned long size) +{ + const unsigned long pattern = CFG_ECC_PATTERN; + unsigned * const end = (unsigned long * const)((long)start + size); + unsigned long * current = start; + unsigned long mcopt1; + long increment; + + if (start >= end) + return; + + mfsdram(SDRAM_MCOPT1, mcopt1); + + /* Enable ECC generation without checking or reporting */ + + mtsdram(SDRAM_MCOPT1, ((mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | + SDRAM_MCOPT1_MCHK_GEN)); + + increment = sizeof(u32); + +#if defined(CONFIG_440) + /* + * Look at the geometry of SDRAM (data width) to determine whether we + * can skip words when writing. + */ + + if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) != SDRAM_MCOPT1_DMWD_32) + increment = sizeof(u64); +#endif /* defined(CONFIG_440) */ + + while (current < end) { + *current = pattern; + current = (unsigned long *)((long)current + increment); + } + + /* Wait until the writes are finished. */ + + sync(); + + /* Enable ECC generation with checking and no reporting */ + + mtsdram(SDRAM_MCOPT1, ((mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | + SDRAM_MCOPT1_MCHK_CHK)); +} +#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */ +#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */ diff --git a/cpu/ppc4xx/ecc.h b/cpu/ppc4xx/ecc.h new file mode 100644 index 00000000000..da1c4fda8a1 --- /dev/null +++ b/cpu/ppc4xx/ecc.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson + * + * Copyright (c) 2007 DENX Software Engineering, GmbH + * Stefan Roese + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will abe useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Description: + * This file implements ECC initialization for PowerPC processors + * using the SDRAM DDR2 controller, including the 405EX(r), + * 440SP(E), 460EX and 460GT. + * + */ + +#ifndef _ECC_H_ +#define _ECC_H_ + +#if !defined(CFG_ECC_PATTERN) +#define CFG_ECC_PATTERN 0x00000000 +#endif /* !defined(CFG_ECC_PATTERN) */ + +extern void ecc_init(unsigned long * const start, unsigned long size); + +#endif /* _ECC_H_ */ diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index 2724d91f0f1..901d650cea1 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -31,6 +31,7 @@ #include #include #include "sdram.h" +#include "ecc.h" #ifdef CONFIG_SDRAM_BANK0 @@ -332,49 +333,6 @@ static void sdram_tr1_set(int ram_address, int* tr1_value) *tr1_value = (first_good + last_bad) / 2; } -#ifdef CONFIG_SDRAM_ECC -static void ecc_init(ulong start, ulong size) -{ - ulong current_addr; /* current byte address */ - ulong end_addr; /* end of memory region */ - ulong addr_inc; /* address skip between writes */ - ulong cfg0_reg; /* for restoring ECC state */ - - /* - * TODO: Enable dcache before running this test (speedup) - */ - - mfsdram(mem_cfg0, cfg0_reg); - mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_GEN); - - /* - * look at geometry of SDRAM (data width) to determine whether we - * can skip words when writing - */ - if ((cfg0_reg & SDRAM_CFG0_DRAMWDTH) == SDRAM_CFG0_DRAMWDTH_32) - addr_inc = 4; - else - addr_inc = 8; - - current_addr = start; - end_addr = start + size; - - while (current_addr < end_addr) { - *((ulong *)current_addr) = 0x00000000; - current_addr += addr_inc; - } - - /* - * TODO: Flush dcache and disable it again - */ - - /* - * Enable ecc checking and parity errors - */ - mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_CHK); -} -#endif - /* * Autodetect onboard DDR SDRAM on 440 platforms * diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 0008170128a..a5d9ec96e0d 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -3,6 +3,8 @@ * Copyright (C) 1999 Magnus Damm * Copyright (C) 2000,2001,2002 Wolfgang Denk * Copyright (C) 2007 Stefan Roese , DENX Software Engineering + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson * * See file CREDITS for list of people who contributed to this * project. @@ -79,34 +81,100 @@ # if (CFG_INIT_DCACHE_CS == 0) # define PBxAP pb0ap # define PBxCR pb0cr +# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) +# define PBxAP_VAL CFG_EBC_PB0AP +# define PBxCR_VAL CFG_EBC_PB0CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 1) # define PBxAP pb1ap # define PBxCR pb1cr +# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR)) +# define PBxAP_VAL CFG_EBC_PB1AP +# define PBxCR_VAL CFG_EBC_PB1CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 2) # define PBxAP pb2ap # define PBxCR pb2cr +# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR)) +# define PBxAP_VAL CFG_EBC_PB2AP +# define PBxCR_VAL CFG_EBC_PB2CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 3) # define PBxAP pb3ap # define PBxCR pb3cr +# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR)) +# define PBxAP_VAL CFG_EBC_PB3AP +# define PBxCR_VAL CFG_EBC_PB3CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 4) # define PBxAP pb4ap # define PBxCR pb4cr +# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR)) +# define PBxAP_VAL CFG_EBC_PB4AP +# define PBxCR_VAL CFG_EBC_PB4CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 5) # define PBxAP pb5ap # define PBxCR pb5cr +# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR)) +# define PBxAP_VAL CFG_EBC_PB5AP +# define PBxCR_VAL CFG_EBC_PB5CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 6) # define PBxAP pb6ap # define PBxCR pb6cr +# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR)) +# define PBxAP_VAL CFG_EBC_PB6AP +# define PBxCR_VAL CFG_EBC_PB6CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 7) # define PBxAP pb7ap # define PBxCR pb7cr +# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR)) +# define PBxAP_VAL CFG_EBC_PB7AP +# define PBxCR_VAL CFG_EBC_PB7CR +# endif +# endif +# ifndef PBxAP_VAL +# define PBxAP_VAL 0 +# endif +# ifndef PBxCR_VAL +# define PBxCR_VAL 0 +# endif +/* + * Memory Bank x (nothingness) initialization CFG_INIT_RAM_ADDR + 64 MiB + * used as temporary stack pointer for the primordial stack + */ +# ifndef CFG_INIT_DCACHE_PBxAR +# define CFG_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(7) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(2) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_NONDELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +# endif /* CFG_INIT_DCACHE_PBxAR */ +# ifndef CFG_INIT_DCACHE_PBxCR +# define CFG_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CFG_INIT_RAM_ADDR) | \ + EBC_BXCR_BS_64MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) +# endif /* CFG_INIT_DCACHE_PBxCR */ +# ifndef CFG_INIT_RAM_PATTERN +# define CFG_INIT_RAM_PATTERN 0xDEADDEAD # endif #endif /* CFG_INIT_DCACHE_CS */ @@ -114,6 +182,23 @@ #error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END! #endif +/* + * Unless otherwise overriden, enable two 128MB cachable instruction regions + * at CFG_SDRAM_BASE and another 128MB cacheable instruction region covering + * NOR flash at CFG_FLASH_BASE. Disable all cacheable data regions. + */ +#if !defined(CFG_ICACHE_SACR_VALUE) +# define CFG_ICACHE_SACR_VALUE \ + (PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + ( 0 << 20)) | \ + PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + (128 << 20)) | \ + PPC_128MB_SACR_VALUE(CFG_FLASH_BASE)) +#endif /* !defined(CFG_ICACHE_SACR_VALUE) */ + +#if !defined(CFG_DCACHE_SACR_VALUE) +# define CFG_DCACHE_SACR_VALUE \ + (0x00000000) +#endif /* !defined(CFG_DCACHE_SACR_VALUE) */ + #define function_prolog(func_name) .text; \ .align 2; \ .globl func_name; \ @@ -840,16 +925,16 @@ _start: /* make sure above stores all comlete before going on */ sync - /*----------------------------------------------------------------------- */ - /* Enable two 128MB cachable regions. */ - /*----------------------------------------------------------------------- */ - addis r1,r0,0xc000 - addi r1,r1,0x0001 - mticcr r1 /* instruction cache */ + /* Set-up icache cacheability. */ + lis r1, CFG_ICACHE_SACR_VALUE@h + ori r1, r1, CFG_ICACHE_SACR_VALUE@l + mticcr r1 + isync - addis r1,r0,0x0000 - addi r1,r1,0x0000 - mtdccr r1 /* data cache */ + /* Set-up dcache cacheability. */ + lis r1, CFG_DCACHE_SACR_VALUE@h + ori r1, r1, CFG_DCACHE_SACR_VALUE@l + mtdccr r1 addis r1,r0,CFG_INIT_RAM_ADDR@h ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */ @@ -892,27 +977,20 @@ _start: /* dbsr is cleared by setting bits to 1) */ mtdbsr r4 /* clear/reset the dbsr */ - /*----------------------------------------------------------------------- */ - /* Invalidate I and D caches. Enable I cache for defined memory regions */ - /* to speed things up. Leave the D cache disabled for now. It will be */ - /* enabled/left disabled later based on user selected menu options. */ - /* Be aware that the I cache may be disabled later based on the menu */ - /* options as well. See miscLib/main.c. */ - /*----------------------------------------------------------------------- */ + /* Invalidate the i- and d-caches. */ bl invalidate_icache bl invalidate_dcache - /*----------------------------------------------------------------------- */ - /* Enable two 128MB cachable regions. */ - /*----------------------------------------------------------------------- */ - lis r4,0xc000 - ori r4,r4,0x0001 - mticcr r4 /* instruction cache */ + /* Set-up icache cacheability. */ + lis r4, CFG_ICACHE_SACR_VALUE@h + ori r4, r4, CFG_ICACHE_SACR_VALUE@l + mticcr r4 isync - lis r4,0x0000 - ori r4,r4,0x0000 - mtdccr r4 /* data cache */ + /* Set-up dcache cacheability. */ + lis r4, CFG_DCACHE_SACR_VALUE@h + ori r4, r4, CFG_DCACHE_SACR_VALUE@l + mtdccr r4 #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) || defined(CONFIG_405EX) /*----------------------------------------------------------------------- */ @@ -922,9 +1000,9 @@ _start: #endif #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM)) /* - * Boards like the Kilauea (405EX) don't have OCM and can't use - * DCache for init-ram. So setup stack here directly after the - * SDRAM is initialized. + * For boards that don't have OCM and can't use the data cache + * for their primordial stack, setup stack here directly after the + * SDRAM is initialized in ext_bus_cntlr_init. */ lis r1, CFG_INIT_RAM_ADDR@h ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */ @@ -1043,47 +1121,86 @@ start_ram: /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ /*----------------------------------------------------------------------- */ #ifdef CFG_INIT_DCACHE_CS - /*----------------------------------------------------------------------- */ - /* Memory Bank x (nothingness) initialization 1GB+64MEG */ - /* used as temporary stack pointer for stage0 */ - /*----------------------------------------------------------------------- */ - li r4,PBxAP - mtdcr ebccfga,r4 - lis r4,0x0380 - ori r4,r4,0x0480 - mtdcr ebccfgd,r4 - - addi r4,0,PBxCR - mtdcr ebccfga,r4 - lis r4,0x400D - ori r4,r4,0xa000 - mtdcr ebccfgd,r4 - - /* turn on data cache for this region */ - lis r4,0x0080 + li r4, PBxAP + mtdcr ebccfga, r4 + lis r4, CFG_INIT_DCACHE_PBxAR@h + ori r4, r4, CFG_INIT_DCACHE_PBxAR@l + mtdcr ebccfgd, r4 + + addi r4, 0, PBxCR + mtdcr ebccfga, r4 + lis r4, CFG_INIT_DCACHE_PBxCR@h + ori r4, r4, CFG_INIT_DCACHE_PBxCR@l + mtdcr ebccfgd, r4 + + /* + * Enable the data cache for the 128MB storage access control region + * at CFG_INIT_RAM_ADDR. + */ + mfdccr r4 + oris r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h + ori r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l mtdccr r4 - /* set stack pointer and clear stack to known value */ + /* + * Preallocate data cache lines to be used to avoid a subsequent + * cache miss and an ensuing machine check exception when exceptions + * are enabled. + */ + li r0, 0 - lis r1,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET@l + lis r3, CFG_INIT_RAM_ADDR@h + ori r3, r3, CFG_INIT_RAM_ADDR@l - li r4,2048 /* we store 2048 words to stack */ + lis r4, CFG_INIT_RAM_END@h + ori r4, r4, CFG_INIT_RAM_END@l + + /* + * Convert the size, in bytes, to the number of cache lines/blocks + * to preallocate. + */ + clrlwi. r5, r4, (32 - L1_CACHE_SHIFT) + srwi r5, r4, L1_CACHE_SHIFT + beq ..load_counter + addi r5, r5, 0x0001 +..load_counter: + mtctr r5 + + /* Preallocate the computed number of cache blocks. */ +..alloc_dcache_block: + dcba r0, r3 + addi r3, r3, L1_CACHE_BYTES + bdnz ..alloc_dcache_block + sync + + /* + * Load the initial stack pointer and data area and convert the size, + * in bytes, to the number of words to initialize to a known value. + */ + lis r1, CFG_INIT_RAM_ADDR@h + ori r1, r1, CFG_INIT_SP_OFFSET@l + + lis r4, (CFG_INIT_RAM_END >> 2)@h + ori r4, r4, (CFG_INIT_RAM_END >> 2)@l mtctr r4 - lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */ - ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */ + lis r2, CFG_INIT_RAM_ADDR@h + ori r2, r2, CFG_INIT_RAM_END@l - lis r4,0xdead /* we store 0xdeaddead in the stack */ - ori r4,r4,0xdead + lis r4, CFG_INIT_RAM_PATTERN@h + ori r4, r4, CFG_INIT_RAM_PATTERN@l ..stackloop: - stwu r4,-4(r2) + stwu r4, -4(r2) bdnz ..stackloop - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + /* + * Make room for stack frame header and clear final stack frame so + * that stack backtraces terminate cleanly. + */ + stwu r0, -4(r1) + stwu r0, -4(r1) + /* * Set up a dummy frame to store reset vector as return address. * this causes stack underflow to reset board. @@ -1328,33 +1445,72 @@ in32r: * This "function" does not return, instead it continues in RAM * after relocating the monitor code. * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize + * r3 = Relocated stack pointer + * r4 = Relocated global data pointer + * r5 = Relocated text pointer */ .globl relocate_code relocate_code: -#ifdef CONFIG_4xx_DCACHE +#if defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS) /* - * We need to flush the Init Data before the dcache will be - * invalidated + * We need to flush the initial global data (gd_t) before the dcache + * will be invalidated. */ - /* save regs */ - mr r9,r3 - mr r10,r4 - mr r11,r5 + /* Save registers */ + mr r9, r3 + mr r10, r4 + mr r11, r5 - mr r3,r4 - addi r4,r4,0x200 /* should be enough for init data */ + /* Flush initial global data range */ + mr r3, r4 + addi r4, r4, CFG_GBL_DATA_SIZE@l bl flush_dcache_range - /* restore regs */ - mr r3,r9 - mr r4,r10 - mr r5,r11 -#endif +#if defined(CFG_INIT_DCACHE_CS) + /* + * Undo the earlier data cache set-up for the primordial stack and + * data area. First, invalidate the data cache and then disable data + * cacheability for that area. Finally, restore the EBC values, if + * any. + */ + + /* Invalidate the primordial stack and data area in cache */ + lis r3, CFG_INIT_RAM_ADDR@h + ori r3, r3, CFG_INIT_RAM_ADDR@l + + lis r4, CFG_INIT_RAM_END@h + ori r4, r4, CFG_INIT_RAM_END@l + add r4, r4, r3 + + bl invalidate_dcache_range + + /* Disable cacheability for the region */ + mfdccr r3 + lis r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h + ori r4, r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l + and r3, r3, r4 + mtdccr r3 + + /* Restore the EBC parameters */ + li r3, PBxAP + mtdcr ebccfga, r3 + lis r3, PBxAP_VAL@h + ori r3, r3, PBxAP_VAL@l + mtdcr ebccfgd, r3 + + li r3, PBxCR + mtdcr ebccfga, r3 + lis r3, PBxCR_VAL@h + ori r3, r3, PBxCR_VAL@l + mtdcr ebccfgd, r3 +#endif /* defined(CFG_INIT_DCACHE_CS) */ + + /* Restore registers */ + mr r3, r9 + mr r4, r10 + mr r5, r11 +#endif /* defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS) */ #ifdef CFG_INIT_RAM_DCACHE /* @@ -1396,13 +1552,13 @@ relocate_code: addi r1,r0,CFG_TLB_FOR_BOOT_FLASH /* Use defined TLB */ #else addi r1,r0,0x0000 /* Default TLB entry is #0 */ -#endif +#endif /* CFG_TLB_FOR_BOOT_FLASH */ tlbre r0,r1,0x0002 /* Read contents */ ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ tlbwe r0,r1,0x0002 /* Save it out */ sync isync -#endif +#endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */ mr r1, r3 /* Set new stack pointer */ mr r9, r4 /* Save copy of Init Data pointer */ mr r10, r5 /* Save copy of Destination Address */ @@ -1425,7 +1581,7 @@ relocate_code: /* First our own GOT */ add r14, r14, r15 - /* the the one used by the C code */ + /* then the one used by the C code */ add r30, r30, r15 /* diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c index 38b6f895550..8b7e32a17bc 100644 --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -170,7 +170,7 @@ MachineCheckException(struct pt_regs *regs) val = get_esr(); -#if !defined(CONFIG_440) +#if !defined(CONFIG_440) && !defined(CONFIG_405EX) if (val& ESR_IMCP) { printf("Instruction"); mtspr(ESR, val & ~ESR_IMCP); @@ -179,7 +179,7 @@ MachineCheckException(struct pt_regs *regs) } printf(" machine check.\n"); -#elif defined(CONFIG_440) +#elif defined(CONFIG_440) || defined(CONFIG_405EX) if (val& ESR_IMCP){ printf("Instruction Synchronous Machine Check exception\n"); mtspr(SPRN_ESR, val & ~ESR_IMCP); @@ -187,10 +187,15 @@ MachineCheckException(struct pt_regs *regs) val = mfspr(MCSR); if (val & MCSR_IB) printf("Instruction Read PLB Error\n"); +#if defined(CONFIG_440) if (val & MCSR_DRB) printf("Data Read PLB Error\n"); if (val & MCSR_DWB) printf("Data Write PLB Error\n"); +#else + if (val & MCSR_DB) + printf("Data PLB Error\n"); +#endif if (val & MCSR_TLBP) printf("TLB Parity Error\n"); if (val & MCSR_ICP){ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 8bdfb9ddf39..cfd84402379 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -460,17 +460,19 @@ #define SPRN_PID2 0x27a /* Process ID Register 2 */ #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ #define SPRN_MCAR 0x23d /* Machine Check Address register */ -#ifdef CONFIG_440 #define MCSR_MCS 0x80000000 /* Machine Check Summary */ #define MCSR_IB 0x40000000 /* Instruction PLB Error */ +#if defined(CONFIG_440) #define MCSR_DRB 0x20000000 /* Data Read PLB Error */ #define MCSR_DWB 0x10000000 /* Data Write PLB Error */ +#else +#define MCSR_DB 0x20000000 /* Data PLB Error */ +#endif /* defined(CONFIG_440) */ #define MCSR_TLBP 0x08000000 /* TLB Parity Error */ #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ -#endif #define ESR_ST 0x00800000 /* Store Operation */ #if defined(CONFIG_MPC86xx) diff --git a/include/ppc405.h b/include/ppc405.h index d953378c73b..c9942890b46 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -22,6 +22,10 @@ #ifndef __PPC405_H__ #define __PPC405_H__ +/* Define bits and masks for real-mode storage attribute control registers */ +#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27) +#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1) + #ifndef CONFIG_IOP480 #define CFG_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */ #else @@ -362,6 +366,120 @@ #define UIC_EXT6 0x00000001 /* External interrupt 6 */ #endif /* defined(CONFIG_405EZ) */ +/****************************************************************************** + * External Bus Controller (EBC) + *****************************************************************************/ + +/* Bank Configuration Register */ +#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF) +#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(unsigned long, n)) & \ + EBC_BXCR_BAS_MASK) << 0) +#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7) +#define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0) +#define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1) +#define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2) +#define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3) +#define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4) +#define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5) +#define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6) +#define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7) +#define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3) +#define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0) +#define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1) +#define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2) +#define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3) +#define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3) +#define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0) +#define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1) +#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3) + +/* Bank Access Parameter Register */ +#define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1) +#define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0) +#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, \ + (static_cast(unsigned long, n)) \ + & 0xFF) +#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, \ + (static_cast(unsigned long, n)) \ + & 0x1F) +#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, \ + (static_cast(unsigned long, n)) \ + & 0x7) +#define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0) +#define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1) +#define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3) +#define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0) +#define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1) +#define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2) +#define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3) +#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, \ + (static_cast(unsigned long, n)) \ + & 0x3) +#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, \ + (static_cast(unsigned long, n)) \ + & 0x3) +#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, \ + (static_cast(unsigned long, n)) \ + & 0x3) +#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, \ + (static_cast(unsigned long, n)) \ + & 0x3) +#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, \ + (static_cast(unsigned long, n)) \ + & 0x7) +#define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1) +#define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0) +#define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0) +#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1) +#define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0) +#define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1) +#define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0) +#define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1) + +/* Configuration Register */ +#define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1) +#define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0) +#define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1) +#define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1) +#define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0) +#define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1) +#define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7) +#define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0) +#define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1) +#define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2) +#define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3) +#define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4) +#define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5) +#define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6) +#define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7) +#define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1) +#define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0) +#define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1) +#define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1) +#define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0) +#define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1) +#define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1) +#define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0) +#define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1) +#define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1) +#define EBC_CFG_OEO_DISABLE PPC_REG_VAL(8, 0x0) +#define EBC_CFG_OEO_ENABLE PPC_REG_VAL(8, 0x1) +#define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1) +#define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0) +#define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1) +#define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1) +#define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0) +#define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1) +#define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F) +#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, \ + (static_cast(unsigned long, n)) \ + & 0x1F) +#define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3) +#define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0) +#define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1) +#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2) +#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3) + /****************************************************************************** * SDRAM Controller ******************************************************************************/ @@ -1218,19 +1336,43 @@ /*-----------------------------------------------------------------------------+ | Memory Bank 0-7 configuration -+-----------------------------------------------------------------------------*/ -#define SDRAM_RXBAS_SDSZ_4 0x00000000 /* 4M */ -#define SDRAM_RXBAS_SDSZ_8 0x00001000 /* 8M */ -#define SDRAM_RXBAS_SDSZ_16 0x00002000 /* 16M */ -#define SDRAM_RXBAS_SDSZ_32 0x00003000 /* 32M */ -#define SDRAM_RXBAS_SDSZ_64 0x00004000 /* 64M */ -#define SDRAM_RXBAS_SDSZ_128 0x00005000 /* 128M */ -#define SDRAM_RXBAS_SDSZ_256 0x00006000 /* 256M */ -#define SDRAM_RXBAS_SDSZ_512 0x00007000 /* 512M */ -#define SDRAM_RXBAS_SDSZ_1024 0x00008000 /* 1024M */ -#define SDRAM_RXBAS_SDSZ_2048 0x00009000 /* 2048M */ -#define SDRAM_RXBAS_SDSZ_4096 0x0000a000 /* 4096M */ -#define SDRAM_RXBAS_SDSZ_8192 0x0000b000 /* 8192M */ ++----------------------------------------------------------------------------*/ +#define SDRAM_RXBAS_SDSZ_MASK PPC_REG_VAL(19, 0xF) +#define SDRAM_RXBAS_SDSZ_4MB PPC_REG_VAL(19, 0x0) +#define SDRAM_RXBAS_SDSZ_8MB PPC_REG_VAL(19, 0x1) +#define SDRAM_RXBAS_SDSZ_16MB PPC_REG_VAL(19, 0x2) +#define SDRAM_RXBAS_SDSZ_32MB PPC_REG_VAL(19, 0x3) +#define SDRAM_RXBAS_SDSZ_64MB PPC_REG_VAL(19, 0x4) +#define SDRAM_RXBAS_SDSZ_128MB PPC_REG_VAL(19, 0x5) +#define SDRAM_RXBAS_SDSZ_256MB PPC_REG_VAL(19, 0x6) +#define SDRAM_RXBAS_SDSZ_512MB PPC_REG_VAL(19, 0x7) +#define SDRAM_RXBAS_SDSZ_1024MB PPC_REG_VAL(19, 0x8) +#define SDRAM_RXBAS_SDSZ_2048MB PPC_REG_VAL(19, 0x9) +#define SDRAM_RXBAS_SDSZ_4096MB PPC_REG_VAL(19, 0xA) +#define SDRAM_RXBAS_SDSZ_8192MB PPC_REG_VAL(19, 0xB) +#define SDRAM_RXBAS_SDSZ_8 SDRAM_RXBAS_SDSZ_8MB +#define SDRAM_RXBAS_SDSZ_16 SDRAM_RXBAS_SDSZ_16MB +#define SDRAM_RXBAS_SDSZ_32 SDRAM_RXBAS_SDSZ_32MB +#define SDRAM_RXBAS_SDSZ_64 SDRAM_RXBAS_SDSZ_64MB +#define SDRAM_RXBAS_SDSZ_128 SDRAM_RXBAS_SDSZ_128MB +#define SDRAM_RXBAS_SDSZ_256 SDRAM_RXBAS_SDSZ_256MB +#define SDRAM_RXBAS_SDSZ_512 SDRAM_RXBAS_SDSZ_512MB +#define SDRAM_RXBAS_SDSZ_1024 SDRAM_RXBAS_SDSZ_1024MB +#define SDRAM_RXBAS_SDSZ_2048 SDRAM_RXBAS_SDSZ_2048MB +#define SDRAM_RXBAS_SDSZ_4096 SDRAM_RXBAS_SDSZ_4096MB +#define SDRAM_RXBAS_SDSZ_8192 SDRAM_RXBAS_SDSZ_8192MB +#define SDRAM_RXBAS_SDAM_MODE0 PPC_REG_VAL(23, 0x0) +#define SDRAM_RXBAS_SDAM_MODE1 PPC_REG_VAL(23, 0x1) +#define SDRAM_RXBAS_SDAM_MODE2 PPC_REG_VAL(23, 0x2) +#define SDRAM_RXBAS_SDAM_MODE3 PPC_REG_VAL(23, 0x3) +#define SDRAM_RXBAS_SDAM_MODE4 PPC_REG_VAL(23, 0x4) +#define SDRAM_RXBAS_SDAM_MODE5 PPC_REG_VAL(23, 0x5) +#define SDRAM_RXBAS_SDAM_MODE6 PPC_REG_VAL(23, 0x6) +#define SDRAM_RXBAS_SDAM_MODE7 PPC_REG_VAL(23, 0x7) +#define SDRAM_RXBAS_SDAM_MODE8 PPC_REG_VAL(23, 0x8) +#define SDRAM_RXBAS_SDAM_MODE9 PPC_REG_VAL(23, 0x9) +#define SDRAM_RXBAS_SDBE_DISABLE PPC_REG_VAL(31, 0x0) +#define SDRAM_RXBAS_SDBE_ENABLE PPC_REG_VAL(31, 0x1) /*-----------------------------------------------------------------------------+ | Memory Controller Status @@ -1612,4 +1754,27 @@ #define SDR0_PFC1_GPT_FREQ 0x0000000f #endif +/* General Purpose Timer (GPT) Register Offsets */ +#define GPT0_TBC 0x00000000 +#define GPT0_IM 0x00000018 +#define GPT0_ISS 0x0000001C +#define GPT0_ISC 0x00000020 +#define GPT0_IE 0x00000024 +#define GPT0_COMP0 0x00000080 +#define GPT0_COMP1 0x00000084 +#define GPT0_COMP2 0x00000088 +#define GPT0_COMP3 0x0000008C +#define GPT0_COMP4 0x00000090 +#define GPT0_COMP5 0x00000094 +#define GPT0_COMP6 0x00000098 +#define GPT0_MASK0 0x000000C0 +#define GPT0_MASK1 0x000000C4 +#define GPT0_MASK2 0x000000C8 +#define GPT0_MASK3 0x000000CC +#define GPT0_MASK4 0x000000D0 +#define GPT0_MASK5 0x000000D4 +#define GPT0_MASK6 0x000000D8 +#define GPT0_DCT0 0x00000110 +#define GPT0_DCIS 0x0000011C + #endif /* __PPC405_H__ */ diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 76fe8727f56..4a6eb86f419 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -28,6 +28,21 @@ #include #endif +/* + * Macro for generating register field mnemonics + */ +#define PPC_REG_BITS 32 +#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) + +/* + * Elide casts when assembling register mnemonics + */ +#ifndef __ASSEMBLY__ +#define static_cast(type, val) (type)(val) +#else +#define static_cast(type, val) (val) +#endif + /* * Common stuff for 4xx (405 and 440) */ -- cgit v1.3.1 From 64852d09e06dd6db2b2db2a3c59bc2db176a54d6 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 2 Jun 2008 14:35:44 +0200 Subject: ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.S This patch consolidates the 405 and 440 parts of the NAND booting code selected via CONFIG_NAND_SPL. Now common code is used to initialize the SDRAM by calling initdram() and to "copy/relocate" to SDRAM/OCM/etc. Only *after* running from this location, nand_boot() is called. Please note that the initsdram() call is now moved from nand_boot.c to start.S. I experienced problems with some boards like Kilauea (405EX), which don't have internal SRAM (OCM) and relocation needs to be done to SDRAM before the NAND controller can get accessed. When initdram() is called later on in nand_boot(), this can lead to problems with variables in the bss sections like nand_ecc_pos[]. Signed-off-by: Stefan Roese Acked-by: Scott Wood --- cpu/ppc4xx/start.S | 206 ++++++++++++++++++++------------------------------- nand_spl/nand_boot.c | 11 ++- 2 files changed, 85 insertions(+), 132 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index a5d9ec96e0d..25ee36932f9 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -187,6 +187,10 @@ * at CFG_SDRAM_BASE and another 128MB cacheable instruction region covering * NOR flash at CFG_FLASH_BASE. Disable all cacheable data regions. */ +#if !defined(CFG_FLASH_BASE) +/* If not already defined, set it to the "last" 128MByte region */ +# define CFG_FLASH_BASE 0xf8000000 +#endif #if !defined(CFG_ICACHE_SACR_VALUE) # define CFG_ICACHE_SACR_VALUE \ (PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + ( 0 << 20)) | \ @@ -486,97 +490,6 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ /* Continue from 'normal' start */ /*----------------------------------------------------------------*/ 2: - -#if defined(CONFIG_NAND_SPL) -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) - /* - * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM) - */ - lis r2,0x7fff - ori r2,r2,0xffff - mfdcr r1,isram0_dpc - and r1,r1,r2 /* Disable parity check */ - mtdcr isram0_dpc,r1 - mfdcr r1,isram0_pmeg - and r1,r1,r2 /* Disable pwr mgmt */ - mtdcr isram0_pmeg,r1 -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) - lis r1,0x4000 /* BAS = 8000_0000 */ - ori r1,r1,0x4580 /* 16k */ - mtdcr isram0_sb0cr,r1 -#endif -#endif -#if defined(CONFIG_440EP) - /* - * On 440EP with no internal SRAM, we setup SDRAM very early - * and copy the NAND_SPL to SDRAM and jump to it - */ - /* Clear Dcache to use as RAM */ - addis r3,r0,CFG_INIT_RAM_ADDR@h - ori r3,r3,CFG_INIT_RAM_ADDR@l - addis r4,r0,CFG_INIT_RAM_END@h - ori r4,r4,CFG_INIT_RAM_END@l - rlwinm. r5,r4,0,27,31 - rlwinm r5,r4,27,5,31 - beq ..d_ran3 - addi r5,r5,0x0001 -..d_ran3: - mtctr r5 -..d_ag3: - dcbz r0,r3 - addi r3,r3,32 - bdnz ..d_ag3 - /*----------------------------------------------------------------*/ - /* Setup the stack in internal SRAM */ - /*----------------------------------------------------------------*/ - lis r1,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET@l - li r0,0 - stwu r0,-4(r1) - stwu r0,-4(r1) /* Terminate call chain */ - - stwu r1,-8(r1) /* Save back chain and move SP */ - lis r0,RESET_VECTOR@h /* Address of reset vector */ - ori r0,r0, RESET_VECTOR@l - stwu r1,-8(r1) /* Save back chain and move SP */ - stw r0,+12(r1) /* Save return addr (underflow vect) */ - sync - bl early_sdram_init - sync -#endif /* CONFIG_440EP */ - - /* - * Copy SPL from cache into internal SRAM - */ - li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1 - mtctr r4 - lis r2,CFG_NAND_BOOT_SPL_SRC@h - ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l - lis r3,CFG_NAND_BOOT_SPL_DST@h - ori r3,r3,CFG_NAND_BOOT_SPL_DST@l -spl_loop: - lwzu r4,4(r2) - stwu r4,4(r3) - bdnz spl_loop - - /* - * Jump to code in RAM - */ - bl 00f -00: mflr r10 - lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h - ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l - sub r10,r10,r3 - addi r10,r10,28 - mtlr r10 - blr - -start_ram: - sync - isync -#endif /* CONFIG_NAND_SPL */ - bl 3f b _start @@ -831,7 +744,7 @@ _start: stw r0,+12(r1) /* Save return addr (underflow vect) */ #ifdef CONFIG_NAND_SPL - bl nand_boot /* will not return */ + bl nand_boot_common /* will not return */ #else GET_GOT @@ -992,12 +905,13 @@ _start: ori r4, r4, CFG_DCACHE_SACR_VALUE@l mtdccr r4 -#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) || defined(CONFIG_405EX) +#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) /*----------------------------------------------------------------------- */ /* Tune the speed and size for flash CS0 */ /*----------------------------------------------------------------------- */ bl ext_bus_cntlr_init #endif + #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM)) /* * For boards that don't have OCM and can't use the data cache @@ -1085,38 +999,6 @@ _start: #endif /* CONFIG_405EZ */ #endif -#ifdef CONFIG_NAND_SPL - /* - * Copy SPL from cache into internal SRAM - */ - li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1 - mtctr r4 - lis r2,CFG_NAND_BOOT_SPL_SRC@h - ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l - lis r3,CFG_NAND_BOOT_SPL_DST@h - ori r3,r3,CFG_NAND_BOOT_SPL_DST@l -spl_loop: - lwzu r4,4(r2) - stwu r4,4(r3) - bdnz spl_loop - - /* - * Jump to code in RAM - */ - bl 00f -00: mflr r10 - lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h - ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l - sub r10,r10,r3 - addi r10,r10,28 - mtlr r10 - blr - -start_ram: - sync - isync -#endif /* CONFIG_NAND_SPL */ - /*----------------------------------------------------------------------- */ /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ /*----------------------------------------------------------------------- */ @@ -1243,7 +1125,7 @@ start_ram: bl sdram_init #ifdef CONFIG_NAND_SPL - bl nand_boot /* will not return */ + bl nand_boot_common /* will not return */ #else GET_GOT /* initialize GOT access */ @@ -2180,3 +2062,75 @@ pll_wait: blr function_epilog(mftlb1) #endif /* CONFIG_440 */ + +#if defined(CONFIG_NAND_SPL) +/* + * void nand_boot_relocate(dst, src, bytes) + * + * r3 = Destination address to copy code to (in SDRAM) + * r4 = Source address to copy code from + * r5 = size to copy in bytes + */ +nand_boot_relocate: + mr r6,r3 + mr r7,r4 + mflr r8 + + /* + * Copy SPL from icache into SDRAM + */ + subi r3,r3,4 + subi r4,r4,4 + srwi r5,r5,2 + mtctr r5 +..spl_loop: + lwzu r0,4(r4) + stwu r0,4(r3) + bdnz ..spl_loop + + /* + * Calculate "corrected" link register, so that we "continue" + * in execution in destination range + */ + sub r3,r7,r6 /* r3 = src - dst */ + sub r8,r8,r3 /* r8 = link-reg - (src - dst) */ + mtlr r8 + blr + +nand_boot_common: + /* + * First initialize SDRAM. It has to be available *before* calling + * nand_boot(). + */ + lis r3,CFG_SDRAM_BASE@h + ori r3,r3,CFG_SDRAM_BASE@l + bl initdram + + /* + * Now copy the 4k SPL code into SDRAM and continue execution + * from there. + */ + lis r3,CFG_NAND_BOOT_SPL_DST@h + ori r3,r3,CFG_NAND_BOOT_SPL_DST@l + lis r4,CFG_NAND_BOOT_SPL_SRC@h + ori r4,r4,CFG_NAND_BOOT_SPL_SRC@l + lis r5,CFG_NAND_BOOT_SPL_SIZE@h + ori r5,r5,CFG_NAND_BOOT_SPL_SIZE@l + bl nand_boot_relocate + + /* + * We're running from SDRAM now!!! + * + * It is necessary for 4xx systems to relocate from running at + * the original location (0xfffffxxx) to somewhere else (SDRAM + * preferably). This is because CS0 needs to be reconfigured for + * NAND access. And we can't reconfigure this CS when currently + * "running" from it. + */ + + /* + * Finally call nand_boot() to load main NAND U-Boot image from + * NAND and jump to it. + */ + bl nand_boot /* will not return */ +#endif /* CONFIG_NAND_SPL */ diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c index bc577252cf7..563a80b9537 100644 --- a/nand_spl/nand_boot.c +++ b/nand_spl/nand_boot.c @@ -221,19 +221,18 @@ static int nand_load(struct mtd_info *mtd, int offs, int uboot_size, uchar *dst) return 0; } +/* + * The main entry for NAND booting. It's necessary that SDRAM is already + * configured and available since this code loads the main U-Boot image + * from NAND into SDRAM and starts it from there. + */ void nand_boot(void) { - ulong mem_size; struct nand_chip nand_chip; nand_info_t nand_info; int ret; void (*uboot)(void); - /* - * Init sdram, so we have access to memory - */ - mem_size = initdram(0); - /* * Init board specific nand support */ -- cgit v1.3.1 From 36ea16f6a066ccb046e91ebce4f326b69f4c0569 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 2 Jun 2008 14:57:41 +0200 Subject: ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part1 This patch removes all SDRAM related defines from the PPC4xx headers ppc405.h and ppc440.h. This is needed since now some 405 PPC's use the same SDRAM controller as 440 systems do (like 405EX and 440SP). It also introduces new defines for the equipped SDRAM controller based on which PPC variant is used. There new defines are: used on 405GR/CR/EP and some Xilinx Virtex boards. used on 440GP/GX/EP/GR. used on 440EPx/GRx. used on 405EX/r/440SP/SPe/460EX/GT. Signed-off-by: Stefan Roese --- cpu/ppc4xx/44x_spd_ddr.c | 151 -------- include/ppc405.h | 414 ---------------------- include/ppc440.h | 896 ----------------------------------------------- include/ppc4xx.h | 25 ++ 4 files changed, 25 insertions(+), 1461 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index b7eeaf2fe26..9efcedefed0 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -81,157 +81,6 @@ void __spd_ddr_init_hang (void) } void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang"))); -/*----------------------------------------------------------------------------- - | Memory Controller Options 0 - +-----------------------------------------------------------------------------*/ -#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */ -#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */ -#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */ -#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */ -#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */ -#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */ -#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */ -#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */ -#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */ -#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */ -#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */ -#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */ - -/*----------------------------------------------------------------------------- - | Memory Controller Options 1 - +-----------------------------------------------------------------------------*/ -#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */ -#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */ - -/*-----------------------------------------------------------------------------+ - | SDRAM DEVPOT Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_DEVOPT_DLL 0x80000000 -#define SDRAM_DEVOPT_DS 0x40000000 - -/*-----------------------------------------------------------------------------+ - | SDRAM MCSTS Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_MCSTS_MRSC 0x80000000 -#define SDRAM_MCSTS_SRMS 0x40000000 -#define SDRAM_MCSTS_CIS 0x20000000 - -/*----------------------------------------------------------------------------- - | SDRAM Refresh Timer Register - +-----------------------------------------------------------------------------*/ -#define SDRAM_RTR_RINT_MASK 0xFFFF0000 -#define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK) -#define sdram_HZ_to_ns(hertz) (1000000000/(hertz)) - -/*-----------------------------------------------------------------------------+ - | SDRAM UABus Base Address Reg - +-----------------------------------------------------------------------------*/ -#define SDRAM_UABBA_UBBA_MASK 0x0000000F - -/*-----------------------------------------------------------------------------+ - | Memory Bank 0-7 configuration - +-----------------------------------------------------------------------------*/ -#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */ -#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */ -#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */ -#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */ -#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */ -#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */ -#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */ -#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */ -#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */ -#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */ -#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */ -#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */ -#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */ -#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */ -#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */ - -/*-----------------------------------------------------------------------------+ - | SDRAM TR0 Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_TR0_SDWR_MASK 0x80000000 -#define SDRAM_TR0_SDWR_2_CLK 0x00000000 -#define SDRAM_TR0_SDWR_3_CLK 0x80000000 -#define SDRAM_TR0_SDWD_MASK 0x40000000 -#define SDRAM_TR0_SDWD_0_CLK 0x00000000 -#define SDRAM_TR0_SDWD_1_CLK 0x40000000 -#define SDRAM_TR0_SDCL_MASK 0x01800000 -#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000 -#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000 -#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000 -#define SDRAM_TR0_SDPA_MASK 0x000C0000 -#define SDRAM_TR0_SDPA_2_CLK 0x00040000 -#define SDRAM_TR0_SDPA_3_CLK 0x00080000 -#define SDRAM_TR0_SDPA_4_CLK 0x000C0000 -#define SDRAM_TR0_SDCP_MASK 0x00030000 -#define SDRAM_TR0_SDCP_2_CLK 0x00000000 -#define SDRAM_TR0_SDCP_3_CLK 0x00010000 -#define SDRAM_TR0_SDCP_4_CLK 0x00020000 -#define SDRAM_TR0_SDCP_5_CLK 0x00030000 -#define SDRAM_TR0_SDLD_MASK 0x0000C000 -#define SDRAM_TR0_SDLD_1_CLK 0x00000000 -#define SDRAM_TR0_SDLD_2_CLK 0x00004000 -#define SDRAM_TR0_SDRA_MASK 0x0000001C -#define SDRAM_TR0_SDRA_6_CLK 0x00000000 -#define SDRAM_TR0_SDRA_7_CLK 0x00000004 -#define SDRAM_TR0_SDRA_8_CLK 0x00000008 -#define SDRAM_TR0_SDRA_9_CLK 0x0000000C -#define SDRAM_TR0_SDRA_10_CLK 0x00000010 -#define SDRAM_TR0_SDRA_11_CLK 0x00000014 -#define SDRAM_TR0_SDRA_12_CLK 0x00000018 -#define SDRAM_TR0_SDRA_13_CLK 0x0000001C -#define SDRAM_TR0_SDRD_MASK 0x00000003 -#define SDRAM_TR0_SDRD_2_CLK 0x00000001 -#define SDRAM_TR0_SDRD_3_CLK 0x00000002 -#define SDRAM_TR0_SDRD_4_CLK 0x00000003 - -/*-----------------------------------------------------------------------------+ - | SDRAM TR1 Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_TR1_RDSS_MASK 0xC0000000 -#define SDRAM_TR1_RDSS_TR0 0x00000000 -#define SDRAM_TR1_RDSS_TR1 0x40000000 -#define SDRAM_TR1_RDSS_TR2 0x80000000 -#define SDRAM_TR1_RDSS_TR3 0xC0000000 -#define SDRAM_TR1_RDSL_MASK 0x00C00000 -#define SDRAM_TR1_RDSL_STAGE1 0x00000000 -#define SDRAM_TR1_RDSL_STAGE2 0x00400000 -#define SDRAM_TR1_RDSL_STAGE3 0x00800000 -#define SDRAM_TR1_RDCD_MASK 0x00000800 -#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000 -#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800 -#define SDRAM_TR1_RDCT_MASK 0x000001FF -#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK) -#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0) -#define SDRAM_TR1_RDCT_MIN 0x00000000 -#define SDRAM_TR1_RDCT_MAX 0x000001FF - -/*-----------------------------------------------------------------------------+ - | SDRAM WDDCTR Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000 -#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000 -#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000 -#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000 -#define SDRAM_WDDCTR_DCD_MASK 0x000001FF - -/*-----------------------------------------------------------------------------+ - | SDRAM CLKTR Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 -#define SDRAM_CLKTR_CLKP_0DEG 0x00000000 -#define SDRAM_CLKTR_CLKP_90DEG 0x40000000 -#define SDRAM_CLKTR_CLKP_180DEG 0x80000000 -#define SDRAM_CLKTR_DCDT_MASK 0x000001FF - -/*-----------------------------------------------------------------------------+ - | SDRAM DLYCAL Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC -#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) -#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) - /*-----------------------------------------------------------------------------+ | General Definition +-----------------------------------------------------------------------------*/ diff --git a/include/ppc405.h b/include/ppc405.h index c9942890b46..2231a5fbb45 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -480,33 +480,6 @@ #define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2) #define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3) -/****************************************************************************** - * SDRAM Controller - ******************************************************************************/ - /* values for memcfga register - indirect addressing of these regs */ -#ifndef CONFIG_405EP - #define mem_besra 0x00 /* bus error syndrome reg a */ - #define mem_besrsa 0x04 /* bus error syndrome reg set a */ - #define mem_besrb 0x08 /* bus error syndrome reg b */ - #define mem_besrsb 0x0c /* bus error syndrome reg set b */ - #define mem_bear 0x10 /* bus error address reg */ -#endif - #define mem_mcopt1 0x20 /* memory controller options 1 */ - #define mem_status 0x24 /* memory status */ - #define mem_rtr 0x30 /* refresh timer reg */ - #define mem_pmit 0x34 /* power management idle timer */ - #define mem_mb0cf 0x40 /* memory bank 0 configuration */ - #define mem_mb1cf 0x44 /* memory bank 1 configuration */ -#ifndef CONFIG_405EP - #define mem_mb2cf 0x48 /* memory bank 2 configuration */ - #define mem_mb3cf 0x4c /* memory bank 3 configuration */ -#endif - #define mem_sdtr1 0x80 /* timing reg 1 */ -#ifndef CONFIG_405EP - #define mem_ecccf 0x94 /* ECC configuration */ - #define mem_eccerr 0x98 /* ECC error status */ -#endif - #ifndef CONFIG_405EP /****************************************************************************** * Decompression Controller @@ -1281,393 +1254,6 @@ #if defined(CONFIG_405EX) #define SDR0_SRST 0x0200 -#define SDRAM_BESR0 0x00 -#define SDRAM_BEARL 0x02 -#define SDRAM_BEARU 0x03 -#define SDRAM_WMIRQ 0x06 /**/ -#define SDRAM_PLBOPT 0x08 /**/ -#define SDRAM_PUABA 0x09 /**/ -#define SDRAM_MCSTAT 0x1F /* memory controller status */ -#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ -#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ -#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ -#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */ -#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */ -#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */ -#define SDRAM_CODT 0x26 /* on die termination for controller */ -#define SDRAM_VVPR 0x27 /* variable VRef programmming */ -#define SDRAM_OPARS 0x28 /* on chip driver control setup */ -#define SDRAM_OPART 0x29 /* on chip driver control trigger */ -#define SDRAM_RTR 0x30 /* refresh timer */ -#define SDRAM_PMIT 0x34 /* power management idle timer */ -#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */ -#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */ -#define SDRAM_MB2CF 0x48 /* memory bank 2 configuration */ -#define SDRAM_MB3CF 0x4C /* memory bank 3 configuration */ -#define SDRAM_INITPLR0 0x50 /* manual initialization control */ -#define SDRAM_INITPLR1 0x51 /* manual initialization control */ -#define SDRAM_INITPLR2 0x52 /* manual initialization control */ -#define SDRAM_INITPLR3 0x53 /* manual initialization control */ -#define SDRAM_INITPLR4 0x54 /* manual initialization control */ -#define SDRAM_INITPLR5 0x55 /* manual initialization control */ -#define SDRAM_INITPLR6 0x56 /* manual initialization control */ -#define SDRAM_INITPLR7 0x57 /* manual initialization control */ -#define SDRAM_INITPLR8 0x58 /* manual initialization control */ -#define SDRAM_INITPLR9 0x59 /* manual initialization control */ -#define SDRAM_INITPLR10 0x5a /* manual initialization control */ -#define SDRAM_INITPLR11 0x5b /* manual initialization control */ -#define SDRAM_INITPLR12 0x5c /* manual initialization control */ -#define SDRAM_INITPLR13 0x5d /* manual initialization control */ -#define SDRAM_INITPLR14 0x5e /* manual initialization control */ -#define SDRAM_INITPLR15 0x5f /* manual initialization control */ -#define SDRAM_RQDC 0x70 /* read DQS delay control */ -#define SDRAM_RFDC 0x74 /* read feedback delay control */ -#define SDRAM_RDCC 0x78 /* read data capture control */ -#define SDRAM_DLCR 0x7A /* delay line calibration */ -#define SDRAM_CLKTR 0x80 /* DDR clock timing */ -#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */ -#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */ -#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */ -#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */ -#define SDRAM_MMODE 0x88 /* memory mode */ -#define SDRAM_MEMODE 0x89 /* memory extended mode */ -#define SDRAM_ECCCR 0x98 /* ECC error status */ -#define SDRAM_RID 0xF8 /* revision ID */ - -/*-----------------------------------------------------------------------------+ -| Memory Bank 0-7 configuration -+----------------------------------------------------------------------------*/ -#define SDRAM_RXBAS_SDSZ_MASK PPC_REG_VAL(19, 0xF) -#define SDRAM_RXBAS_SDSZ_4MB PPC_REG_VAL(19, 0x0) -#define SDRAM_RXBAS_SDSZ_8MB PPC_REG_VAL(19, 0x1) -#define SDRAM_RXBAS_SDSZ_16MB PPC_REG_VAL(19, 0x2) -#define SDRAM_RXBAS_SDSZ_32MB PPC_REG_VAL(19, 0x3) -#define SDRAM_RXBAS_SDSZ_64MB PPC_REG_VAL(19, 0x4) -#define SDRAM_RXBAS_SDSZ_128MB PPC_REG_VAL(19, 0x5) -#define SDRAM_RXBAS_SDSZ_256MB PPC_REG_VAL(19, 0x6) -#define SDRAM_RXBAS_SDSZ_512MB PPC_REG_VAL(19, 0x7) -#define SDRAM_RXBAS_SDSZ_1024MB PPC_REG_VAL(19, 0x8) -#define SDRAM_RXBAS_SDSZ_2048MB PPC_REG_VAL(19, 0x9) -#define SDRAM_RXBAS_SDSZ_4096MB PPC_REG_VAL(19, 0xA) -#define SDRAM_RXBAS_SDSZ_8192MB PPC_REG_VAL(19, 0xB) -#define SDRAM_RXBAS_SDSZ_8 SDRAM_RXBAS_SDSZ_8MB -#define SDRAM_RXBAS_SDSZ_16 SDRAM_RXBAS_SDSZ_16MB -#define SDRAM_RXBAS_SDSZ_32 SDRAM_RXBAS_SDSZ_32MB -#define SDRAM_RXBAS_SDSZ_64 SDRAM_RXBAS_SDSZ_64MB -#define SDRAM_RXBAS_SDSZ_128 SDRAM_RXBAS_SDSZ_128MB -#define SDRAM_RXBAS_SDSZ_256 SDRAM_RXBAS_SDSZ_256MB -#define SDRAM_RXBAS_SDSZ_512 SDRAM_RXBAS_SDSZ_512MB -#define SDRAM_RXBAS_SDSZ_1024 SDRAM_RXBAS_SDSZ_1024MB -#define SDRAM_RXBAS_SDSZ_2048 SDRAM_RXBAS_SDSZ_2048MB -#define SDRAM_RXBAS_SDSZ_4096 SDRAM_RXBAS_SDSZ_4096MB -#define SDRAM_RXBAS_SDSZ_8192 SDRAM_RXBAS_SDSZ_8192MB -#define SDRAM_RXBAS_SDAM_MODE0 PPC_REG_VAL(23, 0x0) -#define SDRAM_RXBAS_SDAM_MODE1 PPC_REG_VAL(23, 0x1) -#define SDRAM_RXBAS_SDAM_MODE2 PPC_REG_VAL(23, 0x2) -#define SDRAM_RXBAS_SDAM_MODE3 PPC_REG_VAL(23, 0x3) -#define SDRAM_RXBAS_SDAM_MODE4 PPC_REG_VAL(23, 0x4) -#define SDRAM_RXBAS_SDAM_MODE5 PPC_REG_VAL(23, 0x5) -#define SDRAM_RXBAS_SDAM_MODE6 PPC_REG_VAL(23, 0x6) -#define SDRAM_RXBAS_SDAM_MODE7 PPC_REG_VAL(23, 0x7) -#define SDRAM_RXBAS_SDAM_MODE8 PPC_REG_VAL(23, 0x8) -#define SDRAM_RXBAS_SDAM_MODE9 PPC_REG_VAL(23, 0x9) -#define SDRAM_RXBAS_SDBE_DISABLE PPC_REG_VAL(31, 0x0) -#define SDRAM_RXBAS_SDBE_ENABLE PPC_REG_VAL(31, 0x1) - -/*-----------------------------------------------------------------------------+ -| Memory Controller Status -+-----------------------------------------------------------------------------*/ -#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */ -#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */ -#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */ -#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */ -#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */ -#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */ - -/*-----------------------------------------------------------------------------+ -| Memory Controller Options 1 -+-----------------------------------------------------------------------------*/ -#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask */ -#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */ -#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */ -#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */ -#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/ -#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3) -#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */ -#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */ -#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */ -#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */ -#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */ -#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */ -#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */ -#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */ -#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */ -#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */ -#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */ -#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */ -#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */ -#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */ -#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */ -#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */ -#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */ -#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */ -#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */ -#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */ -#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */ -#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */ -#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */ -#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */ -#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */ -#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */ -#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */ -#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */ -#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */ - -/*-----------------------------------------------------------------------------+ -| Memory Controller Options 2 -+-----------------------------------------------------------------------------*/ -#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */ -#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */ -#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */ -#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */ -#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */ -#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */ -#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */ -#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */ -#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */ -#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */ -#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */ -#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */ -#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */ -#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */ -#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */ -#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/ -#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */ -#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */ - -/*-----------------------------------------------------------------------------+ -| SDRAM Refresh Timer Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_RTR_RINT_MASK 0xFFF80000 -#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16) -#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8) - -/*-----------------------------------------------------------------------------+ -| SDRAM Read DQS Delay Control Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_RQDC_RQDE_MASK 0x80000000 -#define SDRAM_RQDC_RQDE_DISABLE 0x00000000 -#define SDRAM_RQDC_RQDE_ENABLE 0x80000000 -#define SDRAM_RQDC_RQFD_MASK 0x000001FF -#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) - -#define SDRAM_RQDC_RQFD_MAX 0xFF - -/*-----------------------------------------------------------------------------+ -| SDRAM Read Data Capture Control Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_RDCC_RDSS_MASK 0xC0000000 -#define SDRAM_RDCC_RDSS_T1 0x00000000 -#define SDRAM_RDCC_RDSS_T2 0x40000000 -#define SDRAM_RDCC_RDSS_T3 0x80000000 -#define SDRAM_RDCC_RDSS_T4 0xC0000000 -#define SDRAM_RDCC_RSAE_MASK 0x00000001 -#define SDRAM_RDCC_RSAE_DISABLE 0x00000001 -#define SDRAM_RDCC_RSAE_ENABLE 0x00000000 - -/*-----------------------------------------------------------------------------+ -| SDRAM Read Feedback Delay Control Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_RFDC_ARSE_MASK 0x80000000 -#define SDRAM_RFDC_ARSE_DISABLE 0x80000000 -#define SDRAM_RFDC_ARSE_ENABLE 0x00000000 -#define SDRAM_RFDC_RFOS_MASK 0x007F0000 -#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define SDRAM_RFDC_RFFD_MASK 0x000003FF -#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) - -#define SDRAM_RFDC_RFFD_MAX 0x4FF - -/*-----------------------------------------------------------------------------+ -| SDRAM Delay Line Calibration Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_DLCR_DCLM_MASK 0x80000000 -#define SDRAM_DLCR_DCLM_MANUEL 0x80000000 -#define SDRAM_DLCR_DCLM_AUTO 0x00000000 -#define SDRAM_DLCR_DLCR_MASK 0x08000000 -#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000 -#define SDRAM_DLCR_DLCR_IDLE 0x00000000 -#define SDRAM_DLCR_DLCS_MASK 0x07000000 -#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000 -#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000 -#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000 -#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000 -#define SDRAM_DLCR_DLCS_ERROR 0x04000000 -#define SDRAM_DLCR_DLCV_MASK 0x000001FF -#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) -#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF) - -/*-----------------------------------------------------------------------------+ -| SDRAM Controller On Die Termination Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_CODT_ODT_ON 0x80000000 -#define SDRAM_CODT_ODT_OFF 0x00000000 -#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020 -#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000 -#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020 -#define SDRAM_CODT_DQS_MASK 0x00000010 -#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000 -#define SDRAM_CODT_DQS_SINGLE_END 0x00000010 -#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000 -#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 -#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 -#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 -#define SDRAM_CODT_IO_HIZ 0x00000000 -#define SDRAM_CODT_IO_NMODE 0x00000001 - -/*-----------------------------------------------------------------------------+ -| SDRAM Mode Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_MMODE_WR_MASK 0x00000E00 -#define SDRAM_MMODE_WR_DDR1 0x00000000 -#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400 -#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600 -#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800 -#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00 -#define SDRAM_MMODE_DCL_MASK 0x00000070 -#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020 -#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060 -#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030 -#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020 -#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030 -#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040 -#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050 -#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060 -#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070 - -/*-----------------------------------------------------------------------------+ -| SDRAM Extended Mode Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_MEMODE_DIC_MASK 0x00000002 -#define SDRAM_MEMODE_DIC_NORMAL 0x00000000 -#define SDRAM_MEMODE_DIC_WEAK 0x00000002 -#define SDRAM_MEMODE_DLL_MASK 0x00000001 -#define SDRAM_MEMODE_DLL_DISABLE 0x00000001 -#define SDRAM_MEMODE_DLL_ENABLE 0x00000000 -#define SDRAM_MEMODE_RTT_MASK 0x00000044 -#define SDRAM_MEMODE_RTT_DISABLED 0x00000000 -#define SDRAM_MEMODE_RTT_75OHM 0x00000004 -#define SDRAM_MEMODE_RTT_150OHM 0x00000040 -#define SDRAM_MEMODE_DQS_MASK 0x00000400 -#define SDRAM_MEMODE_DQS_DISABLE 0x00000400 -#define SDRAM_MEMODE_DQS_ENABLE 0x00000000 - -/*-----------------------------------------------------------------------------+ -| SDRAM Clock Timing Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 -#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000 -#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000 - -/*-----------------------------------------------------------------------------+ -| SDRAM Write Timing Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_WRDTR_WDTP_1_CYC 0x80000000 -#define SDRAM_WRDTR_LLWP_MASK 0x10000000 -#define SDRAM_WRDTR_LLWP_DIS 0x10000000 -#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000 -#define SDRAM_WRDTR_WTR_MASK 0x0E000000 -#define SDRAM_WRDTR_WTR_0_DEG 0x06000000 -#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000 -#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000 - -/*-----------------------------------------------------------------------------+ -| SDRAM SDTR1 Options -+-----------------------------------------------------------------------------*/ -#define SDRAM_SDTR1_LDOF_MASK 0x80000000 -#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000 -#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000 -#define SDRAM_SDTR1_RTW_MASK 0x00F00000 -#define SDRAM_SDTR1_RTW_2_CLK 0x00200000 -#define SDRAM_SDTR1_RTW_3_CLK 0x00300000 -#define SDRAM_SDTR1_WTWO_MASK 0x000F0000 -#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000 -#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000 -#define SDRAM_SDTR1_RTRO_MASK 0x0000F000 -#define SDRAM_SDTR1_RTRO_1_CLK 0x00000000 -#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000 - -/*-----------------------------------------------------------------------------+ -| SDRAM SDTR2 Options -+-----------------------------------------------------------------------------*/ -#define SDRAM_SDTR2_RCD_MASK 0xF0000000 -#define SDRAM_SDTR2_RCD_1_CLK 0x10000000 -#define SDRAM_SDTR2_RCD_2_CLK 0x20000000 -#define SDRAM_SDTR2_RCD_3_CLK 0x30000000 -#define SDRAM_SDTR2_RCD_4_CLK 0x40000000 -#define SDRAM_SDTR2_RCD_5_CLK 0x50000000 -#define SDRAM_SDTR2_WTR_MASK 0x0F000000 -#define SDRAM_SDTR2_WTR_1_CLK 0x01000000 -#define SDRAM_SDTR2_WTR_2_CLK 0x02000000 -#define SDRAM_SDTR2_WTR_3_CLK 0x03000000 -#define SDRAM_SDTR2_WTR_4_CLK 0x04000000 -#define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) -#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000 -#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000 -#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000 -#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000 -#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000 -#define SDRAM_SDTR2_WPC_MASK 0x0000F000 -#define SDRAM_SDTR2_WPC_2_CLK 0x00002000 -#define SDRAM_SDTR2_WPC_3_CLK 0x00003000 -#define SDRAM_SDTR2_WPC_4_CLK 0x00004000 -#define SDRAM_SDTR2_WPC_5_CLK 0x00005000 -#define SDRAM_SDTR2_WPC_6_CLK 0x00006000 -#define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12) -#define SDRAM_SDTR2_RPC_MASK 0x00000F00 -#define SDRAM_SDTR2_RPC_2_CLK 0x00000200 -#define SDRAM_SDTR2_RPC_3_CLK 0x00000300 -#define SDRAM_SDTR2_RPC_4_CLK 0x00000400 -#define SDRAM_SDTR2_RP_MASK 0x000000F0 -#define SDRAM_SDTR2_RP_3_CLK 0x00000030 -#define SDRAM_SDTR2_RP_4_CLK 0x00000040 -#define SDRAM_SDTR2_RP_5_CLK 0x00000050 -#define SDRAM_SDTR2_RP_6_CLK 0x00000060 -#define SDRAM_SDTR2_RP_7_CLK 0x00000070 -#define SDRAM_SDTR2_RRD_MASK 0x0000000F -#define SDRAM_SDTR2_RRD_2_CLK 0x00000002 -#define SDRAM_SDTR2_RRD_3_CLK 0x00000003 - -/*-----------------------------------------------------------------------------+ -| SDRAM SDTR3 Options -+-----------------------------------------------------------------------------*/ -#define SDRAM_SDTR3_RAS_MASK 0x1F000000 -#define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define SDRAM_SDTR3_RC_MASK 0x001F0000 -#define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) -#define SDRAM_SDTR3_XCS_MASK 0x00001F00 -#define SDRAM_SDTR3_XCS 0x00000D00 -#define SDRAM_SDTR3_RFC_MASK 0x0000003F -#define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) - -/*-----------------------------------------------------------------------------+ -| Memory Bank 0-1 configuration -+-----------------------------------------------------------------------------*/ -#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */ -#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */ -#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */ -#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */ -#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */ -#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */ -#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */ -#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */ -#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */ -#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */ -#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */ -#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */ -#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */ -#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */ - #define sdr_uart0 0x0120 /* UART0 Config */ #define sdr_uart1 0x0121 /* UART1 Config */ #define sdr_mfr 0x4300 /* SDR0_MFR reg */ diff --git a/include/ppc440.h b/include/ppc440.h index 54b45531395..62f1680441f 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -210,36 +210,6 @@ #define sdr_plbtr 0x4200 #define sdr_mfr 0x4300 /* SDR0_MFR reg */ -/*----------------------------------------------------------------------------- - | SDRAM Controller - +----------------------------------------------------------------------------*/ -/* values for memcfga register - indirect addressing of these regs */ -#define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */ -#define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */ -#define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */ -#define mem_besr1_set 0x000c /* bus error status reg 1 (set) */ -#define mem_bear 0x0010 /* bus error address reg */ -#define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */ -#define mem_mirq_set 0x0012 /* bus master interrupt (set) */ -#define mem_slio 0x0018 /* ddr sdram slave interface options */ -#define mem_cfg0 0x0020 /* ddr sdram options 0 */ -#define mem_cfg1 0x0021 /* ddr sdram options 1 */ -#define mem_devopt 0x0022 /* ddr sdram device options */ -#define mem_mcsts 0x0024 /* memory controller status */ -#define mem_rtr 0x0030 /* refresh timer register */ -#define mem_pmit 0x0034 /* power management idle timer */ -#define mem_uabba 0x0038 /* plb UABus base address */ -#define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */ -#define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */ -#define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */ -#define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */ -#define mem_tr0 0x0080 /* sdram timing register 0 */ -#define mem_tr1 0x0081 /* sdram timing register 1 */ -#define mem_clktr 0x0082 /* ddr clock timing register */ -#define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */ -#define mem_dlycal 0x0084 /* delay line calibration register */ -#define mem_eccesr 0x0098 /* ECC error status */ - #ifdef CONFIG_440GX #define sdr_amp 0x0240 #define sdr_xpllc 0x01c1 @@ -380,872 +350,6 @@ #define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */ #endif /* CONFIG_440SPE */ -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) -/*----------------------------------------------------------------------------+ -| SDRAM Controller -+----------------------------------------------------------------------------*/ -/*-----------------------------------------------------------------------------+ -| SDRAM DLYCAL Options -+-----------------------------------------------------------------------------*/ -#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC -#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) -#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) - -/*----------------------------------------------------------------------------+ -| Memory queue defines -+----------------------------------------------------------------------------*/ -/* A REVOIR versus RWC - SG*/ -#define SDRAMQ_DCR_BASE 0x040 - -#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */ -#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */ -#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */ -#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */ -#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */ -#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */ -#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */ -#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */ -#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */ -#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */ -#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */ -#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */ -#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */ -#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */ -#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */ - -/*-----------------------------------------------------------------------------+ -| Memory Bank 0-7 configuration -+-----------------------------------------------------------------------------*/ -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ -#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFFE00000)>>2) -#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFFE00000)<<2) -#endif /* CONFIG_440SPE */ -#if defined(CONFIG_440SP) -#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */ -#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFF800000)) -#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFF800000)) -#endif /* CONFIG_440SP */ -#define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */ -#define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<6) -#define SDRAM_RXBAS_SDSZ_DECODE(n) ((((unsigned long)(n))>>6)&0x3FF) -#define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */ -#define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */ -#define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */ -#define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */ -#define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */ -#define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */ -#define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */ -#define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */ -#define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */ -#define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */ -#define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */ - -/*----------------------------------------------------------------------------+ -| Memory controller defines -+----------------------------------------------------------------------------*/ -/* A REVOIR versus specs 4 bank - SG*/ -#define SDRAM_MCSTAT 0x14 /* memory controller status */ -#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ -#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ -#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ -#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */ -#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */ -#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */ -#define SDRAM_CODT 0x26 /* on die termination for controller */ -#define SDRAM_VVPR 0x27 /* variable VRef programmming */ -#define SDRAM_OPARS 0x28 /* on chip driver control setup */ -#define SDRAM_OPART 0x29 /* on chip driver control trigger */ -#define SDRAM_RTR 0x30 /* refresh timer */ -#define SDRAM_PMIT 0x34 /* power management idle timer */ -#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */ -#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */ -#define SDRAM_MB2CF 0x48 -#define SDRAM_MB3CF 0x4C -#define SDRAM_INITPLR0 0x50 /* manual initialization control */ -#define SDRAM_INITPLR1 0x51 /* manual initialization control */ -#define SDRAM_INITPLR2 0x52 /* manual initialization control */ -#define SDRAM_INITPLR3 0x53 /* manual initialization control */ -#define SDRAM_INITPLR4 0x54 /* manual initialization control */ -#define SDRAM_INITPLR5 0x55 /* manual initialization control */ -#define SDRAM_INITPLR6 0x56 /* manual initialization control */ -#define SDRAM_INITPLR7 0x57 /* manual initialization control */ -#define SDRAM_INITPLR8 0x58 /* manual initialization control */ -#define SDRAM_INITPLR9 0x59 /* manual initialization control */ -#define SDRAM_INITPLR10 0x5a /* manual initialization control */ -#define SDRAM_INITPLR11 0x5b /* manual initialization control */ -#define SDRAM_INITPLR12 0x5c /* manual initialization control */ -#define SDRAM_INITPLR13 0x5d /* manual initialization control */ -#define SDRAM_INITPLR14 0x5e /* manual initialization control */ -#define SDRAM_INITPLR15 0x5f /* manual initialization control */ -#define SDRAM_RQDC 0x70 /* read DQS delay control */ -#define SDRAM_RFDC 0x74 /* read feedback delay control */ -#define SDRAM_RDCC 0x78 /* read data capture control */ -#define SDRAM_DLCR 0x7A /* delay line calibration */ -#define SDRAM_CLKTR 0x80 /* DDR clock timing */ -#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */ -#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */ -#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */ -#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */ -#define SDRAM_MMODE 0x88 /* memory mode */ -#define SDRAM_MEMODE 0x89 /* memory extended mode */ -#define SDRAM_ECCCR 0x98 /* ECC error status */ -#define SDRAM_CID 0xA4 /* core ID */ -#define SDRAM_RID 0xA8 /* revision ID */ -#define SDRAM_RTSR 0xB1 /* run time status tracking */ - -/*-----------------------------------------------------------------------------+ -| Memory Controller Status -+-----------------------------------------------------------------------------*/ -#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */ -#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */ -#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */ -#define SDRAM_MCSTAT_SRMS_MASK 0x40000000 /* Mem self refresh stat mask */ -#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */ -#define SDRAM_MCSTAT_SRMS_SF 0x40000000 /* Mem in self refresh */ -#define SDRAM_MCSTAT_IDLE_MASK 0x20000000 /* Mem self refresh stat mask */ -#define SDRAM_MCSTAT_IDLE_NOT 0x00000000 /* Mem contr not idle */ -#define SDRAM_MCSTAT_IDLE 0x20000000 /* Mem contr idle */ - -/*-----------------------------------------------------------------------------+ -| Memory Controller Options 1 -+-----------------------------------------------------------------------------*/ -#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/ -#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */ -#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */ -#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */ -#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/ -#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3) -#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */ -#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */ -#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */ -#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */ -#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */ -#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */ -#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */ -#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */ -#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */ -#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */ -#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */ -#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */ -#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */ -#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */ -#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */ -#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */ -#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */ -#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */ -#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */ -#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */ -#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */ -#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */ -#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */ -#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */ -#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */ -#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */ -#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */ -#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */ -#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */ - -/*-----------------------------------------------------------------------------+ -| Memory Controller Options 2 -+-----------------------------------------------------------------------------*/ -#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */ -#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */ -#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */ -#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */ -#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */ -#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */ -#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */ -#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */ -#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */ -#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */ -#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */ -#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */ -#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */ -#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */ -#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */ -#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/ -#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */ -#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */ - -/*-----------------------------------------------------------------------------+ -| SDRAM Refresh Timer Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_RTR_RINT_MASK 0xFFF80000 -#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16) -#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8) - -/*-----------------------------------------------------------------------------+ -| SDRAM Read DQS Delay Control Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_RQDC_RQDE_MASK 0x80000000 -#define SDRAM_RQDC_RQDE_DISABLE 0x00000000 -#define SDRAM_RQDC_RQDE_ENABLE 0x80000000 -#define SDRAM_RQDC_RQFD_MASK 0x000001FF -#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) - -#define SDRAM_RQDC_RQFD_MAX 0x1FF - -/*-----------------------------------------------------------------------------+ -| SDRAM Read Data Capture Control Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_RDCC_RDSS_MASK 0xC0000000 -#define SDRAM_RDCC_RDSS_T1 0x00000000 -#define SDRAM_RDCC_RDSS_T2 0x40000000 -#define SDRAM_RDCC_RDSS_T3 0x80000000 -#define SDRAM_RDCC_RDSS_T4 0xC0000000 -#define SDRAM_RDCC_RSAE_MASK 0x00000001 -#define SDRAM_RDCC_RSAE_DISABLE 0x00000001 -#define SDRAM_RDCC_RSAE_ENABLE 0x00000000 - -/*-----------------------------------------------------------------------------+ -| SDRAM Read Feedback Delay Control Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_RFDC_ARSE_MASK 0x80000000 -#define SDRAM_RFDC_ARSE_DISABLE 0x80000000 -#define SDRAM_RFDC_ARSE_ENABLE 0x00000000 -#define SDRAM_RFDC_RFOS_MASK 0x007F0000 -#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define SDRAM_RFDC_RFFD_MASK 0x000007FF -#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x7FF)<<0) - -#define SDRAM_RFDC_RFFD_MAX 0x7FF - -/*-----------------------------------------------------------------------------+ -| SDRAM Delay Line Calibration Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_DLCR_DCLM_MASK 0x80000000 -#define SDRAM_DLCR_DCLM_MANUEL 0x80000000 -#define SDRAM_DLCR_DCLM_AUTO 0x00000000 -#define SDRAM_DLCR_DLCR_MASK 0x08000000 -#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000 -#define SDRAM_DLCR_DLCR_IDLE 0x00000000 -#define SDRAM_DLCR_DLCS_MASK 0x07000000 -#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000 -#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000 -#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000 -#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000 -#define SDRAM_DLCR_DLCS_ERROR 0x04000000 -#define SDRAM_DLCR_DLCV_MASK 0x000001FF -#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) -#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF) - -/*-----------------------------------------------------------------------------+ -| SDRAM Controller On Die Termination Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_CODT_ODT_ON 0x80000000 -#define SDRAM_CODT_ODT_OFF 0x00000000 -#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020 -#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000 -#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020 -#define SDRAM_CODT_DQS_MASK 0x00000010 -#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000 -#define SDRAM_CODT_DQS_SINGLE_END 0x00000010 -#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000 -#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 -#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 -#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 -#define SDRAM_CODT_IO_HIZ 0x00000000 -#define SDRAM_CODT_IO_NMODE 0x00000001 - -/*-----------------------------------------------------------------------------+ -| SDRAM Mode Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_MMODE_WR_MASK 0x00000E00 -#define SDRAM_MMODE_WR_DDR1 0x00000000 -#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400 -#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600 -#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800 -#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00 -#define SDRAM_MMODE_DCL_MASK 0x00000070 -#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020 -#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060 -#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030 -#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020 -#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030 -#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040 -#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050 -#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060 -#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070 - -/*-----------------------------------------------------------------------------+ -| SDRAM Extended Mode Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_MEMODE_DIC_MASK 0x00000002 -#define SDRAM_MEMODE_DIC_NORMAL 0x00000000 -#define SDRAM_MEMODE_DIC_WEAK 0x00000002 -#define SDRAM_MEMODE_DLL_MASK 0x00000001 -#define SDRAM_MEMODE_DLL_DISABLE 0x00000001 -#define SDRAM_MEMODE_DLL_ENABLE 0x00000000 -#define SDRAM_MEMODE_RTT_MASK 0x00000044 -#define SDRAM_MEMODE_RTT_DISABLED 0x00000000 -#define SDRAM_MEMODE_RTT_75OHM 0x00000004 -#define SDRAM_MEMODE_RTT_150OHM 0x00000040 -#define SDRAM_MEMODE_DQS_MASK 0x00000400 -#define SDRAM_MEMODE_DQS_DISABLE 0x00000400 -#define SDRAM_MEMODE_DQS_ENABLE 0x00000000 - -/*-----------------------------------------------------------------------------+ -| SDRAM Clock Timing Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 -#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000 -#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000 -#define SDRAM_CLKTR_CLKP_90_DEG_ADV 0x40000000 -#define SDRAM_CLKTR_CLKP_270_DEG_ADV 0xC0000000 - -/*-----------------------------------------------------------------------------+ -| SDRAM Write Timing Register -+-----------------------------------------------------------------------------*/ -#define SDRAM_WRDTR_LLWP_MASK 0x10000000 -#define SDRAM_WRDTR_LLWP_DIS 0x10000000 -#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000 -#define SDRAM_WRDTR_WTR_MASK 0x0E000000 -#define SDRAM_WRDTR_WTR_0_DEG 0x06000000 -#define SDRAM_WRDTR_WTR_90_DEG_ADV 0x04000000 -#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000 -#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000 - -/*-----------------------------------------------------------------------------+ -| SDRAM SDTR1 Options -+-----------------------------------------------------------------------------*/ -#define SDRAM_SDTR1_LDOF_MASK 0x80000000 -#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000 -#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000 -#define SDRAM_SDTR1_RTW_MASK 0x00F00000 -#define SDRAM_SDTR1_RTW_2_CLK 0x00200000 -#define SDRAM_SDTR1_RTW_3_CLK 0x00300000 -#define SDRAM_SDTR1_WTWO_MASK 0x000F0000 -#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000 -#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000 -#define SDRAM_SDTR1_RTRO_MASK 0x0000F000 -#define SDRAM_SDTR1_RTRO_1_CLK 0x00001000 -#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000 - -/*-----------------------------------------------------------------------------+ -| SDRAM SDTR2 Options -+-----------------------------------------------------------------------------*/ -#define SDRAM_SDTR2_RCD_MASK 0xF0000000 -#define SDRAM_SDTR2_RCD_1_CLK 0x10000000 -#define SDRAM_SDTR2_RCD_2_CLK 0x20000000 -#define SDRAM_SDTR2_RCD_3_CLK 0x30000000 -#define SDRAM_SDTR2_RCD_4_CLK 0x40000000 -#define SDRAM_SDTR2_RCD_5_CLK 0x50000000 -#define SDRAM_SDTR2_WTR_MASK 0x0F000000 -#define SDRAM_SDTR2_WTR_1_CLK 0x01000000 -#define SDRAM_SDTR2_WTR_2_CLK 0x02000000 -#define SDRAM_SDTR2_WTR_3_CLK 0x03000000 -#define SDRAM_SDTR2_WTR_4_CLK 0x04000000 -#define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) -#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000 -#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000 -#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000 -#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000 -#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000 -#define SDRAM_SDTR2_WPC_MASK 0x0000F000 -#define SDRAM_SDTR2_WPC_2_CLK 0x00002000 -#define SDRAM_SDTR2_WPC_3_CLK 0x00003000 -#define SDRAM_SDTR2_WPC_4_CLK 0x00004000 -#define SDRAM_SDTR2_WPC_5_CLK 0x00005000 -#define SDRAM_SDTR2_WPC_6_CLK 0x00006000 -#define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12) -#define SDRAM_SDTR2_RPC_MASK 0x00000F00 -#define SDRAM_SDTR2_RPC_2_CLK 0x00000200 -#define SDRAM_SDTR2_RPC_3_CLK 0x00000300 -#define SDRAM_SDTR2_RPC_4_CLK 0x00000400 -#define SDRAM_SDTR2_RP_MASK 0x000000F0 -#define SDRAM_SDTR2_RP_3_CLK 0x00000030 -#define SDRAM_SDTR2_RP_4_CLK 0x00000040 -#define SDRAM_SDTR2_RP_5_CLK 0x00000050 -#define SDRAM_SDTR2_RP_6_CLK 0x00000060 -#define SDRAM_SDTR2_RP_7_CLK 0x00000070 -#define SDRAM_SDTR2_RRD_MASK 0x0000000F -#define SDRAM_SDTR2_RRD_2_CLK 0x00000002 -#define SDRAM_SDTR2_RRD_3_CLK 0x00000003 - -/*-----------------------------------------------------------------------------+ -| SDRAM SDTR3 Options -+-----------------------------------------------------------------------------*/ -#define SDRAM_SDTR3_RAS_MASK 0x1F000000 -#define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define SDRAM_SDTR3_RC_MASK 0x001F0000 -#define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) -#define SDRAM_SDTR3_XCS_MASK 0x00001F00 -#define SDRAM_SDTR3_XCS 0x00000D00 -#define SDRAM_SDTR3_RFC_MASK 0x0000003F -#define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) - -/*-----------------------------------------------------------------------------+ -| Memory Bank 0-1 configuration -+-----------------------------------------------------------------------------*/ -#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */ -#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */ -#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */ -#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */ -#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */ -#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */ -#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */ -#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */ -#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */ -#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */ -#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */ -#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */ -#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */ -#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */ - -#define SDRAM_RTSR_TRK1SM_MASK 0xC0000000 /* Tracking State Mach 1*/ -#define SDRAM_RTSR_TRK1SM_ATBASE 0x00000000 /* atbase state */ -#define SDRAM_RTSR_TRK1SM_MISSED 0x40000000 /* missed state */ -#define SDRAM_RTSR_TRK1SM_ATPLS1 0x80000000 /* atpls1 state */ -#define SDRAM_RTSR_TRK1SM_RESET 0xC0000000 /* reset state */ - -#define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */ -#endif /* CONFIG_440SPE */ - -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -/*----------------------------------------------------------------------------- - | SDRAM Controller - +----------------------------------------------------------------------------*/ -#define DDR0_00 0x00 -#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */ -#define DDR0_00_INT_ACK_ALL 0x7F000000 -#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -/* Status */ -#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */ -/* Bit0. A single access outside the defined PHYSICAL memory space detected. */ -#define DDR0_00_INT_STATUS_BIT0 0x00010000 -/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */ -#define DDR0_00_INT_STATUS_BIT1 0x00020000 -/* Bit2. Single correctable ECC event detected */ -#define DDR0_00_INT_STATUS_BIT2 0x00040000 -/* Bit3. Multiple correctable ECC events detected. */ -#define DDR0_00_INT_STATUS_BIT3 0x00080000 -/* Bit4. Single uncorrectable ECC event detected. */ -#define DDR0_00_INT_STATUS_BIT4 0x00100000 -/* Bit5. Multiple uncorrectable ECC events detected. */ -#define DDR0_00_INT_STATUS_BIT5 0x00200000 -/* Bit6. DRAM initialization complete. */ -#define DDR0_00_INT_STATUS_BIT6 0x00400000 -/* Bit7. Logical OR of all lower bits. */ -#define DDR0_00_INT_STATUS_BIT7 0x00800000 - -#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00 -#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_00_DLL_START_POINT_MASK 0x0000007F -#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_01 0x01 -#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000 -#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000 -#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) -#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) -#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */ -#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) -#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) -#define DDR0_01_INT_MASK_MASK 0x000000FF -#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) -#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) -#define DDR0_01_INT_MASK_ALL_ON 0x000000FF -#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 - -#define DDR0_02 0x02 -#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */ -#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24) -#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2) -#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */ -#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) -#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF) -#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */ -#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) -#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF) -#define DDR0_02_START_MASK 0x00000001 -#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1) -#define DDR0_02_START_OFF 0x00000000 -#define DDR0_02_START_ON 0x00000001 - -#define DDR0_03 0x03 -#define DDR0_03_BSTLEN_MASK 0x07000000 -#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_03_CASLAT_MASK 0x00070000 -#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_03_CASLAT_LIN_MASK 0x00000F00 -#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) -#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF) -#define DDR0_03_INITAREF_MASK 0x0000000F -#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) -#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF) - -#define DDR0_04 0x04 -#define DDR0_04_TRC_MASK 0x1F000000 -#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_04_TRRD_MASK 0x00070000 -#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_04_TRTP_MASK 0x00000700 -#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) -#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7) - -#define DDR0_05 0x05 -#define DDR0_05_TMRD_MASK 0x1F000000 -#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_05_TEMRS_MASK 0x00070000 -#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_05_TRP_MASK 0x00000F00 -#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) -#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF) -#define DDR0_05_TRAS_MIN_MASK 0x000000FF -#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) -#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) - -#define DDR0_06 0x06 -#define DDR0_06_WRITEINTERP_MASK 0x01000000 -#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1) -#define DDR0_06_TWTR_MASK 0x00070000 -#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) -#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7) -#define DDR0_06_TDLL_MASK 0x0000FF00 -#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) -#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) -#define DDR0_06_TRFC_MASK 0x0000007F -#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_07 0x07 -#define DDR0_07_NO_CMD_INIT_MASK 0x01000000 -#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1) -#define DDR0_07_TFAW_MASK 0x001F0000 -#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) -#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) -#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100 -#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) -#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) -#define DDR0_07_AREFRESH_MASK 0x00000001 -#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_08 0x08 -#define DDR0_08_WRLAT_MASK 0x07000000 -#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_08_TCPD_MASK 0x00FF0000 -#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_08_DQS_N_EN_MASK 0x00000100 -#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) -#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1) -#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001 -#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_09 0x09 -#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000 -#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_09_RTT_0_MASK 0x00030000 -#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) -#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3) -#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00 -#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F -#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_10 0x0A -#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */ -#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) -#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) -#define DDR0_10_CS_MAP_MASK 0x00000300 -#define DDR0_10_CS_MAP_NO_MEM 0x00000000 -#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100 -#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200 -#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) -#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3) -#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F -#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0) -#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F) - -#define DDR0_11 0x0B -#define DDR0_11_SREFRESH_MASK 0x01000000 -#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) -#define DDR0_11_TXSNR_MASK 0x00FF0000 -#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_11_TXSR_MASK 0x0000FF00 -#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) -#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) - -#define DDR0_12 0x0C -#define DDR0_12_TCKE_MASK 0x0000007 -#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) -#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7) - -#define DDR0_14 0x0E -#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000 -#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) -#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1) -#define DDR0_14_REDUC_MASK 0x00010000 -#define DDR0_14_REDUC_64BITS 0x00000000 -#define DDR0_14_REDUC_32BITS 0x00010000 -#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) -#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1) -#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100 -#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) -#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) - -#define DDR0_17 0x11 -#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000 -#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ -#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 -#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 -#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) -#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) -#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */ -#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) - -#define DDR0_18 0x12 -#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F -#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000 -#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000 -#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00 -#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F -#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_19 0x13 -#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F -#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000 -#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000 -#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00 -#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F -#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_20 0x14 -#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000 -#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000 -#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00 -#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F -#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_21 0x15 -#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000 -#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) -#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) -#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000 -#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00 -#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F -#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_22 0x16 -#define DDR0_22_CTRL_RAW_MASK 0x03000000 -#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */ -#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct */ -#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */ -#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */ -#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3) -#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000 -#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) -#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00 -#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) -#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) -#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F -#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) -#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) - -#define DDR0_23 0x17 -#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000 -#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3) -#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */ -#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) -#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) -#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */ -#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) -#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) -#define DDR0_23_FWC_MASK 0x00000001 /* Write only */ -#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_24 0x18 -#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000 -#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3) -#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000 -#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) -#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3) -#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300 -#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) -#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3) -#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003 -#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0) -#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3) - -#define DDR0_25 0x19 -#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */ -#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) -#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) -#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */ -#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) -#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) - -#define DDR0_26 0x1A -#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000 -#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) -#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) -#define DDR0_26_TREF_MASK 0x00003FFF -#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) -#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) - -#define DDR0_27 0x1B -#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000 -#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) -#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) -#define DDR0_27_TINIT_MASK 0x0000FFFF -#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) -#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) - -#define DDR0_28 0x1C -#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000 -#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) -#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) -#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF -#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) -#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) - -#define DDR0_31 0x1F -#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF -#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) -#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) - -#define DDR0_32 0x20 -#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_33 0x21 -#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */ -#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_34 0x22 -#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_35 0x23 -#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */ -#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_36 0x24 -#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_37 0x25 -#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_38 0x26 -#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_39 0x27 -#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */ -#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_40 0x28 -#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_41 0x29 -#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) -#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) - -#define DDR0_42 0x2A -#define DDR0_42_ADDR_PINS_MASK 0x07000000 -#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F -#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) -#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF) - -#define DDR0_43 0x2B -#define DDR0_43_TWR_MASK 0x07000000 -#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) -#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7) -#define DDR0_43_APREBIT_MASK 0x000F0000 -#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) -#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF) -#define DDR0_43_COLUMN_SIZE_MASK 0x00000700 -#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) -#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) -#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001 -#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001 -#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000 -#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) -#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1) - -#define DDR0_44 0x2C -#define DDR0_44_TRCD_MASK 0x000000FF -#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) -#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) - -#endif /* CONFIG_440EPX */ - /*----------------------------------------------------------------------------- | External Bus Controller +----------------------------------------------------------------------------*/ diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 4a6eb86f419..0a8479f2623 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -22,12 +22,37 @@ #ifndef __PPC4XX_H__ #define __PPC4XX_H__ +/* + * Configure which SDRAM/DDR/DDR2 controller is equipped + */ +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \ + defined(CONFIG_AP1000) || defined(CONFIG_ML2) +#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */ +#endif + +#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) +#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */ +#endif + +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */ +#endif + +#if defined(CONFIG_405EX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ +#endif + #if defined(CONFIG_440) #include #else #include #endif +#include + /* * Macro for generating register field mnemonics */ -- cgit v1.3.1 From ec724f883ee3f3925e6c55027e8ffa70ada83303 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 2 Jun 2008 17:13:55 +0200 Subject: ppc4xx: Change Kilauea to use the common DDR2 init function This patch changes the kilauea and kilauea_nand (for NAND booting) board port to not use a board specific DDR2 init routine anymore. Now the common code from cpu/ppc4xx is used. Thanks to Grant Erickson for all his basic work on this 405EX early bootup. Signed-off-by: Stefan Roese --- board/amcc/kilauea/Makefile | 3 +- board/amcc/kilauea/init.S | 167 --------------------------------- board/amcc/kilauea/memory.c | 84 ----------------- cpu/ppc4xx/44x_spd_ddr2.c | 11 +++ include/configs/kilauea.h | 8 +- nand_spl/board/amcc/kilauea/Makefile | 21 ++--- nand_spl/board/amcc/kilauea/config.mk | 5 +- nand_spl/board/amcc/kilauea/u-boot.lds | 1 - 8 files changed, 29 insertions(+), 271 deletions(-) delete mode 100644 board/amcc/kilauea/init.S delete mode 100644 board/amcc/kilauea/memory.c (limited to 'cpu') diff --git a/board/amcc/kilauea/Makefile b/board/amcc/kilauea/Makefile index 39328c2bda6..981ef3a97e8 100644 --- a/board/amcc/kilauea/Makefile +++ b/board/amcc/kilauea/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o cmd_pll.o memory.o -SOBJS = init.o +COBJS = $(BOARD).o cmd_pll.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/board/amcc/kilauea/init.S b/board/amcc/kilauea/init.S deleted file mode 100644 index bf47d6bb5de..00000000000 --- a/board/amcc/kilauea/init.S +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2008 Nuovation System Designs, LLC - * Grant Erickson - * - * (C) Copyright 2007-2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Originally based on code provided from UDTech and AMCC - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#include -#include - -#define mtsdram_as(reg, value) \ - addi r4,0,reg ; \ - mtdcr memcfga,r4 ; \ - addis r4,0,value@h ; \ - ori r4,r4,value@l ; \ - mtdcr memcfgd,r4 ; - -#if defined(CONFIG_DDR_ECC) - .extern ecc_init -#endif /* defined(CONFIG_DDR_ECC) */ - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: -#if !defined(CFG_INIT_DCACHE_CS) -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - - /* - * DDR2 SDRAM Controller Setup - */ - - /* Set Memory Bank Configuration Registers */ - mtsdram_as(SDRAM_MB0CF, CFG_SDRAM0_MB0CF); - mtsdram_as(SDRAM_MB1CF, CFG_SDRAM0_MB1CF); - mtsdram_as(SDRAM_MB2CF, CFG_SDRAM0_MB2CF); - mtsdram_as(SDRAM_MB3CF, CFG_SDRAM0_MB3CF); - - /* Set Memory Clock Timing Register */ - mtsdram_as(SDRAM_CLKTR, CFG_SDRAM0_CLKTR); - - /* Set Refresh Time Register */ - mtsdram_as(SDRAM_RTR, CFG_SDRAM0_RTR); - - /* Set SDRAM Timing Registers */ - mtsdram_as(SDRAM_SDTR1, CFG_SDRAM0_SDTR1); - mtsdram_as(SDRAM_SDTR2, CFG_SDRAM0_SDTR2); - mtsdram_as(SDRAM_SDTR3, CFG_SDRAM0_SDTR3); - - /* Set Mode and Extended Mode Registers */ - mtsdram_as(SDRAM_MMODE, CFG_SDRAM0_MMODE); - mtsdram_as(SDRAM_MEMODE, CFG_SDRAM0_MEMODE); - - /* Set Memory Controller Options 1 Register */ - mtsdram_as(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1); - - /* Set Manual Initialization Control Registers */ - mtsdram_as(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0); - mtsdram_as(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1); - mtsdram_as(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2); - mtsdram_as(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3); - mtsdram_as(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4); - mtsdram_as(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5); - mtsdram_as(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6); - mtsdram_as(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7); - mtsdram_as(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8); - mtsdram_as(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9); - mtsdram_as(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10); - mtsdram_as(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11); - mtsdram_as(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12); - mtsdram_as(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13); - mtsdram_as(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14); - mtsdram_as(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15); - - /* Set On-Die Termination Registers */ - mtsdram_as(SDRAM_CODT, CFG_SDRAM0_CODT); - mtsdram_as(SDRAM_MODT0, CFG_SDRAM0_MODT0); - mtsdram_as(SDRAM_MODT1, CFG_SDRAM0_MODT1); - - /* Set Write Timing Register */ - mtsdram_as(SDRAM_WRDTR, CFG_SDRAM0_WRDTR); - - /* - * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and - * SDRAM0_MCOPT2[IPTR] = 1 - */ - mtsdram_as(SDRAM_MCOPT2, SDRAM_MCOPT2_SREN_EXIT | \ - SDRAM_MCOPT2_IPTR_EXECUTE); - - /* - * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the - * completion of initialization. - * - * do { - * mfsdram(SDRAM_MCSTAT, val); - * } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP); - */ - li r4,SDRAM_MCSTAT - lis r2,SDRAM_MCSTAT_MIC_COMP@h - ori r2,r2,SDRAM_MCSTAT_MIC_COMP@l -0: mtdcr memcfga,r4 - mfdcr r3,memcfgd - clrrwi r3,r3,31 - cmpw cr7,r3,r2 - bne+ cr7,0b - - /* Set Delay Control Registers */ - mtsdram_as(SDRAM_DLCR, CFG_SDRAM0_DLCR); - mtsdram_as(SDRAM_RDCC, CFG_SDRAM0_RDCC); - mtsdram_as(SDRAM_RQDC, CFG_SDRAM0_RQDC); - mtsdram_as(SDRAM_RFDC, CFG_SDRAM0_RFDC); - - /* - * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1: - * - * mcopt2 = mfsdram(SDRAM_MCOPT2); - */ - li r4,SDRAM_MCOPT2 - mtdcr memcfga,r4 - mfdcr r3,memcfgd - - /* - * mtsdram(SDRAM_MCOPT2, mcopt2 | SDRAM_MCOPT2_DCEN_ENABLE); - */ - mtdcr memcfga,r4 - oris r3,r3,SDRAM_MCOPT2_DCEN_ENABLE@h - ori r3,r3,SDRAM_MCOPT2_DCEN_ENABLE@l - mtdcr memcfgd,r3 - -#if defined(CONFIG_DDR_ECC) - /* - * ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20); - */ - mflr r13 - lis r3,CFG_SDRAM_BASE@h - ori r3,r3,CFG_SDRAM_BASE@l - lis r4,(CFG_MBYTES_SDRAM << 20)@h - ori r4,r4,(CFG_MBYTES_SDRAM << 20)@l - bl ecc_init - mtlr r13 -#endif /* defined(CONFIG_DDR_ECC) */ -#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ -#endif /* !defined(CFG_INIT_DCACHE_CS) */ - - blr diff --git a/board/amcc/kilauea/memory.c b/board/amcc/kilauea/memory.c deleted file mode 100644 index b7e2344fd7c..00000000000 --- a/board/amcc/kilauea/memory.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2008 Nuovation System Designs, LLC - * Grant Erickson - * - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -void sdram_init(void) -{ - return; -} - -#if defined(CONFIG_NAND_U_BOOT) -long int initdram(int board_type) -{ - return (CFG_MBYTES_SDRAM << 20); -} -#endif /* defined(CONFIG_NAND_U_BOOT) */ - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - printf ("testdram\n"); -#if defined (CONFIG_NAND_U_BOOT) - return 0; -#endif - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x00001000; - uint *p; - - for (p = pstart; p < pend; p++) { - *p = 0xaaaaaaaa; - } - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test fails at: %08x\n", (uint) p); -#endif - return 1; - } - } - - for (p = pstart; p < pend; p++) { - *p = 0x55555555; - } - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test fails at: %08x\n", (uint) p); -#endif - return 1; - } - } -#if !defined (CONFIG_NAND_SPL) - printf ("SDRAM test passed!!!\n"); -#endif - return 0; -} -#endif diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index aa4a5302e0d..521491820d7 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -3083,6 +3083,16 @@ static void ppc440sp_sdram_register_dump(void) *---------------------------------------------------------------------------*/ long initdram(int board_type) { + /* + * Only run this SDRAM init code once. For NAND booting + * targets like Kilauea, we call initdram() early from the + * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot(). + * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT) + * which calls initdram() again. This time the controller + * mustn't be reconfigured again since we're already running + * from SDRAM. + */ +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) unsigned long val; /* Set Memory Bank Configuration Registers */ @@ -3178,6 +3188,7 @@ long initdram(int board_type) #if defined(CONFIG_DDR_ECC) ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20); #endif /* defined(CONFIG_DDR_ECC) */ +#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ return (CFG_MBYTES_SDRAM << 20); } diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 035a40e3b57..205577faa63 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -170,9 +170,9 @@ * This NAND U-Boot (NUB) is a special U-Boot version which can be started * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. * - * On 440EPx the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from cache, I experienced problems accessing - * the NAND controller. sr - 2006-08-25 + * On 405EX the SPL is copied to SDRAM before the NAND controller is + * set up. While still running from location 0xfffff000...0xffffffff the + * NAND controller cannot be accessed since it is attached to CS0 too. */ #define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ #define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ @@ -511,7 +511,7 @@ /* Memory Bank 2 (FPGA) initialization */ #define CFG_EBC_PB2AP 0x9400C800 -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */ +#define CFG_EBC_PB2CR (CFG_FPGA_BASE | 0x18000) #define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */ diff --git a/nand_spl/board/amcc/kilauea/Makefile b/nand_spl/board/amcc/kilauea/Makefile index 84bd29824d8..a0293ee2b58 100644 --- a/nand_spl/board/amcc/kilauea/Makefile +++ b/nand_spl/board/amcc/kilauea/Makefile @@ -29,8 +29,8 @@ LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL -SOBJS = start.o init.o resetvec.o cache.o -COBJS = memory.o nand_boot.o nand_ecc.o ndfc.o +SOBJS = start.o resetvec.o cache.o +COBJS = 44x_spd_ddr2.o nand_boot.o nand_ecc.o ndfc.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -57,10 +57,18 @@ $(nandobj)u-boot-spl: $(OBJS) # create symbolic links for common files # from cpu directory +$(obj)44x_spd_ddr2.c: ecc.h + @rm -f $(obj)44x_spd_ddr2.c + ln -s $(SRCTREE)/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c + $(obj)cache.S: @rm -f $(obj)cache.S ln -s $(SRCTREE)/cpu/ppc4xx/cache.S $(obj)cache.S +$(obj)ecc.h: + @rm -f $(obj)ecc.h + ln -s $(SRCTREE)/cpu/ppc4xx/ecc.h $(obj)ecc.h + $(obj)ndfc.c: @rm -f $(obj)ndfc.c ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c @@ -73,15 +81,6 @@ $(obj)start.S: @rm -f $(obj)start.S ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S -# from board directory -$(obj)init.S: - @rm -f $(obj)init.S - ln -s $(SRCTREE)/board/amcc/kilauea/init.S $(obj)init.S - -$(obj)memory.c: - @rm -f $(obj)memory.c - ln -s $(SRCTREE)/board/amcc/kilauea/memory.c $(obj)memory.c - # from nand_spl directory $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c diff --git a/nand_spl/board/amcc/kilauea/config.mk b/nand_spl/board/amcc/kilauea/config.mk index 22490918d07..d89ed3f0478 100644 --- a/nand_spl/board/amcc/kilauea/config.mk +++ b/nand_spl/board/amcc/kilauea/config.mk @@ -29,8 +29,9 @@ # # On 4xx platforms the SPL is located at 0xfffff000...0xffffffff, # in the last 4kBytes of memory space in cache. -# We will copy this SPL into instruction-cache in start.S. So we set -# TEXT_BASE to starting address in i-cache here. +# We will copy this SPL into SDRAM since we can't access the NAND +# controller at CS0 while running from this location. So we set +# TEXT_BASE to starting address in SDRAM here. # TEXT_BASE = 0x00800000 diff --git a/nand_spl/board/amcc/kilauea/u-boot.lds b/nand_spl/board/amcc/kilauea/u-boot.lds index 084db08dd6a..03e0b798f93 100644 --- a/nand_spl/board/amcc/kilauea/u-boot.lds +++ b/nand_spl/board/amcc/kilauea/u-boot.lds @@ -32,7 +32,6 @@ SECTIONS .text : { start.o (.text) - init.o (.text) nand_boot.o (.text) ndfc.o (.text) -- cgit v1.3.1 From 39b32be18cd33b53a84065edcd4e465165cc5564 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 2 Jun 2008 17:20:03 +0200 Subject: ppc4xx: Fix common ECC generation code for 440GP style platforms This patch makes the common 4xx ECC code really usable on 440GP style platforms. Since the IBM DDR controller used on 440GP/GX/EP/GR is not register compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT we need to make some processor dependant defines used later on by the driver. Signed-off-by: Stefan Roese --- cpu/ppc4xx/ecc.c | 14 +++++++------- cpu/ppc4xx/ecc.h | 27 +++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 7 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/ecc.c b/cpu/ppc4xx/ecc.c index 95b941dabbb..3e87c8442ce 100644 --- a/cpu/ppc4xx/ecc.c +++ b/cpu/ppc4xx/ecc.c @@ -76,7 +76,7 @@ void ecc_init(unsigned long * const start, unsigned long size) { const unsigned long pattern = CFG_ECC_PATTERN; - unsigned * const end = (unsigned long * const)((long)start + size); + unsigned long * const end = (unsigned long * const)((long)start + size); unsigned long * current = start; unsigned long mcopt1; long increment; @@ -84,12 +84,12 @@ void ecc_init(unsigned long * const start, unsigned long size) if (start >= end) return; - mfsdram(SDRAM_MCOPT1, mcopt1); + mfsdram(SDRAM_ECC_CFG, mcopt1); /* Enable ECC generation without checking or reporting */ - mtsdram(SDRAM_MCOPT1, ((mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | - SDRAM_MCOPT1_MCHK_GEN)); + mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) | + SDRAM_ECC_CFG_MCHK_GEN)); increment = sizeof(u32); @@ -99,7 +99,7 @@ void ecc_init(unsigned long * const start, unsigned long size) * can skip words when writing. */ - if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) != SDRAM_MCOPT1_DMWD_32) + if ((mcopt1 & SDRAM_ECC_CFG_DMWD_MASK) != SDRAM_ECC_CFG_DMWD_32) increment = sizeof(u64); #endif /* defined(CONFIG_440) */ @@ -114,8 +114,8 @@ void ecc_init(unsigned long * const start, unsigned long size) /* Enable ECC generation with checking and no reporting */ - mtsdram(SDRAM_MCOPT1, ((mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | - SDRAM_MCOPT1_MCHK_CHK)); + mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) | + SDRAM_ECC_CFG_MCHK_CHK)); } #endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */ #endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */ diff --git a/cpu/ppc4xx/ecc.h b/cpu/ppc4xx/ecc.h index da1c4fda8a1..aecf291a8b6 100644 --- a/cpu/ppc4xx/ecc.h +++ b/cpu/ppc4xx/ecc.h @@ -37,6 +37,33 @@ #define CFG_ECC_PATTERN 0x00000000 #endif /* !defined(CFG_ECC_PATTERN) */ +/* + * Since the IBM DDR controller used on 440GP/GX/EP/GR is not register + * compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT + * we need to make some processor dependant defines used later on by the + * driver. + */ + +/* For 440GP/GX/EP/GR */ +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) +#define SDRAM_ECC_CFG SDRAM_CFG0 +#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_CFG0_MCHK_MASK +#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_CFG0_MCHK_GEN +#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_CFG0_MCHK_CHK +#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_CFG0_DMWD_MASK +#define SDRAM_ECC_CFG_DMWD_32 SDRAM_CFG0_DMWD_32 +#endif + +/* For 405EX/440SP/SPe/460EX/GT */ +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) +#define SDRAM_ECC_CFG SDRAM_MCOPT1 +#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_MCOPT1_MCHK_MASK +#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_MCOPT1_MCHK_GEN +#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_MCOPT1_MCHK_CHK +#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_MCOPT1_DMWD_MASK +#define SDRAM_ECC_CFG_DMWD_32 SDRAM_MCOPT1_DMWD_32 +#endif + extern void ecc_init(unsigned long * const start, unsigned long size); #endif /* _ECC_H_ */ -- cgit v1.3.1 From 192f90e272b3989ee7b4a666d1fdab831f20f8d2 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 2 Jun 2008 17:22:11 +0200 Subject: ppc4xx: Use new 4xx SDRAM controller enable defines in common ECC code Signed-off-by: Stefan Roese --- cpu/ppc4xx/ecc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/ecc.c b/cpu/ppc4xx/ecc.c index 3e87c8442ce..a2eb07bd755 100644 --- a/cpu/ppc4xx/ecc.c +++ b/cpu/ppc4xx/ecc.c @@ -45,7 +45,8 @@ #include "ecc.h" -#if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \ + defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) #if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) /* * void ecc_init() @@ -118,4 +119,4 @@ void ecc_init(unsigned long * const start, unsigned long size) SDRAM_ECC_CFG_MCHK_CHK)); } #endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */ -#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */ +#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */ -- cgit v1.3.1 From bbeff30cbd1c5d551eb0ad1c2239ec01844c0b0a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 2 Jun 2008 17:37:28 +0200 Subject: ppc4xx: Remove superfluous dram_init() call or replace it by initdram() Historically the 405 U-Boot port had a dram_init() call in early init stage. This function was still called from start.S and most of the time coded in assembler. This is not needed anymore (since a long time) and boards should implement the common initdram() function in C instead. This patch now removed the dram_init() call from start.S and removes the empty implementations that are scattered through most of the 405 board ports. Some older board ports really implement this dram_init() though. These are: csb272 csb472 ERIC EXBITGEN W7OLMC W7OLMG I changed those boards to call this assembler dram_init() function now from their board specific initdram() instead. This *should* work, but please test again on those platforms. And it is perhaps a good idea that those boards use some common 405 SDRAM initialization code from cpu/ppc4xx at some time. So further patches welcome here. Signed-off-by: Stefan Roese --- board/amcc/acadia/memory.c | 15 ------------ board/amcc/bubinga/bubinga.c | 16 ------------- board/amcc/makalu/makalu.c | 5 ---- board/amcc/walnut/walnut.c | 16 ------------- board/amcc/yosemite/yosemite.c | 52 +++--------------------------------------- board/amirix/ap1000/init.S | 4 ---- board/cray/L1/init.S | 11 --------- board/csb272/csb272.c | 9 ++++++++ board/csb472/csb472.c | 9 ++++++++ board/eric/eric.c | 8 +++++++ board/esd/ar405/ar405.c | 22 ------------------ board/esd/canbt/canbt.c | 19 --------------- board/exbitgen/exbitgen.c | 9 ++++++++ board/g2000/g2000.c | 35 ---------------------------- board/jse/init.S | 10 -------- board/ml2/init.S | 4 ---- board/mpl/mip405/init.S | 13 ----------- board/mpl/pip405/init.S | 13 ----------- board/netstal/hcu4/hcu4.c | 9 -------- board/netstal/hcu5/sdram.c | 26 ++------------------- board/netstal/mcu25/mcu25.c | 9 -------- board/w7o/w7o.c | 8 +++++++ board/xilinx/ml300/init.S | 4 ---- cpu/ppc4xx/sdram.c | 10 ++++++-- cpu/ppc4xx/start.S | 6 ----- 25 files changed, 56 insertions(+), 286 deletions(-) (limited to 'cpu') diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 709d41e41aa..3dec3159a59 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -33,14 +33,6 @@ extern void board_pll_init_f(void); -/* - * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! - */ -void sdram_init(void) -{ - return; -} - #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) static void cram_bcr_write(u32 wr_val) { @@ -116,10 +108,3 @@ long int initdram(int board_type) return (CFG_MBYTES_RAM << 20); } - -#ifndef CONFIG_NAND_SPL -int testdram(void) -{ - return (0); -} -#endif diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c index 66e7509da89..9d508b8937e 100644 --- a/board/amcc/bubinga/bubinga.c +++ b/board/amcc/bubinga/bubinga.c @@ -66,14 +66,6 @@ int checkboard(void) return (0); } -/* - * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! - */ -void sdram_init(void) -{ - return; -} - /* ------------------------------------------------------------------------- initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of the necessary info for SDRAM controller configuration @@ -85,11 +77,3 @@ long int initdram(int board_type) ret = spd_sdram(); return ret; } - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("test: xxx MB - ok\n"); - - return (0); -} diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c index adf604f3ab3..9baec9af67a 100644 --- a/board/amcc/makalu/makalu.c +++ b/board/amcc/makalu/makalu.c @@ -351,8 +351,3 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_strerror(rc)); } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ - -void sdram_init(void) -{ - return; -} diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c index 292e02609e2..641987e871c 100644 --- a/board/amcc/walnut/walnut.c +++ b/board/amcc/walnut/walnut.c @@ -85,14 +85,6 @@ int checkboard(void) return (0); } -/* - * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! - */ -void sdram_init(void) -{ - return; -} - /* * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of * the necessary info for SDRAM controller configuration @@ -101,11 +93,3 @@ long int initdram(int board_type) { return spd_sdram(); } - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("test: xxx MB - ok\n"); - - return (0); -} diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 212fab8d08e..83455375def 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -200,7 +200,7 @@ int checkboard(void) } /************************************************************************* - * sdram_init -- doesn't use serial presence detect. + * initdram -- doesn't use serial presence detect. * * Assumes: 256 MB, ECC, non-registered * PLB @ 133 MHz @@ -281,7 +281,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value) *tr1_value = (first_good + last_bad) / 2; } -void sdram_init(void) +long int initdram(int board) { register uint reg; int tr1_bank1, tr1_bank2; @@ -327,57 +327,11 @@ void sdram_init(void) sdram_tr1_set(0x00000000, &tr1_bank1); sdram_tr1_set(0x08000000, &tr1_bank2); - mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) ); -} + mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800)); -/************************************************************************* - * long int initdram - * - ************************************************************************/ -long int initdram(int board) -{ - sdram_init(); return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */ } -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - - mtmsr(0); - - for (k = 0; k < CFG_KBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - return 0; -} -#endif - /************************************************************************* * pci_pre_init * diff --git a/board/amirix/ap1000/init.S b/board/amirix/ap1000/init.S index 3aaa5c2f1a5..65f13e17a64 100644 --- a/board/amirix/ap1000/init.S +++ b/board/amirix/ap1000/init.S @@ -28,7 +28,3 @@ .globl ext_bus_cntlr_init ext_bus_cntlr_init: blr - - .globl sdram_init -sdram_init: - blr diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S index 72a10d3a1bf..4b6b3f40030 100644 --- a/board/cray/L1/init.S +++ b/board/cray/L1/init.S @@ -134,14 +134,3 @@ ext_bus_cntlr_init: mtdcr ebccfgd,r4 blr - -/*----------------------------------------------------------------------------- */ -/* Function: sdram_init */ -/* Description: Configures SDRAM memory banks. */ -/* NOTE: for CrayL1 we have ECC memory, so enable it. */ -/*....now done in C in L1.c:init_sdram for readability. */ -/*----------------------------------------------------------------------------- */ - .globl sdram_init - -sdram_init: - blr diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c index 24c6f0d9869..640412d10d1 100644 --- a/board/csb272/csb272.c +++ b/board/csb272/csb272.c @@ -27,6 +27,8 @@ #include #include +void sdram_init(void); + /* * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator * @@ -124,6 +126,13 @@ long initdram (int board_type) ulong bank_size; ulong tmp; + /* + * ToDo: Move the asm init routine sdram_init() to this C file, + * or even better use some common ppc4xx code available + * in cpu/ppc4xx + */ + sdram_init(); + tot_size = 0; mtdcr (memcfga, mem_mb0cf); diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c index 833bbce923d..1fbf17f9441 100644 --- a/board/csb472/csb472.c +++ b/board/csb472/csb472.c @@ -27,6 +27,8 @@ #include #include +void sdram_init(void); + /* * board_early_init_f: do early board initialization * @@ -92,6 +94,13 @@ long initdram (int board_type) ulong bank_size; ulong tmp; + /* + * ToDo: Move the asm init routine sdram_init() to this C file, + * or even better use some common ppc4xx code available + * in cpu/ppc4xx + */ + sdram_init(); + tot_size = 0; mtdcr (memcfga, mem_mb0cf); diff --git a/board/eric/eric.c b/board/eric/eric.c index 5413ae15c75..14ba9b0a413 100644 --- a/board/eric/eric.c +++ b/board/eric/eric.c @@ -31,6 +31,8 @@ #define PPC405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */ #define PPC405GP_GPIO0_IR 0xef60071c /* GPIO Input */ +void sdram_init(void); + int board_early_init_f (void) { @@ -127,6 +129,12 @@ long int initdram (int board_type) int TotalSize; #endif + /* + * ToDo: Move the asm init routine sdram_init() to this C file, + * or even better use some common ppc4xx code available + * in cpu/ppc4xx + */ + sdram_init(); #ifdef CONFIG_ERIC /* diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c index dfead3363c2..3abcfe690e9 100644 --- a/board/esd/ar405/ar405.c +++ b/board/esd/ar405/ar405.c @@ -190,28 +190,6 @@ int checkboard (void) return 0; } -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - #if 1 /* test-only: some internal test routines... */ /* diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c index 055a3977306..30fa605abb6 100644 --- a/board/esd/canbt/canbt.c +++ b/board/esd/canbt/canbt.c @@ -181,22 +181,3 @@ int checkboard (void) return 0; } - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - return (16 * 1024 * 1024); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c index 39a97225f8c..49031cfce66 100644 --- a/board/exbitgen/exbitgen.c +++ b/board/exbitgen/exbitgen.c @@ -3,6 +3,8 @@ #include #include "exbitgen.h" +void sdram_init(void); + /* ************************************************************************ */ int board_early_init_f (void) /* ------------------------------------------------------------------------ -- @@ -83,6 +85,13 @@ long int initdram (int board_type) ulong bank_size; ulong tmp; + /* + * ToDo: Move the asm init routine sdram_init() to this C file, + * or even better use some common ppc4xx code available + * in cpu/ppc4xx + */ + sdram_init(); + tot_size = 0; mtdcr (memcfga, mem_mb0cf); diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index 2dfd87c78e5..9fcab748498 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -149,41 +149,6 @@ long int initdram (int board_type) } -#if 1 /* test-only */ -void sdram_init(void) -{ - init_sdram_static_settings(); -} -#endif - - -#if 0 /* test-only */ -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} -#endif - - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - #if defined(CONFIG_CMD_NAND) #include extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/jse/init.S b/board/jse/init.S index 231cd1caf56..c564ed3c94e 100644 --- a/board/jse/init.S +++ b/board/jse/init.S @@ -93,13 +93,3 @@ ext_bus_cntlr_init: mtdcr ebccfgd,r4 blr - - -/*----------------------------------------------------------------------- */ -/* Function: sdram_init */ -/* Description: This function is called by cpu/ppc4xx/start.S code */ -/* to get the SDRAM initialized. */ -/*----------------------------------------------------------------------- */ - .globl sdram_init -sdram_init: - blr diff --git a/board/ml2/init.S b/board/ml2/init.S index 80f98c5bd90..9064d3b669b 100644 --- a/board/ml2/init.S +++ b/board/ml2/init.S @@ -28,7 +28,3 @@ .globl ext_bus_cntlr_init ext_bus_cntlr_init: blr - - .globl sdram_init -sdram_init: - blr diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S index 3351b5b840e..f00a871dfd5 100644 --- a/board/mpl/mip405/init.S +++ b/board/mpl/mip405/init.S @@ -178,19 +178,6 @@ ext_bus_cntlr_init: nop /* pass2 DCR errata #8 */ blr -/*----------------------------------------------------------------------------- - * Function: sdram_init - * Description: Configures the internal SRAM memory. and setup the - * Stackpointer in it. - *----------------------------------------------------------------------------- */ - .globl sdram_init - -sdram_init: - - - blr - - #if defined(CONFIG_BOOT_PCI) .section .bootpg,"ax" .globl _start_pci diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S index 39f2ea534ae..838432525de 100644 --- a/board/mpl/pip405/init.S +++ b/board/mpl/pip405/init.S @@ -175,19 +175,6 @@ nop /* pass2 DCR errata #8 */ blr -/*----------------------------------------------------------------------------- - * Function: sdram_init - * Description: Configures the internal SRAM memory. and setup the - * Stackpointer in it. - *----------------------------------------------------------------------------- */ - .globl sdram_init - -sdram_init: - - - blr - - #if defined(CONFIG_BOOT_PCI) .section .bootpg,"ax" .globl _start_pci diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index dc526fcd7aa..42c7c16cdf0 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -120,15 +120,6 @@ void hcu_led_set(u32 value) out_be32((u32 *)GPIO0_OR, tmp); } -/* - * sdram_init - Dummy implementation for start.S, spd_sdram or initdram - * used for HCUx - */ -void sdram_init(void) -{ - return; -} - /* * hcu_get_slot */ diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 6b1b53a4d05..d8817b831af 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -40,28 +40,6 @@ void hcu_led_set(u32 value); void dcbz_area(u32 start_address, u32 num_bytes); -#define DDR_DCR_BASE 0x10 -#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ -#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ - -#define DDR0_01_INT_MASK_MASK 0x000000FF -#define DDR0_00_INT_ACK_ALL 0x7F000000 -#define DDR0_01_INT_MASK_ALL_ON 0x000000FF -#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 - -#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ -#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 -#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 - -#define DDR0_22 0x16 -/* ECC */ -#define DDR0_22_CTRL_RAW_MASK 0x03000000 -#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not enabled */ -#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC no correction */ -#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* Not a ECC RAM*/ -#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */ -#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) - #define ECC_RAM 0x03267F0B #define NO_ECC_RAM 0x00267F0B @@ -111,11 +89,11 @@ static int wait_for_dlllock(void) /* -----------------------------------------------------------+ * Wait for the DCC master delay line to finish calibration * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_17); + mtdcr(memcfga, DDR0_17); val = DDR0_17_DLLLOCKREG_UNLOCKED; while (wait != 0xffff) { - val = mfdcr(ddrcfgd); + val = mfdcr(memcfgd); if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED) /* dlllockreg bit on */ diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c index 2b21444e2d2..07891f6785a 100644 --- a/board/netstal/mcu25/mcu25.c +++ b/board/netstal/mcu25/mcu25.c @@ -127,15 +127,6 @@ void hcu_led_set(u32 value) out_be16((u16 *)MCU25_LED_REGISTER_ADDRESS, value); } -/* - * sdram_init - Dummy implementation for start.S, spd_sdram or initdram - * used for HCUx - */ -void sdram_init(void) -{ - return; -} - /* * hcu_get_slot */ diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c index c56c269daec..7a3d63a4bf3 100644 --- a/board/w7o/w7o.c +++ b/board/w7o/w7o.c @@ -31,6 +31,7 @@ #include unsigned long get_dram_size (void); +void sdram_init(void); /* * Macros to transform values @@ -153,6 +154,13 @@ int checkboard (void) long int initdram (int board_type) { + /* + * ToDo: Move the asm init routine sdram_init() to this C file, + * or even better use some common ppc4xx code available + * in cpu/ppc4xx + */ + sdram_init(); + return get_dram_size (); } diff --git a/board/xilinx/ml300/init.S b/board/xilinx/ml300/init.S index f753df851aa..a282c9ae228 100644 --- a/board/xilinx/ml300/init.S +++ b/board/xilinx/ml300/init.S @@ -42,7 +42,3 @@ .globl ext_bus_cntlr_init ext_bus_cntlr_init: blr - - .globl sdram_init -sdram_init: - blr diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index 901d650cea1..c7771addaac 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -164,7 +164,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh) /* * Autodetect onboard SDRAM on 405 platforms */ -void sdram_init(void) +long int initdram(int board_type) { ulong speed; ulong sdtr1; @@ -232,9 +232,15 @@ void sdram_init(void) mtsdram(mem_mcopt1, 0); } #endif - return; + + /* + * OK, size detected -> all done + */ + return mb0cf[i].size; } } + + return 0; } #else /* CONFIG_440 */ diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 25ee36932f9..426bf3c6f9a 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -217,7 +217,6 @@ .extern ext_bus_cntlr_init - .extern sdram_init #ifdef CONFIG_NAND_U_BOOT .extern reconfig_tlb0 #endif @@ -1119,11 +1118,6 @@ _start: stw r0, +12(r1) /* Save return addr (underflow vect) */ #endif /* CFG_INIT_DCACHE_CS */ - /*----------------------------------------------------------------------- */ - /* Initialize SDRAM Controller */ - /*----------------------------------------------------------------------- */ - bl sdram_init - #ifdef CONFIG_NAND_SPL bl nand_boot_common /* will not return */ #else -- cgit v1.3.1 From b2815f79288d4da7a3ba18bdbd05120ce09d5622 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 6 Jun 2008 16:10:41 +0200 Subject: ppc4xx: Fix misspelled CONFIG_440SPE/440EPX/GRX config options We use upper case letters for the AMCC processor defines (like CONFIG_440SPE) in U-Boot. So the 440SPe is labeled CONFIG_440SPE and not CONFIG_440SPe. This patch fixes the last misspelled config options. Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_uart.c | 10 +++++----- post/cpu/ppc4xx/uart.c | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c index ffbc222e7a9..a7587d4351f 100644 --- a/cpu/ppc4xx/4xx_uart.c +++ b/cpu/ppc4xx/4xx_uart.c @@ -98,14 +98,14 @@ DECLARE_GLOBAL_DATA_PTR; #define UDIV_SUBTRACT 0 #define UART0_SDR sdr_uart0 #define UART1_SDR sdr_uart1 -#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ - defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPe) || \ +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) #define UART2_SDR sdr_uart2 #endif -#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ - defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \ +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) #define UART3_SDR sdr_uart3 #endif diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c index 27cfb915948..1a57c3dd1f2 100644 --- a/post/cpu/ppc4xx/uart.c +++ b/post/cpu/ppc4xx/uart.c @@ -79,13 +79,13 @@ #define UDIV_SUBTRACT 0 #define UART0_SDR sdr_uart0 #define UART1_SDR sdr_uart1 -#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ - defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPe) +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define UART2_SDR sdr_uart2 #endif -#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ - defined(CONFIG_440GR) || defined(CONFIG_440GRx) +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRX) #define UART3_SDR sdr_uart3 #endif #define MFREG(a, d) mfsdr(a, d) -- cgit v1.3.1