From 0b135cfc2e524dc249b75057b55dd4cc09842e27 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Sun, 13 May 2007 20:58:00 +0900 Subject: sh: First support code of SuperH. Signed-off-by: Nobuhiro Iwamatsu --- cpu/sh4/Makefile | 46 +++++++++++++++++++++++++ cpu/sh4/config.mk | 28 ++++++++++++++++ cpu/sh4/cpu.c | 67 +++++++++++++++++++++++++++++++++++++ cpu/sh4/interrupts.c | 39 ++++++++++++++++++++++ cpu/sh4/start.S | 75 +++++++++++++++++++++++++++++++++++++++++ cpu/sh4/time.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++++ cpu/sh4/watchdog.c | 50 ++++++++++++++++++++++++++++ 7 files changed, 399 insertions(+) create mode 100644 cpu/sh4/Makefile create mode 100644 cpu/sh4/config.mk create mode 100644 cpu/sh4/cpu.c create mode 100644 cpu/sh4/interrupts.c create mode 100644 cpu/sh4/start.S create mode 100644 cpu/sh4/time.c create mode 100644 cpu/sh4/watchdog.c (limited to 'cpu') diff --git a/cpu/sh4/Makefile b/cpu/sh4/Makefile new file mode 100644 index 00000000000..b24a280dbeb --- /dev/null +++ b/cpu/sh4/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2007 +# Nobuhiro Iwamatsu +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +OBJS = cpu.o interrupts.o watchdog.o time.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/sh4/config.mk b/cpu/sh4/config.mk new file mode 100644 index 00000000000..2dc7b918d7c --- /dev/null +++ b/cpu/sh4/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2007 +# Nobuhiro Iwamatsu +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +PLATFORM_CPPFLAGS += -m4-nofpu +PLATFORM_RELFLAGS += -ffixed-r13 diff --git a/cpu/sh4/cpu.c b/cpu/sh4/cpu.c new file mode 100644 index 00000000000..70df45ef9ef --- /dev/null +++ b/cpu/sh4/cpu.c @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2007 + * Nobuhiro Iwamatsu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +int checkcpu(void) +{ + puts("CPU: SH4\n"); + return 0; +} + +int cpu_init (void) +{ + return 0; +} + +int cleanup_before_linux (void) +{ + disable_interrupts(); + return 0; +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + disable_interrupts(); + reset_cpu (0); + return 0; +} + +void flush_cache (unsigned long addr, unsigned long size){} + +void icache_enable (void) +{ + +} + +void icache_disable (void) +{ + +} + + +int icache_status (void) +{ + return 0; +} diff --git a/cpu/sh4/interrupts.c b/cpu/sh4/interrupts.c new file mode 100644 index 00000000000..d310dd2c176 --- /dev/null +++ b/cpu/sh4/interrupts.c @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2007 + * Nobuhiro Iwamatsu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +int interrupt_init (void) +{ + return 0; +} + +void enable_interrupts (void) +{ + +} + +int disable_interrupts (void){ + return 0; +} + diff --git a/cpu/sh4/start.S b/cpu/sh4/start.S new file mode 100644 index 00000000000..d88b705ef08 --- /dev/null +++ b/cpu/sh4/start.S @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2007 + * Nobuhiro Iwamatsu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + .text + .align 2 + + .global _start +_start: + mov.l ._lowlevel_init, r0 +100: bsrf r0 + nop + + bsr 1f + nop +1: sts pr, r5 + mov.l ._reloc_dst, r4 + add #(_start-1b), r5 + mov.l ._reloc_dst_end, r6 + +2: mov.l @r5+, r1 + mov.l r1, @r4 + add #4, r4 + cmp/hs r6, r4 + bf 2b + + mov.l ._bss_start, r4 + mov.l ._bss_end, r5 + mov #0, r1 + +3: mov.l r1, @r4 /* bss clear */ + add #4, r4 + cmp/hs r5, r4 + bf 3b + + mov.l ._gd_init, r13 /* global data */ + mov.l ._stack_init, r15 /* stack */ + + mov.l ._sh_generic_init, r0 + jsr @r0 + nop + +loop: + bra loop + + .align 2 + +._lowlevel_init: .long (lowlevel_init - (100b + 4)) +._reloc_dst: .long reloc_dst +._reloc_dst_end: .long reloc_dst_end +._bss_start: .long bss_start +._bss_end: .long bss_end +._gd_init: .long (_start - CFG_GBL_DATA_SIZE) +._stack_init: .long (_start - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN - 16) +._sh_generic_init: .long sh_generic_init + diff --git a/cpu/sh4/time.c b/cpu/sh4/time.c new file mode 100644 index 00000000000..b6e4d0246b2 --- /dev/null +++ b/cpu/sh4/time.c @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define TMU_MAX_COUNTER (~0UL) + +static void tmu_timer_start (unsigned int timer) +{ + if (timer > 2) + return; + + *((volatile unsigned char *) TSTR0) |= (1 << timer); +} + +int timer_init (void) +{ + /* Divide clock by 4 */ + *(volatile u16 *)TCR0 = 0; + + tmu_timer_start (0); + return 0; +} + +/* + In theory we should return a true 64bit value (ie something that doesn't + overflow). However, we don't. Therefore if TMU runs at fastest rate of + 6.75 MHz this value will wrap after u-boot has been running for approx + 10 minutes. +*/ +unsigned long long get_ticks (void) +{ + return (0 - *((volatile unsigned int *) TCNT0)); +} + +unsigned long get_timer (unsigned long base) +{ + unsigned long n = + *((volatile unsigned int *)TCNT0) ; + + return ((int)n - base ) < 0 ? ( TMU_MAX_COUNTER - ( base -n )):(n - base ); +} + +void set_timer (unsigned long t) +{ + *((volatile unsigned int *) TCNT0) = (0 - t); +} + +void reset_timer (void) +{ + set_timer (0); +} + +void udelay (unsigned long usec) +{ + unsigned int start = get_timer (0); + unsigned int end = 0; + if (usec > 1000000) + end = ((usec/100000) * CFG_HZ) / 10; + else if (usec > 1000) + end = ((usec/100) * CFG_HZ) / 10000; + else + end = (usec * CFG_HZ) / 1000000; + + while (get_timer (0) < end) + continue; +} + +unsigned long get_tbclk (void) +{ + return CFG_HZ; +} + diff --git a/cpu/sh4/watchdog.c b/cpu/sh4/watchdog.c new file mode 100644 index 00000000000..e2bc8203176 --- /dev/null +++ b/cpu/sh4/watchdog.c @@ -0,0 +1,50 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define WDT_BASE WTCNT + +static unsigned char cnt_read (void){ + return *((volatile unsigned char *)(WDT_BASE + 0x00)); +} + +static unsigned char csr_read (void){ + return *((volatile unsigned char *)(WDT_BASE + 0x04)); +} + +static void cnt_write (unsigned char value){ + while (csr_read() & (1 << 5)) { + /* delay */ + } + *((volatile unsigned short *)(WDT_BASE + 0x00)) = ((unsigned short) value) | 0x5A00; +} + +static void csr_write (unsigned char value){ + *((volatile unsigned short *)(WDT_BASE + 0x04)) = ((unsigned short) value) | 0xA500; +} + + +int watchdog_init (void){ return 0; } + +void reset_cpu (unsigned long ignored) +{ + while(1); +} + + -- cgit v1.3.1 From b02bad128669e567fce87d8df823b06a0144b8db Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Sun, 23 Sep 2007 02:12:30 +0900 Subject: sh: Update core code of SuperH. Signed-off-by: Nobuhiro Iwamatsu --- cpu/sh4/Makefile | 2 +- cpu/sh4/cache.c | 108 +++++++++++++++++ cpu/sh4/cpu.c | 24 +++- cpu/sh4/time.c | 34 +++--- cpu/sh4/watchdog.c | 6 +- include/asm-sh/bitops.h | 175 +++++++++++++++++++++++++-- include/asm-sh/cpu_sh4.h | 44 ++++++- include/asm-sh/cpu_sh7750.h | 281 ++++++++++++++++++++++++++------------------ include/asm-sh/errno.h | 156 ++++++++++++++++++++++++ include/asm-sh/io.h | 103 ++++------------ include/asm-sh/irqflags.h | 126 ++++++++++++++++++++ include/asm-sh/string.h | 30 +++++ lib_sh/board.c | 119 +++++++++++++------ lib_sh/sh_linux.c | 1 + lib_sh/time.c | 1 - sh_config.mk | 24 ++++ 16 files changed, 964 insertions(+), 270 deletions(-) create mode 100644 cpu/sh4/cache.c create mode 100644 include/asm-sh/errno.h create mode 100644 include/asm-sh/irqflags.h create mode 100644 sh_config.mk (limited to 'cpu') diff --git a/cpu/sh4/Makefile b/cpu/sh4/Makefile index b24a280dbeb..1bb8bd7729e 100644 --- a/cpu/sh4/Makefile +++ b/cpu/sh4/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -OBJS = cpu.o interrupts.o watchdog.o time.o +OBJS = cpu.o interrupts.o watchdog.o time.o cache.o all: .depend $(START) $(LIB) diff --git a/cpu/sh4/cache.c b/cpu/sh4/cache.c new file mode 100644 index 00000000000..55acb31bc4b --- /dev/null +++ b/cpu/sh4/cache.c @@ -0,0 +1,108 @@ +/* + * (C) Copyright 2007 + * Nobuhiro Iwamatsu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* + * Jump to P2 area. + * When handling TLB or caches, we need to do it from P2 area. + */ +#define jump_to_P2() \ + do { \ + unsigned long __dummy; \ + __asm__ __volatile__( \ + "mov.l 1f, %0\n\t" \ + "or %1, %0\n\t" \ + "jmp @%0\n\t" \ + " nop\n\t" \ + ".balign 4\n" \ + "1: .long 2f\n" \ + "2:" \ + : "=&r" (__dummy) \ + : "r" (0x20000000)); \ + } while (0) + +/* + * Back to P1 area. + */ +#define back_to_P1() \ + do { \ + unsigned long __dummy; \ + __asm__ __volatile__( \ + "nop;nop;nop;nop;nop;nop;nop\n\t" \ + "mov.l 1f, %0\n\t" \ + "jmp @%0\n\t" \ + " nop\n\t" \ + ".balign 4\n" \ + "1: .long 2f\n" \ + "2:" \ + : "=&r" (__dummy)); \ + } while (0) + +#define CACHE_VALID 1 +#define CACHE_UPDATED 2 + +static inline void cache_wback_all(void) +{ + unsigned long addr, data, i, j; + + jump_to_P2(); + for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++){ + for (j = 0; j < CACHE_OC_NUM_WAYS; j++) { + addr = CACHE_OC_ADDRESS_ARRAY | (j << CACHE_OC_WAY_SHIFT) + | (i << CACHE_OC_ENTRY_SHIFT); + data = inl(addr); + if (data & CACHE_UPDATED) { + data &= ~CACHE_UPDATED; + outl(data, addr); + } + } + } + back_to_P1(); +} + + +#define CACHE_ENABLE 0 +#define CACHE_DISABLE 1 + +int cache_control(unsigned int cmd) +{ + unsigned long ccr; + + jump_to_P2(); + ccr = inl(CCR); + + if (ccr & CCR_CACHE_ENABLE) + cache_wback_all(); + + if (cmd == CACHE_DISABLE) + outl(CCR_CACHE_STOP, CCR); + else + outl(CCR_CACHE_INIT, CCR); + back_to_P1(); + + return 0; +} diff --git a/cpu/sh4/cpu.c b/cpu/sh4/cpu.c index 70df45ef9ef..d76d5180e7e 100644 --- a/cpu/sh4/cpu.c +++ b/cpu/sh4/cpu.c @@ -23,6 +23,7 @@ #include #include +#include int checkcpu(void) { @@ -48,20 +49,35 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } -void flush_cache (unsigned long addr, unsigned long size){} +void flush_cache (unsigned long addr, unsigned long size) +{ + +} void icache_enable (void) { - + cache_control(0); } void icache_disable (void) { - + cache_control(1); } - int icache_status (void) { return 0; } + +void dcache_enable (void) +{ +} + +void dcache_disable (void) +{ +} + +int dcache_status (void) +{ + return 0; +} diff --git a/cpu/sh4/time.c b/cpu/sh4/time.c index b6e4d0246b2..5f8a3a0802d 100644 --- a/cpu/sh4/time.c +++ b/cpu/sh4/time.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2007 + * Nobobuhiro Iwamatsu + * * (C) Copyright 2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * @@ -31,7 +34,15 @@ static void tmu_timer_start (unsigned int timer) if (timer > 2) return; - *((volatile unsigned char *) TSTR0) |= (1 << timer); + *((volatile unsigned char *) TSTR) |= (1 << timer); +} + +static void tmu_timer_stop (unsigned int timer) +{ + u8 val = *((volatile u8 *)TSTR); + if (timer > 2) + return; + *((volatile unsigned char *)TSTR) = val &~(1 << timer); } int timer_init (void) @@ -39,7 +50,8 @@ int timer_init (void) /* Divide clock by 4 */ *(volatile u16 *)TCR0 = 0; - tmu_timer_start (0); + tmu_timer_stop(0); + tmu_timer_start(0); return 0; } @@ -51,15 +63,12 @@ int timer_init (void) */ unsigned long long get_ticks (void) { - return (0 - *((volatile unsigned int *) TCNT0)); + return (0 - *((volatile u32 *) TCNT0)); } unsigned long get_timer (unsigned long base) { - unsigned long n = - *((volatile unsigned int *)TCNT0) ; - - return ((int)n - base ) < 0 ? ( TMU_MAX_COUNTER - ( base -n )):(n - base ); + return ((0 - *((volatile u32 *) TCNT0)) - base); } void set_timer (unsigned long t) @@ -69,19 +78,15 @@ void set_timer (unsigned long t) void reset_timer (void) { + tmu_timer_stop(0); set_timer (0); + tmu_timer_start(0); } void udelay (unsigned long usec) { unsigned int start = get_timer (0); - unsigned int end = 0; - if (usec > 1000000) - end = ((usec/100000) * CFG_HZ) / 10; - else if (usec > 1000) - end = ((usec/100) * CFG_HZ) / 10000; - else - end = (usec * CFG_HZ) / 1000000; + unsigned int end = start + (usec * ((CFG_HZ + 500000) / 1000000)); while (get_timer (0) < end) continue; @@ -91,4 +96,3 @@ unsigned long get_tbclk (void) { return CFG_HZ; } - diff --git a/cpu/sh4/watchdog.c b/cpu/sh4/watchdog.c index e2bc8203176..04723a74627 100644 --- a/cpu/sh4/watchdog.c +++ b/cpu/sh4/watchdog.c @@ -32,11 +32,13 @@ static void cnt_write (unsigned char value){ while (csr_read() & (1 << 5)) { /* delay */ } - *((volatile unsigned short *)(WDT_BASE + 0x00)) = ((unsigned short) value) | 0x5A00; + *((volatile unsigned short *)(WDT_BASE + 0x00)) + = ((unsigned short) value) | 0x5A00; } static void csr_write (unsigned char value){ - *((volatile unsigned short *)(WDT_BASE + 0x04)) = ((unsigned short) value) | 0xA500; + *((volatile unsigned short *)(WDT_BASE + 0x04)) + = ((unsigned short) value) | 0xA500; } diff --git a/include/asm-sh/bitops.h b/include/asm-sh/bitops.h index 44dca9ff68a..529d0f2dbb8 100644 --- a/include/asm-sh/bitops.h +++ b/include/asm-sh/bitops.h @@ -1,13 +1,166 @@ -#ifndef __ASM_SH_BITOPS_H_ -#define __ASM_SH_BITOPS_H_ - -extern void set_bit(int nr, volatile void * a); -extern void clear_bit(int nr, volatile void * a); -extern int test_and_clear_bit(int nr, volatile void * a); -extern void change_bit(unsigned long nr, volatile void *addr); -extern int test_and_set_bit(int nr, volatile void * a); -extern int test_and_change_bit(int nr, volatile void * addr); -extern int test_bit(int nr, volatile void * a); -extern int ffs(int i); +#ifndef __ASM_SH_BITOPS_H +#define __ASM_SH_BITOPS_H +#ifdef __KERNEL__ +//#include +#include +/* For __swab32 */ +#include + +static inline void set_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a |= mask; + local_irq_restore(flags); +} + +/* + * clear_bit() doesn't provide any barrier for the compiler. + */ +#define smp_mb__before_clear_bit() barrier() +#define smp_mb__after_clear_bit() barrier() +static inline void clear_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a &= ~mask; + local_irq_restore(flags); +} + +static inline void change_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a ^= mask; + local_irq_restore(flags); +} + +static inline int test_and_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + retval = (mask & *a) != 0; + *a |= mask; + local_irq_restore(flags); + + return retval; +} + +static inline int test_and_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + retval = (mask & *a) != 0; + *a &= ~mask; + local_irq_restore(flags); + + return retval; +} + +static inline int test_and_change_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + retval = (mask & *a) != 0; + *a ^= mask; + local_irq_restore(flags); + + return retval; +} + +//#include + +static inline unsigned long ffz(unsigned long word) +{ + unsigned long result; + + __asm__("1:\n\t" + "shlr %1\n\t" + "bt/s 1b\n\t" + " add #1, %0" + : "=r" (result), "=r" (word) + : "0" (~0L), "1" (word) + : "t"); + return result; +} + +/** + * ffs - find first bit in word. + * @word: The word to search + * + * Undefined if no bit exists, so code should check against 0 first. + */ +static inline int ffs(int x) +{ + int r = 1; + + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) { + x >>= 1; + r += 1; + } + return r; +} + +#if 0 +#include +#include +#include +#include +#include +#include +#include +#include +#include #endif +#endif /* __KERNEL__ */ + +#endif /* __ASM_SH_BITOPS_H */ diff --git a/include/asm-sh/cpu_sh4.h b/include/asm-sh/cpu_sh4.h index e0275f32a05..dca61ca71bc 100644 --- a/include/asm-sh/cpu_sh4.h +++ b/include/asm-sh/cpu_sh4.h @@ -1,10 +1,48 @@ +/* + * (C) Copyright 2007 Nobuhiro Iwamatsu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + #ifndef _ASM_CPU_SH4_H_ #define _ASM_CPU_SH4_H_ + +/* cache control */ +#define CCR_CACHE_STOP 0x00000808 +#define CCR_CACHE_ENABLE 0x00000101 +#define CCR_CACHE_ICI 0x00000800 + +#define CACHE_OC_ADDRESS_ARRAY 0xf4000000 +#define CACHE_OC_WAY_SHIFT 14 +#define CACHE_OC_NUM_ENTRIES 512 +#define CACHE_OC_ENTRY_SHIFT 5 +//#define CACHE_OC_NUM_WAYS 1 + #if defined (CONFIG_CPU_SH7750) #include -#elif defined (CONFIG_CPU_SH7780) -#include +//#ifdef CONFIG_CPU_TYPE_R +//#define CCR_CACHE_INIT 0x8000090d /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */ +//#else +//#define CCR_CACHE_INIT 0x0000090b +//#endif +#elif defined (CONFIG_CPU_SH7722) +#include +//#define CCR_CACHE_INIT 0x0000090d #else #error "Unknown SH4 variant" #endif -#endif + +#endif /* _ASM_CPU_SH4_H_ */ diff --git a/include/asm-sh/cpu_sh7750.h b/include/asm-sh/cpu_sh7750.h index eb4f1affc22..9993e632031 100644 --- a/include/asm-sh/cpu_sh7750.h +++ b/include/asm-sh/cpu_sh7750.h @@ -1,13 +1,44 @@ +/* + * (C) Copyright 2007 Nobuhiro Iwamatsu + * + * SH7750/SH7750S/SH7750R/SH7751/SH7751R + * Internal I/O register + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + #ifndef _ASM_CPU_SH7750_H_ #define _ASM_CPU_SH7750_H_ -#define PTEH 0xFF000000 -#define PTEL 0xFF000004 -#define TTB 0xFF000008 -#define TEA 0xFF00000C -#define MMUCR 0xFF000010 -#define BASRA 0xFF000014 -#define BASRB 0xFF000018 +#ifdef CONFIG_CPU_TYPE_R +#define CACHE_OC_NUM_WAYS 2 +#define CCR_CACHE_INIT 0x8000090d /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */ +#else +#define CACHE_OC_NUM_WAYS 1 +#define CCR_CACHE_INIT 0x0000090b +#endif + +/* OCN */ +#define PTEH 0xFF000000 +#define PTEL 0xFF000004 +#define TTB 0xFF000008 +#define TEA 0xFF00000C +#define MMUCR 0xFF000010 +#define BASRA 0xFF000014 +#define BASRB 0xFF000018 #define CCR 0xFF00001C #define TRA 0xFF000020 #define EXPEVT 0xFF000024 @@ -15,6 +46,8 @@ #define PTEA 0xFF000034 #define QACR0 0xFF000038 #define QACR1 0xFF00003C + +/* UBC */ #define BARA 0xFF200000 #define BAMRA 0xFF200004 #define BBRA 0xFF200008 @@ -25,121 +58,139 @@ #define BDMRB 0xFF20001C #define BRCR 0xFF200020 +/* BSC */ #define BCR1 0xFF800000 -#define BCR2 0xFF800004 -#define BCR3 0xFF800050 -#define BCR4 0xFE0A00F0 -#define WCR1 0xFF800008 -#define WCR2 0xFF80000C -#define WCR3 0xFF800010 -#define MCR 0xFF800014 -#define PCR 0xFF800018 -#define RTCSR 0xFF80001C -#define RTCNT 0xFF800020 -#define RTCOR 0xFF800024 -#define RFCR 0xFF800028 -#define PCTRA 0xFF80002C -#define PDTRA 0xFF800030 -#define PCTRB 0xFF800040 -#define PDTRB 0xFF800044 -#define GPIOIC 0xFF800048 -#define SAR0 0xFFA00000 -#define DAR0 0xFFA00004 -#define DMATCR0 0xFFA00008 -#define CHCR0 0xFFA0000C -#define SAR1 0xFFA00010 -#define DAR1 0xFFA00014 -#define DMATCR1 0xFFA00018 -#define CHCR1 0xFFA0001C -#define SAR2 0xFFA00020 -#define DAR2 0xFFA00024 -#define DMATCR2 0xFFA00028 -#define CHCR2 0xFFA0002C -#define SAR3 0xFFA00030 -#define DAR3 0xFFA00034 -#define DMATCR3 0xFFA00038 -#define CHCR3 0xFFA0003C -#define DMAOR 0xFFA00040 -#define SAR4 0xFFA00050 -#define DAR4 0xFFA00054 -#define DMATCR4 0xFFA00058 +#define BCR2 0xFF800004 +#define BCR3 0xFF800050 +#define BCR4 0xFE0A00F0 +#define WCR1 0xFF800008 +#define WCR2 0xFF80000C +#define WCR3 0xFF800010 +#define MCR 0xFF800014 +#define PCR 0xFF800018 +#define RTCSR 0xFF80001C +#define RTCNT 0xFF800020 +#define RTCOR 0xFF800024 +#define RFCR 0xFF800028 +#define PCTRA 0xFF80002C +#define PDTRA 0xFF800030 +#define PCTRB 0xFF800040 +#define PDTRB 0xFF800044 +#define GPIOIC 0xFF800048 + +/* DMAC */ +#define SAR0 0xFFA00000 +#define DAR0 0xFFA00004 +#define DMATCR0 0xFFA00008 +#define CHCR0 0xFFA0000C +#define SAR1 0xFFA00010 +#define DAR1 0xFFA00014 +#define DMATCR1 0xFFA00018 +#define CHCR1 0xFFA0001C +#define SAR2 0xFFA00020 +#define DAR2 0xFFA00024 +#define DMATCR2 0xFFA00028 +#define CHCR2 0xFFA0002C +#define SAR3 0xFFA00030 +#define DAR3 0xFFA00034 +#define DMATCR3 0xFFA00038 +#define CHCR3 0xFFA0003C +#define DMAOR 0xFFA00040 +#define SAR4 0xFFA00050 +#define DAR4 0xFFA00054 +#define DMATCR4 0xFFA00058 + +/* CPG */ +#define FRQCR 0xFFC00000 +#define STBCR 0xFFC00004 +#define WTCNT 0xFFC00008 +#define WTCSR 0xFFC0000C +#define STBCR2 0xFFC00010 + +/* RTC */ +#define R64CNT 0xFFC80000 +#define RSECCNT 0xFFC80004 +#define RMINCNT 0xFFC80008 +#define RHRCNT 0xFFC8000C +#define RWKCNT 0xFFC80010 +#define RDAYCNT 0xFFC80014 +#define RMONCNT 0xFFC80018 +#define RYRCNT 0xFFC8001C +#define RSECAR 0xFFC80020 +#define RMINAR 0xFFC80024 +#define RHRAR 0xFFC80028 +#define RWKAR 0xFFC8002C +#define RDAYAR 0xFFC80030 +#define RMONAR 0xFFC80034 +#define RCR1 0xFFC80038 +#define RCR2 0xFFC8003C +#define RCR3 0xFFC80050 +#define RYRAR 0xFFC80054 -#define FRQCR 0xFFC00000 -#define STBCR 0xFFC00004 -#define WTCNT 0xFFC00008 -#define WTCSR 0xFFC0000C -#define STBCR2 0xFFC00010 -#define R64CNT 0xFFC80000 -#define RSECCNT 0xFFC80004 -#define RMINCNT 0xFFC80008 -#define RHRCNT 0xFFC8000C -#define RWKCNT 0xFFC80010 -#define RDAYCNT 0xFFC80014 -#define RMONCNT 0xFFC80018 -#define RYRCNT 0xFFC8001C -#define RSECAR 0xFFC80020 -#define RMINAR 0xFFC80024 -#define RHRAR 0xFFC80028 -#define RWKAR 0xFFC8002C -#define RDAYAR 0xFFC80030 -#define RMONAR 0xFFC80034 -#define RCR1 0xFFC80038 -#define RCR2 0xFFC8003C -#define RCR3 0xFFC80050 -#define RYRAR 0xFFC80054 -#define ICR 0xFFD00000 -#define IPRA 0xFFD00004 -#define IPRB 0xFFD00008 -#define IPRC 0xFFD0000C -#define IPRD 0xFFD00010 -#define INTPRI 0xFE080000 -#define INTREQ 0xFE080020 -#define INTMSK 0xFE080040 -#define INTMSKCL 0xFE080060 +/* ICR */ +#define ICR 0xFFD00000 +#define IPRA 0xFFD00004 +#define IPRB 0xFFD00008 +#define IPRC 0xFFD0000C +#define IPRD 0xFFD00010 +#define INTPRI 0xFE080000 +#define INTREQ 0xFE080020 +#define INTMSK 0xFE080040 +#define INTMSKCL 0xFE080060 + +/* CPG */ #define CLKSTP 0xFE0A0000 #define CLKSTPCLR 0xFE0A0008 -#define TSTR2 0xFE100004 -#define TCOR3 0xFE100008 -#define TCNT3 0xFE10000C -#define TCR3 0xFE100010 -#define TCOR4 0xFE100014 -#define TCNT4 0xFE100018 -#define TCR4 0xFE10001C -#define TOCR 0xFFD80000 -#define TSTR0 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 -#define TCOR1 0xFFD80014 -#define TCNT1 0xFFD80018 -#define TCR1 0xFFD8001C -#define TCOR2 0xFFD80020 -#define TCNT2 0xFFD80024 -#define TCR2 0xFFD80028 + +/* TMU */ +#define TSTR2 0xFE100004 +#define TCOR3 0xFE100008 +#define TCNT3 0xFE10000C +#define TCR3 0xFE100010 +#define TCOR4 0xFE100014 +#define TCNT4 0xFE100018 +#define TCR4 0xFE10001C +#define TOCR 0xFFD80000 +#define TSTR0 0xFFD80004 +#define TCOR0 0xFFD80008 +#define TCNT0 0xFFD8000C +#define TCR0 0xFFD80010 +#define TCOR1 0xFFD80014 +#define TCNT1 0xFFD80018 +#define TCR1 0xFFD8001C +#define TCOR2 0xFFD80020 +#define TCNT2 0xFFD80024 +#define TCR2 0xFFD80028 #define TCPR2 0xFFD8002C -#define SCSMR1 0xFFE00000 -#define SCBRR1 0xFFE00004 -#define SCSCR1 0xFFE00008 -#define SCTDR1 0xFFE0000C -#define SCSSR1 0xFFE00010 -#define SCRDR1 0xFFE00014 -#define SCSCMR1 0xFFE00018 -#define SCSPTR1 0xFFE0001C +#define TSTR TSTR0 + +/* SCI */ +#define SCSMR1 0xFFE00000 +#define SCBRR1 0xFFE00004 +#define SCSCR1 0xFFE00008 +#define SCTDR1 0xFFE0000C +#define SCSSR1 0xFFE00010 +#define SCRDR1 0xFFE00014 +#define SCSCMR1 0xFFE00018 +#define SCSPTR1 0xFFE0001C #define SCF0_BASE SCSMR1 + +/* SCIF */ #define SCSMR2 0xFFE80000 -#define SCBRR2 0xFFE80004 -#define SCSCR2 0xFFE80008 -#define SCFTDR2 0xFFE8000C -#define SCFSR2 0xFFE80010 -#define SCFRDR2 0xFFE80014 -#define SCFCR2 0xFFE80018 -#define SCFDR2 0xFFE8001C -#define SCSPTR2 0xFFE80020 -#define SCLSR2 0xFFE80024 +#define SCBRR2 0xFFE80004 +#define SCSCR2 0xFFE80008 +#define SCFTDR2 0xFFE8000C +#define SCFSR2 0xFFE80010 +#define SCFRDR2 0xFFE80014 +#define SCFCR2 0xFFE80018 +#define SCFDR2 0xFFE8001C +#define SCSPTR2 0xFFE80020 +#define SCLSR2 0xFFE80024 #define SCIF1_BASE SCSMR2 -#define SDIR 0xFFF00000 -#define SDDR 0xFFF00008 -#define SDINT 0xFFF00014 -#endif /* _ASM_CPU_SH7750_H_ */ +/* H-UDI */ +#define SDIR 0xFFF00000 +#define SDDR 0xFFF00008 +#define SDINT 0xFFF00014 +#endif /* _ASM_CPU_SH7750_H_ */ diff --git a/include/asm-sh/errno.h b/include/asm-sh/errno.h new file mode 100644 index 00000000000..0d2c618030f --- /dev/null +++ b/include/asm-sh/errno.h @@ -0,0 +1,156 @@ +/* + * U-boot - errno.h Error number defines + * + * Copyright (c) 2005-2007 Analog Devices Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _BLACKFIN_ERRNO_H +#define _BLACKFIN_ERRNO_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Arg list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + +#endif diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h index 70e60b170d0..03427ad33b5 100644 --- a/include/asm-sh/io.h +++ b/include/asm-sh/io.h @@ -91,23 +91,21 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen); * * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. */ -#ifdef __io -#define outb(v,p) __raw_writeb(v,__io(p)) -#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) -#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) - -#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) -#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) -#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) - -#define outsb(p,d,l) __raw_writesb(__io(p),d,l) -#define outsw(p,d,l) __raw_writesw(__io(p),d,l) -#define outsl(p,d,l) __raw_writesl(__io(p),d,l) - -#define insb(p,d,l) __raw_readsb(__io(p),d,l) -#define insw(p,d,l) __raw_readsw(__io(p),d,l) -#define insl(p,d,l) __raw_readsl(__io(p),d,l) -#endif +#define outb(v,p) __raw_writeb(v, p) +#define outw(v,p) __raw_writew(cpu_to_le16(v),p) +#define outl(v,p) __raw_writel(cpu_to_le32(v),p) + +#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; }) +#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; }) +#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; }) + +#define outsb(p,d,l) __raw_writesb(p,d,l) +#define outsw(p,d,l) __raw_writesw(p,d,l) +#define outsl(p,d,l) __raw_writesl(p,d,l) + +#define insb(p,d,l) __raw_readsb(p,d,l) +#define insw(p,d,l) __raw_readsw(p,d,l) +#define insl(p,d,l) __raw_readsl(p,d,l) #define outb_p(val,port) outb((val),(port)) #define outw_p(val,port) outw((val),(port)) @@ -174,8 +172,6 @@ extern void _memcpy_fromio(void *, unsigned long, size_t); extern void _memcpy_toio(unsigned long, const void *, size_t); extern void _memset_io(unsigned long, int, size_t); -extern void __readwrite_bug(const char *fn); - /* * If this architecture has PCI memory IO, then define the read/write * macros. These should only be used with the cookie passed from @@ -217,76 +213,19 @@ out: #elif !defined(readb) -#define readb(addr) (__readwrite_bug("readb"),0) -#define readw(addr) (__readwrite_bug("readw"),0) -#define readl(addr) (__readwrite_bug("readl"),0) -#define writeb(v,addr) __readwrite_bug("writeb") -#define writew(v,addr) __readwrite_bug("writew") -#define writel(v,addr) __readwrite_bug("writel") - -#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") +#define readb(addr) __raw_readb(addr) +#define readw(addr) __raw_readw(addr) +#define readl(addr) __raw_readl(addr) +#define writeb(v,addr) __raw_writeb(v, addr) +#define writew(v,addr) __raw_writew(v, addr) +#define writel(v,addr) __raw_writel(v, addr) #define check_signature(io,sig,len) (0) #endif /* __mem_pci */ -/* - * If this architecture has ISA IO, then define the isa_read/isa_write - * macros. - */ -#ifdef __mem_isa - -#define isa_readb(addr) __raw_readb(__mem_isa(addr)) -#define isa_readw(addr) __raw_readw(__mem_isa(addr)) -#define isa_readl(addr) __raw_readl(__mem_isa(addr)) -#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) -#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) -#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) -#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) -#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) -#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - eth_copy_and_sum((a),__mem_isa(b),(c),(d)) - -static inline int -isa_check_signature(unsigned long io_addr, const unsigned char *signature, - int length) -{ - int retval = 0; - do { - if (isa_readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#else /* __mem_isa */ - -#define isa_readb(addr) (__readwrite_bug("isa_readb"),0) -#define isa_readw(addr) (__readwrite_bug("isa_readw"),0) -#define isa_readl(addr) (__readwrite_bug("isa_readl"),0) -#define isa_writeb(val,addr) __readwrite_bug("isa_writeb") -#define isa_writew(val,addr) __readwrite_bug("isa_writew") -#define isa_writel(val,addr) __readwrite_bug("isa_writel") -#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io") -#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio") -#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio") - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - __readwrite_bug("isa_eth_io_copy_and_sum") - -#define isa_check_signature(io,sig,len) (0) - static inline void sync(void) { } - -#endif /* __mem_isa */ #endif /* __KERNEL__ */ #endif /* __ASM_SH_IO_H */ diff --git a/include/asm-sh/irqflags.h b/include/asm-sh/irqflags.h new file mode 100644 index 00000000000..830e5486acf --- /dev/null +++ b/include/asm-sh/irqflags.h @@ -0,0 +1,126 @@ +#ifndef __ASM_SH_IRQFLAGS_H +#define __ASM_SH_IRQFLAGS_H + +static inline void raw_local_irq_enable(void) +{ + unsigned long __dummy0, __dummy1; + + __asm__ __volatile__ ( + "stc sr, %0\n\t" + "and %1, %0\n\t" +#ifdef CONFIG_CPU_HAS_SR_RB + "stc r6_bank, %1\n\t" + "or %1, %0\n\t" +#endif + "ldc %0, sr\n\t" + : "=&r" (__dummy0), "=r" (__dummy1) + : "1" (~0x000000f0) + : "memory" + ); +} + +static inline void raw_local_irq_disable(void) +{ + unsigned long flags; + + __asm__ __volatile__ ( + "stc sr, %0\n\t" + "or #0xf0, %0\n\t" + "ldc %0, sr\n\t" + : "=&z" (flags) + : /* no inputs */ + : "memory" + ); +} + +static inline void set_bl_bit(void) +{ + unsigned long __dummy0, __dummy1; + + __asm__ __volatile__ ( + "stc sr, %0\n\t" + "or %2, %0\n\t" + "and %3, %0\n\t" + "ldc %0, sr\n\t" + : "=&r" (__dummy0), "=r" (__dummy1) + : "r" (0x10000000), "r" (0xffffff0f) + : "memory" + ); +} + +static inline void clear_bl_bit(void) +{ + unsigned long __dummy0, __dummy1; + + __asm__ __volatile__ ( + "stc sr, %0\n\t" + "and %2, %0\n\t" + "ldc %0, sr\n\t" + : "=&r" (__dummy0), "=r" (__dummy1) + : "1" (~0x10000000) + : "memory" + ); +} + +static inline unsigned long __raw_local_save_flags(void) +{ + unsigned long flags; + + __asm__ __volatile__ ( + "stc sr, %0\n\t" + "and #0xf0, %0\n\t" + : "=&z" (flags) + : /* no inputs */ + : "memory" + ); + + return flags; +} + +#define raw_local_save_flags(flags) \ + do { (flags) = __raw_local_save_flags(); } while (0) + +static inline int raw_irqs_disabled_flags(unsigned long flags) +{ + return (flags != 0); +} + +static inline int raw_irqs_disabled(void) +{ + unsigned long flags = __raw_local_save_flags(); + + return raw_irqs_disabled_flags(flags); +} + +static inline unsigned long __raw_local_irq_save(void) +{ + unsigned long flags, __dummy; + + __asm__ __volatile__ ( + "stc sr, %1\n\t" + "mov %1, %0\n\t" + "or #0xf0, %0\n\t" + "ldc %0, sr\n\t" + "mov %1, %0\n\t" + "and #0xf0, %0\n\t" + : "=&z" (flags), "=&r" (__dummy) + : /* no inputs */ + : "memory" + ); + + return flags; +} + +#define raw_local_irq_save(flags) \ + do { (flags) = __raw_local_irq_save(); } while (0) + +#define local_irq_save raw_local_irq_save + +static inline void raw_local_irq_restore(unsigned long flags) +{ + if ((flags & 0xf0) != 0xf0) + raw_local_irq_enable(); +} +#define local_irq_restore raw_local_irq_restore + +#endif /* __ASM_SH_IRQFLAGS_H */ diff --git a/include/asm-sh/string.h b/include/asm-sh/string.h index a78ef818bc4..27d981b79af 100644 --- a/include/asm-sh/string.h +++ b/include/asm-sh/string.h @@ -8,6 +8,8 @@ * from linux kernel code. */ +#ifdef __KERNEL__ /* only set these up for kernel code */ + #define __HAVE_ARCH_STRCPY static inline char *strcpy(char *__dest, const char *__src) { @@ -129,4 +131,32 @@ extern size_t strlen(const char *); /* arch/sh/lib/strcasecmp.c */ extern int strcasecmp(const char *, const char *); +#else /* KERNEL */ + +/* + * let user libraries deal with these, + * IMHO the kernel has no place defining these functions for user apps + */ + +#define __HAVE_ARCH_STRCPY 1 +#define __HAVE_ARCH_STRNCPY 1 +#define __HAVE_ARCH_STRCAT 1 +#define __HAVE_ARCH_STRNCAT 1 +#define __HAVE_ARCH_STRCMP 1 +#define __HAVE_ARCH_STRNCMP 1 +#define __HAVE_ARCH_STRNICMP 1 +#define __HAVE_ARCH_STRCHR 1 +#define __HAVE_ARCH_STRRCHR 1 +#define __HAVE_ARCH_STRSTR 1 +#define __HAVE_ARCH_STRLEN 1 +#define __HAVE_ARCH_STRNLEN 1 +#define __HAVE_ARCH_MEMSET 1 +#define __HAVE_ARCH_MEMCPY 1 +#define __HAVE_ARCH_MEMMOVE 1 +#define __HAVE_ARCH_MEMSCAN 1 +#define __HAVE_ARCH_MEMCMP 1 +#define __HAVE_ARCH_MEMCHR 1 +#define __HAVE_ARCH_STRTOK 1 + +#endif /* KERNEL */ #endif /* __ASM_SH_STRING_H */ diff --git a/lib_sh/board.c b/lib_sh/board.c index c3f846257ff..c63ac0313a9 100644 --- a/lib_sh/board.c +++ b/lib_sh/board.c @@ -65,6 +65,61 @@ void *sbrk (ptrdiff_t increment) return (void *) old; } +static int sh_flash_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_flashsize = flash_init(); + printf("FLASH: %dMB\n", gd->bd->bi_flashsize / (1024*1024)); + + return 0; +} + +#if defined(CONFIG_CMD_NAND) +void nand_init (void); +static int sh_nand_init(void) +{ + printf("NAND: "); + nand_init(); /* go init the NAND */ + return 0; +} +#endif /* CONFIG_CMD_NAND */ + +#if defined(CONFIG_CMD_IDE) +#include +static int sh_marubun_init(void) +{ + puts ("IDE: "); + ide_init(); + return 0; +} +#endif /* (CONFIG_CMD_IDE) */ + +static int sh_mem_env_init(void) +{ + mem_malloc_init(); + malloc_bin_reloc(); + env_relocate(); + jumptable_init(); + return 0; +} + +static int sh_net_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + char *s, *e; + int i; + + gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr"); + s = getenv("ethaddr"); + for (i = 0; i < 6; ++i) { + gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0; + if (s) s = (*e) ? e + 1 : e; + } + + return 0; +} + typedef int (init_fnc_t) (void); init_fnc_t *init_sequence[] = @@ -74,12 +129,27 @@ init_fnc_t *init_sequence[] = interrupt_init, /* set up exceptions */ env_init, /* event init */ serial_init, /* SCIF init */ - watchdog_init, + watchdog_init, /* watchdog init */ console_init_f, display_options, checkcpu, - checkboard, + checkboard, /* Check support board */ dram_init, /* SDRAM init */ + timer_init, /* SuperH Timer (TCNT0 only) init */ + sh_flash_init, /* Flash memory(NOR) init*/ + sh_mem_env_init, +#if defined(CONFIG_CMD_NAND) + sh_nand_init, /* Flash memory (NAND) init */ +#endif + devices_init, + console_init_r, + interrupt_init, +#ifdef BOARD_LATE_INIT + board_late_init, +#endif +#if defined(CONFIG_CMD_NET) + sh_net_init, /* SH specific eth init */ +#endif NULL /* Terminate this list */ }; @@ -89,14 +159,14 @@ void sh_generic_init (void) bd_t *bd; init_fnc_t **init_fnc_ptr; - char *s, *e; + char *s; int i; memset (gd, 0, CFG_GBL_DATA_SIZE); gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ - gd->bd = (bd_t *) (gd + 1); /* At end of global data */ + gd->bd = (bd_t *) (gd + 1); /* At end of global data */ gd->baudrate = CONFIG_BAUDRATE; gd->cpu_clk = CONFIG_SYS_CLK_FREQ; @@ -111,53 +181,30 @@ void sh_generic_init (void) #endif bd->bi_baudrate = CONFIG_BAUDRATE; - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr , i++) { if ((*init_fnc_ptr) () != 0) { hang(); } } - - timer_init(); - - /* flash_init need timer_init().(TMU) */ - bd->bi_flashsize = flash_init(); - printf("FLASH: %dMB\n", bd->bi_flashsize / (1024*1024)); - - mem_malloc_init(); - malloc_bin_reloc(); - env_relocate(); -#if (CONFIG_COMMANDS & CFG_CMD_NET) - bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); - s = getenv ("ethaddr"); - for (i = 0; i < 6; ++i) { - bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) s = (*e) ? e + 1 : e; - } -#endif - devices_init(); - jumptable_init(); - console_init_r(); - interrupt_init(); -#ifdef BOARD_LATE_INIT - board_late_init (); -#endif -#if (CONFIG_COMMANDS & CFG_CMD_NET) -#if defined(CONFIG_NET_MULTI) +#if defined(CONFIG_CMD_NET) puts ("Net: "); -#endif eth_initialize(gd->bd); -#endif + + if ((s = getenv ("bootfile")) != NULL) { + copy_filename (BootFile, s, sizeof (BootFile)); + } +#endif /* CONFIG_CMD_NET */ + while (1) { main_loop(); } } - /***********************************************************************/ void hang (void) { - puts ("Board ERROR \n"); + puts ("Board ERROR\n"); for (;;); } diff --git a/lib_sh/sh_linux.c b/lib_sh/sh_linux.c index 7237ab3382a..acd47b5db70 100644 --- a/lib_sh/sh_linux.c +++ b/lib_sh/sh_linux.c @@ -69,6 +69,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], /* Setup parameters */ memset(PARAM, 0, 0x1000); /* Clear zero page */ strcpy(COMMAND_LINE, bootargs); + kernel(); } diff --git a/lib_sh/time.c b/lib_sh/time.c index 36201368204..3d33918f28f 100644 --- a/lib_sh/time.c +++ b/lib_sh/time.c @@ -73,4 +73,3 @@ unsigned long get_tbclk (void) { return CFG_HZ; } - diff --git a/sh_config.mk b/sh_config.mk new file mode 100644 index 00000000000..49d50f7ebd9 --- /dev/null +++ b/sh_config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__ -- cgit v1.3.1 From c7c6da23028f146d912514b95aefa3da7cf37699 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 3 Oct 2007 07:34:10 +0200 Subject: ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (1) This patch is the first patch of a series to make the 440SPe PCIe code usable on different 4xx PPC platforms. In preperation for the new 405EX which is also equipped with PCIe interfaces. (1) This patch renames the files from 440spe_pcie to 4xx_pcie Signed-off-by: Stefan Roese --- board/amcc/katmai/katmai.c | 9 +- board/amcc/yucca/yucca.c | 6 +- cpu/ppc4xx/440spe_pcie.c | 1067 -------------------------------------------- cpu/ppc4xx/440spe_pcie.h | 174 -------- cpu/ppc4xx/4xx_pcie.c | 1067 ++++++++++++++++++++++++++++++++++++++++++++ cpu/ppc4xx/Makefile | 5 +- include/asm-ppc/4xx_pcie.h | 174 ++++++++ 7 files changed, 1250 insertions(+), 1252 deletions(-) delete mode 100644 cpu/ppc4xx/440spe_pcie.c delete mode 100644 cpu/ppc4xx/440spe_pcie.h create mode 100644 cpu/ppc4xx/4xx_pcie.c create mode 100644 include/asm-ppc/4xx_pcie.h (limited to 'cpu') diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index a49066fcc94..0c8e6cb701e 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -24,12 +24,11 @@ #include #include -#include #include -#include -#include - -#include "../cpu/ppc4xx/440spe_pcie.h" +#include +#include +#include +#include #undef PCIE_ENDPOINT /* #define PCIE_ENDPOINT 1 */ diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index d7cc384ba0b..17c3ba0f17d 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -27,12 +27,12 @@ #include #include -#include #include -#include +#include +#include +#include #include "yucca.h" -#include "../cpu/ppc4xx/440spe_pcie.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c deleted file mode 100644 index 3eac0ae62cd..00000000000 --- a/cpu/ppc4xx/440spe_pcie.c +++ /dev/null @@ -1,1067 +0,0 @@ -/* - * (C) Copyright 2006 - 2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (c) 2005 Cisco Systems. All rights reserved. - * Roland Dreier - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include - -#if defined(CONFIG_440SPE) && defined(CONFIG_PCI) - -#include "440spe_pcie.h" - -enum { - PTYPE_ENDPOINT = 0x0, - PTYPE_LEGACY_ENDPOINT = 0x1, - PTYPE_ROOT_PORT = 0x4, - - LNKW_X1 = 0x1, - LNKW_X4 = 0x4, - LNKW_X8 = 0x8 -}; - -static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn) -{ - u8 *base = (u8*)hose->cfg_data; - - /* use local configuration space for the first bus */ - if (PCI_BUS(devfn) == 0) { - if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE) - base = (u8*)CFG_PCIE0_XCFGBASE; - if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE) - base = (u8*)CFG_PCIE1_XCFGBASE; - if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE) - base = (u8*)CFG_PCIE2_XCFGBASE; - } - - return base; -} - -static void pcie_dmer_disable(void) -{ - mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE), - mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA); - mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE), - mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA); - mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE), - mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA); -} - -static void pcie_dmer_enable(void) -{ - mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE), - mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA); - mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE), - mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA); - mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE), - mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA); -} - -static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, - int offset, int len, u32 *val) { - - u8 *address; - *val = 0; - - /* - * Bus numbers are relative to hose->first_busno - */ - devfn -= PCI_BDF(hose->first_busno, 0, 0); - - /* - * NOTICE: configuration space ranges are currenlty mapped only for - * the first 16 buses, so such limit must be imposed. In case more - * buses are required the TLB settings in board/amcc//init.S - * need to be altered accordingly (one bus takes 1 MB of memory space). - */ - if (PCI_BUS(devfn) >= 16) - return 0; - - /* - * Only single device/single function is supported for the primary and - * secondary buses of the 440SPe host bridge. - */ - if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && - ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) - return 0; - - address = pcie_get_base(hose, devfn); - offset += devfn << 4; - - /* - * Reading from configuration space of non-existing device can - * generate transaction errors. For the read duration we suppress - * assertion of machine check exceptions to avoid those. - */ - pcie_dmer_disable (); - - switch (len) { - case 1: - *val = in_8(hose->cfg_data + offset); - break; - case 2: - *val = in_le16((u16 *)(hose->cfg_data + offset)); - break; - default: - *val = in_le32((u32*)(hose->cfg_data + offset)); - break; - } - - pcie_dmer_enable (); - - return 0; -} - -static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, - int offset, int len, u32 val) { - - u8 *address; - - /* - * Bus numbers are relative to hose->first_busno - */ - devfn -= PCI_BDF(hose->first_busno, 0, 0); - - /* - * Same constraints as in pcie_read_config(). - */ - if (PCI_BUS(devfn) >= 16) - return 0; - - if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && - ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) - return 0; - - address = pcie_get_base(hose, devfn); - offset += devfn << 4; - - /* - * Suppress MCK exceptions, similar to pcie_read_config() - */ - pcie_dmer_disable (); - - switch (len) { - case 1: - out_8(hose->cfg_data + offset, val); - break; - case 2: - out_le16((u16 *)(hose->cfg_data + offset), val); - break; - default: - out_le32((u32 *)(hose->cfg_data + offset), val); - break; - } - - pcie_dmer_enable (); - - return 0; -} - -int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val) -{ - u32 v; - int rv; - - rv = pcie_read_config(hose, dev, offset, 1, &v); - *val = (u8)v; - return rv; -} - -int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val) -{ - u32 v; - int rv; - - rv = pcie_read_config(hose, dev, offset, 2, &v); - *val = (u16)v; - return rv; -} - -int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val) -{ - u32 v; - int rv; - - rv = pcie_read_config(hose, dev, offset, 3, &v); - *val = (u32)v; - return rv; -} - -int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val) -{ - return pcie_write_config(hose,(u32)dev,offset,1,val); -} - -int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val) -{ - return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val); -} - -int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val) -{ - return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val); -} - -static void ppc440spe_setup_utl(u32 port) { - - volatile void *utl_base = NULL; - - /* - * Map UTL registers - */ - switch (port) { - case 0: - mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c); - mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000); - mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); - mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800); - break; - - case 1: - mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c); - mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000); - mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); - mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800); - break; - - case 2: - mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c); - mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000); - mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001); - mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800); - break; - } - utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port); - - /* - * Set buffer allocations and then assert VRB and TXE. - */ - out_be32(utl_base + PEUTL_OUTTR, 0x08000000); - out_be32(utl_base + PEUTL_INTR, 0x02000000); - out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000); - out_be32(utl_base + PEUTL_PBBSZ, 0x53000000); - out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000); - out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000); - out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); - out_be32(utl_base + PEUTL_PCTL, 0x80800066); -} - -static int check_error(void) -{ - u32 valPE0, valPE1, valPE2; - int err = 0; - - /* SDR0_PEGPLLLCT1 reset */ - if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) { - printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0); - } - - valPE0 = SDR_READ(PESDR0_RCSSET); - valPE1 = SDR_READ(PESDR1_RCSSET); - valPE2 = SDR_READ(PESDR2_RCSSET); - - /* SDR0_PExRCSSET rstgu */ - if (!(valPE0 & 0x01000000) || - !(valPE1 & 0x01000000) || - !(valPE2 & 0x01000000)) { - printf("PCIE: SDR0_PExRCSSET rstgu error\n"); - err = -1; - } - - /* SDR0_PExRCSSET rstdl */ - if (!(valPE0 & 0x00010000) || - !(valPE1 & 0x00010000) || - !(valPE2 & 0x00010000)) { - printf("PCIE: SDR0_PExRCSSET rstdl error\n"); - err = -1; - } - - /* SDR0_PExRCSSET rstpyn */ - if ((valPE0 & 0x00001000) || - (valPE1 & 0x00001000) || - (valPE2 & 0x00001000)) { - printf("PCIE: SDR0_PExRCSSET rstpyn error\n"); - err = -1; - } - - /* SDR0_PExRCSSET hldplb */ - if ((valPE0 & 0x10000000) || - (valPE1 & 0x10000000) || - (valPE2 & 0x10000000)) { - printf("PCIE: SDR0_PExRCSSET hldplb error\n"); - err = -1; - } - - /* SDR0_PExRCSSET rdy */ - if ((valPE0 & 0x00100000) || - (valPE1 & 0x00100000) || - (valPE2 & 0x00100000)) { - printf("PCIE: SDR0_PExRCSSET rdy error\n"); - err = -1; - } - - /* SDR0_PExRCSSET shutdown */ - if ((valPE0 & 0x00000100) || - (valPE1 & 0x00000100) || - (valPE2 & 0x00000100)) { - printf("PCIE: SDR0_PExRCSSET shutdown error\n"); - err = -1; - } - return err; -} - -/* - * Initialize PCI Express core - */ -int ppc440spe_init_pcie(void) -{ - int time_out = 20; - - /* Set PLL clock receiver to LVPECL */ - SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28); - - if (check_error()) - return -1; - - if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) - { - printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n", - SDR_READ(PESDR0_PLLLCT2)); - return -1; - } - /* De-assert reset of PCIe PLL, wait for lock */ - SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24)); - udelay(3); - - while (time_out) { - if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) { - time_out--; - udelay(1); - } else - break; - } - if (!time_out) { - printf("PCIE: VCO output not locked\n"); - return -1; - } - return 0; -} - -/* - * Yucca board as End point and root point setup - * and - * testing inbound and out bound windows - * - * YUCCA board can be plugged into another yucca board or you can get PCI-E - * cable which can be used to setup loop back from one port to another port. - * Please rememeber that unless there is a endpoint plugged in to root port it - * will not initialize. It is the same in case of endpoint , unless there is - * root port attached it will not initialize. - * - * In this release of software all the PCI-E ports are configured as either - * endpoint or rootpoint.In future we will have support for selective ports - * setup as endpoint and root point in single board. - * - * Once your board came up as root point , you can verify by reading - * /proc/bus/pci/devices. Where you can see the configuration registers - * of end point device attached to the port. - * - * Enpoint cofiguration can be verified by connecting Yucca board to any - * host or another yucca board. Then try to scan the device. In case of - * linux use "lspci" or appripriate os command. - * - * How do I verify the inbound and out bound windows ?(yucca to yucca) - * in this configuration inbound and outbound windows are setup to access - * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address - * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000, - * This is waere your POM(PLB out bound memory window) mapped. then - * read the data from other yucca board's u-boot prompt at address - * 0x9000 0000(SRAM). Data should match. - * In case of inbound , write data to u-boot command prompt at 0xb000 0000 - * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check - * data at 0x9000 0000(SRAM).Data should match. - */ -int ppc440spe_init_pcie_rootport(int port) -{ - static int core_init; - volatile u32 val = 0; - int attempts; - - if (!core_init) { - ++core_init; - if (ppc440spe_init_pcie()) - return -1; - } - - /* - * Initialize various parts of the PCI Express core for our port: - * - * - Set as a root port and enable max width - * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). - * - Set up UTL configuration. - * - Increase SERDES drive strength to levels suggested by AMCC. - * - De-assert RSTPYN, RSTDL and RSTGU. - * - * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with - * default setting 0x11310000. The register has new fields, - * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core - * hang. - */ - switch (port) { - case 0: - SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12); - - SDR_WRITE(PESDR0_UTLSET1, 0x21222222); - if (!ppc440spe_revB()) - SDR_WRITE(PESDR0_UTLSET2, 0x11000000); - SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); - SDR_WRITE(PESDR0_RCSSET, - (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; - - case 1: - SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); - SDR_WRITE(PESDR1_UTLSET1, 0x21222222); - if (!ppc440spe_revB()) - SDR_WRITE(PESDR1_UTLSET2, 0x11000000); - SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000); - SDR_WRITE(PESDR1_RCSSET, - (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; - - case 2: - SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); - SDR_WRITE(PESDR2_UTLSET1, 0x21222222); - if (!ppc440spe_revB()) - SDR_WRITE(PESDR2_UTLSET2, 0x11000000); - SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000); - SDR_WRITE(PESDR2_RCSSET, - (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; - } - /* - * Notice: the following delay has critical impact on device - * initialization - if too short (<50ms) the link doesn't get up. - */ - mdelay(100); - - switch (port) { - case 0: - val = SDR_READ(PESDR0_RCSSTS); - break; - case 1: - val = SDR_READ(PESDR1_RCSSTS); - break; - case 2: - val = SDR_READ(PESDR2_RCSSTS); - break; - } - - if (val & (1 << 20)) { - printf("PCIE%d: PGRST failed %08x\n", port, val); - return -1; - } - - /* - * Verify link is up - */ - val = 0; - switch (port) { - case 0: - val = SDR_READ(PESDR0_LOOP); - break; - case 1: - val = SDR_READ(PESDR1_LOOP); - break; - case 2: - val = SDR_READ(PESDR2_LOOP); - break; - } - if (!(val & 0x00001000)) { - printf("PCIE%d: link is not up.\n", port); - return -1; - } - - /* - * Setup UTL registers - but only on revA! - * We use default settings for revB chip. - */ - if (!ppc440spe_revB()) - ppc440spe_setup_utl(port); - - /* - * We map PCI Express configuration access into the 512MB regions - * - * NOTICE: revB is very strict about PLB real addressess and ranges to - * be mapped for config space; it seems to only work with d_nnnn_nnnn - * range (hangs the core upon config transaction attempts when set - * otherwise) while revA uses c_nnnn_nnnn. - * - * For revA: - * PCIE0: 0xc_4000_0000 - * PCIE1: 0xc_8000_0000 - * PCIE2: 0xc_c000_0000 - * - * For revB: - * PCIE0: 0xd_0000_0000 - * PCIE1: 0xd_2000_0000 - * PCIE2: 0xd_4000_0000 - */ - - switch (port) { - case 0: - if (ppc440spe_revB()) { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000); - } else { - /* revA */ - mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000); - } - mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ - break; - - case 1: - if (ppc440spe_revB()) { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000); - } else { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000); - } - mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ - break; - - case 2: - if (ppc440spe_revB()) { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000); - } else { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000); - } - mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ - break; - } - - /* - * Check for VC0 active and assert RDY. - */ - attempts = 10; - switch (port) { - case 0: - while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) { - if (!(attempts--)) { - printf("PCIE0: VC0 not active\n"); - return -1; - } - mdelay(1000); - } - SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20); - break; - case 1: - while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) { - if (!(attempts--)) { - printf("PCIE1: VC0 not active\n"); - return -1; - } - mdelay(1000); - } - - SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20); - break; - case 2: - while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) { - if (!(attempts--)) { - printf("PCIE2: VC0 not active\n"); - return -1; - } - mdelay(1000); - } - - SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20); - break; - } - mdelay(100); - - return 0; -} - -int ppc440spe_init_pcie_endport(int port) -{ - static int core_init; - volatile u32 val = 0; - int attempts; - - if (!core_init) { - ++core_init; - if (ppc440spe_init_pcie()) - return -1; - } - - /* - * Initialize various parts of the PCI Express core for our port: - * - * - Set as a end port and enable max width - * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). - * - Set up UTL configuration. - * - Increase SERDES drive strength to levels suggested by AMCC. - * - De-assert RSTPYN, RSTDL and RSTGU. - * - * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with - * default setting 0x11310000. The register has new fields, - * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core - * hang. - */ - switch (port) { - case 0: - SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X8 << 12); - - SDR_WRITE(PESDR0_UTLSET1, 0x20222222); - if (!ppc440spe_revB()) - SDR_WRITE(PESDR0_UTLSET2, 0x11000000); - SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); - SDR_WRITE(PESDR0_RCSSET, - (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; - - case 1: - SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12); - SDR_WRITE(PESDR1_UTLSET1, 0x20222222); - if (!ppc440spe_revB()) - SDR_WRITE(PESDR1_UTLSET2, 0x11000000); - SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000); - SDR_WRITE(PESDR1_RCSSET, - (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; - - case 2: - SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12); - SDR_WRITE(PESDR2_UTLSET1, 0x20222222); - if (!ppc440spe_revB()) - SDR_WRITE(PESDR2_UTLSET2, 0x11000000); - SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000); - SDR_WRITE(PESDR2_RCSSET, - (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; - } - /* - * Notice: the following delay has critical impact on device - * initialization - if too short (<50ms) the link doesn't get up. - */ - mdelay(100); - - switch (port) { - case 0: val = SDR_READ(PESDR0_RCSSTS); break; - case 1: val = SDR_READ(PESDR1_RCSSTS); break; - case 2: val = SDR_READ(PESDR2_RCSSTS); break; - } - - if (val & (1 << 20)) { - printf("PCIE%d: PGRST failed %08x\n", port, val); - return -1; - } - - /* - * Verify link is up - */ - val = 0; - switch (port) - { - case 0: - val = SDR_READ(PESDR0_LOOP); - break; - case 1: - val = SDR_READ(PESDR1_LOOP); - break; - case 2: - val = SDR_READ(PESDR2_LOOP); - break; - } - if (!(val & 0x00001000)) { - printf("PCIE%d: link is not up.\n", port); - return -1; - } - - /* - * Setup UTL registers - but only on revA! - * We use default settings for revB chip. - */ - if (!ppc440spe_revB()) - ppc440spe_setup_utl(port); - - /* - * We map PCI Express configuration access into the 512MB regions - * - * NOTICE: revB is very strict about PLB real addressess and ranges to - * be mapped for config space; it seems to only work with d_nnnn_nnnn - * range (hangs the core upon config transaction attempts when set - * otherwise) while revA uses c_nnnn_nnnn. - * - * For revA: - * PCIE0: 0xc_4000_0000 - * PCIE1: 0xc_8000_0000 - * PCIE2: 0xc_c000_0000 - * - * For revB: - * PCIE0: 0xd_0000_0000 - * PCIE1: 0xd_2000_0000 - * PCIE2: 0xd_4000_0000 - */ - switch (port) { - case 0: - if (ppc440spe_revB()) { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000); - } else { - /* revA */ - mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000); - } - mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ - break; - - case 1: - if (ppc440spe_revB()) { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000); - } else { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000); - } - mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ - break; - - case 2: - if (ppc440spe_revB()) { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000); - } else { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000); - } - mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ - break; - } - - /* - * Check for VC0 active and assert RDY. - */ - attempts = 10; - switch (port) { - case 0: - while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) { - if (!(attempts--)) { - printf("PCIE0: VC0 not active\n"); - return -1; - } - mdelay(1000); - } - SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20); - break; - case 1: - while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) { - if (!(attempts--)) { - printf("PCIE1: VC0 not active\n"); - return -1; - } - mdelay(1000); - } - - SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20); - break; - case 2: - while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) { - if (!(attempts--)) { - printf("PCIE2: VC0 not active\n"); - return -1; - } - mdelay(1000); - } - - SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20); - break; - } - mdelay(100); - - return 0; -} - -void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) -{ - volatile void *mbase = NULL; - volatile void *rmbase = NULL; - - pci_set_ops(hose, - pcie_read_config_byte, - pcie_read_config_word, - pcie_read_config_dword, - pcie_write_config_byte, - pcie_write_config_word, - pcie_write_config_dword); - - switch (port) { - case 0: - mbase = (u32 *)CFG_PCIE0_XCFGBASE; - rmbase = (u32 *)CFG_PCIE0_CFGBASE; - hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE; - break; - case 1: - mbase = (u32 *)CFG_PCIE1_XCFGBASE; - rmbase = (u32 *)CFG_PCIE1_CFGBASE; - hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; - break; - case 2: - mbase = (u32 *)CFG_PCIE2_XCFGBASE; - rmbase = (u32 *)CFG_PCIE2_CFGBASE; - hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; - break; - } - - /* - * Set bus numbers on our root port - */ - out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); - out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); - out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); - - /* - * Set up outbound translation to hose->mem_space from PLB - * addresses at an offset of 0xd_0000_0000. We set the low - * bits of the mask to 11 to turn off splitting into 8 - * subregions and to enable the outbound translation. - */ - out_le32(mbase + PECFG_POM0LAH, 0x00000000); - out_le32(mbase + PECFG_POM0LAL, 0x00000000); - - switch (port) { - case 0: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE); - mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); - mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), - ~(CFG_PCIE_MEMSIZE - 1) | 3); - break; - case 1: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE)); - mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); - mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), - ~(CFG_PCIE_MEMSIZE - 1) | 3); - break; - case 2: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE)); - mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); - mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), - ~(CFG_PCIE_MEMSIZE - 1) | 3); - break; - } - - /* Set up 16GB inbound memory window at 0 */ - out_le32(mbase + PCI_BASE_ADDRESS_0, 0); - out_le32(mbase + PCI_BASE_ADDRESS_1, 0); - out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); - out_le32(mbase + PECFG_BAR0LMPA, 0); - - out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); - out_le32(mbase + PECFG_PIM01SAL, 0x00000000); - out_le32(mbase + PECFG_PIM0LAL, 0); - out_le32(mbase + PECFG_PIM0LAH, 0); - out_le32(mbase + PECFG_PIM1LAL, 0x00000000); - out_le32(mbase + PECFG_PIM1LAH, 0x00000004); - out_le32(mbase + PECFG_PIMEN, 0x1); - - /* Enable I/O, Mem, and Busmaster cycles */ - out_le16((u16 *)(mbase + PCI_COMMAND), - in_le16((u16 *)(mbase + PCI_COMMAND)) | - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - printf("PCIE:%d successfully set as rootpoint\n",port); - - /* Set Device and Vendor Id */ - switch (port) { - case 0: - out_le16(mbase + 0x200, 0xaaa0); - out_le16(mbase + 0x202, 0xbed0); - break; - case 1: - out_le16(mbase + 0x200, 0xaaa1); - out_le16(mbase + 0x202, 0xbed1); - break; - case 2: - out_le16(mbase + 0x200, 0xaaa2); - out_le16(mbase + 0x202, 0xbed2); - break; - default: - out_le16(mbase + 0x200, 0xaaa3); - out_le16(mbase + 0x202, 0xbed3); - } - - /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ - out_le32(mbase + 0x208, 0x06040001); - -} - -int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port) -{ - volatile void *mbase = NULL; - int attempts = 0; - - pci_set_ops(hose, - pcie_read_config_byte, - pcie_read_config_word, - pcie_read_config_dword, - pcie_write_config_byte, - pcie_write_config_word, - pcie_write_config_dword); - - switch (port) { - case 0: - mbase = (u32 *)CFG_PCIE0_XCFGBASE; - hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE; - break; - case 1: - mbase = (u32 *)CFG_PCIE1_XCFGBASE; - hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; - break; - case 2: - mbase = (u32 *)CFG_PCIE2_XCFGBASE; - hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; - break; - } - - /* - * Set up outbound translation to hose->mem_space from PLB - * addresses at an offset of 0xd_0000_0000. We set the low - * bits of the mask to 11 to turn off splitting into 8 - * subregions and to enable the outbound translation. - */ - out_le32(mbase + PECFG_POM0LAH, 0x00001ff8); - out_le32(mbase + PECFG_POM0LAL, 0x00001000); - - switch (port) { - case 0: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE); - mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); - mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), - ~(CFG_PCIE_MEMSIZE - 1) | 3); - break; - case 1: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE)); - mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); - mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), - ~(CFG_PCIE_MEMSIZE - 1) | 3); - break; - case 2: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE)); - mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); - mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), - ~(CFG_PCIE_MEMSIZE - 1) | 3); - break; - } - - /* Set up 16GB inbound memory window at 0 */ - out_le32(mbase + PCI_BASE_ADDRESS_0, 0); - out_le32(mbase + PCI_BASE_ADDRESS_1, 0); - out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); - out_le32(mbase + PECFG_BAR0LMPA, 0); - out_le32(mbase + PECFG_PIM0LAL, 0x00000000); - out_le32(mbase + PECFG_PIM0LAH, 0x00000004); /* pointing to SRAM */ - out_le32(mbase + PECFG_PIMEN, 0x1); - - /* Enable I/O, Mem, and Busmaster cycles */ - out_le16((u16 *)(mbase + PCI_COMMAND), - in_le16((u16 *)(mbase + PCI_COMMAND)) | - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */ - out_le16(mbase + 0x202,0xfeed); /* Setting device ID */ - attempts = 10; - switch (port) { - case 0: - while (!(SDR_READ(PESDR0_RCSSTS) & (1 << 8))) { - if (!(attempts--)) { - printf("PCIE0: BMEN is not active\n"); - return -1; - } - mdelay(1000); - } - break; - case 1: - while (!(SDR_READ(PESDR1_RCSSTS) & (1 << 8))) { - if (!(attempts--)) { - printf("PCIE1: BMEN is not active\n"); - return -1; - } - mdelay(1000); - } - break; - case 2: - while (!(SDR_READ(PESDR2_RCSSTS) & (1 << 8))) { - if (!(attempts--)) { - printf("PCIE2: BMEN is not active\n"); - return -1; - } - mdelay(1000); - } - break; - } - printf("PCIE:%d successfully set as endpoint\n",port); - - return 0; -} -#endif /* CONFIG_440SPE && CONFIG_PCI */ diff --git a/cpu/ppc4xx/440spe_pcie.h b/cpu/ppc4xx/440spe_pcie.h deleted file mode 100644 index 38745eb797c..00000000000 --- a/cpu/ppc4xx/440spe_pcie.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Copyright (c) 2005 Cisco Systems. All rights reserved. - * Roland Dreier - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#ifndef __440SPE_PCIE_H -#define __440SPE_PCIE_H - -#define mdelay(n) ({unsigned long __ms=(n); while (__ms--) udelay(1000);}) - -#define DCRN_SDR0_CFGADDR 0x00e -#define DCRN_SDR0_CFGDATA 0x00f - -#define DCRN_PCIE0_BASE 0x100 -#define DCRN_PCIE1_BASE 0x120 -#define DCRN_PCIE2_BASE 0x140 -#define PCIE0 DCRN_PCIE0_BASE -#define PCIE1 DCRN_PCIE1_BASE -#define PCIE2 DCRN_PCIE2_BASE - -#define DCRN_PEGPL_CFGBAH(base) (base + 0x00) -#define DCRN_PEGPL_CFGBAL(base) (base + 0x01) -#define DCRN_PEGPL_CFGMSK(base) (base + 0x02) -#define DCRN_PEGPL_MSGBAH(base) (base + 0x03) -#define DCRN_PEGPL_MSGBAL(base) (base + 0x04) -#define DCRN_PEGPL_MSGMSK(base) (base + 0x05) -#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06) -#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07) -#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08) -#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09) -#define DCRN_PEGPL_REGBAH(base) (base + 0x12) -#define DCRN_PEGPL_REGBAL(base) (base + 0x13) -#define DCRN_PEGPL_REGMSK(base) (base + 0x14) -#define DCRN_PEGPL_SPECIAL(base) (base + 0x15) -#define DCRN_PEGPL_CFG(base) (base + 0x16) - -/* - * System DCRs (SDRs) - */ -#define PESDR0_PLLLCT1 0x03a0 -#define PESDR0_PLLLCT2 0x03a1 -#define PESDR0_PLLLCT3 0x03a2 - -#define PESDR0_UTLSET1 0x0300 -#define PESDR0_UTLSET2 0x0301 -#define PESDR0_DLPSET 0x0302 -#define PESDR0_LOOP 0x0303 -#define PESDR0_RCSSET 0x0304 -#define PESDR0_RCSSTS 0x0305 -#define PESDR0_HSSL0SET1 0x0306 -#define PESDR0_HSSL0SET2 0x0307 -#define PESDR0_HSSL0STS 0x0308 -#define PESDR0_HSSL1SET1 0x0309 -#define PESDR0_HSSL1SET2 0x030a -#define PESDR0_HSSL1STS 0x030b -#define PESDR0_HSSL2SET1 0x030c -#define PESDR0_HSSL2SET2 0x030d -#define PESDR0_HSSL2STS 0x030e -#define PESDR0_HSSL3SET1 0x030f -#define PESDR0_HSSL3SET2 0x0310 -#define PESDR0_HSSL3STS 0x0311 -#define PESDR0_HSSL4SET1 0x0312 -#define PESDR0_HSSL4SET2 0x0313 -#define PESDR0_HSSL4STS 0x0314 -#define PESDR0_HSSL5SET1 0x0315 -#define PESDR0_HSSL5SET2 0x0316 -#define PESDR0_HSSL5STS 0x0317 -#define PESDR0_HSSL6SET1 0x0318 -#define PESDR0_HSSL6SET2 0x0319 -#define PESDR0_HSSL6STS 0x031a -#define PESDR0_HSSL7SET1 0x031b -#define PESDR0_HSSL7SET2 0x031c -#define PESDR0_HSSL7STS 0x031d -#define PESDR0_HSSCTLSET 0x031e -#define PESDR0_LANE_ABCD 0x031f -#define PESDR0_LANE_EFGH 0x0320 - -#define PESDR1_UTLSET1 0x0340 -#define PESDR1_UTLSET2 0x0341 -#define PESDR1_DLPSET 0x0342 -#define PESDR1_LOOP 0x0343 -#define PESDR1_RCSSET 0x0344 -#define PESDR1_RCSSTS 0x0345 -#define PESDR1_HSSL0SET1 0x0346 -#define PESDR1_HSSL0SET2 0x0347 -#define PESDR1_HSSL0STS 0x0348 -#define PESDR1_HSSL1SET1 0x0349 -#define PESDR1_HSSL1SET2 0x034a -#define PESDR1_HSSL1STS 0x034b -#define PESDR1_HSSL2SET1 0x034c -#define PESDR1_HSSL2SET2 0x034d -#define PESDR1_HSSL2STS 0x034e -#define PESDR1_HSSL3SET1 0x034f -#define PESDR1_HSSL3SET2 0x0350 -#define PESDR1_HSSL3STS 0x0351 -#define PESDR1_HSSCTLSET 0x0352 -#define PESDR1_LANE_ABCD 0x0353 - -#define PESDR2_UTLSET1 0x0370 -#define PESDR2_UTLSET2 0x0371 -#define PESDR2_DLPSET 0x0372 -#define PESDR2_LOOP 0x0373 -#define PESDR2_RCSSET 0x0374 -#define PESDR2_RCSSTS 0x0375 -#define PESDR2_HSSL0SET1 0x0376 -#define PESDR2_HSSL0SET2 0x0377 -#define PESDR2_HSSL0STS 0x0378 -#define PESDR2_HSSL1SET1 0x0379 -#define PESDR2_HSSL1SET2 0x037a -#define PESDR2_HSSL1STS 0x037b -#define PESDR2_HSSL2SET1 0x037c -#define PESDR2_HSSL2SET2 0x037d -#define PESDR2_HSSL2STS 0x037e -#define PESDR2_HSSL3SET1 0x037f -#define PESDR2_HSSL3SET2 0x0380 -#define PESDR2_HSSL3STS 0x0381 -#define PESDR2_HSSCTLSET 0x0382 -#define PESDR2_LANE_ABCD 0x0383 - -/* - * UTL register offsets - */ -#define PEUTL_PBBSZ 0x20 -#define PEUTL_OPDBSZ 0x68 -#define PEUTL_IPHBSZ 0x70 -#define PEUTL_IPDBSZ 0x78 -#define PEUTL_OUTTR 0x90 -#define PEUTL_INTR 0x98 -#define PEUTL_PCTL 0xa0 -#define PEUTL_RCIRQEN 0xb8 - -/* - * Config space register offsets - */ -#define PECFG_BAR0LMPA 0x210 -#define PECFG_BAR0HMPA 0x214 -#define PECFG_BAR1MPA 0x218 -#define PECFG_BAR2MPA 0x220 - -#define PECFG_PIMEN 0x33c -#define PECFG_PIM0LAL 0x340 -#define PECFG_PIM0LAH 0x344 -#define PECFG_PIM1LAL 0x348 -#define PECFG_PIM1LAH 0x34c -#define PECFG_PIM01SAL 0x350 -#define PECFG_PIM01SAH 0x354 - -#define PECFG_POM0LAL 0x380 -#define PECFG_POM0LAH 0x384 - -#define SDR_READ(offset) ({\ - mtdcr(DCRN_SDR0_CFGADDR, offset); \ - mfdcr(DCRN_SDR0_CFGDATA);}) - -#define SDR_WRITE(offset, data) ({\ - mtdcr(DCRN_SDR0_CFGADDR, offset); \ - mtdcr(DCRN_SDR0_CFGDATA,data);}) - -#define GPL_DMER_MASK_DISA 0x02000000 - -int ppc440spe_init_pcie(void); -int ppc440spe_init_pcie_rootport(int port); -void yucca_setup_pcie_fpga_rootpoint(int port); -void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port); -int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port); -int yucca_pcie_card_present(int port); -int pcie_hose_scan(struct pci_controller *hose, int bus); -#endif /* __440SPE_PCIE_H */ diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c new file mode 100644 index 00000000000..8906adc51e2 --- /dev/null +++ b/cpu/ppc4xx/4xx_pcie.c @@ -0,0 +1,1067 @@ +/* + * (C) Copyright 2006 - 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * Roland Dreier + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include + +#if defined(CONFIG_440SPE) && defined(CONFIG_PCI) + +#include + +enum { + PTYPE_ENDPOINT = 0x0, + PTYPE_LEGACY_ENDPOINT = 0x1, + PTYPE_ROOT_PORT = 0x4, + + LNKW_X1 = 0x1, + LNKW_X4 = 0x4, + LNKW_X8 = 0x8 +}; + +static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn) +{ + u8 *base = (u8*)hose->cfg_data; + + /* use local configuration space for the first bus */ + if (PCI_BUS(devfn) == 0) { + if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE) + base = (u8*)CFG_PCIE0_XCFGBASE; + if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE) + base = (u8*)CFG_PCIE1_XCFGBASE; + if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE) + base = (u8*)CFG_PCIE2_XCFGBASE; + } + + return base; +} + +static void pcie_dmer_disable(void) +{ + mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA); +} + +static void pcie_dmer_enable(void) +{ + mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA); +} + +static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, + int offset, int len, u32 *val) { + + u8 *address; + *val = 0; + + /* + * Bus numbers are relative to hose->first_busno + */ + devfn -= PCI_BDF(hose->first_busno, 0, 0); + + /* + * NOTICE: configuration space ranges are currenlty mapped only for + * the first 16 buses, so such limit must be imposed. In case more + * buses are required the TLB settings in board/amcc//init.S + * need to be altered accordingly (one bus takes 1 MB of memory space). + */ + if (PCI_BUS(devfn) >= 16) + return 0; + + /* + * Only single device/single function is supported for the primary and + * secondary buses of the 440SPe host bridge. + */ + if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && + ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) + return 0; + + address = pcie_get_base(hose, devfn); + offset += devfn << 4; + + /* + * Reading from configuration space of non-existing device can + * generate transaction errors. For the read duration we suppress + * assertion of machine check exceptions to avoid those. + */ + pcie_dmer_disable (); + + switch (len) { + case 1: + *val = in_8(hose->cfg_data + offset); + break; + case 2: + *val = in_le16((u16 *)(hose->cfg_data + offset)); + break; + default: + *val = in_le32((u32*)(hose->cfg_data + offset)); + break; + } + + pcie_dmer_enable (); + + return 0; +} + +static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, + int offset, int len, u32 val) { + + u8 *address; + + /* + * Bus numbers are relative to hose->first_busno + */ + devfn -= PCI_BDF(hose->first_busno, 0, 0); + + /* + * Same constraints as in pcie_read_config(). + */ + if (PCI_BUS(devfn) >= 16) + return 0; + + if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && + ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) + return 0; + + address = pcie_get_base(hose, devfn); + offset += devfn << 4; + + /* + * Suppress MCK exceptions, similar to pcie_read_config() + */ + pcie_dmer_disable (); + + switch (len) { + case 1: + out_8(hose->cfg_data + offset, val); + break; + case 2: + out_le16((u16 *)(hose->cfg_data + offset), val); + break; + default: + out_le32((u32 *)(hose->cfg_data + offset), val); + break; + } + + pcie_dmer_enable (); + + return 0; +} + +int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val) +{ + u32 v; + int rv; + + rv = pcie_read_config(hose, dev, offset, 1, &v); + *val = (u8)v; + return rv; +} + +int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val) +{ + u32 v; + int rv; + + rv = pcie_read_config(hose, dev, offset, 2, &v); + *val = (u16)v; + return rv; +} + +int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val) +{ + u32 v; + int rv; + + rv = pcie_read_config(hose, dev, offset, 3, &v); + *val = (u32)v; + return rv; +} + +int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val) +{ + return pcie_write_config(hose,(u32)dev,offset,1,val); +} + +int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val) +{ + return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val); +} + +int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val) +{ + return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val); +} + +static void ppc440spe_setup_utl(u32 port) { + + volatile void *utl_base = NULL; + + /* + * Map UTL registers + */ + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c); + mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); + mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800); + break; + + case 1: + mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c); + mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); + mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800); + break; + + case 2: + mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c); + mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001); + mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800); + break; + } + utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port); + + /* + * Set buffer allocations and then assert VRB and TXE. + */ + out_be32(utl_base + PEUTL_OUTTR, 0x08000000); + out_be32(utl_base + PEUTL_INTR, 0x02000000); + out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000); + out_be32(utl_base + PEUTL_PBBSZ, 0x53000000); + out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000); + out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000); + out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); + out_be32(utl_base + PEUTL_PCTL, 0x80800066); +} + +static int check_error(void) +{ + u32 valPE0, valPE1, valPE2; + int err = 0; + + /* SDR0_PEGPLLLCT1 reset */ + if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) { + printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0); + } + + valPE0 = SDR_READ(PESDR0_RCSSET); + valPE1 = SDR_READ(PESDR1_RCSSET); + valPE2 = SDR_READ(PESDR2_RCSSET); + + /* SDR0_PExRCSSET rstgu */ + if (!(valPE0 & 0x01000000) || + !(valPE1 & 0x01000000) || + !(valPE2 & 0x01000000)) { + printf("PCIE: SDR0_PExRCSSET rstgu error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rstdl */ + if (!(valPE0 & 0x00010000) || + !(valPE1 & 0x00010000) || + !(valPE2 & 0x00010000)) { + printf("PCIE: SDR0_PExRCSSET rstdl error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rstpyn */ + if ((valPE0 & 0x00001000) || + (valPE1 & 0x00001000) || + (valPE2 & 0x00001000)) { + printf("PCIE: SDR0_PExRCSSET rstpyn error\n"); + err = -1; + } + + /* SDR0_PExRCSSET hldplb */ + if ((valPE0 & 0x10000000) || + (valPE1 & 0x10000000) || + (valPE2 & 0x10000000)) { + printf("PCIE: SDR0_PExRCSSET hldplb error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rdy */ + if ((valPE0 & 0x00100000) || + (valPE1 & 0x00100000) || + (valPE2 & 0x00100000)) { + printf("PCIE: SDR0_PExRCSSET rdy error\n"); + err = -1; + } + + /* SDR0_PExRCSSET shutdown */ + if ((valPE0 & 0x00000100) || + (valPE1 & 0x00000100) || + (valPE2 & 0x00000100)) { + printf("PCIE: SDR0_PExRCSSET shutdown error\n"); + err = -1; + } + return err; +} + +/* + * Initialize PCI Express core + */ +int ppc440spe_init_pcie(void) +{ + int time_out = 20; + + /* Set PLL clock receiver to LVPECL */ + SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28); + + if (check_error()) + return -1; + + if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) + { + printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n", + SDR_READ(PESDR0_PLLLCT2)); + return -1; + } + /* De-assert reset of PCIe PLL, wait for lock */ + SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24)); + udelay(3); + + while (time_out) { + if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) { + time_out--; + udelay(1); + } else + break; + } + if (!time_out) { + printf("PCIE: VCO output not locked\n"); + return -1; + } + return 0; +} + +/* + * Yucca board as End point and root point setup + * and + * testing inbound and out bound windows + * + * YUCCA board can be plugged into another yucca board or you can get PCI-E + * cable which can be used to setup loop back from one port to another port. + * Please rememeber that unless there is a endpoint plugged in to root port it + * will not initialize. It is the same in case of endpoint , unless there is + * root port attached it will not initialize. + * + * In this release of software all the PCI-E ports are configured as either + * endpoint or rootpoint.In future we will have support for selective ports + * setup as endpoint and root point in single board. + * + * Once your board came up as root point , you can verify by reading + * /proc/bus/pci/devices. Where you can see the configuration registers + * of end point device attached to the port. + * + * Enpoint cofiguration can be verified by connecting Yucca board to any + * host or another yucca board. Then try to scan the device. In case of + * linux use "lspci" or appripriate os command. + * + * How do I verify the inbound and out bound windows ?(yucca to yucca) + * in this configuration inbound and outbound windows are setup to access + * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address + * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000, + * This is waere your POM(PLB out bound memory window) mapped. then + * read the data from other yucca board's u-boot prompt at address + * 0x9000 0000(SRAM). Data should match. + * In case of inbound , write data to u-boot command prompt at 0xb000 0000 + * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check + * data at 0x9000 0000(SRAM).Data should match. + */ +int ppc440spe_init_pcie_rootport(int port) +{ + static int core_init; + volatile u32 val = 0; + int attempts; + + if (!core_init) { + ++core_init; + if (ppc440spe_init_pcie()) + return -1; + } + + /* + * Initialize various parts of the PCI Express core for our port: + * + * - Set as a root port and enable max width + * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). + * - Set up UTL configuration. + * - Increase SERDES drive strength to levels suggested by AMCC. + * - De-assert RSTPYN, RSTDL and RSTGU. + * + * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with + * default setting 0x11310000. The register has new fields, + * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core + * hang. + */ + switch (port) { + case 0: + SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12); + + SDR_WRITE(PESDR0_UTLSET1, 0x21222222); + if (!ppc440spe_revB()) + SDR_WRITE(PESDR0_UTLSET2, 0x11000000); + SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); + SDR_WRITE(PESDR0_RCSSET, + (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + break; + + case 1: + SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); + SDR_WRITE(PESDR1_UTLSET1, 0x21222222); + if (!ppc440spe_revB()) + SDR_WRITE(PESDR1_UTLSET2, 0x11000000); + SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000); + SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000); + SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000); + SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000); + SDR_WRITE(PESDR1_RCSSET, + (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + break; + + case 2: + SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); + SDR_WRITE(PESDR2_UTLSET1, 0x21222222); + if (!ppc440spe_revB()) + SDR_WRITE(PESDR2_UTLSET2, 0x11000000); + SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000); + SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000); + SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000); + SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000); + SDR_WRITE(PESDR2_RCSSET, + (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + break; + } + /* + * Notice: the following delay has critical impact on device + * initialization - if too short (<50ms) the link doesn't get up. + */ + mdelay(100); + + switch (port) { + case 0: + val = SDR_READ(PESDR0_RCSSTS); + break; + case 1: + val = SDR_READ(PESDR1_RCSSTS); + break; + case 2: + val = SDR_READ(PESDR2_RCSSTS); + break; + } + + if (val & (1 << 20)) { + printf("PCIE%d: PGRST failed %08x\n", port, val); + return -1; + } + + /* + * Verify link is up + */ + val = 0; + switch (port) { + case 0: + val = SDR_READ(PESDR0_LOOP); + break; + case 1: + val = SDR_READ(PESDR1_LOOP); + break; + case 2: + val = SDR_READ(PESDR2_LOOP); + break; + } + if (!(val & 0x00001000)) { + printf("PCIE%d: link is not up.\n", port); + return -1; + } + + /* + * Setup UTL registers - but only on revA! + * We use default settings for revB chip. + */ + if (!ppc440spe_revB()) + ppc440spe_setup_utl(port); + + /* + * We map PCI Express configuration access into the 512MB regions + * + * NOTICE: revB is very strict about PLB real addressess and ranges to + * be mapped for config space; it seems to only work with d_nnnn_nnnn + * range (hangs the core upon config transaction attempts when set + * otherwise) while revA uses c_nnnn_nnnn. + * + * For revA: + * PCIE0: 0xc_4000_0000 + * PCIE1: 0xc_8000_0000 + * PCIE2: 0xc_c000_0000 + * + * For revB: + * PCIE0: 0xd_0000_0000 + * PCIE1: 0xd_2000_0000 + * PCIE2: 0xd_4000_0000 + */ + + switch (port) { + case 0: + if (ppc440spe_revB()) { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000); + } else { + /* revA */ + mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000); + } + mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ + break; + + case 1: + if (ppc440spe_revB()) { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000); + } else { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000); + } + mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ + break; + + case 2: + if (ppc440spe_revB()) { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000); + } else { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000); + } + mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ + break; + } + + /* + * Check for VC0 active and assert RDY. + */ + attempts = 10; + switch (port) { + case 0: + while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) { + if (!(attempts--)) { + printf("PCIE0: VC0 not active\n"); + return -1; + } + mdelay(1000); + } + SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20); + break; + case 1: + while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) { + if (!(attempts--)) { + printf("PCIE1: VC0 not active\n"); + return -1; + } + mdelay(1000); + } + + SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20); + break; + case 2: + while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) { + if (!(attempts--)) { + printf("PCIE2: VC0 not active\n"); + return -1; + } + mdelay(1000); + } + + SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20); + break; + } + mdelay(100); + + return 0; +} + +int ppc440spe_init_pcie_endport(int port) +{ + static int core_init; + volatile u32 val = 0; + int attempts; + + if (!core_init) { + ++core_init; + if (ppc440spe_init_pcie()) + return -1; + } + + /* + * Initialize various parts of the PCI Express core for our port: + * + * - Set as a end port and enable max width + * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). + * - Set up UTL configuration. + * - Increase SERDES drive strength to levels suggested by AMCC. + * - De-assert RSTPYN, RSTDL and RSTGU. + * + * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with + * default setting 0x11310000. The register has new fields, + * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core + * hang. + */ + switch (port) { + case 0: + SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X8 << 12); + + SDR_WRITE(PESDR0_UTLSET1, 0x20222222); + if (!ppc440spe_revB()) + SDR_WRITE(PESDR0_UTLSET2, 0x11000000); + SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); + SDR_WRITE(PESDR0_RCSSET, + (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + break; + + case 1: + SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12); + SDR_WRITE(PESDR1_UTLSET1, 0x20222222); + if (!ppc440spe_revB()) + SDR_WRITE(PESDR1_UTLSET2, 0x11000000); + SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000); + SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000); + SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000); + SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000); + SDR_WRITE(PESDR1_RCSSET, + (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + break; + + case 2: + SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12); + SDR_WRITE(PESDR2_UTLSET1, 0x20222222); + if (!ppc440spe_revB()) + SDR_WRITE(PESDR2_UTLSET2, 0x11000000); + SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000); + SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000); + SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000); + SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000); + SDR_WRITE(PESDR2_RCSSET, + (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + break; + } + /* + * Notice: the following delay has critical impact on device + * initialization - if too short (<50ms) the link doesn't get up. + */ + mdelay(100); + + switch (port) { + case 0: val = SDR_READ(PESDR0_RCSSTS); break; + case 1: val = SDR_READ(PESDR1_RCSSTS); break; + case 2: val = SDR_READ(PESDR2_RCSSTS); break; + } + + if (val & (1 << 20)) { + printf("PCIE%d: PGRST failed %08x\n", port, val); + return -1; + } + + /* + * Verify link is up + */ + val = 0; + switch (port) + { + case 0: + val = SDR_READ(PESDR0_LOOP); + break; + case 1: + val = SDR_READ(PESDR1_LOOP); + break; + case 2: + val = SDR_READ(PESDR2_LOOP); + break; + } + if (!(val & 0x00001000)) { + printf("PCIE%d: link is not up.\n", port); + return -1; + } + + /* + * Setup UTL registers - but only on revA! + * We use default settings for revB chip. + */ + if (!ppc440spe_revB()) + ppc440spe_setup_utl(port); + + /* + * We map PCI Express configuration access into the 512MB regions + * + * NOTICE: revB is very strict about PLB real addressess and ranges to + * be mapped for config space; it seems to only work with d_nnnn_nnnn + * range (hangs the core upon config transaction attempts when set + * otherwise) while revA uses c_nnnn_nnnn. + * + * For revA: + * PCIE0: 0xc_4000_0000 + * PCIE1: 0xc_8000_0000 + * PCIE2: 0xc_c000_0000 + * + * For revB: + * PCIE0: 0xd_0000_0000 + * PCIE1: 0xd_2000_0000 + * PCIE2: 0xd_4000_0000 + */ + switch (port) { + case 0: + if (ppc440spe_revB()) { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000); + } else { + /* revA */ + mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000); + } + mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ + break; + + case 1: + if (ppc440spe_revB()) { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000); + } else { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000); + } + mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ + break; + + case 2: + if (ppc440spe_revB()) { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000); + } else { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000); + } + mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ + break; + } + + /* + * Check for VC0 active and assert RDY. + */ + attempts = 10; + switch (port) { + case 0: + while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) { + if (!(attempts--)) { + printf("PCIE0: VC0 not active\n"); + return -1; + } + mdelay(1000); + } + SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20); + break; + case 1: + while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) { + if (!(attempts--)) { + printf("PCIE1: VC0 not active\n"); + return -1; + } + mdelay(1000); + } + + SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20); + break; + case 2: + while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) { + if (!(attempts--)) { + printf("PCIE2: VC0 not active\n"); + return -1; + } + mdelay(1000); + } + + SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20); + break; + } + mdelay(100); + + return 0; +} + +void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) +{ + volatile void *mbase = NULL; + volatile void *rmbase = NULL; + + pci_set_ops(hose, + pcie_read_config_byte, + pcie_read_config_word, + pcie_read_config_dword, + pcie_write_config_byte, + pcie_write_config_word, + pcie_write_config_dword); + + switch (port) { + case 0: + mbase = (u32 *)CFG_PCIE0_XCFGBASE; + rmbase = (u32 *)CFG_PCIE0_CFGBASE; + hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE; + break; + case 1: + mbase = (u32 *)CFG_PCIE1_XCFGBASE; + rmbase = (u32 *)CFG_PCIE1_CFGBASE; + hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; + break; + case 2: + mbase = (u32 *)CFG_PCIE2_XCFGBASE; + rmbase = (u32 *)CFG_PCIE2_CFGBASE; + hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; + break; + } + + /* + * Set bus numbers on our root port + */ + out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); + out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); + out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); + + /* + * Set up outbound translation to hose->mem_space from PLB + * addresses at an offset of 0xd_0000_0000. We set the low + * bits of the mask to 11 to turn off splitting into 8 + * subregions and to enable the outbound translation. + */ + out_le32(mbase + PECFG_POM0LAH, 0x00000000); + out_le32(mbase + PECFG_POM0LAL, 0x00000000); + + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), + ~(CFG_PCIE_MEMSIZE - 1) | 3); + break; + case 1: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE)); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), + ~(CFG_PCIE_MEMSIZE - 1) | 3); + break; + case 2: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE)); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), + ~(CFG_PCIE_MEMSIZE - 1) | 3); + break; + } + + /* Set up 16GB inbound memory window at 0 */ + out_le32(mbase + PCI_BASE_ADDRESS_0, 0); + out_le32(mbase + PCI_BASE_ADDRESS_1, 0); + out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); + out_le32(mbase + PECFG_BAR0LMPA, 0); + + out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); + out_le32(mbase + PECFG_PIM01SAL, 0x00000000); + out_le32(mbase + PECFG_PIM0LAL, 0); + out_le32(mbase + PECFG_PIM0LAH, 0); + out_le32(mbase + PECFG_PIM1LAL, 0x00000000); + out_le32(mbase + PECFG_PIM1LAH, 0x00000004); + out_le32(mbase + PECFG_PIMEN, 0x1); + + /* Enable I/O, Mem, and Busmaster cycles */ + out_le16((u16 *)(mbase + PCI_COMMAND), + in_le16((u16 *)(mbase + PCI_COMMAND)) | + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + printf("PCIE:%d successfully set as rootpoint\n",port); + + /* Set Device and Vendor Id */ + switch (port) { + case 0: + out_le16(mbase + 0x200, 0xaaa0); + out_le16(mbase + 0x202, 0xbed0); + break; + case 1: + out_le16(mbase + 0x200, 0xaaa1); + out_le16(mbase + 0x202, 0xbed1); + break; + case 2: + out_le16(mbase + 0x200, 0xaaa2); + out_le16(mbase + 0x202, 0xbed2); + break; + default: + out_le16(mbase + 0x200, 0xaaa3); + out_le16(mbase + 0x202, 0xbed3); + } + + /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ + out_le32(mbase + 0x208, 0x06040001); + +} + +int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port) +{ + volatile void *mbase = NULL; + int attempts = 0; + + pci_set_ops(hose, + pcie_read_config_byte, + pcie_read_config_word, + pcie_read_config_dword, + pcie_write_config_byte, + pcie_write_config_word, + pcie_write_config_dword); + + switch (port) { + case 0: + mbase = (u32 *)CFG_PCIE0_XCFGBASE; + hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE; + break; + case 1: + mbase = (u32 *)CFG_PCIE1_XCFGBASE; + hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; + break; + case 2: + mbase = (u32 *)CFG_PCIE2_XCFGBASE; + hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; + break; + } + + /* + * Set up outbound translation to hose->mem_space from PLB + * addresses at an offset of 0xd_0000_0000. We set the low + * bits of the mask to 11 to turn off splitting into 8 + * subregions and to enable the outbound translation. + */ + out_le32(mbase + PECFG_POM0LAH, 0x00001ff8); + out_le32(mbase + PECFG_POM0LAL, 0x00001000); + + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), + ~(CFG_PCIE_MEMSIZE - 1) | 3); + break; + case 1: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE)); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), + ~(CFG_PCIE_MEMSIZE - 1) | 3); + break; + case 2: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE)); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), + ~(CFG_PCIE_MEMSIZE - 1) | 3); + break; + } + + /* Set up 16GB inbound memory window at 0 */ + out_le32(mbase + PCI_BASE_ADDRESS_0, 0); + out_le32(mbase + PCI_BASE_ADDRESS_1, 0); + out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); + out_le32(mbase + PECFG_BAR0LMPA, 0); + out_le32(mbase + PECFG_PIM0LAL, 0x00000000); + out_le32(mbase + PECFG_PIM0LAH, 0x00000004); /* pointing to SRAM */ + out_le32(mbase + PECFG_PIMEN, 0x1); + + /* Enable I/O, Mem, and Busmaster cycles */ + out_le16((u16 *)(mbase + PCI_COMMAND), + in_le16((u16 *)(mbase + PCI_COMMAND)) | + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */ + out_le16(mbase + 0x202,0xfeed); /* Setting device ID */ + attempts = 10; + switch (port) { + case 0: + while (!(SDR_READ(PESDR0_RCSSTS) & (1 << 8))) { + if (!(attempts--)) { + printf("PCIE0: BMEN is not active\n"); + return -1; + } + mdelay(1000); + } + break; + case 1: + while (!(SDR_READ(PESDR1_RCSSTS) & (1 << 8))) { + if (!(attempts--)) { + printf("PCIE1: BMEN is not active\n"); + return -1; + } + mdelay(1000); + } + break; + case 2: + while (!(SDR_READ(PESDR2_RCSSTS) & (1 << 8))) { + if (!(attempts--)) { + printf("PCIE2: BMEN is not active\n"); + return -1; + } + mdelay(1000); + } + break; + } + printf("PCIE:%d successfully set as endpoint\n",port); + + return 0; +} +#endif /* CONFIG_440SPE && CONFIG_PCI */ diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index af9da5b95fd..28a8e2bcb7e 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -27,13 +27,12 @@ LIB = $(obj)lib$(CPU).a START = start.o resetvec.o kgdb.o SOBJS = dcr.o -COBJS = 405gp_pci.o 440spe_pcie.o 4xx_enet.o \ +COBJS = 405gp_pci.o 4xx_pcie.o 4xx_enet.o \ bedbug_405.o commproc.o \ cpu.o cpu_init.o gpio.o i2c.o interrupts.o \ miiphy.o ndfc.o sdram.o serial.o \ 40x_spd_sdram.o 44x_spd_ddr.o 44x_spd_ddr2.o speed.o \ - tlb.o traps.o usb_ohci.o usb.o usbdev.o \ - 440spe_pcie.o + tlb.o traps.o usb_ohci.o usb.o usbdev.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h new file mode 100644 index 00000000000..38745eb797c --- /dev/null +++ b/include/asm-ppc/4xx_pcie.h @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * Roland Dreier + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#ifndef __440SPE_PCIE_H +#define __440SPE_PCIE_H + +#define mdelay(n) ({unsigned long __ms=(n); while (__ms--) udelay(1000);}) + +#define DCRN_SDR0_CFGADDR 0x00e +#define DCRN_SDR0_CFGDATA 0x00f + +#define DCRN_PCIE0_BASE 0x100 +#define DCRN_PCIE1_BASE 0x120 +#define DCRN_PCIE2_BASE 0x140 +#define PCIE0 DCRN_PCIE0_BASE +#define PCIE1 DCRN_PCIE1_BASE +#define PCIE2 DCRN_PCIE2_BASE + +#define DCRN_PEGPL_CFGBAH(base) (base + 0x00) +#define DCRN_PEGPL_CFGBAL(base) (base + 0x01) +#define DCRN_PEGPL_CFGMSK(base) (base + 0x02) +#define DCRN_PEGPL_MSGBAH(base) (base + 0x03) +#define DCRN_PEGPL_MSGBAL(base) (base + 0x04) +#define DCRN_PEGPL_MSGMSK(base) (base + 0x05) +#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06) +#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07) +#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08) +#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09) +#define DCRN_PEGPL_REGBAH(base) (base + 0x12) +#define DCRN_PEGPL_REGBAL(base) (base + 0x13) +#define DCRN_PEGPL_REGMSK(base) (base + 0x14) +#define DCRN_PEGPL_SPECIAL(base) (base + 0x15) +#define DCRN_PEGPL_CFG(base) (base + 0x16) + +/* + * System DCRs (SDRs) + */ +#define PESDR0_PLLLCT1 0x03a0 +#define PESDR0_PLLLCT2 0x03a1 +#define PESDR0_PLLLCT3 0x03a2 + +#define PESDR0_UTLSET1 0x0300 +#define PESDR0_UTLSET2 0x0301 +#define PESDR0_DLPSET 0x0302 +#define PESDR0_LOOP 0x0303 +#define PESDR0_RCSSET 0x0304 +#define PESDR0_RCSSTS 0x0305 +#define PESDR0_HSSL0SET1 0x0306 +#define PESDR0_HSSL0SET2 0x0307 +#define PESDR0_HSSL0STS 0x0308 +#define PESDR0_HSSL1SET1 0x0309 +#define PESDR0_HSSL1SET2 0x030a +#define PESDR0_HSSL1STS 0x030b +#define PESDR0_HSSL2SET1 0x030c +#define PESDR0_HSSL2SET2 0x030d +#define PESDR0_HSSL2STS 0x030e +#define PESDR0_HSSL3SET1 0x030f +#define PESDR0_HSSL3SET2 0x0310 +#define PESDR0_HSSL3STS 0x0311 +#define PESDR0_HSSL4SET1 0x0312 +#define PESDR0_HSSL4SET2 0x0313 +#define PESDR0_HSSL4STS 0x0314 +#define PESDR0_HSSL5SET1 0x0315 +#define PESDR0_HSSL5SET2 0x0316 +#define PESDR0_HSSL5STS 0x0317 +#define PESDR0_HSSL6SET1 0x0318 +#define PESDR0_HSSL6SET2 0x0319 +#define PESDR0_HSSL6STS 0x031a +#define PESDR0_HSSL7SET1 0x031b +#define PESDR0_HSSL7SET2 0x031c +#define PESDR0_HSSL7STS 0x031d +#define PESDR0_HSSCTLSET 0x031e +#define PESDR0_LANE_ABCD 0x031f +#define PESDR0_LANE_EFGH 0x0320 + +#define PESDR1_UTLSET1 0x0340 +#define PESDR1_UTLSET2 0x0341 +#define PESDR1_DLPSET 0x0342 +#define PESDR1_LOOP 0x0343 +#define PESDR1_RCSSET 0x0344 +#define PESDR1_RCSSTS 0x0345 +#define PESDR1_HSSL0SET1 0x0346 +#define PESDR1_HSSL0SET2 0x0347 +#define PESDR1_HSSL0STS 0x0348 +#define PESDR1_HSSL1SET1 0x0349 +#define PESDR1_HSSL1SET2 0x034a +#define PESDR1_HSSL1STS 0x034b +#define PESDR1_HSSL2SET1 0x034c +#define PESDR1_HSSL2SET2 0x034d +#define PESDR1_HSSL2STS 0x034e +#define PESDR1_HSSL3SET1 0x034f +#define PESDR1_HSSL3SET2 0x0350 +#define PESDR1_HSSL3STS 0x0351 +#define PESDR1_HSSCTLSET 0x0352 +#define PESDR1_LANE_ABCD 0x0353 + +#define PESDR2_UTLSET1 0x0370 +#define PESDR2_UTLSET2 0x0371 +#define PESDR2_DLPSET 0x0372 +#define PESDR2_LOOP 0x0373 +#define PESDR2_RCSSET 0x0374 +#define PESDR2_RCSSTS 0x0375 +#define PESDR2_HSSL0SET1 0x0376 +#define PESDR2_HSSL0SET2 0x0377 +#define PESDR2_HSSL0STS 0x0378 +#define PESDR2_HSSL1SET1 0x0379 +#define PESDR2_HSSL1SET2 0x037a +#define PESDR2_HSSL1STS 0x037b +#define PESDR2_HSSL2SET1 0x037c +#define PESDR2_HSSL2SET2 0x037d +#define PESDR2_HSSL2STS 0x037e +#define PESDR2_HSSL3SET1 0x037f +#define PESDR2_HSSL3SET2 0x0380 +#define PESDR2_HSSL3STS 0x0381 +#define PESDR2_HSSCTLSET 0x0382 +#define PESDR2_LANE_ABCD 0x0383 + +/* + * UTL register offsets + */ +#define PEUTL_PBBSZ 0x20 +#define PEUTL_OPDBSZ 0x68 +#define PEUTL_IPHBSZ 0x70 +#define PEUTL_IPDBSZ 0x78 +#define PEUTL_OUTTR 0x90 +#define PEUTL_INTR 0x98 +#define PEUTL_PCTL 0xa0 +#define PEUTL_RCIRQEN 0xb8 + +/* + * Config space register offsets + */ +#define PECFG_BAR0LMPA 0x210 +#define PECFG_BAR0HMPA 0x214 +#define PECFG_BAR1MPA 0x218 +#define PECFG_BAR2MPA 0x220 + +#define PECFG_PIMEN 0x33c +#define PECFG_PIM0LAL 0x340 +#define PECFG_PIM0LAH 0x344 +#define PECFG_PIM1LAL 0x348 +#define PECFG_PIM1LAH 0x34c +#define PECFG_PIM01SAL 0x350 +#define PECFG_PIM01SAH 0x354 + +#define PECFG_POM0LAL 0x380 +#define PECFG_POM0LAH 0x384 + +#define SDR_READ(offset) ({\ + mtdcr(DCRN_SDR0_CFGADDR, offset); \ + mfdcr(DCRN_SDR0_CFGDATA);}) + +#define SDR_WRITE(offset, data) ({\ + mtdcr(DCRN_SDR0_CFGADDR, offset); \ + mtdcr(DCRN_SDR0_CFGDATA,data);}) + +#define GPL_DMER_MASK_DISA 0x02000000 + +int ppc440spe_init_pcie(void); +int ppc440spe_init_pcie_rootport(int port); +void yucca_setup_pcie_fpga_rootpoint(int port); +void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port); +int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port); +int yucca_pcie_card_present(int port); +int pcie_hose_scan(struct pci_controller *hose, int bus); +#endif /* __440SPE_PCIE_H */ -- cgit v1.3.1 From 026f71106871f31d17d0ea0db9a7547ff92934bc Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 3 Oct 2007 07:48:09 +0200 Subject: ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (2) This patch is the first patch of a series to make the 440SPe PCIe code usable on different 4xx PPC platforms. In preperation for the new 405EX which is also equipped with PCIe interfaces. (2) This patch renames the functions from 440spe_ to 4xx_ with a little additional cleanup Signed-off-by: Stefan Roese --- board/amcc/katmai/katmai.c | 11 ++++------- board/amcc/yucca/yucca.c | 11 ++++------- cpu/ppc4xx/4xx_pcie.c | 20 ++++++++++---------- include/asm-ppc/4xx_pcie.h | 17 ++++++++--------- 4 files changed, 26 insertions(+), 33 deletions(-) (limited to 'cpu') diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index 0c8e6cb701e..f1c352cb86e 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -35,9 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; -int ppc440spe_init_pcie_rootport(int port); -void ppc440spe_setup_pcie(struct pci_controller *hose, int port); - int board_early_init_f (void) { unsigned long mfr; @@ -409,9 +406,9 @@ void pcie_setup_hoses(int busno) continue; #ifdef PCIE_ENDPOINT - if (ppc440spe_init_pcie_endport(i)) { + if (ppc4xx_init_pcie_endport(i)) { #else - if (ppc440spe_init_pcie_rootport(i)) { + if (ppc4xx_init_pcie_rootport(i)) { #endif printf("PCIE%d: initialization failed\n", i); continue; @@ -433,13 +430,13 @@ void pcie_setup_hoses(int busno) pci_register_hose(hose); #ifdef PCIE_ENDPOINT - ppc440spe_setup_pcie_endpoint(hose, i); + ppc4xx_setup_pcie_endpoint(hose, i); /* * Reson for no scanning is endpoint can not generate * upstream configuration accesses. */ #else - ppc440spe_setup_pcie_rootpoint(hose, i); + ppc4xx_setup_pcie_rootpoint(hose, i); env = getenv ("pciscandelay"); if (env != NULL) { diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 17c3ba0f17d..c46721c9229 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -47,9 +47,6 @@ char *remove_l_w_space(char *in_str ); char *remove_t_w_space(char *in_str ); int get_console_port(void); -int ppc440spe_init_pcie_rootport(int port); -void ppc440spe_setup_pcie(struct pci_controller *hose, int port); - #define DEBUG_ENV #ifdef DEBUG_ENV #define DEBUGF(fmt,args...) printf(fmt ,##args) @@ -865,10 +862,10 @@ void pcie_setup_hoses(int busno) #ifdef PCIE_ENDPOINT yucca_setup_pcie_fpga_endpoint(i); - if (ppc440spe_init_pcie_endport(i)) { + if (ppc4xx_init_pcie_endport(i)) { #else yucca_setup_pcie_fpga_rootpoint(i); - if (ppc440spe_init_pcie_rootport(i)) { + if (ppc4xx_init_pcie_rootport(i)) { #endif printf("PCIE%d: initialization failed\n", i); continue; @@ -890,13 +887,13 @@ void pcie_setup_hoses(int busno) pci_register_hose(hose); #ifdef PCIE_ENDPOINT - ppc440spe_setup_pcie_endpoint(hose, i); + ppc4xx_setup_pcie_endpoint(hose, i); /* * Reson for no scanning is endpoint can not generate * upstream configuration accesses. */ #else - ppc440spe_setup_pcie_rootpoint(hose, i); + ppc4xx_setup_pcie_rootpoint(hose, i); env = getenv ("pciscandelay"); if (env != NULL) { diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index 8906adc51e2..c7b21417861 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -222,7 +222,7 @@ int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val); } -static void ppc440spe_setup_utl(u32 port) { +static void ppc4xx_setup_utl(u32 port) { volatile void *utl_base = NULL; @@ -333,7 +333,7 @@ static int check_error(void) /* * Initialize PCI Express core */ -int ppc440spe_init_pcie(void) +int ppc4xx_init_pcie(void) { int time_out = 20; @@ -401,7 +401,7 @@ int ppc440spe_init_pcie(void) * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check * data at 0x9000 0000(SRAM).Data should match. */ -int ppc440spe_init_pcie_rootport(int port) +int ppc4xx_init_pcie_rootport(int port) { static int core_init; volatile u32 val = 0; @@ -409,7 +409,7 @@ int ppc440spe_init_pcie_rootport(int port) if (!core_init) { ++core_init; - if (ppc440spe_init_pcie()) + if (ppc4xx_init_pcie()) return -1; } @@ -520,7 +520,7 @@ int ppc440spe_init_pcie_rootport(int port) * We use default settings for revB chip. */ if (!ppc440spe_revB()) - ppc440spe_setup_utl(port); + ppc4xx_setup_utl(port); /* * We map PCI Express configuration access into the 512MB regions @@ -620,7 +620,7 @@ int ppc440spe_init_pcie_rootport(int port) return 0; } -int ppc440spe_init_pcie_endport(int port) +int ppc4xx_init_pcie_endport(int port) { static int core_init; volatile u32 val = 0; @@ -628,7 +628,7 @@ int ppc440spe_init_pcie_endport(int port) if (!core_init) { ++core_init; - if (ppc440spe_init_pcie()) + if (ppc4xx_init_pcie()) return -1; } @@ -734,7 +734,7 @@ int ppc440spe_init_pcie_endport(int port) * We use default settings for revB chip. */ if (!ppc440spe_revB()) - ppc440spe_setup_utl(port); + ppc4xx_setup_utl(port); /* * We map PCI Express configuration access into the 512MB regions @@ -833,7 +833,7 @@ int ppc440spe_init_pcie_endport(int port) return 0; } -void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) +void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) { volatile void *mbase = NULL; volatile void *rmbase = NULL; @@ -951,7 +951,7 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) } -int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port) +int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) { volatile void *mbase = NULL; int attempts = 0; diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index 38745eb797c..220c60cd761 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -9,8 +9,8 @@ */ #include -#ifndef __440SPE_PCIE_H -#define __440SPE_PCIE_H +#ifndef __4XX_PCIE_H +#define __4XX_PCIE_H #define mdelay(n) ({unsigned long __ms=(n); while (__ms--) udelay(1000);}) @@ -164,11 +164,10 @@ #define GPL_DMER_MASK_DISA 0x02000000 -int ppc440spe_init_pcie(void); -int ppc440spe_init_pcie_rootport(int port); -void yucca_setup_pcie_fpga_rootpoint(int port); -void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port); -int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port); -int yucca_pcie_card_present(int port); +int ppc4xx_init_pcie(void); +int ppc4xx_init_pcie_rootport(int port); +void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port); +int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port); int pcie_hose_scan(struct pci_controller *hose, int bus); -#endif /* __440SPE_PCIE_H */ + +#endif /* __4XX_PCIE_H */ -- cgit v1.3.1 From 03d344bb6a5f082ea10ec9d753558ea7dfd1c626 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 3 Oct 2007 10:38:09 +0200 Subject: ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (3) (3) This patch introduces macros like SDRN_PESDR_DLPSET(port) to access the SDR registers of the PCIe ports. This makes the overall design clearer, since it removed a lot of switch statements which are not needed anymore. Also, the functions ppc4xx_init_pcie_rootport() and ppc4xx_init_pcie_entport() are merged into a single function ppc4xx_init_pcie_port(), since most of the code was duplicated. This makes maintainance and porting to other 4xx platforms easier. Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_pcie.c | 642 ++++++++++++++++----------------------------- include/asm-ppc/4xx_pcie.h | 101 ++++++- 2 files changed, 322 insertions(+), 421 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index c7b21417861..2bc9638f414 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -368,11 +368,167 @@ int ppc4xx_init_pcie(void) } /* - * Yucca board as End point and root point setup + * Board-specific pcie initialization + * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed + */ + +/* + * Initialize various parts of the PCI Express core for our port: + * + * - Set as a root port and enable max width + * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). + * - Set up UTL configuration. + * - Increase SERDES drive strength to levels suggested by AMCC. + * - De-assert RSTPYN, RSTDL and RSTGU. + * + * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it + * with default setting 0x11310000. The register has new fields, + * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core + * hang. + */ +#if defined(CONFIG_440SPE) +int __ppc4xx_init_pcie_port_hw(int port, int rootport) +{ + u32 val = 1 << 24; + u32 utlset1; + + if (rootport) { + val = PTYPE_ROOT_PORT << 20; + utlset1 = 0x21222222; + } else { + val = PTYPE_LEGACY_ENDPOINT << 20; + utlset1 = 0x20222222; + } + + if (port == 0) + val |= LNKW_X8 << 12; + else + val |= LNKW_X4 << 12; + + SDR_WRITE(SDRN_PESDR_DLPSET(port), val); + SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1); + if (!ppc440spe_revB()) + SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000); + SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000); + SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000); + SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000); + SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000); + if (port == 0) { + SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); + } + SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) & + ~(1 << 24 | 1 << 16)) | 1 << 12); + + return 0; +} +#endif /* CONFIG_440SPE */ + +#if defined(CONFIG_405EX) +int __ppc4xx_init_pcie_port_hw(int port, int rootport) +{ + u32 val; + + if (rootport) + val = 0x00401000; + else + val = 0x00101000; + + SDR_WRITE(SDRN_PESDR_DLPSET(port), val); + SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x20222222); + SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01110000); + SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000); + SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003); + + /* Assert the PE0_PHY reset */ + SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000); + udelay(1000); + + /* deassert the PE0_hotreset */ + SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000); + + /* poll for phy !reset */ + while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000)) + ; + + /* deassert the PE0_gpl_utl_reset */ + SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000); + + if (port == 0) + mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */ + else + mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */ + + return 0; +} +#endif /* CONFIG_405EX */ + +int ppc4xx_init_pcie_port_hw(int port, int rootport) + __attribute__((weak, alias("__ppc4xx_init_pcie_port_hw"))); + +/* + * We map PCI Express configuration access into the 512MB regions + * + * NOTICE: revB is very strict about PLB real addressess and ranges to + * be mapped for config space; it seems to only work with d_nnnn_nnnn + * range (hangs the core upon config transaction attempts when set + * otherwise) while revA uses c_nnnn_nnnn. + * + * For revA: + * PCIE0: 0xc_4000_0000 + * PCIE1: 0xc_8000_0000 + * PCIE2: 0xc_c000_0000 + * + * For revB: + * PCIE0: 0xd_0000_0000 + * PCIE1: 0xd_2000_0000 + * PCIE2: 0xd_4000_0000 + * + * For 405EX: + * PCIE0: 0xa000_0000 + * PCIE1: 0xc000_0000 + */ +static inline u64 ppc4xx_get_cfgaddr(int port) +{ +#if defined(CONFIG_405EX) + if (port == 0) + return (u64)CFG_PCIE0_CFGBASE; + else + return (u64)CFG_PCIE1_CFGBASE; +#endif +#if defined(CONFIG_440SPE) + if (ppc440spe_revB()) { + switch (port) { + default: /* to satisfy compiler */ + case 0: + return 0x0000000d00000000ULL; + case 1: + return 0x0000000d20000000ULL; + case 2: + return 0x0000000d40000000ULL; + } + } else { + switch (port) { + default: /* to satisfy compiler */ + case 0: + return 0x0000000c40000000ULL; + case 1: + return 0x0000000c80000000ULL; + case 2: + return 0x0000000cc0000000ULL; + } + } +#endif +} + +/* + * 4xx boards as end point and root point setup * and * testing inbound and out bound windows * - * YUCCA board can be plugged into another yucca board or you can get PCI-E + * 4xx boards can be plugged into another 4xx boards or you can get PCI-E * cable which can be used to setup loop back from one port to another port. * Please rememeber that unless there is a endpoint plugged in to root port it * will not initialize. It is the same in case of endpoint , unless there is @@ -386,26 +542,28 @@ int ppc4xx_init_pcie(void) * /proc/bus/pci/devices. Where you can see the configuration registers * of end point device attached to the port. * - * Enpoint cofiguration can be verified by connecting Yucca board to any - * host or another yucca board. Then try to scan the device. In case of + * Enpoint cofiguration can be verified by connecting 4xx board to any + * host or another 4xx board. Then try to scan the device. In case of * linux use "lspci" or appripriate os command. * - * How do I verify the inbound and out bound windows ?(yucca to yucca) + * How do I verify the inbound and out bound windows ? (4xx to 4xx) * in this configuration inbound and outbound windows are setup to access * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000, * This is waere your POM(PLB out bound memory window) mapped. then - * read the data from other yucca board's u-boot prompt at address + * read the data from other 4xx board's u-boot prompt at address * 0x9000 0000(SRAM). Data should match. * In case of inbound , write data to u-boot command prompt at 0xb000 0000 * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check * data at 0x9000 0000(SRAM).Data should match. */ -int ppc4xx_init_pcie_rootport(int port) +int ppc4xx_init_pcie_port(int port, int rootport) { static int core_init; volatile u32 val = 0; int attempts; + u64 addr; + u32 low, high; if (!core_init) { ++core_init; @@ -414,82 +572,17 @@ int ppc4xx_init_pcie_rootport(int port) } /* - * Initialize various parts of the PCI Express core for our port: - * - * - Set as a root port and enable max width - * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). - * - Set up UTL configuration. - * - Increase SERDES drive strength to levels suggested by AMCC. - * - De-assert RSTPYN, RSTDL and RSTGU. - * - * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with - * default setting 0x11310000. The register has new fields, - * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core - * hang. + * Initialize various parts of the PCI Express core for our port */ - switch (port) { - case 0: - SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12); - - SDR_WRITE(PESDR0_UTLSET1, 0x21222222); - if (!ppc440spe_revB()) - SDR_WRITE(PESDR0_UTLSET2, 0x11000000); - SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); - SDR_WRITE(PESDR0_RCSSET, - (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; + ppc4xx_init_pcie_port_hw(port, rootport); - case 1: - SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); - SDR_WRITE(PESDR1_UTLSET1, 0x21222222); - if (!ppc440spe_revB()) - SDR_WRITE(PESDR1_UTLSET2, 0x11000000); - SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000); - SDR_WRITE(PESDR1_RCSSET, - (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; - - case 2: - SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); - SDR_WRITE(PESDR2_UTLSET1, 0x21222222); - if (!ppc440spe_revB()) - SDR_WRITE(PESDR2_UTLSET2, 0x11000000); - SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000); - SDR_WRITE(PESDR2_RCSSET, - (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; - } /* * Notice: the following delay has critical impact on device * initialization - if too short (<50ms) the link doesn't get up. */ mdelay(100); - switch (port) { - case 0: - val = SDR_READ(PESDR0_RCSSTS); - break; - case 1: - val = SDR_READ(PESDR1_RCSSTS); - break; - case 2: - val = SDR_READ(PESDR2_RCSSTS); - break; - } - + val = SDR_READ(SDRN_PESDR_RCSSTS(sdr_base(port))); if (val & (1 << 20)) { printf("PCIE%d: PGRST failed %08x\n", port, val); return -1; @@ -498,18 +591,7 @@ int ppc4xx_init_pcie_rootport(int port) /* * Verify link is up */ - val = 0; - switch (port) { - case 0: - val = SDR_READ(PESDR0_LOOP); - break; - case 1: - val = SDR_READ(PESDR1_LOOP); - break; - case 2: - val = SDR_READ(PESDR2_LOOP); - break; - } + val = SDR_READ(SDRN_PESDR_LOOP(sdr_base(port))); if (!(val & 0x00001000)) { printf("PCIE%d: link is not up.\n", port); return -1; @@ -524,55 +606,25 @@ int ppc4xx_init_pcie_rootport(int port) /* * We map PCI Express configuration access into the 512MB regions - * - * NOTICE: revB is very strict about PLB real addressess and ranges to - * be mapped for config space; it seems to only work with d_nnnn_nnnn - * range (hangs the core upon config transaction attempts when set - * otherwise) while revA uses c_nnnn_nnnn. - * - * For revA: - * PCIE0: 0xc_4000_0000 - * PCIE1: 0xc_8000_0000 - * PCIE2: 0xc_c000_0000 - * - * For revB: - * PCIE0: 0xd_0000_0000 - * PCIE1: 0xd_2000_0000 - * PCIE2: 0xd_4000_0000 */ + addr = ppc4xx_get_cfgaddr(port); + low = (u32)(addr & 0x00000000ffffffff); + high = (u32)(addr >> 32); switch (port) { case 0: - if (ppc440spe_revB()) { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000); - } else { - /* revA */ - mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000); - } + mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low); mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ break; - case 1: - if (ppc440spe_revB()) { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000); - } else { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000); - } + mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low); mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ break; - case 2: - if (ppc440spe_revB()) { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000); - } else { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000); - } + mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low); mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ break; } @@ -581,256 +633,28 @@ int ppc4xx_init_pcie_rootport(int port) * Check for VC0 active and assert RDY. */ attempts = 10; - switch (port) { - case 0: - while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) { - if (!(attempts--)) { - printf("PCIE0: VC0 not active\n"); - return -1; - } - mdelay(1000); - } - SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20); - break; - case 1: - while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) { - if (!(attempts--)) { - printf("PCIE1: VC0 not active\n"); - return -1; - } - mdelay(1000); - } - - SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20); - break; - case 2: - while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) { - if (!(attempts--)) { - printf("PCIE2: VC0 not active\n"); - return -1; - } - mdelay(1000); + while(!(SDR_READ(SDRN_PESDR_RCSSTS(sdr_base(port))) & (1 << 16))) { + if (!(attempts--)) { + printf("PCIE%d: VC0 not active\n", port); + return -1; } - - SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20); - break; + mdelay(1000); } + SDR_WRITE(SDRN_PESDR_RCSSET(sdr_base(port)), + SDR_READ(SDRN_PESDR_RCSSET(sdr_base(port))) | 1 << 20); mdelay(100); return 0; } -int ppc4xx_init_pcie_endport(int port) +int ppc4xx_init_pcie_rootport(int port) { - static int core_init; - volatile u32 val = 0; - int attempts; - - if (!core_init) { - ++core_init; - if (ppc4xx_init_pcie()) - return -1; - } - - /* - * Initialize various parts of the PCI Express core for our port: - * - * - Set as a end port and enable max width - * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). - * - Set up UTL configuration. - * - Increase SERDES drive strength to levels suggested by AMCC. - * - De-assert RSTPYN, RSTDL and RSTGU. - * - * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with - * default setting 0x11310000. The register has new fields, - * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core - * hang. - */ - switch (port) { - case 0: - SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X8 << 12); - - SDR_WRITE(PESDR0_UTLSET1, 0x20222222); - if (!ppc440spe_revB()) - SDR_WRITE(PESDR0_UTLSET2, 0x11000000); - SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); - SDR_WRITE(PESDR0_RCSSET, - (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; - - case 1: - SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12); - SDR_WRITE(PESDR1_UTLSET1, 0x20222222); - if (!ppc440spe_revB()) - SDR_WRITE(PESDR1_UTLSET2, 0x11000000); - SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000); - SDR_WRITE(PESDR1_RCSSET, - (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; - - case 2: - SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12); - SDR_WRITE(PESDR2_UTLSET1, 0x20222222); - if (!ppc440spe_revB()) - SDR_WRITE(PESDR2_UTLSET2, 0x11000000); - SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000); - SDR_WRITE(PESDR2_RCSSET, - (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; - } - /* - * Notice: the following delay has critical impact on device - * initialization - if too short (<50ms) the link doesn't get up. - */ - mdelay(100); - - switch (port) { - case 0: val = SDR_READ(PESDR0_RCSSTS); break; - case 1: val = SDR_READ(PESDR1_RCSSTS); break; - case 2: val = SDR_READ(PESDR2_RCSSTS); break; - } - - if (val & (1 << 20)) { - printf("PCIE%d: PGRST failed %08x\n", port, val); - return -1; - } - - /* - * Verify link is up - */ - val = 0; - switch (port) - { - case 0: - val = SDR_READ(PESDR0_LOOP); - break; - case 1: - val = SDR_READ(PESDR1_LOOP); - break; - case 2: - val = SDR_READ(PESDR2_LOOP); - break; - } - if (!(val & 0x00001000)) { - printf("PCIE%d: link is not up.\n", port); - return -1; - } - - /* - * Setup UTL registers - but only on revA! - * We use default settings for revB chip. - */ - if (!ppc440spe_revB()) - ppc4xx_setup_utl(port); - - /* - * We map PCI Express configuration access into the 512MB regions - * - * NOTICE: revB is very strict about PLB real addressess and ranges to - * be mapped for config space; it seems to only work with d_nnnn_nnnn - * range (hangs the core upon config transaction attempts when set - * otherwise) while revA uses c_nnnn_nnnn. - * - * For revA: - * PCIE0: 0xc_4000_0000 - * PCIE1: 0xc_8000_0000 - * PCIE2: 0xc_c000_0000 - * - * For revB: - * PCIE0: 0xd_0000_0000 - * PCIE1: 0xd_2000_0000 - * PCIE2: 0xd_4000_0000 - */ - switch (port) { - case 0: - if (ppc440spe_revB()) { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000); - } else { - /* revA */ - mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000); - } - mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ - break; - - case 1: - if (ppc440spe_revB()) { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000); - } else { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000); - } - mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ - break; - - case 2: - if (ppc440spe_revB()) { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000); - } else { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000); - } - mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ - break; - } - - /* - * Check for VC0 active and assert RDY. - */ - attempts = 10; - switch (port) { - case 0: - while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) { - if (!(attempts--)) { - printf("PCIE0: VC0 not active\n"); - return -1; - } - mdelay(1000); - } - SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20); - break; - case 1: - while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) { - if (!(attempts--)) { - printf("PCIE1: VC0 not active\n"); - return -1; - } - mdelay(1000); - } - - SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20); - break; - case 2: - while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) { - if (!(attempts--)) { - printf("PCIE2: VC0 not active\n"); - return -1; - } - mdelay(1000); - } - - SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20); - break; - } - mdelay(100); + return ppc4xx_init_pcie_port(port, 1); +} - return 0; +int ppc4xx_init_pcie_endport(int port) +{ + return ppc4xx_init_pcie_port(port, 0); } void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) @@ -839,12 +663,12 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) volatile void *rmbase = NULL; pci_set_ops(hose, - pcie_read_config_byte, - pcie_read_config_word, - pcie_read_config_dword, - pcie_write_config_byte, - pcie_write_config_word, - pcie_write_config_dword); + pcie_read_config_byte, + pcie_read_config_word, + pcie_read_config_dword, + pcie_write_config_byte, + pcie_write_config_word, + pcie_write_config_dword); switch (port) { case 0: @@ -884,26 +708,26 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) case 0: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE); + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), - ~(CFG_PCIE_MEMSIZE - 1) | 3); + ~(CFG_PCIE_MEMSIZE - 1) | 3); break; case 1: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE)); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), - ~(CFG_PCIE_MEMSIZE - 1) | 3); + ~(CFG_PCIE_MEMSIZE - 1) | 3); break; case 2: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE)); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), - ~(CFG_PCIE_MEMSIZE - 1) | 3); + ~(CFG_PCIE_MEMSIZE - 1) | 3); break; } @@ -925,7 +749,6 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) out_le16((u16 *)(mbase + PCI_COMMAND), in_le16((u16 *)(mbase + PCI_COMMAND)) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - printf("PCIE:%d successfully set as rootpoint\n",port); /* Set Device and Vendor Id */ switch (port) { @@ -949,6 +772,7 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ out_le32(mbase + 0x208, 0x06040001); + printf("PCIE:%d successfully set as rootpoint\n", port); } int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) @@ -992,26 +816,26 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) case 0: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE); + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), - ~(CFG_PCIE_MEMSIZE - 1) | 3); + ~(CFG_PCIE_MEMSIZE - 1) | 3); break; case 1: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE)); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), - ~(CFG_PCIE_MEMSIZE - 1) | 3); + ~(CFG_PCIE_MEMSIZE - 1) | 3); break; case 2: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE)); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), - ~(CFG_PCIE_MEMSIZE - 1) | 3); + ~(CFG_PCIE_MEMSIZE - 1) | 3); break; } @@ -1026,40 +850,20 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) /* Enable I/O, Mem, and Busmaster cycles */ out_le16((u16 *)(mbase + PCI_COMMAND), - in_le16((u16 *)(mbase + PCI_COMMAND)) | - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + in_le16((u16 *)(mbase + PCI_COMMAND)) | + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */ out_le16(mbase + 0x202,0xfeed); /* Setting device ID */ + attempts = 10; - switch (port) { - case 0: - while (!(SDR_READ(PESDR0_RCSSTS) & (1 << 8))) { - if (!(attempts--)) { - printf("PCIE0: BMEN is not active\n"); - return -1; - } - mdelay(1000); - } - break; - case 1: - while (!(SDR_READ(PESDR1_RCSSTS) & (1 << 8))) { - if (!(attempts--)) { - printf("PCIE1: BMEN is not active\n"); - return -1; - } - mdelay(1000); - } - break; - case 2: - while (!(SDR_READ(PESDR2_RCSSTS) & (1 << 8))) { - if (!(attempts--)) { - printf("PCIE2: BMEN is not active\n"); - return -1; - } - mdelay(1000); + while(!(SDR_READ(SDRN_PESDR_RCSSTS(sdr_base(port))) & (1 << 8))) { + if (!(attempts--)) { + printf("PCIE%d: BME not active\n", port); + return -1; } - break; + mdelay(1000); } + printf("PCIE:%d successfully set as endpoint\n",port); return 0; diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index 220c60cd761..1bb8fc7ed13 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -12,14 +12,20 @@ #ifndef __4XX_PCIE_H #define __4XX_PCIE_H -#define mdelay(n) ({unsigned long __ms=(n); while (__ms--) udelay(1000);}) - #define DCRN_SDR0_CFGADDR 0x00e #define DCRN_SDR0_CFGDATA 0x00f +#if defined(CONFIG_440SPE) #define DCRN_PCIE0_BASE 0x100 #define DCRN_PCIE1_BASE 0x120 #define DCRN_PCIE2_BASE 0x140 +#endif + +#if defined(CONFIG_405EX) +#define DCRN_PCIE0_BASE 0x040 +#define DCRN_PCIE1_BASE 0x060 +#endif + #define PCIE0 DCRN_PCIE0_BASE #define PCIE1 DCRN_PCIE1_BASE #define PCIE2 DCRN_PCIE2_BASE @@ -47,6 +53,39 @@ #define PESDR0_PLLLCT2 0x03a1 #define PESDR0_PLLLCT3 0x03a2 +#if defined(CONFIG_440SPE) +#define PCIE0_SDR 0x300 +#define PCIE1_SDR 0x340 +#define PCIE2_SDR 0x370 +#endif + +#if defined(CONFIG_405EX) +#define PCIE0_SDR 0x400 +#define PCIE1_SDR 0x440 +#endif + +/* common regs, at least for 405EX and 440SPe */ +#define SDRN_PESDR_UTLSET1(n) (sdr_base(n) + 0x00) +#define SDRN_PESDR_UTLSET2(n) (sdr_base(n) + 0x01) +#define SDRN_PESDR_DLPSET(n) (sdr_base(n) + 0x02) +#define SDRN_PESDR_LOOP(n) (sdr_base(n) + 0x03) +#define SDRN_PESDR_RCSSET(n) (sdr_base(n) + 0x04) +#define SDRN_PESDR_RCSSTS(n) (sdr_base(n) + 0x05) + +#if defined(CONFIG_440SPE) +#define SDRN_PESDR_HSSL0SET1(n) (sdr_base(n) + 0x06) +#define SDRN_PESDR_HSSL0SET2(n) (sdr_base(n) + 0x07) +#define SDRN_PESDR_HSSL0STS(n) (sdr_base(n) + 0x08) +#define SDRN_PESDR_HSSL1SET1(n) (sdr_base(n) + 0x09) +#define SDRN_PESDR_HSSL1SET2(n) (sdr_base(n) + 0x0a) +#define SDRN_PESDR_HSSL1STS(n) (sdr_base(n) + 0x0b) +#define SDRN_PESDR_HSSL2SET1(n) (sdr_base(n) + 0x0c) +#define SDRN_PESDR_HSSL2SET2(n) (sdr_base(n) + 0x0d) +#define SDRN_PESDR_HSSL2STS(n) (sdr_base(n) + 0x0e) +#define SDRN_PESDR_HSSL3SET1(n) (sdr_base(n) + 0x0f) +#define SDRN_PESDR_HSSL3SET2(n) (sdr_base(n) + 0x10) +#define SDRN_PESDR_HSSL3STS(n) (sdr_base(n) + 0x11) + #define PESDR0_UTLSET1 0x0300 #define PESDR0_UTLSET2 0x0301 #define PESDR0_DLPSET 0x0302 @@ -123,6 +162,40 @@ #define PESDR2_HSSCTLSET 0x0382 #define PESDR2_LANE_ABCD 0x0383 +#elif defined(CONFIG_405EX) + +#define SDRN_PESDR_PHYSET1(n) (sdr_base(n) + 0x06) +#define SDRN_PESDR_PHYSET2(n) (sdr_base(n) + 0x07) +#define SDRN_PESDR_BIST(n) (sdr_base(n) + 0x08) +#define SDRN_PESDR_LPB(n) (sdr_base(n) + 0x0b) +#define SDRN_PESDR_PHYSTA(n) (sdr_base(n) + 0x0c) + +#define PESDR0_UTLSET1 0x0400 +#define PESDR0_UTLSET2 0x0401 +#define PESDR0_DLPSET 0x0402 +#define PESDR0_LOOP 0x0403 +#define PESDR0_RCSSET 0x0404 +#define PESDR0_RCSSTS 0x0405 +#define PESDR0_PHYSET1 0x0406 +#define PESDR0_PHYSET2 0x0407 +#define PESDR0_BIST 0x0408 +#define PESDR0_LPB 0x040B +#define PESDR0_PHYSTA 0x040C + +#define PESDR1_UTLSET1 0x0440 +#define PESDR1_UTLSET2 0x0441 +#define PESDR1_DLPSET 0x0442 +#define PESDR1_LOOP 0x0443 +#define PESDR1_RCSSET 0x0444 +#define PESDR1_RCSSTS 0x0445 +#define PESDR1_PHYSET1 0x0446 +#define PESDR1_PHYSET2 0x0447 +#define PESDR1_BIST 0x0448 +#define PESDR1_LPB 0x044B +#define PESDR1_PHYSTA 0x044C + +#endif + /* * UTL register offsets */ @@ -166,8 +239,32 @@ int ppc4xx_init_pcie(void); int ppc4xx_init_pcie_rootport(int port); +int ppc4xx_init_pcie_endport(int port); void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port); int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port); int pcie_hose_scan(struct pci_controller *hose, int bus); +static inline void mdelay(int n) +{ + u32 ms = n; + + while (ms--) + udelay(1000); +} + +static inline u32 sdr_base(int port) +{ + switch (port) { + default: /* to satisfy compiler */ + case 0: + return PCIE0_SDR; + case 1: + return PCIE1_SDR; +#if defined(PCIE2_SDR) + case 2: + return PCIE2_SDR; +#endif + } +} + #endif /* __4XX_PCIE_H */ -- cgit v1.3.1 From 94276eb0a7a35b9e8c053d589ae225b0f017a237 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 3 Oct 2007 14:14:58 +0200 Subject: ppc4xx: Add a comment for 405EX PCIe endpoint configuration Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_pcie.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index 2bc9638f414..177e2ad2e7a 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -431,6 +431,12 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport) { u32 val; + /* + * test-only: + * This needs some testing and perhaps changes for + * endpoint configuration. Probably no PHY reset at all, etc. + * sr, 2007-10-03 + */ if (rootport) val = 0x00401000; else -- cgit v1.3.1 From 3048bcbf0bad262378c5af68f2bf6778fb7d829a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 3 Oct 2007 15:01:02 +0200 Subject: ppc4xx: Rename 405gp_pci to 4xx_pci since its used on all 4xx platforms These files were introduced with the IBM 405GP but are currently used on all 4xx PPC platforms. So the name doesn't match the content anymore. This patch renames the files to 4xx_pci.c/h. Signed-off-by: Stefan Roese --- board/esd/ocrtc/cmd_ocrtc.c | 2 +- board/esd/pci405/cmd_pci405.c | 2 +- board/esd/pci405/pci405.c | 2 +- board/mpl/common/common_util.c | 4 +- board/mpl/common/flash.c | 2 +- common/usb.c | 2 +- cpu/ppc4xx/405gp_pci.c | 595 ----------------------------------------- cpu/ppc4xx/4xx_pci.c | 595 +++++++++++++++++++++++++++++++++++++++++ cpu/ppc4xx/Makefile | 6 +- include/405gp_pci.h | 52 ---- include/asm-ppc/4xx_pci.h | 52 ++++ 11 files changed, 657 insertions(+), 657 deletions(-) delete mode 100644 cpu/ppc4xx/405gp_pci.c create mode 100644 cpu/ppc4xx/4xx_pci.c delete mode 100644 include/405gp_pci.h create mode 100644 include/asm-ppc/4xx_pci.h (limited to 'cpu') diff --git a/board/esd/ocrtc/cmd_ocrtc.c b/board/esd/ocrtc/cmd_ocrtc.c index 4177f68ef4d..f83dfe870bc 100644 --- a/board/esd/ocrtc/cmd_ocrtc.c +++ b/board/esd/ocrtc/cmd_ocrtc.c @@ -25,7 +25,7 @@ #include #include #include -#include <405gp_pci.h> +#include #if defined(CONFIG_CMD_BSP) diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c index 5b5ad8c4465..9a0bf1e3603 100644 --- a/board/esd/pci405/cmd_pci405.c +++ b/board/esd/pci405/cmd_pci405.c @@ -27,7 +27,7 @@ #include #include #include -#include <405gp_pci.h> +#include #include #include "pci405.h" diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index e5d2273f07f..c4ab0720091 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -26,7 +26,7 @@ #include #include #include -#include <405gp_pci.h> +#include #include "pci405.h" diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index 278ad5c3488..f3aa0a73007 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -36,11 +36,11 @@ #ifdef CONFIG_PIP405 #include "../pip405/pip405.h" -#include <405gp_pci.h> +#include #endif #ifdef CONFIG_MIP405 #include "../mip405/mip405.h" -#include <405gp_pci.h> +#include #endif DECLARE_GLOBAL_DATA_PTR; diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c index fd430083e2f..6f53192ac75 100644 --- a/board/mpl/common/flash.c +++ b/board/mpl/common/flash.c @@ -47,7 +47,7 @@ #if defined(CONFIG_PIP405) #include "../pip405/pip405.h" #endif -#include <405gp_pci.h> +#include #else /* defined(CONFIG_PATI) */ #include #endif diff --git a/common/usb.c b/common/usb.c index 933afa9e7bc..4df01eabe51 100644 --- a/common/usb.c +++ b/common/usb.c @@ -53,7 +53,7 @@ #include #ifdef CONFIG_4xx -#include <405gp_pci.h> +#include #endif #undef USB_DEBUG diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c deleted file mode 100644 index 282e7a1ba47..00000000000 --- a/cpu/ppc4xx/405gp_pci.c +++ /dev/null @@ -1,595 +0,0 @@ -/*-----------------------------------------------------------------------------+ - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - *-----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ - * - * File Name: 405gp_pci.c - * - * Function: Initialization code for the 405GP PCI Configuration regs. - * - * Author: Mark Game - * - * Change Activity- - * - * Date Description of Change BY - * --------- --------------------- --- - * 09-Sep-98 Created MCG - * 02-Nov-98 Removed External arbiter selected message JWB - * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB - * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG - * from (0 to n) to (1 to n). - * 17-May-99 Port to Walnut JWB - * 17-Jun-99 Updated for VGA support JWB - * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB - * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG - * target latency timer values are not supported). - * Should be fixed in pass 2. - * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB - * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS. - * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB - * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not - * really required after a reset since PMMxMAs are already - * disabled but is a good practice nonetheless. JWB - * 12-Jun-01 stefan.roese@esd-electronics.com - * - PCI host/adapter handling reworked - * 09-Jul-01 stefan.roese@esd-electronics.com - * - PCI host now configures from device 0 (not 1) to max_dev, - * (host configures itself) - * - On CPCI-405 pci base address and size is generated from - * SDRAM and FLASH size (CFG regs not used anymore) - * - Some minor changes for CPCI-405-A (adapter version) - * 14-Sep-01 stefan.roese@esd-electronics.com - * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup - * 28-Sep-01 stefan.roese@esd-electronics.com - * - Changed pci master configuration for linux compatibility - * (no need for bios_fixup() anymore) - * 26-Feb-02 stefan.roese@esd-electronics.com - * - Bug fixed in pci configuration (Andrew May) - * - Removed pci class code init for CPCI405 board - * 15-May-02 stefan.roese@esd-electronics.com - * - New vga device handling - * 29-May-02 stefan.roese@esd-electronics.com - * - PCI class code init added (if defined) - *----------------------------------------------------------------------------*/ - -#include -#include -#if !defined(CONFIG_440) -#include <405gp_pci.h> -#endif -#include -#include - -#ifdef CONFIG_PCI - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Board-specific pci initialization - * Platform code can reimplement pci_pre_init() if needed - */ -int __pci_pre_init(struct pci_controller *hose) -{ - return 1; -} -int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init"))); - -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) - -#if defined(CONFIG_PMC405) -ushort pmc405_pci_subsys_deviceid(void); -#endif - -/*#define DEBUG*/ - -/*-----------------------------------------------------------------------------+ - * pci_init. Initializes the 405GP PCI Configuration regs. - *-----------------------------------------------------------------------------*/ -void pci_405gp_init(struct pci_controller *hose) -{ - int i, reg_num = 0; - bd_t *bd = gd->bd; - - unsigned short temp_short; - unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI}; -#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405) - char *ptmla_str, *ptmms_str; -#endif - unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA}; - unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS}; -#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405) - unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0}; - unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0}; - unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0}; - unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0}; -#else - unsigned long pmmla[3] = {0x80000000, 0,0}; - unsigned long pmmma[3] = {0xC0000001, 0,0}; - unsigned long pmmpcila[3] = {0x80000000, 0,0}; - unsigned long pmmpciha[3] = {0x00000000, 0,0}; -#endif -#ifdef CONFIG_PCI_PNP -#if (CONFIG_PCI_HOST == PCI_HOST_AUTO) - char *s; -#endif -#endif - -#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405) - ptmla_str = getenv("ptm1la"); - ptmms_str = getenv("ptm1ms"); - if(NULL != ptmla_str && NULL != ptmms_str ) { - ptmla[0] = simple_strtoul (ptmla_str, NULL, 16); - ptmms[0] = simple_strtoul (ptmms_str, NULL, 16); - } - - ptmla_str = getenv("ptm2la"); - ptmms_str = getenv("ptm2ms"); - if(NULL != ptmla_str && NULL != ptmms_str ) { - ptmla[1] = simple_strtoul (ptmla_str, NULL, 16); - ptmms[1] = simple_strtoul (ptmms_str, NULL, 16); - } -#endif - - /* - * Register the hose - */ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* ISA/PCI I/O space */ - pci_set_region(hose->regions + reg_num++, - MIN_PCI_PCI_IOADDR, - MIN_PLB_PCI_IOADDR, - 0x10000, - PCI_REGION_IO); - - /* PCI I/O space */ - pci_set_region(hose->regions + reg_num++, - 0x00800000, - 0xe8800000, - 0x03800000, - PCI_REGION_IO); - - reg_num = 2; - - /* Memory spaces */ - for (i=0; i<2; i++) - if (ptmms[i] & 1) - { - if (!i) hose->pci_fb = hose->regions + reg_num; - - pci_set_region(hose->regions + reg_num++, - ptmpcila[i], ptmla[i], - ~(ptmms[i] & 0xfffff000) + 1, - PCI_REGION_MEM | - PCI_REGION_MEMORY); - } - - /* PCI memory spaces */ - for (i=0; i<3; i++) - if (pmmma[i] & 1) - { - pci_set_region(hose->regions + reg_num++, - pmmpcila[i], pmmla[i], - ~(pmmma[i] & 0xfffff000) + 1, - PCI_REGION_MEM); - } - - hose->region_count = reg_num; - - pci_setup_indirect(hose, - PCICFGADR, - PCICFGDATA); - - if (hose->pci_fb) - pciauto_region_init(hose->pci_fb); - - /* Let board change/modify hose & do initial checks */ - if (pci_pre_init (hose) == 0) { - printf("PCI: Board-specific initialization failed.\n"); - printf("PCI: Configuration aborted.\n"); - return; - } - - pci_register_hose(hose); - - /*--------------------------------------------------------------------------+ - * 405GP PCI Master configuration. - * Map one 512 MB range of PLB/processor addresses to PCI memory space. - * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF - * Use byte reversed out routines to handle endianess. - *--------------------------------------------------------------------------*/ - out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */ - out32r(PMM0LA, pmmla[0]); - out32r(PMM0PCILA, pmmpcila[0]); - out32r(PMM0PCIHA, pmmpciha[0]); - out32r(PMM0MA, pmmma[0]); - - /*--------------------------------------------------------------------------+ - * PMM1 is not used. Initialize them to zero. - *--------------------------------------------------------------------------*/ - out32r(PMM1MA, (pmmma[1]&~0x1)); - out32r(PMM1LA, pmmla[1]); - out32r(PMM1PCILA, pmmpcila[1]); - out32r(PMM1PCIHA, pmmpciha[1]); - out32r(PMM1MA, pmmma[1]); - - /*--------------------------------------------------------------------------+ - * PMM2 is not used. Initialize them to zero. - *--------------------------------------------------------------------------*/ - out32r(PMM2MA, (pmmma[2]&~0x1)); - out32r(PMM2LA, pmmla[2]); - out32r(PMM2PCILA, pmmpcila[2]); - out32r(PMM2PCIHA, pmmpciha[2]); - out32r(PMM2MA, pmmma[2]); - - /*--------------------------------------------------------------------------+ - * 405GP PCI Target configuration. (PTM1) - * Note: PTM1MS is hardwire enabled but we set the enable bit anyway. - *--------------------------------------------------------------------------*/ - out32r(PTM1LA, ptmla[0]); /* insert address */ - out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */ - pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]); - - /*--------------------------------------------------------------------------+ - * 405GP PCI Target configuration. (PTM2) - *--------------------------------------------------------------------------*/ - out32r(PTM2LA, ptmla[1]); /* insert address */ - pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]); - - if (ptmms[1] == 0) - { - out32r(PTM2MS, 0x00000001); /* set enable bit */ - pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000); - out32r(PTM2MS, 0x00000000); /* disable */ - } - else - { - out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */ - } - - /* - * Insert Subsystem Vendor and Device ID - */ - pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID); -#ifdef CONFIG_CPCI405 - if (mfdcr(strap) & PSR_PCI_ARBIT_EN) - pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID); - else - pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2); -#else - pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID); -#endif - - /* - * Insert Class-code - */ -#ifdef CFG_PCI_CLASSCODE - pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE); -#endif /* CFG_PCI_CLASSCODE */ - - /*--------------------------------------------------------------------------+ - * If PCI speed = 66Mhz, set 66Mhz capable bit. - *--------------------------------------------------------------------------*/ - if (bd->bi_pci_busfreq >= 66000000) { - pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short); - pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ)); - } - -#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER) -#if (CONFIG_PCI_HOST == PCI_HOST_AUTO) - if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) || - (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) -#endif - { - /*--------------------------------------------------------------------------+ - * Write the 405GP PCI Configuration regs. - * Enable 405GP to be a master on the PCI bus (PMM). - * Enable 405GP to act as a PCI memory target (PTM). - *--------------------------------------------------------------------------*/ - pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short); - pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short | - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - } -#endif - -#if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */ - pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014); /* IBM */ -#endif - - /* - * Set HCE bit (Host Configuration Enabled) - */ - pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short); - pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001)); - -#ifdef CONFIG_PCI_PNP - /*--------------------------------------------------------------------------+ - * Scan the PCI bus and configure devices found. - *--------------------------------------------------------------------------*/ -#if (CONFIG_PCI_HOST == PCI_HOST_AUTO) - if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) || - (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) -#endif - { -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - hose->last_busno = pci_hose_scan(hose); - } -#endif /* CONFIG_PCI_PNP */ - -} - -/* - * drivers/pci.c skips every host bridge but the 405GP since it could - * be set as an Adapter. - * - * I (Andrew May) don't know what we should do here, but I don't want - * the auto setup of a PCI device disabling what is done pci_405gp_init - * as has happened before. - */ -void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *entry) -{ -#ifdef DEBUG - printf("405gp_setup_bridge\n"); -#endif -} - -/* - * - */ - -void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char int_line = 0xff; - - /* - * Write pci interrupt line register (cpci405 specific) - */ - switch (PCI_DEV(dev) & 0x03) - { - case 0: - int_line = 27 + 2; - break; - case 1: - int_line = 27 + 3; - break; - case 2: - int_line = 27 + 0; - break; - case 3: - int_line = 27 + 1; - break; - } - - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); -} - -void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *entry) -{ - unsigned int cmdstat = 0; - - pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io); - - /* always enable io space on vga boards */ - pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); - cmdstat |= PCI_COMMAND_IO; - pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); -} - -#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3)) - -/* - *As is these functs get called out of flash Not a horrible - *thing, but something to keep in mind. (no statics?) - */ -static struct pci_config_table pci_405gp_config_table[] = { -/*if VendID is 0 it terminates the table search (ie Walnut)*/ -#ifdef CFG_PCI_SUBSYS_VENDORID - {CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge}, -#endif - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, - - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, - - { } -}; - -static struct pci_controller hose = { - fixup_irq: pci_405gp_fixup_irq, - config_table: pci_405gp_config_table, -}; - -void pci_init_board(void) -{ - /*we want the ptrs to RAM not flash (ie don't use init list)*/ - hose.fixup_irq = pci_405gp_fixup_irq; - hose.config_table = pci_405gp_config_table; - pci_405gp_init(&hose); -} - -#endif - -#endif /* CONFIG_405GP */ - -/*-----------------------------------------------------------------------------+ - * CONFIG_440 - *-----------------------------------------------------------------------------*/ -#if defined(CONFIG_440) - -static struct pci_controller ppc440_hose = {0}; - - -int pci_440_init (struct pci_controller *hose) -{ - int reg_num = 0; - -#ifndef CONFIG_DISABLE_PISE_TEST - /*--------------------------------------------------------------------------+ - * The PCI initialization sequence enable bit must be set ... if not abort - * pci setup since updating the bit requires chip reset. - *--------------------------------------------------------------------------*/ -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) - unsigned long strap; - - mfsdr(sdr_sdstp1,strap); - if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) { - printf("PCI: SDR0_STRP1[PISE] not set.\n"); - printf("PCI: Configuration aborted.\n"); - return -1; - } -#elif defined(CONFIG_440GP) - unsigned long strap; - - strap = mfdcr(cpc0_strp1); - if ((strap & CPC0_STRP1_PISE_MASK) == 0) { - printf("PCI: CPC0_STRP1[PISE] not set.\n"); - printf("PCI: Configuration aborted.\n"); - return -1; - } -#endif -#endif /* CONFIG_DISABLE_PISE_TEST */ - - /*--------------------------------------------------------------------------+ - * PCI controller init - *--------------------------------------------------------------------------*/ - hose->first_busno = 0; - hose->last_busno = 0; - - /* PCI I/O space */ - pci_set_region(hose->regions + reg_num++, - 0x00000000, - PCIX0_IOBASE, - 0x10000, - PCI_REGION_IO); - - /* PCI memory space */ - pci_set_region(hose->regions + reg_num++, - CFG_PCI_TARGBASE, - CFG_PCI_MEMBASE, -#ifdef CFG_PCI_MEMSIZE - CFG_PCI_MEMSIZE, -#else - 0x10000000, -#endif - PCI_REGION_MEM ); - -#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \ - defined(CONFIG_PCI_SYS_MEM_SIZE) - /* System memory space */ - pci_set_region(hose->regions + reg_num++, - CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - CONFIG_PCI_SYS_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY ); -#endif - - hose->region_count = reg_num; - - pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA); - - /* Let board change/modify hose & do initial checks */ - if (pci_pre_init (hose) == 0) { - printf("PCI: Board-specific initialization failed.\n"); - printf("PCI: Configuration aborted.\n"); - return -1; - } - - pci_register_hose( hose ); - - /*--------------------------------------------------------------------------+ - * PCI target init - *--------------------------------------------------------------------------*/ -#if defined(CFG_PCI_TARGET_INIT) - pci_target_init(hose); /* Let board setup pci target */ -#else - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID ); - out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ -#endif - -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) - out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ - out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ -#elif defined(PCIX0_BRDGOPT1) - out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ - out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */ -#endif - - /*--------------------------------------------------------------------------+ - * PCI master init: default is one 256MB region for PCI memory: - * 0x3_00000000 - 0x3_0FFFFFFF ==> CFG_PCI_MEMBASE - *--------------------------------------------------------------------------*/ -#if defined(CFG_PCI_MASTER_INIT) - pci_master_init(hose); /* Let board setup pci master */ -#else - out32r( PCIX0_POM0SA, 0 ); /* disable */ - out32r( PCIX0_POM1SA, 0 ); /* disable */ - out32r( PCIX0_POM2SA, 0 ); /* disable */ -#if defined(CONFIG_440SPE) - out32r( PCIX0_POM0LAL, 0x10000000 ); - out32r( PCIX0_POM0LAH, 0x0000000c ); -#else - out32r( PCIX0_POM0LAL, 0x00000000 ); - out32r( PCIX0_POM0LAH, 0x00000003 ); -#endif - out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE ); - out32r( PCIX0_POM0PCIAH, 0x00000000 ); - out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */ - out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 ); -#endif - - /*--------------------------------------------------------------------------+ - * PCI host configuration -- we don't make any assumptions here ... the - * _board_must_indicate_ what to do -- there's just too many runtime - * scenarios in environments like cPCI, PPMC, etc. to make a determination - * based on hard-coded values or state of arbiter enable. - *--------------------------------------------------------------------------*/ - if (is_pci_host(hose)) { -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif -#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \ - !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) - out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER); -#endif - hose->last_busno = pci_hose_scan(hose); - } - return hose->last_busno; -} - -void pci_init_board(void) -{ - int busno; - - busno = pci_440_init (&ppc440_hose); -#if defined(CONFIG_440SPE) - pcie_setup_hoses(busno + 1); -#endif -} - -#endif /* CONFIG_440 */ -#endif /* CONFIG_PCI */ diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c new file mode 100644 index 00000000000..e6170517ae6 --- /dev/null +++ b/cpu/ppc4xx/4xx_pci.c @@ -0,0 +1,595 @@ +/*-----------------------------------------------------------------------------+ + * + * This source code has been made available to you by IBM on an AS-IS + * basis. Anyone receiving this source is licensed under IBM + * copyrights to use it in any way he or she deems fit, including + * copying it, modifying it, compiling it, and redistributing it either + * with or without modifications. No license under IBM patents or + * patent applications is to be implied by the copyright license. + * + * Any user of this software should understand that IBM cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work + * must include the IBM copyright notice, this paragraph, and the + * preceding two paragraphs in the transferred software. + * + * COPYRIGHT I B M CORPORATION 1995 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + *-----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------+ + * + * File Name: 405gp_pci.c + * + * Function: Initialization code for the 405GP PCI Configuration regs. + * + * Author: Mark Game + * + * Change Activity- + * + * Date Description of Change BY + * --------- --------------------- --- + * 09-Sep-98 Created MCG + * 02-Nov-98 Removed External arbiter selected message JWB + * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB + * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG + * from (0 to n) to (1 to n). + * 17-May-99 Port to Walnut JWB + * 17-Jun-99 Updated for VGA support JWB + * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB + * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG + * target latency timer values are not supported). + * Should be fixed in pass 2. + * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB + * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS. + * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB + * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not + * really required after a reset since PMMxMAs are already + * disabled but is a good practice nonetheless. JWB + * 12-Jun-01 stefan.roese@esd-electronics.com + * - PCI host/adapter handling reworked + * 09-Jul-01 stefan.roese@esd-electronics.com + * - PCI host now configures from device 0 (not 1) to max_dev, + * (host configures itself) + * - On CPCI-405 pci base address and size is generated from + * SDRAM and FLASH size (CFG regs not used anymore) + * - Some minor changes for CPCI-405-A (adapter version) + * 14-Sep-01 stefan.roese@esd-electronics.com + * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup + * 28-Sep-01 stefan.roese@esd-electronics.com + * - Changed pci master configuration for linux compatibility + * (no need for bios_fixup() anymore) + * 26-Feb-02 stefan.roese@esd-electronics.com + * - Bug fixed in pci configuration (Andrew May) + * - Removed pci class code init for CPCI405 board + * 15-May-02 stefan.roese@esd-electronics.com + * - New vga device handling + * 29-May-02 stefan.roese@esd-electronics.com + * - PCI class code init added (if defined) + *----------------------------------------------------------------------------*/ + +#include +#include +#if !defined(CONFIG_440) +#include +#endif +#include +#include + +#ifdef CONFIG_PCI + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Board-specific pci initialization + * Platform code can reimplement pci_pre_init() if needed + */ +int __pci_pre_init(struct pci_controller *hose) +{ + return 1; +} +int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init"))); + +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) + +#if defined(CONFIG_PMC405) +ushort pmc405_pci_subsys_deviceid(void); +#endif + +/*#define DEBUG*/ + +/*-----------------------------------------------------------------------------+ + * pci_init. Initializes the 405GP PCI Configuration regs. + *-----------------------------------------------------------------------------*/ +void pci_405gp_init(struct pci_controller *hose) +{ + int i, reg_num = 0; + bd_t *bd = gd->bd; + + unsigned short temp_short; + unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI}; +#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405) + char *ptmla_str, *ptmms_str; +#endif + unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA}; + unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS}; +#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405) + unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0}; + unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0}; + unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0}; + unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0}; +#else + unsigned long pmmla[3] = {0x80000000, 0,0}; + unsigned long pmmma[3] = {0xC0000001, 0,0}; + unsigned long pmmpcila[3] = {0x80000000, 0,0}; + unsigned long pmmpciha[3] = {0x00000000, 0,0}; +#endif +#ifdef CONFIG_PCI_PNP +#if (CONFIG_PCI_HOST == PCI_HOST_AUTO) + char *s; +#endif +#endif + +#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405) + ptmla_str = getenv("ptm1la"); + ptmms_str = getenv("ptm1ms"); + if(NULL != ptmla_str && NULL != ptmms_str ) { + ptmla[0] = simple_strtoul (ptmla_str, NULL, 16); + ptmms[0] = simple_strtoul (ptmms_str, NULL, 16); + } + + ptmla_str = getenv("ptm2la"); + ptmms_str = getenv("ptm2ms"); + if(NULL != ptmla_str && NULL != ptmms_str ) { + ptmla[1] = simple_strtoul (ptmla_str, NULL, 16); + ptmms[1] = simple_strtoul (ptmms_str, NULL, 16); + } +#endif + + /* + * Register the hose + */ + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* ISA/PCI I/O space */ + pci_set_region(hose->regions + reg_num++, + MIN_PCI_PCI_IOADDR, + MIN_PLB_PCI_IOADDR, + 0x10000, + PCI_REGION_IO); + + /* PCI I/O space */ + pci_set_region(hose->regions + reg_num++, + 0x00800000, + 0xe8800000, + 0x03800000, + PCI_REGION_IO); + + reg_num = 2; + + /* Memory spaces */ + for (i=0; i<2; i++) + if (ptmms[i] & 1) + { + if (!i) hose->pci_fb = hose->regions + reg_num; + + pci_set_region(hose->regions + reg_num++, + ptmpcila[i], ptmla[i], + ~(ptmms[i] & 0xfffff000) + 1, + PCI_REGION_MEM | + PCI_REGION_MEMORY); + } + + /* PCI memory spaces */ + for (i=0; i<3; i++) + if (pmmma[i] & 1) + { + pci_set_region(hose->regions + reg_num++, + pmmpcila[i], pmmla[i], + ~(pmmma[i] & 0xfffff000) + 1, + PCI_REGION_MEM); + } + + hose->region_count = reg_num; + + pci_setup_indirect(hose, + PCICFGADR, + PCICFGDATA); + + if (hose->pci_fb) + pciauto_region_init(hose->pci_fb); + + /* Let board change/modify hose & do initial checks */ + if (pci_pre_init (hose) == 0) { + printf("PCI: Board-specific initialization failed.\n"); + printf("PCI: Configuration aborted.\n"); + return; + } + + pci_register_hose(hose); + + /*--------------------------------------------------------------------------+ + * 405GP PCI Master configuration. + * Map one 512 MB range of PLB/processor addresses to PCI memory space. + * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF + * Use byte reversed out routines to handle endianess. + *--------------------------------------------------------------------------*/ + out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */ + out32r(PMM0LA, pmmla[0]); + out32r(PMM0PCILA, pmmpcila[0]); + out32r(PMM0PCIHA, pmmpciha[0]); + out32r(PMM0MA, pmmma[0]); + + /*--------------------------------------------------------------------------+ + * PMM1 is not used. Initialize them to zero. + *--------------------------------------------------------------------------*/ + out32r(PMM1MA, (pmmma[1]&~0x1)); + out32r(PMM1LA, pmmla[1]); + out32r(PMM1PCILA, pmmpcila[1]); + out32r(PMM1PCIHA, pmmpciha[1]); + out32r(PMM1MA, pmmma[1]); + + /*--------------------------------------------------------------------------+ + * PMM2 is not used. Initialize them to zero. + *--------------------------------------------------------------------------*/ + out32r(PMM2MA, (pmmma[2]&~0x1)); + out32r(PMM2LA, pmmla[2]); + out32r(PMM2PCILA, pmmpcila[2]); + out32r(PMM2PCIHA, pmmpciha[2]); + out32r(PMM2MA, pmmma[2]); + + /*--------------------------------------------------------------------------+ + * 405GP PCI Target configuration. (PTM1) + * Note: PTM1MS is hardwire enabled but we set the enable bit anyway. + *--------------------------------------------------------------------------*/ + out32r(PTM1LA, ptmla[0]); /* insert address */ + out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */ + pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]); + + /*--------------------------------------------------------------------------+ + * 405GP PCI Target configuration. (PTM2) + *--------------------------------------------------------------------------*/ + out32r(PTM2LA, ptmla[1]); /* insert address */ + pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]); + + if (ptmms[1] == 0) + { + out32r(PTM2MS, 0x00000001); /* set enable bit */ + pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000); + out32r(PTM2MS, 0x00000000); /* disable */ + } + else + { + out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */ + } + + /* + * Insert Subsystem Vendor and Device ID + */ + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID); +#ifdef CONFIG_CPCI405 + if (mfdcr(strap) & PSR_PCI_ARBIT_EN) + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID); + else + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2); +#else + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID); +#endif + + /* + * Insert Class-code + */ +#ifdef CFG_PCI_CLASSCODE + pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE); +#endif /* CFG_PCI_CLASSCODE */ + + /*--------------------------------------------------------------------------+ + * If PCI speed = 66Mhz, set 66Mhz capable bit. + *--------------------------------------------------------------------------*/ + if (bd->bi_pci_busfreq >= 66000000) { + pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short); + pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ)); + } + +#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER) +#if (CONFIG_PCI_HOST == PCI_HOST_AUTO) + if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) || + (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) +#endif + { + /*--------------------------------------------------------------------------+ + * Write the 405GP PCI Configuration regs. + * Enable 405GP to be a master on the PCI bus (PMM). + * Enable 405GP to act as a PCI memory target (PTM). + *--------------------------------------------------------------------------*/ + pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short); + pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short | + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + } +#endif + +#if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */ + pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014); /* IBM */ +#endif + + /* + * Set HCE bit (Host Configuration Enabled) + */ + pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short); + pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001)); + +#ifdef CONFIG_PCI_PNP + /*--------------------------------------------------------------------------+ + * Scan the PCI bus and configure devices found. + *--------------------------------------------------------------------------*/ +#if (CONFIG_PCI_HOST == PCI_HOST_AUTO) + if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) || + (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) +#endif + { +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + hose->last_busno = pci_hose_scan(hose); + } +#endif /* CONFIG_PCI_PNP */ + +} + +/* + * drivers/pci.c skips every host bridge but the 405GP since it could + * be set as an Adapter. + * + * I (Andrew May) don't know what we should do here, but I don't want + * the auto setup of a PCI device disabling what is done pci_405gp_init + * as has happened before. + */ +void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *entry) +{ +#ifdef DEBUG + printf("405gp_setup_bridge\n"); +#endif +} + +/* + * + */ + +void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + unsigned char int_line = 0xff; + + /* + * Write pci interrupt line register (cpci405 specific) + */ + switch (PCI_DEV(dev) & 0x03) + { + case 0: + int_line = 27 + 2; + break; + case 1: + int_line = 27 + 3; + break; + case 2: + int_line = 27 + 0; + break; + case 3: + int_line = 27 + 1; + break; + } + + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); +} + +void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *entry) +{ + unsigned int cmdstat = 0; + + pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io); + + /* always enable io space on vga boards */ + pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); + cmdstat |= PCI_COMMAND_IO; + pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); +} + +#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3)) + +/* + *As is these functs get called out of flash Not a horrible + *thing, but something to keep in mind. (no statics?) + */ +static struct pci_config_table pci_405gp_config_table[] = { +/*if VendID is 0 it terminates the table search (ie Walnut)*/ +#ifdef CFG_PCI_SUBSYS_VENDORID + {CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge}, +#endif + {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, + + {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, + + { } +}; + +static struct pci_controller hose = { + fixup_irq: pci_405gp_fixup_irq, + config_table: pci_405gp_config_table, +}; + +void pci_init_board(void) +{ + /*we want the ptrs to RAM not flash (ie don't use init list)*/ + hose.fixup_irq = pci_405gp_fixup_irq; + hose.config_table = pci_405gp_config_table; + pci_405gp_init(&hose); +} + +#endif + +#endif /* CONFIG_405GP */ + +/*-----------------------------------------------------------------------------+ + * CONFIG_440 + *-----------------------------------------------------------------------------*/ +#if defined(CONFIG_440) + +static struct pci_controller ppc440_hose = {0}; + + +int pci_440_init (struct pci_controller *hose) +{ + int reg_num = 0; + +#ifndef CONFIG_DISABLE_PISE_TEST + /*--------------------------------------------------------------------------+ + * The PCI initialization sequence enable bit must be set ... if not abort + * pci setup since updating the bit requires chip reset. + *--------------------------------------------------------------------------*/ +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) + unsigned long strap; + + mfsdr(sdr_sdstp1,strap); + if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) { + printf("PCI: SDR0_STRP1[PISE] not set.\n"); + printf("PCI: Configuration aborted.\n"); + return -1; + } +#elif defined(CONFIG_440GP) + unsigned long strap; + + strap = mfdcr(cpc0_strp1); + if ((strap & CPC0_STRP1_PISE_MASK) == 0) { + printf("PCI: CPC0_STRP1[PISE] not set.\n"); + printf("PCI: Configuration aborted.\n"); + return -1; + } +#endif +#endif /* CONFIG_DISABLE_PISE_TEST */ + + /*--------------------------------------------------------------------------+ + * PCI controller init + *--------------------------------------------------------------------------*/ + hose->first_busno = 0; + hose->last_busno = 0; + + /* PCI I/O space */ + pci_set_region(hose->regions + reg_num++, + 0x00000000, + PCIX0_IOBASE, + 0x10000, + PCI_REGION_IO); + + /* PCI memory space */ + pci_set_region(hose->regions + reg_num++, + CFG_PCI_TARGBASE, + CFG_PCI_MEMBASE, +#ifdef CFG_PCI_MEMSIZE + CFG_PCI_MEMSIZE, +#else + 0x10000000, +#endif + PCI_REGION_MEM ); + +#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \ + defined(CONFIG_PCI_SYS_MEM_SIZE) + /* System memory space */ + pci_set_region(hose->regions + reg_num++, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + CONFIG_PCI_SYS_MEM_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY ); +#endif + + hose->region_count = reg_num; + + pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA); + + /* Let board change/modify hose & do initial checks */ + if (pci_pre_init (hose) == 0) { + printf("PCI: Board-specific initialization failed.\n"); + printf("PCI: Configuration aborted.\n"); + return -1; + } + + pci_register_hose( hose ); + + /*--------------------------------------------------------------------------+ + * PCI target init + *--------------------------------------------------------------------------*/ +#if defined(CFG_PCI_TARGET_INIT) + pci_target_init(hose); /* Let board setup pci target */ +#else + out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID ); + out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ +#endif + +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) + out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ + out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ +#elif defined(PCIX0_BRDGOPT1) + out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ + out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */ +#endif + + /*--------------------------------------------------------------------------+ + * PCI master init: default is one 256MB region for PCI memory: + * 0x3_00000000 - 0x3_0FFFFFFF ==> CFG_PCI_MEMBASE + *--------------------------------------------------------------------------*/ +#if defined(CFG_PCI_MASTER_INIT) + pci_master_init(hose); /* Let board setup pci master */ +#else + out32r( PCIX0_POM0SA, 0 ); /* disable */ + out32r( PCIX0_POM1SA, 0 ); /* disable */ + out32r( PCIX0_POM2SA, 0 ); /* disable */ +#if defined(CONFIG_440SPE) + out32r( PCIX0_POM0LAL, 0x10000000 ); + out32r( PCIX0_POM0LAH, 0x0000000c ); +#else + out32r( PCIX0_POM0LAL, 0x00000000 ); + out32r( PCIX0_POM0LAH, 0x00000003 ); +#endif + out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE ); + out32r( PCIX0_POM0PCIAH, 0x00000000 ); + out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */ + out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 ); +#endif + + /*--------------------------------------------------------------------------+ + * PCI host configuration -- we don't make any assumptions here ... the + * _board_must_indicate_ what to do -- there's just too many runtime + * scenarios in environments like cPCI, PPMC, etc. to make a determination + * based on hard-coded values or state of arbiter enable. + *--------------------------------------------------------------------------*/ + if (is_pci_host(hose)) { +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif +#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \ + !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) + out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER); +#endif + hose->last_busno = pci_hose_scan(hose); + } + return hose->last_busno; +} + +void pci_init_board(void) +{ + int busno; + + busno = pci_440_init (&ppc440_hose); +#if defined(CONFIG_440SPE) + pcie_setup_hoses(busno + 1); +#endif +} + +#endif /* CONFIG_440 */ +#endif /* CONFIG_PCI */ diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 28a8e2bcb7e..a11faec14e1 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -27,11 +27,11 @@ LIB = $(obj)lib$(CPU).a START = start.o resetvec.o kgdb.o SOBJS = dcr.o -COBJS = 405gp_pci.o 4xx_pcie.o 4xx_enet.o \ +COBJS = 40x_spd_sdram.o 44x_spd_ddr.o 44x_spd_ddr2.o \ + 4xx_pci.o 4xx_pcie.o 4xx_enet.o \ bedbug_405.o commproc.o \ cpu.o cpu_init.o gpio.o i2c.o interrupts.o \ - miiphy.o ndfc.o sdram.o serial.o \ - 40x_spd_sdram.o 44x_spd_ddr.o 44x_spd_ddr2.o speed.o \ + miiphy.o ndfc.o sdram.o serial.o speed.o \ tlb.o traps.o usb_ohci.o usb.o usbdev.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/include/405gp_pci.h b/include/405gp_pci.h deleted file mode 100644 index 3c1adec19c5..00000000000 --- a/include/405gp_pci.h +++ /dev/null @@ -1,52 +0,0 @@ -#ifndef _405GP_PCI_H -#define _405GP_PCI_H - -/*----------------------------------------------------------------------------+ -| 405GP PCI core memory map defines. -+----------------------------------------------------------------------------*/ -#define MIN_PCI_MEMADDR1 0x80000000 -#define MIN_PCI_MEMADDR2 0x00000000 -#define MIN_PLB_PCI_IOADDR 0xE8000000 /* PLB side of PCI I/O address space */ -#define MIN_PCI_PCI_IOADDR 0x00000000 /* PCI side of PCI I/O address space */ -#define MAX_PCI_DEVICES 32 - -/*----------------------------------------------------------------------------+ -| Defines for the 405GP PCI Config address and data registers followed by -| defines for the standard PCI device configuration header. -+----------------------------------------------------------------------------*/ -#define PCICFGADR 0xEEC00000 -#define PCICFGDATA 0xEEC00004 - -#define PCIBUSNUM 0x40 /* 405GP specific parameters */ -#define PCISUBBUSNUM 0x41 -#define PCIDISCOUNT 0x42 -#define PCIBRDGOPT1 0x4A -#define PCIBRDGOPT2 0x60 - -/*----------------------------------------------------------------------------+ -| Defines for 405GP PCI Master local configuration regs. -+----------------------------------------------------------------------------*/ -#define PMM0LA 0xEF400000 -#define PMM0MA 0xEF400004 -#define PMM0PCILA 0xEF400008 -#define PMM0PCIHA 0xEF40000C -#define PMM1LA 0xEF400010 -#define PMM1MA 0xEF400014 -#define PMM1PCILA 0xEF400018 -#define PMM1PCIHA 0xEF40001C -#define PMM2LA 0xEF400020 -#define PMM2MA 0xEF400024 -#define PMM2PCILA 0xEF400028 -#define PMM2PCIHA 0xEF40002C - -/*----------------------------------------------------------------------------+ -| Defines for 405GP PCI Target local configuration regs. -+----------------------------------------------------------------------------*/ -#define PTM1MS 0xEF400030 -#define PTM1LA 0xEF400034 -#define PTM2MS 0xEF400038 -#define PTM2LA 0xEF40003C - -#define PCIDEVID_405GP 0x0 - -#endif diff --git a/include/asm-ppc/4xx_pci.h b/include/asm-ppc/4xx_pci.h new file mode 100644 index 00000000000..3c1adec19c5 --- /dev/null +++ b/include/asm-ppc/4xx_pci.h @@ -0,0 +1,52 @@ +#ifndef _405GP_PCI_H +#define _405GP_PCI_H + +/*----------------------------------------------------------------------------+ +| 405GP PCI core memory map defines. ++----------------------------------------------------------------------------*/ +#define MIN_PCI_MEMADDR1 0x80000000 +#define MIN_PCI_MEMADDR2 0x00000000 +#define MIN_PLB_PCI_IOADDR 0xE8000000 /* PLB side of PCI I/O address space */ +#define MIN_PCI_PCI_IOADDR 0x00000000 /* PCI side of PCI I/O address space */ +#define MAX_PCI_DEVICES 32 + +/*----------------------------------------------------------------------------+ +| Defines for the 405GP PCI Config address and data registers followed by +| defines for the standard PCI device configuration header. ++----------------------------------------------------------------------------*/ +#define PCICFGADR 0xEEC00000 +#define PCICFGDATA 0xEEC00004 + +#define PCIBUSNUM 0x40 /* 405GP specific parameters */ +#define PCISUBBUSNUM 0x41 +#define PCIDISCOUNT 0x42 +#define PCIBRDGOPT1 0x4A +#define PCIBRDGOPT2 0x60 + +/*----------------------------------------------------------------------------+ +| Defines for 405GP PCI Master local configuration regs. ++----------------------------------------------------------------------------*/ +#define PMM0LA 0xEF400000 +#define PMM0MA 0xEF400004 +#define PMM0PCILA 0xEF400008 +#define PMM0PCIHA 0xEF40000C +#define PMM1LA 0xEF400010 +#define PMM1MA 0xEF400014 +#define PMM1PCILA 0xEF400018 +#define PMM1PCIHA 0xEF40001C +#define PMM2LA 0xEF400020 +#define PMM2MA 0xEF400024 +#define PMM2PCILA 0xEF400028 +#define PMM2PCIHA 0xEF40002C + +/*----------------------------------------------------------------------------+ +| Defines for 405GP PCI Target local configuration regs. ++----------------------------------------------------------------------------*/ +#define PTM1MS 0xEF400030 +#define PTM1LA 0xEF400034 +#define PTM2MS 0xEF400038 +#define PTM2LA 0xEF40003C + +#define PCIDEVID_405GP 0x0 + +#endif -- cgit v1.3.1 From 6d95289281ed2958ebf76d2b55f86bbd88591fd2 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 3 Oct 2007 21:16:32 +0200 Subject: ppc4xx: 4xx_pcie: Fix problem with SDRN access using port number as idx Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_pcie.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index 177e2ad2e7a..2b3e657806a 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -588,7 +588,7 @@ int ppc4xx_init_pcie_port(int port, int rootport) */ mdelay(100); - val = SDR_READ(SDRN_PESDR_RCSSTS(sdr_base(port))); + val = SDR_READ(SDRN_PESDR_RCSSTS(port)); if (val & (1 << 20)) { printf("PCIE%d: PGRST failed %08x\n", port, val); return -1; @@ -597,7 +597,7 @@ int ppc4xx_init_pcie_port(int port, int rootport) /* * Verify link is up */ - val = SDR_READ(SDRN_PESDR_LOOP(sdr_base(port))); + val = SDR_READ(SDRN_PESDR_LOOP(port)); if (!(val & 0x00001000)) { printf("PCIE%d: link is not up.\n", port); return -1; @@ -639,15 +639,15 @@ int ppc4xx_init_pcie_port(int port, int rootport) * Check for VC0 active and assert RDY. */ attempts = 10; - while(!(SDR_READ(SDRN_PESDR_RCSSTS(sdr_base(port))) & (1 << 16))) { + while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) { if (!(attempts--)) { printf("PCIE%d: VC0 not active\n", port); return -1; } mdelay(1000); } - SDR_WRITE(SDRN_PESDR_RCSSET(sdr_base(port)), - SDR_READ(SDRN_PESDR_RCSSET(sdr_base(port))) | 1 << 20); + SDR_WRITE(SDRN_PESDR_RCSSET(port), + SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20); mdelay(100); return 0; @@ -862,7 +862,7 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) out_le16(mbase + 0x202,0xfeed); /* Setting device ID */ attempts = 10; - while(!(SDR_READ(SDRN_PESDR_RCSSTS(sdr_base(port))) & (1 << 8))) { + while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) { if (!(attempts--)) { printf("PCIE%d: BME not active\n", port); return -1; -- cgit v1.3.1 From 4dbee8a90df613eb517aadbecebd70f168913d30 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 5 Oct 2007 07:57:20 +0200 Subject: ppc4xx: 4xx_pcie: Change CFG_PCIE_MEMSIZE to 128MB on Yucca & Katmai 128MB seems to be the smallest possible value for the memory size for on PCIe port. With this change now the BAR's of the PCIe cards are accessible under U-Boot. One big note: This only works for PCIe port 0 & 1. For port 2 this currently doesn't work, since the base address is now 0xc0000000 (0xb0000000 + 2 * 0x08000000), and this is already occupied by CFG_PCIE0_CFGBASE. But solving this issue for port 2 would mean to change the base addresses completely and this change would have too much impact right now. This patch adds debug output to the 4xx pcie driver too. Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_pcie.c | 25 ++++++++++++++++++++++++- include/configs/katmai.h | 2 +- include/configs/yucca.h | 2 +- 3 files changed, 26 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index 2b3e657806a..7ac8ce0d765 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -20,6 +20,11 @@ * */ +/* define DEBUG for debugging output (obviously ;-)) */ +#if 1 +#define DEBUG +#endif + #include #include #include @@ -708,7 +713,10 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) * subregions and to enable the outbound translation. */ out_le32(mbase + PECFG_POM0LAH, 0x00000000); - out_le32(mbase + PECFG_POM0LAL, 0x00000000); + out_le32(mbase + PECFG_POM0LAL, CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE); + debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH), + in_le32(mbase + PECFG_POM0LAL)); switch (port) { case 0: @@ -718,6 +726,11 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), ~(CFG_PCIE_MEMSIZE - 1) | 3); + debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", + mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)), + mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)), + mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)), + mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0))); break; case 1: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); @@ -726,6 +739,11 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), ~(CFG_PCIE_MEMSIZE - 1) | 3); + debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", + mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)), + mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)), + mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)), + mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1))); break; case 2: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); @@ -734,6 +752,11 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), ~(CFG_PCIE_MEMSIZE - 1) | 3); + debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", + mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)), + mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)), + mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)), + mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2))); break; } diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 7908e5a4743..03c3cb3bdf0 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -62,7 +62,7 @@ #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE #define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ -#define CFG_PCIE_MEMSIZE 0x01000000 +#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */ #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ #define CFG_PCIE0_CFGBASE 0xc0000000 diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 74033b4aef4..6caf21bcb51 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -64,7 +64,7 @@ #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE #define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ -#define CFG_PCIE_MEMSIZE 0x01000000 +#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */ #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ #define CFG_PCIE0_CFGBASE 0xc0000000 -- cgit v1.3.1 From 97923770cb52b64d69eec958a11b2eda8d46e0f7 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 5 Oct 2007 09:18:23 +0200 Subject: ppc4xx: 4xx_pcie: More general cleanup and 405EX PCIe support added Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_pcie.c | 93 +++++++++++++++++++++++++++------------------- include/asm-ppc/4xx_pcie.h | 31 ++++++++++------ include/configs/katmai.h | 3 ++ include/configs/yucca.h | 3 ++ 4 files changed, 79 insertions(+), 51 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index 7ac8ce0d765..d1ba8905312 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -31,7 +31,8 @@ #include #include -#if defined(CONFIG_440SPE) && defined(CONFIG_PCI) +#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX)) && \ + defined(CONFIG_PCI) #include @@ -55,8 +56,10 @@ static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn) base = (u8*)CFG_PCIE0_XCFGBASE; if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE) base = (u8*)CFG_PCIE1_XCFGBASE; +#if CFG_PCIE_NR_PORTS > 2 if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE) base = (u8*)CFG_PCIE2_XCFGBASE; +#endif } return base; @@ -68,8 +71,10 @@ static void pcie_dmer_disable(void) mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA); mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE), mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA); +#if CFG_PCIE_NR_PORTS > 2 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE), mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA); +#endif } static void pcie_dmer_enable(void) @@ -78,8 +83,10 @@ static void pcie_dmer_enable(void) mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA); mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE), mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA); +#if CFG_PCIE_NR_PORTS > 2 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE), mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA); +#endif } static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, @@ -120,6 +127,7 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, */ pcie_dmer_disable (); + debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset); switch (len) { case 1: *val = in_8(hose->cfg_data + offset); @@ -227,6 +235,7 @@ int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val); } +#if defined(CONFIG_440SPE) static void ppc4xx_setup_utl(u32 port) { volatile void *utl_base = NULL; @@ -371,6 +380,15 @@ int ppc4xx_init_pcie(void) } return 0; } +#else +int ppc4xx_init_pcie(void) +{ + /* + * Nothing to do on 405EX + */ + return 0; +} +#endif /* * Board-specific pcie initialization @@ -608,19 +626,21 @@ int ppc4xx_init_pcie_port(int port, int rootport) return -1; } +#if defined(CONFIG_440SPE) /* * Setup UTL registers - but only on revA! * We use default settings for revB chip. */ if (!ppc440spe_revB()) ppc4xx_setup_utl(port); +#endif /* * We map PCI Express configuration access into the 512MB regions */ addr = ppc4xx_get_cfgaddr(port); - low = (u32)(addr & 0x00000000ffffffff); - high = (u32)(addr >> 32); + low = U64_TO_U32_LOW(addr); + high = U64_TO_U32_HIGH(addr); switch (port) { case 0: @@ -633,11 +653,13 @@ int ppc4xx_init_pcie_port(int port, int rootport) mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low); mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ break; +#if CFG_PCIE_NR_PORTS > 2 case 2: mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high); mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low); mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ break; +#endif } /* @@ -692,11 +714,13 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) rmbase = (u32 *)CFG_PCIE1_CFGBASE; hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; break; +#if CFG_PCIE_NR_PORTS > 2 case 2: mbase = (u32 *)CFG_PCIE2_XCFGBASE; rmbase = (u32 *)CFG_PCIE2_CFGBASE; hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; break; +#endif } /* @@ -720,8 +744,8 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) switch (port) { case 0: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), @@ -733,8 +757,8 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0))); break; case 1: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE + + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), @@ -745,9 +769,10 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)), mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1))); break; +#if CFG_PCIE_NR_PORTS > 2 case 2: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE + + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), @@ -758,6 +783,7 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)), mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2))); break; +#endif } /* Set up 16GB inbound memory window at 0 */ @@ -770,8 +796,8 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) out_le32(mbase + PECFG_PIM01SAL, 0x00000000); out_le32(mbase + PECFG_PIM0LAL, 0); out_le32(mbase + PECFG_PIM0LAH, 0); - out_le32(mbase + PECFG_PIM1LAL, 0x00000000); - out_le32(mbase + PECFG_PIM1LAH, 0x00000004); + out_le32(mbase + PECFG_PIM1LAL, 0x00000000); + out_le32(mbase + PECFG_PIM1LAH, 0x00000004); out_le32(mbase + PECFG_PIMEN, 0x1); /* Enable I/O, Mem, and Busmaster cycles */ @@ -780,23 +806,8 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); /* Set Device and Vendor Id */ - switch (port) { - case 0: - out_le16(mbase + 0x200, 0xaaa0); - out_le16(mbase + 0x202, 0xbed0); - break; - case 1: - out_le16(mbase + 0x200, 0xaaa1); - out_le16(mbase + 0x202, 0xbed1); - break; - case 2: - out_le16(mbase + 0x200, 0xaaa2); - out_le16(mbase + 0x202, 0xbed2); - break; - default: - out_le16(mbase + 0x200, 0xaaa3); - out_le16(mbase + 0x202, 0xbed3); - } + out_le16(mbase + 0x200, 0xaaa0 + port); + out_le16(mbase + 0x202, 0xbed0 + port); /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ out_le32(mbase + 0x208, 0x06040001); @@ -826,10 +837,12 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) mbase = (u32 *)CFG_PCIE1_XCFGBASE; hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; break; +#if defined(CFG_PCIE2_CFGBASE) case 2: mbase = (u32 *)CFG_PCIE2_XCFGBASE; hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; break; +#endif } /* @@ -843,29 +856,31 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) switch (port) { case 0: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), ~(CFG_PCIE_MEMSIZE - 1) | 3); break; case 1: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE + + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), ~(CFG_PCIE_MEMSIZE - 1) | 3); break; +#if CFG_PCIE_NR_PORTS > 2 case 2: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE + + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), ~(CFG_PCIE_MEMSIZE - 1) | 3); break; +#endif } /* Set up 16GB inbound memory window at 0 */ @@ -873,16 +888,16 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) out_le32(mbase + PCI_BASE_ADDRESS_1, 0); out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); out_le32(mbase + PECFG_BAR0LMPA, 0); - out_le32(mbase + PECFG_PIM0LAL, 0x00000000); - out_le32(mbase + PECFG_PIM0LAH, 0x00000004); /* pointing to SRAM */ + out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CFG_PCIE_INBOUND_BASE)); + out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CFG_PCIE_INBOUND_BASE)); out_le32(mbase + PECFG_PIMEN, 0x1); /* Enable I/O, Mem, and Busmaster cycles */ out_le16((u16 *)(mbase + PCI_COMMAND), in_le16((u16 *)(mbase + PCI_COMMAND)) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */ - out_le16(mbase + 0x202,0xfeed); /* Setting device ID */ + out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */ + out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */ attempts = 10; while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) { @@ -893,7 +908,7 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) mdelay(1000); } - printf("PCIE:%d successfully set as endpoint\n",port); + printf("PCIE:%d successfully set as endpoint\n", port); return 0; } diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index 1bb8fc7ed13..17ac57b23bc 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -16,14 +16,29 @@ #define DCRN_SDR0_CFGDATA 0x00f #if defined(CONFIG_440SPE) +#define CFG_PCIE_NR_PORTS 3 + +#define CFG_PCIE_ADDR_HIGH 0x0000000d + #define DCRN_PCIE0_BASE 0x100 #define DCRN_PCIE1_BASE 0x120 #define DCRN_PCIE2_BASE 0x140 + +#define PCIE0_SDR 0x300 +#define PCIE1_SDR 0x340 +#define PCIE2_SDR 0x370 #endif #if defined(CONFIG_405EX) +#define CFG_PCIE_NR_PORTS 2 + +#define CFG_PCIE_ADDR_HIGH 0x00000000 + #define DCRN_PCIE0_BASE 0x040 #define DCRN_PCIE1_BASE 0x060 + +#define PCIE0_SDR 0x400 +#define PCIE1_SDR 0x440 #endif #define PCIE0 DCRN_PCIE0_BASE @@ -53,17 +68,6 @@ #define PESDR0_PLLLCT2 0x03a1 #define PESDR0_PLLLCT3 0x03a2 -#if defined(CONFIG_440SPE) -#define PCIE0_SDR 0x300 -#define PCIE1_SDR 0x340 -#define PCIE2_SDR 0x370 -#endif - -#if defined(CONFIG_405EX) -#define PCIE0_SDR 0x400 -#define PCIE1_SDR 0x440 -#endif - /* common regs, at least for 405EX and 440SPe */ #define SDRN_PESDR_UTLSET1(n) (sdr_base(n) + 0x00) #define SDRN_PESDR_UTLSET2(n) (sdr_base(n) + 0x01) @@ -237,6 +241,9 @@ #define GPL_DMER_MASK_DISA 0x02000000 +#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL)) +#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32)) + int ppc4xx_init_pcie(void); int ppc4xx_init_pcie_rootport(int port); int ppc4xx_init_pcie_endport(int port); @@ -260,7 +267,7 @@ static inline u32 sdr_base(int port) return PCIE0_SDR; case 1: return PCIE1_SDR; -#if defined(PCIE2_SDR) +#if CFG_PCIE_NR_PORTS > 2 case 2: return PCIE2_SDR; #endif diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 03c3cb3bdf0..8a963279f08 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -72,6 +72,9 @@ #define CFG_PCIE1_XCFGBASE 0xc3001000 #define CFG_PCIE2_XCFGBASE 0xc3002000 +/* base address of inbound PCIe window */ +#define CFG_PCIE_INBOUND_BASE 0x0000000400000000ULL + /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 6caf21bcb51..ab7fb0ab8c2 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -74,6 +74,9 @@ #define CFG_PCIE1_XCFGBASE 0xc3001000 #define CFG_PCIE2_XCFGBASE 0xc3002000 +/* base address of inbound PCIe window */ +#define CFG_PCIE_INBOUND_BASE 0x0000000400000000ULL + /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE -- cgit v1.3.1 From ff68f66bcb0da847845aa2fac11eba6c25938c99 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 5 Oct 2007 09:22:33 +0200 Subject: ppc4xx: 4xx_pcie: Disable debug output as default Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_pcie.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index d1ba8905312..167aba69608 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -21,7 +21,7 @@ */ /* define DEBUG for debugging output (obviously ;-)) */ -#if 1 +#if 0 #define DEBUG #endif -- cgit v1.3.1 From 19e93b1e16d267220440d827b920fbad8abfa70f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 5 Oct 2007 14:23:43 +0200 Subject: ppc4xx: 4xx_pcie: Change PCIe status output to match common style Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_pcie.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index 167aba69608..7ee0e5bc89d 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -812,7 +812,7 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ out_le32(mbase + 0x208, 0x06040001); - printf("PCIE:%d successfully set as rootpoint\n", port); + printf("PCIE%d: successfully set as root-complex\n", port); } int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) @@ -908,7 +908,7 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) mdelay(1000); } - printf("PCIE:%d successfully set as endpoint\n", port); + printf("PCIE%d: successfully set as endpoint\n", port); return 0; } -- cgit v1.3.1 From 4f14ed6230b9c109aac9a6fb878497dabd44c2db Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 5 Oct 2007 17:07:50 +0200 Subject: ppc4xx: Add initial fdt support to 4xx (first needed on 405EX) Signed-off-by: Stefan Roese --- cpu/ppc4xx/fdt.c | 171 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 171 insertions(+) create mode 100644 cpu/ppc4xx/fdt.c (limited to 'cpu') diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c new file mode 100644 index 00000000000..a1c81e60b46 --- /dev/null +++ b/cpu/ppc4xx/fdt.c @@ -0,0 +1,171 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + +#include +#include +#include +#include +#include + +#if defined(CONFIG_OF_LIBFDT) +#include +#include + +static void do_fixup(void *fdt, const char *node, const char *prop, + const void *val, int len, int create) +{ +#if defined(DEBUG) + int i; + debug("Updating property '%s/%s' = ", node, prop); + for (i = 0; i < len; i++) + debug(" %.2x", *(u8*)(val+i)); + debug("\n"); +#endif + int rc = fdt_find_and_setprop(fdt, node, prop, val, len, create); + if (rc) + printf("Unable to update property %s:%s, err=%s\n", + node, prop, fdt_strerror(rc)); +} + +static void do_fixup_macaddr(void *fdt, int offset, const void *val, int i) +{ + int rc; + + debug("Updating node EMAC%d\n", i); + + rc = fdt_setprop(fdt, offset, "mac-address", val, 6); + if (rc) + printf("Unable to update property %s, err=%s\n", + "mac-address", fdt_strerror(rc)); + rc = fdt_setprop(fdt, offset, "local-mac-address", val, 6); + if (rc) + printf("Unable to update property %s, err=%s\n", + "local-mac-address", fdt_strerror(rc)); +} + +static void do_fixup_u32(void *fdt, const char *node, const char *prop, + u32 val, int create) +{ + val = cpu_to_fdt32(val); + do_fixup(fdt, node, prop, &val, sizeof(val), create); +} + +static void do_fixup_uart(void *fdt, int offset, int i, bd_t *bd) +{ + int rc; + u32 val; + + debug("Updating node UART%d\n", i); + + val = cpu_to_fdt32(CFG_EXT_SERIAL_CLOCK); + rc = fdt_setprop(fdt, offset, "clock-frequency", &val, 4); + if (rc) + printf("Unable to update node UART, err=%s\n", fdt_strerror(rc)); + + val = cpu_to_fdt32(bd->bi_baudrate); + rc = fdt_setprop(fdt, offset, "current-speed", &val, 4); + if (rc) + printf("Unable to update node UART, err=%s\n", fdt_strerror(rc)); +} + +void ft_cpu_setup(void *blob, bd_t *bd) +{ + char * cpu_path = "/cpus/" OF_CPU; + sys_info_t sys_info; + int offset; + int i; + int tmp[2]; + + get_sys_info (&sys_info); + + do_fixup_u32(blob, cpu_path, "timebase-frequency", bd->bi_intfreq, 1); + do_fixup_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); + do_fixup_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1); + do_fixup_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1); + do_fixup_u32(blob, "/plb/opb/ebc", "clock-frequency", sys_info.freqEBC, 1); + + /* update, or add and update /memory node */ + offset = fdt_find_node_by_path(blob, "/memory"); + if (offset < 0) { + offset = fdt_add_subnode(blob, 0, "memory"); + if (offset < 0) + debug("failed to add /memory node: %s\n", + fdt_strerror(offset)); + } + if (offset >= 0) { + fdt_setprop(blob, offset, "device_type", + "memory", sizeof("memory")); + tmp[0] = cpu_to_fdt32(bd->bi_memstart); + tmp[1] = cpu_to_fdt32(bd->bi_memsize); + fdt_setprop(blob, offset, "reg", tmp, sizeof(tmp)); + } + + /* + * Setup all baudrates for the UARTs + */ + offset = 0; + for (i = 0; i < 4; i++) { + offset = fdt_find_node_by_type(blob, offset, "serial"); + if (offset < 0) + break; + + do_fixup_uart(blob, offset, i, bd); + } + + /* + * Setup all MAC addresses in fdt + */ + offset = 0; + for (i = 0; i < 4; i++) { + offset = fdt_find_node_by_type(blob, offset, "network"); + if (offset < 0) + break; + + switch (i) { + case 0: + do_fixup_macaddr(blob, offset, bd->bi_enetaddr, 0); + break; +#ifdef CONFIG_HAS_ETH1 + case 1: + do_fixup_macaddr(blob, offset, bd->bi_enet1addr, 1); + break; +#endif +#ifdef CONFIG_HAS_ETH2 + case 2: + do_fixup_macaddr(blob, offset, bd->bi_enet2addr, 2); + break; +#endif +#ifdef CONFIG_HAS_ETH3 + case 3: + do_fixup_macaddr(blob, offset, bd->bi_enet3addr, 3); + break; +#endif + } + } +} +#endif /* CONFIG_OF_LIBFDT */ -- cgit v1.3.1 From 1d7b874e9c9a7c66f5d8da9ec78a3733765d3e31 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 5 Oct 2007 17:09:36 +0200 Subject: ppc4xx: Cleanup of 4xx PCI and PCIe support (renaming) Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_pci.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c index e6170517ae6..a68c419b1ba 100644 --- a/cpu/ppc4xx/4xx_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -592,4 +592,15 @@ void pci_init_board(void) } #endif /* CONFIG_440 */ + +#if defined(CONFIG_405EX) +void pci_init_board(void) +{ +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + pcie_setup_hoses(0); +} +#endif /* CONFIG_405EX */ + #endif /* CONFIG_PCI */ -- cgit v1.3.1 From dbbd125721aea6645fdb962f36bd41f59e272f9d Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 5 Oct 2007 17:10:59 +0200 Subject: ppc4xx: Add PPC405EX support Signed-off-by: Stefan Roese --- common/serial.c | 6 +- cpu/ppc4xx/4xx_enet.c | 113 ++++++-- cpu/ppc4xx/Makefile | 2 +- cpu/ppc4xx/cpu.c | 63 +++-- cpu/ppc4xx/cpu_init.c | 14 +- cpu/ppc4xx/interrupts.c | 20 +- cpu/ppc4xx/miiphy.c | 22 +- cpu/ppc4xx/ndfc.c | 3 +- cpu/ppc4xx/serial.c | 42 ++- cpu/ppc4xx/speed.c | 180 +++++++++++- cpu/ppc4xx/start.S | 69 +++-- cpu/ppc4xx/vecnum.h | 104 +++++++ include/405_mal.h | 4 +- include/4xx_i2c.h | 2 +- include/asm-ppc/processor.h | 4 + include/asm-ppc/u-boot.h | 1 + include/common.h | 4 +- include/ppc405.h | 675 ++++++++++++++++++++++++++++++++++++++++++-- include/ppc440.h | 2 +- include/ppc4xx_enet.h | 15 +- include/serial.h | 5 +- 21 files changed, 1205 insertions(+), 145 deletions(-) (limited to 'cpu') diff --git a/common/serial.c b/common/serial.c index dee1cc0ab9c..b9916e2b5ec 100644 --- a/common/serial.c +++ b/common/serial.c @@ -41,7 +41,8 @@ struct serial_device *default_serial_console (void) || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) return &serial_scc_device; #elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ - || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx) + || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \ + || defined(CONFIG_MPC5xxx) #if defined(CONFIG_CONS_INDEX) && defined(CFG_NS16550_SERIAL) #if (CONFIG_CONS_INDEX==1) return &eserial1_device; @@ -91,7 +92,8 @@ void serial_initialize (void) #endif #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ - || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx) + || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \ + || defined(CONFIG_MPC5xxx) serial_register(&serial0_device); serial_register(&serial1_device); #endif diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 71a9e372da0..841cb77d6de 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -133,13 +133,15 @@ #define BI_PHYMODE_GMII 3 #define BI_PHYMODE_RTBI 4 #define BI_PHYMODE_TBI 5 -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) #define BI_PHYMODE_SMII 6 #define BI_PHYMODE_MII 7 #endif -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || \ - defined(CONFIG_440GRX) || defined(CONFIG_440SP) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1)) #endif @@ -172,6 +174,12 @@ struct eth_device *emac0_dev = NULL; #define CONFIG_EMAC_NR_START 0 #endif +#if defined(CONFIG_405EX) || defined(CONFIG_440EPX) +#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev))) +#else +#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * 2)) +#endif + /*-----------------------------------------------------------------------------+ * Prototypes and externals. *-----------------------------------------------------------------------------*/ @@ -197,7 +205,9 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) { EMAC_4XX_HW_PST hw_p = dev->priv; uint32_t failsafe = 10000; -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) unsigned long mfr; #endif @@ -221,7 +231,9 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) } /* EMAC RESET */ -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) /* provide clocks for EMAC internal loopback */ mfsdr (sdr_mfr, mfr); mfr |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); @@ -230,7 +242,9 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) /* remove clocks for EMAC internal loopback */ mfsdr (sdr_mfr, mfr); mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); @@ -389,6 +403,38 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) } #endif /* CONFIG_440EPX */ +#if defined(CONFIG_405EX) +int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) +{ + u32 gmiifer = 0; + + /* + * Right now only 2*RGMII is supported. Please extend when needed. + * sr - 2007-09-19 + */ + switch (1) { + case 1: + /* 2 x RGMII ports */ + out32 (RGMII_FER, 0x00000055); + bis->bi_phymode[0] = BI_PHYMODE_RGMII; + bis->bi_phymode[1] = BI_PHYMODE_RGMII; + break; + case 2: + /* 2 x SMII ports */ + break; + default: + break; + } + + /* Ensure we setup mdio for this devnum and ONLY this devnum */ + gmiifer = in32(RGMII_FER); + gmiifer |= (1 << (19-devnum)); + out32 (RGMII_FER, gmiifer); + + return ((int)0x0); +} +#endif /* CONFIG_405EX */ + static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) { int i, j; @@ -402,19 +448,21 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) unsigned short reg_short; #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_405EX) sys_info_t sysinfo; #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) int ethgroup = -1; #endif #endif #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_405EX) unsigned long mfr; #endif - EMAC_4XX_HW_PST hw_p = dev->priv; /* before doing anything, figure out if we have a MAC address */ @@ -426,7 +474,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_405EX) /* Need to get the OPB frequency so we can access the PHY */ get_sys_info (&sysinfo); #endif @@ -498,12 +547,16 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ +#if defined(CONFIG_405EX) + ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); +#endif __asm__ volatile ("eieio"); /* reset emac so we have access to the phy */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) /* provide clocks for EMAC internal loopback */ mfsdr (sdr_mfr, mfr); mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum); @@ -521,8 +574,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) if (failsafe <= 0) printf("\nProblem resetting EMAC!\n"); -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) /* remove clocks for EMAC internal loopback */ mfsdr (sdr_mfr, mfr); mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum); @@ -531,7 +585,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_405EX) /* Whack the M1 register */ mode_reg = 0x0; mode_reg &= ~0x00000038; @@ -591,7 +646,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_405EX) #if defined(CONFIG_CIS8201_PHY) /* @@ -723,7 +779,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) } #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) if (speed == 1000) reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); else if (speed == 100) @@ -740,7 +797,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* set the Mal configuration reg */ #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_405EX) mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); #else @@ -978,8 +1036,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* * Connect interrupt service routines */ - irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2), - (interrupt_handler_t *) enetInt, dev); + irq_install_handler(ETH_IRQ_NUM(hw_p->devnum), + (interrupt_handler_t *) enetInt, dev); } mtmsr (msr); /* enable interrupts again */ @@ -1059,7 +1117,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, } -#if defined (CONFIG_440) +#if defined (CONFIG_440) || defined(CONFIG_405EX) #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* @@ -1073,7 +1131,8 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, #define UIC0SR uic0sr #endif -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) #define UICMSR_ETHX uic0msr #define UICSR_ETHX uic0sr #else @@ -1601,7 +1660,11 @@ int ppc_4xx_eth_initialize (bd_t * bis) bis->bi_phynum[3] = CONFIG_PHY3_ADDR; bis->bi_phymode[2] = 2; bis->bi_phymode[3] = 2; +#endif +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) ppc_4xx_eth_setup_bridge(0, bis); #endif @@ -1649,7 +1712,9 @@ int ppc_4xx_eth_initialize (bd_t * bis) if (0 == virgin) { /* set the MAL IER ??? names may change with new spec ??? */ -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) mal_ier = MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE | MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ; diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index a11faec14e1..bc65aa0571d 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -30,7 +30,7 @@ SOBJS = dcr.o COBJS = 40x_spd_sdram.o 44x_spd_ddr.o 44x_spd_ddr2.o \ 4xx_pci.o 4xx_pcie.o 4xx_enet.o \ bedbug_405.o commproc.o \ - cpu.o cpu_init.o gpio.o i2c.o interrupts.o \ + cpu.o cpu_init.o fdt.o gpio.o i2c.o interrupts.o \ miiphy.o ndfc.o sdram.o serial.o speed.o \ tlb.o traps.o usb_ohci.o usb.o usbdev.o diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index c07bc0c325e..7addb9251f5 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2006 + * (C) Copyright 2000-2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -45,15 +45,6 @@ DECLARE_GLOBAL_DATA_PTR; void board_reset(void); #endif -#if defined(CONFIG_440) -#define FREQ_EBC (sys_info.freqEPB) -#elif defined(CONFIG_405EZ) -#define FREQ_EBC ((CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / \ - sys_info.pllExtBusDiv) -#else -#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv) -#endif - #if defined(CONFIG_405GP) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) @@ -76,7 +67,8 @@ int pci_async_enabled(void) } #endif -#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405) +#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \ + !defined(CONFIG_405) && !defined(CONFIG_405EX) int pci_arbiter_enabled(void) { #if defined(CONFIG_405GP) @@ -110,7 +102,8 @@ int pci_arbiter_enabled(void) #if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_405EX) #define I2C_BOOTROM @@ -207,6 +200,21 @@ static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \ 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' }; #endif +#if defined(CONFIG_405EX) +#define SDR0_PINSTP_SHIFT 29 +static char *bootstrap_str[] = { + "EBC (8 bits)", + "EBC (16 bits)", + "EBC (16 bits)", + "NAND (8 bits)", + "NAND (8 bits)", + "I2C (Addr 0x54)", + "EBC (8 bits)", + "I2C (Addr 0x52)", +}; +static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; +#endif + #if defined(SDR0_PINSTP_SHIFT) static int bootstrap_option(void) { @@ -241,7 +249,8 @@ int checkcpu (void) puts("AMCC PowerPC 4"); #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || defined(CONFIG_405EZ) + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ + defined(CONFIG_405EX) puts("05"); #endif #if defined(CONFIG_440) @@ -293,6 +302,26 @@ int checkcpu (void) puts("EZ Rev. A"); break; + case PVR_405EX1_RA: + puts("EX Rev. A"); + strcpy(addstr, "Security support"); + break; + + case PVR_405EX2_RA: + puts("EX Rev. A"); + strcpy(addstr, "No Security support"); + break; + + case PVR_405EXR1_RA: + puts("EXr Rev. A"); + strcpy(addstr, "Security support"); + break; + + case PVR_405EXR2_RA: + puts("EXr Rev. A"); + strcpy(addstr, "No Security support"); + break; + #if defined(CONFIG_440) case PVR_440GP_RB: puts("GP Rev. B"); @@ -424,7 +453,7 @@ int checkcpu (void) printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), sys_info.freqPLB / 1000000, get_OPB_freq() / 1000000, - FREQ_EBC / 1000000); + sys_info.freqEBC / 1000000); if (addstr[0] != 0) printf(" %s\n", addstr); @@ -437,7 +466,7 @@ int checkcpu (void) printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]); #endif /* SDR0_PINSTP_SHIFT */ -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) && !defined(CONFIG_405EX) printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis"); #endif @@ -450,11 +479,11 @@ int checkcpu (void) } #endif -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) && !defined(CONFIG_405EX) putc('\n'); #endif -#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) +#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) printf (" 16 kB I-Cache 16 kB D-Cache"); #elif defined(CONFIG_440) printf (" 32 kB I-Cache 32 kB D-Cache"); diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 351da36e855..afb94cc0700 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2006 + * (C) Copyright 2000-2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -112,7 +112,7 @@ cpu_init_f (void) unsigned long val; #endif -#if defined(CONFIG_405EP) +#if defined(CONFIG_405EP) || defined (CONFIG_405EX) /* * GPIO0 setup (select GPIO or alternate function) */ @@ -128,13 +128,21 @@ cpu_init_f (void) out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L); out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ out32(GPIO0_TSRL, CFG_GPIO0_TSRL); +#if defined(CFG_GPIO0_ISR2H) + out32(GPIO0_ISR2H, CFG_GPIO0_ISR2H); + out32(GPIO0_ISR2L, CFG_GPIO0_ISR2L); +#endif +#if defined (CFG_GPIO0_TCR) out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ +#endif +#if defined (CONFIG_450EP) /* * Set EMAC noise filter bits */ mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); #endif /* CONFIG_405EP */ +#endif /* CONFIG_405EP */ #if defined(CFG_440_GPIO_TABLE) gpio_set_chip_configuration(); @@ -146,7 +154,7 @@ cpu_init_f (void) #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_405)) + defined(CONFIG_405EX) || defined(CONFIG_405)) /* * Move the next instructions into icache, since these modify the flash * we are running from! diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index ca565cc3e07..2026cc927a9 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -52,7 +52,7 @@ struct irq_action { static struct irq_action irq_vecs[32]; void uic0_interrupt( void * parms); /* UIC0 handler */ -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) static struct irq_action irq_vecs1[32]; /* For UIC1 */ void uic1_interrupt( void * parms); /* UIC1 handler */ @@ -116,7 +116,7 @@ int interrupt_init_cpu (unsigned *decrementer_count) irq_vecs[vec].handler = NULL; irq_vecs[vec].arg = NULL; irq_vecs[vec].count = 0; -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) irq_vecs1[vec].handler = NULL; irq_vecs1[vec].arg = NULL; irq_vecs1[vec].count = 0; @@ -172,7 +172,7 @@ int interrupt_init_cpu (unsigned *decrementer_count) */ set_evpr(0x00000000); -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) #if !defined(CONFIG_440GX) /* Install the UIC1 handlers */ irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0); @@ -378,7 +378,7 @@ void uic0_interrupt( void * parms) #endif /* CONFIG_440GX */ -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) /* Handler for UIC1 interrupt */ void uic1_interrupt( void * parms) { @@ -525,7 +525,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) struct irq_action *irqa = irq_vecs; int i = vec; -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) if ((vec > 31) && (vec < 64)) { @@ -553,7 +553,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) irqa[i].handler = handler; irqa[i].arg = arg; -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) if ((vec > 31) && (vec < 64)) @@ -577,7 +577,7 @@ void irq_free_handler (int vec) struct irq_action *irqa = irq_vecs; int i = vec; -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) if ((vec > 31) && (vec < 64)) { @@ -599,7 +599,7 @@ void irq_free_handler (int vec) vec, irq_vecs[vec].handler); #endif -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) if ((vec > 31) && (vec < 64)) @@ -641,7 +641,7 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int vec; printf ("\nInterrupt-Information:\n"); -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) printf ("\nUIC 0\n"); #endif printf ("Nr Routine Arg Count\n"); @@ -656,7 +656,7 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } } -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) printf ("\nUIC 1\n"); printf ("Nr Routine Arg Count\n"); diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index 6b98025308f..2c675e9be6b 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -141,6 +141,16 @@ unsigned int miiphy_getemac_offset (void) return (eoffset); #else + +#if defined(CONFIG_NET_MULTI) && defined(CONFIG_405EX) + unsigned long rgmii; + int devnum = 1; + + rgmii = in32(RGMII_FER); + if (rgmii & (1 << (19 - devnum))) + return 0x100; +#endif + return 0; #endif } @@ -174,7 +184,8 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) #if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ; #else @@ -186,7 +197,8 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, #if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \ !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ - !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) + !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ + !defined(CONFIG_405EX) sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; #endif sta_reg = sta_reg | (addr << 5); /* Phy address */ @@ -248,7 +260,8 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) #if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE; #else @@ -260,7 +273,8 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, #if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \ !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ - !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) + !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ + !defined(CONFIG_405EX) sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */ #endif sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */ diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c index 398457726f4..ec1b38cffa3 100644 --- a/cpu/ppc4xx/ndfc.c +++ b/cpu/ppc4xx/ndfc.c @@ -34,7 +34,7 @@ #if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \ (defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_405EZ)) + defined(CONFIG_405EZ) || defined(CONFIG_405EX)) #include #include @@ -222,6 +222,7 @@ int board_nand_init(struct nand_chip *nand) */ board_nand_select_device(nand, cs); out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), 0x80002222); + return 0; } diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index 60712b151e2..8b1e2ffa0b4 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -266,7 +266,7 @@ int serial_tstc () /*****************************************************************************/ #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_440) + defined(CONFIG_405EX) || defined(CONFIG_440) #if defined(CONFIG_440) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ @@ -318,6 +318,15 @@ int serial_tstc () #define UCR0_UDIV_POS 0 #define UCR1_UDIV_POS 8 #define UDIV_MAX 127 +#elif defined(CONFIG_405EX) +#define UART0_BASE 0xef600200 +#define UART1_BASE 0xef600300 +#define CR0_MASK 0x000000ff +#define CR0_EXTCLK_ENA 0x00800000 +#define CR0_UDIV_POS 0 +#define UDIV_SUBTRACT 0 +#define UART0_SDR sdr_uart0 +#define UART1_SDR sdr_uart1 #else /* CONFIG_405GP || CONFIG_405CR */ #define UART0_BASE 0xef600300 #define UART1_BASE 0xef600400 @@ -391,7 +400,8 @@ typedef struct { volatile static serial_buffer_t buf_info; #endif -#if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK) +#if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \ + !defined(CFG_EXT_SERIAL_CLOCK) static void serial_divs (int baudrate, unsigned long *pudiv, unsigned short *pbdiv) { @@ -572,7 +582,31 @@ int serial_init (void) unsigned short bdiv; volatile char val; -#if defined(CONFIG_405EZ) +#ifdef CONFIG_405EX + clk = tmp = 0; + mfsdr(UART0_SDR, reg); + reg &= ~CR0_MASK; +#ifdef CFG_EXT_SERIAL_CLOCK + reg |= CR0_EXTCLK_ENA; + udiv = 1; + tmp = gd->baudrate * 16; + bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp; +#else + serial_divs(gd->baudrate, &udiv, &bdiv); +#endif + reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ + + /* + * Configure input clock to baudrate generator for all + * available serial ports here + */ + mtsdr(UART0_SDR, reg); + +#if defined(UART1_SDR) + mtsdr(UART1_SDR, reg); +#endif + +#elif defined(CONFIG_405EZ) serial_divs(gd->baudrate, &udiv, &bdiv); clk = tmp = reg = 0; #else @@ -608,7 +642,7 @@ int serial_init (void) #endif /* CONFIG_405EP */ tmp = gd->baudrate * udiv * 16; bdiv = (clk + tmp / 2) / tmp; -#endif /* CONFIG_405EZ */ +#endif /* CONFIG_405EX */ out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */ out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */ diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index da5330a3604..750b0958762 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000-2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -263,7 +263,7 @@ void get_sys_info (sys_info_t *sysInfo) sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA; sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0; sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; - sysInfo->freqEPB = sysInfo->freqPLB/sysInfo->pllExtBusDiv; + sysInfo->freqEBC = sysInfo->freqPLB/sysInfo->pllExtBusDiv; sysInfo->freqPCI = sysInfo->freqPLB/sysInfo->pllPciDiv; /* Figure which timer source to use */ @@ -317,7 +317,7 @@ void get_sys_info (sys_info_t * sysInfo) if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */ sysInfo->freqPLB >>= 1; sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; - sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv; + sysInfo->freqEBC = sysInfo->freqOPB/sysInfo->pllExtBusDiv; } #else @@ -393,7 +393,7 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA; sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0; sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; - sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv; + sysInfo->freqEBC = sysInfo->freqOPB/sysInfo->pllExtBusDiv; #if defined(CONFIG_YUCCA) /* Determine PCI Clock Period */ @@ -733,6 +733,8 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo) * Determine PLB clock frequency */ sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv; + + sysInfo->freqEBC = sysInfo->freqPLB / sysInfo->pllExtBusDiv; } @@ -856,6 +858,9 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo) */ sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * m) / sysInfo->pllFwdDiv / sysInfo->pllPlbDiv; + + sysInfo->freqEBC = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / + sysInfo->pllExtBusDiv; } /******************************************** @@ -874,13 +879,175 @@ ulong get_OPB_freq (void) return val; } +#elif defined(CONFIG_405EX) + +/* + * TODO: We need to get the CPR registers and calculate these values correctly!!!! + * We need the specs!!!! + */ +static unsigned char get_fbdv(unsigned char index) +{ + unsigned char ret = 0; + /* This is table should be 256 bytes. + * Only take first 52 values. + */ + unsigned char fbdv_tb[] = { + 0x00, 0xff, 0x7f, 0xfd, + 0x7a, 0xf5, 0x6a, 0xd5, + 0x2a, 0xd4, 0x29, 0xd3, + 0x26, 0xcc, 0x19, 0xb3, + 0x67, 0xce, 0x1d, 0xbb, + 0x77, 0xee, 0x5d, 0xba, + 0x74, 0xe9, 0x52, 0xa5, + 0x4b, 0x96, 0x2c, 0xd8, + 0x31, 0xe3, 0x46, 0x8d, + 0x1b, 0xb7, 0x6f, 0xde, + 0x3d, 0xfb, 0x76, 0xed, + 0x5a, 0xb5, 0x6b, 0xd6, + 0x2d, 0xdb, 0x36, 0xec, + + }; + + if ((index & 0x7f) == 0) + return 1; + while (ret < sizeof (fbdv_tb)) { + if (fbdv_tb[ret] == index) + break; + ret++; + } + ret++; + + return ret; +} + +#define PLL_FBK_PLL_LOCAL 0 +#define PLL_FBK_CPU 1 +#define PLL_FBK_PERCLK 5 + +void get_sys_info (sys_info_t * sysInfo) +{ + unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000); + unsigned long m = 1; + unsigned int tmp; + unsigned char fwdva[16] = { + 1, 2, 14, 9, 4, 11, 16, 13, + 12, 5, 6, 15, 10, 7, 8, 3, + }; + unsigned char sel, cpudv0, plb2xDiv; + + mfcpr(cpr0_plld, tmp); + + /* + * Determine forward divider A + */ + sysInfo->pllFwdDiv = fwdva[((tmp >> 16) & 0x0f)]; /* FWDVA */ + + /* + * Determine FBK_DIV. + */ + sysInfo->pllFbkDiv = get_fbdv(((tmp >> 24) & 0x0ff)); /* FBDV */ + + /* + * Determine PLBDV0 + */ + sysInfo->pllPlbDiv = 2; + + /* + * Determine PERDV0 + */ + mfcpr(cpr0_perd, tmp); + tmp = (tmp >> 24) & 0x03; + sysInfo->pllExtBusDiv = (tmp == 0) ? 4 : tmp; + + /* + * Determine OPBDV0 + */ + mfcpr(cpr0_opbd, tmp); + tmp = (tmp >> 24) & 0x03; + sysInfo->pllOpbDiv = (tmp == 0) ? 4 : tmp; + + /* Determine PLB2XDV0 */ + mfcpr(cpr0_plbd, tmp); + tmp = (tmp >> 16) & 0x07; + plb2xDiv = (tmp == 0) ? 8 : tmp; + + /* Determine CPUDV0 */ + mfcpr(cpr0_cpud, tmp); + tmp = (tmp >> 24) & 0x07; + cpudv0 = (tmp == 0) ? 8 : tmp; + + /* Determine SEL(5:7) in CPR0_PLLC */ + mfcpr(cpr0_pllc, tmp); + sel = (tmp >> 24) & 0x07; + + /* + * Determine the M factor + * PLL local: M = FBDV + * CPU clock: M = FBDV * FWDVA * CPUDV0 + * PerClk : M = FBDV * FWDVA * PLB2XDV0 * PLBDV0(2) * OPBDV0 * PERDV0 + * + */ + switch (sel) { + case PLL_FBK_CPU: + m = sysInfo->pllFwdDiv * cpudv0; + break; + case PLL_FBK_PERCLK: + m = sysInfo->pllFwdDiv * plb2xDiv * 2 + * sysInfo->pllOpbDiv * sysInfo->pllExtBusDiv; + break; + case PLL_FBK_PLL_LOCAL: + break; + default: + printf("%s unknown m\n", __FUNCTION__); + return; + + } + m *= sysInfo->pllFbkDiv; + + /* + * Determine VCO clock frequency + */ + sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) / + (unsigned long long)sysClkPeriodPs; + + /* + * Determine CPU clock frequency + */ + sysInfo->freqProcessor = sysInfo->freqVCOHz / (sysInfo->pllFwdDiv * cpudv0); + + /* + * Determine PLB clock frequency, ddr1x should be the same + */ + sysInfo->freqPLB = sysInfo->freqVCOHz / (sysInfo->pllFwdDiv * plb2xDiv * 2); + sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; + sysInfo->freqDDR = sysInfo->freqPLB; + sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv; +} + +/******************************************** + * get_OPB_freq + * return OPB bus freq in Hz + *********************************************/ +ulong get_OPB_freq (void) +{ + ulong val = 0; + + PPC405_SYS_INFO sys_info; + + get_sys_info (&sys_info); + val = sys_info.freqPLB / sys_info.pllOpbDiv; + + return val; +} + #endif int get_clocks (void) { #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_440) || defined(CONFIG_405) + defined(CONFIG_405EX) || defined(CONFIG_405) || \ + defined(CONFIG_440) sys_info_t sys_info; get_sys_info (&sys_info); @@ -907,7 +1074,8 @@ ulong get_bus_freq (ulong dummy) #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_440) || defined(CONFIG_405) + defined(CONFIG_405EX) || defined(CONFIG_405) || \ + defined(CONFIG_440) sys_info_t sys_info; get_sys_info (&sys_info); diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 9626b65c885..81a15fe922d 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -800,7 +800,7 @@ _start: /*----------------------------------------------------------------------- */ /* Enable two 128MB cachable regions. */ /*----------------------------------------------------------------------- */ - addis r1,r0,0x8000 + addis r1,r0,0xc000 addi r1,r1,0x0001 mticcr r1 /* instruction cache */ @@ -823,12 +823,23 @@ _start: /*****************************************************************************/ #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_405) + defined(CONFIG_405EX) || defined(CONFIG_405) /*----------------------------------------------------------------------- */ /* Clear and set up some registers. */ /*----------------------------------------------------------------------- */ addi r4,r0,0x0000 +#if !defined(CONFIG_405EX) mtspr sgr,r4 +#else + /* + * On 405EX, completely clearing the SGR leads to PPC hangup + * upon PCIe configuration access. The PCIe memory regions + * need to be guarded! + */ + lis r3,0x0000 + ori r3,r3,0x7FFC + mtspr sgr,r3 +#endif mtspr dcwr,r4 mtesr r4 /* clear Exception Syndrome Reg */ mttcr r4 /* clear Timer Control Reg */ @@ -851,7 +862,7 @@ _start: /*----------------------------------------------------------------------- */ /* Enable two 128MB cachable regions. */ /*----------------------------------------------------------------------- */ - lis r4,0x8000 + lis r4,0xc000 ori r4,r4,0x0001 mticcr r4 /* instruction cache */ isync @@ -860,12 +871,34 @@ _start: ori r4,r4,0x0000 mtdccr r4 /* data cache */ -#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) +#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) || defined(CONFIG_405EX) /*----------------------------------------------------------------------- */ /* Tune the speed and size for flash CS0 */ /*----------------------------------------------------------------------- */ bl ext_bus_cntlr_init #endif +#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM)) + /* + * Boards like the Kilauea (405EX) don't have OCM and can't use + * DCache for init-ram. So setup stack here directly after the + * SDRAM is initialized. + */ + lis r1, CFG_INIT_RAM_ADDR@h + ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */ + + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + /* + * Set up a dummy frame to store reset vector as return address. + * this causes stack underflow to reset board. + */ + stwu r1, -8(r1) /* Save back chain and move SP */ + lis r0, RESET_VECTOR@h /* Address of reset vector */ + ori r0, r0, RESET_VECTOR@l + stwu r1, -8(r1) /* Save back chain and move SP */ + stw r0, +12(r1) /* Save return addr (underflow vect) */ +#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */ #if defined(CONFIG_405EP) /*----------------------------------------------------------------------- */ @@ -983,7 +1016,7 @@ start_ram: ori r4,r4,0xa000 mtdcr ebccfgd,r4 - /* turn on data chache for this region */ + /* turn on data cache for this region */ lis r4,0x0080 mtdccr r4 @@ -1049,30 +1082,6 @@ start_ram: /*----------------------------------------------------------------------- */ bl sdram_init - /* - * Setup temporary stack pointer only for boards - * that do not use SDRAM SPD I2C stuff since it - * is already initialized to use DCACHE or OCM - * stacks. - */ -#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM)) - lis r1, CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */ - - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - /* - * Set up a dummy frame to store reset vector as return address. - * this causes stack underflow to reset board. - */ - stwu r1, -8(r1) /* Save back chain and move SP */ - lis r0, RESET_VECTOR@h /* Address of reset vector */ - ori r0, r0, RESET_VECTOR@l - stwu r1, -8(r1) /* Save back chain and move SP */ - stw r0, +12(r1) /* Save return addr (underflow vect) */ -#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */ - #ifdef CONFIG_NAND_SPL bl nand_boot /* will not return */ #else @@ -1273,7 +1282,7 @@ icache_enable: bl invalidate_icache mtlr r8 isync - addis r3,r0, 0x8000 /* set bit 0 */ + addis r3,r0, 0xc000 /* set bit 0 */ mticcr r3 blr diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h index bddf9e5daa9..93e51b90ccd 100644 --- a/cpu/ppc4xx/vecnum.h +++ b/cpu/ppc4xx/vecnum.h @@ -270,6 +270,110 @@ #define VECNUM_EIR3 30 /* External interrupt 3 */ #define VECNUM_EIR4 31 /* External interrupt 4 */ +#elif defined(CONFIG_405EX) + +/* UIC 0 */ +#define VECNUM_U0 00 +#define VECNUM_U1 01 +#define VECNUM_IIC0 02 +#define VECNUM_PKA 03 +#define VECNUM_TRNG 04 +#define VECNUM_EBM 05 +#define VECNUM_BGI 06 +#define VECNUM_IIC1 07 +#define VECNUM_SPI 08 +#define VECNUM_EIR0 09 +#define VECNUM_MTE 10 /* MAL Tx EOB */ +#define VECNUM_MRE 11 /* MAL Rx EOB */ +#define VECNUM_DMA0 12 +#define VECNUM_DMA1 13 +#define VECNUM_DMA2 14 +#define VECNUM_DMA3 15 +#define VECNUM_PCIE0AL 16 +#define VECNUM_PCIE0VPD 17 +#define VECNUM_RPCIE0HRST 18 +#define VECNUM_FPCIE0HRST 19 +#define VECNUM_PCIE0TCR 20 +#define VECNUM_PCIEMSI0 21 +#define VECNUM_PCIEMSI1 22 +#define VECNUM_SECURITY 23 +#define VECNUM_ETH0 24 +#define VECNUM_ETH1 25 +#define VECNUM_PCIEMSI2 26 +#define VECNUM_EIR4 27 +#define VECNUM_UIC2NC 28 +#define VECNUM_UIC2C 29 +#define VECNUM_UIC1NC 30 +#define VECNUM_UIC1C 31 + +/* UIC 1 */ +#define VECNUM_MS (32 + 00) /* MAL SERR */ +#define VECNUM_TXDE (32 + 01) /* MAL TXDE */ +#define VECNUM_RXDE (32 + 02) /* MAL RXDE */ +#define VECNUM_PCIE0BMVC0 (32 + 03) +#define VECNUM_PCIE0DCRERR (32 + 04) +#define VECNUM_EBC (32 + 05) +#define VECNUM_NDFC (32 + 06) +#define VECNUM_PCEI1DCRERR (32 + 07) +#define VECNUM_CT8 (32 + 08) +#define VECNUM_CT9 (32 + 09) +#define VECNUM_PCIE1AL (32 + 10) +#define VECNUM_PCIE1VPD (32 + 11) +#define VECNUM_RPCE1HRST (32 + 12) +#define VECNUM_FPCE1HRST (32 + 13) +#define VECNUM_PCIE1TCR (32 + 14) +#define VECNUM_PCIE1VC0 (32 + 15) +#define VECNUM_CT3 (32 + 16) +#define VECNUM_CT4 (32 + 17) +#define VECNUM_EIR7 (32 + 18) +#define VECNUM_EIR8 (32 + 19) +#define VECNUM_EIR9 (32 + 20) +#define VECNUM_CT5 (32 + 21) +#define VECNUM_CT6 (32 + 22) +#define VECNUM_CT7 (32 + 23) +#define VECNUM_SROM (32 + 24) /* SERIAL ROM */ +#define VECNUM_GPTDECPULS (32 + 25) /* GPT Decrement pulse */ +#define VECNUM_EIR2 (32 + 26) +#define VECNUM_EIR5 (32 + 27) +#define VECNUM_EIR6 (32 + 28) +#define VECNUM_EMAC0WAKE (32 + 29) +#define VECNUM_EIR1 (32 + 30) +#define VECNUM_EMAC1WAKE (32 + 31) + +/* UIC 2 */ +#define VECNUM_PCIE0INTA (64 + 00) /* PCIE0 INTA */ +#define VECNUM_PCIE0INTB (64 + 01) /* PCIE0 INTB */ +#define VECNUM_PCIE0INTC (64 + 02) /* PCIE0 INTC */ +#define VECNUM_PCIE0INTD (64 + 03) /* PCIE0 INTD */ +#define VECNUM_EIR3 (64 + 04) /* External IRQ 3 */ +#define VECNUM_DDRMCUE (64 + 05) +#define VECNUM_DDRMCCE (64 + 06) +#define VECNUM_MALINTCOATX0 (64 + 07) /* Interrupt coalecence TX0 */ +#define VECNUM_MALINTCOATX1 (64 + 08) /* Interrupt coalecence TX1 */ +#define VECNUM_MALINTCOARX0 (64 + 09) /* Interrupt coalecence RX0 */ +#define VECNUM_MALINTCOARX1 (64 + 10) /* Interrupt coalecence RX1 */ +#define VECNUM_PCIE1INTA (64 + 11) /* PCIE0 INTA */ +#define VECNUM_PCIE1INTB (64 + 12) /* PCIE0 INTB */ +#define VECNUM_PCIE1INTC (64 + 13) /* PCIE0 INTC */ +#define VECNUM_PCIE1INTD (64 + 14) /* PCIE0 INTD */ +#define VECNUM_RPCIEMSI2 (64 + 15) /* MSI level 2 */ +#define VECNUM_PCIEMSI3 (64 + 16) /* MSI level 2 */ +#define VECNUM_PCIEMSI4 (64 + 17) /* MSI level 2 */ +#define VECNUM_PCIEMSI5 (64 + 18) /* MSI level 2 */ +#define VECNUM_PCIEMSI6 (64 + 19) /* MSI level 2 */ +#define VECNUM_PCIEMSI7 (64 + 20) /* MSI level 2 */ +#define VECNUM_PCIEMSI8 (64 + 21) /* MSI level 2 */ +#define VECNUM_PCIEMSI9 (64 + 22) /* MSI level 2 */ +#define VECNUM_PCIEMSI10 (64 + 23) /* MSI level 2 */ +#define VECNUM_PCIEMSI11 (64 + 24) /* MSI level 2 */ +#define VECNUM_PCIEMSI12 (64 + 25) /* MSI level 2 */ +#define VECNUM_PCIEMSI13 (64 + 26) /* MSI level 2 */ +#define VECNUM_PCIEMSI14 (64 + 27) /* MSI level 2 */ +#define VECNUM_PCIEMSI15 (64 + 28) /* MSI level 2 */ +#define VECNUM_PLB4XAHB (64 + 29) /* PLBxAHB bridge */ +#define VECNUM_USBWAKE (64 + 30) /* USB wakup */ +#define VECNUM_USBOTG (64 + 31) /* USB OTG */ + #else /* !CONFIG_405EZ */ #define VECNUM_U0 0 /* UART0 */ diff --git a/include/405_mal.h b/include/405_mal.h index 2a421848b4b..7ea4eb1cc48 100644 --- a/include/405_mal.h +++ b/include/405_mal.h @@ -92,7 +92,9 @@ #define MAL_ESR_PBEI 0x00000001 /* ^^ ^^ */ /* Mal IER */ -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) #define MAL_IER_PT 0x00000080 #define MAL_IER_PRE 0x00000040 #define MAL_IER_PWE 0x00000020 diff --git a/include/4xx_i2c.h b/include/4xx_i2c.h index 66b7997419b..7c79bd153ec 100644 --- a/include/4xx_i2c.h +++ b/include/4xx_i2c.h @@ -43,7 +43,7 @@ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS) -#elif defined(CONFIG_440) +#elif defined(CONFIG_440) || defined(CONFIG_405EX) /* all remaining 440 variants */ #define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400 + I2C_BUS_OFFS) #else diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 0a160e2513a..451ee94f618 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -765,6 +765,10 @@ #define PVR_405EP_RA 0x51210950 #define PVR_405GPR_RB 0x50910951 #define PVR_405EZ_RA 0x41511460 +#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A with Security */ +#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A without Security */ +#define PVR_405EX1_RA 0x12911477 /* 405EX rev A with Security */ +#define PVR_405EX2_RA 0x12911475 /* 405EX rev A without Security */ #define PVR_440GP_RB 0x40120440 #define PVR_440GP_RC 0x40120481 #define PVR_440EP_RA 0x42221850 diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index 464f6b5756e..bd9b6f70dda 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -84,6 +84,7 @@ typedef struct bd_info { defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || \ defined(CONFIG_405EZ) || \ + defined(CONFIG_405EX) || \ defined(CONFIG_440) unsigned char bi_s_version[4]; /* Version of this structure */ unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ diff --git a/include/common.h b/include/common.h index aca281bdad6..98655914f72 100644 --- a/include/common.h +++ b/include/common.h @@ -266,7 +266,7 @@ void pciinfo (int, int); int pci_pre_init (struct pci_controller * ); #endif -#if defined(CONFIG_PCI) && defined(CONFIG_440) +#if defined(CONFIG_PCI) && (defined(CONFIG_440) || defined(CONFIG_405EX)) # if defined(CFG_PCI_TARGET_INIT) void pci_target_init (struct pci_controller *); # endif @@ -274,7 +274,7 @@ void pciinfo (int, int); void pci_master_init (struct pci_controller *); # endif int is_pci_host (struct pci_controller *); -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || defined(CONFIG_405EX) void pcie_setup_hoses(int busno); #endif #endif diff --git a/include/ppc405.h b/include/ppc405.h index 0c7bf3e6def..82bc25e1f41 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -123,6 +123,40 @@ #define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */ #define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */ +#if defined(CONFIG_405EX) +#define uic0sr uicsr /* UIC status */ +#define uic0srs uicsrs /* UIC status set */ +#define uic0er uicer /* UIC enable */ +#define uic0cr uiccr /* UIC critical */ +#define uic0pr uicpr /* UIC polarity */ +#define uic0tr uictr /* UIC triggering */ +#define uic0msr uicmsr /* UIC masked status */ +#define uic0vr uicvr /* UIC vector */ +#define uic0vcr uicvcr /* UIC vector configuration*/ + +#define UIC_DCR_BASE1 0xd0 +#define uic1sr (UIC_DCR_BASE1+0x0) /* UIC status */ +#define uic1srs (UIC_DCR_BASE1+0x1) /* UIC status set */ +#define uic1er (UIC_DCR_BASE1+0x2) /* UIC enable */ +#define uic1cr (UIC_DCR_BASE1+0x3) /* UIC critical */ +#define uic1pr (UIC_DCR_BASE1+0x4) /* UIC polarity */ +#define uic1tr (UIC_DCR_BASE1+0x5) /* UIC triggering */ +#define uic1msr (UIC_DCR_BASE1+0x6) /* UIC masked status */ +#define uic1vr (UIC_DCR_BASE1+0x7) /* UIC vector */ +#define uic1vcr (UIC_DCR_BASE1+0x8) /* UIC vector configuration*/ + +#define UIC_DCR_BASE2 0xe0 +#define uic2sr (UIC_DCR_BASE2+0x0) /* UIC status */ +#define uic2srs (UIC_DCR_BASE2+0x1) /* UIC status set */ +#define uic2er (UIC_DCR_BASE2+0x2) /* UIC enable */ +#define uic2cr (UIC_DCR_BASE2+0x3) /* UIC critical */ +#define uic2pr (UIC_DCR_BASE2+0x4) /* UIC polarity */ +#define uic2tr (UIC_DCR_BASE2+0x5) /* UIC triggering */ +#define uic2msr (UIC_DCR_BASE2+0x6) /* UIC masked status */ +#define uic2vr (UIC_DCR_BASE2+0x7) /* UIC vector */ +#define uic2vcr (UIC_DCR_BASE2+0x8) /* UIC vector configuration*/ +#endif + /*-----------------------------------------------------------------------------+ | Universal interrupt controller interrupts +-----------------------------------------------------------------------------*/ @@ -166,6 +200,116 @@ #define UIC_EXT3 0x00000002 /* External interrupt 3 */ #define UIC_EXT4 0x00000001 /* External interrupt 4 */ +#elif defined(CONFIG_405EX) + +/* UIC 0 */ +#define UIC_U0 0x80000000 /* */ +#define UIC_U1 0x40000000 /* */ +#define UIC_IIC0 0x20000000 /* */ +#define UIC_PKA 0x10000000 /* */ +#define UIC_TRNG 0x08000000 /* */ +#define UIC_EBM 0x04000000 /* */ +#define UIC_BGI 0x02000000 /* */ +#define UIC_IIC1 0x01000000 /* */ +#define UIC_SPI 0x00800000 /* */ +#define UIC_EIRQ0 0x00400000 /**/ +#define UIC_MTE 0x00200000 /*MAL Tx EOB */ +#define UIC_MRE 0x00100000 /*MAL Rx EOB */ +#define UIC_DMA0 0x00080000 /* */ +#define UIC_DMA1 0x00040000 /* */ +#define UIC_DMA2 0x00020000 /* */ +#define UIC_DMA3 0x00010000 /* */ +#define UIC_PCIE0AL 0x00008000 /* */ +#define UIC_PCIE0VPD 0x00004000 /* */ +#define UIC_RPCIE0HRST 0x00002000 /* */ +#define UIC_FPCIE0HRST 0x00001000 /* */ +#define UIC_PCIE0TCR 0x00000800 /* */ +#define UIC_PCIEMSI0 0x00000400 /* */ +#define UIC_PCIEMSI1 0x00000200 /* */ +#define UIC_SECURITY 0x00000100 /* */ +#define UIC_ENET 0x00000080 /* */ +#define UIC_ENET1 0x00000040 /* */ +#define UIC_PCIEMSI2 0x00000020 /* */ +#define UIC_EIRQ4 0x00000010 /**/ +#define UIC_UIC2NC 0x00000008 /* */ +#define UIC_UIC2C 0x00000004 /* */ +#define UIC_UIC1NC 0x00000002 /* */ +#define UIC_UIC1C 0x00000001 /* */ + +#define UIC_MAL_TXEOB UIC_MTE/* MAL TXEOB */ +#define UIC_MAL_RXEOB UIC_MRE/* MAL RXEOB */ +/* UIC 1 */ +#define UIC_MS 0x80000000 /* MAL SERR */ +#define UIC_MTDE 0x40000000 /* MAL TXDE */ +#define UIC_MRDE 0x20000000 /* MAL RXDE */ +#define UIC_PCIE0BMVC0 0x10000000 /* */ +#define UIC_PCIE0DCRERR 0x08000000 /* */ +#define UIC_EBC 0x04000000 /* */ +#define UIC_NDFC 0x02000000 /* */ +#define UIC_PCEI1DCRERR 0x01000000 /* */ +#define UIC_GPTCMPT8 0x00800000 /* */ +#define UIC_GPTCMPT9 0x00400000 /* */ +#define UIC_PCIE1AL 0x00200000 /* */ +#define UIC_PCIE1VPD 0x00100000 /* */ +#define UIC_RPCE1HRST 0x00080000 /* */ +#define UIC_FPCE1HRST 0x00040000 /* */ +#define UIC_PCIE1TCR 0x00020000 /* */ +#define UIC_PCIE1VC0 0x00010000 /* */ +#define UIC_GPTCMPT3 0x00008000 /* */ +#define UIC_GPTCMPT4 0x00004000 /* */ +#define UIC_EIRQ7 0x00002000 /* */ +#define UIC_EIRQ8 0x00001000 /* */ +#define UIC_EIRQ9 0x00000800 /* */ +#define UIC_GPTCMP5 0x00000400 /* */ +#define UIC_GPTCMP6 0x00000200 /* */ +#define UIC_GPTCMP7 0x00000100 /* */ +#define UIC_SROM 0x00000080 /* SERIAL ROM*/ +#define UIC_GPTDECPULS 0x00000040 /* GPT Decrement pulse*/ +#define UIC_EIRQ2 0x00000020 /* */ +#define UIC_EIRQ5 0x00000010 /* */ +#define UIC_EIRQ6 0x00000008 /* */ +#define UIC_EMAC0WAKE 0x00000004 /* */ +#define UIC_EIRQ1 0x00000002 /* */ +#define UIC_EMAC1WAKE 0x00000001 /* */ +#define UIC_MAL_SERR UIC_MS /* MAL SERR */ +#define UIC_MAL_TXDE UIC_MTDE /* MAL TXDE */ +#define UIC_MAL_RXDE UIC_MRDE /* MAL RXDE */ +/* UIC 2 */ +#define UIC_PCIE0INTA 0x80000000 /* PCIE0 INTA*/ +#define UIC_PCIE0INTB 0x40000000 /* PCIE0 INTB*/ +#define UIC_PCIE0INTC 0x20000000 /* PCIE0 INTC*/ +#define UIC_PCIE0INTD 0x10000000 /* PCIE0 INTD*/ +#define UIC_EIRQ3 0x08000000 /* External IRQ 3*/ +#define UIC_DDRMCUE 0x04000000 /* */ +#define UIC_DDRMCCE 0x02000000 /* */ +#define UIC_MALINTCOATX0 0x01000000 /* Interrupt coalecence TX0*/ +#define UIC_MALINTCOATX1 0x00800000 /* Interrupt coalecence TX1*/ +#define UIC_MALINTCOARX0 0x00400000 /* Interrupt coalecence RX0*/ +#define UIC_MALINTCOARX1 0x00200000 /* Interrupt coalecence RX1*/ +#define UIC_PCIE1INTA 0x00100000 /* PCIE0 INTA*/ +#define UIC_PCIE1INTB 0x00080000 /* PCIE0 INTB*/ +#define UIC_PCIE1INTC 0x00040000 /* PCIE0 INTC*/ +#define UIC_PCIE1INTD 0x00020000 /* PCIE0 INTD*/ +#define UIC_RPCIEMSI2 0x00010000 /* MSI level 2 Note this looks same as uic0-26*/ +#define UIC_PCIEMSI3 0x00008000 /* MSI level 2*/ +#define UIC_PCIEMSI4 0x00004000 /* MSI level 2*/ +#define UIC_PCIEMSI5 0x00002000 /* MSI level 2*/ +#define UIC_PCIEMSI6 0x00001000 /* MSI level 2*/ +#define UIC_PCIEMSI7 0x00000800 /* MSI level 2*/ +#define UIC_PCIEMSI8 0x00000400 /* MSI level 2*/ +#define UIC_PCIEMSI9 0x00000200 /* MSI level 2*/ +#define UIC_PCIEMSI10 0x00000100 /* MSI level 2*/ +#define UIC_PCIEMSI11 0x00000080 /* MSI level 2*/ +#define UIC_PCIEMSI12 0x00000040 /* MSI level 2*/ +#define UIC_PCIEMSI13 0x00000020 /* MSI level 2*/ +#define UIC_PCIEMSI14 0x00000010 /* MSI level 2*/ +#define UIC_PCIEMSI15 0x00000008 /* MSI level 2*/ +#define UIC_PLB4XAHB 0x00000004 /* PLBxAHB bridge*/ +#define UIC_USBWAKE 0x00000002 /* USB wakup*/ +#define UIC_USBOTG 0x00000001 /* USB OTG*/ +#define UIC_ETH0 UIC_ENET +#define UIC_ETH1 UIC_ENET1 + #else /* !defined(CONFIG_405EZ) */ #define UIC_UART0 0x80000000 /* UART 0 */ @@ -256,7 +400,11 @@ /****************************************************************************** * Power Management ******************************************************************************/ +#ifdef CONFIG_405EX +#define POWERMAN_DCR_BASE 0xb0 +#else #define POWERMAN_DCR_BASE 0xb8 +#endif #define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ #define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ #define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ @@ -561,16 +709,6 @@ #define VCO_MIN 500 #define VCO_MAX 1000 #elif defined(CONFIG_405EZ) -/****************************************************************************** - * SDR Registers - ******************************************************************************/ -#define SDR_DCR_BASE 0x0E -#define sdrcfga (SDR_DCR_BASE+0x0) /* ADDR */ -#define sdrcfgd (SDR_DCR_BASE+0x1) /* Data */ - -#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0) -#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0) - #define sdrnand0 0x4000 #define sdrultra0 0x4040 #define sdrultra1 0x4050 @@ -1214,6 +1352,25 @@ #define GPIO1_ISR3L (GPIO1_BASE+0x40) #define GPIO1_ISR3H (GPIO1_BASE+0x44) +#elif defined(CONFIG_405EX) +#define GPIO_BASE 0xEF600800 +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRL (GPIO_BASE+0x8) +#define GPIO0_OSRH (GPIO_BASE+0xC) +#define GPIO0_TSRL (GPIO_BASE+0x10) +#define GPIO0_TSRH (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_ISR1L (GPIO_BASE+0x30) +#define GPIO0_ISR1H (GPIO_BASE+0x34) +#define GPIO0_ISR2L (GPIO_BASE+0x38) +#define GPIO0_ISR2H (GPIO_BASE+0x3C) +#define GPIO0_ISR3L (GPIO_BASE+0x40) +#define GPIO0_ISR3H (GPIO_BASE+0x44) + #else /* !405EZ */ #define GPIO_BASE 0xEF600700 @@ -1234,33 +1391,489 @@ #endif /* CONFIG_405EZ */ -/* - * Macro for accessing the indirect EBC register - */ -#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) -#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd) +#if defined(CONFIG_405EX) +#define SDR0_SRST 0x0200 + +#define SDRAM_BESR0 0x00 +#define SDRAM_BEARL 0x02 +#define SDRAM_BEARU 0x03 +#define SDRAM_WMIRQ 0x06 /**/ +#define SDRAM_PLBOPT 0x08 /**/ +#define SDRAM_PUABA 0x09 /**/ +#define SDRAM_MCSTAT 0x1F /* memory controller status */ +#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ +#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ +#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ +#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */ +#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */ +#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */ +#define SDRAM_CODT 0x26 /* on die termination for controller */ +#define SDRAM_VVPR 0x27 /* variable VRef programmming */ +#define SDRAM_OPARS 0x28 /* on chip driver control setup */ +#define SDRAM_OPART 0x29 /* on chip driver control trigger */ +#define SDRAM_RTR 0x30 /* refresh timer */ +#define SDRAM_PMIT 0x34 /* power management idle timer */ +#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */ +#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */ +#define SDRAM_MB2CF 0x48 /* memory bank 2 configuration */ +#define SDRAM_MB3CF 0x4C /* memory bank 3 configuration */ +#define SDRAM_INITPLR0 0x50 /* manual initialization control */ +#define SDRAM_INITPLR1 0x51 /* manual initialization control */ +#define SDRAM_INITPLR2 0x52 /* manual initialization control */ +#define SDRAM_INITPLR3 0x53 /* manual initialization control */ +#define SDRAM_INITPLR4 0x54 /* manual initialization control */ +#define SDRAM_INITPLR5 0x55 /* manual initialization control */ +#define SDRAM_INITPLR6 0x56 /* manual initialization control */ +#define SDRAM_INITPLR7 0x57 /* manual initialization control */ +#define SDRAM_INITPLR8 0x58 /* manual initialization control */ +#define SDRAM_INITPLR9 0x59 /* manual initialization control */ +#define SDRAM_INITPLR10 0x5a /* manual initialization control */ +#define SDRAM_INITPLR11 0x5b /* manual initialization control */ +#define SDRAM_INITPLR12 0x5c /* manual initialization control */ +#define SDRAM_INITPLR13 0x5d /* manual initialization control */ +#define SDRAM_INITPLR14 0x5e /* manual initialization control */ +#define SDRAM_INITPLR15 0x5f /* manual initialization control */ +#define SDRAM_RQDC 0x70 /* read DQS delay control */ +#define SDRAM_RFDC 0x74 /* read feedback delay control */ +#define SDRAM_RDCC 0x78 /* read data capture control */ +#define SDRAM_DLCR 0x7A /* delay line calibration */ +#define SDRAM_CLKTR 0x80 /* DDR clock timing */ +#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */ +#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */ +#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */ +#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */ +#define SDRAM_MMODE 0x88 /* memory mode */ +#define SDRAM_MEMODE 0x89 /* memory extended mode */ +#define SDRAM_ECCCR 0x98 /* ECC error status */ +#define SDRAM_RID 0xF8 /* revision ID */ + +/*-----------------------------------------------------------------------------+ +| Memory Bank 0-7 configuration ++-----------------------------------------------------------------------------*/ +#define SDRAM_RXBAS_SDSZ_4 0x00000000 /* 4M */ +#define SDRAM_RXBAS_SDSZ_8 0x00001000 /* 8M */ +#define SDRAM_RXBAS_SDSZ_16 0x00002000 /* 16M */ +#define SDRAM_RXBAS_SDSZ_32 0x00003000 /* 32M */ +#define SDRAM_RXBAS_SDSZ_64 0x00004000 /* 64M */ +#define SDRAM_RXBAS_SDSZ_128 0x00005000 /* 128M */ +#define SDRAM_RXBAS_SDSZ_256 0x00006000 /* 256M */ +#define SDRAM_RXBAS_SDSZ_512 0x00007000 /* 512M */ +#define SDRAM_RXBAS_SDSZ_1024 0x00008000 /* 1024M */ +#define SDRAM_RXBAS_SDSZ_2048 0x00009000 /* 2048M */ +#define SDRAM_RXBAS_SDSZ_4096 0x0000a000 /* 4096M */ +#define SDRAM_RXBAS_SDSZ_8192 0x0000b000 /* 8192M */ + +/*-----------------------------------------------------------------------------+ +| Memory Controller Status ++-----------------------------------------------------------------------------*/ +#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */ +#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */ +#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */ +#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */ +#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */ +#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */ + +/*-----------------------------------------------------------------------------+ +| Memory Controller Options 1 ++-----------------------------------------------------------------------------*/ +#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask */ +#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */ +#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */ +#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */ +#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/ +#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3) +#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */ +#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */ +#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */ +#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */ +#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */ +#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */ +#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */ +#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */ +#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */ +#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */ +#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */ +#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */ +#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */ +#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */ +#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */ +#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */ +#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */ +#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */ +#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */ +#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */ +#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */ +#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */ +#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */ +#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */ +#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */ +#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */ +#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */ +#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */ +#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */ + +/*-----------------------------------------------------------------------------+ +| Memory Controller Options 2 ++-----------------------------------------------------------------------------*/ +#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */ +#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */ +#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */ +#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */ +#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */ +#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */ +#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */ +#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */ +#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */ +#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */ +#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */ +#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */ +#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */ +#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */ +#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */ +#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/ +#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */ +#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */ + +/*-----------------------------------------------------------------------------+ +| SDRAM Refresh Timer Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RTR_RINT_MASK 0xFFF80000 +#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16) +#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8) + +/*-----------------------------------------------------------------------------+ +| SDRAM Read DQS Delay Control Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RQDC_RQDE_MASK 0x80000000 +#define SDRAM_RQDC_RQDE_DISABLE 0x00000000 +#define SDRAM_RQDC_RQDE_ENABLE 0x80000000 +#define SDRAM_RQDC_RQFD_MASK 0x000001FF +#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) + +#define SDRAM_RQDC_RQFD_MAX 0xFF + +/*-----------------------------------------------------------------------------+ +| SDRAM Read Data Capture Control Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RDCC_RDSS_MASK 0xC0000000 +#define SDRAM_RDCC_RDSS_T1 0x00000000 +#define SDRAM_RDCC_RDSS_T2 0x40000000 +#define SDRAM_RDCC_RDSS_T3 0x80000000 +#define SDRAM_RDCC_RDSS_T4 0xC0000000 +#define SDRAM_RDCC_RSAE_MASK 0x00000001 +#define SDRAM_RDCC_RSAE_DISABLE 0x00000001 +#define SDRAM_RDCC_RSAE_ENABLE 0x00000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM Read Feedback Delay Control Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RFDC_ARSE_MASK 0x80000000 +#define SDRAM_RFDC_ARSE_DISABLE 0x80000000 +#define SDRAM_RFDC_ARSE_ENABLE 0x00000000 +#define SDRAM_RFDC_RFOS_MASK 0x007F0000 +#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define SDRAM_RFDC_RFFD_MASK 0x000003FF +#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) + +#define SDRAM_RFDC_RFFD_MAX 0x4FF + +/*-----------------------------------------------------------------------------+ +| SDRAM Delay Line Calibration Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_DLCR_DCLM_MASK 0x80000000 +#define SDRAM_DLCR_DCLM_MANUEL 0x80000000 +#define SDRAM_DLCR_DCLM_AUTO 0x00000000 +#define SDRAM_DLCR_DLCR_MASK 0x08000000 +#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000 +#define SDRAM_DLCR_DLCR_IDLE 0x00000000 +#define SDRAM_DLCR_DLCS_MASK 0x07000000 +#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000 +#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000 +#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000 +#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000 +#define SDRAM_DLCR_DLCS_ERROR 0x04000000 +#define SDRAM_DLCR_DLCV_MASK 0x000001FF +#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) +#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF) + +/*-----------------------------------------------------------------------------+ +| SDRAM Controller On Die Termination Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_CODT_ODT_ON 0x80000000 +#define SDRAM_CODT_ODT_OFF 0x00000000 +#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020 +#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000 +#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020 +#define SDRAM_CODT_DQS_MASK 0x00000010 +#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000 +#define SDRAM_CODT_DQS_SINGLE_END 0x00000010 +#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000 +#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 +#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 +#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 +#define SDRAM_CODT_IO_HIZ 0x00000000 +#define SDRAM_CODT_IO_NMODE 0x00000001 + +/*-----------------------------------------------------------------------------+ +| SDRAM Mode Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_MMODE_WR_MASK 0x00000E00 +#define SDRAM_MMODE_WR_DDR1 0x00000000 +#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400 +#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600 +#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800 +#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00 +#define SDRAM_MMODE_DCL_MASK 0x00000070 +#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020 +#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060 +#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030 +#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020 +#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030 +#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040 +#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050 +#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060 +#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070 + +/*-----------------------------------------------------------------------------+ +| SDRAM Extended Mode Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_MEMODE_DIC_MASK 0x00000002 +#define SDRAM_MEMODE_DIC_NORMAL 0x00000000 +#define SDRAM_MEMODE_DIC_WEAK 0x00000002 +#define SDRAM_MEMODE_DLL_MASK 0x00000001 +#define SDRAM_MEMODE_DLL_DISABLE 0x00000001 +#define SDRAM_MEMODE_DLL_ENABLE 0x00000000 +#define SDRAM_MEMODE_RTT_MASK 0x00000044 +#define SDRAM_MEMODE_RTT_DISABLED 0x00000000 +#define SDRAM_MEMODE_RTT_75OHM 0x00000004 +#define SDRAM_MEMODE_RTT_150OHM 0x00000040 +#define SDRAM_MEMODE_DQS_MASK 0x00000400 +#define SDRAM_MEMODE_DQS_DISABLE 0x00000400 +#define SDRAM_MEMODE_DQS_ENABLE 0x00000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM Clock Timing Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 +#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000 +#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM Write Timing Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_WRDTR_WDTP_1_CYC 0x80000000 +#define SDRAM_WRDTR_LLWP_MASK 0x10000000 +#define SDRAM_WRDTR_LLWP_DIS 0x10000000 +#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000 +#define SDRAM_WRDTR_WTR_MASK 0x0E000000 +#define SDRAM_WRDTR_WTR_0_DEG 0x06000000 +#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000 +#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM SDTR1 Options ++-----------------------------------------------------------------------------*/ +#define SDRAM_SDTR1_LDOF_MASK 0x80000000 +#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000 +#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000 +#define SDRAM_SDTR1_RTW_MASK 0x00F00000 +#define SDRAM_SDTR1_RTW_2_CLK 0x00200000 +#define SDRAM_SDTR1_RTW_3_CLK 0x00300000 +#define SDRAM_SDTR1_WTWO_MASK 0x000F0000 +#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000 +#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000 +#define SDRAM_SDTR1_RTRO_MASK 0x0000F000 +#define SDRAM_SDTR1_RTRO_1_CLK 0x00000000 +#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000 + +/*-----------------------------------------------------------------------------+ +| SDRAM SDTR2 Options ++-----------------------------------------------------------------------------*/ +#define SDRAM_SDTR2_RCD_MASK 0xF0000000 +#define SDRAM_SDTR2_RCD_1_CLK 0x10000000 +#define SDRAM_SDTR2_RCD_2_CLK 0x20000000 +#define SDRAM_SDTR2_RCD_3_CLK 0x30000000 +#define SDRAM_SDTR2_RCD_4_CLK 0x40000000 +#define SDRAM_SDTR2_RCD_5_CLK 0x50000000 +#define SDRAM_SDTR2_WTR_MASK 0x0F000000 +#define SDRAM_SDTR2_WTR_1_CLK 0x01000000 +#define SDRAM_SDTR2_WTR_2_CLK 0x02000000 +#define SDRAM_SDTR2_WTR_3_CLK 0x03000000 +#define SDRAM_SDTR2_WTR_4_CLK 0x04000000 +#define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) +#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000 +#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000 +#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000 +#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000 +#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000 +#define SDRAM_SDTR2_WPC_MASK 0x0000F000 +#define SDRAM_SDTR2_WPC_2_CLK 0x00002000 +#define SDRAM_SDTR2_WPC_3_CLK 0x00003000 +#define SDRAM_SDTR2_WPC_4_CLK 0x00004000 +#define SDRAM_SDTR2_WPC_5_CLK 0x00005000 +#define SDRAM_SDTR2_WPC_6_CLK 0x00006000 +#define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12) +#define SDRAM_SDTR2_RPC_MASK 0x00000F00 +#define SDRAM_SDTR2_RPC_2_CLK 0x00000200 +#define SDRAM_SDTR2_RPC_3_CLK 0x00000300 +#define SDRAM_SDTR2_RPC_4_CLK 0x00000400 +#define SDRAM_SDTR2_RP_MASK 0x000000F0 +#define SDRAM_SDTR2_RP_3_CLK 0x00000030 +#define SDRAM_SDTR2_RP_4_CLK 0x00000040 +#define SDRAM_SDTR2_RP_5_CLK 0x00000050 +#define SDRAM_SDTR2_RP_6_CLK 0x00000060 +#define SDRAM_SDTR2_RP_7_CLK 0x00000070 +#define SDRAM_SDTR2_RRD_MASK 0x0000000F +#define SDRAM_SDTR2_RRD_2_CLK 0x00000002 +#define SDRAM_SDTR2_RRD_3_CLK 0x00000003 + +/*-----------------------------------------------------------------------------+ +| SDRAM SDTR3 Options ++-----------------------------------------------------------------------------*/ +#define SDRAM_SDTR3_RAS_MASK 0x1F000000 +#define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define SDRAM_SDTR3_RC_MASK 0x001F0000 +#define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) +#define SDRAM_SDTR3_XCS_MASK 0x00001F00 +#define SDRAM_SDTR3_XCS 0x00000D00 +#define SDRAM_SDTR3_RFC_MASK 0x0000003F +#define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) + +/*-----------------------------------------------------------------------------+ +| Memory Bank 0-1 configuration ++-----------------------------------------------------------------------------*/ +#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */ +#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */ +#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */ +#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */ +#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */ +#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */ +#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */ +#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */ +#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */ +#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */ +#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */ +#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */ +#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */ +#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */ + +#define sdr_uart0 0x0120 /* UART0 Config */ +#define sdr_uart1 0x0121 /* UART1 Config */ +#define sdr_mfr 0x4300 /* SDR0_MFR reg */ + +/* Defines for CPC0_EPRCSR register */ +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 + +#define cpr0_clkupd 0x020 +#define cpr0_pllc 0x040 +#define cpr0_plld 0x060 +#define cpr0_cpud 0x080 +#define cpr0_plbd 0x0a0 +#define cpr0_opbd 0x0c0 +#define cpr0_perd 0x0e0 +#define cpr0_ahbd 0x100 +#define cpr0_icfg 0x140 + +#define SDR_PINSTP 0x0040 +#define sdr_sdcs 0x0060 + +#define SDR0_SDCS_SDD (0x80000000 >> 31) + +/* CUST0 Customer Configuration Register0 */ +#define SDR0_CUST0 0x4000 +#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ +#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ +#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ +#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ + +#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ +#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ +#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ + +#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ +#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ +#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ + +#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ +#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) +#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) + +#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ +#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) +#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) + +#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ + +#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ +#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ +#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ + +#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ +#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) +#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) + +#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ +#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ +#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ +#endif + +/****************************************************************************** + * SDR Registers + ******************************************************************************/ +#define SDR_DCR_BASE 0x0E +#define sdrcfga (SDR_DCR_BASE+0x0) +#define sdrcfgd (SDR_DCR_BASE+0x1) + +#define CPR0_DCR_BASE 0x0C +#define cprcfga (CPR0_DCR_BASE+0x0) +#define cprcfgd (CPR0_DCR_BASE+0x1) + +#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) +#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) + +#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) +#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) + +#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) +#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) -#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0) -#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0) +#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) +#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) #ifndef __ASSEMBLY__ typedef struct { - unsigned long pllFwdDiv; - unsigned long pllFwdDivB; - unsigned long pllFbkDiv; - unsigned long pllPlbDiv; - unsigned long pllPciDiv; - unsigned long pllExtBusDiv; - unsigned long pllOpbDiv; - unsigned long freqVCOMhz; /* in MHz */ - unsigned long freqProcessor; - unsigned long freqPLB; - unsigned long freqPCI; - unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ - unsigned long pciClkSync; /* PCI clock is synchronous */ - unsigned long freqVCOHz; + unsigned long pllFwdDiv; + unsigned long pllFwdDivB; + unsigned long pllFbkDiv; + unsigned long pllPlbDiv; + unsigned long pllPciDiv; + unsigned long pllExtBusDiv; + unsigned long pllOpbDiv; + unsigned long freqVCOMhz; /* in MHz */ + unsigned long freqProcessor; + unsigned long freqPLB; + unsigned long freqPCI; + unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ + unsigned long pciClkSync; /* PCI clock is synchronous */ + unsigned long freqVCOHz; + unsigned long freqOPB; + unsigned long freqEBC; + unsigned long freqDDR; } PPC405_SYS_INFO; #endif /* _ASMLANGUAGE */ diff --git a/include/ppc440.h b/include/ppc440.h index 38809f34b4b..e77c4c3fb66 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -3345,7 +3345,7 @@ typedef struct { unsigned long freqTmrClk; unsigned long freqPLB; unsigned long freqOPB; - unsigned long freqEPB; + unsigned long freqEBC; unsigned long freqPCI; #ifdef CONFIG_440SPE unsigned long freqDDR; diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h index 3d8ca090600..76c1d127efb 100644 --- a/include/ppc4xx_enet.h +++ b/include/ppc4xx_enet.h @@ -146,11 +146,12 @@ typedef struct emac_4xx_hw_st { #endif #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) #define SDR0_PFC1_EM_1000 (0x00200000) #endif -/*ZMII Bridge Register addresses */ +/* ZMII Bridge Register addresses */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00) @@ -202,6 +203,8 @@ typedef struct emac_4xx_hw_st { /* RGMII Register Addresses */ #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x1000) +#elif defined(CONFIG_405EX) +#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0xB00) #else #define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x0790) #endif @@ -223,7 +226,8 @@ typedef struct emac_4xx_hw_st { #define RGMII_SSR_SP_100MBPS (0x02) #define RGMII_SSR_SP_1000MBPS (0x04) -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) #define RGMII_SSR_V(__x) ((__x) * 8) #else #define RGMII_SSR_V(__x) ((__x -2) * 8) @@ -304,7 +308,7 @@ typedef struct emac_4xx_hw_st { #define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800) #endif #else -#if defined(CONFIG_405EZ) +#if defined(CONFIG_405EZ) || defined(CONFIG_405EX) #define EMAC_BASE 0xEF600900 #else #define EMAC_BASE 0xEF600800 @@ -338,7 +342,8 @@ typedef struct emac_4xx_hw_st { /* on 440GX EMAC_MR1 has a different layout! */ #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_405EX) /* MODE Reg 1 */ #define EMAC_M1_FDE (0x80000000) #define EMAC_M1_ILE (0x40000000) diff --git a/include/serial.h b/include/serial.h index 30bfde3089b..e292f0cd901 100644 --- a/include/serial.h +++ b/include/serial.h @@ -22,8 +22,9 @@ extern struct serial_device serial_smc_device; extern struct serial_device serial_scc_device; extern struct serial_device * default_serial_console (void); -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ - || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ + defined(CONFIG_MPC5xxx) extern struct serial_device serial0_device; extern struct serial_device serial1_device; #if defined(CFG_NS16550_SERIAL) -- cgit v1.3.1 From 1941cce71b1ae975602854045061e82f94ecd012 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 5 Oct 2007 17:35:10 +0200 Subject: ppc4xx: Fix small merge problem in 4xx_enet.c Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_enet.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 841cb77d6de..6b4834481e3 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -139,7 +139,7 @@ #define BI_PHYMODE_MII 7 #endif -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) \ +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EX) #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1)) -- cgit v1.3.1 From 4994ffd890b9d95d807387a9b7bd8a4803ee406e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 11 Oct 2007 11:11:45 +0200 Subject: ppc4xx: Add additional debug info to 4xx fdt support Signed-off-by: Stefan Roese --- cpu/ppc4xx/fdt.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'cpu') diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c index a1c81e60b46..2acb250e055 100644 --- a/cpu/ppc4xx/fdt.c +++ b/cpu/ppc4xx/fdt.c @@ -123,6 +123,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) tmp[0] = cpu_to_fdt32(bd->bi_memstart); tmp[1] = cpu_to_fdt32(bd->bi_memsize); fdt_setprop(blob, offset, "reg", tmp, sizeof(tmp)); + debug("Updating /memory node to %d:%d\n", + bd->bi_memstart, bd->bi_memsize); } /* -- cgit v1.3.1 From d4cb2d17946466740afeb195a57d6cb290bf4cc0 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 13 Oct 2007 16:43:23 +0200 Subject: ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint mode This patch adds support for dynamic configuration of PCIe ports for the AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe boards Yucca & Katmai and the 405EX board Kilauea. This dynamic configuration is done via the "pcie_mode" environement variable. This variable can be set to "EP" or "RP" for endpoint or rootpoint mode. Multiple values can be joined via the ":" delimiter. Here an example: pcie_mode=RP:EP:EP This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2 as endpoint. Per default Yucca will be configured as: pcie_mode=RP:EP:EP Per default Katmai will be configured as: pcie_mode=RP:RP:REP Per default Kilauea will be configured as: pcie_mode=RP:RP Signed-off-by: Tirumala R Marri Signed-off-by: Stefan Roese --- board/amcc/katmai/katmai.c | 65 +++++++++++++++++++-------------------- board/amcc/kilauea/kilauea.c | 66 +++++++++++++++++++-------------------- board/amcc/yucca/yucca.c | 73 ++++++++++++++++++++++---------------------- cpu/ppc4xx/4xx_pcie.c | 22 ++++++++++++- include/asm-ppc/4xx_pcie.h | 52 +++++++++++++++++++++++++++++++ include/configs/katmai.h | 1 + include/configs/kilauea.h | 1 + include/configs/yucca.h | 1 + 8 files changed, 176 insertions(+), 105 deletions(-) (limited to 'cpu') diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index f1c352cb86e..0627a7a095c 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -30,9 +30,6 @@ #include #include -#undef PCIE_ENDPOINT -/* #define PCIE_ENDPOINT 1 */ - DECLARE_GLOBAL_DATA_PTR; int board_early_init_f (void) @@ -392,6 +389,7 @@ void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; + int ret = 0; char *env; unsigned int delay; @@ -405,11 +403,14 @@ void pcie_setup_hoses(int busno) if (!katmai_pcie_card_present(i)) continue; -#ifdef PCIE_ENDPOINT - if (ppc4xx_init_pcie_endport(i)) { -#else - if (ppc4xx_init_pcie_rootport(i)) { -#endif + if (is_end_point(i)) { + printf("PCIE%d: will be configured as endpoint\n", i); + ret = ppc4xx_init_pcie_endport(i); + } else { + printf("PCIE%d: will be configured as root-complex\n", i); + ret = ppc4xx_init_pcie_rootport(i); + } + if (ret) { printf("PCIE%d: initialization failed\n", i); continue; } @@ -424,35 +425,33 @@ void pcie_setup_hoses(int busno) CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, CFG_PCIE_MEMSIZE, - PCI_REGION_MEM - ); + PCI_REGION_MEM); hose->region_count = 1; pci_register_hose(hose); -#ifdef PCIE_ENDPOINT - ppc4xx_setup_pcie_endpoint(hose, i); - /* - * Reson for no scanning is endpoint can not generate - * upstream configuration accesses. - */ -#else - ppc4xx_setup_pcie_rootpoint(hose, i); - - env = getenv ("pciscandelay"); - if (env != NULL) { - delay = simple_strtoul (env, NULL, 10); - if (delay > 5) - printf ("Warning, expect noticable delay before PCIe" - "scan due to 'pciscandelay' value!\n"); - mdelay (delay * 1000); + if (is_end_point(i)) { + ppc4xx_setup_pcie_endpoint(hose, i); + /* + * Reson for no scanning is endpoint can not generate + * upstream configuration accesses. + */ + } else { + ppc4xx_setup_pcie_rootpoint(hose, i); + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul(env, NULL, 10); + if (delay > 5) + printf("Warning, expect noticable delay before " + "PCIe scan due to 'pciscandelay' value!\n"); + mdelay(delay * 1000); + } + + /* + * Config access can only go down stream + */ + hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; } - - /* - * Config access can only go down stream - */ - hose->last_busno = pci_hose_scan(hose); - bus = hose->last_busno + 1; -#endif } } #endif /* defined(CONFIG_PCI) */ diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c index 8767f758810..b59bd6fc0e2 100644 --- a/board/amcc/kilauea/kilauea.c +++ b/board/amcc/kilauea/kilauea.c @@ -299,35 +299,29 @@ void pci_target_init(struct pci_controller * hose ) #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ #ifdef CONFIG_PCI -static int pcie_port_is_rootpoint(int port) -{ - return 1; -} - static struct pci_controller pcie_hose[2] = {{0},{0}}; void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; + int ret = 0; bus = busno; char *env; unsigned int delay; for (i = 0; i < 2; i++) { - if (pcie_port_is_rootpoint(i)) { - printf("PORT%d will be configured as root-complex\n", i); - if (ppc4xx_init_pcie_rootport(i)) { - printf("PCIE%d: initialization failed\n", i); - continue; - } + if (is_end_point(i)) { + printf("PCIE%d: will be configured as endpoint\n", i); + ret = ppc4xx_init_pcie_endport(i); } else { - printf("PORT%d will be configured as endpoint\n", i); - if (ppc4xx_init_pcie_endport(i)) { - printf("PCIE%d: initialization failed\n", i); - continue; - } + printf("PCIE%d: will be configured as root-complex\n", i); + ret = ppc4xx_init_pcie_rootport(i); + } + if (ret) { + printf("PCIE%d: initialization failed\n", i); + continue; } hose = &pcie_hose[i]; @@ -344,25 +338,29 @@ void pcie_setup_hoses(int busno) hose->region_count = 1; pci_register_hose(hose); - if (pcie_port_is_rootpoint(i)) - ppc4xx_setup_pcie_rootpoint(hose, i); - else - ppc4xx_setup_pcie_endpoint(hose, i); - - env = getenv("pciscandelay"); - if (env != NULL) { - delay = simple_strtoul(env, NULL, 10); - if (delay > 5) - printf("Warning, expect noticable delay before PCIe" - "scan due to 'pciscandelay' value!\n"); - mdelay(delay * 1000); - } + if (is_end_point(i)) { + ppc4xx_setup_pcie_endpoint(hose, i); + /* + * Reson for no scanning is endpoint can not generate + * upstream configuration accesses. + */ + } else { + ppc4xx_setup_pcie_rootpoint(hose, i); + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul(env, NULL, 10); + if (delay > 5) + printf("Warning, expect noticable delay before " + "PCIe scan due to 'pciscandelay' value!\n"); + mdelay(delay * 1000); + } - /* - * Config access can only go down stream - */ - hose->last_busno = pci_hose_scan(hose); - bus = hose->last_busno + 1; + /* + * Config access can only go down stream + */ + hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; + } } } #endif diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index c46721c9229..efdf814bf08 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -36,11 +36,8 @@ DECLARE_GLOBAL_DATA_PTR; -#undef PCIE_ENDPOINT -/* #define PCIE_ENDPOINT 1 */ void fpga_init (void); - void get_sys_info(PPC440_SYS_INFO *board_cfg ); int compare_to_true(char *str ); char *remove_l_w_space(char *in_str ); @@ -847,6 +844,7 @@ void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; + int ret = 0; char *env; unsigned int delay; @@ -860,16 +858,19 @@ void pcie_setup_hoses(int busno) if (!yucca_pcie_card_present(i)) continue; -#ifdef PCIE_ENDPOINT - yucca_setup_pcie_fpga_endpoint(i); - if (ppc4xx_init_pcie_endport(i)) { -#else - yucca_setup_pcie_fpga_rootpoint(i); - if (ppc4xx_init_pcie_rootport(i)) { -#endif - printf("PCIE%d: initialization failed\n", i); - continue; + if (is_end_point(i)) { + printf("PCIE%d: will be configured as endpoint\n",i); + yucca_setup_pcie_fpga_endpoint(i); + ret = ppc4xx_init_pcie_endport(i); + } else { + printf("PCIE%d: will be configured as root-complex\n",i); + yucca_setup_pcie_fpga_rootpoint(i); + ret = ppc4xx_init_pcie_rootport(i); } + if (ret) { + printf("PCIE%d: initialization failed\n", i); + continue; + } hose = &pcie_hose[i]; hose->first_busno = bus; @@ -881,35 +882,33 @@ void pcie_setup_hoses(int busno) CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, CFG_PCIE_MEMSIZE, - PCI_REGION_MEM - ); + PCI_REGION_MEM); hose->region_count = 1; pci_register_hose(hose); -#ifdef PCIE_ENDPOINT - ppc4xx_setup_pcie_endpoint(hose, i); - /* - * Reson for no scanning is endpoint can not generate - * upstream configuration accesses. - */ -#else - ppc4xx_setup_pcie_rootpoint(hose, i); - - env = getenv ("pciscandelay"); - if (env != NULL) { - delay = simple_strtoul (env, NULL, 10); - if (delay > 5) - printf ("Warning, expect noticable delay before PCIe" - "scan due to 'pciscandelay' value!\n"); - mdelay (delay * 1000); - } + if (is_end_point(i)) { + ppc4xx_setup_pcie_endpoint(hose, i); + /* + * Reson for no scanning is endpoint can not generate + * upstream configuration accesses. + */ + } else { + ppc4xx_setup_pcie_rootpoint(hose, i); + env = getenv("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul(env, NULL, 10); + if (delay > 5) + printf("Warning, expect noticable delay before " + "PCIe scan due to 'pciscandelay' value!\n"); + mdelay(delay * 1000); + } - /* - * Config access can only go down stream - */ - hose->last_busno = pci_hose_scan(hose); - bus = hose->last_busno + 1; -#endif + /* + * Config access can only go down stream + */ + hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; + } } } #endif /* defined(CONFIG_PCI) */ diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index 7ee0e5bc89d..9ab358857ad 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -46,6 +46,20 @@ enum { LNKW_X8 = 0x8 }; +static int validate_endpoint(struct pci_controller *hose) +{ + if (hose->cfg_data == (u8 *)CFG_PCIE0_CFGBASE) + return (is_end_point(0)); + else if (hose->cfg_data == (u8 *)CFG_PCIE1_CFGBASE) + return (is_end_point(1)); +#if CFG_PCIE_NR_PORTS > 2 + else if (hose->cfg_data == (u8 *)CFG_PCIE2_CFGBASE) + return (is_end_point(2)); +#endif + + return 0; +} + static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn) { u8 *base = (u8*)hose->cfg_data; @@ -95,6 +109,9 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, u8 *address; *val = 0; + if (validate_endpoint(hose)) + return 0; /* No upstream config access */ + /* * Bus numbers are relative to hose->first_busno */ @@ -150,6 +167,9 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, u8 *address; + if (validate_endpoint(hose)) + return 0; /* No upstream config access */ + /* * Bus numbers are relative to hose->first_busno */ @@ -595,9 +615,9 @@ int ppc4xx_init_pcie_port(int port, int rootport) u32 low, high; if (!core_init) { - ++core_init; if (ppc4xx_init_pcie()) return -1; + ++core_init; } /* diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index 17ac57b23bc..1830c6a8efd 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -244,6 +244,9 @@ #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL)) #define U64_TO_U32_HIGH(val) ((u32)((val) >> 32)) +/* + * Prototypes + */ int ppc4xx_init_pcie(void); int ppc4xx_init_pcie_rootport(int port); int ppc4xx_init_pcie_endport(int port); @@ -251,6 +254,55 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port); int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port); int pcie_hose_scan(struct pci_controller *hose, int bus); +/* + * Function to determine root port or endport from env variable. + */ +static inline int is_end_point(int port) +{ + static char s[10], *tk; + + strcpy(s, getenv("pcie_mode")); + tk = strtok(s, ":"); + + switch (port) { + case 0: + if (tk != NULL) { + if (!(strcmp(tk, "ep") && strcmp(tk, "EP"))) + return 1; + else + return 0; + } + else + return 0; + + case 1: + tk = strtok(NULL, ":"); + if (tk != NULL) { + if (!(strcmp(tk, "ep") && strcmp(tk, "EP"))) + return 1; + else + return 0; + } + else + return 0; + + case 2: + tk = strtok(NULL, ":"); + if (tk != NULL) + tk = strtok(NULL, ":"); + if (tk != NULL) { + if (!(strcmp(tk, "ep") && strcmp(tk, "EP"))) + return 1; + else + return 0; + } + else + return 0; + } + + return 0; +} + static inline void mdelay(int n) { u32 ms = n; diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 8a963279f08..cccfc1316d5 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -205,6 +205,7 @@ "upd=run load;run update\0" \ "kozio=bootm ffc60000\0" \ "pciconfighost=1\0" \ + "pcie_mode=RP:RP:RP\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 461f8f0591d..f5e20235f74 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -205,6 +205,7 @@ "setenv filesize;saveenv\0" \ "nupd=run nload nupdate\0" \ "pciconfighost=1\0" \ + "pcie_mode=RP:RP\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/yucca.h b/include/configs/yucca.h index ab7fb0ab8c2..2b4024dfd97 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -186,6 +186,7 @@ "setenv filesize;saveenv\0" \ "upd=run load;run update\0" \ "pciconfighost=1\0" \ + "pcie_mode=RP:EP:EP\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" -- cgit v1.3.1 From 5cb4af4791f61843432155142b6cfac901f66c10 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 18 Oct 2007 07:39:38 +0200 Subject: ppc4xx: Add PCIe endpoint support on Kilauea (405EX) This patch adds endpoint support for the AMCC Kilauea eval board. It can be tested by connecting a reworked PCIe cable (only 1x lane singles connected) to another root-complex. In this test setup, a 64MB inbound window is configured at BAR0 which maps to 0 on the PLB side. So accessing this BAR0 from the root-complex will access the first 64MB of the SDRAM on the PPC side. Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_pcie.c | 31 +++++++++++++++++++++---------- include/asm-ppc/4xx_pcie.h | 11 ++++++++--- 2 files changed, 29 insertions(+), 13 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index 9ab358857ad..da179f9c3a8 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -474,12 +474,6 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport) { u32 val; - /* - * test-only: - * This needs some testing and perhaps changes for - * endpoint configuration. Probably no PHY reset at all, etc. - * sr, 2007-10-03 - */ if (rootport) val = 0x00401000; else @@ -496,7 +490,10 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport) udelay(1000); /* deassert the PE0_hotreset */ - SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000); + if (is_end_point(port)) + SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01111000); + else + SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000); /* poll for phy !reset */ while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000)) @@ -903,11 +900,22 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) #endif } - /* Set up 16GB inbound memory window at 0 */ + /* Set up 64MB inbound memory window at 0 */ out_le32(mbase + PCI_BASE_ADDRESS_0, 0); out_le32(mbase + PCI_BASE_ADDRESS_1, 0); - out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); - out_le32(mbase + PECFG_BAR0LMPA, 0); + + out_le32(mbase + PECFG_PIM01SAH, 0xffffffff); + out_le32(mbase + PECFG_PIM01SAL, 0xfc000000); + + /* Setup BAR0 */ + out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffff); + out_le32(mbase + PECFG_BAR0LMPA, 0xfc000000 | PCI_BASE_ADDRESS_MEM_TYPE_64); + + /* Disable BAR1 & BAR2 */ + out_le32(mbase + PECFG_BAR1MPA, 0); + out_le32(mbase + PECFG_BAR2HMPA, 0); + out_le32(mbase + PECFG_BAR2LMPA, 0); + out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CFG_PCIE_INBOUND_BASE)); out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CFG_PCIE_INBOUND_BASE)); out_le32(mbase + PECFG_PIMEN, 0x1); @@ -919,6 +927,9 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */ out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */ + /* Set Class Code to Processor/PPC */ + out_le32(mbase + 0x208, 0x0b200001); + attempts = 10; while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) { if (!(attempts--)) { diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index 1830c6a8efd..ffe07706a31 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -218,7 +218,8 @@ #define PECFG_BAR0LMPA 0x210 #define PECFG_BAR0HMPA 0x214 #define PECFG_BAR1MPA 0x218 -#define PECFG_BAR2MPA 0x220 +#define PECFG_BAR2LMPA 0x220 +#define PECFG_BAR2HMPA 0x224 #define PECFG_PIMEN 0x33c #define PECFG_PIM0LAL 0x340 @@ -259,9 +260,13 @@ int pcie_hose_scan(struct pci_controller *hose, int bus); */ static inline int is_end_point(int port) { - static char s[10], *tk; + char s[10], *tk; + char *pcie_mode = getenv("pcie_mode"); - strcpy(s, getenv("pcie_mode")); + if (pcie_mode == NULL) + return 0; + + strcpy(s, pcie_mode); tk = strtok(s, ":"); switch (port) { -- cgit v1.3.1 From 087dfdb79b5fd1ab99a26990c62a732c01a8c7f6 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sun, 21 Oct 2007 08:12:41 +0200 Subject: ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx This patch moves some common 4xx macros and the PPC405_SYS_INFO/ PPC440_SYS_INFO structure into the common ppc4xx.h header. Lot's of other macros are good candidates to be consolidated this way in the future. Signed-off-by: Stefan Roese --- board/amcc/taishan/showinfo.c | 14 +++---- board/amcc/yucca/yucca.c | 6 --- board/lwmon5/sdram.c | 2 +- board/mpl/common/common_util.c | 2 +- board/netstal/hcu5/sdram.c | 2 +- board/xilinx/ml300/ml300.c | 2 +- cpu/ppc4xx/40x_spd_sdram.c | 2 +- cpu/ppc4xx/44x_spd_ddr.c | 6 +-- cpu/ppc4xx/44x_spd_ddr2.c | 27 ++++++------- cpu/ppc4xx/speed.c | 30 +++++++-------- include/common.h | 4 +- include/ppc405.h | 58 ---------------------------- include/ppc440.h | 87 ------------------------------------------ include/ppc4xx.h | 73 +++++++++++++++++++++++++++++++++-- 14 files changed, 113 insertions(+), 202 deletions(-) (limited to 'cpu') diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c index 57b9d1c4218..040b8004dac 100644 --- a/board/amcc/taishan/showinfo.c +++ b/board/amcc/taishan/showinfo.c @@ -33,25 +33,25 @@ void show_reset_reg(void) /* read clock regsiter */ printf("===== Display reset and initialize register Start =========\n"); - mfclk(clk_pllc,reg); + mfcpr(clk_pllc,reg); printf("cpr_pllc = %#010x\n",reg); - mfclk(clk_plld,reg); + mfcpr(clk_plld,reg); printf("cpr_plld = %#010x\n",reg); - mfclk(clk_primad,reg); + mfcpr(clk_primad,reg); printf("cpr_primad = %#010x\n",reg); - mfclk(clk_primbd,reg); + mfcpr(clk_primbd,reg); printf("cpr_primbd = %#010x\n",reg); - mfclk(clk_opbd,reg); + mfcpr(clk_opbd,reg); printf("cpr_opbd = %#010x\n",reg); - mfclk(clk_perd,reg); + mfcpr(clk_perd,reg); printf("cpr_perd = %#010x\n",reg); - mfclk(clk_mald,reg); + mfcpr(clk_mald,reg); printf("cpr_mald = %#010x\n",reg); /* read sdr register */ diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index efdf814bf08..bb3e59400f0 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -36,13 +36,7 @@ DECLARE_GLOBAL_DATA_PTR; - void fpga_init (void); -void get_sys_info(PPC440_SYS_INFO *board_cfg ); -int compare_to_true(char *str ); -char *remove_l_w_space(char *in_str ); -char *remove_t_w_space(char *in_str ); -int get_console_port(void); #define DEBUG_ENV #ifdef DEBUG_ENV diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index d4547e24cf1..399da8ae654 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -71,7 +71,7 @@ static u32 is_ecc_enabled(void) void board_add_ram_info(int use_default) { - PPC440_SYS_INFO board_cfg; + PPC4xx_SYS_INFO board_cfg; u32 val; if (is_ecc_enabled()) diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index f3aa0a73007..8d4cbe852e9 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -587,7 +587,7 @@ extern int get_boot_mode(void); void video_get_info_str (int line_number, char *info) { /* init video info strings for graphic console */ - PPC405_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; char rev; int i,boot; unsigned long pvr; diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 9ee9ab599b6..cbb2839cc02 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -72,7 +72,7 @@ void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); void board_add_ram_info(int use_default) { - PPC440_SYS_INFO board_cfg; + PPC4xx_SYS_INFO board_cfg; u32 val; mfsdram(DDR0_22, val); val &= DDR0_22_CTRL_RAW_MASK; diff --git a/board/xilinx/ml300/ml300.c b/board/xilinx/ml300/ml300.c index 60f0bc24e78..58bfac07166 100644 --- a/board/xilinx/ml300/ml300.c +++ b/board/xilinx/ml300/ml300.c @@ -108,7 +108,7 @@ ulong get_PCI_freq(void) { ulong val; - PPC405_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; get_sys_info(&sys_info); val = sys_info.freqPCI; diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c index 19c4f764e39..42fd7fb872f 100644 --- a/cpu/ppc4xx/40x_spd_sdram.c +++ b/cpu/ppc4xx/40x_spd_sdram.c @@ -148,7 +148,7 @@ long int spd_sdram(int(read_spd)(uint addr)) int t_rc; int min_cas; - PPC405_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; unsigned long bus_period_x_10; /* diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index 4a4c6f29edf..65ce46daf34 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -645,7 +645,7 @@ static void program_rtr(unsigned long *dimm_populated, unsigned char refresh_rate_type; unsigned long refresh_interval; unsigned long sdram_rtr; - PPC440_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; /* * get the board info @@ -721,7 +721,7 @@ static void program_tr0(unsigned long *dimm_populated, unsigned long tcyc_2_0_ns_x_10; unsigned long tcyc_reg; unsigned long bus_period_x_10; - PPC440_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; unsigned long residue; /* @@ -1065,7 +1065,7 @@ static void program_tr1(void) unsigned char window_found; unsigned char fail_found; unsigned char pass_found; - PPC440_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; /* * get the board info diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 67ba5bdef24..b3413671b51 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -623,7 +623,7 @@ static void get_spd_info(unsigned long *dimm_populated, void board_add_ram_info(int use_default) { - PPC440_SYS_INFO board_cfg; + PPC4xx_SYS_INFO board_cfg; u32 val; if (is_ecc_enabled()) @@ -741,7 +741,7 @@ static void check_frequency(unsigned long *dimm_populated, unsigned long calc_cycle_time; unsigned long sdram_freq; unsigned long sdr_ddrpll; - PPC440_SYS_INFO board_cfg; + PPC4xx_SYS_INFO board_cfg; /*------------------------------------------------------------------ * Get the board configuration info. @@ -1353,7 +1353,7 @@ static void program_mode(unsigned long *dimm_populated, unsigned long max_4_0_tcyc_ns_x_100; unsigned long max_5_0_tcyc_ns_x_100; unsigned long cycle_time_ns_x_100[3]; - PPC440_SYS_INFO board_cfg; + PPC4xx_SYS_INFO board_cfg; unsigned char cas_2_0_available; unsigned char cas_2_5_available; unsigned char cas_3_0_available; @@ -1640,7 +1640,7 @@ static void program_rtr(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks) { - PPC440_SYS_INFO board_cfg; + PPC4xx_SYS_INFO board_cfg; unsigned long max_refresh_rate; unsigned long dimm_num; unsigned long refresh_rate_type; @@ -1737,7 +1737,7 @@ static void program_tr(unsigned long *dimm_populated, unsigned long sdram_freq; unsigned long sdr_ddrpll; - PPC440_SYS_INFO board_cfg; + PPC4xx_SYS_INFO board_cfg; /*------------------------------------------------------------------ * Get the board configuration info. @@ -2048,14 +2048,10 @@ static void program_bxcf(unsigned long *dimm_populated, /*------------------------------------------------------------------ * Set the BxCF regs. First, wipe out the bank config registers. *-----------------------------------------------------------------*/ - mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF); - mtdcr(SDRAMC_CFGDATA, 0x00000000); - mtdcr(SDRAMC_CFGADDR, SDRAM_MB1CF); - mtdcr(SDRAMC_CFGDATA, 0x00000000); - mtdcr(SDRAMC_CFGADDR, SDRAM_MB2CF); - mtdcr(SDRAMC_CFGDATA, 0x00000000); - mtdcr(SDRAMC_CFGADDR, SDRAM_MB3CF); - mtdcr(SDRAMC_CFGDATA, 0x00000000); + mtsdram(SDRAM_MB0CF, 0x00000000); + mtsdram(SDRAM_MB1CF, 0x00000000); + mtsdram(SDRAM_MB2CF, 0x00000000); + mtsdram(SDRAM_MB3CF, 0x00000000); mode = SDRAM_BXCF_M_BE_ENABLE; @@ -2107,8 +2103,9 @@ static void program_bxcf(unsigned long *dimm_populated, bank_0_populated = 1; for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) { - mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF + ((dimm_num + bank_0_populated + ind_rank) << 2)); - mtdcr(SDRAMC_CFGDATA, mode); + mtsdram(SDRAM_MB0CF + + ((dimm_num + bank_0_populated + ind_rank) << 2), + mode); } } } diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 750b0958762..26182dabf01 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_405GP) || defined(CONFIG_405CR) -void get_sys_info (PPC405_SYS_INFO * sysInfo) +void get_sys_info (PPC4xx_SYS_INFO * sysInfo) { unsigned long pllmr; unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000); @@ -173,7 +173,7 @@ ulong get_OPB_freq (void) { ulong val = 0; - PPC405_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; get_sys_info (&sys_info); val = sys_info.freqPLB / sys_info.pllOpbDiv; @@ -189,7 +189,7 @@ ulong get_OPB_freq (void) ulong get_PCI_freq (void) { ulong val; - PPC405_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; get_sys_info (&sys_info); val = sys_info.freqPLB / sys_info.pllPciDiv; @@ -216,7 +216,7 @@ void get_sys_info (sys_info_t *sysInfo) */ /* Decode CPR0_PLLD0 for divisors */ - mfclk(clk_plld, reg); + mfcpr(clk_plld, reg); temp = (reg & PLLD_FWDVA_MASK) >> 16; sysInfo->pllFwdDivA = temp ? temp : 16; temp = (reg & PLLD_FWDVB_MASK) >> 8; @@ -225,19 +225,19 @@ void get_sys_info (sys_info_t *sysInfo) sysInfo->pllFbkDiv = temp ? temp : 32; lfdiv = reg & PLLD_LFBDV_MASK; - mfclk(clk_opbd, reg); + mfcpr(clk_opbd, reg); temp = (reg & OPBDDV_MASK) >> 24; sysInfo->pllOpbDiv = temp ? temp : 4; - mfclk(clk_perd, reg); + mfcpr(clk_perd, reg); temp = (reg & PERDV_MASK) >> 24; sysInfo->pllExtBusDiv = temp ? temp : 8; - mfclk(clk_primbd, reg); + mfcpr(clk_primbd, reg); temp = (reg & PRBDV_MASK) >> 24; prbdv0 = temp ? temp : 8; - mfclk(clk_spcid, reg); + mfcpr(clk_spcid, reg); temp = (reg & SPCID_MASK) >> 24; sysInfo->pllPciDiv = temp ? temp : 4; @@ -246,7 +246,7 @@ void get_sys_info (sys_info_t *sysInfo) temp = (reg & PLLSYS0_SEL_MASK) >> 27; if (temp == 0) { /* PLL output */ /* Figure which pll to use */ - mfclk(clk_pllc, reg); + mfcpr(clk_pllc, reg); temp = (reg & PLLC_SRC_MASK) >> 29; if (!temp) /* PLLOUTA */ m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA; @@ -650,7 +650,7 @@ void get_sys_info (sys_info_t * sysInfo) { } #elif defined(CONFIG_405EP) -void get_sys_info (PPC405_SYS_INFO * sysInfo) +void get_sys_info (PPC4xx_SYS_INFO * sysInfo) { unsigned long pllmr0; unsigned long pllmr1; @@ -746,7 +746,7 @@ ulong get_OPB_freq (void) { ulong val = 0; - PPC405_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; get_sys_info (&sys_info); val = sys_info.freqPLB / sys_info.pllOpbDiv; @@ -762,7 +762,7 @@ ulong get_OPB_freq (void) ulong get_PCI_freq (void) { ulong val; - PPC405_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; get_sys_info (&sys_info); val = sys_info.freqPLB / sys_info.pllPciDiv; @@ -770,7 +770,7 @@ ulong get_PCI_freq (void) } #elif defined(CONFIG_405EZ) -void get_sys_info (PPC405_SYS_INFO * sysInfo) +void get_sys_info (PPC4xx_SYS_INFO * sysInfo) { unsigned long cpr_plld; unsigned long cpr_pllc; @@ -871,7 +871,7 @@ ulong get_OPB_freq (void) { ulong val = 0; - PPC405_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; get_sys_info (&sys_info); val = (CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / sys_info.pllOpbDiv; @@ -1032,7 +1032,7 @@ ulong get_OPB_freq (void) { ulong val = 0; - PPC405_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; get_sys_info (&sys_info); val = sys_info.freqPLB / sys_info.pllOpbDiv; diff --git a/include/common.h b/include/common.h index 98655914f72..46ed6bd97b3 100644 --- a/include/common.h +++ b/include/common.h @@ -513,15 +513,13 @@ void get_sys_info ( sys_info_t * ); #if defined(CONFIG_4xx) || defined(CONFIG_IOP480) # if defined(CONFIG_440) - typedef PPC440_SYS_INFO sys_info_t; # if defined(CONFIG_440SPE) unsigned long determine_sysper(void); unsigned long determine_pci_clock_per(void); int ppc440spe_revB(void); # endif -# else - typedef PPC405_SYS_INFO sys_info_t; # endif +typedef PPC4xx_SYS_INFO sys_info_t; void get_sys_info ( sys_info_t * ); #endif diff --git a/include/ppc405.h b/include/ppc405.h index 4d2514425e2..97528e88a82 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -344,9 +344,6 @@ /****************************************************************************** * SDRAM Controller ******************************************************************************/ -#define SDRAM_DCR_BASE 0x10 -#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */ -#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */ /* values for memcfga register - indirect addressing of these regs */ #ifndef CONFIG_405EP #define mem_besra 0x00 /* bus error syndrome reg a */ @@ -412,9 +409,6 @@ /****************************************************************************** * Extrnal Bus Controller ******************************************************************************/ -#define EBC_DCR_BASE 0x12 -#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */ -#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */ /* values for ebccfga register - indirect addressing of these regs */ #define pb0cr 0x00 /* periph bank 0 config reg */ #define pb1cr 0x01 /* periph bank 1 config reg */ @@ -1574,56 +1568,4 @@ #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ #endif -/****************************************************************************** - * SDR Registers - ******************************************************************************/ -#define SDR_DCR_BASE 0x0E -#define sdrcfga (SDR_DCR_BASE+0x0) -#define sdrcfgd (SDR_DCR_BASE+0x1) - -#define CPR0_DCR_BASE 0x0C -#define cprcfga (CPR0_DCR_BASE+0x0) -#define cprcfgd (CPR0_DCR_BASE+0x1) - -#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) -#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) - -#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) -#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) - -#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) -#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) - -#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) -#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) - -#ifndef __ASSEMBLY__ - -typedef struct -{ - unsigned long pllFwdDiv; - unsigned long pllFwdDivB; - unsigned long pllFbkDiv; - unsigned long pllPlbDiv; - unsigned long pllPciDiv; - unsigned long pllExtBusDiv; - unsigned long pllOpbDiv; - unsigned long freqVCOMhz; /* in MHz */ - unsigned long freqProcessor; - unsigned long freqPLB; - unsigned long freqPCI; - unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ - unsigned long pciClkSync; /* PCI clock is synchronous */ - unsigned long freqVCOHz; - unsigned long freqOPB; - unsigned long freqEBC; - unsigned long freqDDR; -} PPC405_SYS_INFO; - -#endif /* _ASMLANGUAGE */ - -#define RESET_VECTOR 0xfffffffc -#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache - line aligned data. */ - #endif /* __PPC405_H__ */ diff --git a/include/ppc440.h b/include/ppc440.h index e77c4c3fb66..dc5eb98c909 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -123,10 +123,6 @@ /*----------------------------------------------------------------------------- | Clocking Controller +----------------------------------------------------------------------------*/ -#define CLOCKING_DCR_BASE 0x0c -#define clkcfga (CLOCKING_DCR_BASE+0x0) -#define clkcfgd (CLOCKING_DCR_BASE+0x1) - /* values for clkcfga register - indirect addressing of these regs */ #define clk_clkukpd 0x0020 #define clk_pllc 0x0040 @@ -140,9 +136,6 @@ #define clk_icfg 0x0140 /* 440gx sdr register definations */ -#define SDR_DCR_BASE 0x0e -#define sdrcfga (SDR_DCR_BASE+0x0) -#define sdrcfgd (SDR_DCR_BASE+0x1) #define sdr_sdstp0 0x0020 /* */ #define sdr_sdstp1 0x0021 /* */ #define SDR_PINSTP 0x0040 @@ -242,10 +235,6 @@ /*----------------------------------------------------------------------------- | SDRAM Controller +----------------------------------------------------------------------------*/ -#define SDRAM_DCR_BASE 0x10 -#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */ -#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */ - /* values for memcfga register - indirect addressing of these regs */ #define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */ #define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */ @@ -331,9 +320,6 @@ #define sdr_sdstp6 0x4005 #define sdr_sdstp7 0x4007 -#define SDR0_CFGADDR 0x00E -#define SDR0_CFGDATA 0x00F - /****************************************************************************** * PCI express defines ******************************************************************************/ @@ -480,10 +466,6 @@ /*----------------------------------------------------------------------------+ | Memory controller defines +----------------------------------------------------------------------------*/ -#define SDRAMC_DCR_BASE 0x010 -#define SDRAMC_CFGADDR (SDRAMC_DCR_BASE+0x0) /* Memory configuration add */ -#define SDRAMC_CFGDATA (SDRAMC_DCR_BASE+0x1) /* Memory configuration data */ - /* A REVOIR versus specs 4 bank - SG*/ #define SDRAM_MCSTAT 0x14 /* memory controller status */ #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ @@ -834,9 +816,6 @@ /*----------------------------------------------------------------------------- | External Bus Controller +----------------------------------------------------------------------------*/ -#define EBC_DCR_BASE 0x12 -#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */ -#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */ /* values for ebccfga register - indirect addressing of these regs */ #define pb0cr 0x00 /* periph bank 0 config reg */ #define pb1cr 0x01 /* periph bank 1 config reg */ @@ -2207,9 +2186,6 @@ #define SDR0_CP440_NTO1_NTO1 0x00000002 #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) -#define SDR0_CFGADDR 0x00E /*already defined line 277 */ -#define SDR0_CFGDATA 0x00F - #define SDR0_SDSTP0 0x0020 #define SDR0_SDSTP0_ENG_MASK 0x80000000 @@ -3289,71 +3265,8 @@ #define GPIO1_ISR3H (GPIO1_BASE+0x44) #endif -/* - * Macros for accessing the indirect EBC registers - */ -#define mtebc(reg, data) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,data); } while (0) -#define mfebc(reg, data) do { mtdcr(ebccfga,reg);data = mfdcr(ebccfgd); } while (0) - -/* - * Macros for accessing the indirect SDRAM controller registers - */ -#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0) -#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0) - -/* - * Macros for accessing the indirect clocking controller registers - */ -#define mtclk(reg, data) do { mtdcr(clkcfga,reg);mtdcr(clkcfgd,data); } while (0) -#define mfclk(reg, data) do { mtdcr(clkcfga,reg);data = mfdcr(clkcfgd); } while (0) - -/* - * Macros for accessing the sdr controller registers - */ -#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0) -#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0) - -/* - * All 44x except 440GP have CPR registers (indirect DCR) - */ -#if !defined(CONFIG_440GP) -#define CPR0_CFGADDR 0x00C -#define CPR0_CFGDATA 0x00D - -#define mtcpr(reg, data) do { \ - mtdcr(CPR0_CFGADDR, reg); \ - mtdcr(CPR0_CFGDATA, data); \ - } while (0) - -#define mfcpr(reg, data) do { \ - mtdcr(CPR0_CFGADDR, reg); \ - data = mfdcr(CPR0_CFGDATA); \ - } while (0) -#endif - #ifndef __ASSEMBLY__ -typedef struct { - unsigned long pllFwdDivA; - unsigned long pllFwdDivB; - unsigned long pllFbkDiv; - unsigned long pllOpbDiv; - unsigned long pllPciDiv; - unsigned long pllExtBusDiv; - unsigned long freqVCOMhz; /* in MHz */ - unsigned long freqProcessor; - unsigned long freqTmrClk; - unsigned long freqPLB; - unsigned long freqOPB; - unsigned long freqEBC; - unsigned long freqPCI; -#ifdef CONFIG_440SPE - unsigned long freqDDR; -#endif - unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ - unsigned long pciClkSync; /* PCI clock is synchronous */ -} PPC440_SYS_INFO; - static inline u32 get_mcsr(void) { u32 val; diff --git a/include/ppc4xx.h b/include/ppc4xx.h index ca241d2c13c..76fe8727f56 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -22,13 +22,80 @@ #ifndef __PPC4XX_H__ #define __PPC4XX_H__ -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ -#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) - #if defined(CONFIG_440) #include #else #include #endif +/* + * Common stuff for 4xx (405 and 440) + */ + +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) + +#define RESET_VECTOR 0xfffffffc +#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache + line aligned data. */ + +#define CPR0_DCR_BASE 0x0C +#define cprcfga (CPR0_DCR_BASE+0x0) +#define cprcfgd (CPR0_DCR_BASE+0x1) + +#define SDR_DCR_BASE 0x0E +#define sdrcfga (SDR_DCR_BASE+0x0) +#define sdrcfgd (SDR_DCR_BASE+0x1) + +#define SDRAM_DCR_BASE 0x10 +#define memcfga (SDRAM_DCR_BASE+0x0) +#define memcfgd (SDRAM_DCR_BASE+0x1) + +#define EBC_DCR_BASE 0x12 +#define ebccfga (EBC_DCR_BASE+0x0) +#define ebccfgd (EBC_DCR_BASE+0x1) + +/* + * Macros for indirect DCR access + */ +#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) +#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) + +#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) +#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) + +#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) +#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) + +#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) +#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) + +#ifndef __ASSEMBLY__ + +typedef struct +{ + unsigned long freqDDR; + unsigned long freqEBC; + unsigned long freqOPB; + unsigned long freqPCI; + unsigned long freqPLB; + unsigned long freqTmrClk; + unsigned long freqUART; + unsigned long freqProcessor; + unsigned long freqVCOHz; + unsigned long freqVCOMhz; /* in MHz */ + unsigned long pciClkSync; /* PCI clock is synchronous */ + unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ + unsigned long pllExtBusDiv; + unsigned long pllFbkDiv; + unsigned long pllFwdDiv; + unsigned long pllFwdDivA; + unsigned long pllFwdDivB; + unsigned long pllOpbDiv; + unsigned long pllPciDiv; + unsigned long pllPlbDiv; +} PPC4xx_SYS_INFO; + +#endif /* __ASSEMBLY__ */ + #endif /* __PPC4XX_H__ */ -- cgit v1.3.1 From fa8aea20456e6f1dba43f46bcc72024dd9499998 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 22 Oct 2007 07:33:52 +0200 Subject: ppc4xx: Add freqUART to CPU speed detection This value is needed later for the device tree configuration of the uart clock. Signed-off-by: Stefan Roese --- cpu/ppc4xx/fdt.c | 7 +++++++ cpu/ppc4xx/speed.c | 25 +++++++++++++++++-------- 2 files changed, 24 insertions(+), 8 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c index 2acb250e055..44e95a5a91a 100644 --- a/cpu/ppc4xx/fdt.c +++ b/cpu/ppc4xx/fdt.c @@ -79,10 +79,17 @@ static void do_fixup_uart(void *fdt, int offset, int i, bd_t *bd) { int rc; u32 val; + PPC4xx_SYS_INFO sys_info; + + get_sys_info(&sys_info); debug("Updating node UART%d\n", i); +#if defined(CFG_EXT_SERIAL_CLOCK) val = cpu_to_fdt32(CFG_EXT_SERIAL_CLOCK); +#else + val = cpu_to_fdt32(sys_info.freqUART); +#endif rc = fdt_setprop(fdt, offset, "clock-frequency", &val, 4); if (rc) printf("Unable to update node UART, err=%s\n", fdt_strerror(rc)); diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 26182dabf01..90066142de1 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -162,6 +162,8 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv; } } + + sysInfo->freqUART = sysInfo->freqProcessor; } @@ -265,6 +267,7 @@ void get_sys_info (sys_info_t *sysInfo) sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; sysInfo->freqEBC = sysInfo->freqPLB/sysInfo->pllExtBusDiv; sysInfo->freqPCI = sysInfo->freqPLB/sysInfo->pllPciDiv; + sysInfo->freqUART = sysInfo->freqPLB; /* Figure which timer source to use */ if (mfspr(ccr1) & 0x0080) { /* External Clock, assume same as SYS_CLK */ @@ -277,6 +280,7 @@ void get_sys_info (sys_info_t *sysInfo) else /* Internal clock */ sysInfo->freqTmrClk = sysInfo->freqProcessor; } + /******************************************** * get_PCI_freq * return PCI bus freq in Hz @@ -318,7 +322,7 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqPLB >>= 1; sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; sysInfo->freqEBC = sysInfo->freqOPB/sysInfo->pllExtBusDiv; - + sysInfo->freqUART = sysInfo->freqPLB; } #else void get_sys_info (sys_info_t * sysInfo) @@ -403,7 +407,7 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll)); #endif - + sysInfo->freqUART = sysInfo->freqPLB; } #endif @@ -632,7 +636,8 @@ extern void get_sys_info (sys_info_t * sysInfo); extern ulong get_PCI_freq (void); #elif defined(CONFIG_AP1000) -void get_sys_info (sys_info_t * sysInfo) { +void get_sys_info (sys_info_t * sysInfo) +{ sysInfo->freqProcessor = 240 * 1000 * 1000; sysInfo->freqPLB = 80 * 1000 * 1000; sysInfo->freqPCI = 33 * 1000 * 1000; @@ -640,13 +645,12 @@ void get_sys_info (sys_info_t * sysInfo) { #elif defined(CONFIG_405) -void get_sys_info (sys_info_t * sysInfo) { - +void get_sys_info (sys_info_t * sysInfo) +{ sysInfo->freqVCOMhz=3125000; sysInfo->freqProcessor=12*1000*1000; sysInfo->freqPLB=50*1000*1000; sysInfo->freqPCI=66*1000*1000; - } #elif defined(CONFIG_405EP) @@ -678,9 +682,8 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) * Determine FBK_DIV. */ sysInfo->pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20); - if (sysInfo->pllFbkDiv == 0) { + if (sysInfo->pllFbkDiv == 0) sysInfo->pllFbkDiv = 16; - } /* * Determine PLB_DIV. @@ -735,6 +738,8 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv; sysInfo->freqEBC = sysInfo->freqPLB / sysInfo->pllExtBusDiv; + + sysInfo->freqUART = sysInfo->freqProcessor * pllmr0_ccdv; } @@ -808,6 +813,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) * Read CPR_PRIMAD register */ mfcpr(cprprimad, cpr_primad); + /* * Determine PLB_DIV. */ @@ -861,6 +867,8 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) sysInfo->freqEBC = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / sysInfo->pllExtBusDiv; + + sysInfo->freqUART = sysInfo->freqVCOHz; } /******************************************** @@ -1022,6 +1030,7 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; sysInfo->freqDDR = sysInfo->freqPLB; sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv; + sysInfo->freqUART = sysInfo->freqPLB; } /******************************************** -- cgit v1.3.1 From 764e7417ee5f6e25b1715720e7d7dd3487109385 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 22 Oct 2007 10:30:38 +0200 Subject: ppc4xx: Correct UART input clock calculation and passing to fdt Signed-off-by: Stefan Roese --- cpu/ppc4xx/fdt.c | 4 ---- cpu/ppc4xx/serial.c | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c index 44e95a5a91a..bf97c2a4356 100644 --- a/cpu/ppc4xx/fdt.c +++ b/cpu/ppc4xx/fdt.c @@ -85,11 +85,7 @@ static void do_fixup_uart(void *fdt, int offset, int i, bd_t *bd) debug("Updating node UART%d\n", i); -#if defined(CFG_EXT_SERIAL_CLOCK) - val = cpu_to_fdt32(CFG_EXT_SERIAL_CLOCK); -#else val = cpu_to_fdt32(sys_info.freqUART); -#endif rc = fdt_setprop(fdt, offset, "clock-frequency", &val, 4); if (rc) printf("Unable to update node UART, err=%s\n", fdt_strerror(rc)); diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index 8b1e2ffa0b4..0fdef7e64f4 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -528,12 +528,18 @@ int serial_init(void) udiv = 1; tmp = gd->baudrate * 16; bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp; + gd->freqUART = CFG_EXT_SERIAL_CLOCK; #else /* For 440, the cpu clock is on divider chain A, UART on divider * chain B ... so cpu clock is irrelevant. Get the "optimized" * values that are subject to the 1/2 opb clock constraint */ serial_divs (gd->baudrate, &udiv, &bdiv); + + /* Correct UART frequency in bd-info struct now that + * the UART divisor is available + */ + gd->freqUART = gd->freqUART / udiv; #endif reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ @@ -644,6 +650,15 @@ int serial_init (void) bdiv = (clk + tmp / 2) / tmp; #endif /* CONFIG_405EX */ + /* Correct UART frequency in bd-info struct now that + * the UART divisor is available + */ +#ifdef CFG_EXT_SERIAL_CLOCK + gd->freqUART = CFG_EXT_SERIAL_CLOCK; +#else + gd->freqUART = gd->freqUART / udiv; +#endif + out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */ out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */ out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */ -- cgit v1.3.1 From ad31e40bed042cb670d0036fea96435007afb838 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 22 Oct 2007 15:09:59 +0200 Subject: ppc4xx: Rework of 4xx serial driver (1) This patch starts the rework of the PPC4xx serial driver. First we split the file into two seperate files, one 4xx_uart.c with the 405/440 UART handling code and the other one iop480_uart.c with the UART code for the PLX-Tech IOP480 PPC (PPC403 based). Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_uart.c | 888 +++++++++++++++++++++++++++++++++++++ cpu/ppc4xx/Makefile | 10 +- cpu/ppc4xx/iop480_uart.c | 238 ++++++++++ cpu/ppc4xx/serial.c | 1091 ---------------------------------------------- 4 files changed, 1131 insertions(+), 1096 deletions(-) create mode 100644 cpu/ppc4xx/4xx_uart.c create mode 100644 cpu/ppc4xx/iop480_uart.c delete mode 100644 cpu/ppc4xx/serial.c (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c new file mode 100644 index 00000000000..8560456e52d --- /dev/null +++ b/cpu/ppc4xx/4xx_uart.c @@ -0,0 +1,888 @@ +/* + * (C) Copyright 2000-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/*------------------------------------------------------------------------------+ */ +/* + * This source code has been made available to you by IBM on an AS-IS + * basis. Anyone receiving this source is licensed under IBM + * copyrights to use it in any way he or she deems fit, including + * copying it, modifying it, compiling it, and redistributing it either + * with or without modifications. No license under IBM patents or + * patent applications is to be implied by the copyright license. + * + * Any user of this software should understand that IBM cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work + * must include the IBM copyright notice, this paragraph, and the + * preceding two paragraphs in the transferred software. + * + * COPYRIGHT I B M CORPORATION 1995 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + */ +/*------------------------------------------------------------------------------- */ +/* + * Travis Sawyer 15 September 2004 + * Added CONFIG_SERIAL_MULTI support + */ +#include +#include +#include +#include +#include "vecnum.h" + +#ifdef CONFIG_SERIAL_MULTI +#include +#endif + +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ + defined(CONFIG_405EX) || defined(CONFIG_440) + +#if defined(CONFIG_440) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300 +#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400 +#else +#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200 +#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300 +#endif + +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600 +#endif + +#if defined(CONFIG_440GP) +#define CR0_MASK 0x3fff0000 +#define CR0_EXTCLK_ENA 0x00600000 +#define CR0_UDIV_POS 16 +#define UDIV_SUBTRACT 1 +#define UART0_SDR cntrl0 +#define MFREG(a, d) d = mfdcr(a) +#define MTREG(a, d) mtdcr(a, d) +#else /* #if defined(CONFIG_440GP) */ +/* all other 440 PPC's access clock divider via sdr register */ +#define CR0_MASK 0xdfffffff +#define CR0_EXTCLK_ENA 0x00800000 +#define CR0_UDIV_POS 0 +#define UDIV_SUBTRACT 0 +#define UART0_SDR sdr_uart0 +#define UART1_SDR sdr_uart1 +#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPe) +#define UART2_SDR sdr_uart2 +#endif +#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRx) +#define UART3_SDR sdr_uart3 +#endif +#define MFREG(a, d) mfsdr(a, d) +#define MTREG(a, d) mtsdr(a, d) +#endif /* #if defined(CONFIG_440GP) */ +#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ) +#define UART0_BASE 0xef600300 +#define UART1_BASE 0xef600400 +#define UCR0_MASK 0x0000007f +#define UCR1_MASK 0x00007f00 +#define UCR0_UDIV_POS 0 +#define UCR1_UDIV_POS 8 +#define UDIV_MAX 127 +#elif defined(CONFIG_405EX) +#define UART0_BASE 0xef600200 +#define UART1_BASE 0xef600300 +#define CR0_MASK 0x000000ff +#define CR0_EXTCLK_ENA 0x00800000 +#define CR0_UDIV_POS 0 +#define UDIV_SUBTRACT 0 +#define UART0_SDR sdr_uart0 +#define UART1_SDR sdr_uart1 +#else /* CONFIG_405GP || CONFIG_405CR */ +#define UART0_BASE 0xef600300 +#define UART1_BASE 0xef600400 +#define CR0_MASK 0x00001fff +#define CR0_EXTCLK_ENA 0x000000c0 +#define CR0_UDIV_POS 1 +#define UDIV_MAX 32 +#endif + +/* using serial port 0 or 1 as U-Boot console ? */ +#if defined(CONFIG_UART1_CONSOLE) +#define ACTING_UART0_BASE UART1_BASE +#define ACTING_UART1_BASE UART0_BASE +#else +#define ACTING_UART0_BASE UART0_BASE +#define ACTING_UART1_BASE UART1_BASE +#endif + +#if defined(CONFIG_SERIAL_MULTI) +#define UART_BASE dev_base +#else +#define UART_BASE ACTING_UART0_BASE +#endif + +#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK) +#error "External serial clock not supported on AMCC PPC405EP!" +#endif + +#define UART_RBR 0x00 +#define UART_THR 0x00 +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/*-----------------------------------------------------------------------------+ + | Line Status Register. + +-----------------------------------------------------------------------------*/ +/*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */ +#define asyncLSRDataReady1 0x01 +#define asyncLSROverrunError1 0x02 +#define asyncLSRParityError1 0x04 +#define asyncLSRFramingError1 0x08 +#define asyncLSRBreakInterrupt1 0x10 +#define asyncLSRTxHoldEmpty1 0x20 +#define asyncLSRTxShiftEmpty1 0x40 +#define asyncLSRRxFifoError1 0x80 + +/*-----------------------------------------------------------------------------+ + | Miscellanies defines. + +-----------------------------------------------------------------------------*/ +/*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */ +/*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */ + +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO +/*-----------------------------------------------------------------------------+ + | Fifo + +-----------------------------------------------------------------------------*/ +typedef struct { + char *rx_buffer; + ulong rx_put; + ulong rx_get; +} serial_buffer_t; + +volatile static serial_buffer_t buf_info; +#endif + +#if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \ + !defined(CFG_EXT_SERIAL_CLOCK) +static void serial_divs (int baudrate, unsigned long *pudiv, + unsigned short *pbdiv) +{ + sys_info_t sysinfo; + unsigned long div; /* total divisor udiv * bdiv */ + unsigned long umin; /* minimum udiv */ + unsigned short diff; /* smallest diff */ + unsigned long udiv; /* best udiv */ + unsigned short idiff; /* current diff */ + unsigned short ibdiv; /* current bdiv */ + unsigned long i; + unsigned long est; /* current estimate */ + + get_sys_info(&sysinfo); + + udiv = 32; /* Assume lowest possible serial clk */ + div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */ + umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */ + diff = 32; /* highest possible */ + + /* i is the test udiv value -- start with the largest + * possible (32) to minimize serial clock and constrain + * search to umin. + */ + for (i = 32; i > umin; i--) { + ibdiv = div / i; + est = i * ibdiv; + idiff = (est > div) ? (est-div) : (div-est); + if (idiff == 0) { + udiv = i; + break; /* can't do better */ + } else if (idiff < diff) { + udiv = i; /* best so far */ + diff = idiff; /* update lowest diff*/ + } + } + + *pudiv = udiv; + *pbdiv = div / udiv; +} + +#elif defined(CONFIG_405EZ) + +static void serial_divs (int baudrate, unsigned long *pudiv, + unsigned short *pbdiv) +{ + sys_info_t sysinfo; + unsigned long div; /* total divisor udiv * bdiv */ + unsigned long umin; /* minimum udiv */ + unsigned short diff; /* smallest diff */ + unsigned long udiv; /* best udiv */ + unsigned short idiff; /* current diff */ + unsigned short ibdiv; /* current bdiv */ + unsigned long i; + unsigned long est; /* current estimate */ + unsigned long plloutb; + unsigned long cpr_pllc; + u32 reg; + + /* check the pll feedback source */ + mfcpr(cprpllc, cpr_pllc); + + get_sys_info(&sysinfo); + + plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ? + sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * sysinfo.pllFbkDiv) / + sysinfo.pllFwdDivB); + udiv = 256; /* Assume lowest possible serial clk */ + div = plloutb / (16 * baudrate); /* total divisor */ + umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */ + diff = 256; /* highest possible */ + + /* i is the test udiv value -- start with the largest + * possible (256) to minimize serial clock and constrain + * search to umin. + */ + for (i = 256; i > umin; i--) { + ibdiv = div / i; + est = i * ibdiv; + idiff = (est > div) ? (est-div) : (div-est); + if (idiff == 0) { + udiv = i; + break; /* can't do better */ + } else if (idiff < diff) { + udiv = i; /* best so far */ + diff = idiff; /* update lowest diff*/ + } + } + + *pudiv = udiv; + mfcpr(cprperd0, reg); + reg &= ~0x0000ffff; + reg |= ((udiv - 0) << 8) | (udiv - 0); + mtcpr(cprperd0, reg); + *pbdiv = div / udiv; +} +#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */ + +/* + * Minimal serial functions needed to use one of the SMC ports + * as serial console interface. + */ + +#if defined(CONFIG_440) +#if defined(CONFIG_SERIAL_MULTI) +int serial_init_dev (unsigned long dev_base) +#else +int serial_init(void) +#endif +{ + unsigned long reg; + unsigned long udiv; + unsigned short bdiv; + volatile char val; +#ifdef CFG_EXT_SERIAL_CLOCK + unsigned long tmp; +#endif + + MFREG(UART0_SDR, reg); + reg &= ~CR0_MASK; + +#ifdef CFG_EXT_SERIAL_CLOCK + reg |= CR0_EXTCLK_ENA; + udiv = 1; + tmp = gd->baudrate * 16; + bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp; + gd->freqUART = CFG_EXT_SERIAL_CLOCK; +#else + /* For 440, the cpu clock is on divider chain A, UART on divider + * chain B ... so cpu clock is irrelevant. Get the "optimized" + * values that are subject to the 1/2 opb clock constraint + */ + serial_divs (gd->baudrate, &udiv, &bdiv); + + /* Correct UART frequency in bd-info struct now that + * the UART divisor is available + */ + gd->freqUART = gd->freqUART / udiv; +#endif + + reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ + + /* + * Configure input clock to baudrate generator for all + * available serial ports here + */ + MTREG(UART0_SDR, reg); +#if defined(UART1_SDR) + MTREG(UART1_SDR, reg); +#endif +#if defined(UART2_SDR) + MTREG(UART2_SDR, reg); +#endif +#if defined(UART3_SDR) + MTREG(UART3_SDR, reg); +#endif + + out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */ + out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */ + out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */ + out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8(UART_BASE + UART_LSR); /* clear line status */ + val = in8(UART_BASE + UART_RBR); /* read receive buffer */ + out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */ + out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */ + + return (0); +} + +#else /* !defined(CONFIG_440) */ + +#if defined(CONFIG_SERIAL_MULTI) +int serial_init_dev (unsigned long dev_base) +#else +int serial_init (void) +#endif +{ + unsigned long reg; + unsigned long tmp; + unsigned long clk; + unsigned long udiv; + unsigned short bdiv; + volatile char val; + +#ifdef CONFIG_405EX + clk = tmp = 0; + mfsdr(UART0_SDR, reg); + reg &= ~CR0_MASK; +#ifdef CFG_EXT_SERIAL_CLOCK + reg |= CR0_EXTCLK_ENA; + udiv = 1; + tmp = gd->baudrate * 16; + bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp; +#else + serial_divs(gd->baudrate, &udiv, &bdiv); +#endif + reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ + + /* + * Configure input clock to baudrate generator for all + * available serial ports here + */ + mtsdr(UART0_SDR, reg); + +#if defined(UART1_SDR) + mtsdr(UART1_SDR, reg); +#endif + +#elif defined(CONFIG_405EZ) + serial_divs(gd->baudrate, &udiv, &bdiv); + clk = tmp = reg = 0; +#else +#ifdef CONFIG_405EP + reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK); + clk = gd->cpu_clk; + tmp = CFG_BASE_BAUD * 16; + udiv = (clk + tmp / 2) / tmp; + if (udiv > UDIV_MAX) /* max. n bits for udiv */ + udiv = UDIV_MAX; + reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */ + reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */ + mtdcr (cpc0_ucr, reg); +#else /* CONFIG_405EP */ + reg = mfdcr(cntrl0) & ~CR0_MASK; +#ifdef CFG_EXT_SERIAL_CLOCK + clk = CFG_EXT_SERIAL_CLOCK; + udiv = 1; + reg |= CR0_EXTCLK_ENA; +#else + clk = gd->cpu_clk; +#ifdef CFG_405_UART_ERRATA_59 + udiv = 31; /* Errata 59: stuck at 31 */ +#else + tmp = CFG_BASE_BAUD * 16; + udiv = (clk + tmp / 2) / tmp; + if (udiv > UDIV_MAX) /* max. n bits for udiv */ + udiv = UDIV_MAX; +#endif +#endif + reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ + mtdcr (cntrl0, reg); +#endif /* CONFIG_405EP */ + tmp = gd->baudrate * udiv * 16; + bdiv = (clk + tmp / 2) / tmp; +#endif /* CONFIG_405EX */ + + /* Correct UART frequency in bd-info struct now that + * the UART divisor is available + */ +#ifdef CFG_EXT_SERIAL_CLOCK + gd->freqUART = CFG_EXT_SERIAL_CLOCK; +#else + gd->freqUART = gd->freqUART / udiv; +#endif + + out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */ + out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */ + out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */ + out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8(UART_BASE + UART_LSR); /* clear line status */ + val = in8(UART_BASE + UART_RBR); /* read receive buffer */ + out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */ + out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */ + + return (0); +} + +#endif /* if defined(CONFIG_440) */ + +#if defined(CONFIG_SERIAL_MULTI) +void serial_setbrg_dev (unsigned long dev_base) +#else +void serial_setbrg (void) +#endif +{ +#if defined(CONFIG_SERIAL_MULTI) + serial_init_dev(dev_base); +#else + serial_init(); +#endif +} + +#if defined(CONFIG_SERIAL_MULTI) +void serial_putc_dev (unsigned long dev_base, const char c) +#else +void serial_putc (const char c) +#endif +{ + int i; + + if (c == '\n') +#if defined(CONFIG_SERIAL_MULTI) + serial_putc_dev (dev_base, '\r'); +#else + serial_putc ('\r'); +#endif + + /* check THRE bit, wait for transmiter available */ + for (i = 1; i < 3500; i++) { + if ((in8 (UART_BASE + UART_LSR) & 0x20) == 0x20) + break; + udelay (100); + } + out8 (UART_BASE + UART_THR, c); /* put character out */ +} + +#if defined(CONFIG_SERIAL_MULTI) +void serial_puts_dev (unsigned long dev_base, const char *s) +#else +void serial_puts (const char *s) +#endif +{ + while (*s) { +#if defined(CONFIG_SERIAL_MULTI) + serial_putc_dev (dev_base, *s++); +#else + serial_putc (*s++); +#endif + } +} + +#if defined(CONFIG_SERIAL_MULTI) +int serial_getc_dev (unsigned long dev_base) +#else +int serial_getc (void) +#endif +{ + unsigned char status = 0; + + while (1) { +#if defined(CONFIG_HW_WATCHDOG) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ +#endif /* CONFIG_HW_WATCHDOG */ + status = in8 (UART_BASE + UART_LSR); + if ((status & asyncLSRDataReady1) != 0x0) { + break; + } + if ((status & ( asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1 )) != 0) { + out8 (UART_BASE + UART_LSR, + asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1); + } + } + return (0x000000ff & (int) in8 (UART_BASE)); +} + +#if defined(CONFIG_SERIAL_MULTI) +int serial_tstc_dev (unsigned long dev_base) +#else +int serial_tstc (void) +#endif +{ + unsigned char status; + + status = in8 (UART_BASE + UART_LSR); + if ((status & asyncLSRDataReady1) != 0x0) { + return (1); + } + if ((status & ( asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1 )) != 0) { + out8 (UART_BASE + UART_LSR, + asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1); + } + return 0; +} + +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO + +void serial_isr (void *arg) +{ + int space; + int c; + const int rx_get = buf_info.rx_get; + int rx_put = buf_info.rx_put; + + if (rx_get <= rx_put) { + space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); + } else { + space = rx_get - rx_put; + } + while (serial_tstc_dev (ACTING_UART0_BASE)) { + c = serial_getc_dev (ACTING_UART0_BASE); + if (space) { + buf_info.rx_buffer[rx_put++] = c; + space--; + } + if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) + rx_put = 0; + if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) { + /* Stop flow by setting RTS inactive */ + out8 (ACTING_UART0_BASE + UART_MCR, + in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02)); + } + } + buf_info.rx_put = rx_put; +} + +void serial_buffered_init (void) +{ + serial_puts ("Switching to interrupt driven serial input mode.\n"); + buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO); + buf_info.rx_put = 0; + buf_info.rx_get = 0; + + if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) { + serial_puts ("Check CTS signal present on serial port: OK.\n"); + } else { + serial_puts ("WARNING: CTS signal not present on serial port.\n"); + } + + irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ , + serial_isr /*interrupt_handler_t *handler */ , + (void *) &buf_info /*void *arg */ ); + + /* Enable "RX Data Available" Interrupt on UART */ + /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */ + out8 (ACTING_UART0_BASE + UART_IER, 0x01); + /* Set DTR active */ + out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01); + /* Start flow by setting RTS active */ + out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02); + /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */ + out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1); +} + +void serial_buffered_putc (const char c) +{ + /* Wait for CTS */ +#if defined(CONFIG_HW_WATCHDOG) + while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)) + WATCHDOG_RESET (); +#else + while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)); +#endif + serial_putc (c); +} + +void serial_buffered_puts (const char *s) +{ + serial_puts (s); +} + +int serial_buffered_getc (void) +{ + int space; + int c; + int rx_get = buf_info.rx_get; + int rx_put; + +#if defined(CONFIG_HW_WATCHDOG) + while (rx_get == buf_info.rx_put) + WATCHDOG_RESET (); +#else + while (rx_get == buf_info.rx_put); +#endif + c = buf_info.rx_buffer[rx_get++]; + if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO) + rx_get = 0; + buf_info.rx_get = rx_get; + + rx_put = buf_info.rx_put; + if (rx_get <= rx_put) { + space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); + } else { + space = rx_get - rx_put; + } + if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) { + /* Start flow by setting RTS active */ + out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02); + } + + return c; +} + +int serial_buffered_tstc (void) +{ + return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0; +} + +#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ + +#if defined(CONFIG_CMD_KGDB) +/* + AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port + number 0 or number 1 + - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 : + configuration has been already done + - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 : + configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE +*/ +#if (CONFIG_KGDB_SER_INDEX & 2) +void kgdb_serial_init (void) +{ + volatile char val; + unsigned short br_reg; + + get_clocks (); + br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) + + 5) / 10; + /* + * Init onboard 16550 UART + */ + out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */ + out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */ + out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */ + out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */ + out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */ + val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */ + out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */ + out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */ +} + +void putDebugChar (const char c) +{ + if (c == '\n') + serial_putc ('\r'); + + out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */ + + /* check THRE bit, wait for transfer done */ + while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20); +} + +void putDebugStr (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int getDebugChar (void) +{ + unsigned char status = 0; + + while (1) { + status = in8 (ACTING_UART1_BASE + UART_LSR); + if ((status & asyncLSRDataReady1) != 0x0) { + break; + } + if ((status & ( asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1 )) != 0) { + out8 (ACTING_UART1_BASE + UART_LSR, + asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1); + } + } + return (0x000000ff & (int) in8 (ACTING_UART1_BASE)); +} + +void kgdb_interruptible (int yes) +{ + return; +} + +#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */ + +void kgdb_serial_init (void) +{ + serial_printf ("[on serial] "); +} + +void putDebugChar (int c) +{ + serial_putc (c); +} + +void putDebugStr (const char *str) +{ + serial_puts (str); +} + +int getDebugChar (void) +{ + return serial_getc (); +} + +void kgdb_interruptible (int yes) +{ + return; +} +#endif /* (CONFIG_KGDB_SER_INDEX & 2) */ +#endif + + +#if defined(CONFIG_SERIAL_MULTI) +int serial0_init(void) +{ + return (serial_init_dev(UART0_BASE)); +} + +int serial1_init(void) +{ + return (serial_init_dev(UART1_BASE)); +} +void serial0_setbrg (void) +{ + serial_setbrg_dev(UART0_BASE); +} +void serial1_setbrg (void) +{ + serial_setbrg_dev(UART1_BASE); +} + +void serial0_putc(const char c) +{ + serial_putc_dev(UART0_BASE,c); +} + +void serial1_putc(const char c) +{ + serial_putc_dev(UART1_BASE, c); +} +void serial0_puts(const char *s) +{ + serial_puts_dev(UART0_BASE, s); +} + +void serial1_puts(const char *s) +{ + serial_puts_dev(UART1_BASE, s); +} + +int serial0_getc(void) +{ + return(serial_getc_dev(UART0_BASE)); +} + +int serial1_getc(void) +{ + return(serial_getc_dev(UART1_BASE)); +} +int serial0_tstc(void) +{ + return (serial_tstc_dev(UART0_BASE)); +} + +int serial1_tstc(void) +{ + return (serial_tstc_dev(UART1_BASE)); +} + +struct serial_device serial0_device = +{ + "serial0", + "UART0", + serial0_init, + serial0_setbrg, + serial0_getc, + serial0_tstc, + serial0_putc, + serial0_puts, +}; + +struct serial_device serial1_device = +{ + "serial1", + "UART1", + serial1_init, + serial1_setbrg, + serial1_getc, + serial1_tstc, + serial1_putc, + serial1_puts, +}; +#endif /* CONFIG_SERIAL_MULTI */ + +#endif /* CONFIG_405GP || CONFIG_405CR */ diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index bc65aa0571d..194724990de 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -28,11 +28,11 @@ LIB = $(obj)lib$(CPU).a START = start.o resetvec.o kgdb.o SOBJS = dcr.o COBJS = 40x_spd_sdram.o 44x_spd_ddr.o 44x_spd_ddr2.o \ - 4xx_pci.o 4xx_pcie.o 4xx_enet.o \ - bedbug_405.o commproc.o \ - cpu.o cpu_init.o fdt.o gpio.o i2c.o interrupts.o \ - miiphy.o ndfc.o sdram.o serial.o speed.o \ - tlb.o traps.o usb_ohci.o usb.o usbdev.o + 4xx_enet.o 4xx_pci.o 4xx_pcie.o 4xx_uart.o \ + bedbug_405.o commproc.o cpu.o cpu_init.o \ + fdt.o gpio.o i2c.o interrupts.o iop480_uart.o \ + miiphy.o ndfc.o sdram.o speed.o \ + tlb.o traps.o usb.o usb_ohci.o usbdev.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/ppc4xx/iop480_uart.c b/cpu/ppc4xx/iop480_uart.c new file mode 100644 index 00000000000..8dd226729e2 --- /dev/null +++ b/cpu/ppc4xx/iop480_uart.c @@ -0,0 +1,238 @@ +/* + * (C) Copyright 2000-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include "vecnum.h" + +#ifdef CONFIG_SERIAL_MULTI +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_IOP480 + +#define SPU_BASE 0x40000000 + +#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */ +#define spu_LineStat_w 0x04 /* Line Status Register (Set) */ +#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */ +#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */ +#define spu_BRateDivh 0x10 /* Baud rate divisor high */ +#define spu_BRateDivl 0x14 /* Baud rate divisor low */ +#define spu_CtlReg 0x18 /* Control Register */ +#define spu_RxCmd 0x1c /* Rx Command Register */ +#define spu_TxCmd 0x20 /* Tx Command Register */ +#define spu_RxBuff 0x24 /* Rx data buffer */ +#define spu_TxBuff 0x24 /* Tx data buffer */ + +/*-----------------------------------------------------------------------------+ + | Line Status Register. + +-----------------------------------------------------------------------------*/ +#define asyncLSRport1 0x40000000 +#define asyncLSRport1set 0x40000004 +#define asyncLSRDataReady 0x80 +#define asyncLSRFramingError 0x40 +#define asyncLSROverrunError 0x20 +#define asyncLSRParityError 0x10 +#define asyncLSRBreakInterrupt 0x08 +#define asyncLSRTxHoldEmpty 0x04 +#define asyncLSRTxShiftEmpty 0x02 + +/*-----------------------------------------------------------------------------+ + | Handshake Status Register. + +-----------------------------------------------------------------------------*/ +#define asyncHSRport1 0x40000008 +#define asyncHSRport1set 0x4000000c +#define asyncHSRDsr 0x80 +#define asyncLSRCts 0x40 + +/*-----------------------------------------------------------------------------+ + | Control Register. + +-----------------------------------------------------------------------------*/ +#define asyncCRport1 0x40000018 +#define asyncCRNormal 0x00 +#define asyncCRLoopback 0x40 +#define asyncCRAutoEcho 0x80 +#define asyncCRDtr 0x20 +#define asyncCRRts 0x10 +#define asyncCRWordLength7 0x00 +#define asyncCRWordLength8 0x08 +#define asyncCRParityDisable 0x00 +#define asyncCRParityEnable 0x04 +#define asyncCREvenParity 0x00 +#define asyncCROddParity 0x02 +#define asyncCRStopBitsOne 0x00 +#define asyncCRStopBitsTwo 0x01 +#define asyncCRDisableDtrRts 0x00 + +/*-----------------------------------------------------------------------------+ + | Receiver Command Register. + +-----------------------------------------------------------------------------*/ +#define asyncRCRport1 0x4000001c +#define asyncRCRDisable 0x00 +#define asyncRCREnable 0x80 +#define asyncRCRIntDisable 0x00 +#define asyncRCRIntEnabled 0x20 +#define asyncRCRDMACh2 0x40 +#define asyncRCRDMACh3 0x60 +#define asyncRCRErrorInt 0x10 +#define asyncRCRPauseEnable 0x08 + +/*-----------------------------------------------------------------------------+ + | Transmitter Command Register. + +-----------------------------------------------------------------------------*/ +#define asyncTCRport1 0x40000020 +#define asyncTCRDisable 0x00 +#define asyncTCREnable 0x80 +#define asyncTCRIntDisable 0x00 +#define asyncTCRIntEnabled 0x20 +#define asyncTCRDMACh2 0x40 +#define asyncTCRDMACh3 0x60 +#define asyncTCRTxEmpty 0x10 +#define asyncTCRErrorInt 0x08 +#define asyncTCRStopPause 0x04 +#define asyncTCRBreakGen 0x02 + +/*-----------------------------------------------------------------------------+ + | Miscellanies defines. + +-----------------------------------------------------------------------------*/ +#define asyncTxBufferport1 0x40000024 +#define asyncRxBufferport1 0x40000024 +#define asyncDLABLsbport1 0x40000014 +#define asyncDLABMsbport1 0x40000010 +#define asyncXOFFchar 0x13 +#define asyncXONchar 0x11 + +/* + * Minimal serial functions needed to use one of the SMC ports + * as serial console interface. + */ + +int serial_init (void) +{ + volatile char val; + unsigned short br_reg; + + br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); + + /* + * Init onboard UART + */ + out_8((u8 *)SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */ + out_8((u8 *)SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */ + out_8((u8 *)SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */ + out_8((u8 *)SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */ + out_8((u8 *)SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */ + out_8((u8 *)SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */ + out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ + val = in_8((u8 *)SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */ + + return (0); +} + +void serial_setbrg (void) +{ + unsigned short br_reg; + + br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); + + out_8((u8 *)SPU_BASE + spu_BRateDivl, + (br_reg & 0x00ff)); /* Set baud rate divisor... */ + out_8((u8 *)SPU_BASE + spu_BRateDivh, + ((br_reg & 0xff00) >> 8)); /* ... */ +} + +void serial_putc (const char c) +{ + if (c == '\n') + serial_putc ('\r'); + + /* load status from handshake register */ + if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00) + out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ + + out_8((u8 *)SPU_BASE + spu_TxBuff, c); /* Put char */ + + while ((in_8((u8 *)SPU_BASE + spu_LineStat_rc) & 04) != 04) { + if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00) + out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ + } +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int serial_getc () +{ + unsigned char status = 0; + + while (1) { + status = in_8((u8 *)asyncLSRport1); + if ((status & asyncLSRDataReady) != 0x0) { + break; + } + if ((status & ( asyncLSRFramingError | + asyncLSROverrunError | + asyncLSRParityError | + asyncLSRBreakInterrupt )) != 0) { + (void) out_8((u8 *)asyncLSRport1, + asyncLSRFramingError | + asyncLSROverrunError | + asyncLSRParityError | + asyncLSRBreakInterrupt ); + } + } + return (0x000000ff & (int) in_8((u8 *)asyncRxBufferport1)); +} + +int serial_tstc () +{ + unsigned char status; + + status = in_8((u8 *)asyncLSRport1); + if ((status & asyncLSRDataReady) != 0x0) { + return (1); + } + if ((status & ( asyncLSRFramingError | + asyncLSROverrunError | + asyncLSRParityError | + asyncLSRBreakInterrupt )) != 0) { + (void) out_8((u8 *)asyncLSRport1, + asyncLSRFramingError | + asyncLSROverrunError | + asyncLSRParityError | + asyncLSRBreakInterrupt); + } + return 0; +} + +#endif /* CONFIG_IOP480 */ diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c deleted file mode 100644 index 0fdef7e64f4..00000000000 --- a/cpu/ppc4xx/serial.c +++ /dev/null @@ -1,1091 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/*------------------------------------------------------------------------------+ */ -/* - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - */ -/*------------------------------------------------------------------------------- */ -/* - * Travis Sawyer 15 September 2004 - * Added CONFIG_SERIAL_MULTI support - */ -#include -#include -#include -#include -#include "vecnum.h" - -#ifdef CONFIG_SERIAL_MULTI -#include -#endif - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/*****************************************************************************/ -#ifdef CONFIG_IOP480 - -#define SPU_BASE 0x40000000 - -#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */ -#define spu_LineStat_w 0x04 /* Line Status Register (Set) */ -#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */ -#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */ -#define spu_BRateDivh 0x10 /* Baud rate divisor high */ -#define spu_BRateDivl 0x14 /* Baud rate divisor low */ -#define spu_CtlReg 0x18 /* Control Register */ -#define spu_RxCmd 0x1c /* Rx Command Register */ -#define spu_TxCmd 0x20 /* Tx Command Register */ -#define spu_RxBuff 0x24 /* Rx data buffer */ -#define spu_TxBuff 0x24 /* Tx data buffer */ - -/*-----------------------------------------------------------------------------+ - | Line Status Register. - +-----------------------------------------------------------------------------*/ -#define asyncLSRport1 0x40000000 -#define asyncLSRport1set 0x40000004 -#define asyncLSRDataReady 0x80 -#define asyncLSRFramingError 0x40 -#define asyncLSROverrunError 0x20 -#define asyncLSRParityError 0x10 -#define asyncLSRBreakInterrupt 0x08 -#define asyncLSRTxHoldEmpty 0x04 -#define asyncLSRTxShiftEmpty 0x02 - -/*-----------------------------------------------------------------------------+ - | Handshake Status Register. - +-----------------------------------------------------------------------------*/ -#define asyncHSRport1 0x40000008 -#define asyncHSRport1set 0x4000000c -#define asyncHSRDsr 0x80 -#define asyncLSRCts 0x40 - -/*-----------------------------------------------------------------------------+ - | Control Register. - +-----------------------------------------------------------------------------*/ -#define asyncCRport1 0x40000018 -#define asyncCRNormal 0x00 -#define asyncCRLoopback 0x40 -#define asyncCRAutoEcho 0x80 -#define asyncCRDtr 0x20 -#define asyncCRRts 0x10 -#define asyncCRWordLength7 0x00 -#define asyncCRWordLength8 0x08 -#define asyncCRParityDisable 0x00 -#define asyncCRParityEnable 0x04 -#define asyncCREvenParity 0x00 -#define asyncCROddParity 0x02 -#define asyncCRStopBitsOne 0x00 -#define asyncCRStopBitsTwo 0x01 -#define asyncCRDisableDtrRts 0x00 - -/*-----------------------------------------------------------------------------+ - | Receiver Command Register. - +-----------------------------------------------------------------------------*/ -#define asyncRCRport1 0x4000001c -#define asyncRCRDisable 0x00 -#define asyncRCREnable 0x80 -#define asyncRCRIntDisable 0x00 -#define asyncRCRIntEnabled 0x20 -#define asyncRCRDMACh2 0x40 -#define asyncRCRDMACh3 0x60 -#define asyncRCRErrorInt 0x10 -#define asyncRCRPauseEnable 0x08 - -/*-----------------------------------------------------------------------------+ - | Transmitter Command Register. - +-----------------------------------------------------------------------------*/ -#define asyncTCRport1 0x40000020 -#define asyncTCRDisable 0x00 -#define asyncTCREnable 0x80 -#define asyncTCRIntDisable 0x00 -#define asyncTCRIntEnabled 0x20 -#define asyncTCRDMACh2 0x40 -#define asyncTCRDMACh3 0x60 -#define asyncTCRTxEmpty 0x10 -#define asyncTCRErrorInt 0x08 -#define asyncTCRStopPause 0x04 -#define asyncTCRBreakGen 0x02 - -/*-----------------------------------------------------------------------------+ - | Miscellanies defines. - +-----------------------------------------------------------------------------*/ -#define asyncTxBufferport1 0x40000024 -#define asyncRxBufferport1 0x40000024 -#define asyncDLABLsbport1 0x40000014 -#define asyncDLABMsbport1 0x40000010 -#define asyncXOFFchar 0x13 -#define asyncXONchar 0x11 - -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -int serial_init (void) -{ - volatile char val; - unsigned short br_reg; - - br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); - - /* - * Init onboard UART - */ - out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */ - out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */ - out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */ - out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */ - out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */ - out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */ - out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ - val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */ - - return (0); -} - -void serial_setbrg (void) -{ - unsigned short br_reg; - - br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); - - out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */ - out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */ -} - -void serial_putc (const char c) -{ - if (c == '\n') - serial_putc ('\r'); - - /* load status from handshake register */ - if (in8 (SPU_BASE + spu_Handshk_rc) != 00) - out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ - - out8 (SPU_BASE + spu_TxBuff, c); /* Put char */ - - while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) { - if (in8 (SPU_BASE + spu_Handshk_rc) != 00) - out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ - } -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int serial_getc () -{ - unsigned char status = 0; - - while (1) { - status = in8 (asyncLSRport1); - if ((status & asyncLSRDataReady) != 0x0) { - break; - } - if ((status & ( asyncLSRFramingError | - asyncLSROverrunError | - asyncLSRParityError | - asyncLSRBreakInterrupt )) != 0) { - (void) out8 (asyncLSRport1, - asyncLSRFramingError | - asyncLSROverrunError | - asyncLSRParityError | - asyncLSRBreakInterrupt ); - } - } - return (0x000000ff & (int) in8 (asyncRxBufferport1)); -} - -int serial_tstc () -{ - unsigned char status; - - status = in8 (asyncLSRport1); - if ((status & asyncLSRDataReady) != 0x0) { - return (1); - } - if ((status & ( asyncLSRFramingError | - asyncLSROverrunError | - asyncLSRParityError | - asyncLSRBreakInterrupt )) != 0) { - (void) out8 (asyncLSRport1, - asyncLSRFramingError | - asyncLSROverrunError | - asyncLSRParityError | - asyncLSRBreakInterrupt); - } - return 0; -} - -#endif /* CONFIG_IOP480 */ - -/*****************************************************************************/ -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_405EX) || defined(CONFIG_440) - -#if defined(CONFIG_440) -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300 -#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400 -#else -#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200 -#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300 -#endif - -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) -#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600 -#endif - -#if defined(CONFIG_440GP) -#define CR0_MASK 0x3fff0000 -#define CR0_EXTCLK_ENA 0x00600000 -#define CR0_UDIV_POS 16 -#define UDIV_SUBTRACT 1 -#define UART0_SDR cntrl0 -#define MFREG(a, d) d = mfdcr(a) -#define MTREG(a, d) mtdcr(a, d) -#else /* #if defined(CONFIG_440GP) */ -/* all other 440 PPC's access clock divider via sdr register */ -#define CR0_MASK 0xdfffffff -#define CR0_EXTCLK_ENA 0x00800000 -#define CR0_UDIV_POS 0 -#define UDIV_SUBTRACT 0 -#define UART0_SDR sdr_uart0 -#define UART1_SDR sdr_uart1 -#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ - defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPe) -#define UART2_SDR sdr_uart2 -#endif -#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ - defined(CONFIG_440GR) || defined(CONFIG_440GRx) -#define UART3_SDR sdr_uart3 -#endif -#define MFREG(a, d) mfsdr(a, d) -#define MTREG(a, d) mtsdr(a, d) -#endif /* #if defined(CONFIG_440GP) */ -#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ) -#define UART0_BASE 0xef600300 -#define UART1_BASE 0xef600400 -#define UCR0_MASK 0x0000007f -#define UCR1_MASK 0x00007f00 -#define UCR0_UDIV_POS 0 -#define UCR1_UDIV_POS 8 -#define UDIV_MAX 127 -#elif defined(CONFIG_405EX) -#define UART0_BASE 0xef600200 -#define UART1_BASE 0xef600300 -#define CR0_MASK 0x000000ff -#define CR0_EXTCLK_ENA 0x00800000 -#define CR0_UDIV_POS 0 -#define UDIV_SUBTRACT 0 -#define UART0_SDR sdr_uart0 -#define UART1_SDR sdr_uart1 -#else /* CONFIG_405GP || CONFIG_405CR */ -#define UART0_BASE 0xef600300 -#define UART1_BASE 0xef600400 -#define CR0_MASK 0x00001fff -#define CR0_EXTCLK_ENA 0x000000c0 -#define CR0_UDIV_POS 1 -#define UDIV_MAX 32 -#endif - -/* using serial port 0 or 1 as U-Boot console ? */ -#if defined(CONFIG_UART1_CONSOLE) -#define ACTING_UART0_BASE UART1_BASE -#define ACTING_UART1_BASE UART0_BASE -#else -#define ACTING_UART0_BASE UART0_BASE -#define ACTING_UART1_BASE UART1_BASE -#endif - -#if defined(CONFIG_SERIAL_MULTI) -#define UART_BASE dev_base -#else -#define UART_BASE ACTING_UART0_BASE -#endif - -#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK) -#error "External serial clock not supported on AMCC PPC405EP!" -#endif - -#define UART_RBR 0x00 -#define UART_THR 0x00 -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/*-----------------------------------------------------------------------------+ - | Line Status Register. - +-----------------------------------------------------------------------------*/ -/*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */ -#define asyncLSRDataReady1 0x01 -#define asyncLSROverrunError1 0x02 -#define asyncLSRParityError1 0x04 -#define asyncLSRFramingError1 0x08 -#define asyncLSRBreakInterrupt1 0x10 -#define asyncLSRTxHoldEmpty1 0x20 -#define asyncLSRTxShiftEmpty1 0x40 -#define asyncLSRRxFifoError1 0x80 - -/*-----------------------------------------------------------------------------+ - | Miscellanies defines. - +-----------------------------------------------------------------------------*/ -/*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */ -/*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */ - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO -/*-----------------------------------------------------------------------------+ - | Fifo - +-----------------------------------------------------------------------------*/ -typedef struct { - char *rx_buffer; - ulong rx_put; - ulong rx_get; -} serial_buffer_t; - -volatile static serial_buffer_t buf_info; -#endif - -#if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \ - !defined(CFG_EXT_SERIAL_CLOCK) -static void serial_divs (int baudrate, unsigned long *pudiv, - unsigned short *pbdiv) -{ - sys_info_t sysinfo; - unsigned long div; /* total divisor udiv * bdiv */ - unsigned long umin; /* minimum udiv */ - unsigned short diff; /* smallest diff */ - unsigned long udiv; /* best udiv */ - unsigned short idiff; /* current diff */ - unsigned short ibdiv; /* current bdiv */ - unsigned long i; - unsigned long est; /* current estimate */ - - get_sys_info(&sysinfo); - - udiv = 32; /* Assume lowest possible serial clk */ - div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */ - umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */ - diff = 32; /* highest possible */ - - /* i is the test udiv value -- start with the largest - * possible (32) to minimize serial clock and constrain - * search to umin. - */ - for (i = 32; i > umin; i--) { - ibdiv = div / i; - est = i * ibdiv; - idiff = (est > div) ? (est-div) : (div-est); - if (idiff == 0) { - udiv = i; - break; /* can't do better */ - } else if (idiff < diff) { - udiv = i; /* best so far */ - diff = idiff; /* update lowest diff*/ - } - } - - *pudiv = udiv; - *pbdiv = div / udiv; -} - -#elif defined(CONFIG_405EZ) - -static void serial_divs (int baudrate, unsigned long *pudiv, - unsigned short *pbdiv) -{ - sys_info_t sysinfo; - unsigned long div; /* total divisor udiv * bdiv */ - unsigned long umin; /* minimum udiv */ - unsigned short diff; /* smallest diff */ - unsigned long udiv; /* best udiv */ - unsigned short idiff; /* current diff */ - unsigned short ibdiv; /* current bdiv */ - unsigned long i; - unsigned long est; /* current estimate */ - unsigned long plloutb; - unsigned long cpr_pllc; - u32 reg; - - /* check the pll feedback source */ - mfcpr(cprpllc, cpr_pllc); - - get_sys_info(&sysinfo); - - plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ? - sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * sysinfo.pllFbkDiv) / - sysinfo.pllFwdDivB); - udiv = 256; /* Assume lowest possible serial clk */ - div = plloutb / (16 * baudrate); /* total divisor */ - umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */ - diff = 256; /* highest possible */ - - /* i is the test udiv value -- start with the largest - * possible (256) to minimize serial clock and constrain - * search to umin. - */ - for (i = 256; i > umin; i--) { - ibdiv = div / i; - est = i * ibdiv; - idiff = (est > div) ? (est-div) : (div-est); - if (idiff == 0) { - udiv = i; - break; /* can't do better */ - } else if (idiff < diff) { - udiv = i; /* best so far */ - diff = idiff; /* update lowest diff*/ - } - } - - *pudiv = udiv; - mfcpr(cprperd0, reg); - reg &= ~0x0000ffff; - reg |= ((udiv - 0) << 8) | (udiv - 0); - mtcpr(cprperd0, reg); - *pbdiv = div / udiv; -} -#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */ - -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -#if defined(CONFIG_440) -#if defined(CONFIG_SERIAL_MULTI) -int serial_init_dev (unsigned long dev_base) -#else -int serial_init(void) -#endif -{ - unsigned long reg; - unsigned long udiv; - unsigned short bdiv; - volatile char val; -#ifdef CFG_EXT_SERIAL_CLOCK - unsigned long tmp; -#endif - - MFREG(UART0_SDR, reg); - reg &= ~CR0_MASK; - -#ifdef CFG_EXT_SERIAL_CLOCK - reg |= CR0_EXTCLK_ENA; - udiv = 1; - tmp = gd->baudrate * 16; - bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp; - gd->freqUART = CFG_EXT_SERIAL_CLOCK; -#else - /* For 440, the cpu clock is on divider chain A, UART on divider - * chain B ... so cpu clock is irrelevant. Get the "optimized" - * values that are subject to the 1/2 opb clock constraint - */ - serial_divs (gd->baudrate, &udiv, &bdiv); - - /* Correct UART frequency in bd-info struct now that - * the UART divisor is available - */ - gd->freqUART = gd->freqUART / udiv; -#endif - - reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ - - /* - * Configure input clock to baudrate generator for all - * available serial ports here - */ - MTREG(UART0_SDR, reg); -#if defined(UART1_SDR) - MTREG(UART1_SDR, reg); -#endif -#if defined(UART2_SDR) - MTREG(UART2_SDR, reg); -#endif -#if defined(UART3_SDR) - MTREG(UART3_SDR, reg); -#endif - - out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */ - out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */ - out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */ - out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8(UART_BASE + UART_LSR); /* clear line status */ - val = in8(UART_BASE + UART_RBR); /* read receive buffer */ - out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */ - out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */ - - return (0); -} - -#else /* !defined(CONFIG_440) */ - -#if defined(CONFIG_SERIAL_MULTI) -int serial_init_dev (unsigned long dev_base) -#else -int serial_init (void) -#endif -{ - unsigned long reg; - unsigned long tmp; - unsigned long clk; - unsigned long udiv; - unsigned short bdiv; - volatile char val; - -#ifdef CONFIG_405EX - clk = tmp = 0; - mfsdr(UART0_SDR, reg); - reg &= ~CR0_MASK; -#ifdef CFG_EXT_SERIAL_CLOCK - reg |= CR0_EXTCLK_ENA; - udiv = 1; - tmp = gd->baudrate * 16; - bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp; -#else - serial_divs(gd->baudrate, &udiv, &bdiv); -#endif - reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ - - /* - * Configure input clock to baudrate generator for all - * available serial ports here - */ - mtsdr(UART0_SDR, reg); - -#if defined(UART1_SDR) - mtsdr(UART1_SDR, reg); -#endif - -#elif defined(CONFIG_405EZ) - serial_divs(gd->baudrate, &udiv, &bdiv); - clk = tmp = reg = 0; -#else -#ifdef CONFIG_405EP - reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK); - clk = gd->cpu_clk; - tmp = CFG_BASE_BAUD * 16; - udiv = (clk + tmp / 2) / tmp; - if (udiv > UDIV_MAX) /* max. n bits for udiv */ - udiv = UDIV_MAX; - reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */ - reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */ - mtdcr (cpc0_ucr, reg); -#else /* CONFIG_405EP */ - reg = mfdcr(cntrl0) & ~CR0_MASK; -#ifdef CFG_EXT_SERIAL_CLOCK - clk = CFG_EXT_SERIAL_CLOCK; - udiv = 1; - reg |= CR0_EXTCLK_ENA; -#else - clk = gd->cpu_clk; -#ifdef CFG_405_UART_ERRATA_59 - udiv = 31; /* Errata 59: stuck at 31 */ -#else - tmp = CFG_BASE_BAUD * 16; - udiv = (clk + tmp / 2) / tmp; - if (udiv > UDIV_MAX) /* max. n bits for udiv */ - udiv = UDIV_MAX; -#endif -#endif - reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ - mtdcr (cntrl0, reg); -#endif /* CONFIG_405EP */ - tmp = gd->baudrate * udiv * 16; - bdiv = (clk + tmp / 2) / tmp; -#endif /* CONFIG_405EX */ - - /* Correct UART frequency in bd-info struct now that - * the UART divisor is available - */ -#ifdef CFG_EXT_SERIAL_CLOCK - gd->freqUART = CFG_EXT_SERIAL_CLOCK; -#else - gd->freqUART = gd->freqUART / udiv; -#endif - - out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */ - out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */ - out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */ - out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8(UART_BASE + UART_LSR); /* clear line status */ - val = in8(UART_BASE + UART_RBR); /* read receive buffer */ - out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */ - out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */ - - return (0); -} - -#endif /* if defined(CONFIG_440) */ - -#if defined(CONFIG_SERIAL_MULTI) -void serial_setbrg_dev (unsigned long dev_base) -#else -void serial_setbrg (void) -#endif -{ -#if defined(CONFIG_SERIAL_MULTI) - serial_init_dev(dev_base); -#else - serial_init(); -#endif -} - -#if defined(CONFIG_SERIAL_MULTI) -void serial_putc_dev (unsigned long dev_base, const char c) -#else -void serial_putc (const char c) -#endif -{ - int i; - - if (c == '\n') -#if defined(CONFIG_SERIAL_MULTI) - serial_putc_dev (dev_base, '\r'); -#else - serial_putc ('\r'); -#endif - - /* check THRE bit, wait for transmiter available */ - for (i = 1; i < 3500; i++) { - if ((in8 (UART_BASE + UART_LSR) & 0x20) == 0x20) - break; - udelay (100); - } - out8 (UART_BASE + UART_THR, c); /* put character out */ -} - -#if defined(CONFIG_SERIAL_MULTI) -void serial_puts_dev (unsigned long dev_base, const char *s) -#else -void serial_puts (const char *s) -#endif -{ - while (*s) { -#if defined(CONFIG_SERIAL_MULTI) - serial_putc_dev (dev_base, *s++); -#else - serial_putc (*s++); -#endif - } -} - -#if defined(CONFIG_SERIAL_MULTI) -int serial_getc_dev (unsigned long dev_base) -#else -int serial_getc (void) -#endif -{ - unsigned char status = 0; - - while (1) { -#if defined(CONFIG_HW_WATCHDOG) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ -#endif /* CONFIG_HW_WATCHDOG */ - status = in8 (UART_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) { - break; - } - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - out8 (UART_BASE + UART_LSR, - asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1); - } - } - return (0x000000ff & (int) in8 (UART_BASE)); -} - -#if defined(CONFIG_SERIAL_MULTI) -int serial_tstc_dev (unsigned long dev_base) -#else -int serial_tstc (void) -#endif -{ - unsigned char status; - - status = in8 (UART_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) { - return (1); - } - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - out8 (UART_BASE + UART_LSR, - asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1); - } - return 0; -} - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - -void serial_isr (void *arg) -{ - int space; - int c; - const int rx_get = buf_info.rx_get; - int rx_put = buf_info.rx_put; - - if (rx_get <= rx_put) { - space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); - } else { - space = rx_get - rx_put; - } - while (serial_tstc_dev (ACTING_UART0_BASE)) { - c = serial_getc_dev (ACTING_UART0_BASE); - if (space) { - buf_info.rx_buffer[rx_put++] = c; - space--; - } - if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) - rx_put = 0; - if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) { - /* Stop flow by setting RTS inactive */ - out8 (ACTING_UART0_BASE + UART_MCR, - in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02)); - } - } - buf_info.rx_put = rx_put; -} - -void serial_buffered_init (void) -{ - serial_puts ("Switching to interrupt driven serial input mode.\n"); - buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO); - buf_info.rx_put = 0; - buf_info.rx_get = 0; - - if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) { - serial_puts ("Check CTS signal present on serial port: OK.\n"); - } else { - serial_puts ("WARNING: CTS signal not present on serial port.\n"); - } - - irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ , - serial_isr /*interrupt_handler_t *handler */ , - (void *) &buf_info /*void *arg */ ); - - /* Enable "RX Data Available" Interrupt on UART */ - /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */ - out8 (ACTING_UART0_BASE + UART_IER, 0x01); - /* Set DTR active */ - out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01); - /* Start flow by setting RTS active */ - out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02); - /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */ - out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1); -} - -void serial_buffered_putc (const char c) -{ - /* Wait for CTS */ -#if defined(CONFIG_HW_WATCHDOG) - while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)) - WATCHDOG_RESET (); -#else - while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)); -#endif - serial_putc (c); -} - -void serial_buffered_puts (const char *s) -{ - serial_puts (s); -} - -int serial_buffered_getc (void) -{ - int space; - int c; - int rx_get = buf_info.rx_get; - int rx_put; - -#if defined(CONFIG_HW_WATCHDOG) - while (rx_get == buf_info.rx_put) - WATCHDOG_RESET (); -#else - while (rx_get == buf_info.rx_put); -#endif - c = buf_info.rx_buffer[rx_get++]; - if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO) - rx_get = 0; - buf_info.rx_get = rx_get; - - rx_put = buf_info.rx_put; - if (rx_get <= rx_put) { - space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); - } else { - space = rx_get - rx_put; - } - if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) { - /* Start flow by setting RTS active */ - out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02); - } - - return c; -} - -int serial_buffered_tstc (void) -{ - return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0; -} - -#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ - -#if defined(CONFIG_CMD_KGDB) -/* - AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port - number 0 or number 1 - - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 : - configuration has been already done - - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 : - configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE -*/ -#if (CONFIG_KGDB_SER_INDEX & 2) -void kgdb_serial_init (void) -{ - volatile char val; - unsigned short br_reg; - - get_clocks (); - br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) + - 5) / 10; - /* - * Init onboard 16550 UART - */ - out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */ - out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */ - out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */ - out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */ - out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */ - val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */ - out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */ - out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */ -} - -void putDebugChar (const char c) -{ - if (c == '\n') - serial_putc ('\r'); - - out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */ - - /* check THRE bit, wait for transfer done */ - while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20); -} - -void putDebugStr (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int getDebugChar (void) -{ - unsigned char status = 0; - - while (1) { - status = in8 (ACTING_UART1_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) { - break; - } - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - out8 (ACTING_UART1_BASE + UART_LSR, - asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1); - } - } - return (0x000000ff & (int) in8 (ACTING_UART1_BASE)); -} - -void kgdb_interruptible (int yes) -{ - return; -} - -#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */ - -void kgdb_serial_init (void) -{ - serial_printf ("[on serial] "); -} - -void putDebugChar (int c) -{ - serial_putc (c); -} - -void putDebugStr (const char *str) -{ - serial_puts (str); -} - -int getDebugChar (void) -{ - return serial_getc (); -} - -void kgdb_interruptible (int yes) -{ - return; -} -#endif /* (CONFIG_KGDB_SER_INDEX & 2) */ -#endif - - -#if defined(CONFIG_SERIAL_MULTI) -int serial0_init(void) -{ - return (serial_init_dev(UART0_BASE)); -} - -int serial1_init(void) -{ - return (serial_init_dev(UART1_BASE)); -} -void serial0_setbrg (void) -{ - serial_setbrg_dev(UART0_BASE); -} -void serial1_setbrg (void) -{ - serial_setbrg_dev(UART1_BASE); -} - -void serial0_putc(const char c) -{ - serial_putc_dev(UART0_BASE,c); -} - -void serial1_putc(const char c) -{ - serial_putc_dev(UART1_BASE, c); -} -void serial0_puts(const char *s) -{ - serial_puts_dev(UART0_BASE, s); -} - -void serial1_puts(const char *s) -{ - serial_puts_dev(UART1_BASE, s); -} - -int serial0_getc(void) -{ - return(serial_getc_dev(UART0_BASE)); -} - -int serial1_getc(void) -{ - return(serial_getc_dev(UART1_BASE)); -} -int serial0_tstc(void) -{ - return (serial_tstc_dev(UART0_BASE)); -} - -int serial1_tstc(void) -{ - return (serial_tstc_dev(UART1_BASE)); -} - -struct serial_device serial0_device = -{ - "serial0", - "UART0", - serial0_init, - serial0_setbrg, - serial0_getc, - serial0_tstc, - serial0_putc, - serial0_puts, -}; - -struct serial_device serial1_device = -{ - "serial1", - "UART1", - serial1_init, - serial1_setbrg, - serial1_getc, - serial1_tstc, - serial1_putc, - serial1_puts, -}; -#endif /* CONFIG_SERIAL_MULTI */ - -#endif /* CONFIG_405GP || CONFIG_405CR */ -- cgit v1.3.1 From 3248f63ad89cb031491edb7016587fe6e9a238b9 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 22 Oct 2007 16:22:40 +0200 Subject: ppc4xx: Rework of 4xx serial driver (4) Change 4xx_uart.c: - Use in_8/out_8 macros instead of in8/out8 - No need for UART_BASE marco anymore, now really handled via function parameter - serial_init_common() introduced - Further coding style cleanup Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_uart.c | 313 +++++++++++++++++++++++--------------------------- 1 file changed, 146 insertions(+), 167 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c index 8560456e52d..c6b229f3a6c 100644 --- a/cpu/ppc4xx/4xx_uart.c +++ b/cpu/ppc4xx/4xx_uart.c @@ -20,7 +20,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -/*------------------------------------------------------------------------------+ */ + /* * This source code has been made available to you by IBM on an AS-IS * basis. Anyone receiving this source is licensed under IBM @@ -40,14 +40,11 @@ * COPYRIGHT I B M CORPORATION 1995 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ -/*------------------------------------------------------------------------------- */ -/* - * Travis Sawyer 15 September 2004 - * Added CONFIG_SERIAL_MULTI support - */ + #include #include #include +#include #include #include "vecnum.h" @@ -142,12 +139,6 @@ DECLARE_GLOBAL_DATA_PTR; #define ACTING_UART1_BASE UART1_BASE #endif -#if defined(CONFIG_SERIAL_MULTI) -#define UART_BASE dev_base -#else -#define UART_BASE ACTING_UART0_BASE -#endif - #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK) #error "External serial clock not supported on AMCC PPC405EP!" #endif @@ -168,7 +159,6 @@ DECLARE_GLOBAL_DATA_PTR; /*-----------------------------------------------------------------------------+ | Line Status Register. +-----------------------------------------------------------------------------*/ -/*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */ #define asyncLSRDataReady1 0x01 #define asyncLSROverrunError1 0x02 #define asyncLSRParityError1 0x04 @@ -178,12 +168,6 @@ DECLARE_GLOBAL_DATA_PTR; #define asyncLSRTxShiftEmpty1 0x40 #define asyncLSRRxFifoError1 0x80 -/*-----------------------------------------------------------------------------+ - | Miscellanies defines. - +-----------------------------------------------------------------------------*/ -/*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */ -/*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */ - #ifdef CONFIG_SERIAL_SOFTWARE_FIFO /*-----------------------------------------------------------------------------+ | Fifo @@ -197,8 +181,36 @@ typedef struct { volatile static serial_buffer_t buf_info; #endif -#if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \ - !defined(CFG_EXT_SERIAL_CLOCK) +static void serial_init_common(u32 base, u32 udiv, u16 bdiv) +{ + PPC4xx_SYS_INFO sys_info; + u8 val; + + get_sys_info(&sys_info); + + /* Correct UART frequency in bd-info struct now that + * the UART divisor is available + */ +#ifdef CFG_EXT_SERIAL_CLOCK + sys_info.freqUART = CFG_EXT_SERIAL_CLOCK; +#else + sys_info.freqUART = sys_info.freqUART / udiv; +#endif + + out_8((u8 *)base + UART_LCR, 0x80); /* set DLAB bit */ + out_8((u8 *)base + UART_DLL, bdiv); /* set baudrate divisor */ + out_8((u8 *)base + UART_DLM, bdiv >> 8); /* set baudrate divisor */ + out_8((u8 *)base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out_8((u8 *)base + UART_FCR, 0x00); /* disable FIFO */ + out_8((u8 *)base + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in_8((u8 *)base + UART_LSR); /* clear line status */ + val = in_8((u8 *)base + UART_RBR); /* read receive buffer */ + out_8((u8 *)base + UART_SCR, 0x00); /* set scratchpad */ + out_8((u8 *)base + UART_IER, 0x00); /* set interrupt enable reg */ +} + +#if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \ + !defined(CFG_EXT_SERIAL_CLOCK) static void serial_divs (int baudrate, unsigned long *pudiv, unsigned short *pbdiv) { @@ -264,8 +276,8 @@ static void serial_divs (int baudrate, unsigned long *pudiv, get_sys_info(&sysinfo); plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ? - sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * sysinfo.pllFbkDiv) / - sysinfo.pllFwdDivB); + sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * + sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB); udiv = 256; /* Assume lowest possible serial clk */ div = plloutb / (16 * baudrate); /* total divisor */ umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */ @@ -303,16 +315,11 @@ static void serial_divs (int baudrate, unsigned long *pudiv, */ #if defined(CONFIG_440) -#if defined(CONFIG_SERIAL_MULTI) -int serial_init_dev (unsigned long dev_base) -#else -int serial_init(void) -#endif +int serial_init_dev(unsigned long base) { unsigned long reg; unsigned long udiv; unsigned short bdiv; - volatile char val; #ifdef CFG_EXT_SERIAL_CLOCK unsigned long tmp; #endif @@ -325,18 +332,12 @@ int serial_init(void) udiv = 1; tmp = gd->baudrate * 16; bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp; - gd->freqUART = CFG_EXT_SERIAL_CLOCK; #else /* For 440, the cpu clock is on divider chain A, UART on divider * chain B ... so cpu clock is irrelevant. Get the "optimized" * values that are subject to the 1/2 opb clock constraint */ serial_divs (gd->baudrate, &udiv, &bdiv); - - /* Correct UART frequency in bd-info struct now that - * the UART divisor is available - */ - gd->freqUART = gd->freqUART / udiv; #endif reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ @@ -356,34 +357,20 @@ int serial_init(void) MTREG(UART3_SDR, reg); #endif - out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */ - out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */ - out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */ - out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8(UART_BASE + UART_LSR); /* clear line status */ - val = in8(UART_BASE + UART_RBR); /* read receive buffer */ - out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */ - out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */ + serial_init_common(base, udiv, bdiv); return (0); } #else /* !defined(CONFIG_440) */ -#if defined(CONFIG_SERIAL_MULTI) -int serial_init_dev (unsigned long dev_base) -#else -int serial_init (void) -#endif +int serial_init_dev (unsigned long base) { unsigned long reg; unsigned long tmp; unsigned long clk; unsigned long udiv; unsigned short bdiv; - volatile char val; #ifdef CONFIG_405EX clk = tmp = 0; @@ -447,88 +434,42 @@ int serial_init (void) bdiv = (clk + tmp / 2) / tmp; #endif /* CONFIG_405EX */ - /* Correct UART frequency in bd-info struct now that - * the UART divisor is available - */ -#ifdef CFG_EXT_SERIAL_CLOCK - gd->freqUART = CFG_EXT_SERIAL_CLOCK; -#else - gd->freqUART = gd->freqUART / udiv; -#endif - - out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */ - out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */ - out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */ - out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8(UART_BASE + UART_LSR); /* clear line status */ - val = in8(UART_BASE + UART_RBR); /* read receive buffer */ - out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */ - out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */ + serial_init_common(base, udiv, bdiv); return (0); } #endif /* if defined(CONFIG_440) */ -#if defined(CONFIG_SERIAL_MULTI) -void serial_setbrg_dev (unsigned long dev_base) -#else -void serial_setbrg (void) -#endif +void serial_setbrg_dev(unsigned long base) { -#if defined(CONFIG_SERIAL_MULTI) - serial_init_dev(dev_base); -#else - serial_init(); -#endif + serial_init_dev(base); } -#if defined(CONFIG_SERIAL_MULTI) -void serial_putc_dev (unsigned long dev_base, const char c) -#else -void serial_putc (const char c) -#endif +void serial_putc_dev(unsigned long base, const char c) { int i; if (c == '\n') -#if defined(CONFIG_SERIAL_MULTI) - serial_putc_dev (dev_base, '\r'); -#else - serial_putc ('\r'); -#endif + serial_putc_dev(base, '\r'); /* check THRE bit, wait for transmiter available */ for (i = 1; i < 3500; i++) { - if ((in8 (UART_BASE + UART_LSR) & 0x20) == 0x20) + if ((in_8((u8 *)base + UART_LSR) & 0x20) == 0x20) break; udelay (100); } - out8 (UART_BASE + UART_THR, c); /* put character out */ + + out_8((u8 *)base + UART_THR, c); /* put character out */ } -#if defined(CONFIG_SERIAL_MULTI) -void serial_puts_dev (unsigned long dev_base, const char *s) -#else -void serial_puts (const char *s) -#endif +void serial_puts_dev (unsigned long base, const char *s) { - while (*s) { -#if defined(CONFIG_SERIAL_MULTI) - serial_putc_dev (dev_base, *s++); -#else - serial_putc (*s++); -#endif - } + while (*s) + serial_putc_dev (base, *s++); } -#if defined(CONFIG_SERIAL_MULTI) -int serial_getc_dev (unsigned long dev_base) -#else -int serial_getc (void) -#endif +int serial_getc_dev (unsigned long base) { unsigned char status = 0; @@ -536,46 +477,45 @@ int serial_getc (void) #if defined(CONFIG_HW_WATCHDOG) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ #endif /* CONFIG_HW_WATCHDOG */ - status = in8 (UART_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) { + + status = in_8((u8 *)base + UART_LSR); + if ((status & asyncLSRDataReady1) != 0x0) break; - } + if ((status & ( asyncLSRFramingError1 | asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1 )) != 0) { - out8 (UART_BASE + UART_LSR, + out_8((u8 *)base + UART_LSR, asyncLSRFramingError1 | asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1); } } - return (0x000000ff & (int) in8 (UART_BASE)); + + return (0x000000ff & (int) in_8((u8 *)base)); } -#if defined(CONFIG_SERIAL_MULTI) -int serial_tstc_dev (unsigned long dev_base) -#else -int serial_tstc (void) -#endif +int serial_tstc_dev (unsigned long base) { unsigned char status; - status = in8 (UART_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) { + status = in_8((u8 *)base + UART_LSR); + if ((status & asyncLSRDataReady1) != 0x0) return (1); - } + if ((status & ( asyncLSRFramingError1 | asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1 )) != 0) { - out8 (UART_BASE + UART_LSR, + out_8((u8 *)base + UART_LSR, asyncLSRFramingError1 | asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1); } + return 0; } @@ -588,11 +528,11 @@ void serial_isr (void *arg) const int rx_get = buf_info.rx_get; int rx_put = buf_info.rx_put; - if (rx_get <= rx_put) { + if (rx_get <= rx_put) space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); - } else { + else space = rx_get - rx_put; - } + while (serial_tstc_dev (ACTING_UART0_BASE)) { c = serial_getc_dev (ACTING_UART0_BASE); if (space) { @@ -603,8 +543,9 @@ void serial_isr (void *arg) rx_put = 0; if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) { /* Stop flow by setting RTS inactive */ - out8 (ACTING_UART0_BASE + UART_MCR, - in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02)); + out_8((u8 *)ACTING_UART0_BASE + UART_MCR, + in_8((u8 *)ACTING_UART0_BASE + UART_MCR) & + (0xFF ^ 0x02)); } } buf_info.rx_put = rx_put; @@ -617,35 +558,35 @@ void serial_buffered_init (void) buf_info.rx_put = 0; buf_info.rx_get = 0; - if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) { + if (in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10) serial_puts ("Check CTS signal present on serial port: OK.\n"); - } else { + else serial_puts ("WARNING: CTS signal not present on serial port.\n"); - } irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ , serial_isr /*interrupt_handler_t *handler */ , (void *) &buf_info /*void *arg */ ); /* Enable "RX Data Available" Interrupt on UART */ - /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */ - out8 (ACTING_UART0_BASE + UART_IER, 0x01); + out_8(ACTING_UART0_BASE + UART_IER, 0x01); /* Set DTR active */ - out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01); + out_8(ACTING_UART0_BASE + UART_MCR, + in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x01); /* Start flow by setting RTS active */ - out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02); + out_8(ACTING_UART0_BASE + UART_MCR, + in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02); /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */ - out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1); + out_8(ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1); } void serial_buffered_putc (const char c) { /* Wait for CTS */ #if defined(CONFIG_HW_WATCHDOG) - while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)) + while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10)) WATCHDOG_RESET (); #else - while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)); + while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10)); #endif serial_putc (c); } @@ -674,14 +615,15 @@ int serial_buffered_getc (void) buf_info.rx_get = rx_get; rx_put = buf_info.rx_put; - if (rx_get <= rx_put) { + if (rx_get <= rx_put) space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); - } else { + else space = rx_get - rx_put; - } + if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) { /* Start flow by setting RTS active */ - out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02); + out_8(ACTING_UART0_BASE + UART_MCR, + in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02); } return c; @@ -706,8 +648,8 @@ int serial_buffered_tstc (void) #if (CONFIG_KGDB_SER_INDEX & 2) void kgdb_serial_init (void) { - volatile char val; - unsigned short br_reg; + u8 val; + u16 br_reg; get_clocks (); br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) + @@ -715,16 +657,16 @@ void kgdb_serial_init (void) /* * Init onboard 16550 UART */ - out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */ - out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */ - out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */ - out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */ - out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */ - val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */ - out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */ - out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */ + out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out_8((u8 *)ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */ + out_8((u8 *)ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */ + out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */ + out_8((u8 *)ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */ + out_8((u8 *)ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in_8((u8 *)ACTING_UART1_BASE + UART_LSR); /* clear line status */ + val = in_8((u8 *)ACTING_UART1_BASE + UART_RBR); /* read receive buffer */ + out_8((u8 *)ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */ + out_8((u8 *)ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */ } void putDebugChar (const char c) @@ -732,17 +674,16 @@ void putDebugChar (const char c) if (c == '\n') serial_putc ('\r'); - out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */ + out_8((u8 *)ACTING_UART1_BASE + UART_THR, c); /* put character out */ /* check THRE bit, wait for transfer done */ - while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20); + while ((in_8((u8 *)ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20); } void putDebugStr (const char *s) { - while (*s) { + while (*s) serial_putc (*s++); - } } int getDebugChar (void) @@ -750,22 +691,23 @@ int getDebugChar (void) unsigned char status = 0; while (1) { - status = in8 (ACTING_UART1_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) { + status = in_8((u8 *)ACTING_UART1_BASE + UART_LSR); + if ((status & asyncLSRDataReady1) != 0x0) break; - } - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - out8 (ACTING_UART1_BASE + UART_LSR, + + if ((status & (asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1 )) != 0) { + out_8((u8 *)ACTING_UART1_BASE + UART_LSR, asyncLSRFramingError1 | asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1); } } - return (0x000000ff & (int) in8 (ACTING_UART1_BASE)); + + return (0x000000ff & (int) in_8((u8 *)ACTING_UART1_BASE)); } void kgdb_interruptible (int yes) @@ -813,10 +755,12 @@ int serial1_init(void) { return (serial_init_dev(UART1_BASE)); } + void serial0_setbrg (void) { serial_setbrg_dev(UART0_BASE); } + void serial1_setbrg (void) { serial_setbrg_dev(UART1_BASE); @@ -831,6 +775,7 @@ void serial1_putc(const char c) { serial_putc_dev(UART1_BASE, c); } + void serial0_puts(const char *s) { serial_puts_dev(UART0_BASE, s); @@ -850,6 +795,7 @@ int serial1_getc(void) { return(serial_getc_dev(UART1_BASE)); } + int serial0_tstc(void) { return (serial_tstc_dev(UART0_BASE)); @@ -883,6 +829,39 @@ struct serial_device serial1_device = serial1_putc, serial1_puts, }; +#else +/* + * Wrapper functions + */ +int serial_init(void) +{ + return serial_init_dev(ACTING_UART0_BASE); +} + +void serial_setbrg(void) +{ + serial_setbrg_dev(ACTING_UART0_BASE); +} + +void serial_putc(const char c) +{ + serial_putc_dev(ACTING_UART0_BASE, c); +} + +void serial_puts(const char *s) +{ + serial_puts_dev(ACTING_UART0_BASE, s); +} + +int serial_getc(void) +{ + return serial_getc_dev(ACTING_UART0_BASE); +} + +int serial_tstc(void) +{ + return serial_tstc_dev(ACTING_UART0_BASE); +} #endif /* CONFIG_SERIAL_MULTI */ #endif /* CONFIG_405GP || CONFIG_405CR */ -- cgit v1.3.1 From 353f2688b4e0fc7b969bc70a02be4b40bf0dd124 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 23 Oct 2007 10:10:08 +0200 Subject: ppc4xx: Add initial AMCC Haleakala PPC405EXr eval board support The Haleakala is nearly identical with the Kilauea eval board. The only difference is that the 405EXr only supports one EMAC and one PCIe interface. This patch adds support for the Haleakala board by using the identical image for Kilauea and Haleakala. The distinction is done by comparing the PVR. Signed-off-by: Stefan Roese --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 6 ++++-- board/amcc/kilauea/kilauea.c | 36 +++++++++++++++++++++++++++++++++--- cpu/ppc4xx/4xx_enet.c | 10 ++++++++++ include/configs/kilauea.h | 1 + 6 files changed, 50 insertions(+), 5 deletions(-) (limited to 'cpu') diff --git a/MAINTAINERS b/MAINTAINERS index 5ae588f6644..bf0ebb17583 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -303,6 +303,7 @@ Stefan Roese bamboo PPC440EP bunbinga PPC405EP ebony PPC440GP + haleakala PPC405EXr katmai PPC440SPe kilauea PPC405EX lwmon5 PPC440EPx diff --git a/MAKEALL b/MAKEALL index 874d3a6710d..67b39c319b5 100755 --- a/MAKEALL +++ b/MAKEALL @@ -180,6 +180,7 @@ LIST_4xx=" \ ERIC \ EXBITGEN \ G2000 \ + haleakala \ hcu4 \ hcu5 \ HH405 \ diff --git a/Makefile b/Makefile index 039cec08f76..814bba8af72 100644 --- a/Makefile +++ b/Makefile @@ -1168,8 +1168,10 @@ KAREF_config: unconfig katmai_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx katmai amcc -kilauea_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx kilauea amcc +# Kilauea & Haleakala images are identical (recognized via PVR) +kilauea_config \ +haleakala_config: unconfig + @$(MKCONFIG) -n $@ -a kilauea ppc ppc4xx kilauea amcc luan_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx luan amcc diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c index b59bd6fc0e2..77c0eb43641 100644 --- a/board/amcc/kilauea/kilauea.c +++ b/board/amcc/kilauea/kilauea.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #if defined(CONFIG_PCI) #include @@ -225,11 +225,41 @@ int misc_init_r(void) return 0; } +int board_emac_count(void) +{ + u32 pvr = get_pvr(); + + /* + * 405EXr only has one EMAC interface, 405EX has two + */ + if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA)) + return 1; + else + return 2; +} + +static int board_pcie_count(void) +{ + u32 pvr = get_pvr(); + + /* + * 405EXr only has one EMAC interface, 405EX has two + */ + if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA)) + return 1; + else + return 2; +} + int checkboard (void) { char *s = getenv("serial#"); + u32 pvr = get_pvr(); - printf("Board: Kilauea - AMCC PPC405EX Evaluation Board"); + if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA)) + printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board"); + else + printf("Board: Kilauea - AMCC PPC405EX Evaluation Board"); if (s != NULL) { puts(", serial# "); @@ -310,7 +340,7 @@ void pcie_setup_hoses(int busno) char *env; unsigned int delay; - for (i = 0; i < 2; i++) { + for (i = 0; i < board_pcie_count(); i++) { if (is_end_point(i)) { printf("PCIE%d: will be configured as endpoint\n", i); diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 6b4834481e3..67b3a24d2ff 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -158,7 +158,14 @@ struct eth_device *emac0_dev = NULL; /* * Get count of EMAC devices (doesn't have to be the max. possible number * supported by the cpu) + * + * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the + * EMAC count is possible. As it is needed for the Kilauea/Haleakala + * 405EX/405EXr eval board, using the same binary. */ +#if defined(CONFIG_BOARD_EMAC_COUNT) +#define LAST_EMAC_NUM board_emac_count() +#else /* CONFIG_BOARD_EMAC_COUNT */ #if defined(CONFIG_HAS_ETH3) #define LAST_EMAC_NUM 4 #elif defined(CONFIG_HAS_ETH2) @@ -168,6 +175,7 @@ struct eth_device *emac0_dev = NULL; #else #define LAST_EMAC_NUM 1 #endif +#endif /* CONFIG_BOARD_EMAC_COUNT */ /* normal boards start with EMAC0 */ #if !defined(CONFIG_EMAC_NR_START) @@ -197,6 +205,8 @@ extern int emac4xx_miiphy_read (char *devname, unsigned char addr, extern int emac4xx_miiphy_write (char *devname, unsigned char addr, unsigned char reg, unsigned short value); +int board_emac_count(void); + /*-----------------------------------------------------------------------------+ | ppc_4xx_eth_halt | Disable MAL channel, and EMACn diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 90bdd6959b7..9a9f7ba1bc2 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -38,6 +38,7 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_BOARD_EMAC_COUNT /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the -- cgit v1.3.1 From f10493c6d77a1e07a6c2ff4d772937a5e7359d6a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 23 Oct 2007 11:31:05 +0200 Subject: ppc4xx: Correct UART input clock calculation and passing to fdt We now use a value in the gd (global data) structure for the UART input frequency, since the PPC4xx_SYS_INFO struct is always rewritten completely in get_sys_info(). Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_uart.c | 4 ++-- cpu/ppc4xx/fdt.c | 8 +++++--- include/asm-ppc/global_data.h | 3 +++ 3 files changed, 10 insertions(+), 5 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c index c6b229f3a6c..ac2b12b8773 100644 --- a/cpu/ppc4xx/4xx_uart.c +++ b/cpu/ppc4xx/4xx_uart.c @@ -192,9 +192,9 @@ static void serial_init_common(u32 base, u32 udiv, u16 bdiv) * the UART divisor is available */ #ifdef CFG_EXT_SERIAL_CLOCK - sys_info.freqUART = CFG_EXT_SERIAL_CLOCK; + gd->uart_clk = CFG_EXT_SERIAL_CLOCK; #else - sys_info.freqUART = sys_info.freqUART / udiv; + gd->uart_clk = sys_info.freqUART / udiv; #endif out_8((u8 *)base + UART_LCR, 0x80); /* set DLAB bit */ diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c index bf97c2a4356..dcedbbb3083 100644 --- a/cpu/ppc4xx/fdt.c +++ b/cpu/ppc4xx/fdt.c @@ -36,6 +36,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + static void do_fixup(void *fdt, const char *node, const char *prop, const void *val, int len, int create) { @@ -44,7 +46,7 @@ static void do_fixup(void *fdt, const char *node, const char *prop, debug("Updating property '%s/%s' = ", node, prop); for (i = 0; i < len; i++) debug(" %.2x", *(u8*)(val+i)); - debug("\n"); + debug("(%d)\n", *(u32 *)val); #endif int rc = fdt_find_and_setprop(fdt, node, prop, val, len, create); if (rc) @@ -83,9 +85,9 @@ static void do_fixup_uart(void *fdt, int offset, int i, bd_t *bd) get_sys_info(&sys_info); - debug("Updating node UART%d\n", i); + debug("Updating node UART%d: clock-frequency=%d\n", i, gd->uart_clk); - val = cpu_to_fdt32(sys_info.freqUART); + val = cpu_to_fdt32(gd->uart_clk); rc = fdt_setprop(fdt, offset, "clock-frequency", &val, 4); if (rc) printf("Unable to update node UART, err=%s\n", fdt_strerror(rc)); diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 4676e2c4089..05aee749494 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -107,6 +107,9 @@ typedef struct global_data { unsigned int dp_alloc_base; unsigned int dp_alloc_top; #endif +#if defined(CONFIG_4xx) + u32 uart_clk; +#endif /* CONFIG_4xx */ #if defined(CFG_GT_6426x) unsigned int mirror_hack[16]; #endif -- cgit v1.3.1 From 2d83476a4c1c9911d158a3f8a4312d354bc1bdb7 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 23 Oct 2007 14:03:17 +0200 Subject: ppc4xx: Change 4xx_enet & miiphy to use out_be32() and friends This patch changes all in32/out32 calls to use the recommended in_be32/ out_be32 macros instead. Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_enet.c | 118 +++++++++++++++++++++++++------------------------- cpu/ppc4xx/miiphy.c | 29 +++++++------ 2 files changed, 74 insertions(+), 73 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 67b3a24d2ff..6ab04e73d5a 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -81,6 +81,7 @@ #include #include #include +#include #include #include #include @@ -221,7 +222,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) unsigned long mfr; #endif - out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ + out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ /* 1st reset MAL channel */ /* Note: writing a 0 to a channel has no effect */ @@ -250,7 +251,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) mtsdr(sdr_mfr, mfr); #endif - out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); + out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); #if defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ @@ -353,8 +354,8 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) /* Ensure we setup mdio for this devnum and ONLY this devnum */ zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); - out32 (ZMII_FER, zmiifer); - out32 (RGMII_FER, rmiifer); + out_be32(ZMII_FER, zmiifer); + out_be32(RGMII_FER, rmiifer); return ((int)pfc1); } @@ -372,31 +373,31 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) switch (pfc1) { case SDR0_PFC1_SELECT_CONFIG_2: /* 1 x GMII port */ - out32 (ZMII_FER, 0x00); - out32 (RGMII_FER, 0x00000037); + out_be32((void *)ZMII_FER, 0x00); + out_be32((void *)RGMII_FER, 0x00000037); bis->bi_phymode[0] = BI_PHYMODE_GMII; bis->bi_phymode[1] = BI_PHYMODE_NONE; break; case SDR0_PFC1_SELECT_CONFIG_4: /* 2 x RGMII ports */ - out32 (ZMII_FER, 0x00); - out32 (RGMII_FER, 0x00000055); + out_be32((void *)ZMII_FER, 0x00); + out_be32((void *)RGMII_FER, 0x00000055); bis->bi_phymode[0] = BI_PHYMODE_RGMII; bis->bi_phymode[1] = BI_PHYMODE_RGMII; break; case SDR0_PFC1_SELECT_CONFIG_6: /* 2 x SMII ports */ - out32 (ZMII_FER, - ((ZMII_FER_SMII) << ZMII_FER_V(0)) | - ((ZMII_FER_SMII) << ZMII_FER_V(1))); - out32 (RGMII_FER, 0x00000000); + out_be32((void *)ZMII_FER, + ((ZMII_FER_SMII) << ZMII_FER_V(0)) | + ((ZMII_FER_SMII) << ZMII_FER_V(1))); + out_be32((void *)RGMII_FER, 0x00000000); bis->bi_phymode[0] = BI_PHYMODE_SMII; bis->bi_phymode[1] = BI_PHYMODE_SMII; break; case SDR0_PFC1_SELECT_CONFIG_1_2: /* only 1 x MII supported */ - out32 (ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); - out32 (RGMII_FER, 0x00000000); + out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); + out_be32((void *)RGMII_FER, 0x00000000); bis->bi_phymode[0] = BI_PHYMODE_MII; bis->bi_phymode[1] = BI_PHYMODE_NONE; break; @@ -405,9 +406,9 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) } /* Ensure we setup mdio for this devnum and ONLY this devnum */ - zmiifer = in32 (ZMII_FER); + zmiifer = in_be32((void *)ZMII_FER); zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); - out32 (ZMII_FER, zmiifer); + out_be32((void *)ZMII_FER, zmiifer); return ((int)0x0); } @@ -425,7 +426,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) switch (1) { case 1: /* 2 x RGMII ports */ - out32 (RGMII_FER, 0x00000055); + out_be32((void *)RGMII_FER, 0x00000055); bis->bi_phymode[0] = BI_PHYMODE_RGMII; bis->bi_phymode[1] = BI_PHYMODE_RGMII; break; @@ -437,9 +438,9 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) } /* Ensure we setup mdio for this devnum and ONLY this devnum */ - gmiifer = in32(RGMII_FER); + gmiifer = in_be32((void *)RGMII_FER); gmiifer |= (1 << (19-devnum)); - out32 (RGMII_FER, gmiifer); + out_be32((void *)RGMII_FER, gmiifer); return ((int)0x0); } @@ -535,27 +536,27 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* NOTE: Therefore, disable all other EMACS, since we handle */ /* NOTE: only one emac at a time */ reg = 0; - out32 (ZMII_FER, 0); + out_be32((void *)ZMII_FER, 0); udelay (100); #if defined(CONFIG_440EP) || defined(CONFIG_440GR) - out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); + out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); #elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); #elif defined(CONFIG_440GP) /* set RMII mode */ - out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0); + out_be32((void *)ZMII_FER, ZMII_RMII | ZMII_MDI0); #else if ((devnum == 0) || (devnum == 1)) { - out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); + out_be32((void *)ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); } else { /* ((devnum == 2) || (devnum == 3)) */ - out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum)); - out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) | - (RGMII_FER_RGMII << RGMII_FER_V (3)))); + out_be32((void *)ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum)); + out_be32((void *)RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) | + (RGMII_FER_RGMII << RGMII_FER_V (3)))); } #endif - out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); + out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ #if defined(CONFIG_405EX) ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); @@ -573,11 +574,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) mtsdr(sdr_mfr, mfr); #endif - out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); - __asm__ volatile ("eieio"); + out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); failsafe = 1000; - while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { + while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { udelay (1000); failsafe--; } @@ -610,7 +610,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) else mode_reg |= EMAC_M1_OBCI_GT100; - out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); + out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ /* wait for PHY to complete auto negotiation */ @@ -768,11 +768,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #endif /* Set ZMII/RGMII speed according to the phy link speed */ - reg = in32 (ZMII_SSR); + reg = in_be32(ZMII_SSR); if ( (speed == 100) || (speed == 1000) ) - out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); + out_be32(ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); else - out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); + out_be32(ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); if ((devnum == 2) || (devnum == 3)) { if (speed == 1000) @@ -785,7 +785,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) printf("Error in RGMII Speed\n"); return -1; } - out32 (RGMII_SSR, reg); + out_be32(RGMII_SSR, reg); } #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ @@ -801,7 +801,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) printf("Error in RGMII Speed\n"); return -1; } - out32 (RGMII_SSR, reg); + out_be32((void *)RGMII_SSR, reg); #endif /* set the Mal configuration reg */ @@ -912,7 +912,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) reg = reg << 8; reg |= dev->enetaddr[1]; - out32 (EMAC_IAH + hw_p->hw_addr, reg); + out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg); reg = 0x00000000; reg |= dev->enetaddr[2]; /* set low address */ @@ -923,7 +923,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) reg = reg << 8; reg |= dev->enetaddr[5]; - out32 (EMAC_IAL + hw_p->hw_addr, reg); + out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg); switch (devnum) { case 1: @@ -984,10 +984,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); /* set transmit enable & receive enable */ - out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); + out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); /* set receive fifo to 4k and tx fifo to 2k */ - mode_reg = in32 (EMAC_M1 + hw_p->hw_addr); + mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K; /* set speed */ @@ -1008,39 +1008,39 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) if (duplex == FULL) mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST; - out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); + out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); /* Enable broadcast and indvidual address */ /* TBS: enabling runts as some misbehaved nics will send runts */ - out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); + out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); /* we probably need to set the tx mode1 reg? maybe at tx time */ /* set transmit request threshold register */ - out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ + out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ /* set receive low/high water mark register */ #if defined(CONFIG_440) /* 440s has a 64 byte burst length */ - out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); + out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); #else /* 405s have a 16 byte burst length */ - out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); + out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); #endif /* defined(CONFIG_440) */ - out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); + out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); /* Set fifo limit entry in tx mode 0 */ - out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003); + out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003); /* Frame gap set */ - out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); + out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); /* Set EMAC IER */ hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; if (speed == _100BASET) hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; - out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ - out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); + out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ + out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); if (hw_p->first_init == 0) { /* @@ -1098,8 +1098,8 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, __asm__ volatile ("eieio"); - out32 (EMAC_TXM0 + hw_p->hw_addr, - in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); + out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, + in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); #ifdef INFO_4XX_ENET hw_p->stats.pkts_tx++; #endif @@ -1109,7 +1109,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, *-----------------------------------------------------------------------*/ time_start = get_timer (0); while (1) { - temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr); + temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr); /* loop until either TINT turns on or 3 seconds elapse */ if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) { /* transmit is done, so now check for errors @@ -1218,7 +1218,7 @@ int enetInt (struct eth_device *dev) /* port by port dispatch of emac interrupts */ if (hw_p->devnum == 0) { if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */ - emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); + emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); if ((hw_p->emac_ier & emac_isr) != 0) { emac_err (dev, emac_isr); serviced = 1; @@ -1237,7 +1237,7 @@ int enetInt (struct eth_device *dev) #if !defined(CONFIG_440SP) if (hw_p->devnum == 1) { if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */ - emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); + emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); if ((hw_p->emac_ier & emac_isr) != 0) { emac_err (dev, emac_isr); serviced = 1; @@ -1255,7 +1255,7 @@ int enetInt (struct eth_device *dev) #if defined (CONFIG_440GX) if (hw_p->devnum == 2) { if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */ - emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); + emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); if ((hw_p->emac_ier & emac_isr) != 0) { emac_err (dev, emac_isr); serviced = 1; @@ -1273,7 +1273,7 @@ int enetInt (struct eth_device *dev) if (hw_p->devnum == 3) { if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */ - emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); + emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); if ((hw_p->emac_ier & emac_isr) != 0) { emac_err (dev, emac_isr); serviced = 1; @@ -1385,7 +1385,7 @@ int enetInt (struct eth_device *dev) /* port by port dispatch of emac interrupts */ if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */ - emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); + emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); if ((hw_p->emac_ier & emac_isr) != 0) { emac_err (dev, emac_isr); serviced = 1; @@ -1459,7 +1459,7 @@ static void emac_err (struct eth_device *dev, unsigned long isr) EMAC_4XX_HW_PST hw_p = dev->priv; printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); - out32 (EMAC_ISR + hw_p->hw_addr, isr); + out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr); } /*-----------------------------------------------------------------------------+ diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index 2c675e9be6b..98ba0a7b356 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -44,6 +44,7 @@ #include #include +#include #include #include #include @@ -113,7 +114,7 @@ unsigned int miiphy_getemac_offset (void) unsigned long eoffset; /* Need to find out which mdi port we're using */ - zmii = in32 (ZMII_FER); + zmii = in_be32((void *)ZMII_FER); if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) { /* using port 0 */ @@ -131,12 +132,12 @@ unsigned int miiphy_getemac_offset (void) /* None of the mdi ports are enabled! */ /* enable port 0 */ zmii |= ZMII_FER_MDI << ZMII_FER_V (0); - out32 (ZMII_FER, zmii); + out_be32((void *)ZMII_FER, zmii); eoffset = 0; /* need to soft reset port 0 */ - zmii = in32 (EMAC_M0); + zmii = in_be32((void *)EMAC_M0); zmii |= EMAC_M0_SRST; - out32 (EMAC_M0, zmii); + out_be32((void *)EMAC_M0, zmii); } return (eoffset); @@ -146,7 +147,7 @@ unsigned int miiphy_getemac_offset (void) unsigned long rgmii; int devnum = 1; - rgmii = in32(RGMII_FER); + rgmii = in_be32((void *)RGMII_FER); if (rgmii & (1 << (19 - devnum))) return 0x100; #endif @@ -169,11 +170,11 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, i = 0; /* see if it is ready for sec */ - while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { + while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { udelay (7); if (i > 5) { #ifdef ET_DEBUG - sta_reg = in32 (EMAC_STACR + emac_reg); + sta_reg = in_be32((void *)EMAC_STACR + emac_reg); printf ("read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ printf ("read err 1\n"); #endif @@ -203,12 +204,12 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, #endif sta_reg = sta_reg | (addr << 5); /* Phy address */ sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ - out32 (EMAC_STACR + emac_reg, sta_reg); + out_be32((void *)EMAC_STACR + emac_reg, sta_reg); #ifdef ET_DEBUG printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif - sta_reg = in32 (EMAC_STACR + emac_reg); + sta_reg = in_be32((void *)EMAC_STACR + emac_reg); #ifdef ET_DEBUG printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif @@ -219,7 +220,7 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, return -1; } i++; - sta_reg = in32 (EMAC_STACR + emac_reg); + sta_reg = in_be32((void *)EMAC_STACR + emac_reg); #ifdef ET_DEBUG printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif @@ -250,7 +251,7 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, /* see if it is ready for 1000 nsec */ i = 0; - while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { + while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { if (i > 5) return -1; udelay (7); @@ -281,11 +282,11 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ memcpy (&sta_reg, &value, 2); /* put in data */ - out32 (EMAC_STACR + emac_reg, sta_reg); + out_be32((void *)EMAC_STACR + emac_reg, sta_reg); /* wait for completion */ i = 0; - sta_reg = in32 (EMAC_STACR + emac_reg); + sta_reg = in_be32((void *)EMAC_STACR + emac_reg); #ifdef ET_DEBUG printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif @@ -294,7 +295,7 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, if (i > 5) return -1; i++; - sta_reg = in32 (EMAC_STACR + emac_reg); + sta_reg = in_be32((void *)EMAC_STACR + emac_reg); #ifdef ET_DEBUG printf ("a32: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif -- cgit v1.3.1 From 1338e6a81834099ba19733b69aafd8ef5f098094 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 23 Oct 2007 14:05:08 +0200 Subject: ppc4xx: Change autonegotiation timeout from 4 to 5 seconds I lately noticed, that newer 4xx board with GBit support sometimes don't finish link autonegotiation in 4 seconds. Changing this timeout to 5 seconds seems fine here. Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_enet.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 6ab04e73d5a..697e038d5eb 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -106,7 +106,7 @@ #endif #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */ -#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */ +#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */ /* Ethernet Transmit and Receive Buffers */ /* AS.HARNOIS -- cgit v1.3.1 From 9b94ac61d2176185c30adf0793e079ec30e68687 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 31 Oct 2007 17:55:58 +0100 Subject: ppc4xx: Rework 4xx cache support New cache handling functions added and all existing functions moved from start.S into seperate cache.S. Signed-off-by: Stefan Roese --- cpu/ppc4xx/Makefile | 40 +++++++-- cpu/ppc4xx/cache.S | 233 ++++++++++++++++++++++++++++++++++++++++++++++++ cpu/ppc4xx/kgdb.S | 8 +- cpu/ppc4xx/start.S | 144 +++++------------------------- include/asm-ppc/cache.h | 21 +++-- include/ppc405.h | 6 ++ include/ppc440.h | 6 +- lib_ppc/cache.c | 2 +- 8 files changed, 315 insertions(+), 145 deletions(-) create mode 100644 cpu/ppc4xx/cache.S (limited to 'cpu') diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 194724990de..9155e9a98d1 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -25,14 +25,38 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o resetvec.o kgdb.o -SOBJS = dcr.o -COBJS = 40x_spd_sdram.o 44x_spd_ddr.o 44x_spd_ddr2.o \ - 4xx_enet.o 4xx_pci.o 4xx_pcie.o 4xx_uart.o \ - bedbug_405.o commproc.o cpu.o cpu_init.o \ - fdt.o gpio.o i2c.o interrupts.o iop480_uart.o \ - miiphy.o ndfc.o sdram.o speed.o \ - tlb.o traps.o usb.o usb_ohci.o usbdev.o +START := resetvec.o +START += start.o + +SOBJS := cache.o +SOBJS += dcr.o +SOBJS += kgdb.o + +COBJS := 40x_spd_sdram.o +COBJS += 44x_spd_ddr.o +COBJS += 44x_spd_ddr2.o +COBJS += 4xx_enet.o +COBJS += 4xx_pci.o +COBJS += 4xx_pcie.o +COBJS += 4xx_uart.o +COBJS += bedbug_405.o +COBJS += commproc.o +COBJS += cpu.o +COBJS += cpu_init.o +COBJS += fdt.o +COBJS += gpio.o +COBJS += i2c.o +COBJS += interrupts.o +COBJS += iop480_uart.o +COBJS += miiphy.o +COBJS += ndfc.o +COBJS += sdram.o +COBJS += speed.o +COBJS += tlb.o +COBJS += traps.o +COBJS += usb.o +COBJS += usb_ohci.o +COBJS += usbdev.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/ppc4xx/cache.S b/cpu/ppc4xx/cache.S new file mode 100644 index 00000000000..5124dec77f4 --- /dev/null +++ b/cpu/ppc4xx/cache.S @@ -0,0 +1,233 @@ +/* + * This file contains miscellaneous low-level functions. + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Largely rewritten by Cort Dougan (cort@cs.nmt.edu) + * and Paul Mackerras. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * Flush instruction cache. + */ +_GLOBAL(invalidate_icache) + iccci r0,r0 + isync + blr + +/* + * Write any modified data cache blocks out to memory + * and invalidate the corresponding instruction cache blocks. + * + * flush_icache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(flush_icache_range) + li r5,L1_CACHE_BYTES-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,L1_CACHE_SHIFT + beqlr + mtctr r4 + mr r6,r3 +1: dcbst 0,r3 + addi r3,r3,L1_CACHE_BYTES + bdnz 1b + sync /* wait for dcbst's to get to ram */ + mtctr r4 +2: icbi 0,r6 + addi r6,r6,L1_CACHE_BYTES + bdnz 2b + sync /* additional sync needed on g4 */ + isync + blr + +/* + * Write any modified data cache blocks out to memory. + * Does not invalidate the corresponding cache lines (especially for + * any corresponding instruction cache). + * + * clean_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(clean_dcache_range) + li r5,L1_CACHE_BYTES-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,L1_CACHE_SHIFT + beqlr + mtctr r4 + +1: dcbst 0,r3 + addi r3,r3,L1_CACHE_BYTES + bdnz 1b + sync /* wait for dcbst's to get to ram */ + blr + +/* + * Write any modified data cache blocks out to memory and invalidate them. + * Does not invalidate the corresponding instruction cache blocks. + * + * flush_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(flush_dcache_range) + li r5,L1_CACHE_BYTES-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,L1_CACHE_SHIFT + beqlr + mtctr r4 + +1: dcbf 0,r3 + addi r3,r3,L1_CACHE_BYTES + bdnz 1b + sync /* wait for dcbst's to get to ram */ + blr + +/* + * Like above, but invalidate the D-cache. This is used by the 8xx + * to invalidate the cache so the PPC core doesn't get stale data + * from the CPM (no cache snooping here :-). + * + * invalidate_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(invalidate_dcache_range) + li r5,L1_CACHE_BYTES-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,L1_CACHE_SHIFT + beqlr + mtctr r4 + +1: dcbi 0,r3 + addi r3,r3,L1_CACHE_BYTES + bdnz 1b + sync /* wait for dcbi's to get to ram */ + blr + +/* + * 40x cores have 8K or 16K dcache and 32 byte line size. + * 44x has a 32K dcache and 32 byte line size. + * 8xx has 1, 2, 4, 8K variants. + * For now, cover the worst case of the 44x. + * Must be called with external interrupts disabled. + */ +#define CACHE_NWAYS 64 +#define CACHE_NLINES 32 + +_GLOBAL(flush_dcache) + li r4,(2 * CACHE_NWAYS * CACHE_NLINES) + mtctr r4 + lis r5,0 +1: lwz r3,0(r5) /* Load one word from every line */ + addi r5,r5,L1_CACHE_BYTES + bdnz 1b + sync + blr + +_GLOBAL(invalidate_dcache) + addi r6,0,0x0000 /* clear GPR 6 */ + /* Do loop for # of dcache congruence classes. */ + lis r7,(CFG_DCACHE_SIZE / L1_CACHE_BYTES / 2)@ha /* TBS for large sized cache */ + ori r7,r7,(CFG_DCACHE_SIZE / L1_CACHE_BYTES / 2)@l + /* NOTE: dccci invalidates both */ + mtctr r7 /* ways in the D cache */ +..dcloop: + dccci 0,r6 /* invalidate line */ + addi r6,r6,L1_CACHE_BYTES /* bump to next line */ + bdnz ..dcloop + sync + blr + +/* + * Cache functions. + * + * NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM, + * although for some cache-ralated calls stubs have to be provided to satisfy + * symbols resolution. + * Icache-related functions are used in POST framework. + * + */ +#ifdef CONFIG_440 + + .globl dcache_disable + .globl icache_disable + .globl icache_enable +dcache_disable: +icache_disable: +icache_enable: + blr + + .globl dcache_status + .globl icache_status +dcache_status: +icache_status: + mr r3, 0 + blr + +#else /* CONFIG_440 */ + + .globl icache_enable +icache_enable: + mflr r8 + bl invalidate_icache + mtlr r8 + isync + addis r3,r0, 0xc000 /* set bit 0 */ + mticcr r3 + blr + + .globl icache_disable +icache_disable: + addis r3,r0, 0x0000 /* clear bit 0 */ + mticcr r3 + isync + blr + + .globl icache_status +icache_status: + mficcr r3 + srwi r3, r3, 31 /* >>31 => select bit 0 */ + blr + + .globl dcache_enable +dcache_enable: + mflr r8 + bl invalidate_dcache + mtlr r8 + isync + addis r3,r0, 0x8000 /* set bit 0 */ + mtdccr r3 + blr + + .globl dcache_disable +dcache_disable: + mflr r8 + bl flush_dcache + mtlr r8 + addis r3,r0, 0x0000 /* clear bit 0 */ + mtdccr r3 + blr + + .globl dcache_status +dcache_status: + mfdccr r3 + srwi r3, r3, 31 /* >>31 => select bit 0 */ + blr + +#endif /* CONFIG_440 */ diff --git a/cpu/ppc4xx/kgdb.S b/cpu/ppc4xx/kgdb.S index 8c4bbf2e4de..42b9546d3d2 100644 --- a/cpu/ppc4xx/kgdb.S +++ b/cpu/ppc4xx/kgdb.S @@ -56,21 +56,21 @@ kgdb_flush_cache_all: .globl kgdb_flush_cache_range kgdb_flush_cache_range: - li r5,CFG_CACHELINE_SIZE-1 + li r5,L1_CACHE_BYTES-1 andc r3,r3,r5 subf r4,r3,r4 add r4,r4,r5 - srwi. r4,r4,CFG_CACHELINE_SHIFT + srwi. r4,r4,L1_CACHE_SHIFT beqlr mtctr r4 mr r6,r3 1: dcbst 0,r3 - addi r3,r3,CFG_CACHELINE_SIZE + addi r3,r3,L1_CACHE_BYTES bdnz 1b sync /* wait for dcbst's to get to ram */ mtctr r4 2: icbi 0,r6 - addi r6,r6,CFG_CACHELINE_SIZE + addi r6,r6,L1_CACHE_BYTES bdnz 2b SYNC blr diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 81a15fe922d..f5a135f1a01 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1220,111 +1220,6 @@ mck_return: #endif /* CONFIG_440 */ -/* - * Cache functions. - * - * NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM, - * although for some cache-ralated calls stubs have to be provided to satisfy - * symbols resolution. - * Icache-related functions are used in POST framework. - * - */ -#ifdef CONFIG_440 - .globl dcache_disable - .globl icache_disable - .globl icache_enable -dcache_disable: -icache_disable: -icache_enable: - blr - - .globl dcache_status - .globl icache_status -dcache_status: -icache_status: - mr r3, 0 - blr -#else -flush_dcache: - addis r9,r0,0x0002 /* set mask for EE and CE msr bits */ - ori r9,r9,0x8000 - mfmsr r12 /* save msr */ - andc r9,r12,r9 - mtmsr r9 /* disable EE and CE */ - addi r10,r0,0x0001 /* enable data cache for unused memory */ - mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */ - or r10,r10,r9 /* bit 31 in dccr */ - mtdccr r10 - - /* do loop for # of congruence classes. */ - lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */ - ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l - lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */ - ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */ - mtctr r10 - addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */ - add r11,r10,r11 /* add to get to other side of cache line */ -..flush_dcache_loop: - lwz r3,0(r10) /* least recently used side */ - lwz r3,0(r11) /* the other side */ - dccci r0,r11 /* invalidate both sides */ - addi r10,r10,CFG_CACHELINE_SIZE /* bump to next line */ - addi r11,r11,CFG_CACHELINE_SIZE /* bump to next line */ - bdnz ..flush_dcache_loop - sync /* allow memory access to complete */ - mtdccr r9 /* restore dccr */ - mtmsr r12 /* restore msr */ - blr - - .globl icache_enable -icache_enable: - mflr r8 - bl invalidate_icache - mtlr r8 - isync - addis r3,r0, 0xc000 /* set bit 0 */ - mticcr r3 - blr - - .globl icache_disable -icache_disable: - addis r3,r0, 0x0000 /* clear bit 0 */ - mticcr r3 - isync - blr - - .globl icache_status -icache_status: - mficcr r3 - srwi r3, r3, 31 /* >>31 => select bit 0 */ - blr - - .globl dcache_enable -dcache_enable: - mflr r8 - bl invalidate_dcache - mtlr r8 - isync - addis r3,r0, 0x8000 /* set bit 0 */ - mtdccr r3 - blr - - .globl dcache_disable -dcache_disable: - mflr r8 - bl flush_dcache - mtlr r8 - addis r3,r0, 0x0000 /* clear bit 0 */ - mtdccr r3 - blr - - .globl dcache_status -dcache_status: - mfdccr r3 - srwi r3, r3, 31 /* >>31 => select bit 0 */ - blr -#endif - .globl get_pvr get_pvr: mfspr r3, PVR @@ -1430,6 +1325,26 @@ ppcSync: */ .globl relocate_code relocate_code: +#ifdef CONFIG_4xx_DCACHE + /* + * We need to flush the Init Data before the dcache will be + * invalidated + */ + + /* save regs */ + mr r9,r3 + mr r10,r4 + mr r11,r5 + + mr r3,r4 + addi r4,r4,0x200 /* should be enough for init data */ + bl flush_dcache_range + + /* restore regs */ + mr r3,r9 + mr r4,r10 + mr r5,r11 +#endif #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) @@ -1457,7 +1372,7 @@ relocate_code: ori r4, r4, CFG_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6, L1_CACHE_BYTES /* Cache Line Size */ /* * Fix GOT pointer: @@ -1777,23 +1692,6 @@ in32: lwz 3,0x0000(3) blr -invalidate_icache: - iccci r0,r0 /* for 405, iccci invalidates the */ - blr /* entire I cache */ - -invalidate_dcache: - addi r6,0,0x0000 /* clear GPR 6 */ - /* Do loop for # of dcache congruence classes. */ - lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */ - ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l - /* NOTE: dccci invalidates both */ - mtctr r7 /* ways in the D cache */ -..dcloop: - dccci 0,r6 /* invalidate line */ - addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */ - bdnz ..dcloop - blr - /**************************************************************************/ /* PPC405EP specific stuff */ /**************************************************************************/ diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h index 5befab4d536..e29bfc2a7b4 100644 --- a/include/asm-ppc/cache.h +++ b/include/asm-ppc/cache.h @@ -8,15 +8,24 @@ #include /* bytes per L1 cache line */ -#if !defined(CONFIG_8xx) || defined(CONFIG_8260) +#if !(defined(CONFIG_8xx) || defined(CONFIG_IOP480)) #if defined(CONFIG_PPC64BRIDGE) -#define L1_CACHE_BYTES 128 +#define L1_CACHE_SHIFT 7 #else -#define L1_CACHE_BYTES 32 +#define L1_CACHE_SHIFT 5 #endif /* PPC64 */ #else -#define L1_CACHE_BYTES 16 -#endif /* !8xx || 8260 */ +#define L1_CACHE_SHIFT 4 +#endif /* !(8xx || IOP480) */ + +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +/* + * For compatibility reasons support the CFG_CACHELINE_SIZE too + */ +#ifndef CFG_CACHELINE_SIZE +#define CFG_CACHELINE_SIZE L1_CACHE_BYTES +#endif #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) #define L1_CACHE_PAGES 8 @@ -35,6 +44,8 @@ extern void flush_dcache_range(unsigned long start, unsigned long stop); extern void clean_dcache_range(unsigned long start, unsigned long stop); extern void invalidate_dcache_range(unsigned long start, unsigned long stop); +extern void flush_dcache(void); +extern void invalidate_dcache(void); #ifdef CFG_INIT_RAM_LOCK extern void unlock_ram_in_cache(void); #endif /* CFG_INIT_RAM_LOCK */ diff --git a/include/ppc405.h b/include/ppc405.h index 97528e88a82..2c5591726c3 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -22,6 +22,12 @@ #ifndef __PPC405_H__ #define __PPC405_H__ +#ifndef CONFIG_IOP480 +#define CFG_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */ +#else +#define CFG_DCACHE_SIZE (2 << 10) /* For PLX IOP480 (403) */ +#endif + /*--------------------------------------------------------------------- */ /* Special Purpose Registers */ /*--------------------------------------------------------------------- */ diff --git a/include/ppc440.h b/include/ppc440.h index dc5eb98c909..2f841fa6bc6 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -22,6 +22,8 @@ #ifndef __PPC440_H__ #define __PPC440_H__ +#define CFG_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */ + /*--------------------------------------------------------------------- */ /* Special Purpose Registers */ /*--------------------------------------------------------------------- */ @@ -3282,8 +3284,4 @@ static inline void set_mcsr(u32 val) #endif /* _ASMLANGUAGE */ -#define RESET_VECTOR 0xfffffffc -#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for */ - /* cache line aligned data. */ - #endif /* __PPC440_H__ */ diff --git a/lib_ppc/cache.c b/lib_ppc/cache.c index a81ab5e363f..27e1a823c61 100644 --- a/lib_ppc/cache.c +++ b/lib_ppc/cache.c @@ -22,7 +22,7 @@ */ #include - +#include void flush_cache (ulong start_addr, ulong size) { -- cgit v1.3.1 From 483e09a223c666269ef81d3573a6591b1046b0ef Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 31 Oct 2007 17:59:22 +0100 Subject: ppc4xx: Add change_tlb function to modify I attribute of TLB(s) This function is used to either turn cache on or off in a specific memory area. Signed-off-by: Stefan Roese --- cpu/ppc4xx/tlb.c | 88 ++++++++++++++++++++++++++++++++++++++++++++++++++- include/asm-ppc/mmu.h | 1 + 2 files changed, 88 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/tlb.c b/cpu/ppc4xx/tlb.c index 098694caf49..ed493f1a710 100644 --- a/cpu/ppc4xx/tlb.c +++ b/cpu/ppc4xx/tlb.c @@ -26,6 +26,7 @@ #if defined(CONFIG_440) #include +#include #include #include @@ -42,7 +43,6 @@ void remove_tlb(u32 vaddr, u32 size) u32 tlb_vaddr; u32 tlb_size = 0; - /* First, find the index of a TLB entry not being used */ for (i=0; i= vaddr)) { + /* + * TLB is enabled and start address is lower or equal + * than the area we are looking for. Now we only have + * to check the size/end address for a match. + */ + switch (tlb_word0_value & TLB_WORD0_SIZE_MASK) { + case TLB_WORD0_SIZE_1KB: + tlb_size = 1 << 10; + break; + case TLB_WORD0_SIZE_4KB: + tlb_size = 4 << 10; + break; + case TLB_WORD0_SIZE_16KB: + tlb_size = 16 << 10; + break; + case TLB_WORD0_SIZE_64KB: + tlb_size = 64 << 10; + break; + case TLB_WORD0_SIZE_256KB: + tlb_size = 256 << 10; + break; + case TLB_WORD0_SIZE_1MB: + tlb_size = 1 << 20; + break; + case TLB_WORD0_SIZE_16MB: + tlb_size = 16 << 20; + break; + case TLB_WORD0_SIZE_256MB: + tlb_size = 256 << 20; + break; + } + + /* + * Now check the end-address if it's in the range + */ + if ((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) { + /* + * Found a TLB in the range. + * Change cache attribute in tlb2 word. + */ + tlb_word2_value = + TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE | + TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE | + TLB_WORD2_W_DISABLE | tlb_word2_i_value | + TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE | + TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE | + TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE | + TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE | + TLB_WORD2_SR_ENABLE; + + /* + * Now either flush or invalidate the dcache + */ + if (tlb_word2_i_value) + flush_dcache(); + else + invalidate_dcache(); + + mttlb3(i, tlb_word2_value); + asm("iccci 0,0"); + } + } + } + + /* Execute an ISYNC instruction so that the new TLB entry takes effect */ + asm("isync"); +} + static int add_tlb_entry(unsigned long phys_addr, unsigned long virt_addr, unsigned long tlb_word0_size_value, diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index b3cfa9b3726..edcb3b9ca37 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -648,6 +648,7 @@ unsigned long mftlb3(unsigned long index); void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); void remove_tlb(u32 vaddr, u32 size); +void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_440 */ -- cgit v1.3.1 From ff768cb168d8157c24a25016dbfbeb465e47f420 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 31 Oct 2007 18:01:24 +0100 Subject: ppc4xx: Change 4xx ethernet driver to handle cached memory too This patch enables the 4xx EMAC driver to work too, when dcache is enabled. Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_enet.c | 137 +++++++++++++++++++++++--------------------------- include/ppc4xx_enet.h | 2 + 2 files changed, 64 insertions(+), 75 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 697e038d5eb..c08bf61e480 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -82,6 +82,8 @@ #include #include #include +#include +#include #include #include #include @@ -189,6 +191,10 @@ struct eth_device *emac0_dev = NULL; #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * 2)) #endif +#define MAL_RX_DESC_SIZE 2048 +#define MAL_TX_DESC_SIZE 2048 +#define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE) + /*-----------------------------------------------------------------------------+ * Prototypes and externals. *-----------------------------------------------------------------------------*/ @@ -354,8 +360,8 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) /* Ensure we setup mdio for this devnum and ONLY this devnum */ zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); - out_be32(ZMII_FER, zmiifer); - out_be32(RGMII_FER, rmiifer); + out_be32((void *)ZMII_FER, zmiifer); + out_be32((void *)RGMII_FER, rmiifer); return ((int)pfc1); } @@ -446,9 +452,15 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) } #endif /* CONFIG_405EX */ +static inline void *malloc_aligned(u32 size, u32 align) +{ + return (void *)(((u32)malloc(size + align) + align - 1) & + ~(align - 1)); +} + static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) { - int i, j; + int i; unsigned long reg = 0; unsigned long msr; unsigned long speed; @@ -473,6 +485,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) defined(CONFIG_405EX) unsigned long mfr; #endif + u32 bd_cached; + u32 bd_uncached = 0; EMAC_4XX_HW_PST hw_p = dev->priv; @@ -768,11 +782,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #endif /* Set ZMII/RGMII speed according to the phy link speed */ - reg = in_be32(ZMII_SSR); + reg = in_be32((void *)ZMII_SSR); if ( (speed == 100) || (speed == 1000) ) - out_be32(ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); + out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); else - out_be32(ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); + out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); if ((devnum == 2) || (devnum == 3)) { if (speed == 1000) @@ -785,7 +799,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) printf("Error in RGMII Speed\n"); return -1; } - out_be32(RGMII_SSR, reg); + out_be32((void *)RGMII_SSR, reg); } #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ @@ -819,91 +833,60 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) } #endif - /* Free "old" buffers */ - if (hw_p->alloc_tx_buf) - free (hw_p->alloc_tx_buf); - if (hw_p->alloc_rx_buf) - free (hw_p->alloc_rx_buf); - /* * Malloc MAL buffer desciptors, make sure they are * aligned on cache line boundary size * (401/403/IOP480 = 16, 405 = 32) * and doesn't cross cache block boundaries. */ - hw_p->alloc_tx_buf = - (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) + - ((2 * CFG_CACHELINE_SIZE) - 2)); - if (NULL == hw_p->alloc_tx_buf) - return -1; - if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) { - hw_p->tx = - (mal_desc_t *) ((int) hw_p->alloc_tx_buf + - CFG_CACHELINE_SIZE - - ((int) hw_p-> - alloc_tx_buf & CACHELINE_MASK)); - } else { - hw_p->tx = hw_p->alloc_tx_buf; - } + if (hw_p->first_init == 0) { + debug("*** Allocating descriptor memory ***\n"); - hw_p->alloc_rx_buf = - (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) + - ((2 * CFG_CACHELINE_SIZE) - 2)); - if (NULL == hw_p->alloc_rx_buf) { - free(hw_p->alloc_tx_buf); - hw_p->alloc_tx_buf = NULL; - return -1; - } + bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096); + if (!bd_cached) { + printf("%s: Error allocating MAL descriptor buffers!\n"); + return -1; + } - if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) { - hw_p->rx = - (mal_desc_t *) ((int) hw_p->alloc_rx_buf + - CFG_CACHELINE_SIZE - - ((int) hw_p-> - alloc_rx_buf & CACHELINE_MASK)); - } else { - hw_p->rx = hw_p->alloc_rx_buf; +#ifdef CONFIG_4xx_DCACHE + flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE); + hw_p->tx_phys = bd_cached; + hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE; + bd_uncached = bis->bi_memsize; + program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE, + TLB_WORD2_I_ENABLE); +#else + bd_uncached = bd_cached; +#endif + hw_p->tx_phys = bd_cached; + hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE; + hw_p->tx = (mal_desc_t *)(bd_uncached); + hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE); + debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx); } for (i = 0; i < NUM_TX_BUFF; i++) { hw_p->tx[i].ctrl = 0; hw_p->tx[i].data_len = 0; - if (hw_p->first_init == 0) { - hw_p->txbuf_ptr = - (char *) malloc (ENET_MAX_MTU_ALIGNED); - if (NULL == hw_p->txbuf_ptr) { - free(hw_p->alloc_rx_buf); - free(hw_p->alloc_tx_buf); - hw_p->alloc_rx_buf = NULL; - hw_p->alloc_tx_buf = NULL; - for(j = 0; j < i; j++) { - free(hw_p->tx[i].data_ptr); - hw_p->tx[i].data_ptr = NULL; - } - } - } + if (hw_p->first_init == 0) + hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE, + L1_CACHE_BYTES); hw_p->tx[i].data_ptr = hw_p->txbuf_ptr; if ((NUM_TX_BUFF - 1) == i) hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP; hw_p->tx_run[i] = -1; -#if 0 - printf ("TX_BUFF %d @ 0x%08lx\n", i, - (ulong) hw_p->tx[i].data_ptr); -#endif + debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr); } for (i = 0; i < NUM_RX_BUFF; i++) { hw_p->rx[i].ctrl = 0; hw_p->rx[i].data_len = 0; - /* rx[i].data_ptr = (char *) &rx_buff[i]; */ - hw_p->rx[i].data_ptr = (char *) NetRxPackets[i]; + hw_p->rx[i].data_ptr = (char *)NetRxPackets[i]; if ((NUM_RX_BUFF - 1) == i) hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP; hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR; hw_p->rx_ready[i] = -1; -#if 0 - printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) hw_p->rx[i].data_ptr); -#endif + debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr); } reg = 0x00000000; @@ -929,15 +912,15 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) case 1: /* setup MAL tx & rx channel pointers */ #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) - mtdcr (maltxctp2r, hw_p->tx); + mtdcr (maltxctp2r, hw_p->tx_phys); #else - mtdcr (maltxctp1r, hw_p->tx); + mtdcr (maltxctp1r, hw_p->tx_phys); #endif #if defined(CONFIG_440) mtdcr (maltxbattr, 0x0); mtdcr (malrxbattr, 0x0); #endif - mtdcr (malrxctp1r, hw_p->rx); + mtdcr (malrxctp1r, hw_p->rx_phys); /* set RX buffer size */ mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16); break; @@ -946,17 +929,17 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* setup MAL tx & rx channel pointers */ mtdcr (maltxbattr, 0x0); mtdcr (malrxbattr, 0x0); - mtdcr (maltxctp2r, hw_p->tx); - mtdcr (malrxctp2r, hw_p->rx); + mtdcr (maltxctp2r, hw_p->tx_phys); + mtdcr (malrxctp2r, hw_p->rx_phys); /* set RX buffer size */ mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16); break; case 3: /* setup MAL tx & rx channel pointers */ mtdcr (maltxbattr, 0x0); - mtdcr (maltxctp3r, hw_p->tx); + mtdcr (maltxctp3r, hw_p->tx_phys); mtdcr (malrxbattr, 0x0); - mtdcr (malrxctp3r, hw_p->rx); + mtdcr (malrxctp3r, hw_p->rx_phys); /* set RX buffer size */ mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16); break; @@ -968,8 +951,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) mtdcr (maltxbattr, 0x0); mtdcr (malrxbattr, 0x0); #endif - mtdcr (maltxctp0r, hw_p->tx); - mtdcr (malrxctp0r, hw_p->rx); + mtdcr (maltxctp0r, hw_p->tx_phys); + mtdcr (malrxctp0r, hw_p->rx_phys); /* set RX buffer size */ mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16); break; @@ -1083,6 +1066,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */ memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len); + flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len); /*-----------------------------------------------------------------------+ * set TX Buffer busy, and send it @@ -1582,6 +1566,9 @@ static int ppc_4xx_eth_rx (struct eth_device *dev) /* Pass the packet up to the protocol layers. */ /* NetReceive(NetRxPackets[rxIdx], length - 4); */ /* NetReceive(NetRxPackets[i], length); */ + invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr, + (u32)hw_p->rx[user_index].data_ptr + + length - 4); NetReceive (NetRxPackets[user_index], length - 4); /* Free Recv Buffer */ hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY; diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h index 76c1d127efb..f2855007391 100644 --- a/include/ppc4xx_enet.h +++ b/include/ppc4xx_enet.h @@ -102,6 +102,8 @@ typedef struct emac_4xx_hw_st { uint32_t emac_ier; volatile mal_desc_t *tx; volatile mal_desc_t *rx; + u32 tx_phys; + u32 rx_phys; bd_t *bis; /* for eth_init upon mal error */ mal_desc_t *alloc_tx_buf; mal_desc_t *alloc_rx_buf; -- cgit v1.3.1 From ea2e142843533ca593fcb5cb3e1daf1b7f5e5949 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 31 Oct 2007 20:57:11 +0100 Subject: ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAM This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files and to the Sequoia TLB init code. Now the cache can be enabled on 44x boards by defining CONFIG_4xx_DCACHE in the board config file. This option will disappear, when more boards use is successfully and no more known problems exist. This is tested successfully on Sequoia and Katmai. The only problem that needs to be fixed is, that USB is not working on Sequoia right now, since it will need some cache handling code too, similar to the 4xx EMAC driver. Signed-off-by: Stefan Roese --- board/amcc/sequoia/init.S | 4 ++++ cpu/ppc4xx/44x_spd_ddr.c | 9 +++------ cpu/ppc4xx/44x_spd_ddr2.c | 4 ++-- 3 files changed, 9 insertions(+), 8 deletions(-) (limited to 'cpu') diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index 5fe3af9a092..c7da5216dc8 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -98,7 +98,11 @@ tlbtab: #endif /* TLB-entry for DDR SDRAM (Up to 2GB) */ +#ifdef CONFIG_4xx_DCACHE + tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G) +#else tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) +#endif #ifdef CFG_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index 65ce46daf34..b9cf5cbfcca 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -251,10 +251,10 @@ void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")) * memory. * * If at some time this restriction doesn't apply anymore, just define - * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup + * CONFIG_4xx_DCACHE in the board config file and this code should setup * everything correctly. */ -#ifdef CFG_ENABLE_SDRAM_CACHE +#ifdef CONFIG_4xx_DCACHE #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ #else #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ @@ -345,7 +345,7 @@ long int spd_sdram(void) { */ check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) /* * Soft-reset SDRAM controller. */ @@ -1197,9 +1197,6 @@ static void program_tr1(void) } rdclt_average = ((max_start + max_end) >> 1); - if (rdclt_average >= 0x60) - while (1) - ; if (rdclt_average < 0) { rdclt_average = 0; diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index b3413671b51..e19929437e2 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -120,10 +120,10 @@ * memory. * * If at some time this restriction doesn't apply anymore, just define - * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup + * CONFIG_4xx_DCACHE in the board config file and this code should setup * everything correctly. */ -#ifdef CFG_ENABLE_SDRAM_CACHE +#ifdef CONFIG_4xx_DCACHE #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ #else #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ -- cgit v1.3.1 From c7f69c340277935a6c19a956421852da944a365f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 9 Nov 2007 12:18:54 +0100 Subject: ppc4xx: Make output a little shorter on I2C bootrom detection Most 4xx PPC capable of using an I2C bootrom for bootstrap setting already print a line with the information which I2C bootrom is used for bootstrap configuration. So we don't need this extra line with "I2C boot EEPROM en-/dis-abled". This patch also has a little code cleanup integrated. Signed-off-by: Stefan Roese --- cpu/ppc4xx/cpu.c | 53 +++++++++++++++++++---------------------------------- 1 file changed, 19 insertions(+), 34 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 7addb9251f5..d376f52a608 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -37,13 +37,9 @@ #include #include -#if !defined(CONFIG_405) DECLARE_GLOBAL_DATA_PTR; -#endif -#if defined(CONFIG_BOARD_RESET) void board_reset(void); -#endif #if defined(CONFIG_405GP) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ @@ -51,7 +47,7 @@ void board_reset(void); #define PCI_ASYNC -int pci_async_enabled(void) +static int pci_async_enabled(void) { #if defined(CONFIG_405GP) return (mfdcr(strap) & PSR_PCI_ASYNC_EN); @@ -69,7 +65,7 @@ int pci_async_enabled(void) #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \ !defined(CONFIG_405) && !defined(CONFIG_405EX) -int pci_arbiter_enabled(void) +static int pci_arbiter_enabled(void) { #if defined(CONFIG_405GP) return (mfdcr(strap) & PSR_PCI_ARBIT_EN); @@ -99,15 +95,10 @@ int pci_arbiter_enabled(void) } #endif -#if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_405EX) - +#if defined(CONFIG_405EP) #define I2C_BOOTROM -int i2c_bootrom_enabled(void) +static int i2c_bootrom_enabled(void) { #if defined(CONFIG_405EP) return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP); @@ -227,7 +218,19 @@ static int bootstrap_option(void) #if defined(CONFIG_440) -static int do_chip_reset(unsigned long sys0, unsigned long sys1); +static int do_chip_reset (unsigned long sys0, unsigned long sys1) +{ + /* Changes to cpc0_sys0 and cpc0_sys1 require chip + * reset. + */ + mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */ + mtdcr (cpc0_sys0, sys0); + mtdcr (cpc0_sys1, sys1); + mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */ + mtspr (dbcr0, 0x20000000); /* Reset the chip */ + + return 1; +} #endif @@ -539,22 +542,6 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } -#if defined(CONFIG_440) -static int do_chip_reset (unsigned long sys0, unsigned long sys1) -{ - /* Changes to cpc0_sys0 and cpc0_sys1 require chip - * reset. - */ - mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */ - mtdcr (cpc0_sys0, sys0); - mtdcr (cpc0_sys1, sys1); - mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */ - mtspr (dbcr0, 0x20000000); /* Reset the chip */ - - return 1; -} -#endif - /* * Get timebase clock frequency @@ -574,16 +561,14 @@ unsigned long get_tbclk (void) #if defined(CONFIG_WATCHDOG) -void -watchdog_reset(void) +void watchdog_reset(void) { int re_enable = disable_interrupts(); reset_4xx_watchdog(); if (re_enable) enable_interrupts(); } -void -reset_4xx_watchdog(void) +void reset_4xx_watchdog(void) { /* * Clear TSR(WIS) bit -- cgit v1.3.1 From fbde2169d2c48fcc9ff03489534a78ffb0a8a0d4 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 9 Nov 2007 15:36:44 +0100 Subject: ppc4xx: Remove redundant code from 4xx network driver This patch removes some redundant code and decrements the end address of cache flush and invalidate by 1. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_enet.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index c08bf61e480..c20dc730ef0 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -849,9 +849,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) } #ifdef CONFIG_4xx_DCACHE - flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE); - hw_p->tx_phys = bd_cached; - hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE; + flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE - 1); bd_uncached = bis->bi_memsize; program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE, TLB_WORD2_I_ENABLE); @@ -1066,7 +1064,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */ memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len); - flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len); + flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len - 1); /*-----------------------------------------------------------------------+ * set TX Buffer busy, and send it @@ -1568,7 +1566,7 @@ static int ppc_4xx_eth_rx (struct eth_device *dev) /* NetReceive(NetRxPackets[i], length); */ invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr, (u32)hw_p->rx[user_index].data_ptr + - length - 4); + length - 4 - 1); NetReceive (NetRxPackets[user_index], length - 4); /* Free Recv Buffer */ hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY; -- cgit v1.3.1 From 9be659ac0868dc367caa957c5c725e46b07f6a5f Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 9 Nov 2007 15:37:23 +0100 Subject: ppc4xx: Make USB working with CONFIG_4xx_DCACHE defined This patch disables the 44x d-cache on 'usb start' and reenables it on 'usb stop'. This should be seen as a temporary fix until the generic usb-ohci driver can life with d-cache enabled. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- cpu/ppc4xx/usb.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/usb.c b/cpu/ppc4xx/usb.c index 272ed8c15e4..cb8d5c7d30f 100644 --- a/cpu/ppc4xx/usb.c +++ b/cpu/ppc4xx/usb.c @@ -25,25 +25,41 @@ #if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) +#ifdef CONFIG_4xx_DCACHE +#include +DECLARE_GLOBAL_DATA_PTR; +#endif + #include "usbdev.h" int usb_cpu_init(void) { +#ifdef CONFIG_4xx_DCACHE + /* disable cache */ + change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE); +#endif #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) usb_dev_init(); #endif - return 0; } int usb_cpu_stop(void) { +#ifdef CONFIG_4xx_DCACHE + /* enable cache */ + change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0); +#endif return 0; } int usb_cpu_init_fail(void) { +#ifdef CONFIG_4xx_DCACHE + /* enable cache */ + change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0); +#endif return 0; } -- cgit v1.3.1 From 7d0a4066b5a6b698e5fc1b66cfe9705774bbce93 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 13 Nov 2007 08:06:11 +0100 Subject: ppc4xx: Fix 405EX PCIe UTLSET register setup Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_pcie.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index da179f9c3a8..de7955280e0 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -480,8 +480,8 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport) val = 0x00101000; SDR_WRITE(SDRN_PESDR_DLPSET(port), val); - SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x20222222); - SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01110000); + SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000); + SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000); SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000); SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003); -- cgit v1.3.1 From aee747f19b460a0e9da20ff21e90fdaac1cec359 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 15 Nov 2007 14:23:55 +0100 Subject: ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platforms - Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE - Cleanup of the 4xx GPIO functions - Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h Signed-off-by: Stefan Roese --- cpu/ppc4xx/cpu_init.c | 6 +- cpu/ppc4xx/gpio.c | 134 ++++++++++++++++++++------------------------- include/asm-ppc/gpio.h | 35 ++++++++++++ include/configs/lwmon5.h | 2 +- include/configs/pcs440ep.h | 2 +- include/ppc405.h | 2 + include/ppc440.h | 28 ---------- 7 files changed, 101 insertions(+), 108 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index afb94cc0700..01ab523c512 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -112,7 +112,7 @@ cpu_init_f (void) unsigned long val; #endif -#if defined(CONFIG_405EP) || defined (CONFIG_405EX) +#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE) /* * GPIO0 setup (select GPIO or alternate function) */ @@ -144,9 +144,9 @@ cpu_init_f (void) #endif /* CONFIG_405EP */ #endif /* CONFIG_405EP */ -#if defined(CFG_440_GPIO_TABLE) +#if defined(CFG_4xx_GPIO_TABLE) gpio_set_chip_configuration(); -#endif /* CFG_440_GPIO_TABLE */ +#endif /* CFG_4xx_GPIO_TABLE */ /* * External Bus Controller (EBC) Setup diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c index 50f2fdf1139..dcf1fba8384 100644 --- a/cpu/ppc4xx/gpio.c +++ b/cpu/ppc4xx/gpio.c @@ -26,8 +26,8 @@ #include #include -#if defined(CFG_440_GPIO_TABLE) -gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE; +#if defined(CFG_4xx_GPIO_TABLE) +gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_4xx_GPIO_TABLE; #endif #if defined(GPIO0_OSRL) @@ -55,10 +55,10 @@ void gpio_config(int pin, int in_out, int gpio_alt, int out_val) mask2 = 0xc0000000 >> (pin2 << 1); /* first set TCR to 0 */ - out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) & ~mask); + out_be32((void *)GPIO0_TCR + offs, in_be32((void *)GPIO0_TCR + offs) & ~mask); if (in_out == GPIO_OUT) { - val = in32(GPIO0_OSRL + offs + offs2) & ~mask2; + val = in_be32((void *)GPIO0_OSRL + offs + offs2) & ~mask2; switch (gpio_alt) { case GPIO_ALT1: val |= GPIO_ALT1_SEL >> pin2; @@ -70,20 +70,23 @@ void gpio_config(int pin, int in_out, int gpio_alt, int out_val) val |= GPIO_ALT3_SEL >> pin2; break; } - out32(GPIO0_OSRL + offs + offs2, val); + out_be32((void *)GPIO0_OSRL + offs + offs2, val); /* setup requested output value */ if (out_val == GPIO_OUT_0) - out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~mask); + out_be32((void *)GPIO0_OR + offs, + in_be32((void *)GPIO0_OR + offs) & ~mask); else if (out_val == GPIO_OUT_1) - out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | mask); + out_be32((void *)GPIO0_OR + offs, + in_be32((void *)GPIO0_OR + offs) | mask); /* now configure TCR to drive output if selected */ - out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) | mask); + out_be32((void *)GPIO0_TCR + offs, + in_be32((void *)GPIO0_TCR + offs) | mask); } else { - val = in32(GPIO0_ISR1L + offs + offs2) & ~mask2; + val = in_be32((void *)GPIO0_ISR1L + offs + offs2) & ~mask2; val |= GPIO_IN_SEL >> pin2; - out32(GPIO0_ISR1L + offs + offs2, val); + out_be32((void *)GPIO0_ISR1L + offs + offs2, val); } } #endif /* GPIO_OSRL */ @@ -98,9 +101,11 @@ void gpio_write_bit(int pin, int val) } if (val) - out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | GPIO_VAL(pin)); + out_be32((void *)GPIO0_OR + offs, + in_be32((void *)GPIO0_OR + offs) | GPIO_VAL(pin)); else - out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~GPIO_VAL(pin)); + out_be32((void *)GPIO0_OR + offs, + in_be32((void *)GPIO0_OR + offs) & ~GPIO_VAL(pin)); } int gpio_read_out_bit(int pin) @@ -112,10 +117,10 @@ int gpio_read_out_bit(int pin) pin -= GPIO_MAX; } - return (in32(GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0); + return (in_be32((void *)GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0); } -#if defined(CFG_440_GPIO_TABLE) +#if defined(CFG_4xx_GPIO_TABLE) void gpio_set_chip_configuration(void) { unsigned char i=0, j=0, offs=0, gpio_core; @@ -141,24 +146,24 @@ void gpio_set_chip_configuration(void) break; case GPIO_ALT1: - reg = in32(GPIO_IS1(core_add+offs)) + reg = in_be32((void *)GPIO_IS1(core_add+offs)) & ~(GPIO_MASK >> (j*2)); reg = reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS1(core_add+offs), reg); + out_be32((void *)GPIO_IS1(core_add+offs), reg); break; case GPIO_ALT2: - reg = in32(GPIO_IS2(core_add+offs)) + reg = in_be32((void *)GPIO_IS2(core_add+offs)) & ~(GPIO_MASK >> (j*2)); reg = reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS2(core_add+offs), reg); + out_be32((void *)GPIO_IS2(core_add+offs), reg); break; case GPIO_ALT3: - reg = in32(GPIO_IS3(core_add+offs)) + reg = in_be32((void *)GPIO_IS3(core_add+offs)) & ~(GPIO_MASK >> (j*2)); reg = reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS3(core_add+offs), reg); + out_be32((void *)GPIO_IS3(core_add+offs), reg); break; } } @@ -168,87 +173,66 @@ void gpio_set_chip_configuration(void) switch (gpio_tab[gpio_core][i].alt_nb) { case GPIO_SEL: - if (gpio_core == GPIO0) { - /* - * Setup output value - * 1 -> high level - * 0 -> low level - * else -> don't touch - */ - reg = in32(GPIO0_OR); - if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) - reg |= (0x80000000 >> (i)); - else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0) - reg &= ~(0x80000000 >> (i)); - out32(GPIO0_OR, reg); - - reg = in32(GPIO0_TCR) | (0x80000000 >> (i)); - out32(GPIO0_TCR, reg); - } - -#ifdef GPIO1 - if (gpio_core == GPIO1) { - /* - * Setup output value - * 1 -> high level - * 0 -> low level - * else -> don't touch - */ - reg = in32(GPIO1_OR); - if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) - reg |= (0x80000000 >> (i)); - else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0) - reg &= ~(0x80000000 >> (i)); - out32(GPIO1_OR, reg); - - reg = in32(GPIO1_TCR) | (0x80000000 >> (i)); - out32(GPIO1_TCR, reg); - } -#endif /* GPIO1 */ - - reg = in32(GPIO_OS(core_add+offs)) + /* + * Setup output value + * 1 -> high level + * 0 -> low level + * else -> don't touch + */ + reg = in_be32((void *)GPIO_OR(core_add)); + if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) + reg |= (0x80000000 >> (i)); + else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0) + reg &= ~(0x80000000 >> (i)); + out_be32((void *)GPIO_OR(core_add), reg); + + reg = in_be32((void *)GPIO_TCR(core_add)) | + (0x80000000 >> (i)); + out_be32((void *)GPIO_TCR(core_add), reg); + + reg = in_be32((void *)GPIO_OS(core_add+offs)) & ~(GPIO_MASK >> (j*2)); - out32(GPIO_OS(core_add+offs), reg); - reg = in32(GPIO_TS(core_add+offs)) + out_be32((void *)GPIO_OS(core_add+offs), reg); + reg = in_be32((void *)GPIO_TS(core_add+offs)) & ~(GPIO_MASK >> (j*2)); - out32(GPIO_TS(core_add+offs), reg); + out_be32((void *)GPIO_TS(core_add+offs), reg); break; case GPIO_ALT1: - reg = in32(GPIO_OS(core_add+offs)) + reg = in_be32((void *)GPIO_OS(core_add+offs)) & ~(GPIO_MASK >> (j*2)); reg = reg | (GPIO_ALT1_SEL >> (j*2)); - out32(GPIO_OS(core_add+offs), reg); - reg = in32(GPIO_TS(core_add+offs)) + out_be32((void *)GPIO_OS(core_add+offs), reg); + reg = in_be32((void *)GPIO_TS(core_add+offs)) & ~(GPIO_MASK >> (j*2)); reg = reg | (GPIO_ALT1_SEL >> (j*2)); - out32(GPIO_TS(core_add+offs), reg); + out_be32((void *)GPIO_TS(core_add+offs), reg); break; case GPIO_ALT2: - reg = in32(GPIO_OS(core_add+offs)) + reg = in_be32((void *)GPIO_OS(core_add+offs)) & ~(GPIO_MASK >> (j*2)); reg = reg | (GPIO_ALT2_SEL >> (j*2)); - out32(GPIO_OS(core_add+offs), reg); - reg = in32(GPIO_TS(core_add+offs)) + out_be32((void *)GPIO_OS(core_add+offs), reg); + reg = in_be32((void *)GPIO_TS(core_add+offs)) & ~(GPIO_MASK >> (j*2)); reg = reg | (GPIO_ALT2_SEL >> (j*2)); - out32(GPIO_TS(core_add+offs), reg); + out_be32((void *)GPIO_TS(core_add+offs), reg); break; case GPIO_ALT3: - reg = in32(GPIO_OS(core_add+offs)) + reg = in_be32((void *)GPIO_OS(core_add+offs)) & ~(GPIO_MASK >> (j*2)); reg = reg | (GPIO_ALT3_SEL >> (j*2)); - out32(GPIO_OS(core_add+offs), reg); - reg = in32(GPIO_TS(core_add+offs)) + out_be32((void *)GPIO_OS(core_add+offs), reg); + reg = in_be32((void *)GPIO_TS(core_add+offs)) & ~(GPIO_MASK >> (j*2)); reg = reg | (GPIO_ALT3_SEL >> (j*2)); - out32(GPIO_TS(core_add+offs), reg); + out_be32((void *)GPIO_TS(core_add+offs), reg); break; } } } } } -#endif /* CFG_440_GPIO_TABLE */ +#endif /* CFG_4xx_GPIO_TABLE */ diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h index c9b6a36b4f9..d0c3eba8846 100644 --- a/include/asm-ppc/gpio.h +++ b/include/asm-ppc/gpio.h @@ -21,6 +21,9 @@ * MA 02111-1307 USA */ +#ifndef __ASM_PPC_GPIO_H +#define __ASM_PPC_GPIO_H + /* 4xx PPC's have 2 GPIO controllers */ #if defined(CONFIG_405EZ) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ @@ -30,6 +33,36 @@ #define GPIO_GROUP_MAX 1 #endif +/* Offsets */ +#define GPIOx_OR 0x00 /* GPIO Output Register */ +#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ +#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */ +#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */ +#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */ +#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */ +#define GPIOx_ODR 0x18 /* GPIO Open drain Register */ +#define GPIOx_IR 0x1C /* GPIO Input Register */ +#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */ +#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */ +#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */ +#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */ +#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */ +#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */ +#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */ +#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */ +#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */ + +#define GPIO_OR(x) (x+GPIOx_OR) /* GPIO Output Register */ +#define GPIO_TCR(x) (x+GPIOx_TCR) /* GPIO Three-State Control Register */ +#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Select Register High or Low */ +#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */ +#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */ +#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */ +#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */ + +#define GPIO0 0 +#define GPIO1 1 + #define GPIO_MAX 32 #define GPIO_ALT1_SEL 0x40000000 #define GPIO_ALT2_SEL 0x80000000 @@ -56,3 +89,5 @@ void gpio_config(int pin, int in_out, int gpio_alt, int out_val); void gpio_write_bit(int pin, int val); int gpio_read_out_bit(int pin); void gpio_set_chip_configuration(void); + +#endif /* __ASM_PPC_GPIO_H */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 3180617b1e0..9cb483d3ca7 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -414,7 +414,7 @@ /*----------------------------------------------------------------------- * PPC440 GPIO Configuration */ -#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ +#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ { \ /* GPIO Core 0 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index d467338e920..d66f4bd449b 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -365,7 +365,7 @@ /*----------------------------------------------------------------------- * PPC440 GPIO Configuration */ -#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ +#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ { \ /* GPIO Core 0 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ diff --git a/include/ppc405.h b/include/ppc405.h index 2c5591726c3..e5051d45956 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -1135,6 +1135,8 @@ #endif /* CONFIG_405EZ */ +#define GPIO0_BASE GPIO_BASE + #if defined(CONFIG_405EX) #define SDR0_SRST 0x0200 diff --git a/include/ppc440.h b/include/ppc440.h index 2f841fa6bc6..dfa3d2a6100 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -3187,9 +3187,6 @@ /****************************************************************************** * GPIO macro register defines ******************************************************************************/ -#define GPIO0 0 -#define GPIO1 1 - #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700) @@ -3205,31 +3202,6 @@ #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00) #define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00) -/* Offsets */ -#define GPIOx_OR 0x00 /* GPIO Output Register */ -#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ -#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */ -#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */ -#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */ -#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */ -#define GPIOx_ODR 0x18 /* GPIO Open drain Register */ -#define GPIOx_IR 0x1C /* GPIO Input Register */ -#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */ -#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */ -#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */ -#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */ -#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */ -#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */ -#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */ -#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */ -#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */ - -#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */ -#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */ -#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */ -#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */ -#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */ - #define GPIO0_OR (GPIO0_BASE+0x0) #define GPIO0_TCR (GPIO0_BASE+0x4) #define GPIO0_OSRL (GPIO0_BASE+0x8) -- cgit v1.3.1 From f31d38b9eea9b32f6a1ac848a298cc71ca4c9a03 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 16 Nov 2007 14:16:54 +0100 Subject: ppc4xx: Enable 405EX PCIe UTL register configuration Till now the UTL registers on 405EX were not initialized but left with their default values. This patch new initializes some of the UTL registers on 405EX. Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_pcie.c | 44 ++++++++++++++++++++++++++++++++++++++++++-- cpu/ppc4xx/cpu.c | 2 -- include/asm-ppc/4xx_pcie.h | 2 ++ include/common.h | 2 +- 4 files changed, 45 insertions(+), 5 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index de7955280e0..cafd9338900 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -401,6 +401,48 @@ int ppc4xx_init_pcie(void) return 0; } #else +static void ppc4xx_setup_utl(u32 port) +{ + u32 utl_base; + + /* + * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK + */ + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000); + mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE); + mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0xfffffc01); /* 4k region, valid */ + mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0); + break; + + case 1: + mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000); + mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE); + mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0xfffffc01); /* 4k region, valid */ + mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0); + + break; + } + utl_base = (port==0) ? CFG_PCIE0_UTLBASE : CFG_PCIE1_UTLBASE; + + /* + * Set buffer allocations and then assert VRB and TXE. + */ + out_be32((u32 *)(utl_base + PEUTL_OUTTR), 0x02000000); + out_be32((u32 *)(utl_base + PEUTL_INTR), 0x02000000); + out_be32((u32 *)(utl_base + PEUTL_OPDBSZ), 0x04000000); + out_be32((u32 *)(utl_base + PEUTL_PBBSZ), 0x21000000); + out_be32((u32 *)(utl_base + PEUTL_IPHBSZ), 0x02000000); + out_be32((u32 *)(utl_base + PEUTL_IPDBSZ), 0x04000000); + out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000); + out_be32((u32 *)(utl_base + PEUTL_PCTL), 0x80800066); + + out_be32((u32 *)(utl_base + PEUTL_PBCTL), 0x0800000c); + out_be32((u32 *)(utl_base + PEUTL_RCSTA), + in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000); +} + int ppc4xx_init_pcie(void) { /* @@ -643,14 +685,12 @@ int ppc4xx_init_pcie_port(int port, int rootport) return -1; } -#if defined(CONFIG_440SPE) /* * Setup UTL registers - but only on revA! * We use default settings for revB chip. */ if (!ppc440spe_revB()) ppc4xx_setup_utl(port); -#endif /* * We map PCI Express configuration access into the 512MB regions diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index d376f52a608..9e9c685afe3 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -510,7 +510,6 @@ int checkcpu (void) return 0; } -#if defined (CONFIG_440SPE) int ppc440spe_revB() { unsigned int pvr; @@ -520,7 +519,6 @@ int ppc440spe_revB() { else return 0; } -#endif /* ------------------------------------------------------------------------- */ diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index ffe07706a31..4c03b050fef 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -203,6 +203,7 @@ /* * UTL register offsets */ +#define PEUTL_PBCTL 0x00 #define PEUTL_PBBSZ 0x20 #define PEUTL_OPDBSZ 0x68 #define PEUTL_IPHBSZ 0x70 @@ -210,6 +211,7 @@ #define PEUTL_OUTTR 0x90 #define PEUTL_INTR 0x98 #define PEUTL_PCTL 0xa0 +#define PEUTL_RCSTA 0xb0 #define PEUTL_RCIRQEN 0xb8 /* diff --git a/include/common.h b/include/common.h index 46ed6bd97b3..77aed1a318d 100644 --- a/include/common.h +++ b/include/common.h @@ -516,10 +516,10 @@ void get_sys_info ( sys_info_t * ); # if defined(CONFIG_440SPE) unsigned long determine_sysper(void); unsigned long determine_pci_clock_per(void); - int ppc440spe_revB(void); # endif # endif typedef PPC4xx_SYS_INFO sys_info_t; +int ppc440spe_revB(void); void get_sys_info ( sys_info_t * ); #endif -- cgit v1.3.1 From 653811a3c2b35856bf12e196dcc8c4694e28e420 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sun, 18 Nov 2007 14:44:44 +0100 Subject: ppc4xx: Correct 405EX PCIe UTL register mapping Map 4k mem space for UTL registers for each port. Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_pcie.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index cafd9338900..3af9862bfff 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -412,14 +412,14 @@ static void ppc4xx_setup_utl(u32 port) case 0: mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000); mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE); - mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0xfffffc01); /* 4k region, valid */ + mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */ mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0); break; case 1: mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000); mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE); - mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0xfffffc01); /* 4k region, valid */ + mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */ mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0); break; @@ -554,7 +554,7 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport) #endif /* CONFIG_405EX */ int ppc4xx_init_pcie_port_hw(int port, int rootport) - __attribute__((weak, alias("__ppc4xx_init_pcie_port_hw"))); +__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw"))); /* * We map PCI Express configuration access into the 512MB regions -- cgit v1.3.1 From 246d4ae6bc282bc1841224e1c5fc49dc925e0bf7 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 27 Nov 2007 21:59:46 -0600 Subject: Convert boards that set memory node to use fdt_fixup_memory() Signed-off-by: Kumar Gala --- board/cm5200/cm5200.c | 15 ++------------- board/ids8247/ids8247.c | 17 +++-------------- cpu/mpc83xx/cpu.c | 18 ++---------------- 3 files changed, 7 insertions(+), 43 deletions(-) (limited to 'cpu') diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c index 4a86d3c5527..79fb71dc704 100644 --- a/board/cm5200/cm5200.c +++ b/board/cm5200/cm5200.c @@ -263,7 +263,6 @@ static void ft_blob_update(void *blob, bd_t *bd) { int len, ret, nodeoffset = 0; char module_name[MODULE_NAME_MAXLEN] = {0}; - ulong memory_data[2] = {0}; compose_module_name(hw_id, module_name); len = strlen(module_name) + 1; @@ -273,22 +272,12 @@ static void ft_blob_update(void *blob, bd_t *bd) printf("ft_blob_update(): cannot set /model property err:%s\n", fdt_strerror(ret)); - memory_data[0] = cpu_to_be32(bd->bi_memstart); - memory_data[1] = cpu_to_be32(bd->bi_memsize); + ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); - nodeoffset = fdt_path_offset (blob, "/memory"); - if (nodeoffset >= 0) { - ret = fdt_setprop(blob, nodeoffset, "reg", memory_data, - sizeof(memory_data)); - if (ret < 0) + if (ret < 0) { printf("ft_blob_update): cannot set /memory/reg " "property err:%s\n", fdt_strerror(ret)); } - else { - /* memory node is required in dts */ - printf("ft_blob_update(): cannot find /memory node " - "err:%s\n", fdt_strerror(nodeoffset)); - } } #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c index d1d8c56ac5e..7176770f685 100644 --- a/board/ids8247/ids8247.c +++ b/board/ids8247/ids8247.c @@ -329,25 +329,14 @@ nand_init (void) */ void ft_blob_update(void *blob, bd_t *bd) { - int ret, nodeoffset = 0; - ulong memory_data[2] = {0}; + int ret; - memory_data[0] = cpu_to_be32(bd->bi_memstart); - memory_data[1] = cpu_to_be32(bd->bi_memsize); + ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); - nodeoffset = fdt_path_offset (blob, "/memory"); - if (nodeoffset >= 0) { - ret = fdt_setprop(blob, nodeoffset, "reg", memory_data, - sizeof(memory_data)); - if (ret < 0) + if (ret < 0) { printf("ft_blob_update): cannot set /memory/reg " "property err:%s\n", fdt_strerror(ret)); } - else { - /* memory node is required in dts */ - printf("ft_blob_update(): cannot find /memory node " - "err:%s\n", fdt_strerror(nodeoffset)); - } } void ft_board_setup(void *blob, bd_t *bd) diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index b2c35d3007c..f1ea17d5a52 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -35,6 +35,7 @@ #include #elif defined(CONFIG_OF_LIBFDT) #include +#include #endif DECLARE_GLOBAL_DATA_PTR; @@ -526,7 +527,6 @@ ft_cpu_setup(void *blob, bd_t *bd) int nodeoffset; int err; int j; - int tmp[2]; for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) { nodeoffset = fdt_path_offset(blob, fixup_props[j].node); @@ -543,21 +543,7 @@ ft_cpu_setup(void *blob, bd_t *bd) } } - /* update, or add and update /memory node */ - nodeoffset = fdt_path_offset(blob, "/memory"); - if (nodeoffset < 0) { - nodeoffset = fdt_add_subnode(blob, 0, "memory"); - if (nodeoffset < 0) - debug("failed to add /memory node: %s\n", - fdt_strerror(nodeoffset)); - } - if (nodeoffset >= 0) { - fdt_setprop(blob, nodeoffset, "device_type", - "memory", sizeof("memory")); - tmp[0] = cpu_to_be32(bd->bi_memstart); - tmp[1] = cpu_to_be32(bd->bi_memsize); - fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp)); - } + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); } #elif defined(CONFIG_OF_FLAT_TREE) void -- cgit v1.3.1 From 3b9abdc448a1c2c6a4c2aa292724b4d1a05166a9 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 11 Dec 2007 13:38:19 +0100 Subject: ppc4xx: Correct GPIO offset in gpio_config() Thanks to Gary Jennejohn for pointing this out. Signed-off-by: Stefan Roese --- cpu/ppc4xx/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c index dcf1fba8384..7b09a2f7d37 100644 --- a/cpu/ppc4xx/gpio.c +++ b/cpu/ppc4xx/gpio.c @@ -47,7 +47,7 @@ void gpio_config(int pin, int in_out, int gpio_alt, int out_val) } if (pin >= GPIO_MAX/2) { - offs2 = 0x100; + offs2 = 0x4; pin2 = (pin - GPIO_MAX/2) << 1; } -- cgit v1.3.1 From f852ce72f100cabd1f11c21c085a0ad8eca9fb65 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 29 Nov 2007 00:15:30 -0600 Subject: Add libfdt based ft_cpu_setup for mpc85xx Signed-off-by: Kumar Gala --- cpu/mpc85xx/Makefile | 4 +++- cpu/mpc85xx/fdt.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+), 1 deletion(-) create mode 100644 cpu/mpc85xx/fdt.c (limited to 'cpu') diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 32091fa4e1d..d179d701bdd 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -29,8 +29,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o resetvec.o +COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o + pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o \ + $(COBJS-y) SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c new file mode 100644 index 00000000000..737a6c485a2 --- /dev/null +++ b/cpu/mpc85xx/fdt.c @@ -0,0 +1,64 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +void ft_cpu_setup(void *blob, bd_t *bd) +{ +#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ + defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) + fdt_fixup_ethernet(blob, bd); +#endif + + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "timebase-frequency", bd->bi_busfreq / 8, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "clock-frequency", bd->bi_intfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "soc", 4, + "bus-frequency", bd->bi_busfreq, 1); +#ifdef CONFIG_QE + do_fixup_by_prop_u32(blob, "device_type", "soc", 4, + "bus-frequency", bd->bi_busfreq, 1); +#endif + +#ifdef CFG_NS16550 + do_fixup_by_compat_u32(blob, "ns16550", + "clock-frequency", bd->bi_busfreq, 1); +#endif + +#ifdef CONFIG_CPM2 + do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", + "current-speed", bd->bi_baudrate, 1); + + do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", + "clock-frequency", bd->bi_brgfreq, 1); +#endif + + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); +} -- cgit v1.3.1 From f59b55a5b8fcadaa99781ba48e7a38e956afa527 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 27 Nov 2007 23:25:02 -0600 Subject: Stop using immap_t for guts offset on 85xx In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers instead of getting it via &immap->im_gur. Signed-off-by: Kumar Gala --- board/cds/mpc8541cds/mpc8541cds.c | 8 +++----- board/cds/mpc8548cds/mpc8548cds.c | 10 ++++------ board/cds/mpc8555cds/mpc8555cds.c | 8 +++----- board/freescale/mpc8544ds/mpc8544ds.c | 5 ++--- board/mpc8540ads/mpc8540ads.c | 5 ++--- board/mpc8540eval/mpc8540eval.c | 2 +- board/mpc8560ads/mpc8560ads.c | 5 ++--- board/mpc8568mds/mpc8568mds.c | 5 ++--- board/pm854/pm854.c | 5 ++--- board/pm856/pm856.c | 5 ++--- board/sbc8560/sbc8560.c | 3 +-- board/stxgp3/stxgp3.c | 3 +-- board/stxssa/stxssa.c | 3 +-- board/tqm85xx/sdram.c | 3 +-- board/tqm85xx/tqm85xx.c | 2 +- cpu/mpc85xx/pci.c | 2 +- cpu/mpc85xx/qe_io.c | 4 ++-- cpu/mpc85xx/spd_sdram.c | 2 +- cpu/mpc85xx/speed.c | 3 +-- include/asm-ppc/immap_85xx.h | 5 +++-- 20 files changed, 36 insertions(+), 52 deletions(-) (limited to 'cpu') diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c index 558ba9903ce..36b2fa1616f 100644 --- a/board/cds/mpc8541cds/mpc8541cds.c +++ b/board/cds/mpc8541cds/mpc8541cds.c @@ -203,8 +203,7 @@ int board_early_init_f (void) int checkboard (void) { - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); @@ -250,7 +249,6 @@ long int initdram(int board_type) { long dram_size = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; puts("Initializing\n"); @@ -263,7 +261,7 @@ initdram(int board_type) * Override DLL = 1, Course Adj = 1, Tap Select = 0 */ - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); gur->ddrdllcr = 0x81000000; asm("sync;isync;msync"); @@ -294,7 +292,7 @@ void local_bus_init(void) { volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); volatile ccsr_lbc_t *lbc = &immap->im_lbc; uint clkdiv; diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 36d7e1ed487..4f02f64db5b 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -56,7 +56,7 @@ int board_early_init_f (void) int checkboard (void) { volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; /* PCI slot in USER bits CSR[6:7] by convention. */ @@ -96,7 +96,6 @@ long int initdram(int board_type) { long dram_size = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; puts("Initializing\n"); @@ -109,7 +108,7 @@ initdram(int board_type) * Override DLL = 1, Course Adj = 1, Tap Select = 0 */ - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); gur->ddrdllcr = 0x81000000; asm("sync;isync;msync"); @@ -140,7 +139,7 @@ void local_bus_init(void) { volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); volatile ccsr_lbc_t *lbc = &immap->im_lbc; uint clkdiv; @@ -330,8 +329,7 @@ int first_free_busno=0; void pci_init_board(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c index 8f1642187c1..2f1b00e1ab4 100644 --- a/board/cds/mpc8555cds/mpc8555cds.c +++ b/board/cds/mpc8555cds/mpc8555cds.c @@ -201,8 +201,7 @@ int board_early_init_f (void) int checkboard (void) { - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); @@ -248,7 +247,6 @@ long int initdram(int board_type) { long dram_size = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; puts("Initializing\n"); @@ -261,7 +259,7 @@ initdram(int board_type) * Override DLL = 1, Course Adj = 1, Tap Select = 0 */ - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); gur->ddrdllcr = 0x81000000; asm("sync;isync;msync"); @@ -292,7 +290,7 @@ void local_bus_init(void) { volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); volatile ccsr_lbc_t *lbc = &immap->im_lbc; uint clkdiv; diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 6f9864aefcc..e13be6388cb 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -50,7 +50,7 @@ int board_early_init_f (void) int checkboard (void) { volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); volatile ccsr_lbc_t *lbc = &immap->im_lbc; volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; @@ -146,8 +146,7 @@ int first_free_busno=0; void pci_init_board(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c index 914e51a7607..2db8b3256b8 100644 --- a/board/mpc8540ads/mpc8540ads.c +++ b/board/mpc8540ads/mpc8540ads.c @@ -77,13 +77,12 @@ initdram(int board_type) { long dram_size = 0; extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; puts("Initializing\n"); #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); uint temp_ddrdll = 0; /* @@ -126,7 +125,7 @@ void local_bus_init(void) { volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); volatile ccsr_lbc_t *lbc = &immap->im_lbc; uint clkdiv; diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index 3b3c8ed26d0..52fe8cad0c2 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -75,7 +75,7 @@ long int initdram (int board_type) uint temp_lbcdll = 0; #endif #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_DDR_DLL) diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c index eef524b45ea..4a30bce2a79 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/mpc8560ads/mpc8560ads.c @@ -278,13 +278,12 @@ initdram(int board_type) { long dram_size = 0; extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; puts("Initializing\n"); #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); uint temp_ddrdll = 0; /* @@ -327,7 +326,7 @@ void local_bus_init(void) { volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); volatile ccsr_lbc_t *lbc = &immap->im_lbc; uint clkdiv; diff --git a/board/mpc8568mds/mpc8568mds.c b/board/mpc8568mds/mpc8568mds.c index 818ff138a99..2a68185bb9e 100644 --- a/board/mpc8568mds/mpc8568mds.c +++ b/board/mpc8568mds/mpc8568mds.c @@ -133,7 +133,6 @@ long int initdram(int board_type) { long dram_size = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; puts("Initializing\n"); @@ -146,7 +145,7 @@ initdram(int board_type) * Override DLL = 1, Course Adj = 1, Tap Select = 0 */ - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); gur->ddrdllcr = 0x81000000; asm("sync;isync;msync"); @@ -177,7 +176,7 @@ void local_bus_init(void) { volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); volatile ccsr_lbc_t *lbc = &immap->im_lbc; uint clkdiv; diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index 6ead1d06309..15e948c5171 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -79,13 +79,12 @@ initdram(int board_type) { long dram_size = 0; extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; puts("Initializing\n"); #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); int i,x; x = 10; @@ -134,7 +133,7 @@ void local_bus_init(void) { volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); volatile ccsr_lbc_t *lbc = &immap->im_lbc; uint clkdiv; diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index a10075451e0..da4fd883365 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -232,13 +232,12 @@ initdram(int board_type) { long dram_size = 0; extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; puts("Initializing\n"); #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); int i,x; x = 10; @@ -288,7 +287,7 @@ void local_bus_init(void) { volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); volatile ccsr_lbc_t *lbc = &immap->im_lbc; uint clkdiv; diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index e8b9929e771..e02fb55678f 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -264,7 +264,6 @@ long int initdram (int board_type) { long dram_size = 0; extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; #if 0 #if !defined(CONFIG_RAM_AS_FLASH) volatile ccsr_lbc_t *lbc= &immap->im_lbc; @@ -273,7 +272,7 @@ long int initdram (int board_type) #endif #endif /* 0 */ #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_DDR_DLL) uint temp_ddrdll = 0; diff --git a/board/stxgp3/stxgp3.c b/board/stxgp3/stxgp3.c index a58c043b629..3b04949e025 100644 --- a/board/stxgp3/stxgp3.c +++ b/board/stxgp3/stxgp3.c @@ -283,11 +283,10 @@ initdram (int board_type) { long dram_size = 0; extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); uint temp_ddrdll = 0; /* Work around to stabilize DDR DLL */ diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c index 9bacb98d865..253fb2b28f2 100644 --- a/board/stxssa/stxssa.c +++ b/board/stxssa/stxssa.c @@ -302,8 +302,7 @@ initdram (int board_type) #if defined(CONFIG_DDR_DLL) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); uint temp_ddrdll = 0; /* Work around to stabilize DDR DLL */ diff --git a/board/tqm85xx/sdram.c b/board/tqm85xx/sdram.c index 9c1f0876872..8ca50f54d93 100644 --- a/board/tqm85xx/sdram.c +++ b/board/tqm85xx/sdram.c @@ -150,8 +150,7 @@ long int initdram (int board_type) * This DLL-Override only used on TQM8540 and TQM8560 */ { - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile ccsr_gur_t *gur= &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); int i,x; x = 10; diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c index 256c076c7dd..c45676c0483 100644 --- a/board/tqm85xx/tqm85xx.c +++ b/board/tqm85xx/tqm85xx.c @@ -325,7 +325,7 @@ int misc_init_r (void) void local_bus_init (void) { volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); volatile ccsr_lbc_t *lbc = &immap->im_lbc; uint clkdiv; diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index db09e45fbcc..35e96d98963 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -48,7 +48,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose) #ifdef CONFIG_MPC85XX_PCI2 volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2; #endif - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); struct pci_controller * hose; pci_hose = board_hose; diff --git a/cpu/mpc85xx/qe_io.c b/cpu/mpc85xx/qe_io.c index 8878bc53193..98075bbe54f 100644 --- a/cpu/mpc85xx/qe_io.c +++ b/cpu/mpc85xx/qe_io.c @@ -34,9 +34,9 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) u32 pin_2bit_assign; u32 pin_1bit_mask; u32 tmp_val; - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); volatile par_io_t *par_io = (volatile par_io_t *) - &(im->im_gur.qe_par_io); + &(gur->qe_par_io); /* Caculate pin location and 2bit mask and dir */ pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 5dc223a53e3..307ba3bf013 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -309,7 +309,7 @@ spd_sdram(void) if ((SVR_VER(get_svr()) == SVR_8548_E) && (SVR_MJREV(get_svr()) == 1) && (spd.mem_type == SPD_MEMTYPE_DDR2)) { - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); gur->ddrioovcr = (0x80000000 /* Enable */ | 0x10000000);/* VSEL to 1.8V */ } diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 12359a2d64b..5c35d4a50af 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -35,8 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info (sys_info_t * sysInfo) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); uint plat_ratio,e500_ratio,half_freqSystemBus; plat_ratio = (gur->porpllsr) & 0x0000003e; diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 496fc72da34..df53bd2d800 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1617,6 +1617,9 @@ typedef struct ccsr_gur { char res15[61648]; /* 0xe0f30 to 0xefffff */ } ccsr_gur_t; +#define CFG_MPC85xx_GUTS_OFFSET (0xE0000) +#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET) + #define PORDEVSR_PCI (0x00800000) /* PCI Mode */ typedef struct immap { @@ -1634,8 +1637,6 @@ typedef struct immap { ccsr_tsec_t im_tsec2; ccsr_pic_t im_pic; ccsr_cpm_t im_cpm; - ccsr_rio_t im_rio; - ccsr_gur_t im_gur; } immap_t; extern immap_t *immr; -- cgit v1.3.1 From aafeefbdb8b029f5ca2a195598d0a501a606eea9 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 28 Nov 2007 00:36:33 -0600 Subject: Stop using immap_t for cpm offset on 85xx In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers instead of getting it via &immap->im_cpm. Signed-off-by: Kumar Gala --- cpu/mpc85xx/commproc.c | 28 +++++++++++------------ cpu/mpc85xx/cpu_init.c | 6 ++--- cpu/mpc85xx/ether_fcc.c | 54 ++++++++++++++++++++++---------------------- cpu/mpc85xx/serial_scc.c | 35 +++++++++++++--------------- cpu/mpc85xx/speed.c | 6 ++--- include/asm-ppc/immap_85xx.h | 4 +++- include/asm-ppc/iopin_85xx.h | 40 ++++++++++++++++---------------- include/ioports.h | 2 +- 8 files changed, 87 insertions(+), 88 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/commproc.c b/cpu/mpc85xx/commproc.c index 3504d50caed..b0ecd25507b 100644 --- a/cpu/mpc85xx/commproc.c +++ b/cpu/mpc85xx/commproc.c @@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; void m8560_cpm_reset(void) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; volatile ulong count; gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); @@ -50,11 +50,11 @@ m8560_cpm_reset(void) /* * Reset CPM */ - immr->im_cpm.im_cpm_cp.cpcr = CPM_CR_RST; + cpm->im_cpm_cp.cpcr = CPM_CR_RST; count = 0; do { /* Spin until command processed */ __asm__ __volatile__ ("eieio"); - } while ((immr->im_cpm.im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000); + } while ((cpm->im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000); } /* Allocate some memory from the dual ported ram. @@ -64,7 +64,7 @@ m8560_cpm_reset(void) uint m8560_cpm_dpalloc(uint size, uint align) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; uint retloc; uint align_mask, off; uint savebase; @@ -86,7 +86,7 @@ m8560_cpm_dpalloc(uint size, uint align) retloc = gd->dp_alloc_base; gd->dp_alloc_base += size; - memset((void *)&(immr->im_cpm.im_dprambase[retloc]), 0, size); + memset((void *)&(cpm->im_dprambase[retloc]), 0, size); return(retloc); } @@ -120,16 +120,16 @@ m8560_cpm_hostalloc(uint size, uint align) void m8560_cpm_setbrg(uint brg, uint rate) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; volatile uint *bp; /* This is good enough to get SMCs running..... */ if (brg < 4) { - bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1); + bp = (uint *)&(cpm->im_cpm_brg1.brgc1); } else { - bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5); + bp = (uint *)&(cpm->im_cpm_brg2.brgc5); brg -= 4; } bp += brg; @@ -142,16 +142,16 @@ m8560_cpm_setbrg(uint brg, uint rate) void m8560_cpm_fastbrg(uint brg, uint rate, int div16) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; volatile uint *bp; /* This is good enough to get SMCs running..... */ if (brg < 4) { - bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1); + bp = (uint *)&(cpm->im_cpm_brg1.brgc1); } else { - bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5); + bp = (uint *)&(cpm->im_cpm_brg2.brgc5); brg -= 4; } bp += brg; @@ -167,14 +167,14 @@ m8560_cpm_fastbrg(uint brg, uint rate, int div16) void m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; volatile uint *bp; if (brg < 4) { - bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1); + bp = (uint *)&(cpm->im_cpm_brg1.brgc1); } else { - bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5); + bp = (uint *)&(cpm->im_cpm_brg2.brgc5); brg -= 4; } bp += brg; diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 79ad20c91aa..5af69cea8de 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -59,7 +59,7 @@ static void config_qe_ioports(void) #endif #ifdef CONFIG_CPM2 -static void config_8560_ioports (volatile immap_t * immr) +void config_8560_ioports (volatile ccsr_cpm_t * cpm) { int portnum; @@ -99,7 +99,7 @@ static void config_8560_ioports (volatile immap_t * immr) } if (pmsk != 0) { - volatile ioport_t *iop = ioport_addr (immr, portnum); + volatile ioport_t *iop = ioport_addr (cpm, portnum); uint tpmsk = ~pmsk; /* @@ -143,7 +143,7 @@ void cpu_init_f (void) #ifdef CONFIG_CPM2 - config_8560_ioports(immap); + config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR); #endif /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c index 5b23a80e1ca..bd62aab9f34 100644 --- a/cpu/mpc85xx/ether_fcc.c +++ b/cpu/mpc85xx/ether_fcc.c @@ -230,8 +230,8 @@ static int fec_init(struct eth_device* dev, bd_t *bis) { struct ether_fcc_info_s * info = dev->priv; int i; - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_cpm_cp_t *cp = &(immr->im_cpm.im_cpm_cp); + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp); fcc_enet_t *pram_ptr; unsigned long mem_addr; @@ -242,35 +242,35 @@ static int fec_init(struct eth_device* dev, bd_t *bis) /* 28.9 - (1-2): ioports have been set up already */ /* 28.9 - (3): connect FCC's tx and rx clocks */ - immr->im_cpm.im_cpm_mux.cmxuar = 0; /* ATM */ - immr->im_cpm.im_cpm_mux.cmxfcr = (immr->im_cpm.im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) | + cpm->im_cpm_mux.cmxuar = 0; /* ATM */ + cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) | info->cmxfcr_value; /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */ if(info->ether_index == 0) { - immr->im_cpm.im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; + cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; } else if (info->ether_index == 1) { - immr->im_cpm.im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; + cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; } else if (info->ether_index == 2) { - immr->im_cpm.im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; + cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; } /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */ if(info->ether_index == 0) { - immr->im_cpm.im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + cpm->im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; } else if (info->ether_index == 1){ - immr->im_cpm.im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + cpm->im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; } else if (info->ether_index == 2){ - immr->im_cpm.im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + cpm->im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; } /* 28.9 - (6): FDSR: Ethernet Syn */ if(info->ether_index == 0) { - immr->im_cpm.im_cpm_fcc1.fdsr = 0xD555; + cpm->im_cpm_fcc1.fdsr = 0xD555; } else if (info->ether_index == 1) { - immr->im_cpm.im_cpm_fcc2.fdsr = 0xD555; + cpm->im_cpm_fcc2.fdsr = 0xD555; } else if (info->ether_index == 2) { - immr->im_cpm.im_cpm_fcc3.fdsr = 0xD555; + cpm->im_cpm_fcc3.fdsr = 0xD555; } /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */ @@ -296,7 +296,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis) rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; /* 28.9 - (7): initialize parameter ram */ - pram_ptr = (fcc_enet_t *)&(immr->im_cpm.im_dprambase[info->proff_enet]); + pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]); /* clear whole structure to make sure all reserved fields are zero */ memset((void*)pram_ptr, 0, sizeof(fcc_enet_t)); @@ -385,14 +385,14 @@ static int fec_init(struct eth_device* dev, bd_t *bis) /* 28.9 - (8)(9): clear out events in FCCE */ /* 28.9 - (9): FCCM: mask all events */ if(info->ether_index == 0) { - immr->im_cpm.im_cpm_fcc1.fcce = ~0x0; - immr->im_cpm.im_cpm_fcc1.fccm = 0; + cpm->im_cpm_fcc1.fcce = ~0x0; + cpm->im_cpm_fcc1.fccm = 0; } else if (info->ether_index == 1) { - immr->im_cpm.im_cpm_fcc2.fcce = ~0x0; - immr->im_cpm.im_cpm_fcc2.fccm = 0; + cpm->im_cpm_fcc2.fcce = ~0x0; + cpm->im_cpm_fcc2.fccm = 0; } else if (info->ether_index == 2) { - immr->im_cpm.im_cpm_fcc3.fcce = ~0x0; - immr->im_cpm.im_cpm_fcc3.fccm = 0; + cpm->im_cpm_fcc3.fcce = ~0x0; + cpm->im_cpm_fcc3.fccm = 0; } /* 28.9 - (10-12): we don't use ethernet interrupts */ @@ -413,11 +413,11 @@ static int fec_init(struct eth_device* dev, bd_t *bis) /* 28.9 - (14): enable tx/rx in gfmr */ if(info->ether_index == 0) { - immr->im_cpm.im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; + cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; } else if (info->ether_index == 1) { - immr->im_cpm.im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; + cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; } else if (info->ether_index == 2) { - immr->im_cpm.im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; + cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; } return 1; @@ -426,15 +426,15 @@ static int fec_init(struct eth_device* dev, bd_t *bis) static void fec_halt(struct eth_device* dev) { struct ether_fcc_info_s * info = dev->priv; - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; /* write GFMR: disable tx/rx */ if(info->ether_index == 0) { - immr->im_cpm.im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); + cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); } else if(info->ether_index == 1) { - immr->im_cpm.im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); + cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); } else if(info->ether_index == 2) { - immr->im_cpm.im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); + cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); } } diff --git a/cpu/mpc85xx/serial_scc.c b/cpu/mpc85xx/serial_scc.c index 4e925f8bea2..7ee3cc8234c 100644 --- a/cpu/mpc85xx/serial_scc.c +++ b/cpu/mpc85xx/serial_scc.c @@ -88,17 +88,17 @@ DECLARE_GLOBAL_DATA_PTR; int serial_init (void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; volatile ccsr_cpm_scc_t *sp; volatile scc_uart_t *up; volatile cbd_t *tbdf, *rbdf; - volatile ccsr_cpm_cp_t *cp = &(im->im_cpm.im_cpm_cp); + volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp); uint dpaddr; /* initialize pointers to SCC */ - sp = (ccsr_cpm_scc_t *) &(im->im_cpm.im_cpm_scc[SCC_INDEX]); - up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); + sp = (ccsr_cpm_scc_t *) &(cpm->im_cpm_scc[SCC_INDEX]); + up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); /* Disable transmitter/receiver. */ @@ -107,8 +107,8 @@ int serial_init (void) /* put the SCC channel into NMSI (non multiplexd serial interface) * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15). */ - im->im_cpm.im_cpm_mux.cmxscr = \ - (im->im_cpm.im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE; + cpm->im_cpm_mux.cmxscr = \ + (cpm->im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE; /* Set up the baud rate generator. */ @@ -123,7 +123,7 @@ int serial_init (void) /* Set the physical address of the host memory buffers in * the buffer descriptors. */ - rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[dpaddr]); + rbdf = (cbd_t *)&(cpm->im_dprambase[dpaddr]); rbdf->cbd_bufaddr = (uint) (rbdf+2); rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; tbdf = rbdf + 1; @@ -201,14 +201,13 @@ serial_putc(const char c) { volatile scc_uart_t *up; volatile cbd_t *tbdf; - volatile immap_t *im; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; if (c == '\n') serial_putc ('\r'); - im = (immap_t *)CFG_IMMR; - up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); - tbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_tbase]); + up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); + tbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_tbase]); /* Wait for last character to go. */ @@ -235,12 +234,11 @@ serial_getc(void) { volatile cbd_t *rbdf; volatile scc_uart_t *up; - volatile immap_t *im; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; unsigned char c; - im = (immap_t *)CFG_IMMR; - up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); - rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]); + up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); + rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]); /* Wait for character to show up. */ @@ -260,11 +258,10 @@ serial_tstc() { volatile cbd_t *rbdf; volatile scc_uart_t *up; - volatile immap_t *im; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; - im = (immap_t *)CFG_IMMR; - up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); - rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]); + up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); + rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]); return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0); } diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 5c35d4a50af..293269c5732 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -55,12 +55,12 @@ int get_clocks (void) { sys_info_t sys_info; #if defined(CONFIG_CPM2) - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; uint sccr, dfbrg; /* set VCO = 4 * BRG */ - immap->im_cpm.im_cpm_intctl.sccr &= 0xfffffffc; - sccr = immap->im_cpm.im_cpm_intctl.sccr; + cpm->im_cpm_intctl.sccr &= 0xfffffffc; + sccr = cpm->im_cpm_intctl.sccr; dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; #endif get_sys_info (&sys_info); diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index df53bd2d800..393fdda0afa 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1636,9 +1636,11 @@ typedef struct immap { ccsr_tsec_t im_tsec1; ccsr_tsec_t im_tsec2; ccsr_pic_t im_pic; - ccsr_cpm_t im_cpm; } immap_t; +#define CFG_MPC85xx_CPM_OFFSET (0x80000) +#define CFG_MPC85xx_CPM_ADDR (CFG_IMMR + CFG_MPC85xx_CPM_OFFSET) + extern immap_t *immr; #endif /*__IMMAP_85xx__*/ diff --git a/include/asm-ppc/iopin_85xx.h b/include/asm-ppc/iopin_85xx.h index f854df633aa..daddb554d49 100644 --- a/include/asm-ppc/iopin_85xx.h +++ b/include/asm-ppc/iopin_85xx.h @@ -23,121 +23,121 @@ typedef struct { extern __inline__ void iopin_set_high (iopin_t * iopin) { - volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; datp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_low (iopin_t * iopin) { - volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_high (iopin_t * iopin) { - volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_low (iopin_t * iopin) { - volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_out (iopin_t * iopin) { - volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; dirp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_in (iopin_t * iopin) { - volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_out (iopin_t * iopin) { - volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_in (iopin_t * iopin) { - volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_odr (iopin_t * iopin) { - volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; odrp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_act (iopin_t * iopin) { - volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_odr (iopin_t * iopin) { - volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_act (iopin_t * iopin) { - volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_ded (iopin_t * iopin) { - volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; parp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_gen (iopin_t * iopin) { - volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_ded (iopin_t * iopin) { - volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_gen (iopin_t * iopin) { - volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_opt2 (iopin_t * iopin) { - volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; sorp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_opt1 (iopin_t * iopin) { - volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_opt2 (iopin_t * iopin) { - volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_opt1 (iopin_t * iopin) { - volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } diff --git a/include/ioports.h b/include/ioports.h index cfba667cab2..1134ea52081 100644 --- a/include/ioports.h +++ b/include/ioports.h @@ -26,7 +26,7 @@ typedef struct { * a 0x20 byte boundary */ #ifdef CONFIG_MPC85xx -#define ioport_addr(im, idx) (ioport_t *)((uint)&((im)->im_cpm.im_cpm_iop) + ((idx)*0x20)) +#define ioport_addr(im, idx) (ioport_t *)((uint)&(im->im_cpm_iop) + ((idx)*0x20)) #else #define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20)) #endif -- cgit v1.3.1 From 2714223f8e04ab3e4133ff65872eef366d90bfea Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 29 Nov 2007 01:23:09 -0600 Subject: Remove CONFIG_OF_FLAT_TREE related code from mpc85xx since we now use libfdt Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 96 ------------------------------------------------------- cpu/mpc85xx/pci.c | 27 ---------------- 2 files changed, 123 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index bbc54448daa..50ff3b49121 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -30,11 +30,6 @@ #include #include -#if defined(CONFIG_OF_FLAT_TREE) -#include -#endif - - int checkcpu (void) { sys_info_t sysinfo; @@ -258,94 +253,3 @@ int dma_xfer(void *dest, uint count, void *src) { return dma_check(); } #endif - - -#ifdef CONFIG_OF_FLAT_TREE -void -ft_cpu_setup(void *blob, bd_t *bd) -{ - u32 *p; - ulong clock; - int len; - - clock = bd->bi_busfreq; - p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len); - if (p != NULL) - *p = cpu_to_be32(clock); - - p = ft_get_prop(blob, "/qe@e0080000/" OF_CPU "/bus-frequency", &len); - if (p != NULL) - *p = cpu_to_be32(clock); - - p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len); - if (p != NULL) - *p = cpu_to_be32(clock); - - p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len); - if (p != NULL) - *p = cpu_to_be32(clock); - -#if defined(CONFIG_HAS_ETH0) - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); - if (p) - memcpy(p, bd->bi_enetaddr, 6); - - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len); - if (p) - memcpy(p, bd->bi_enetaddr, 6); -#endif - -#if defined(CONFIG_HAS_ETH1) - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); - if (p) - memcpy(p, bd->bi_enet1addr, 6); - - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len); - if (p) - memcpy(p, bd->bi_enet1addr, 6); -#endif - -#if defined(CONFIG_HAS_ETH2) - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len); - if (p) - memcpy(p, bd->bi_enet2addr, 6); - - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len); - if (p) - memcpy(p, bd->bi_enet2addr, 6); - -#ifdef CONFIG_UEC_ETH - p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len); - if (p) - memcpy(p, bd->bi_enet2addr, 6); - - p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len); - if (p) - memcpy(p, bd->bi_enet2addr, 6); - -#endif -#endif - -#if defined(CONFIG_HAS_ETH3) - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len); - if (p) - memcpy(p, bd->bi_enet3addr, 6); - - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len); - if (p) - memcpy(p, bd->bi_enet3addr, 6); - -#ifdef CONFIG_UEC_ETH - p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len); - if (p) - memcpy(p, bd->bi_enet3addr, 6); - - p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len); - if (p) - memcpy(p, bd->bi_enet3addr, 6); - -#endif -#endif - -} -#endif diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index 35e96d98963..d9f49c829f5 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -29,10 +29,6 @@ #include #include -#if defined(CONFIG_OF_FLAT_TREE) -#include -#endif - #if defined(CONFIG_PCI) static struct pci_controller *pci_hose; @@ -216,27 +212,4 @@ pci_mpc85xx_init(struct pci_controller *board_hose) hose->last_busno = pci_hose_scan(hose); #endif } - -#ifdef CONFIG_OF_FLAT_TREE -void -ft_pci_setup(void *blob, bd_t *bd) -{ - u32 *p; - int len; - - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len); - if (p != NULL) { - p[0] = pci_hose[0].first_busno; - p[1] = pci_hose[0].last_busno; - } - -#ifdef CONFIG_MPC85XX_PCI2 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len); - if (p != NULL) { - p[0] = pci_hose[1].first_busno; - p[1] = pci_hose[1].last_busno; - } -#endif -} -#endif /* CONFIG_OF_FLAT_TREE */ #endif /* CONFIG_PCI */ -- cgit v1.3.1 From 04db400892da37b76a585e332a0c137954ad2015 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 29 Nov 2007 02:10:09 -0600 Subject: Stop using immap_t on 85xx In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_*_ADDR as the base of the registers instead of getting it via &immap. Signed-off-by: Kumar Gala --- board/cds/mpc8541cds/mpc8541cds.c | 6 ++--- board/cds/mpc8548cds/mpc8548cds.c | 9 +++---- board/cds/mpc8555cds/mpc8555cds.c | 6 ++--- board/freescale/mpc8544ds/mpc8544ds.c | 5 ++-- board/mpc8540ads/mpc8540ads.c | 9 +++---- board/mpc8540eval/mpc8540eval.c | 12 ++++------ board/mpc8560ads/mpc8560ads.c | 9 +++---- board/mpc8568mds/mpc8568mds.c | 6 ++--- board/pm854/pm854.c | 9 +++---- board/pm856/pm856.c | 6 ++--- board/sbc8560/sbc8560.c | 11 ++++----- board/stxgp3/stxgp3.c | 3 +-- board/stxssa/stxssa.c | 3 +-- board/tqm85xx/sdram.c | 3 +-- board/tqm85xx/tqm85xx.c | 6 ++--- cpu/mpc85xx/cpu.c | 12 ++++------ cpu/mpc85xx/cpu_init.c | 10 +++----- cpu/mpc85xx/interrupts.c | 10 ++++---- cpu/mpc85xx/pci.c | 5 ++-- cpu/mpc85xx/spd_sdram.c | 9 +++---- cpu/mpc85xx/traps.c | 4 ++-- include/asm-ppc/immap_85xx.h | 44 ++++++++++++++++------------------- 22 files changed, 73 insertions(+), 124 deletions(-) (limited to 'cpu') diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c index 5b64fd66888..9ab98d4b686 100644 --- a/board/cds/mpc8541cds/mpc8541cds.c +++ b/board/cds/mpc8541cds/mpc8541cds.c @@ -293,9 +293,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -344,8 +343,7 @@ sdram_init(void) #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) uint idx; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; uint cpu_board_rev; uint lsdmr_common; diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index ddf308a40e0..47e2dd86cba 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -54,9 +54,8 @@ int board_early_init_f (void) int checkboard (void) { - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); @@ -137,9 +136,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -175,8 +173,7 @@ sdram_init(void) #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) uint idx; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; uint cpu_board_rev; uint lsdmr_common; diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c index 3ed10052c75..74c220d4fd9 100644 --- a/board/cds/mpc8555cds/mpc8555cds.c +++ b/board/cds/mpc8555cds/mpc8555cds.c @@ -291,9 +291,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -342,8 +341,7 @@ sdram_init(void) #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) uint idx; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; uint cpu_board_rev; uint lsdmr_common; diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index e13be6388cb..66cb536a4be 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -49,10 +49,9 @@ int board_early_init_f (void) int checkboard (void) { - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); if ((uint)&gur->porpllsr != 0xe00e0000) { printf("immap size error %x\n",&gur->porpllsr); diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c index 4e7f8565183..35f5eeaf032 100644 --- a/board/mpc8540ads/mpc8540ads.c +++ b/board/mpc8540ads/mpc8540ads.c @@ -121,9 +121,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -182,8 +181,7 @@ local_bus_init(void) void sdram_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc= &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; puts(" SDRAM: "); @@ -278,8 +276,7 @@ int testdram (void) long int fixed_sdram (void) { #ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); ddr->cs0_bnds = CFG_DDR_CS0_BNDS; ddr->cs0_config = CFG_DDR_CS0_CONFIG; diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index 52fe8cad0c2..64dfe0930cc 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -35,8 +35,7 @@ long int fixed_sdram (void); int board_pre_init (void) { #if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; + volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); pci->peer &= 0xffffffdf; /* disable master abort */ #endif @@ -68,9 +67,8 @@ long int initdram (int board_type) { long dram_size = 0; extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; #if !defined(CONFIG_RAM_AS_FLASH) - volatile ccsr_lbc_t *lbc= &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); sys_info_t sysinfo; uint temp_lbcdll = 0; #endif @@ -138,8 +136,7 @@ long int initdram (int board_type) * enable errors */ uint *p = 0; uint i = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); dma_init(); for (*p = 0; p < (uint *)(8 * 1024); p++) { if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } @@ -222,8 +219,7 @@ int testdram (void) long int fixed_sdram (void) { #ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); ddr->cs0_bnds = CFG_DDR_CS0_BNDS; ddr->cs0_config = CFG_DDR_CS0_CONFIG; diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c index 7a7941f18ea..bb7f11bcc8a 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/mpc8560ads/mpc8560ads.c @@ -323,9 +323,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -384,8 +383,7 @@ local_bus_init(void) void sdram_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc= &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; puts(" SDRAM: "); @@ -480,8 +478,7 @@ int testdram (void) long int fixed_sdram (void) { #ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); ddr->cs0_bnds = CFG_DDR_CS0_BNDS; ddr->cs0_config = CFG_DDR_CS0_CONFIG; diff --git a/board/mpc8568mds/mpc8568mds.c b/board/mpc8568mds/mpc8568mds.c index 3e3feeca5b5..460cb1b2753 100644 --- a/board/mpc8568mds/mpc8568mds.c +++ b/board/mpc8568mds/mpc8568mds.c @@ -178,9 +178,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -213,8 +212,7 @@ sdram_init(void) #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) uint idx; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; uint lsdmr_common; diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index 15e948c5171..999d8b52598 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -45,8 +45,7 @@ long int fixed_sdram(void); int board_early_init_f (void) { #if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; + volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); pci->peer &= 0xffffffdf; /* disable master abort */ #endif @@ -132,9 +131,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -228,8 +226,7 @@ int testdram (void) long int fixed_sdram (void) { #ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); ddr->cs0_bnds = CFG_DDR_CS0_BNDS; ddr->cs0_config = CFG_DDR_CS0_CONFIG; diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index da4fd883365..bfde6959b4e 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -286,9 +286,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -381,8 +380,7 @@ int testdram (void) long int fixed_sdram (void) { #ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); ddr->cs0_bnds = CFG_DDR_CS0_BNDS; ddr->cs0_config = CFG_DDR_CS0_CONFIG; diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index e02fb55678f..47df884ce53 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -195,8 +195,7 @@ const iop_conf_t iop_conf_tab[4][32] = { int board_early_init_f (void) { #if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; + volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); pci->peer &= 0xfffffffdf; /* disable master abort */ #endif @@ -266,7 +265,7 @@ long int initdram (int board_type) extern long spd_sdram (void); #if 0 #if !defined(CONFIG_RAM_AS_FLASH) - volatile ccsr_lbc_t *lbc= &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); sys_info_t sysinfo; uint temp_lbcdll = 0; #endif @@ -335,8 +334,7 @@ long int initdram (int board_type) * enable errors */ uint *p = 0; uint i = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); dma_init(); for (*p = 0; p < (uint *)(8 * 1024); p++) { if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } @@ -423,8 +421,7 @@ long int fixed_sdram (void) #define CFG_DDR_CONTROL 0xc2000000 #ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); ddr->cs0_bnds = 0x00000007; ddr->cs1_bnds = 0x0010001f; diff --git a/board/stxgp3/stxgp3.c b/board/stxgp3/stxgp3.c index 3b04949e025..3649acf07de 100644 --- a/board/stxgp3/stxgp3.c +++ b/board/stxgp3/stxgp3.c @@ -203,8 +203,7 @@ int board_early_init_f(void) { #if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; + volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); pci->peer &= 0xfffffffdf; /* disable master abort */ #endif diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c index 253fb2b28f2..e2b38a62056 100644 --- a/board/stxssa/stxssa.c +++ b/board/stxssa/stxssa.c @@ -252,8 +252,7 @@ int board_early_init_f(void) { #if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; + volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); pci->peer &= 0xffffffdf; /* disable master abort */ #endif diff --git a/board/tqm85xx/sdram.c b/board/tqm85xx/sdram.c index 8ca50f54d93..2053adefb46 100644 --- a/board/tqm85xx/sdram.c +++ b/board/tqm85xx/sdram.c @@ -57,8 +57,7 @@ int cas_latency(void); long int sdram_setup(int casl) { int i; - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile ccsr_ddr_t *ddr = &immap->im_ddr; + volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); unsigned long cfg_ddr_timing1; unsigned long cfg_ddr_mode; diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c index c45676c0483..5d5cb1b75cb 100644 --- a/board/tqm85xx/tqm85xx.c +++ b/board/tqm85xx/tqm85xx.c @@ -262,8 +262,7 @@ int checkboard (void) int misc_init_r (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *memctl = &immap->im_lbc; + volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); /* * Adjust flash start and offset to detected values @@ -324,9 +323,8 @@ int misc_init_r (void) */ void local_bus_init (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 50ff3b49121..e55d3372890 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -108,8 +108,7 @@ int checkcpu (void) lcrr = CFG_LBC_LCRR; #else { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc= &immap->im_lbc; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); lcrr = lbc->lcrr; } @@ -209,8 +208,7 @@ reset_85xx_watchdog(void) #if defined(CONFIG_DDR_ECC) void dma_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_dma_t *dma = &immap->im_dma; + volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); dma->satr0 = 0x02c40000; dma->datr0 = 0x02c40000; @@ -220,8 +218,7 @@ void dma_init(void) { } uint dma_check(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_dma_t *dma = &immap->im_dma; + volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); volatile uint status = dma->sr0; /* While the channel is busy, spin */ @@ -240,8 +237,7 @@ uint dma_check(void) { } int dma_xfer(void *dest, uint count, void *src) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_dma_t *dma = &immap->im_dma; + volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); dma->dar0 = (uint) dest; dma->sar0 = (uint) src; diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 5af69cea8de..fdb9ecbd509 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -131,8 +131,7 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) void cpu_init_f (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *memctl = &immap->im_lbc; + volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); extern void m8560_cpm_reset (void); /* Pointer is writable since we allocated a register for it */ @@ -222,18 +221,15 @@ void cpu_init_f (void) int cpu_init_r(void) { -#if defined(CONFIG_CLEAR_LAW0) || defined(CONFIG_L2_CACHE) - volatile immap_t *immap = (immap_t *)CFG_IMMR; -#endif #ifdef CONFIG_CLEAR_LAW0 - volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); /* clear alternate boot location LAW (used for sdram, or ddr bank) */ ecm->lawar0 = 0; #endif #if defined(CONFIG_L2_CACHE) - volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache; + volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR; volatile uint cache_ctl; uint svr, ver; uint l2srbar; diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c index bf737d62286..18e5377b32b 100644 --- a/cpu/mpc85xx/interrupts.c +++ b/cpu/mpc85xx/interrupts.c @@ -80,19 +80,17 @@ int disable_interrupts (void) int interrupt_init (void) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); - immr->im_pic.gcr = MPC85xx_PICGCR_RST; - while (immr->im_pic.gcr & MPC85xx_PICGCR_RST); - immr->im_pic.gcr = MPC85xx_PICGCR_M; + pic->gcr = MPC85xx_PICGCR_RST; + while (pic->gcr & MPC85xx_PICGCR_RST); + pic->gcr = MPC85xx_PICGCR_M; decrementer_count = get_tbclk() / CFG_HZ; mtspr(SPRN_TCR, TCR_PIE); set_dec (decrementer_count); set_msr (get_msr () | MSR_EE); #ifdef CONFIG_INTERRUPTS - volatile ccsr_pic_t *pic = &immr->im_pic; - pic->iivpr1 = 0x810002; /* 50220 enable ecm interrupts */ debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1); diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index d9f49c829f5..a5060cdec43 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -39,10 +39,9 @@ pci_mpc85xx_init(struct pci_controller *board_hose) u16 reg16; u32 dev; - volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; - volatile ccsr_pcix_t *pcix = &immap->im_pcix; + volatile ccsr_pcix_t *pcix = (void *)(CFG_MPC85xx_PCIX_ADDR); #ifdef CONFIG_MPC85XX_PCI2 - volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2; + volatile ccsr_pcix_t *pcix2 = (void *)(CFG_MPC85xx_PCIX2_ADDR); #endif volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); struct pci_controller * hose; diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 307ba3bf013..2a4cd57b69f 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -171,8 +171,7 @@ unsigned int determine_refresh_rate(unsigned int spd_refresh) long int spd_sdram(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr = &immap->im_ddr; + volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); spd_eeprom_t spd; unsigned int n_ranks; unsigned int rank_density; @@ -1023,8 +1022,7 @@ spd_sdram(void) static unsigned int setup_laws_and_tlbs(unsigned int memsize) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); unsigned int tlb_size; unsigned int law_size; unsigned int ram_tlb_index; @@ -1130,8 +1128,7 @@ ddr_enable_ecc(unsigned int dram_size) { uint *p = 0; uint i = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); dma_init(); diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c index efc80c7aee7..2381fb0654c 100644 --- a/cpu/mpc85xx/traps.c +++ b/cpu/mpc85xx/traps.c @@ -288,8 +288,8 @@ UnknownException(struct pt_regs *regs) void ExtIntException(struct pt_regs *regs) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_pic_t *pic = &immap->im_pic; + volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); + uint vect; #if defined(CONFIG_CMD_KGDB) diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 393fdda0afa..d769d701203 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -720,11 +720,10 @@ typedef struct ccsr_tsec { } ccsr_tsec_t; /* - * PIC Registers(0x2_6000-0x4_0000-0x8_0000) + * PIC Registers(0x4_0000-0x8_0000) */ typedef struct ccsr_pic { - char res0[106496]; /* 0x26000-0x40000 */ - char res1[64]; + char res1[64]; /* 0x40000 */ uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */ char res2[12]; uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */ @@ -1617,30 +1616,27 @@ typedef struct ccsr_gur { char res15[61648]; /* 0xe0f30 to 0xefffff */ } ccsr_gur_t; -#define CFG_MPC85xx_GUTS_OFFSET (0xE0000) -#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET) - #define PORDEVSR_PCI (0x00800000) /* PCI Mode */ -typedef struct immap { - ccsr_local_ecm_t im_local_ecm; - ccsr_ddr_t im_ddr; - ccsr_i2c_t im_i2c; - ccsr_duart_t im_duart; - ccsr_lbc_t im_lbc; - ccsr_pcix_t im_pcix; - ccsr_pcix_t im_pcix2; - char reserved[90112]; - ccsr_l2cache_t im_l2cache; - ccsr_dma_t im_dma; - ccsr_tsec_t im_tsec1; - ccsr_tsec_t im_tsec2; - ccsr_pic_t im_pic; -} immap_t; - +#define CFG_MPC85xx_GUTS_OFFSET (0xE0000) +#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET) +#define CFG_MPC85xx_ECM_OFFSET (0x0000) +#define CFG_MPC85xx_ECM_ADDR (CFG_IMMR + CFG_MPC85xx_ECM_OFFSET) +#define CFG_MPC85xx_DDR_OFFSET (0x2000) +#define CFG_MPC85xx_DDR_ADDR (CFG_IMMR + CFG_MPC85xx_DDR_OFFSET) +#define CFG_MPC85xx_LBC_OFFSET (0x5000) +#define CFG_MPC85xx_LBC_ADDR (CFG_IMMR + CFG_MPC85xx_LBC_OFFSET) +#define CFG_MPC85xx_PCIX_OFFSET (0x8000) +#define CFG_MPC85xx_PCIX_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET) +#define CFG_MPC85xx_PCIX2_OFFSET (0x9000) +#define CFG_MPC85xx_PCIX2_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET) +#define CFG_MPC85xx_L2_OFFSET (0x20000) +#define CFG_MPC85xx_L2_ADDR (CFG_IMMR + CFG_MPC85xx_L2_OFFSET) +#define CFG_MPC85xx_DMA_OFFSET (0x21000) +#define CFG_MPC85xx_DMA_ADDR (CFG_IMMR + CFG_MPC85xx_DMA_OFFSET) +#define CFG_MPC85xx_PIC_OFFSET (0x40000) +#define CFG_MPC85xx_PIC_ADDR (CFG_IMMR + CFG_MPC85xx_PIC_OFFSET) #define CFG_MPC85xx_CPM_OFFSET (0x80000) #define CFG_MPC85xx_CPM_ADDR (CFG_IMMR + CFG_MPC85xx_CPM_OFFSET) -extern immap_t *immr; - #endif /*__IMMAP_85xx__*/ -- cgit v1.3.1 From d435793229ce29a42797c1edc39f5b34f987f91a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 7 Dec 2007 04:59:26 -0600 Subject: Handle Asynchronous DDR clock on 85xx The MPC8572 introduces the concept of an asynchronous DDR clock with regards to the platform clock. Introduce get_ddr_freq() to report the DDR freq regardless of sync/async mode. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 16 +++++++++++++++- cpu/mpc85xx/spd_sdram.c | 6 +++--- cpu/mpc85xx/speed.c | 25 +++++++++++++++++++++++++ include/common.h | 1 + include/e500.h | 1 + 5 files changed, 45 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index e55d3372890..ac8b018b0aa 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -39,6 +39,8 @@ int checkcpu (void) uint fam; uint ver; uint major, minor; + u32 ddr_ratio; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); svr = get_svr(); ver = SVR_VER(svr); @@ -102,7 +104,19 @@ int checkcpu (void) puts("Clock Configuration:\n"); printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000); - printf(" DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); + + ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + switch (ddr_ratio) { + case 0x0: + printf(" DDR:%4lu MHz, ", sysinfo.freqDDRBus / 2000000); + break; + case 0x7: + printf(" DDR:%4lu MHz (Synchronous), ", sysinfo.freqDDRBus / 2000000); + break; + default: + printf(" DDR:%4lu MHz (Asynchronous), ", sysinfo.freqDDRBus / 2000000); + break; + } #if defined(CFG_LBC_LCRR) lcrr = CFG_LBC_LCRR; diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 2a4cd57b69f..553f736a56a 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -53,8 +53,8 @@ picos_to_clk(int picos) { int clks; - clks = picos / (2000000000 / (get_bus_freq(0) / 1000)); - if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) { + clks = picos / (2000000000 / (get_ddr_freq(0) / 1000)); + if (picos % (2000000000 / (get_ddr_freq(0) / 1000)) != 0) { clks++; } @@ -421,7 +421,7 @@ spd_sdram(void) * Adjust the CAS Latency to allow for bus speeds that * are slower than the DDR module. */ - busfreq = get_bus_freq(0) / 1000000; /* MHz */ + busfreq = get_ddr_freq(0) / 1000000; /* MHz */ effective_data_rate = max_data_rate; if (busfreq < 90) { diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 293269c5732..27de37afa87 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -48,6 +48,15 @@ void get_sys_info (sys_info_t * sysInfo) * overflow for processor speeds above 2GHz */ half_freqSystemBus = sysInfo->freqSystemBus/2; sysInfo->freqProcessor = e500_ratio*half_freqSystemBus; + sysInfo->freqDDRBus = sysInfo->freqSystemBus; + +#ifdef CONFIG_DDR_CLK_FREQ + { + u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + if (ddr_ratio != 0x7) + sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; + } +#endif } @@ -93,3 +102,19 @@ ulong get_bus_freq (ulong dummy) return val; } + +/******************************************** + * get_ddr_freq + * return ddr bus freq in Hz + *********************************************/ +ulong get_ddr_freq (ulong dummy) +{ + ulong val; + + sys_info_t sys_info; + + get_sys_info (&sys_info); + val = sys_info.freqDDRBus; + + return val; +} diff --git a/include/common.h b/include/common.h index 63ac8b062cd..01957e3d5fd 100644 --- a/include/common.h +++ b/include/common.h @@ -497,6 +497,7 @@ ulong get_bus_freq (ulong); #if defined(CONFIG_MPC85xx) typedef MPC85xx_SYS_INFO sys_info_t; void get_sys_info ( sys_info_t * ); +ulong get_ddr_freq (ulong); #endif #if defined(CONFIG_MPC86xx) typedef MPC86xx_SYS_INFO sys_info_t; diff --git a/include/e500.h b/include/e500.h index 8e3bf8cb7d2..0d73260f40c 100644 --- a/include/e500.h +++ b/include/e500.h @@ -12,6 +12,7 @@ typedef struct { unsigned long freqProcessor; unsigned long freqSystemBus; + unsigned long freqDDRBus; } MPC85xx_SYS_INFO; #endif /* _ASMLANGUAGE */ -- cgit v1.3.1 From 4d5fa99c73f354e7cf985efcf417ea55ca2f6a5e Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Fri, 29 Jun 2007 18:22:34 +0200 Subject: atmel_mci: Show SR when block read fails Show controller status as well as card status when an error occurs during block read. Signed-off-by: Haavard Skinnemoen --- cpu/at32ap/atmel_mci.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'cpu') diff --git a/cpu/at32ap/atmel_mci.c b/cpu/at32ap/atmel_mci.c index cf48be10ba4..f59dfb5995e 100644 --- a/cpu/at32ap/atmel_mci.c +++ b/cpu/at32ap/atmel_mci.c @@ -198,11 +198,11 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, /* Put the device into Transfer state */ ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR); - if (ret) goto fail; + if (ret) goto out; /* Set block length */ ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR); - if (ret) goto fail; + if (ret) goto out; pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR)); @@ -211,7 +211,7 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, start * mmc_blkdev.blksz, resp, (R1 | NCR | TRCMD_START | TRDIR_READ | TRTYP_BLOCK)); - if (ret) goto fail; + if (ret) goto out; ret = -EIO; wordcount = 0; @@ -219,7 +219,7 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, do { status = mmci_readl(SR); if (status & (ERROR_FLAGS | MMCI_BIT(OVRE))) - goto fail; + goto read_error; } while (!(status & MMCI_BIT(RXRDY))); if (status & MMCI_BIT(RXRDY)) { @@ -244,9 +244,10 @@ out: mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR); return i; -fail: +read_error: mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); - printf("mmc: bread failed, card status = %08x\n", card_status); + printf("mmc: bread failed, status = %08x, card status = %08x\n", + status, card_status); goto out; } -- cgit v1.3.1 From 36f28f8a9605ee5dcfa330482cfc62171261af97 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Mon, 29 Oct 2007 13:09:56 +0100 Subject: AVR32: Rename at32ap7000 -> at32ap700x The SoC-specific code for all the AT32AP700x CPUs is practically identical; the only difference is that some chips have less features than others. By doing this rename, we can add support for the AP7000 derivatives simply by making some features conditional. Signed-off-by: Haavard Skinnemoen --- Makefile | 2 +- cpu/at32ap/at32ap7000/Makefile | 43 ----- cpu/at32ap/at32ap7000/gpio.c | 137 --------------- cpu/at32ap/at32ap700x/Makefile | 43 +++++ cpu/at32ap/at32ap700x/gpio.c | 137 +++++++++++++++ include/asm-avr32/arch-at32ap7000/clk.h | 70 -------- include/asm-avr32/arch-at32ap7000/gpio.h | 212 ---------------------- include/asm-avr32/arch-at32ap7000/hmatrix2.h | 232 ------------------------- include/asm-avr32/arch-at32ap7000/memory-map.h | 66 ------- include/asm-avr32/arch-at32ap7000/mmc.h | 96 ---------- include/asm-avr32/arch-at32ap700x/clk.h | 70 ++++++++ include/asm-avr32/arch-at32ap700x/gpio.h | 212 ++++++++++++++++++++++ include/asm-avr32/arch-at32ap700x/hmatrix2.h | 232 +++++++++++++++++++++++++ include/asm-avr32/arch-at32ap700x/memory-map.h | 66 +++++++ include/asm-avr32/arch-at32ap700x/mmc.h | 96 ++++++++++ 15 files changed, 857 insertions(+), 857 deletions(-) delete mode 100644 cpu/at32ap/at32ap7000/Makefile delete mode 100644 cpu/at32ap/at32ap7000/gpio.c create mode 100644 cpu/at32ap/at32ap700x/Makefile create mode 100644 cpu/at32ap/at32ap700x/gpio.c delete mode 100644 include/asm-avr32/arch-at32ap7000/clk.h delete mode 100644 include/asm-avr32/arch-at32ap7000/gpio.h delete mode 100644 include/asm-avr32/arch-at32ap7000/hmatrix2.h delete mode 100644 include/asm-avr32/arch-at32ap7000/memory-map.h delete mode 100644 include/asm-avr32/arch-at32ap7000/mmc.h create mode 100644 include/asm-avr32/arch-at32ap700x/clk.h create mode 100644 include/asm-avr32/arch-at32ap700x/gpio.h create mode 100644 include/asm-avr32/arch-at32ap700x/hmatrix2.h create mode 100644 include/asm-avr32/arch-at32ap700x/memory-map.h create mode 100644 include/asm-avr32/arch-at32ap700x/mmc.h (limited to 'cpu') diff --git a/Makefile b/Makefile index 1ff80b50d99..1969dcf7399 100644 --- a/Makefile +++ b/Makefile @@ -2656,7 +2656,7 @@ bf561-ezkit_config: unconfig ######################################################################### atstk1002_config : unconfig - @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap7000 + @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x ######################################################################### ######################################################################### diff --git a/cpu/at32ap/at32ap7000/Makefile b/cpu/at32ap/at32ap7000/Makefile deleted file mode 100644 index d2767121184..00000000000 --- a/cpu/at32ap/at32ap7000/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# Copyright (C) 2005-2006 Atmel Corporation -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB := $(obj)lib$(SOC).a - -COBJS := gpio.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $^ - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/cpu/at32ap/at32ap7000/gpio.c b/cpu/at32ap/at32ap7000/gpio.c deleted file mode 100644 index 52f5372a607..00000000000 --- a/cpu/at32ap/at32ap7000/gpio.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include - -#include - -/* - * Lots of small functions here. We depend on --gc-sections getting - * rid of the ones we don't need. - */ -void gpio_enable_ebi(void) -{ -#ifdef CFG_HSDRAMC -#ifndef CFG_SDRAM_16BIT - gpio_select_periph_A(GPIO_PIN_PE0, 0); - gpio_select_periph_A(GPIO_PIN_PE1, 0); - gpio_select_periph_A(GPIO_PIN_PE2, 0); - gpio_select_periph_A(GPIO_PIN_PE3, 0); - gpio_select_periph_A(GPIO_PIN_PE4, 0); - gpio_select_periph_A(GPIO_PIN_PE5, 0); - gpio_select_periph_A(GPIO_PIN_PE6, 0); - gpio_select_periph_A(GPIO_PIN_PE7, 0); - gpio_select_periph_A(GPIO_PIN_PE8, 0); - gpio_select_periph_A(GPIO_PIN_PE9, 0); - gpio_select_periph_A(GPIO_PIN_PE10, 0); - gpio_select_periph_A(GPIO_PIN_PE11, 0); - gpio_select_periph_A(GPIO_PIN_PE12, 0); - gpio_select_periph_A(GPIO_PIN_PE13, 0); - gpio_select_periph_A(GPIO_PIN_PE14, 0); - gpio_select_periph_A(GPIO_PIN_PE15, 0); -#endif - gpio_select_periph_A(GPIO_PIN_PE26, 0); -#endif -} - -void gpio_enable_usart0(void) -{ - gpio_select_periph_B(GPIO_PIN_PA8, 0); - gpio_select_periph_B(GPIO_PIN_PA9, 0); -} - -void gpio_enable_usart1(void) -{ - gpio_select_periph_A(GPIO_PIN_PA17, 0); - gpio_select_periph_A(GPIO_PIN_PA18, 0); -} - -void gpio_enable_usart2(void) -{ - gpio_select_periph_B(GPIO_PIN_PB26, 0); - gpio_select_periph_B(GPIO_PIN_PB27, 0); -} - -void gpio_enable_usart3(void) -{ - gpio_select_periph_B(GPIO_PIN_PB18, 0); - gpio_select_periph_B(GPIO_PIN_PB19, 0); -} - -void gpio_enable_macb0(void) -{ - gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */ - gpio_select_periph_A(GPIO_PIN_PC4, 0); /* TXD1 */ - gpio_select_periph_A(GPIO_PIN_PC7, 0); /* TXEN */ - gpio_select_periph_A(GPIO_PIN_PC8, 0); /* TXCK */ - gpio_select_periph_A(GPIO_PIN_PC9, 0); /* RXD0 */ - gpio_select_periph_A(GPIO_PIN_PC10, 0); /* RXD1 */ - gpio_select_periph_A(GPIO_PIN_PC13, 0); /* RXER */ - gpio_select_periph_A(GPIO_PIN_PC15, 0); /* RXDV */ - gpio_select_periph_A(GPIO_PIN_PC16, 0); /* MDC */ - gpio_select_periph_A(GPIO_PIN_PC17, 0); /* MDIO */ -#if !defined(CONFIG_RMII) - gpio_select_periph_A(GPIO_PIN_PC0, 0); /* COL */ - gpio_select_periph_A(GPIO_PIN_PC1, 0); /* CRS */ - gpio_select_periph_A(GPIO_PIN_PC2, 0); /* TXER */ - gpio_select_periph_A(GPIO_PIN_PC5, 0); /* TXD2 */ - gpio_select_periph_A(GPIO_PIN_PC6, 0); /* TXD3 */ - gpio_select_periph_A(GPIO_PIN_PC11, 0); /* RXD2 */ - gpio_select_periph_A(GPIO_PIN_PC12, 0); /* RXD3 */ - gpio_select_periph_A(GPIO_PIN_PC14, 0); /* RXCK */ - gpio_select_periph_A(GPIO_PIN_PC18, 0); /* SPD */ -#endif -} - -void gpio_enable_macb1(void) -{ - gpio_select_periph_B(GPIO_PIN_PD13, 0); /* TXD0 */ - gpio_select_periph_B(GPIO_PIN_PD14, 0); /* TXD1 */ - gpio_select_periph_B(GPIO_PIN_PD11, 0); /* TXEN */ - gpio_select_periph_B(GPIO_PIN_PD12, 0); /* TXCK */ - gpio_select_periph_B(GPIO_PIN_PD10, 0); /* RXD0 */ - gpio_select_periph_B(GPIO_PIN_PD6, 0); /* RXD1 */ - gpio_select_periph_B(GPIO_PIN_PD5, 0); /* RXER */ - gpio_select_periph_B(GPIO_PIN_PD4, 0); /* RXDV */ - gpio_select_periph_B(GPIO_PIN_PD3, 0); /* MDC */ - gpio_select_periph_B(GPIO_PIN_PD2, 0); /* MDIO */ -#if !defined(CONFIG_RMII) - gpio_select_periph_B(GPIO_PIN_PC19, 0); /* COL */ - gpio_select_periph_B(GPIO_PIN_PC23, 0); /* CRS */ - gpio_select_periph_B(GPIO_PIN_PC26, 0); /* TXER */ - gpio_select_periph_B(GPIO_PIN_PC27, 0); /* TXD2 */ - gpio_select_periph_B(GPIO_PIN_PC28, 0); /* TXD3 */ - gpio_select_periph_B(GPIO_PIN_PC29, 0); /* RXD2 */ - gpio_select_periph_B(GPIO_PIN_PC30, 0); /* RXD3 */ - gpio_select_periph_B(GPIO_PIN_PC24, 0); /* RXCK */ - gpio_select_periph_B(GPIO_PIN_PD15, 0); /* SPD */ -#endif -} - -void gpio_enable_mmci(void) -{ - gpio_select_periph_A(GPIO_PIN_PA10, 0); /* CLK */ - gpio_select_periph_A(GPIO_PIN_PA11, 0); /* CMD */ - gpio_select_periph_A(GPIO_PIN_PA12, 0); /* DATA0 */ - gpio_select_periph_A(GPIO_PIN_PA13, 0); /* DATA1 */ - gpio_select_periph_A(GPIO_PIN_PA14, 0); /* DATA2 */ - gpio_select_periph_A(GPIO_PIN_PA15, 0); /* DATA3 */ -} diff --git a/cpu/at32ap/at32ap700x/Makefile b/cpu/at32ap/at32ap700x/Makefile new file mode 100644 index 00000000000..d2767121184 --- /dev/null +++ b/cpu/at32ap/at32ap700x/Makefile @@ -0,0 +1,43 @@ +# +# Copyright (C) 2005-2006 Atmel Corporation +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)lib$(SOC).a + +COBJS := gpio.o +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $^ + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/at32ap/at32ap700x/gpio.c b/cpu/at32ap/at32ap700x/gpio.c new file mode 100644 index 00000000000..52f5372a607 --- /dev/null +++ b/cpu/at32ap/at32ap700x/gpio.c @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include + +/* + * Lots of small functions here. We depend on --gc-sections getting + * rid of the ones we don't need. + */ +void gpio_enable_ebi(void) +{ +#ifdef CFG_HSDRAMC +#ifndef CFG_SDRAM_16BIT + gpio_select_periph_A(GPIO_PIN_PE0, 0); + gpio_select_periph_A(GPIO_PIN_PE1, 0); + gpio_select_periph_A(GPIO_PIN_PE2, 0); + gpio_select_periph_A(GPIO_PIN_PE3, 0); + gpio_select_periph_A(GPIO_PIN_PE4, 0); + gpio_select_periph_A(GPIO_PIN_PE5, 0); + gpio_select_periph_A(GPIO_PIN_PE6, 0); + gpio_select_periph_A(GPIO_PIN_PE7, 0); + gpio_select_periph_A(GPIO_PIN_PE8, 0); + gpio_select_periph_A(GPIO_PIN_PE9, 0); + gpio_select_periph_A(GPIO_PIN_PE10, 0); + gpio_select_periph_A(GPIO_PIN_PE11, 0); + gpio_select_periph_A(GPIO_PIN_PE12, 0); + gpio_select_periph_A(GPIO_PIN_PE13, 0); + gpio_select_periph_A(GPIO_PIN_PE14, 0); + gpio_select_periph_A(GPIO_PIN_PE15, 0); +#endif + gpio_select_periph_A(GPIO_PIN_PE26, 0); +#endif +} + +void gpio_enable_usart0(void) +{ + gpio_select_periph_B(GPIO_PIN_PA8, 0); + gpio_select_periph_B(GPIO_PIN_PA9, 0); +} + +void gpio_enable_usart1(void) +{ + gpio_select_periph_A(GPIO_PIN_PA17, 0); + gpio_select_periph_A(GPIO_PIN_PA18, 0); +} + +void gpio_enable_usart2(void) +{ + gpio_select_periph_B(GPIO_PIN_PB26, 0); + gpio_select_periph_B(GPIO_PIN_PB27, 0); +} + +void gpio_enable_usart3(void) +{ + gpio_select_periph_B(GPIO_PIN_PB18, 0); + gpio_select_periph_B(GPIO_PIN_PB19, 0); +} + +void gpio_enable_macb0(void) +{ + gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */ + gpio_select_periph_A(GPIO_PIN_PC4, 0); /* TXD1 */ + gpio_select_periph_A(GPIO_PIN_PC7, 0); /* TXEN */ + gpio_select_periph_A(GPIO_PIN_PC8, 0); /* TXCK */ + gpio_select_periph_A(GPIO_PIN_PC9, 0); /* RXD0 */ + gpio_select_periph_A(GPIO_PIN_PC10, 0); /* RXD1 */ + gpio_select_periph_A(GPIO_PIN_PC13, 0); /* RXER */ + gpio_select_periph_A(GPIO_PIN_PC15, 0); /* RXDV */ + gpio_select_periph_A(GPIO_PIN_PC16, 0); /* MDC */ + gpio_select_periph_A(GPIO_PIN_PC17, 0); /* MDIO */ +#if !defined(CONFIG_RMII) + gpio_select_periph_A(GPIO_PIN_PC0, 0); /* COL */ + gpio_select_periph_A(GPIO_PIN_PC1, 0); /* CRS */ + gpio_select_periph_A(GPIO_PIN_PC2, 0); /* TXER */ + gpio_select_periph_A(GPIO_PIN_PC5, 0); /* TXD2 */ + gpio_select_periph_A(GPIO_PIN_PC6, 0); /* TXD3 */ + gpio_select_periph_A(GPIO_PIN_PC11, 0); /* RXD2 */ + gpio_select_periph_A(GPIO_PIN_PC12, 0); /* RXD3 */ + gpio_select_periph_A(GPIO_PIN_PC14, 0); /* RXCK */ + gpio_select_periph_A(GPIO_PIN_PC18, 0); /* SPD */ +#endif +} + +void gpio_enable_macb1(void) +{ + gpio_select_periph_B(GPIO_PIN_PD13, 0); /* TXD0 */ + gpio_select_periph_B(GPIO_PIN_PD14, 0); /* TXD1 */ + gpio_select_periph_B(GPIO_PIN_PD11, 0); /* TXEN */ + gpio_select_periph_B(GPIO_PIN_PD12, 0); /* TXCK */ + gpio_select_periph_B(GPIO_PIN_PD10, 0); /* RXD0 */ + gpio_select_periph_B(GPIO_PIN_PD6, 0); /* RXD1 */ + gpio_select_periph_B(GPIO_PIN_PD5, 0); /* RXER */ + gpio_select_periph_B(GPIO_PIN_PD4, 0); /* RXDV */ + gpio_select_periph_B(GPIO_PIN_PD3, 0); /* MDC */ + gpio_select_periph_B(GPIO_PIN_PD2, 0); /* MDIO */ +#if !defined(CONFIG_RMII) + gpio_select_periph_B(GPIO_PIN_PC19, 0); /* COL */ + gpio_select_periph_B(GPIO_PIN_PC23, 0); /* CRS */ + gpio_select_periph_B(GPIO_PIN_PC26, 0); /* TXER */ + gpio_select_periph_B(GPIO_PIN_PC27, 0); /* TXD2 */ + gpio_select_periph_B(GPIO_PIN_PC28, 0); /* TXD3 */ + gpio_select_periph_B(GPIO_PIN_PC29, 0); /* RXD2 */ + gpio_select_periph_B(GPIO_PIN_PC30, 0); /* RXD3 */ + gpio_select_periph_B(GPIO_PIN_PC24, 0); /* RXCK */ + gpio_select_periph_B(GPIO_PIN_PD15, 0); /* SPD */ +#endif +} + +void gpio_enable_mmci(void) +{ + gpio_select_periph_A(GPIO_PIN_PA10, 0); /* CLK */ + gpio_select_periph_A(GPIO_PIN_PA11, 0); /* CMD */ + gpio_select_periph_A(GPIO_PIN_PA12, 0); /* DATA0 */ + gpio_select_periph_A(GPIO_PIN_PA13, 0); /* DATA1 */ + gpio_select_periph_A(GPIO_PIN_PA14, 0); /* DATA2 */ + gpio_select_periph_A(GPIO_PIN_PA15, 0); /* DATA3 */ +} diff --git a/include/asm-avr32/arch-at32ap7000/clk.h b/include/asm-avr32/arch-at32ap7000/clk.h deleted file mode 100644 index 7e20d97b7f9..00000000000 --- a/include/asm-avr32/arch-at32ap7000/clk.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_ARCH_CLK_H__ -#define __ASM_AVR32_ARCH_CLK_H__ - -#ifdef CONFIG_PLL -#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) -#else -#define MAIN_CLK_RATE (CFG_OSC0_HZ) -#endif - -static inline unsigned long get_cpu_clk_rate(void) -{ - return MAIN_CLK_RATE >> CFG_CLKDIV_CPU; -} -static inline unsigned long get_hsb_clk_rate(void) -{ - return MAIN_CLK_RATE >> CFG_CLKDIV_HSB; -} -static inline unsigned long get_pba_clk_rate(void) -{ - return MAIN_CLK_RATE >> CFG_CLKDIV_PBA; -} -static inline unsigned long get_pbb_clk_rate(void) -{ - return MAIN_CLK_RATE >> CFG_CLKDIV_PBB; -} - -/* Accessors for specific devices. More will be added as needed. */ -static inline unsigned long get_sdram_clk_rate(void) -{ - return get_hsb_clk_rate(); -} -static inline unsigned long get_usart_clk_rate(unsigned int dev_id) -{ - return get_pba_clk_rate(); -} -static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) -{ - return get_pbb_clk_rate(); -} -static inline unsigned long get_macb_hclk_rate(unsigned int dev_id) -{ - return get_hsb_clk_rate(); -} -static inline unsigned long get_mci_clk_rate(void) -{ - return get_pbb_clk_rate(); -} - -#endif /* __ASM_AVR32_ARCH_CLK_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/gpio.h b/include/asm-avr32/arch-at32ap7000/gpio.h deleted file mode 100644 index e4812d4d08b..00000000000 --- a/include/asm-avr32/arch-at32ap7000/gpio.h +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_ARCH_GPIO_H__ -#define __ASM_AVR32_ARCH_GPIO_H__ - -#include - -#define NR_GPIO_CONTROLLERS 5 - -/* - * Pin numbers identifying specific GPIO pins on the chip. - */ -#define GPIO_PIOA_BASE (0) -#define GPIO_PIN_PA0 (GPIO_PIOA_BASE + 0) -#define GPIO_PIN_PA1 (GPIO_PIOA_BASE + 1) -#define GPIO_PIN_PA2 (GPIO_PIOA_BASE + 2) -#define GPIO_PIN_PA3 (GPIO_PIOA_BASE + 3) -#define GPIO_PIN_PA4 (GPIO_PIOA_BASE + 4) -#define GPIO_PIN_PA5 (GPIO_PIOA_BASE + 5) -#define GPIO_PIN_PA6 (GPIO_PIOA_BASE + 6) -#define GPIO_PIN_PA7 (GPIO_PIOA_BASE + 7) -#define GPIO_PIN_PA8 (GPIO_PIOA_BASE + 8) -#define GPIO_PIN_PA9 (GPIO_PIOA_BASE + 9) -#define GPIO_PIN_PA10 (GPIO_PIOA_BASE + 10) -#define GPIO_PIN_PA11 (GPIO_PIOA_BASE + 11) -#define GPIO_PIN_PA12 (GPIO_PIOA_BASE + 12) -#define GPIO_PIN_PA13 (GPIO_PIOA_BASE + 13) -#define GPIO_PIN_PA14 (GPIO_PIOA_BASE + 14) -#define GPIO_PIN_PA15 (GPIO_PIOA_BASE + 15) -#define GPIO_PIN_PA16 (GPIO_PIOA_BASE + 16) -#define GPIO_PIN_PA17 (GPIO_PIOA_BASE + 17) -#define GPIO_PIN_PA18 (GPIO_PIOA_BASE + 18) -#define GPIO_PIN_PA19 (GPIO_PIOA_BASE + 19) -#define GPIO_PIN_PA20 (GPIO_PIOA_BASE + 20) -#define GPIO_PIN_PA21 (GPIO_PIOA_BASE + 21) -#define GPIO_PIN_PA22 (GPIO_PIOA_BASE + 22) -#define GPIO_PIN_PA23 (GPIO_PIOA_BASE + 23) -#define GPIO_PIN_PA24 (GPIO_PIOA_BASE + 24) -#define GPIO_PIN_PA25 (GPIO_PIOA_BASE + 25) -#define GPIO_PIN_PA26 (GPIO_PIOA_BASE + 26) -#define GPIO_PIN_PA27 (GPIO_PIOA_BASE + 27) -#define GPIO_PIN_PA28 (GPIO_PIOA_BASE + 28) -#define GPIO_PIN_PA29 (GPIO_PIOA_BASE + 29) -#define GPIO_PIN_PA30 (GPIO_PIOA_BASE + 30) -#define GPIO_PIN_PA31 (GPIO_PIOA_BASE + 31) - -#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32) -#define GPIO_PIN_PB0 (GPIO_PIOB_BASE + 0) -#define GPIO_PIN_PB1 (GPIO_PIOB_BASE + 1) -#define GPIO_PIN_PB2 (GPIO_PIOB_BASE + 2) -#define GPIO_PIN_PB3 (GPIO_PIOB_BASE + 3) -#define GPIO_PIN_PB4 (GPIO_PIOB_BASE + 4) -#define GPIO_PIN_PB5 (GPIO_PIOB_BASE + 5) -#define GPIO_PIN_PB6 (GPIO_PIOB_BASE + 6) -#define GPIO_PIN_PB7 (GPIO_PIOB_BASE + 7) -#define GPIO_PIN_PB8 (GPIO_PIOB_BASE + 8) -#define GPIO_PIN_PB9 (GPIO_PIOB_BASE + 9) -#define GPIO_PIN_PB10 (GPIO_PIOB_BASE + 10) -#define GPIO_PIN_PB11 (GPIO_PIOB_BASE + 11) -#define GPIO_PIN_PB12 (GPIO_PIOB_BASE + 12) -#define GPIO_PIN_PB13 (GPIO_PIOB_BASE + 13) -#define GPIO_PIN_PB14 (GPIO_PIOB_BASE + 14) -#define GPIO_PIN_PB15 (GPIO_PIOB_BASE + 15) -#define GPIO_PIN_PB16 (GPIO_PIOB_BASE + 16) -#define GPIO_PIN_PB17 (GPIO_PIOB_BASE + 17) -#define GPIO_PIN_PB18 (GPIO_PIOB_BASE + 18) -#define GPIO_PIN_PB19 (GPIO_PIOB_BASE + 19) -#define GPIO_PIN_PB20 (GPIO_PIOB_BASE + 20) -#define GPIO_PIN_PB21 (GPIO_PIOB_BASE + 21) -#define GPIO_PIN_PB22 (GPIO_PIOB_BASE + 22) -#define GPIO_PIN_PB23 (GPIO_PIOB_BASE + 23) -#define GPIO_PIN_PB24 (GPIO_PIOB_BASE + 24) -#define GPIO_PIN_PB25 (GPIO_PIOB_BASE + 25) -#define GPIO_PIN_PB26 (GPIO_PIOB_BASE + 26) -#define GPIO_PIN_PB27 (GPIO_PIOB_BASE + 27) -#define GPIO_PIN_PB28 (GPIO_PIOB_BASE + 28) -#define GPIO_PIN_PB29 (GPIO_PIOB_BASE + 29) -#define GPIO_PIN_PB30 (GPIO_PIOB_BASE + 30) - -#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32) -#define GPIO_PIN_PC0 (GPIO_PIOC_BASE + 0) -#define GPIO_PIN_PC1 (GPIO_PIOC_BASE + 1) -#define GPIO_PIN_PC2 (GPIO_PIOC_BASE + 2) -#define GPIO_PIN_PC3 (GPIO_PIOC_BASE + 3) -#define GPIO_PIN_PC4 (GPIO_PIOC_BASE + 4) -#define GPIO_PIN_PC5 (GPIO_PIOC_BASE + 5) -#define GPIO_PIN_PC6 (GPIO_PIOC_BASE + 6) -#define GPIO_PIN_PC7 (GPIO_PIOC_BASE + 7) -#define GPIO_PIN_PC8 (GPIO_PIOC_BASE + 8) -#define GPIO_PIN_PC9 (GPIO_PIOC_BASE + 9) -#define GPIO_PIN_PC10 (GPIO_PIOC_BASE + 10) -#define GPIO_PIN_PC11 (GPIO_PIOC_BASE + 11) -#define GPIO_PIN_PC12 (GPIO_PIOC_BASE + 12) -#define GPIO_PIN_PC13 (GPIO_PIOC_BASE + 13) -#define GPIO_PIN_PC14 (GPIO_PIOC_BASE + 14) -#define GPIO_PIN_PC15 (GPIO_PIOC_BASE + 15) -#define GPIO_PIN_PC16 (GPIO_PIOC_BASE + 16) -#define GPIO_PIN_PC17 (GPIO_PIOC_BASE + 17) -#define GPIO_PIN_PC18 (GPIO_PIOC_BASE + 18) -#define GPIO_PIN_PC19 (GPIO_PIOC_BASE + 19) -#define GPIO_PIN_PC20 (GPIO_PIOC_BASE + 20) -#define GPIO_PIN_PC21 (GPIO_PIOC_BASE + 21) -#define GPIO_PIN_PC22 (GPIO_PIOC_BASE + 22) -#define GPIO_PIN_PC23 (GPIO_PIOC_BASE + 23) -#define GPIO_PIN_PC24 (GPIO_PIOC_BASE + 24) -#define GPIO_PIN_PC25 (GPIO_PIOC_BASE + 25) -#define GPIO_PIN_PC26 (GPIO_PIOC_BASE + 26) -#define GPIO_PIN_PC27 (GPIO_PIOC_BASE + 27) -#define GPIO_PIN_PC28 (GPIO_PIOC_BASE + 28) -#define GPIO_PIN_PC29 (GPIO_PIOC_BASE + 29) -#define GPIO_PIN_PC30 (GPIO_PIOC_BASE + 30) -#define GPIO_PIN_PC31 (GPIO_PIOC_BASE + 31) - -#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32) -#define GPIO_PIN_PD0 (GPIO_PIOD_BASE + 0) -#define GPIO_PIN_PD1 (GPIO_PIOD_BASE + 1) -#define GPIO_PIN_PD2 (GPIO_PIOD_BASE + 2) -#define GPIO_PIN_PD3 (GPIO_PIOD_BASE + 3) -#define GPIO_PIN_PD4 (GPIO_PIOD_BASE + 4) -#define GPIO_PIN_PD5 (GPIO_PIOD_BASE + 5) -#define GPIO_PIN_PD6 (GPIO_PIOD_BASE + 6) -#define GPIO_PIN_PD7 (GPIO_PIOD_BASE + 7) -#define GPIO_PIN_PD8 (GPIO_PIOD_BASE + 8) -#define GPIO_PIN_PD9 (GPIO_PIOD_BASE + 9) -#define GPIO_PIN_PD10 (GPIO_PIOD_BASE + 10) -#define GPIO_PIN_PD11 (GPIO_PIOD_BASE + 11) -#define GPIO_PIN_PD12 (GPIO_PIOD_BASE + 12) -#define GPIO_PIN_PD13 (GPIO_PIOD_BASE + 13) -#define GPIO_PIN_PD14 (GPIO_PIOD_BASE + 14) -#define GPIO_PIN_PD15 (GPIO_PIOD_BASE + 15) -#define GPIO_PIN_PD16 (GPIO_PIOD_BASE + 16) -#define GPIO_PIN_PD17 (GPIO_PIOD_BASE + 17) - -#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32) -#define GPIO_PIN_PE0 (GPIO_PIOE_BASE + 0) -#define GPIO_PIN_PE1 (GPIO_PIOE_BASE + 1) -#define GPIO_PIN_PE2 (GPIO_PIOE_BASE + 2) -#define GPIO_PIN_PE3 (GPIO_PIOE_BASE + 3) -#define GPIO_PIN_PE4 (GPIO_PIOE_BASE + 4) -#define GPIO_PIN_PE5 (GPIO_PIOE_BASE + 5) -#define GPIO_PIN_PE6 (GPIO_PIOE_BASE + 6) -#define GPIO_PIN_PE7 (GPIO_PIOE_BASE + 7) -#define GPIO_PIN_PE8 (GPIO_PIOE_BASE + 8) -#define GPIO_PIN_PE9 (GPIO_PIOE_BASE + 9) -#define GPIO_PIN_PE10 (GPIO_PIOE_BASE + 10) -#define GPIO_PIN_PE11 (GPIO_PIOE_BASE + 11) -#define GPIO_PIN_PE12 (GPIO_PIOE_BASE + 12) -#define GPIO_PIN_PE13 (GPIO_PIOE_BASE + 13) -#define GPIO_PIN_PE14 (GPIO_PIOE_BASE + 14) -#define GPIO_PIN_PE15 (GPIO_PIOE_BASE + 15) -#define GPIO_PIN_PE16 (GPIO_PIOE_BASE + 16) -#define GPIO_PIN_PE17 (GPIO_PIOE_BASE + 17) -#define GPIO_PIN_PE18 (GPIO_PIOE_BASE + 18) -#define GPIO_PIN_PE19 (GPIO_PIOE_BASE + 19) -#define GPIO_PIN_PE20 (GPIO_PIOE_BASE + 20) -#define GPIO_PIN_PE21 (GPIO_PIOE_BASE + 21) -#define GPIO_PIN_PE22 (GPIO_PIOE_BASE + 22) -#define GPIO_PIN_PE23 (GPIO_PIOE_BASE + 23) -#define GPIO_PIN_PE24 (GPIO_PIOE_BASE + 24) -#define GPIO_PIN_PE25 (GPIO_PIOE_BASE + 25) -#define GPIO_PIN_PE26 (GPIO_PIOE_BASE + 26) - -static inline void *gpio_pin_to_addr(unsigned int pin) -{ - switch (pin >> 5) { - case 0: - return (void *)PIOA_BASE; - case 1: - return (void *)PIOB_BASE; - case 2: - return (void *)PIOC_BASE; - case 3: - return (void *)PIOD_BASE; - case 4: - return (void *)PIOE_BASE; - default: - return NULL; - } -} - -void gpio_select_periph_A(unsigned int pin, int use_pullup); -void gpio_select_periph_B(unsigned int pin, int use_pullup); - -void gpio_enable_ebi(void); -void gpio_enable_usart0(void); -void gpio_enable_usart1(void); -void gpio_enable_usart2(void); -void gpio_enable_usart3(void); -void gpio_enable_macb0(void); -void gpio_enable_macb1(void); -void gpio_enable_mmci(void); - -#endif /* __ASM_AVR32_ARCH_GPIO_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/hmatrix2.h b/include/asm-avr32/arch-at32ap7000/hmatrix2.h deleted file mode 100644 index b0e787a92f9..00000000000 --- a/include/asm-avr32/arch-at32ap7000/hmatrix2.h +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Register definition for the High-speed Bus Matrix - */ -#ifndef __ASM_AVR32_HMATRIX2_H__ -#define __ASM_AVR32_HMATRIX2_H__ - -/* HMATRIX2 register offsets */ -#define HMATRIX2_MCFG0 0x0000 -#define HMATRIX2_MCFG1 0x0004 -#define HMATRIX2_MCFG2 0x0008 -#define HMATRIX2_MCFG3 0x000c -#define HMATRIX2_MCFG4 0x0010 -#define HMATRIX2_MCFG5 0x0014 -#define HMATRIX2_MCFG6 0x0018 -#define HMATRIX2_MCFG7 0x001c -#define HMATRIX2_MCFG8 0x0020 -#define HMATRIX2_MCFG9 0x0024 -#define HMATRIX2_MCFG10 0x0028 -#define HMATRIX2_MCFG11 0x002c -#define HMATRIX2_MCFG12 0x0030 -#define HMATRIX2_MCFG13 0x0034 -#define HMATRIX2_MCFG14 0x0038 -#define HMATRIX2_MCFG15 0x003c -#define HMATRIX2_SCFG0 0x0040 -#define HMATRIX2_SCFG1 0x0044 -#define HMATRIX2_SCFG2 0x0048 -#define HMATRIX2_SCFG3 0x004c -#define HMATRIX2_SCFG4 0x0050 -#define HMATRIX2_SCFG5 0x0054 -#define HMATRIX2_SCFG6 0x0058 -#define HMATRIX2_SCFG7 0x005c -#define HMATRIX2_SCFG8 0x0060 -#define HMATRIX2_SCFG9 0x0064 -#define HMATRIX2_SCFG10 0x0068 -#define HMATRIX2_SCFG11 0x006c -#define HMATRIX2_SCFG12 0x0070 -#define HMATRIX2_SCFG13 0x0074 -#define HMATRIX2_SCFG14 0x0078 -#define HMATRIX2_SCFG15 0x007c -#define HMATRIX2_PRAS0 0x0080 -#define HMATRIX2_PRBS0 0x0084 -#define HMATRIX2_PRAS1 0x0088 -#define HMATRIX2_PRBS1 0x008c -#define HMATRIX2_PRAS2 0x0090 -#define HMATRIX2_PRBS2 0x0094 -#define HMATRIX2_PRAS3 0x0098 -#define HMATRIX2_PRBS3 0x009c -#define HMATRIX2_PRAS4 0x00a0 -#define HMATRIX2_PRBS4 0x00a4 -#define HMATRIX2_PRAS5 0x00a8 -#define HMATRIX2_PRBS5 0x00ac -#define HMATRIX2_PRAS6 0x00b0 -#define HMATRIX2_PRBS6 0x00b4 -#define HMATRIX2_PRAS7 0x00b8 -#define HMATRIX2_PRBS7 0x00bc -#define HMATRIX2_PRAS8 0x00c0 -#define HMATRIX2_PRBS8 0x00c4 -#define HMATRIX2_PRAS9 0x00c8 -#define HMATRIX2_PRBS9 0x00cc -#define HMATRIX2_PRAS10 0x00d0 -#define HMATRIX2_PRBS10 0x00d4 -#define HMATRIX2_PRAS11 0x00d8 -#define HMATRIX2_PRBS11 0x00dc -#define HMATRIX2_PRAS12 0x00e0 -#define HMATRIX2_PRBS12 0x00e4 -#define HMATRIX2_PRAS13 0x00e8 -#define HMATRIX2_PRBS13 0x00ec -#define HMATRIX2_PRAS14 0x00f0 -#define HMATRIX2_PRBS14 0x00f4 -#define HMATRIX2_PRAS15 0x00f8 -#define HMATRIX2_PRBS15 0x00fc -#define HMATRIX2_MRCR 0x0100 -#define HMATRIX2_SFR0 0x0110 -#define HMATRIX2_SFR1 0x0114 -#define HMATRIX2_SFR2 0x0118 -#define HMATRIX2_SFR3 0x011c -#define HMATRIX2_SFR4 0x0120 -#define HMATRIX2_SFR5 0x0124 -#define HMATRIX2_SFR6 0x0128 -#define HMATRIX2_SFR7 0x012c -#define HMATRIX2_SFR8 0x0130 -#define HMATRIX2_SFR9 0x0134 -#define HMATRIX2_SFR10 0x0138 -#define HMATRIX2_SFR11 0x013c -#define HMATRIX2_SFR12 0x0140 -#define HMATRIX2_SFR13 0x0144 -#define HMATRIX2_SFR14 0x0148 -#define HMATRIX2_SFR15 0x014c -#define HMATRIX2_VERSION 0x01fc - -/* Bitfields in MCFG0 */ -#define HMATRIX2_ULBT_OFFSET 0 -#define HMATRIX2_ULBT_SIZE 3 - -/* Bitfields in SCFG0 */ -#define HMATRIX2_SLOT_CYCLE_OFFSET 0 -#define HMATRIX2_SLOT_CYCLE_SIZE 8 -#define HMATRIX2_DEFMSTR_TYPE_OFFSET 16 -#define HMATRIX2_DEFMSTR_TYPE_SIZE 2 -#define HMATRIX2_FIXED_DEFMSTR_OFFSET 18 -#define HMATRIX2_FIXED_DEFMSTR_SIZE 4 -#define HMATRIX2_ARBT_OFFSET 24 -#define HMATRIX2_ARBT_SIZE 2 - -/* Bitfields in PRAS0 */ -#define HMATRIX2_M0PR_OFFSET 0 -#define HMATRIX2_M0PR_SIZE 4 -#define HMATRIX2_M1PR_OFFSET 4 -#define HMATRIX2_M1PR_SIZE 4 -#define HMATRIX2_M2PR_OFFSET 8 -#define HMATRIX2_M2PR_SIZE 4 -#define HMATRIX2_M3PR_OFFSET 12 -#define HMATRIX2_M3PR_SIZE 4 -#define HMATRIX2_M4PR_OFFSET 16 -#define HMATRIX2_M4PR_SIZE 4 -#define HMATRIX2_M5PR_OFFSET 20 -#define HMATRIX2_M5PR_SIZE 4 -#define HMATRIX2_M6PR_OFFSET 24 -#define HMATRIX2_M6PR_SIZE 4 -#define HMATRIX2_M7PR_OFFSET 28 -#define HMATRIX2_M7PR_SIZE 4 - -/* Bitfields in PRBS0 */ -#define HMATRIX2_M8PR_OFFSET 0 -#define HMATRIX2_M8PR_SIZE 4 -#define HMATRIX2_M9PR_OFFSET 4 -#define HMATRIX2_M9PR_SIZE 4 -#define HMATRIX2_M10PR_OFFSET 8 -#define HMATRIX2_M10PR_SIZE 4 -#define HMATRIX2_M11PR_OFFSET 12 -#define HMATRIX2_M11PR_SIZE 4 -#define HMATRIX2_M12PR_OFFSET 16 -#define HMATRIX2_M12PR_SIZE 4 -#define HMATRIX2_M13PR_OFFSET 20 -#define HMATRIX2_M13PR_SIZE 4 -#define HMATRIX2_M14PR_OFFSET 24 -#define HMATRIX2_M14PR_SIZE 4 -#define HMATRIX2_M15PR_OFFSET 28 -#define HMATRIX2_M15PR_SIZE 4 - -/* Bitfields in MRCR */ -#define HMATRIX2_RBC0_OFFSET 0 -#define HMATRIX2_RBC0_SIZE 1 -#define HMATRIX2_RBC1_OFFSET 1 -#define HMATRIX2_RBC1_SIZE 1 -#define HMATRIX2_RBC2_OFFSET 2 -#define HMATRIX2_RBC2_SIZE 1 -#define HMATRIX2_RBC3_OFFSET 3 -#define HMATRIX2_RBC3_SIZE 1 -#define HMATRIX2_RBC4_OFFSET 4 -#define HMATRIX2_RBC4_SIZE 1 -#define HMATRIX2_RBC5_OFFSET 5 -#define HMATRIX2_RBC5_SIZE 1 -#define HMATRIX2_RBC6_OFFSET 6 -#define HMATRIX2_RBC6_SIZE 1 -#define HMATRIX2_RBC7_OFFSET 7 -#define HMATRIX2_RBC7_SIZE 1 -#define HMATRIX2_RBC8_OFFSET 8 -#define HMATRIX2_RBC8_SIZE 1 -#define HMATRIX2_RBC9_OFFSET 9 -#define HMATRIX2_RBC9_SIZE 1 -#define HMATRIX2_RBC10_OFFSET 10 -#define HMATRIX2_RBC10_SIZE 1 -#define HMATRIX2_RBC11_OFFSET 11 -#define HMATRIX2_RBC11_SIZE 1 -#define HMATRIX2_RBC12_OFFSET 12 -#define HMATRIX2_RBC12_SIZE 1 -#define HMATRIX2_RBC13_OFFSET 13 -#define HMATRIX2_RBC13_SIZE 1 -#define HMATRIX2_RBC14_OFFSET 14 -#define HMATRIX2_RBC14_SIZE 1 -#define HMATRIX2_RBC15_OFFSET 15 -#define HMATRIX2_RBC15_SIZE 1 - -/* Bitfields in SFR0 */ -#define HMATRIX2_SFR_OFFSET 0 -#define HMATRIX2_SFR_SIZE 32 - -/* Bitfields in SFR4 */ -#define HMATRIX2_CS1A_OFFSET 1 -#define HMATRIX2_CS1A_SIZE 1 -#define HMATRIX2_CS3A_OFFSET 3 -#define HMATRIX2_CS3A_SIZE 1 -#define HMATRIX2_CS4A_OFFSET 4 -#define HMATRIX2_CS4A_SIZE 1 -#define HMATRIX2_CS5A_OFFSET 5 -#define HMATRIX2_CS5A_SIZE 1 -#define HMATRIX2_DBPUC_OFFSET 8 -#define HMATRIX2_DBPUC_SIZE 1 - -/* Bitfields in VERSION */ -#define HMATRIX2_VERSION_OFFSET 0 -#define HMATRIX2_VERSION_SIZE 12 -#define HMATRIX2_MFN_OFFSET 16 -#define HMATRIX2_MFN_SIZE 3 - -/* Constants for ULBT */ -#define HMATRIX2_ULBT_INFINITE 0 -#define HMATRIX2_ULBT_SINGLE 1 -#define HMATRIX2_ULBT_FOUR_BEAT 2 -#define HMATRIX2_ULBT_SIXTEEN_BEAT 4 - -/* Constants for DEFMSTR_TYPE */ -#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT 0 -#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT 1 -#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT 2 - -/* Constants for ARBT */ -#define HMATRIX2_ARBT_ROUND_ROBIN 0 -#define HMATRIX2_ARBT_FIXED_PRIORITY 1 - -/* Bit manipulation macros */ -#define HMATRIX2_BIT(name) \ - (1 << HMATRIX2_##name##_OFFSET) -#define HMATRIX2_BF(name,value) \ - (((value) & ((1 << HMATRIX2_##name##_SIZE) - 1)) \ - << HMATRIX2_##name##_OFFSET) -#define HMATRIX2_BFEXT(name,value) \ - (((value) >> HMATRIX2_##name##_OFFSET) \ - & ((1 << HMATRIX2_##name##_SIZE) - 1)) -#define HMATRIX2_BFINS(name,value,old) \ - (((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1) \ - << HMATRIX2_##name##_OFFSET)) \ - | HMATRIX2_BF(name,value)) - -/* Register access macros */ -#define hmatrix2_readl(reg) \ - readl((void *)HMATRIX_BASE + HMATRIX2_##reg) -#define hmatrix2_writel(reg,value) \ - writel((value), (void *)HMATRIX_BASE + HMATRIX2_##reg) - -#endif /* __ASM_AVR32_HMATRIX2_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/memory-map.h b/include/asm-avr32/arch-at32ap7000/memory-map.h deleted file mode 100644 index 5513e88e7b0..00000000000 --- a/include/asm-avr32/arch-at32ap7000/memory-map.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __AT32AP7000_MEMORY_MAP_H__ -#define __AT32AP7000_MEMORY_MAP_H__ - -/* Devices on the High Speed Bus (HSB) */ -#define LCDC_BASE 0xFF000000 -#define DMAC_BASE 0xFF200000 -#define USB_FIFO 0xFF300000 - -/* Devices on Peripheral Bus A (PBA) */ -#define SPI0_BASE 0xFFE00000 -#define SPI1_BASE 0xFFE00400 -#define TWI_BASE 0xFFE00800 -#define USART0_BASE 0xFFE00C00 -#define USART1_BASE 0xFFE01000 -#define USART2_BASE 0xFFE01400 -#define USART3_BASE 0xFFE01800 -#define SSC0_BASE 0xFFE01C00 -#define SSC1_BASE 0xFFE02000 -#define SSC2_BASE 0xFFE02400 -#define PIOA_BASE 0xFFE02800 -#define PIOB_BASE 0xFFE02C00 -#define PIOC_BASE 0xFFE03000 -#define PIOD_BASE 0xFFE03400 -#define PIOE_BASE 0xFFE03800 -#define PSIF_BASE 0xFFE03C00 - -/* Devices on Peripheral Bus B (PBB) */ -#define SM_BASE 0xFFF00000 -#define INTC_BASE 0xFFF00400 -#define HMATRIX_BASE 0xFFF00800 -#define TIMER0_BASE 0xFFF00C00 -#define TIMER1_BASE 0xFFF01000 -#define PWM_BASE 0xFFF01400 -#define MACB0_BASE 0xFFF01800 -#define MACB1_BASE 0xFFF01C00 -#define DAC_BASE 0xFFF02000 -#define MMCI_BASE 0xFFF02400 -#define AUDIOC_BASE 0xFFF02800 -#define HISI_BASE 0xFFF02C00 -#define USB_BASE 0xFFF03000 -#define HSMC_BASE 0xFFF03400 -#define HSDRAMC_BASE 0xFFF03800 -#define ECC_BASE 0xFFF03C00 - -#endif /* __AT32AP7000_MEMORY_MAP_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/mmc.h b/include/asm-avr32/arch-at32ap7000/mmc.h deleted file mode 100644 index fcfbbb3c6cb..00000000000 --- a/include/asm-avr32/arch-at32ap7000/mmc.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_MMC_H -#define __ASM_AVR32_MMC_H - -struct mmc_cid { - unsigned long psn; - unsigned short oid; - unsigned char mid; - unsigned char prv; - unsigned char mdt; - char pnm[7]; -}; - -struct mmc_csd -{ - u8 csd_structure:2, - spec_vers:4, - rsvd1:2; - u8 taac; - u8 nsac; - u8 tran_speed; - u16 ccc:12, - read_bl_len:4; - u64 read_bl_partial:1, - write_blk_misalign:1, - read_blk_misalign:1, - dsr_imp:1, - rsvd2:2, - c_size:12, - vdd_r_curr_min:3, - vdd_r_curr_max:3, - vdd_w_curr_min:3, - vdd_w_curr_max:3, - c_size_mult:3, - sector_size:5, - erase_grp_size:5, - wp_grp_size:5, - wp_grp_enable:1, - default_ecc:2, - r2w_factor:3, - write_bl_len:4, - write_bl_partial:1, - rsvd3:5; - u8 file_format_grp:1, - copy:1, - perm_write_protect:1, - tmp_write_protect:1, - file_format:2, - ecc:2; - u8 crc:7; - u8 one:1; -}; - -/* MMC Command numbers */ -#define MMC_CMD_GO_IDLE_STATE 0 -#define MMC_CMD_SEND_OP_COND 1 -#define MMC_CMD_ALL_SEND_CID 2 -#define MMC_CMD_SET_RELATIVE_ADDR 3 -#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3 -#define MMC_CMD_SET_DSR 4 -#define MMC_CMD_SELECT_CARD 7 -#define MMC_CMD_SEND_CSD 9 -#define MMC_CMD_SEND_CID 10 -#define MMC_CMD_SEND_STATUS 13 -#define MMC_CMD_SET_BLOCKLEN 16 -#define MMC_CMD_READ_SINGLE_BLOCK 17 -#define MMC_CMD_READ_MULTIPLE_BLOCK 18 -#define MMC_CMD_WRITE_BLOCK 24 -#define MMC_CMD_APP_CMD 55 - -#define MMC_ACMD_SD_SEND_OP_COND 41 - -#define R1_ILLEGAL_COMMAND (1 << 22) -#define R1_APP_CMD (1 << 5) - -#endif /* __ASM_AVR32_MMC_H */ diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h new file mode 100644 index 00000000000..7e20d97b7f9 --- /dev/null +++ b/include/asm-avr32/arch-at32ap700x/clk.h @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_ARCH_CLK_H__ +#define __ASM_AVR32_ARCH_CLK_H__ + +#ifdef CONFIG_PLL +#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) +#else +#define MAIN_CLK_RATE (CFG_OSC0_HZ) +#endif + +static inline unsigned long get_cpu_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_CPU; +} +static inline unsigned long get_hsb_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_HSB; +} +static inline unsigned long get_pba_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_PBA; +} +static inline unsigned long get_pbb_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_PBB; +} + +/* Accessors for specific devices. More will be added as needed. */ +static inline unsigned long get_sdram_clk_rate(void) +{ + return get_hsb_clk_rate(); +} +static inline unsigned long get_usart_clk_rate(unsigned int dev_id) +{ + return get_pba_clk_rate(); +} +static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) +{ + return get_pbb_clk_rate(); +} +static inline unsigned long get_macb_hclk_rate(unsigned int dev_id) +{ + return get_hsb_clk_rate(); +} +static inline unsigned long get_mci_clk_rate(void) +{ + return get_pbb_clk_rate(); +} + +#endif /* __ASM_AVR32_ARCH_CLK_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/gpio.h b/include/asm-avr32/arch-at32ap700x/gpio.h new file mode 100644 index 00000000000..e4812d4d08b --- /dev/null +++ b/include/asm-avr32/arch-at32ap700x/gpio.h @@ -0,0 +1,212 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_ARCH_GPIO_H__ +#define __ASM_AVR32_ARCH_GPIO_H__ + +#include + +#define NR_GPIO_CONTROLLERS 5 + +/* + * Pin numbers identifying specific GPIO pins on the chip. + */ +#define GPIO_PIOA_BASE (0) +#define GPIO_PIN_PA0 (GPIO_PIOA_BASE + 0) +#define GPIO_PIN_PA1 (GPIO_PIOA_BASE + 1) +#define GPIO_PIN_PA2 (GPIO_PIOA_BASE + 2) +#define GPIO_PIN_PA3 (GPIO_PIOA_BASE + 3) +#define GPIO_PIN_PA4 (GPIO_PIOA_BASE + 4) +#define GPIO_PIN_PA5 (GPIO_PIOA_BASE + 5) +#define GPIO_PIN_PA6 (GPIO_PIOA_BASE + 6) +#define GPIO_PIN_PA7 (GPIO_PIOA_BASE + 7) +#define GPIO_PIN_PA8 (GPIO_PIOA_BASE + 8) +#define GPIO_PIN_PA9 (GPIO_PIOA_BASE + 9) +#define GPIO_PIN_PA10 (GPIO_PIOA_BASE + 10) +#define GPIO_PIN_PA11 (GPIO_PIOA_BASE + 11) +#define GPIO_PIN_PA12 (GPIO_PIOA_BASE + 12) +#define GPIO_PIN_PA13 (GPIO_PIOA_BASE + 13) +#define GPIO_PIN_PA14 (GPIO_PIOA_BASE + 14) +#define GPIO_PIN_PA15 (GPIO_PIOA_BASE + 15) +#define GPIO_PIN_PA16 (GPIO_PIOA_BASE + 16) +#define GPIO_PIN_PA17 (GPIO_PIOA_BASE + 17) +#define GPIO_PIN_PA18 (GPIO_PIOA_BASE + 18) +#define GPIO_PIN_PA19 (GPIO_PIOA_BASE + 19) +#define GPIO_PIN_PA20 (GPIO_PIOA_BASE + 20) +#define GPIO_PIN_PA21 (GPIO_PIOA_BASE + 21) +#define GPIO_PIN_PA22 (GPIO_PIOA_BASE + 22) +#define GPIO_PIN_PA23 (GPIO_PIOA_BASE + 23) +#define GPIO_PIN_PA24 (GPIO_PIOA_BASE + 24) +#define GPIO_PIN_PA25 (GPIO_PIOA_BASE + 25) +#define GPIO_PIN_PA26 (GPIO_PIOA_BASE + 26) +#define GPIO_PIN_PA27 (GPIO_PIOA_BASE + 27) +#define GPIO_PIN_PA28 (GPIO_PIOA_BASE + 28) +#define GPIO_PIN_PA29 (GPIO_PIOA_BASE + 29) +#define GPIO_PIN_PA30 (GPIO_PIOA_BASE + 30) +#define GPIO_PIN_PA31 (GPIO_PIOA_BASE + 31) + +#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32) +#define GPIO_PIN_PB0 (GPIO_PIOB_BASE + 0) +#define GPIO_PIN_PB1 (GPIO_PIOB_BASE + 1) +#define GPIO_PIN_PB2 (GPIO_PIOB_BASE + 2) +#define GPIO_PIN_PB3 (GPIO_PIOB_BASE + 3) +#define GPIO_PIN_PB4 (GPIO_PIOB_BASE + 4) +#define GPIO_PIN_PB5 (GPIO_PIOB_BASE + 5) +#define GPIO_PIN_PB6 (GPIO_PIOB_BASE + 6) +#define GPIO_PIN_PB7 (GPIO_PIOB_BASE + 7) +#define GPIO_PIN_PB8 (GPIO_PIOB_BASE + 8) +#define GPIO_PIN_PB9 (GPIO_PIOB_BASE + 9) +#define GPIO_PIN_PB10 (GPIO_PIOB_BASE + 10) +#define GPIO_PIN_PB11 (GPIO_PIOB_BASE + 11) +#define GPIO_PIN_PB12 (GPIO_PIOB_BASE + 12) +#define GPIO_PIN_PB13 (GPIO_PIOB_BASE + 13) +#define GPIO_PIN_PB14 (GPIO_PIOB_BASE + 14) +#define GPIO_PIN_PB15 (GPIO_PIOB_BASE + 15) +#define GPIO_PIN_PB16 (GPIO_PIOB_BASE + 16) +#define GPIO_PIN_PB17 (GPIO_PIOB_BASE + 17) +#define GPIO_PIN_PB18 (GPIO_PIOB_BASE + 18) +#define GPIO_PIN_PB19 (GPIO_PIOB_BASE + 19) +#define GPIO_PIN_PB20 (GPIO_PIOB_BASE + 20) +#define GPIO_PIN_PB21 (GPIO_PIOB_BASE + 21) +#define GPIO_PIN_PB22 (GPIO_PIOB_BASE + 22) +#define GPIO_PIN_PB23 (GPIO_PIOB_BASE + 23) +#define GPIO_PIN_PB24 (GPIO_PIOB_BASE + 24) +#define GPIO_PIN_PB25 (GPIO_PIOB_BASE + 25) +#define GPIO_PIN_PB26 (GPIO_PIOB_BASE + 26) +#define GPIO_PIN_PB27 (GPIO_PIOB_BASE + 27) +#define GPIO_PIN_PB28 (GPIO_PIOB_BASE + 28) +#define GPIO_PIN_PB29 (GPIO_PIOB_BASE + 29) +#define GPIO_PIN_PB30 (GPIO_PIOB_BASE + 30) + +#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32) +#define GPIO_PIN_PC0 (GPIO_PIOC_BASE + 0) +#define GPIO_PIN_PC1 (GPIO_PIOC_BASE + 1) +#define GPIO_PIN_PC2 (GPIO_PIOC_BASE + 2) +#define GPIO_PIN_PC3 (GPIO_PIOC_BASE + 3) +#define GPIO_PIN_PC4 (GPIO_PIOC_BASE + 4) +#define GPIO_PIN_PC5 (GPIO_PIOC_BASE + 5) +#define GPIO_PIN_PC6 (GPIO_PIOC_BASE + 6) +#define GPIO_PIN_PC7 (GPIO_PIOC_BASE + 7) +#define GPIO_PIN_PC8 (GPIO_PIOC_BASE + 8) +#define GPIO_PIN_PC9 (GPIO_PIOC_BASE + 9) +#define GPIO_PIN_PC10 (GPIO_PIOC_BASE + 10) +#define GPIO_PIN_PC11 (GPIO_PIOC_BASE + 11) +#define GPIO_PIN_PC12 (GPIO_PIOC_BASE + 12) +#define GPIO_PIN_PC13 (GPIO_PIOC_BASE + 13) +#define GPIO_PIN_PC14 (GPIO_PIOC_BASE + 14) +#define GPIO_PIN_PC15 (GPIO_PIOC_BASE + 15) +#define GPIO_PIN_PC16 (GPIO_PIOC_BASE + 16) +#define GPIO_PIN_PC17 (GPIO_PIOC_BASE + 17) +#define GPIO_PIN_PC18 (GPIO_PIOC_BASE + 18) +#define GPIO_PIN_PC19 (GPIO_PIOC_BASE + 19) +#define GPIO_PIN_PC20 (GPIO_PIOC_BASE + 20) +#define GPIO_PIN_PC21 (GPIO_PIOC_BASE + 21) +#define GPIO_PIN_PC22 (GPIO_PIOC_BASE + 22) +#define GPIO_PIN_PC23 (GPIO_PIOC_BASE + 23) +#define GPIO_PIN_PC24 (GPIO_PIOC_BASE + 24) +#define GPIO_PIN_PC25 (GPIO_PIOC_BASE + 25) +#define GPIO_PIN_PC26 (GPIO_PIOC_BASE + 26) +#define GPIO_PIN_PC27 (GPIO_PIOC_BASE + 27) +#define GPIO_PIN_PC28 (GPIO_PIOC_BASE + 28) +#define GPIO_PIN_PC29 (GPIO_PIOC_BASE + 29) +#define GPIO_PIN_PC30 (GPIO_PIOC_BASE + 30) +#define GPIO_PIN_PC31 (GPIO_PIOC_BASE + 31) + +#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32) +#define GPIO_PIN_PD0 (GPIO_PIOD_BASE + 0) +#define GPIO_PIN_PD1 (GPIO_PIOD_BASE + 1) +#define GPIO_PIN_PD2 (GPIO_PIOD_BASE + 2) +#define GPIO_PIN_PD3 (GPIO_PIOD_BASE + 3) +#define GPIO_PIN_PD4 (GPIO_PIOD_BASE + 4) +#define GPIO_PIN_PD5 (GPIO_PIOD_BASE + 5) +#define GPIO_PIN_PD6 (GPIO_PIOD_BASE + 6) +#define GPIO_PIN_PD7 (GPIO_PIOD_BASE + 7) +#define GPIO_PIN_PD8 (GPIO_PIOD_BASE + 8) +#define GPIO_PIN_PD9 (GPIO_PIOD_BASE + 9) +#define GPIO_PIN_PD10 (GPIO_PIOD_BASE + 10) +#define GPIO_PIN_PD11 (GPIO_PIOD_BASE + 11) +#define GPIO_PIN_PD12 (GPIO_PIOD_BASE + 12) +#define GPIO_PIN_PD13 (GPIO_PIOD_BASE + 13) +#define GPIO_PIN_PD14 (GPIO_PIOD_BASE + 14) +#define GPIO_PIN_PD15 (GPIO_PIOD_BASE + 15) +#define GPIO_PIN_PD16 (GPIO_PIOD_BASE + 16) +#define GPIO_PIN_PD17 (GPIO_PIOD_BASE + 17) + +#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32) +#define GPIO_PIN_PE0 (GPIO_PIOE_BASE + 0) +#define GPIO_PIN_PE1 (GPIO_PIOE_BASE + 1) +#define GPIO_PIN_PE2 (GPIO_PIOE_BASE + 2) +#define GPIO_PIN_PE3 (GPIO_PIOE_BASE + 3) +#define GPIO_PIN_PE4 (GPIO_PIOE_BASE + 4) +#define GPIO_PIN_PE5 (GPIO_PIOE_BASE + 5) +#define GPIO_PIN_PE6 (GPIO_PIOE_BASE + 6) +#define GPIO_PIN_PE7 (GPIO_PIOE_BASE + 7) +#define GPIO_PIN_PE8 (GPIO_PIOE_BASE + 8) +#define GPIO_PIN_PE9 (GPIO_PIOE_BASE + 9) +#define GPIO_PIN_PE10 (GPIO_PIOE_BASE + 10) +#define GPIO_PIN_PE11 (GPIO_PIOE_BASE + 11) +#define GPIO_PIN_PE12 (GPIO_PIOE_BASE + 12) +#define GPIO_PIN_PE13 (GPIO_PIOE_BASE + 13) +#define GPIO_PIN_PE14 (GPIO_PIOE_BASE + 14) +#define GPIO_PIN_PE15 (GPIO_PIOE_BASE + 15) +#define GPIO_PIN_PE16 (GPIO_PIOE_BASE + 16) +#define GPIO_PIN_PE17 (GPIO_PIOE_BASE + 17) +#define GPIO_PIN_PE18 (GPIO_PIOE_BASE + 18) +#define GPIO_PIN_PE19 (GPIO_PIOE_BASE + 19) +#define GPIO_PIN_PE20 (GPIO_PIOE_BASE + 20) +#define GPIO_PIN_PE21 (GPIO_PIOE_BASE + 21) +#define GPIO_PIN_PE22 (GPIO_PIOE_BASE + 22) +#define GPIO_PIN_PE23 (GPIO_PIOE_BASE + 23) +#define GPIO_PIN_PE24 (GPIO_PIOE_BASE + 24) +#define GPIO_PIN_PE25 (GPIO_PIOE_BASE + 25) +#define GPIO_PIN_PE26 (GPIO_PIOE_BASE + 26) + +static inline void *gpio_pin_to_addr(unsigned int pin) +{ + switch (pin >> 5) { + case 0: + return (void *)PIOA_BASE; + case 1: + return (void *)PIOB_BASE; + case 2: + return (void *)PIOC_BASE; + case 3: + return (void *)PIOD_BASE; + case 4: + return (void *)PIOE_BASE; + default: + return NULL; + } +} + +void gpio_select_periph_A(unsigned int pin, int use_pullup); +void gpio_select_periph_B(unsigned int pin, int use_pullup); + +void gpio_enable_ebi(void); +void gpio_enable_usart0(void); +void gpio_enable_usart1(void); +void gpio_enable_usart2(void); +void gpio_enable_usart3(void); +void gpio_enable_macb0(void); +void gpio_enable_macb1(void); +void gpio_enable_mmci(void); + +#endif /* __ASM_AVR32_ARCH_GPIO_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/hmatrix2.h b/include/asm-avr32/arch-at32ap700x/hmatrix2.h new file mode 100644 index 00000000000..b0e787a92f9 --- /dev/null +++ b/include/asm-avr32/arch-at32ap700x/hmatrix2.h @@ -0,0 +1,232 @@ +/* + * Register definition for the High-speed Bus Matrix + */ +#ifndef __ASM_AVR32_HMATRIX2_H__ +#define __ASM_AVR32_HMATRIX2_H__ + +/* HMATRIX2 register offsets */ +#define HMATRIX2_MCFG0 0x0000 +#define HMATRIX2_MCFG1 0x0004 +#define HMATRIX2_MCFG2 0x0008 +#define HMATRIX2_MCFG3 0x000c +#define HMATRIX2_MCFG4 0x0010 +#define HMATRIX2_MCFG5 0x0014 +#define HMATRIX2_MCFG6 0x0018 +#define HMATRIX2_MCFG7 0x001c +#define HMATRIX2_MCFG8 0x0020 +#define HMATRIX2_MCFG9 0x0024 +#define HMATRIX2_MCFG10 0x0028 +#define HMATRIX2_MCFG11 0x002c +#define HMATRIX2_MCFG12 0x0030 +#define HMATRIX2_MCFG13 0x0034 +#define HMATRIX2_MCFG14 0x0038 +#define HMATRIX2_MCFG15 0x003c +#define HMATRIX2_SCFG0 0x0040 +#define HMATRIX2_SCFG1 0x0044 +#define HMATRIX2_SCFG2 0x0048 +#define HMATRIX2_SCFG3 0x004c +#define HMATRIX2_SCFG4 0x0050 +#define HMATRIX2_SCFG5 0x0054 +#define HMATRIX2_SCFG6 0x0058 +#define HMATRIX2_SCFG7 0x005c +#define HMATRIX2_SCFG8 0x0060 +#define HMATRIX2_SCFG9 0x0064 +#define HMATRIX2_SCFG10 0x0068 +#define HMATRIX2_SCFG11 0x006c +#define HMATRIX2_SCFG12 0x0070 +#define HMATRIX2_SCFG13 0x0074 +#define HMATRIX2_SCFG14 0x0078 +#define HMATRIX2_SCFG15 0x007c +#define HMATRIX2_PRAS0 0x0080 +#define HMATRIX2_PRBS0 0x0084 +#define HMATRIX2_PRAS1 0x0088 +#define HMATRIX2_PRBS1 0x008c +#define HMATRIX2_PRAS2 0x0090 +#define HMATRIX2_PRBS2 0x0094 +#define HMATRIX2_PRAS3 0x0098 +#define HMATRIX2_PRBS3 0x009c +#define HMATRIX2_PRAS4 0x00a0 +#define HMATRIX2_PRBS4 0x00a4 +#define HMATRIX2_PRAS5 0x00a8 +#define HMATRIX2_PRBS5 0x00ac +#define HMATRIX2_PRAS6 0x00b0 +#define HMATRIX2_PRBS6 0x00b4 +#define HMATRIX2_PRAS7 0x00b8 +#define HMATRIX2_PRBS7 0x00bc +#define HMATRIX2_PRAS8 0x00c0 +#define HMATRIX2_PRBS8 0x00c4 +#define HMATRIX2_PRAS9 0x00c8 +#define HMATRIX2_PRBS9 0x00cc +#define HMATRIX2_PRAS10 0x00d0 +#define HMATRIX2_PRBS10 0x00d4 +#define HMATRIX2_PRAS11 0x00d8 +#define HMATRIX2_PRBS11 0x00dc +#define HMATRIX2_PRAS12 0x00e0 +#define HMATRIX2_PRBS12 0x00e4 +#define HMATRIX2_PRAS13 0x00e8 +#define HMATRIX2_PRBS13 0x00ec +#define HMATRIX2_PRAS14 0x00f0 +#define HMATRIX2_PRBS14 0x00f4 +#define HMATRIX2_PRAS15 0x00f8 +#define HMATRIX2_PRBS15 0x00fc +#define HMATRIX2_MRCR 0x0100 +#define HMATRIX2_SFR0 0x0110 +#define HMATRIX2_SFR1 0x0114 +#define HMATRIX2_SFR2 0x0118 +#define HMATRIX2_SFR3 0x011c +#define HMATRIX2_SFR4 0x0120 +#define HMATRIX2_SFR5 0x0124 +#define HMATRIX2_SFR6 0x0128 +#define HMATRIX2_SFR7 0x012c +#define HMATRIX2_SFR8 0x0130 +#define HMATRIX2_SFR9 0x0134 +#define HMATRIX2_SFR10 0x0138 +#define HMATRIX2_SFR11 0x013c +#define HMATRIX2_SFR12 0x0140 +#define HMATRIX2_SFR13 0x0144 +#define HMATRIX2_SFR14 0x0148 +#define HMATRIX2_SFR15 0x014c +#define HMATRIX2_VERSION 0x01fc + +/* Bitfields in MCFG0 */ +#define HMATRIX2_ULBT_OFFSET 0 +#define HMATRIX2_ULBT_SIZE 3 + +/* Bitfields in SCFG0 */ +#define HMATRIX2_SLOT_CYCLE_OFFSET 0 +#define HMATRIX2_SLOT_CYCLE_SIZE 8 +#define HMATRIX2_DEFMSTR_TYPE_OFFSET 16 +#define HMATRIX2_DEFMSTR_TYPE_SIZE 2 +#define HMATRIX2_FIXED_DEFMSTR_OFFSET 18 +#define HMATRIX2_FIXED_DEFMSTR_SIZE 4 +#define HMATRIX2_ARBT_OFFSET 24 +#define HMATRIX2_ARBT_SIZE 2 + +/* Bitfields in PRAS0 */ +#define HMATRIX2_M0PR_OFFSET 0 +#define HMATRIX2_M0PR_SIZE 4 +#define HMATRIX2_M1PR_OFFSET 4 +#define HMATRIX2_M1PR_SIZE 4 +#define HMATRIX2_M2PR_OFFSET 8 +#define HMATRIX2_M2PR_SIZE 4 +#define HMATRIX2_M3PR_OFFSET 12 +#define HMATRIX2_M3PR_SIZE 4 +#define HMATRIX2_M4PR_OFFSET 16 +#define HMATRIX2_M4PR_SIZE 4 +#define HMATRIX2_M5PR_OFFSET 20 +#define HMATRIX2_M5PR_SIZE 4 +#define HMATRIX2_M6PR_OFFSET 24 +#define HMATRIX2_M6PR_SIZE 4 +#define HMATRIX2_M7PR_OFFSET 28 +#define HMATRIX2_M7PR_SIZE 4 + +/* Bitfields in PRBS0 */ +#define HMATRIX2_M8PR_OFFSET 0 +#define HMATRIX2_M8PR_SIZE 4 +#define HMATRIX2_M9PR_OFFSET 4 +#define HMATRIX2_M9PR_SIZE 4 +#define HMATRIX2_M10PR_OFFSET 8 +#define HMATRIX2_M10PR_SIZE 4 +#define HMATRIX2_M11PR_OFFSET 12 +#define HMATRIX2_M11PR_SIZE 4 +#define HMATRIX2_M12PR_OFFSET 16 +#define HMATRIX2_M12PR_SIZE 4 +#define HMATRIX2_M13PR_OFFSET 20 +#define HMATRIX2_M13PR_SIZE 4 +#define HMATRIX2_M14PR_OFFSET 24 +#define HMATRIX2_M14PR_SIZE 4 +#define HMATRIX2_M15PR_OFFSET 28 +#define HMATRIX2_M15PR_SIZE 4 + +/* Bitfields in MRCR */ +#define HMATRIX2_RBC0_OFFSET 0 +#define HMATRIX2_RBC0_SIZE 1 +#define HMATRIX2_RBC1_OFFSET 1 +#define HMATRIX2_RBC1_SIZE 1 +#define HMATRIX2_RBC2_OFFSET 2 +#define HMATRIX2_RBC2_SIZE 1 +#define HMATRIX2_RBC3_OFFSET 3 +#define HMATRIX2_RBC3_SIZE 1 +#define HMATRIX2_RBC4_OFFSET 4 +#define HMATRIX2_RBC4_SIZE 1 +#define HMATRIX2_RBC5_OFFSET 5 +#define HMATRIX2_RBC5_SIZE 1 +#define HMATRIX2_RBC6_OFFSET 6 +#define HMATRIX2_RBC6_SIZE 1 +#define HMATRIX2_RBC7_OFFSET 7 +#define HMATRIX2_RBC7_SIZE 1 +#define HMATRIX2_RBC8_OFFSET 8 +#define HMATRIX2_RBC8_SIZE 1 +#define HMATRIX2_RBC9_OFFSET 9 +#define HMATRIX2_RBC9_SIZE 1 +#define HMATRIX2_RBC10_OFFSET 10 +#define HMATRIX2_RBC10_SIZE 1 +#define HMATRIX2_RBC11_OFFSET 11 +#define HMATRIX2_RBC11_SIZE 1 +#define HMATRIX2_RBC12_OFFSET 12 +#define HMATRIX2_RBC12_SIZE 1 +#define HMATRIX2_RBC13_OFFSET 13 +#define HMATRIX2_RBC13_SIZE 1 +#define HMATRIX2_RBC14_OFFSET 14 +#define HMATRIX2_RBC14_SIZE 1 +#define HMATRIX2_RBC15_OFFSET 15 +#define HMATRIX2_RBC15_SIZE 1 + +/* Bitfields in SFR0 */ +#define HMATRIX2_SFR_OFFSET 0 +#define HMATRIX2_SFR_SIZE 32 + +/* Bitfields in SFR4 */ +#define HMATRIX2_CS1A_OFFSET 1 +#define HMATRIX2_CS1A_SIZE 1 +#define HMATRIX2_CS3A_OFFSET 3 +#define HMATRIX2_CS3A_SIZE 1 +#define HMATRIX2_CS4A_OFFSET 4 +#define HMATRIX2_CS4A_SIZE 1 +#define HMATRIX2_CS5A_OFFSET 5 +#define HMATRIX2_CS5A_SIZE 1 +#define HMATRIX2_DBPUC_OFFSET 8 +#define HMATRIX2_DBPUC_SIZE 1 + +/* Bitfields in VERSION */ +#define HMATRIX2_VERSION_OFFSET 0 +#define HMATRIX2_VERSION_SIZE 12 +#define HMATRIX2_MFN_OFFSET 16 +#define HMATRIX2_MFN_SIZE 3 + +/* Constants for ULBT */ +#define HMATRIX2_ULBT_INFINITE 0 +#define HMATRIX2_ULBT_SINGLE 1 +#define HMATRIX2_ULBT_FOUR_BEAT 2 +#define HMATRIX2_ULBT_SIXTEEN_BEAT 4 + +/* Constants for DEFMSTR_TYPE */ +#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT 0 +#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT 1 +#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT 2 + +/* Constants for ARBT */ +#define HMATRIX2_ARBT_ROUND_ROBIN 0 +#define HMATRIX2_ARBT_FIXED_PRIORITY 1 + +/* Bit manipulation macros */ +#define HMATRIX2_BIT(name) \ + (1 << HMATRIX2_##name##_OFFSET) +#define HMATRIX2_BF(name,value) \ + (((value) & ((1 << HMATRIX2_##name##_SIZE) - 1)) \ + << HMATRIX2_##name##_OFFSET) +#define HMATRIX2_BFEXT(name,value) \ + (((value) >> HMATRIX2_##name##_OFFSET) \ + & ((1 << HMATRIX2_##name##_SIZE) - 1)) +#define HMATRIX2_BFINS(name,value,old) \ + (((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1) \ + << HMATRIX2_##name##_OFFSET)) \ + | HMATRIX2_BF(name,value)) + +/* Register access macros */ +#define hmatrix2_readl(reg) \ + readl((void *)HMATRIX_BASE + HMATRIX2_##reg) +#define hmatrix2_writel(reg,value) \ + writel((value), (void *)HMATRIX_BASE + HMATRIX2_##reg) + +#endif /* __ASM_AVR32_HMATRIX2_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/memory-map.h b/include/asm-avr32/arch-at32ap700x/memory-map.h new file mode 100644 index 00000000000..5513e88e7b0 --- /dev/null +++ b/include/asm-avr32/arch-at32ap700x/memory-map.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __AT32AP7000_MEMORY_MAP_H__ +#define __AT32AP7000_MEMORY_MAP_H__ + +/* Devices on the High Speed Bus (HSB) */ +#define LCDC_BASE 0xFF000000 +#define DMAC_BASE 0xFF200000 +#define USB_FIFO 0xFF300000 + +/* Devices on Peripheral Bus A (PBA) */ +#define SPI0_BASE 0xFFE00000 +#define SPI1_BASE 0xFFE00400 +#define TWI_BASE 0xFFE00800 +#define USART0_BASE 0xFFE00C00 +#define USART1_BASE 0xFFE01000 +#define USART2_BASE 0xFFE01400 +#define USART3_BASE 0xFFE01800 +#define SSC0_BASE 0xFFE01C00 +#define SSC1_BASE 0xFFE02000 +#define SSC2_BASE 0xFFE02400 +#define PIOA_BASE 0xFFE02800 +#define PIOB_BASE 0xFFE02C00 +#define PIOC_BASE 0xFFE03000 +#define PIOD_BASE 0xFFE03400 +#define PIOE_BASE 0xFFE03800 +#define PSIF_BASE 0xFFE03C00 + +/* Devices on Peripheral Bus B (PBB) */ +#define SM_BASE 0xFFF00000 +#define INTC_BASE 0xFFF00400 +#define HMATRIX_BASE 0xFFF00800 +#define TIMER0_BASE 0xFFF00C00 +#define TIMER1_BASE 0xFFF01000 +#define PWM_BASE 0xFFF01400 +#define MACB0_BASE 0xFFF01800 +#define MACB1_BASE 0xFFF01C00 +#define DAC_BASE 0xFFF02000 +#define MMCI_BASE 0xFFF02400 +#define AUDIOC_BASE 0xFFF02800 +#define HISI_BASE 0xFFF02C00 +#define USB_BASE 0xFFF03000 +#define HSMC_BASE 0xFFF03400 +#define HSDRAMC_BASE 0xFFF03800 +#define ECC_BASE 0xFFF03C00 + +#endif /* __AT32AP7000_MEMORY_MAP_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/mmc.h b/include/asm-avr32/arch-at32ap700x/mmc.h new file mode 100644 index 00000000000..fcfbbb3c6cb --- /dev/null +++ b/include/asm-avr32/arch-at32ap700x/mmc.h @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_MMC_H +#define __ASM_AVR32_MMC_H + +struct mmc_cid { + unsigned long psn; + unsigned short oid; + unsigned char mid; + unsigned char prv; + unsigned char mdt; + char pnm[7]; +}; + +struct mmc_csd +{ + u8 csd_structure:2, + spec_vers:4, + rsvd1:2; + u8 taac; + u8 nsac; + u8 tran_speed; + u16 ccc:12, + read_bl_len:4; + u64 read_bl_partial:1, + write_blk_misalign:1, + read_blk_misalign:1, + dsr_imp:1, + rsvd2:2, + c_size:12, + vdd_r_curr_min:3, + vdd_r_curr_max:3, + vdd_w_curr_min:3, + vdd_w_curr_max:3, + c_size_mult:3, + sector_size:5, + erase_grp_size:5, + wp_grp_size:5, + wp_grp_enable:1, + default_ecc:2, + r2w_factor:3, + write_bl_len:4, + write_bl_partial:1, + rsvd3:5; + u8 file_format_grp:1, + copy:1, + perm_write_protect:1, + tmp_write_protect:1, + file_format:2, + ecc:2; + u8 crc:7; + u8 one:1; +}; + +/* MMC Command numbers */ +#define MMC_CMD_GO_IDLE_STATE 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RELATIVE_ADDR 3 +#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3 +#define MMC_CMD_SET_DSR 4 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_SINGLE_BLOCK 17 +#define MMC_CMD_READ_MULTIPLE_BLOCK 18 +#define MMC_CMD_WRITE_BLOCK 24 +#define MMC_CMD_APP_CMD 55 + +#define MMC_ACMD_SD_SEND_OP_COND 41 + +#define R1_ILLEGAL_COMMAND (1 << 22) +#define R1_APP_CMD (1 << 5) + +#endif /* __ASM_AVR32_MMC_H */ -- cgit v1.3.1 From 5fee84a794a51ec830548cda485a770efb018b92 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Mon, 29 Oct 2007 13:23:33 +0100 Subject: AVR32: Make some AT32AP700x peripherals optional Add a chip-features file providing definitions of the form AT32AP700x_CHIP_HAS_ to indicate the availability of the given peripheral on the currently selected chip. Signed-off-by: Haavard Skinnemoen --- cpu/at32ap/at32ap700x/gpio.c | 7 +++++ include/asm-avr32/arch-at32ap700x/chip-features.h | 34 +++++++++++++++++++++++ include/asm-avr32/arch-at32ap700x/clk.h | 8 ++++++ include/asm-avr32/arch-at32ap700x/gpio.h | 8 ++++++ 4 files changed, 57 insertions(+) create mode 100644 include/asm-avr32/arch-at32ap700x/chip-features.h (limited to 'cpu') diff --git a/cpu/at32ap/at32ap700x/gpio.c b/cpu/at32ap/at32ap700x/gpio.c index 52f5372a607..2d53726b040 100644 --- a/cpu/at32ap/at32ap700x/gpio.c +++ b/cpu/at32ap/at32ap700x/gpio.c @@ -21,6 +21,7 @@ */ #include +#include #include /* @@ -52,6 +53,7 @@ void gpio_enable_ebi(void) #endif } +#ifdef AT32AP700x_CHIP_HAS_USART void gpio_enable_usart0(void) { gpio_select_periph_B(GPIO_PIN_PA8, 0); @@ -75,7 +77,9 @@ void gpio_enable_usart3(void) gpio_select_periph_B(GPIO_PIN_PB18, 0); gpio_select_periph_B(GPIO_PIN_PB19, 0); } +#endif +#ifdef AT32AP700x_CHIP_HAS_MACB void gpio_enable_macb0(void) { gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */ @@ -125,7 +129,9 @@ void gpio_enable_macb1(void) gpio_select_periph_B(GPIO_PIN_PD15, 0); /* SPD */ #endif } +#endif +#ifdef AT32AP700x_CHIP_HAS_MMCI void gpio_enable_mmci(void) { gpio_select_periph_A(GPIO_PIN_PA10, 0); /* CLK */ @@ -135,3 +141,4 @@ void gpio_enable_mmci(void) gpio_select_periph_A(GPIO_PIN_PA14, 0); /* DATA2 */ gpio_select_periph_A(GPIO_PIN_PA15, 0); /* DATA3 */ } +#endif diff --git a/include/asm-avr32/arch-at32ap700x/chip-features.h b/include/asm-avr32/arch-at32ap700x/chip-features.h new file mode 100644 index 00000000000..29b1fd663d0 --- /dev/null +++ b/include/asm-avr32/arch-at32ap700x/chip-features.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2007 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_ARCH_CHIP_FEATURES_H__ +#define __ASM_AVR32_ARCH_CHIP_FEATURES_H__ + +/* Currently, all the AP700x chips have these */ +#define AT32AP700x_CHIP_HAS_USART +#define AT32AP700x_CHIP_HAS_MMCI + +/* Only AP7000 has ethernet interface */ +#ifdef CONFIG_AT32AP7000 +#define AT32AP700x_CHIP_HAS_MACB +#endif + +#endif /* __ASM_AVR32_ARCH_CHIP_FEATURES_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h index 7e20d97b7f9..ea84c0874c0 100644 --- a/include/asm-avr32/arch-at32ap700x/clk.h +++ b/include/asm-avr32/arch-at32ap700x/clk.h @@ -22,6 +22,8 @@ #ifndef __ASM_AVR32_ARCH_CLK_H__ #define __ASM_AVR32_ARCH_CLK_H__ +#include + #ifdef CONFIG_PLL #define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) #else @@ -50,10 +52,13 @@ static inline unsigned long get_sdram_clk_rate(void) { return get_hsb_clk_rate(); } +#ifdef AT32AP700x_CHIP_HAS_USART static inline unsigned long get_usart_clk_rate(unsigned int dev_id) { return get_pba_clk_rate(); } +#endif +#ifdef AT32AP700x_CHIP_HAS_USART static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) { return get_pbb_clk_rate(); @@ -62,9 +67,12 @@ static inline unsigned long get_macb_hclk_rate(unsigned int dev_id) { return get_hsb_clk_rate(); } +#endif +#ifdef AT32AP700x_CHIP_HAS_MMCI static inline unsigned long get_mci_clk_rate(void) { return get_pbb_clk_rate(); } +#endif #endif /* __ASM_AVR32_ARCH_CLK_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/gpio.h b/include/asm-avr32/arch-at32ap700x/gpio.h index e4812d4d08b..b10a3e4f868 100644 --- a/include/asm-avr32/arch-at32ap700x/gpio.h +++ b/include/asm-avr32/arch-at32ap700x/gpio.h @@ -22,6 +22,7 @@ #ifndef __ASM_AVR32_ARCH_GPIO_H__ #define __ASM_AVR32_ARCH_GPIO_H__ +#include #include #define NR_GPIO_CONTROLLERS 5 @@ -201,12 +202,19 @@ void gpio_select_periph_A(unsigned int pin, int use_pullup); void gpio_select_periph_B(unsigned int pin, int use_pullup); void gpio_enable_ebi(void); + +#ifdef AT32AP700x_CHIP_HAS_USART void gpio_enable_usart0(void); void gpio_enable_usart1(void); void gpio_enable_usart2(void); void gpio_enable_usart3(void); +#endif +#ifdef AT32AP700x_CHIP_HAS_MACB void gpio_enable_macb0(void); void gpio_enable_macb1(void); +#endif +#ifdef AT32AP700x_CHIP_HAS_MMCI void gpio_enable_mmci(void); +#endif #endif /* __ASM_AVR32_ARCH_GPIO_H__ */ -- cgit v1.3.1 From 9570bcd87f4db255514f43b6701746c412f8fef0 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Thu, 15 Nov 2007 10:03:45 +0100 Subject: AVR32: Fix wrong pin setup for USART3 As reported by Gerhard Berghofer: in "gpio_enable_usart3" the correct pins for USART 3 are PB17 and PB18 instead of PB18 and PB19. which is obviously correct. There's currently no code that uses USART3, but custom boards may run into problems. Signed-off-by: Haavard Skinnemoen --- cpu/at32ap/at32ap700x/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/at32ap/at32ap700x/gpio.c b/cpu/at32ap/at32ap700x/gpio.c index 2d53726b040..859124a91f6 100644 --- a/cpu/at32ap/at32ap700x/gpio.c +++ b/cpu/at32ap/at32ap700x/gpio.c @@ -74,8 +74,8 @@ void gpio_enable_usart2(void) void gpio_enable_usart3(void) { + gpio_select_periph_B(GPIO_PIN_PB17, 0); gpio_select_periph_B(GPIO_PIN_PB18, 0); - gpio_select_periph_B(GPIO_PIN_PB19, 0); } #endif -- cgit v1.3.1 From 61fb15c516fef5631e305f1976d7b3a679725856 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 27 Dec 2007 01:52:50 +0100 Subject: Fix coding style issues; update CHANGELOG. Signed-off-by: Wolfgang Denk --- CHANGELOG | 752 ++++++++++++++++++++++++++++++++++++++++ MAINTAINERS | 2 +- board/ms7722se/Makefile | 2 +- board/ms7722se/config.mk | 1 - board/ms7722se/lowlevel_init.S | 22 +- board/ms7722se/ms7722se.c | 3 +- board/ms7722se/u-boot.lds | 11 +- board/ms7750se/lowlevel_init.S | 9 +- board/ms7750se/ms7750se.c | 2 +- board/ms7750se/u-boot.lds | 11 +- cpu/sh4/cache.c | 48 +-- cpu/sh4/config.mk | 2 +- cpu/sh4/cpu.c | 2 +- cpu/sh4/interrupts.c | 7 +- cpu/sh4/start.S | 19 +- cpu/sh4/watchdog.c | 6 +- doc/README.marubun-pcmcia | 34 +- doc/README.sh | 19 +- drivers/pcmcia/marubun_pcmcia.c | 12 +- drivers/serial/serial_sh.c | 8 +- examples/stubs.c | 24 +- include/asm-sh/bitops.h | 67 ++-- include/asm-sh/byteorder.h | 1 - include/asm-sh/cpu_sh7722.h | 18 +- include/asm-sh/cpu_sh7750.h | 2 +- include/asm-sh/posix_types.h | 2 +- include/asm-sh/u-boot.h | 2 - include/configs/ms7722se.h | 11 +- include/configs/ms7750se.h | 6 +- lib_sh/Makefile | 2 +- lib_sh/board.c | 4 +- lib_sh/sh_linux.c | 3 +- 32 files changed, 917 insertions(+), 197 deletions(-) (limited to 'cpu') diff --git a/CHANGELOG b/CHANGELOG index 015a4ac01b5..ef5c7ea98b5 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,687 @@ +commit 467bcee11fe26ad422f2de971aa70866079870f2 +Author: Haavard Skinnemoen +Date: Fri Dec 14 15:36:18 2007 +0100 + + cfi_flash: Add manufacturer-specific fixups + + Run fixups based on the JEDEC manufacturer ID independent of the + command set ID. + + This changes current behaviour: Previously, geometry reversal for AMD + chips were done based on the command set ID, while they are now done + based on the JEDEC manufacturer and device ID. + + Also add fixup for top-boot Atmel chips. A fixup is needed for + AT49BV6416(T) too, but since u-boot currently only reads the low byte + of the device ID, there's no way to tell it apart from AT49BV642D, + which should not have this fixup. Since AT49BV642D support is + necessary to get ATNGW100 board support into mainline, I've commented + out the fixup for now. + + Signed-off-by: Haavard Skinnemoen + +commit 0ddf06ddf6b4bd057ad4c5f0dffea7870ba06a2a +Author: Haavard Skinnemoen +Date: Fri Dec 14 15:36:17 2007 +0100 + + cfi_flash: Add cmdset-specific init functions + + Move things like reading JEDEC IDs and fixing up geometry reversal + into separate functions. The geometry reversal fixup is now performed + by altering the qry structure directly, which makes the sector init + code slightly cleaner. + + Signed-off-by: Haavard Skinnemoen + +commit e23741f4a6d8047520ef0d4971762749b3587d32 +Author: Haavard Skinnemoen +Date: Fri Dec 14 15:36:16 2007 +0100 + + cfi_flash: Read whole QRY structure in one go + + Read out the whole CFI Standard Query structure after successful cfi + identification. This allows subsequent code to access this information + directly without having to go through flash_read_uchar() and friends. + + Signed-off-by: Haavard Skinnemoen + +commit df9c25ea04b38a0e05d4f8c73c5cc144cdafa7db +Author: Haavard Skinnemoen +Date: Mon Dec 17 11:02:44 2007 +0100 + + AVR32: Fix logic inversion in disable_interrupts() + + disable_interrupts() should return nonzero if interrupts were + _enabled_ before, not disabled. + + Signed-off-by: Haavard Skinnemoen + +commit acac475212cbedb17b321a363a1c878e2b47b37f +Author: Haavard Skinnemoen +Date: Fri Dec 14 16:51:22 2007 +0100 + + AVR32: Enable interrupts at bootup + + The timer code depends on the timer interrupt to keep track of the + upper 32 bits of the cycle counter. This obviously doesn't work when + interrupts are disabled the whole time. + + Signed-off-by: Haavard Skinnemoen + +commit 9570bcd87f4db255514f43b6701746c412f8fef0 +Author: Haavard Skinnemoen +Date: Thu Nov 15 10:03:45 2007 +0100 + + AVR32: Fix wrong pin setup for USART3 + + As reported by Gerhard Berghofer: + + in "gpio_enable_usart3" the correct pins for USART 3 are PB17 and PB18 + instead of PB18 and PB19. + + which is obviously correct. There's currently no code that uses + USART3, but custom boards may run into problems. + + Signed-off-by: Haavard Skinnemoen + +commit 09ea0de03dcc3ee7af045b0b572227bda2c1c918 +Author: Haavard Skinnemoen +Date: Thu Nov 1 12:44:20 2007 +0100 + + README: Remove ATSTK1000 daughterboard list + + As noted by Kim Phillips, these lists tend to become out of date. + + Signed-off-by: Haavard Skinnemoen + +commit c81cbbad21cb0ae983e2e796211202234cdc8be2 +Author: Haavard Skinnemoen +Date: Tue Oct 30 14:56:36 2007 +0100 + + Add ATSTK100[234] to MAINTAINERS + + Add all the ATSTK1000 daughterboards to MAINTAINERS along with their + "mother". Also update the entry for ATSTK1000 to be not only about the + AP7000 CPU; it's intended to handle all CPUs in the AT32AP family. + + Signed-off-by: Haavard Skinnemoen + +commit 64ff2357b1727213803591813dbc779c924bf772 +Author: Haavard Skinnemoen +Date: Mon Oct 29 13:02:54 2007 +0100 + + AVR32: Add support for the ATSTK1004 board + + ATSTK1004 is a daughterboard for ATSTK1000 with the AT32AP7002 CPU, + which is a derivative of AT32AP7000. + + Signed-off-by: Haavard Skinnemoen + +commit 667568db157f374b85abd7e03596ddd1f0b25681 +Author: Haavard Skinnemoen +Date: Mon Oct 29 13:02:54 2007 +0100 + + AVR32: Add support for the ATSTK1003 board + + ATSTK1003 is a daughterboard for ATSTK1000 with the AT32AP7001 CPU, + which is a derivative of AT32AP7000. + + Signed-off-by: Haavard Skinnemoen + +commit 5fee84a794a51ec830548cda485a770efb018b92 +Author: Haavard Skinnemoen +Date: Mon Oct 29 13:23:33 2007 +0100 + + AVR32: Make some AT32AP700x peripherals optional + + Add a chip-features file providing definitions of the form + + AT32AP700x_CHIP_HAS_ + + to indicate the availability of the given peripheral on the currently + selected chip. + + Signed-off-by: Haavard Skinnemoen + +commit 36f28f8a9605ee5dcfa330482cfc62171261af97 +Author: Haavard Skinnemoen +Date: Mon Oct 29 13:09:56 2007 +0100 + + AVR32: Rename at32ap7000 -> at32ap700x + + The SoC-specific code for all the AT32AP700x CPUs is practically + identical; the only difference is that some chips have less features + than others. By doing this rename, we can add support for the AP7000 + derivatives simply by making some features conditional. + + Signed-off-by: Haavard Skinnemoen + +commit 4d5fa99c73f354e7cf985efcf417ea55ca2f6a5e +Author: Haavard Skinnemoen +Date: Fri Jun 29 18:22:34 2007 +0200 + + atmel_mci: Show SR when block read fails + + Show controller status as well as card status when an error occurs + during block read. + + Signed-off-by: Haavard Skinnemoen + +commit 12d30aa79779c2aa7a998bbae4c075f822a53004 +Author: Haavard Skinnemoen +Date: Thu Dec 13 12:56:34 2007 +0100 + + cfi_flash: Use map_physmem() and unmap_physmem() + + Use map_physmem() and unmap_physmem() to convert from physical to + virtual addresses. This gives the arch a chance to provide an uncached + mapping for flash accesses. + + Signed-off-by: Haavard Skinnemoen + +commit 4d7d6936eb29af7cca330937808312aa5f61454d +Author: Haavard Skinnemoen +Date: Thu Dec 13 12:56:33 2007 +0100 + + Introduce map_physmem() and unmap_physmem() + + map_physmem() returns a virtual address which can be used to access a + given physical address without involving the cache. unmap_physmem() + should be called when the virtual address returned by map_physmem() is + no longer needed. + + This patch adds a stub implementation which simply returns the + physical address cast to a uchar * for all architectures except AVR32, + which converts the physical address to an uncached virtual mapping. + unmap_physmem() is a no-op on all architectures, but if any + architecture needs to do such mappings through the TLB, this is the + hook where those TLB entries can be invalidated. + + Signed-off-by: Haavard Skinnemoen + +commit cdbaefb5f5f03e54455d0439dcf6dbd97ead1f9d +Author: Haavard Skinnemoen +Date: Thu Dec 13 12:56:32 2007 +0100 + + cfi_flash: Introduce read and write accessors + + Introduce flash_read{8,16,32,64) and flash_write{8,16,32,64} and use + them to access the flash memory. This makes it clearer when the flash + is actually being accessed; merely dereferencing a volatile pointer + looks just like any other kind of access. + + Signed-off-by: Haavard Skinnemoen + +commit 812711ce6b3a386125dcf0d6a59588e461abbb87 +Author: Haavard Skinnemoen +Date: Thu Dec 13 12:56:31 2007 +0100 + + Implement __raw_{read,write}[bwl] on all architectures + + This adds implementations of __raw_read[bwl] and __raw_write[bwl] to + m68k, ppc, nios and nios2. The m68k and ppc implementations were taken + from Linux. + + Signed-off-by: Haavard Skinnemoen + +commit be60a9021c82fc5aecd5b2b1fc96f70a9c81bbcd +Author: Haavard Skinnemoen +Date: Sat Oct 6 18:55:36 2007 +0200 + + cfi_flash: Reorder functions and eliminate extra prototypes + + Reorder the functions in cfi_flash.c so that each function only uses + functions that have been defined before it. This allows the static + prototype declarations near the top to be eliminated and might allow + gcc to do a better job inlining functions. + + Signed-off-by: Haavard Skinnemoen + +commit 3055793bcbdf24b1f8117f606ffb766d32eb766f +Author: Haavard Skinnemoen +Date: Thu Dec 13 12:56:29 2007 +0100 + + cfi_flash: Make some needlessly global functions static + + Make functions not declared in any header file static. + + Signed-off-by: Haavard Skinnemoen + +commit 7e5b9b471518c5652febc68ba62b432193d6abf4 +Author: Haavard Skinnemoen +Date: Thu Dec 13 12:56:28 2007 +0100 + + cfi_flash: Break long lines + + This patch tries to keep all lines in the cfi_flash driver below 80 + columns. There are a few lines left which don't fit this requirement + because I couldn't find any trivial way to break them (i.e. it would + take some restructuring, which I intend to do in a later patch.) + + Signed-off-by: Haavard Skinnemoen + +commit 42026c9cb3a76849b41e6e24abfb7b56807a5c1a +Author: Bartlomiej Sieka +Date: Tue Dec 11 13:59:57 2007 +0100 + + CFI: synchronize command offsets with Linux CFI driver + + Fixes non-working CFI Flash on the Inka4x0 board. + + Signed-off-by: Bartlomiej Sieka + +commit 8ff3de61fc5f9b3b21647bce081a3b7f710f0d4d +Author: Kumar Gala +Date: Fri Dec 7 12:17:34 2007 -0600 + + Handle MPC85xx PCIe reset errata (PCI-Ex 38) + + On the MPC85xx boards that have PCIe enable the PCIe errata fix. + (MPC8544DS, MPC8548CDS, MPC8568MDS). + + Signed-off-by: Kumar Gala + +commit 82ac8c97145a4c3bf8b3dbfad00fa96e920f9b9c +Author: Kumar Gala +Date: Fri Dec 7 12:04:30 2007 -0600 + + Update Freescale MPC85xx ADS/CDS/MDS board config + + * Enabled CONFIG_CMD_ELF + + Signed-off-by: Kumar Gala + +commit d435793229ce29a42797c1edc39f5b34f987f91a +Author: Kumar Gala +Date: Fri Dec 7 04:59:26 2007 -0600 + + Handle Asynchronous DDR clock on 85xx + + The MPC8572 introduces the concept of an asynchronous DDR clock with + regards to the platform clock. + + Introduce get_ddr_freq() to report the DDR freq regardless of sync/async + mode. + + Signed-off-by: Kumar Gala + +commit 22abb2d2eaf7b795a6923c6273ec9cb53fda9a10 +Author: Kumar Gala +Date: Thu Nov 29 10:34:28 2007 -0600 + + Update Freescale MPC85xx ADS/CDS/MDS board config + + * Removed some misc environment setup + * Enabled CONFIG_CMDLINE_EDITING + + Signed-off-by: Kumar Gala + +commit 415a613babb84d5e5d5b42e8e553868c71fc3a64 +Author: Kumar Gala +Date: Thu Nov 29 10:47:44 2007 -0600 + + Move the MPC8541/MPC8555/MPC8548 CDS board under board/freescale. + + Minor path corrections needed to ensure buildability. + + Signed-off-by: Kumar Gala + +commit c2d943ffbfd3359b3b45d177b437379d2cb86fbf +Author: Kumar Gala +Date: Thu Nov 29 10:16:18 2007 -0600 + + Move the MPC8540 ADS board under board/freescale. + + Minor path corrections needed to ensure buildability. + + Signed-off-by: Kumar Gala + +commit 870ceac5b3a3486c109396e005af81ae762b5710 +Author: Kumar Gala +Date: Thu Nov 29 10:14:50 2007 -0600 + + Move the MPC8560 ADS board under board/freescale. + + Minor path corrections needed to ensure buildability. + + Signed-off-by: Kumar Gala + +commit acbca876fb3fec25cd9c55b0efc81ff618ff5262 +Author: Kumar Gala +Date: Thu Nov 29 10:13:47 2007 -0600 + + Move the MPC8568 MDS board under board/freescale. + + Minor path corrections needed to ensure buildability. + + Signed-off-by: Kumar Gala + +commit a853d56c59b33415304531443633808736acfc6e +Author: Kumar Gala +Date: Thu Nov 29 02:18:59 2007 -0600 + + Use standard LAWAR_TRGT_IF_* defines for LAW setup on 85xx + + We already had defines for LAWAR_TRGT_IF_* that we should use + rather than creating new ones. Also, added some missing defines for + PCIE targets. + + Signed-off-by: Kumar Gala + +commit 04db400892da37b76a585e332a0c137954ad2015 +Author: Kumar Gala +Date: Thu Nov 29 02:10:09 2007 -0600 + + Stop using immap_t on 85xx + + In the future the offsets to various blocks may not be in same location. + Move to using CFG_MPC85xx_*_ADDR as the base of the registers + instead of getting it via &immap. + + Signed-off-by: Kumar Gala + +commit 2714223f8e04ab3e4133ff65872eef366d90bfea +Author: Kumar Gala +Date: Thu Nov 29 01:23:09 2007 -0600 + + Remove CONFIG_OF_FLAT_TREE related code from mpc85xx since we now use libfdt + + Signed-off-by: Kumar Gala + +commit c480861bf000156e6a3e932c258db59ff2212dd3 +Author: Kumar Gala +Date: Thu Nov 29 01:06:19 2007 -0600 + + Update MPC8568 MDS to use libfdt + + Updated the MPC8568 MDS config to use libfdt and assume use of aliases for + ethernet, pci, and serial for the various fixups that are done. + + Signed-off-by: Kumar Gala + +commit 1563f56e0c68f6920f956382d6d13bee3f01c0f7 +Author: Haiying Wang +Date: Wed Nov 14 15:52:06 2007 -0500 + + Add PCI Express support on MPC8568MDS + + Signed-off-by: Haiying Wang + Signed-off-by: Kumar Gala + +commit b90d25497625b90ffa3f2911a0895ca237556ff5 +Author: Kumar Gala +Date: Thu Nov 29 00:11:44 2007 -0600 + + Update MPC85xx CDS to use libfdt + + Updated the MPC85xx CDS config to use libfdt and assume use of aliases for + ethernet, pci, and serial for the various fixups that are done. + + Signed-off-by: Kumar Gala + +commit 0fd5ec66b10521a057ad73e69ab5f0f9eafba255 +Author: Kumar Gala +Date: Wed Nov 28 22:54:27 2007 -0600 + + Update MPC8540 ADS to use libfdt + + Updated the MPC8540 ADS config to use libfdt and assume use of aliases for + ethernet, pci, and serial for the various fixups that are done. + + Signed-off-by: Kumar Gala + +commit 5ce715802f6c50dc78b3405b92f184b1e3710519 +Author: Kumar Gala +Date: Wed Nov 28 22:40:31 2007 -0600 + + Update MPC8560 ADS to use libfdt + + Updated the MPC8560 ADS config to use libfdt and assume use of aliases for + ethernet, pci, and serial for the various fixups that are done. + + Signed-off-by: Kumar Gala + +commit aafeefbdb8b029f5ca2a195598d0a501a606eea9 +Author: Kumar Gala +Date: Wed Nov 28 00:36:33 2007 -0600 + + Stop using immap_t for cpm offset on 85xx + + In the future the offsets to various blocks may not be in same location. + Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers + instead of getting it via &immap->im_cpm. + + Signed-off-by: Kumar Gala + +commit f59b55a5b8fcadaa99781ba48e7a38e956afa527 +Author: Kumar Gala +Date: Tue Nov 27 23:25:02 2007 -0600 + + Stop using immap_t for guts offset on 85xx + + In the future the offsets to various blocks may not be in same location. + Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers + instead of getting it via &immap->im_gur. + + Signed-off-by: Kumar Gala + +commit 50c03c8cf494d91cdec39670d95337c743e16ec9 +Author: Kumar Gala +Date: Tue Nov 27 22:42:34 2007 -0600 + + Update MPC8544 DS config + + * Removed HAS_ETH2/HAS_ETH3 - MPC8544 only has TSEC1/2 + * Removed some misc environment setup + * Moved to using fdtfile & fdtaddr as fdt env var names + * Enabled CONFIG_CMDLINE_EDITING + + Signed-off-by: Kumar Gala + +commit addce57e2e4c49e77ffb2020a84690713bb18b47 +Author: Kumar Gala +Date: Mon Nov 26 17:12:24 2007 -0600 + + Update MPC8544DS to use libfdt + + Updated the MPC8544DS config to use libfdt and assume use of aliases for + ethernet, pci, and serial for the various fixups that are done. + + Signed-off-by: Kumar Gala + +commit f852ce72f100cabd1f11c21c085a0ad8eca9fb65 +Author: Kumar Gala +Date: Thu Nov 29 00:15:30 2007 -0600 + + Add libfdt based ft_cpu_setup for mpc85xx + + Signed-off-by: Kumar Gala + +commit 9692c2734a47f23b44a0f68042a3e2ca8d1bfb39 +Author: Stefan Roese +Date: Sat Dec 8 08:25:09 2007 +0100 + + CFI: Coding style cleanup + + Signed-off-by: Stefan Roese + +commit 81b20ccc2d795ae9a1199db5a50ad9c28d1e4d22 +Author: Michael Schwingen +Date: Fri Dec 7 23:35:02 2007 +0100 + + CFI: support JEDEC flash roms in CFI-flash framework + + The following patch adds support for non-CFI flash ROMS, by hooking into the + CFI flash code and using most of its code, as recently discussed here in the + thread "Mixing CFI and non-CFI flashs". + + Signed-off-by: Michael Schwingen + Signed-off-by: Stefan Roese + +commit c01b17dd856fa120b2970f50d9598546a4927ec3 +Author: Gerald Van Baren +Date: Wed Nov 28 21:24:50 2007 -0500 + + Conditionally compile fdt_fixup_ethernet() + + Fix compiler warnings: On boards that don't have ethernets defined, + don't compile fdt_fixup_ethernet(). + +commit 246d4ae6bc282bc1841224e1c5fc49dc925e0bf7 +Author: Kumar Gala +Date: Tue Nov 27 21:59:46 2007 -0600 + + Convert boards that set memory node to use fdt_fixup_memory() + + Signed-off-by: Kumar Gala + +commit 151c8b09b35eebe8fd9139cb6c1d91c27b22f058 +Author: Kumar Gala +Date: Mon Nov 26 17:06:15 2007 -0600 + + Added fdt_fixup_stdout that uses aliases to set linux,stdout-path + + We use a combination of the serialN alias and CONFIG_CONS_INDEX to + determine which serial alias we should set linux,stdout-path to. + + Signed-off-by: Kumar Gala + +commit 3c9272813fad84c691d0e4989bb18a3ffebdebfc +Author: Kumar Gala +Date: Mon Nov 26 14:57:45 2007 -0600 + + Add common memory fixup function + + Add the function fdt_fixup_memory() to fixup the /memory node of the fdt + + Signed-off-by: Kumar Gala + +commit 9c9109e7fcf7ac2ca19c95b8ac54b8d1c773b157 +Author: Kumar Gala +Date: Mon Nov 26 11:19:12 2007 -0600 + + Conditionally compile fdt_support.c + + Modify common/Makefile to conditionally compile fdt_support.c based + on CONFIG_OF_LIBFDT. + + Signed-off-by: Kumar Gala + +commit d88e7ba0980773479e1a64badb293116071b7ef0 +Author: Kumar Gala +Date: Mon Nov 26 10:41:40 2007 -0600 + + Fix build breakage due to libfdt import + + The IDS8247 got lost in the update and need an API update + do to rename of functions in libfdt. + + Signed-off-by: Kumar Gala + +commit 28f384b171bbf1fb2dafb1046e6d259a6b2f8714 +Author: Gerald Van Baren +Date: Fri Nov 23 19:43:20 2007 -0500 + + Add spaces around the = in the fdt print format. + + Signed-off-by: Gerald Van Baren + +commit 29592ecba3b932b9b152bcec6c0c0806412db4a3 +Author: Nobuhiro Iwamatsu +Date: Fri Dec 7 01:25:38 2007 +0900 + + sh: Moved driver of the SuperH dependence + + The composition of the directory in the drivers/ changed. + I moved SuperH serial driver and marubun PCMCIA driver. + + Signed-off-by: Nobuhiro Iwamatsu + +commit 41be969f4957115ed7b1fe8b890bfaee99d7a7a2 +Author: Wolfgang Denk +Date: Thu Dec 6 10:21:19 2007 +0100 + + Release v1.3.1 + + Signed-off-by: Wolfgang Denk + +commit cf5933ba1e97a1cd8f5f24070e820f21d976eaeb +Author: Wolfgang Denk +Date: Thu Dec 6 10:21:03 2007 +0100 + + ADS5121 Board: fix compile problem. + + Signed-off-by: Wolfgang Denk + +commit 8d4f040a3c15036a6ea25a9c39e7d89fefa8440d +Author: Wolfgang Denk +Date: Mon Dec 3 00:15:28 2007 +0100 + + Prepare for 1.3.1-rc1 + + Signed-off-by: Wolfgang Denk + +commit 260eea5676ca46903a335686cc020b29c4ca46fe +Author: Nobuhiro Iwamatsu +Date: Thu Nov 29 01:21:54 2007 +0900 + + sh: Add SuperH boards maintainer to MAINTAINERS file + + Add MS7750SE and MS7722SE's board maintainer to MAINTAINERS file. + + Signed-off-by: Nobuhiro Iwamatsu + +commit aa9c4f1d22701a92347c1c81f34d12c8ad3a3747 +Author: Nobuhiro Iwamatsu +Date: Thu Nov 29 00:13:04 2007 +0900 + + sh: Add ms7750se support in MAKEALL + + Signed-off-by: Nobuhiro Iwamatsu + +commit c7144373427a178332bf9754131c8c34c52c200a +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Tue Nov 27 09:44:53 2007 +0100 + + sh: Add sh3 and sh4 support in MAKEALL + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Nobuhiro Iwamatsu + +commit 130080874a3d28450098481a262c5f7c855e908d +Author: Nobuhiro Iwamatsu +Date: Sun Nov 25 02:51:17 2007 +0900 + + sh: Add document for SuperH. + + This document is a summary of information concerning SuperH of U-Boot. + + Signed-off-by: Nobuhiro Iwamatsu + +commit 33ecdc2f9d64926e1a6067b28f3a0aefc3b6d23d +Author: Nobuhiro Iwamatsu +Date: Sun Nov 25 02:39:31 2007 +0900 + + sh: Add marubun's pcmcia driver + + Marubun pcmcia is a chip for PCMCIA used with SuperH. + Of course, this can be used even by other architectures. + When use this driver, came to be able to use CompactFlash + and Ethernet. + + Signed-off-by: Nobuhiro Iwamatsu + +commit febd86b969b975289ed948f1ac0eb9722da41ced +Author: Nobuhiro Iwamatsu +Date: Sun Nov 25 02:32:13 2007 +0900 + + sh: Update SuperH SCIF driver + + - Changed volatile unsigned to vu_. + - Changed Makefile for kconfig. + + Signed-off-by: Nobuhiro Iwamatsu + commit a5f601fd1b1278deae5aa9fc27a232b0d1c1c788 Author: Wolfgang Denk Date: Mon Nov 26 19:18:21 2007 +0100 @@ -1927,6 +2611,56 @@ Date: Mon Sep 24 00:08:37 2007 +0200 synchronizition with mainline +commit eda3e1e6619ad0bee94ae4b16c99d88e77e2af13 +Author: Nobuhiro Iwamatsu +Date: Sun Sep 23 02:42:38 2007 +0900 + + sh: Add support command of ide with sh + + Signed-off-by: Nobuhiro Iwamatsu + +commit d91ea45d15cf8e0987456bd211ffbb650824b6f1 +Author: Nobuhiro Iwamatsu +Date: Sun Sep 23 02:38:42 2007 +0900 + + sh: Update Makefile + + Add support MS7722SE01 to Makefile. + + Signed-off-by: Nobuhiro Iwamatsu + +commit 6c0bbdccd379f5c8702af9e0765294c2fb7472a6 +Author: Nobuhiro Iwamatsu +Date: Sun Sep 23 02:31:13 2007 +0900 + + sh: Add support Renesas sh7722 processor and Hitachi MS7722SE01 board + + Signed-off-by: Nobuhiro Iwamatsu + +commit 047375bfa4c3052fa50a748da7ff89e9dad3b364 +Author: Nobuhiro Iwamatsu +Date: Sun Sep 23 02:19:24 2007 +0900 + + sh: Update MS7750SE01 platform + + Signed-off-by: Nobuhiro Iwamatsu + +commit 516ad760db3553766267ada01b7d5d727faa4bbd +Author: Nobuhiro Iwamatsu +Date: Sun Sep 23 02:17:08 2007 +0900 + + sh: Remove comment out code from include/asm-sh/cpu_sh4.h + + Signed-off-by: Nobuhiro Iwamatsu + +commit b02bad128669e567fce87d8df823b06a0144b8db +Author: Nobuhiro Iwamatsu +Date: Sun Sep 23 02:12:30 2007 +0900 + + sh: Update core code of SuperH. + + Signed-off-by: Nobuhiro Iwamatsu + commit 66dcad3a9a53e0766d90e0084123bd8529522fb0 Author: Wolfgang Denk Date: Thu Sep 20 00:04:14 2007 +0200 @@ -8634,6 +9368,24 @@ Date: Tue May 15 07:55:42 2007 -0700 Fix to compile JSE against 20070514 git of u-boot +commit 69df3c4da0c93017cceb25a366e794570bd0ed98 +Author: Nobuhiro Iwamatsu +Date: Sun May 13 21:01:03 2007 +0900 + + sh: MS7750SE support. + + This adds support for the Hitachi MS7750SE. + + Signed-off-by: Nobuhiro Iwamatsu + +commit 0b135cfc2e524dc249b75057b55dd4cc09842e27 +Author: Nobuhiro Iwamatsu +Date: Sun May 13 20:58:00 2007 +0900 + + sh: First support code of SuperH. + + Signed-off-by: Nobuhiro Iwamatsu + commit 61936667e86a250ae12fd2dc189d3588f0a59e0b Author: Stefan Roese Date: Fri May 11 12:01:49 2007 +0200 diff --git a/MAINTAINERS b/MAINTAINERS index 5c68e5d74dc..9052a196c43 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -634,7 +634,7 @@ Haavard Skinnemoen ATSTK1002 AT32AP7000 ATSTK1003 AT32AP7001 ATSTK1004 AT32AP7002 - + ######################################################################### # SuperH Systems: # # # diff --git a/board/ms7722se/Makefile b/board/ms7722se/Makefile index 94469f7c6e4..6dec0136c2e 100644 --- a/board/ms7722se/Makefile +++ b/board/ms7722se/Makefile @@ -1,7 +1,7 @@ # # Copyright (C) 2007 # Nobuhiro Iwamatsu -# +# # Copyright (C) 2007 # Kenati Technologies, Inc. # diff --git a/board/ms7722se/config.mk b/board/ms7722se/config.mk index e4ca55acadc..4797d6f8f6c 100644 --- a/board/ms7722se/config.mk +++ b/board/ms7722se/config.mk @@ -29,4 +29,3 @@ # TEXT_BASE = 0x8FFC0000 - diff --git a/board/ms7722se/lowlevel_init.S b/board/ms7722se/lowlevel_init.S index e0d519c55a4..2024e27ffe8 100644 --- a/board/ms7722se/lowlevel_init.S +++ b/board/ms7722se/lowlevel_init.S @@ -1,7 +1,7 @@ /* * Copyright (C) 2007 * Nobuhiro Iwamatsu - * + * * Copyright (C) 2007 * Kenati Technologies, Inc. * @@ -52,19 +52,19 @@ lowlevel_init: mov.l r0, @r1 mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0 - mov.l MSTPCR0_D, r0 ! + mov.l MSTPCR0_D, r0 ! mov.l r0, @r1 mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2 - mov.l MSTPCR2_D, r0 ! + mov.l MSTPCR2_D, r0 ! mov.l r0, @r1 - mov.l SBSCR_A, r1 ! - mov.w SBSCR_D, r0 ! + mov.l SBSCR_A, r1 ! + mov.w SBSCR_D, r0 ! mov.w r0, @r1 - mov.l PSCR_A, r1 ! - mov.w PSCR_D, r0 ! + mov.l PSCR_A, r1 ! + mov.w PSCR_D, r0 ! mov.w r0, @r1 ! mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register) @@ -80,7 +80,7 @@ lowlevel_init: mov.w r0, @r1 mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register - mov.l FRQCR_D, r0 ! + mov.l FRQCR_D, r0 ! mov.l r0, @r1 mov.l CCR_A, r1 ! Address of Cache Control Register @@ -200,11 +200,9 @@ bsc_init: rts mov #0, r0 - - .align 2 -CCR_A: .long CCR +CCR_A: .long CCR MMUCR_A: .long MMUCR MSTPCR0_A: .long MSTPCR0 MSTPCR2_A: .long MSTPCR2 @@ -223,7 +221,7 @@ FRQCR_D: .long 0x07022538 PSELA_A: .long 0xa405014E PSELA_D: .word 0x0A10 - .align 2 + .align 2 DRVCR_A: .long 0xa405018A DRVCR_D: .word 0x0554 diff --git a/board/ms7722se/ms7722se.c b/board/ms7722se/ms7722se.c index 3eeb1b7d807..0d3d55cf5ca 100644 --- a/board/ms7722se/ms7722se.c +++ b/board/ms7722se/ms7722se.c @@ -4,7 +4,7 @@ * * Copyright (C) 2007 * Kenati Technologies, Inc. - * + * * board/ms7722se/ms7722se.c * * This program is free software; you can redistribute it and/or @@ -57,4 +57,3 @@ void led_set_state (unsigned short value) { *((volatile unsigned short *) LED_BASE) = (value & 0xFF); } - diff --git a/board/ms7722se/u-boot.lds b/board/ms7722se/u-boot.lds index 24c218495ce..692bc62918e 100644 --- a/board/ms7722se/u-boot.lds +++ b/board/ms7722se/u-boot.lds @@ -32,19 +32,19 @@ SECTIONS Although size of SDRAM can be either 16 or 32 MBytes, we assume 16 MBytes (ie ignore upper half if the full 32 MBytes is present). - + NOTE: This address must match with the definition of TEXT_BASE in config.mk (in this directory). - + */ . = 0x8C000000 + (64*1024*1024) - (256*1024); - + PROVIDE (reloc_dst = .); PROVIDE (_ftext = .); PROVIDE (_fcode = .); PROVIDE (_start = .); - + .text : { cpu/sh4/start.o (.text) @@ -89,7 +89,7 @@ SECTIONS } PROVIDE (__u_boot_cmd_end = .); - PROVIDE (reloc_dst_end = .); + PROVIDE (reloc_dst_end = .); /* _reloc_dst_end = .; */ PROVIDE (bss_start = .); @@ -103,4 +103,3 @@ SECTIONS PROVIDE (_end = .); } - diff --git a/board/ms7750se/lowlevel_init.S b/board/ms7750se/lowlevel_init.S index 360c9fa1730..d3e3cd5e8d0 100644 --- a/board/ms7750se/lowlevel_init.S +++ b/board/ms7750se/lowlevel_init.S @@ -2,8 +2,8 @@ modified from SH-IPL+g Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting. - Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R - + Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R + Coyright (c) 2007 Nobuhiro Iwamatsu * See file CREDITS for list of people who contributed to this @@ -102,7 +102,7 @@ init_bsc: mov #0,r0 mov.b r0,@r1 - ! Do you need PCMCIA setting? + ! Do you need PCMCIA setting? ! If so, please add the lines here... mov.l RTCNT_A,r1 /* RTCNT Address */ @@ -165,7 +165,7 @@ WCR2_A: .long WCR2 WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */ WCR3_A: .long WCR3 WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */ -RTCSR_A: .long RTCSR +RTCSR_A: .long RTCSR RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */ RTCNT_A: .long RTCNT RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ @@ -177,4 +177,3 @@ MCR_D1: .long MCR_D1_VALUE MCR_D2: .long MCR_D2_VALUE RFCR_A: .long RFCR RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ - diff --git a/board/ms7750se/ms7750se.c b/board/ms7750se/ms7750se.c index 1ae9dd13a5d..d2d824c5a7d 100644 --- a/board/ms7750se/ms7750se.c +++ b/board/ms7750se/ms7750se.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 + * Copyright (C) 2007 * Nobuhiro Iwamatsu * * See file CREDITS for list of people who contributed to this diff --git a/board/ms7750se/u-boot.lds b/board/ms7750se/u-boot.lds index 24c218495ce..692bc62918e 100644 --- a/board/ms7750se/u-boot.lds +++ b/board/ms7750se/u-boot.lds @@ -32,19 +32,19 @@ SECTIONS Although size of SDRAM can be either 16 or 32 MBytes, we assume 16 MBytes (ie ignore upper half if the full 32 MBytes is present). - + NOTE: This address must match with the definition of TEXT_BASE in config.mk (in this directory). - + */ . = 0x8C000000 + (64*1024*1024) - (256*1024); - + PROVIDE (reloc_dst = .); PROVIDE (_ftext = .); PROVIDE (_fcode = .); PROVIDE (_start = .); - + .text : { cpu/sh4/start.o (.text) @@ -89,7 +89,7 @@ SECTIONS } PROVIDE (__u_boot_cmd_end = .); - PROVIDE (reloc_dst_end = .); + PROVIDE (reloc_dst_end = .); /* _reloc_dst_end = .; */ PROVIDE (bss_start = .); @@ -103,4 +103,3 @@ SECTIONS PROVIDE (_end = .); } - diff --git a/cpu/sh4/cache.c b/cpu/sh4/cache.c index 55acb31bc4b..4e744d71453 100644 --- a/cpu/sh4/cache.c +++ b/cpu/sh4/cache.c @@ -30,36 +30,36 @@ * Jump to P2 area. * When handling TLB or caches, we need to do it from P2 area. */ -#define jump_to_P2() \ - do { \ +#define jump_to_P2() \ + do { \ unsigned long __dummy; \ - __asm__ __volatile__( \ - "mov.l 1f, %0\n\t" \ - "or %1, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy) \ - : "r" (0x20000000)); \ + __asm__ __volatile__( \ + "mov.l 1f, %0\n\t" \ + "or %1, %0\n\t" \ + "jmp @%0\n\t" \ + " nop\n\t" \ + ".balign 4\n" \ + "1: .long 2f\n" \ + "2:" \ + : "=&r" (__dummy) \ + : "r" (0x20000000)); \ } while (0) /* * Back to P1 area. */ -#define back_to_P1() \ - do { \ - unsigned long __dummy; \ - __asm__ __volatile__( \ - "nop;nop;nop;nop;nop;nop;nop\n\t" \ - "mov.l 1f, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy)); \ +#define back_to_P1() \ + do { \ + unsigned long __dummy; \ + __asm__ __volatile__( \ + "nop;nop;nop;nop;nop;nop;nop\n\t" \ + "mov.l 1f, %0\n\t" \ + "jmp @%0\n\t" \ + " nop\n\t" \ + ".balign 4\n" \ + "1: .long 2f\n" \ + "2:" \ + : "=&r" (__dummy)); \ } while (0) #define CACHE_VALID 1 diff --git a/cpu/sh4/config.mk b/cpu/sh4/config.mk index 2dc7b918d7c..b3feb2a5158 100644 --- a/cpu/sh4/config.mk +++ b/cpu/sh4/config.mk @@ -4,7 +4,7 @@ # # (C) Copyright 2007 # Nobuhiro Iwamatsu -# +# # See file CREDITS for list of people who contributed to this # project. # diff --git a/cpu/sh4/cpu.c b/cpu/sh4/cpu.c index d76d5180e7e..0ebf95180c3 100644 --- a/cpu/sh4/cpu.c +++ b/cpu/sh4/cpu.c @@ -66,7 +66,7 @@ void icache_disable (void) int icache_status (void) { - return 0; + return 0; } void dcache_enable (void) diff --git a/cpu/sh4/interrupts.c b/cpu/sh4/interrupts.c index d310dd2c176..6988ecc7c28 100644 --- a/cpu/sh4/interrupts.c +++ b/cpu/sh4/interrupts.c @@ -25,7 +25,7 @@ int interrupt_init (void) { - return 0; + return 0; } void enable_interrupts (void) @@ -33,7 +33,6 @@ void enable_interrupts (void) } -int disable_interrupts (void){ - return 0; +int disable_interrupts (void){ + return 0; } - diff --git a/cpu/sh4/start.S b/cpu/sh4/start.S index d88b705ef08..a68ebb8c93e 100644 --- a/cpu/sh4/start.S +++ b/cpu/sh4/start.S @@ -33,21 +33,21 @@ _start: bsr 1f nop 1: sts pr, r5 - mov.l ._reloc_dst, r4 - add #(_start-1b), r5 - mov.l ._reloc_dst_end, r6 + mov.l ._reloc_dst, r4 + add #(_start-1b), r5 + mov.l ._reloc_dst_end, r6 2: mov.l @r5+, r1 mov.l r1, @r4 add #4, r4 cmp/hs r6, r4 bf 2b - - mov.l ._bss_start, r4 - mov.l ._bss_end, r5 + + mov.l ._bss_start, r4 + mov.l ._bss_end, r5 mov #0, r1 -3: mov.l r1, @r4 /* bss clear */ +3: mov.l r1, @r4 /* bss clear */ add #4, r4 cmp/hs r5, r4 bf 3b @@ -56,8 +56,8 @@ _start: mov.l ._stack_init, r15 /* stack */ mov.l ._sh_generic_init, r0 - jsr @r0 - nop + jsr @r0 + nop loop: bra loop @@ -72,4 +72,3 @@ loop: ._gd_init: .long (_start - CFG_GBL_DATA_SIZE) ._stack_init: .long (_start - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN - 16) ._sh_generic_init: .long sh_generic_init - diff --git a/cpu/sh4/watchdog.c b/cpu/sh4/watchdog.c index 04723a74627..346e21714fd 100644 --- a/cpu/sh4/watchdog.c +++ b/cpu/sh4/watchdog.c @@ -32,12 +32,12 @@ static void cnt_write (unsigned char value){ while (csr_read() & (1 << 5)) { /* delay */ } - *((volatile unsigned short *)(WDT_BASE + 0x00)) + *((volatile unsigned short *)(WDT_BASE + 0x00)) = ((unsigned short) value) | 0x5A00; } static void csr_write (unsigned char value){ - *((volatile unsigned short *)(WDT_BASE + 0x04)) + *((volatile unsigned short *)(WDT_BASE + 0x04)) = ((unsigned short) value) | 0xA500; } @@ -48,5 +48,3 @@ void reset_cpu (unsigned long ignored) { while(1); } - - diff --git a/doc/README.marubun-pcmcia b/doc/README.marubun-pcmcia index 73c9f7f53bf..3ed5cd33c4b 100644 --- a/doc/README.marubun-pcmcia +++ b/doc/README.marubun-pcmcia @@ -1,59 +1,59 @@ U-Boot MARUBUN MR-SHPC-01 PCMCIA controller driver Last update 21/11/2007 by Nobuhiro Iwamatsu - + ======================================================================================== -0. What's this? +0. What's this? This driver supports MARUBUN MR-SHPC-01. url: http://www.marubun.co.jp/product/semicon/devices/qgc18e0000002n2z.html (Sorry Japanese only.) - This chip is used with SuperH well, and adopted by the - reference board. + This chip is used with SuperH well, and adopted by the + reference board. ex. * MS7750SE01 * MS7722SE01 - * other - + * other + This chip doesn't support CardBus. -1. base source code +1. base source code The code is based on sources from the Linux kernel - ( arch/sh/kernel/cf-enabler.c ). + ( arch/sh/kernel/cf-enabler.c ). -2. How to use +2. How to use The options you have to specify in the config file are (with the value for my board as an example): * CONFIG_MARUBUN_PCCARD If you want to use this device driver, should define CONFIG_MARUBUN_PCCARD. ex. #define CONFIG_MARUBUN_PCCARD - + * CONFIG_PCMCIA_SLOT_A Most devices have only one slot. You should define CONFIG_PCMCIA_SLOT_A . ex. #define CONFIG_PCMCIA_SLOT_A 1 * CFG_MARUBUN_MRSHPC This is MR-SHPC-01 PCMCIA controler base address. - You should do the setting matched to your environment. - ex. #define CFG_MARUBUN_MRSHPC 0xb03fffe0 + You should do the setting matched to your environment. + ex. #define CFG_MARUBUN_MRSHPC 0xb03fffe0 ( for MS7722SE01 environment ) * CFG_MARUBUN_MW1 This is MR-SHPC-01 memory window base address. - You should do the setting matched to your environment. + You should do the setting matched to your environment. ex. #define CFG_MARUBUN_MW1 0xb0400000 ( for MS7722SE01 environment ) - + * CFG_MARUBUN_MW1 This is MR-SHPC-01 attribute window base address. - You should do the setting matched to your environment. + You should do the setting matched to your environment. ex. #define CFG_MARUBUN_MW2 0xb0500000 ( for MS7722SE01 environment ) - + * CFG_MARUBUN_MW1 This is MR-SHPC-01 I/O window base address. - You should do the setting matched to your environment. + You should do the setting matched to your environment. ex. #define CFG_MARUBUN_IO 0xb0600000 ( for MS7722SE01 environment ) diff --git a/doc/README.sh b/doc/README.sh index 0441a7a6462..075d360e908 100644 --- a/doc/README.sh +++ b/doc/README.sh @@ -1,5 +1,5 @@ -U-Boot for Renesas SuperH +U-Boot for Renesas SuperH Last update 08/10/2007 by Nobuhiro Iwamatsu ================================================================================ @@ -9,10 +9,10 @@ U-Boot for Renesas SuperH ================================================================================ 1. Overview - SuperH has an original boot loader. However, source code is dirty, and + SuperH has an original boot loader. However, source code is dirty, and maintenance is not done. - To improve sharing and the maintenance of the code, Nobuhiro Iwamatsu - started the porting to u-boot in 2007. + To improve sharing and the maintenance of the code, Nobuhiro Iwamatsu + started the porting to u-boot in 2007. ================================================================================ 2. Supported CPUs @@ -33,13 +33,13 @@ U-Boot for Renesas SuperH ** README ** In SuperH, S-record and binary of made u-boot work on the memory. - When u-boot is written in the flash, it is necessary to change the - address by using 'objcopy'. + When u-boot is written in the flash, it is necessary to change the + address by using 'objcopy'. ex) shX-linux-objcopy -Ibinary -Osrec u-boot.bin u-boot.flash.srec - + ================================================================================ 4. Compiler - You can use the following of u-boot to compile. + You can use the following of u-boot to compile. - SuperH Linux Open site http://www.superh-linux.org/ - KPIT GNU tools @@ -52,11 +52,10 @@ U-Boot for Renesas SuperH - SH7710/SH7712 (SH3) - SH7780(SH4) - SH7785(SH4) - + 5.2. Boards - Many boards ;-) ================================================================================ Copyright (c) 2007 Nobuhiro Iwamatsu - diff --git a/drivers/pcmcia/marubun_pcmcia.c b/drivers/pcmcia/marubun_pcmcia.c index 89b201526c8..7b112af9226 100644 --- a/drivers/pcmcia/marubun_pcmcia.c +++ b/drivers/pcmcia/marubun_pcmcia.c @@ -17,8 +17,8 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA - * - */ + * + */ #include #include @@ -34,7 +34,7 @@ #endif #if defined(CONFIG_PCMCIA) \ - && (defined(CONFIG_MARUBUN_PCCARD)) + && (defined(CONFIG_MARUBUN_PCCARD)) /* MR-SHPC-01 register */ #define MRSHPC_MODE (CFG_MARUBUN_MRSHPC + 4) @@ -79,14 +79,14 @@ int pcmcia_on (void) outw(0x0b00,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 1 */ else outw(0x0300,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 0 */ - + /* attribute window open */ outw(0x8a85,MRSHPC_MW1CR1); /* window 0xb8500000 */ if ((inw(MRSHPC_CSR) & 0x4000) != 0) outw(0x0a00,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 1 */ else outw(0x0200,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 0 */ - + /* I/O window open */ outw(0x8a86,MRSHPC_IOWCR1); /* I/O window 0xb8600000 */ outw(0x0008,MRSHPC_CDCR); /* I/O card mode */ @@ -94,7 +94,7 @@ int pcmcia_on (void) outw(0x0a00,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1 */ else outw(0x0200,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0 */ - + outw(0x0000,MRSHPC_ISR); outw(0x2000,MRSHPC_ICR); outb(0x00,(CFG_MARUBUN_MW2 + 0x206)); diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 78186326f0d..ee44ba26445 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -1,7 +1,7 @@ /* * SuperH SCIF device driver. * Copyright (c) 2007 Nobuhiro Iwamatsu - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -31,7 +31,7 @@ #endif #define SCSMR (vu_short *)(SCIF_BASE + 0x0) -#define SCBRR (vu_char *)(SCIF_BASE + 0x4) +#define SCBRR (vu_char *)(SCIF_BASE + 0x4) #define SCSCR (vu_short *)(SCIF_BASE + 0x8) #define SCFTDR (vu_char *)(SCIF_BASE + 0xC) #define SCFSR (vu_short *)(SCIF_BASE + 0x10) @@ -51,7 +51,7 @@ #endif #define SCR_RE (1 << 4) -#define SCR_TE (1 << 5) +#define SCR_TE (1 << 5) #define FCR_RFRST (1 << 1) /* RFCL */ #define FCR_TFRST (1 << 2) /* TFCL */ #define FSR_DR (1 << 0) @@ -69,7 +69,7 @@ void serial_setbrg (void) DECLARE_GLOBAL_DATA_PTR; int divisor = gd->baudrate * 32; - *SCBRR = (CONFIG_SYS_CLK_FREQ + (divisor / 2)) / + *SCBRR = (CONFIG_SYS_CLK_FREQ + (divisor / 2)) / (gd->baudrate * 32) - 1; } diff --git a/examples/stubs.c b/examples/stubs.c index 263dd8c3de9..571c4d50a43 100644 --- a/examples/stubs.c +++ b/examples/stubs.c @@ -132,7 +132,7 @@ gd_t *global_data; */ #define EXPORT_FUNC(x) \ asm volatile ( \ -" .globl _" #x "\n_" \ +" .globl _" #x "\n_" \ #x ":\n" \ " P0 = [P5 + %0]\n" \ " P0 = [P0 + %1]\n" \ @@ -155,17 +155,17 @@ gd_t *global_data; /* * r13 holds the pointer to the global_data. r1 is a call clobbered. */ -#define EXPORT_FUNC(x) \ - asm volatile ( \ - " .align 2\n" \ - " .globl " #x "\n" \ - #x ":\n" \ - " mov r13, r1\n" \ - " add %0, r1\n" \ - " add %1, r1\n" \ - " jmp @r1\n" \ - " nop\n" \ - " nop\n" \ +#define EXPORT_FUNC(x) \ + asm volatile ( \ + " .align 2\n" \ + " .globl " #x "\n" \ + #x ":\n" \ + " mov r13, r1\n" \ + " add %0, r1\n" \ + " add %1, r1\n" \ + " jmp @r1\n" \ + " nop\n" \ + " nop\n" \ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r1"); #else #error stubs definition missing for this architecture diff --git a/include/asm-sh/bitops.h b/include/asm-sh/bitops.h index 529d0f2dbb8..410fba46eff 100644 --- a/include/asm-sh/bitops.h +++ b/include/asm-sh/bitops.h @@ -2,7 +2,6 @@ #define __ASM_SH_BITOPS_H #ifdef __KERNEL__ -//#include #include /* For __swab32 */ #include @@ -99,8 +98,6 @@ static inline int test_and_change_bit(int nr, volatile void * addr) return retval; } -//#include - static inline unsigned long ffz(unsigned long word) { unsigned long result; @@ -121,46 +118,34 @@ static inline unsigned long ffz(unsigned long word) * * Undefined if no bit exists, so code should check against 0 first. */ -static inline int ffs(int x) +static inline int ffs (int x) { - int r = 1; - - if (!x) - return 0; - if (!(x & 0xffff)) { - x >>= 16; - r += 16; - } - if (!(x & 0xff)) { - x >>= 8; - r += 8; - } - if (!(x & 0xf)) { - x >>= 4; - r += 4; - } - if (!(x & 3)) { - x >>= 2; - r += 2; - } - if (!(x & 1)) { - x >>= 1; - r += 1; - } - return r; + int r = 1; + + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) { + x >>= 1; + r += 1; + } + return r; } - -#if 0 -#include -#include -#include -#include -#include -#include -#include -#include -#include -#endif #endif /* __KERNEL__ */ #endif /* __ASM_SH_BITOPS_H */ diff --git a/include/asm-sh/byteorder.h b/include/asm-sh/byteorder.h index 8836e657def..25626a07606 100644 --- a/include/asm-sh/byteorder.h +++ b/include/asm-sh/byteorder.h @@ -28,4 +28,3 @@ #endif #endif - diff --git a/include/asm-sh/cpu_sh7722.h b/include/asm-sh/cpu_sh7722.h index fb63c6ea49f..13d4a77ede1 100644 --- a/include/asm-sh/cpu_sh7722.h +++ b/include/asm-sh/cpu_sh7722.h @@ -31,13 +31,13 @@ #define INTEVT 0xFF000028 /* MMU */ -#define PTEH 0xFF000000 -#define PTEL 0xFF000004 -#define TTB 0xFF000008 -#define TEA 0xFF00000C -#define MMUCR 0xFF000010 -#define PASCR 0xFF000070 -#define IRMCR 0xFF000078 +#define PTEH 0xFF000000 +#define PTEL 0xFF000004 +#define TTB 0xFF000008 +#define TEA 0xFF00000C +#define MMUCR 0xFF000010 +#define PASCR 0xFF000070 +#define IRMCR 0xFF000078 /* CACHE */ #define CCR 0xFF00001C @@ -325,7 +325,7 @@ #define SPICR1 0xA4420030 /* SCIF */ -/* +/* #define SCSMR 0xFFE00000 #define SCBRR 0xFFE00004 #define SCSCR 0xFFE00008 @@ -1334,4 +1334,4 @@ #define SDDRL 0xFC11000A #define SDINT 0xFC110018 -#endif /* _ASM_CPU_SH7722_H_ */ +#endif /* _ASM_CPU_SH7722_H_ */ diff --git a/include/asm-sh/cpu_sh7750.h b/include/asm-sh/cpu_sh7750.h index 9993e632031..bb6461a6bfc 100644 --- a/include/asm-sh/cpu_sh7750.h +++ b/include/asm-sh/cpu_sh7750.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2007 Nobuhiro Iwamatsu * - * SH7750/SH7750S/SH7750R/SH7751/SH7751R + * SH7750/SH7750S/SH7750R/SH7751/SH7751R * Internal I/O register * * This program is free software; you can redistribute it and/or diff --git a/include/asm-sh/posix_types.h b/include/asm-sh/posix_types.h index 4bb9f7e26f2..c9d9fb84f1f 100644 --- a/include/asm-sh/posix_types.h +++ b/include/asm-sh/posix_types.h @@ -68,7 +68,7 @@ static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) #undef __FD_ISSET static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) -{ +{ unsigned long __tmp = __fd / __NFDBITS; unsigned long __rem = __fd % __NFDBITS; return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; diff --git a/include/asm-sh/u-boot.h b/include/asm-sh/u-boot.h index c74e97cdfb5..b79644cfd28 100644 --- a/include/asm-sh/u-boot.h +++ b/include/asm-sh/u-boot.h @@ -25,7 +25,6 @@ #ifndef __ASM_SH_U_BOOT_H_ #define __ASM_SH_U_BOOT_H_ - typedef struct bd_info { unsigned long bi_memstart; /* start of DRAM memory */ unsigned long bi_memsize; /* size of DRAM memory in bytes */ @@ -41,4 +40,3 @@ typedef struct bd_info { } bd_t; #endif - diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h index 18e985118c4..ae0d0185154 100644 --- a/include/configs/ms7722se.h +++ b/include/configs/ms7722se.h @@ -25,7 +25,7 @@ #ifndef __MS7722SE_H #define __MS7722SE_H -#undef DEBUG +#undef DEBUG #define CONFIG_SH 1 #define CONFIG_SH4 1 #define CONFIG_CPU_SH7722 1 @@ -56,7 +56,6 @@ /* MEMORY */ #define MS7722SE_SDRAM_BASE (0x8C000000) #define MS7722SE_FLASH_BASE_1 (0xA0000000) -//#define MS7722SE_FLASH_BASE_1 (0xA1000000) #define MS7722SE_FLASH_BANK_SIZE (8*1024 * 1024) #define CFG_LONGHELP /* undef to save memory */ @@ -87,12 +86,12 @@ #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) /* default load address for scripts ?!? */ -#define CFG_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image +#define CFG_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ #define CFG_MONITOR_LEN (128 * 1024) /* */ #define CFG_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ #define CFG_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */ -#define CFG_BOOTMAPSZ (8 * 1024 * 1024) +#define CFG_BOOTMAPSZ (8 * 1024 * 1024) /* FLASH */ #define CFG_FLASH_CFI @@ -102,7 +101,7 @@ #define CFG_FLASH_BASE (MS7722SE_FLASH_BASE_1) /* Physical start address of Flash memory */ -#define CFG_MAX_FLASH_SECT 150 /* Max number of sectors on each +#define CFG_MAX_FLASH_SECT 150 /* Max number of sectors on each Flash chip */ /* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */ @@ -131,7 +130,7 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ 33333333 -#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ +#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ #define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) #endif /* __MS7722SE_H */ diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h index 7925f209d77..36681568f8a 100644 --- a/include/configs/ms7750se.h +++ b/include/configs/ms7750se.h @@ -37,7 +37,7 @@ /* * Command line configuration. */ -//#include +/*#include */ #define CONFIG_CMD_DFL #define CONFIG_CMD_FLASH @@ -56,7 +56,7 @@ #define CFG_SDRAM_BASE (0x8C000000) #define CFG_SDRAM_SIZE (64 * 1024 * 1024) -#define CFG_LONGHELP +#define CFG_LONGHELP #define CFG_PROMPT "=> " #define CFG_CBSIZE 256 #define CFG_PBSIZE 256 @@ -71,7 +71,7 @@ /* NOR Flash */ /* #define CFG_FLASH_BASE (0xA1000000)*/ #define CFG_FLASH_BASE (0xA0000000) -#define CFG_MAX_FLASH_BANKS (1) /* Max number of +#define CFG_MAX_FLASH_BANKS (1) /* Max number of * Flash memory banks */ #define CFG_MAX_FLASH_SECT 142 diff --git a/lib_sh/Makefile b/lib_sh/Makefile index c84276af883..cf127a826c0 100644 --- a/lib_sh/Makefile +++ b/lib_sh/Makefile @@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(ARCH).a -SOBJS = +SOBJS = COBJS = board.o sh_linux.o # time.o diff --git a/lib_sh/board.c b/lib_sh/board.c index c63ac0313a9..2cd60d76be2 100644 --- a/lib_sh/board.c +++ b/lib_sh/board.c @@ -47,7 +47,7 @@ static void mem_malloc_init (void) mem_malloc_start = (TEXT_BASE - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN); mem_malloc_end = (mem_malloc_start + CFG_MALLOC_LEN - 16); mem_malloc_brk = mem_malloc_start; - memset ((void *) mem_malloc_start, 0, + memset ((void *) mem_malloc_start, 0, (mem_malloc_end - mem_malloc_start)); } @@ -191,7 +191,7 @@ void sh_generic_init (void) puts ("Net: "); eth_initialize(gd->bd); - if ((s = getenv ("bootfile")) != NULL) { + if ((s = getenv ("bootfile")) != NULL) { copy_filename (BootFile, s, sizeof (BootFile)); } #endif /* CONFIG_CMD_NET */ diff --git a/lib_sh/sh_linux.c b/lib_sh/sh_linux.c index acd47b5db70..14b6815cd40 100644 --- a/lib_sh/sh_linux.c +++ b/lib_sh/sh_linux.c @@ -28,7 +28,7 @@ extern image_header_t header; /* common/cmd_bootm.c */ /* The SH kernel reads arguments from the empty zero page at location - * 0 at the start of SDRAM. The following are copied from + * 0 at the start of SDRAM. The following are copied from * arch/sh/kernel/setup.c and may require tweaking if the kernel sources * change. */ @@ -72,4 +72,3 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], kernel(); } - -- cgit v1.3.1 From 22d1a56cbfb0bff34f477b4db6a55d076d829b83 Mon Sep 17 00:00:00 2001 From: Jens Gehrlein Date: Wed, 26 Sep 2007 17:55:54 +0200 Subject: TQM885D: Exchanged SDRAM timing by a more relaxed timing. CAS-Latency=2, Write Recovery Time tWR=2 The max. supported bus frequency is 66 MHz. Therefore, changed threshold to switch from 1:1 mode to 2:1 from 80 MHz to 66 MHz. Signed-off-by: Martin Krause --- board/tqm8xx/tqm8xx.c | 11 ++++++----- cpu/mpc8xx/speed.c | 5 +---- include/configs/TQM885D.h | 2 +- 3 files changed, 8 insertions(+), 10 deletions(-) (limited to 'cpu') diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c index cebdcc07649..06bf5f8ee23 100644 --- a/board/tqm8xx/tqm8xx.c +++ b/board/tqm8xx/tqm8xx.c @@ -37,6 +37,7 @@ static long int dram_size (long int, long int *, long int); #define _NOT_USED_ 0xFFFFFFFF +/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */ const uint sdram_table[] = { /* @@ -63,14 +64,14 @@ const uint sdram_table[] = /* * Single Write. (Offset 18 in UPMA RAM) */ - 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44, + 0x1FF5FC47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, /* * Burst Write. (Offset 20 in UPMA RAM) */ 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */ - _NOT_USED_, + 0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* @@ -83,7 +84,7 @@ const uint sdram_table[] = /* * Exception. (Offset 3c in UPMA RAM) */ - 0x7FFFFC07, /* last */ + 0xFFFFFC07, /* last */ _NOT_USED_, _NOT_USED_, _NOT_USED_, }; diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c index 101d5f9cb35..11b089330b8 100644 --- a/cpu/mpc8xx/speed.c +++ b/cpu/mpc8xx/speed.c @@ -259,11 +259,8 @@ int get_clocks_866 (void) */ sccr_reg = immr->im_clkrst.car_sccr; sccr_reg &= ~SCCR_EBDF11; -#if defined(CONFIG_TQM885D) - if (gd->cpu_clk <= 80000000) { -#else + if (gd->cpu_clk <= 66000000) { -#endif sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */ gd->bus_clk = gd->cpu_clk; } else { diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index dd26d542627..e0c69652bb2 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -42,7 +42,7 @@ #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ #define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ #define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ -#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 50 MHz - CPU default clock */ +#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ /* (it will be used if there is no */ /* 'cpuclk' variable with valid value) */ -- cgit v1.3.1 From 136288847e3b04f2ff357a067ad45e10afa0a24c Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 13 Dec 2007 14:52:53 +0100 Subject: ppc4xx: Bring 4xx fdt support up-to-date This patch update the 4xx fdt support. It enabled fdt booting on the AMCC Kilauea and Sequoia for now. More can follow later quite easily. Signed-off-by: Stefan Roese --- board/amcc/kilauea/kilauea.c | 1 + board/amcc/sequoia/sequoia.c | 25 +++++++++- cpu/ppc4xx/fdt.c | 114 +++++++++++++------------------------------ include/configs/kilauea.h | 3 +- include/configs/sequoia.h | 6 +++ 5 files changed, 66 insertions(+), 83 deletions(-) (limited to 'cpu') diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c index 96c0dd46003..2ee896abd96 100644 --- a/board/amcc/kilauea/kilauea.c +++ b/board/amcc/kilauea/kilauea.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 4e47ab395b4..f81f07146da 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -23,9 +23,11 @@ */ #include +#include +#include +#include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -583,3 +585,24 @@ int post_hotkeys_pressed(void) return 0; /* No hotkeys supported */ } #endif /* CONFIG_POST */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + u32 val[4]; + int rc; + + ft_cpu_setup(blob, bd); + + /* Fixup NOR mapping */ + val[0] = 0; /* chip select number */ + val[1] = 0; /* always 0 */ + val[2] = gd->bd->bi_flashstart; + val[3] = gd->bd->bi_flashsize; + rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", + val, sizeof(val), 1); + if (rc) + printf("Unable to update property NOR mapping, err=%s\n", + fdt_strerror(rc)); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c index dcedbbb3083..3ef30004fb7 100644 --- a/cpu/ppc4xx/fdt.c +++ b/cpu/ppc4xx/fdt.c @@ -35,25 +35,18 @@ #if defined(CONFIG_OF_LIBFDT) #include #include +#include DECLARE_GLOBAL_DATA_PTR; -static void do_fixup(void *fdt, const char *node, const char *prop, - const void *val, int len, int create) -{ -#if defined(DEBUG) - int i; - debug("Updating property '%s/%s' = ", node, prop); - for (i = 0; i < len; i++) - debug(" %.2x", *(u8*)(val+i)); - debug("(%d)\n", *(u32 *)val); -#endif - int rc = fdt_find_and_setprop(fdt, node, prop, val, len, create); - if (rc) - printf("Unable to update property %s:%s, err=%s\n", - node, prop, fdt_strerror(rc)); -} +/* + * The aliases needed for this generic etherne MAC address + * fixup function are not in place yet. So don't use this + * approach for now. This will be enabled later. + */ +#undef USES_FDT_ALIASES +#ifndef USES_FDT_ALIASES static void do_fixup_macaddr(void *fdt, int offset, const void *val, int i) { int rc; @@ -69,87 +62,47 @@ static void do_fixup_macaddr(void *fdt, int offset, const void *val, int i) printf("Unable to update property %s, err=%s\n", "local-mac-address", fdt_strerror(rc)); } - -static void do_fixup_u32(void *fdt, const char *node, const char *prop, - u32 val, int create) -{ - val = cpu_to_fdt32(val); - do_fixup(fdt, node, prop, &val, sizeof(val), create); -} - -static void do_fixup_uart(void *fdt, int offset, int i, bd_t *bd) -{ - int rc; - u32 val; - PPC4xx_SYS_INFO sys_info; - - get_sys_info(&sys_info); - - debug("Updating node UART%d: clock-frequency=%d\n", i, gd->uart_clk); - - val = cpu_to_fdt32(gd->uart_clk); - rc = fdt_setprop(fdt, offset, "clock-frequency", &val, 4); - if (rc) - printf("Unable to update node UART, err=%s\n", fdt_strerror(rc)); - - val = cpu_to_fdt32(bd->bi_baudrate); - rc = fdt_setprop(fdt, offset, "current-speed", &val, 4); - if (rc) - printf("Unable to update node UART, err=%s\n", fdt_strerror(rc)); -} +#endif /* USES_FDT_ALIASES */ void ft_cpu_setup(void *blob, bd_t *bd) { - char * cpu_path = "/cpus/" OF_CPU; + char *cpu_path = "/cpus/" OF_CPU; sys_info_t sys_info; int offset; int i; - int tmp[2]; - get_sys_info (&sys_info); + get_sys_info(&sys_info); - do_fixup_u32(blob, cpu_path, "timebase-frequency", bd->bi_intfreq, 1); - do_fixup_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); - do_fixup_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1); - do_fixup_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1); - do_fixup_u32(blob, "/plb/opb/ebc", "clock-frequency", sys_info.freqEBC, 1); - - /* update, or add and update /memory node */ - offset = fdt_find_node_by_path(blob, "/memory"); - if (offset < 0) { - offset = fdt_add_subnode(blob, 0, "memory"); - if (offset < 0) - debug("failed to add /memory node: %s\n", - fdt_strerror(offset)); - } - if (offset >= 0) { - fdt_setprop(blob, offset, "device_type", - "memory", sizeof("memory")); - tmp[0] = cpu_to_fdt32(bd->bi_memstart); - tmp[1] = cpu_to_fdt32(bd->bi_memsize); - fdt_setprop(blob, offset, "reg", tmp, sizeof(tmp)); - debug("Updating /memory node to %d:%d\n", - bd->bi_memstart, bd->bi_memsize); - } + do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", bd->bi_intfreq, 1); + do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); + do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1); + do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1); + do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency", + sys_info.freqEBC, 1); + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); /* * Setup all baudrates for the UARTs */ - offset = 0; - for (i = 0; i < 4; i++) { - offset = fdt_find_node_by_type(blob, offset, "serial"); - if (offset < 0) - break; - - do_fixup_uart(blob, offset, i, bd); - } + do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", gd->uart_clk, 1); +#ifdef USES_FDT_ALIASES /* - * Setup all MAC addresses in fdt + * The aliases needed for this generic etherne MAC address + * fixup function are not in place yet. So don't use this + * approach for now. This will be enabled later. */ - offset = 0; + fdt_fixup_ethernet(blob, bd); +#else + offset = -1; for (i = 0; i < 4; i++) { - offset = fdt_find_node_by_type(blob, offset, "network"); + /* + * FIXME: This will cause problems with emac3 compatible + * devices, like on 405GP. But hopefully when we deal + * with those devices, the aliases stuff will be in + * place. + */ + offset = fdt_node_offset_by_compatible(blob, offset, "ibm,emac4"); if (offset < 0) break; @@ -174,5 +127,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif } } +#endif /* USES_FDT_ALIASES */ } #endif /* CONFIG_OF_LIBFDT */ diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index e3f24a44b61..bec9fde73aa 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -519,7 +519,6 @@ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,405EX@0" +#define OF_CPU "cpu@0" #endif /* __CONFIG_H */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 2af675ae146..58acbc090e5 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -487,4 +487,10 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define OF_CPU "cpu@0" + #endif /* __CONFIG_H */ -- cgit v1.3.1 From 871e6ce188a7c6bc7321bcf8372857035d20f1cd Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 14 Dec 2007 08:41:29 +0100 Subject: ppc4xx: fdt: use fdt_fixup_ethernet() By using aliases in the dts file, the ethernet node fixup is much easier with the recently added functions. Please note that the dts file needs the aliases for this to work. Signed-off-by: Stefan Roese --- cpu/ppc4xx/fdt.c | 73 ++------------------------------------------------------ 1 file changed, 2 insertions(+), 71 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c index 3ef30004fb7..f351b8bf3c0 100644 --- a/cpu/ppc4xx/fdt.c +++ b/cpu/ppc4xx/fdt.c @@ -21,11 +21,6 @@ * MA 02111-1307 USA */ -/* define DEBUG for debugging output (obviously ;-)) */ -#if 0 -#define DEBUG -#endif - #include #include #include @@ -39,37 +34,10 @@ DECLARE_GLOBAL_DATA_PTR; -/* - * The aliases needed for this generic etherne MAC address - * fixup function are not in place yet. So don't use this - * approach for now. This will be enabled later. - */ -#undef USES_FDT_ALIASES - -#ifndef USES_FDT_ALIASES -static void do_fixup_macaddr(void *fdt, int offset, const void *val, int i) -{ - int rc; - - debug("Updating node EMAC%d\n", i); - - rc = fdt_setprop(fdt, offset, "mac-address", val, 6); - if (rc) - printf("Unable to update property %s, err=%s\n", - "mac-address", fdt_strerror(rc)); - rc = fdt_setprop(fdt, offset, "local-mac-address", val, 6); - if (rc) - printf("Unable to update property %s, err=%s\n", - "local-mac-address", fdt_strerror(rc)); -} -#endif /* USES_FDT_ALIASES */ - void ft_cpu_setup(void *blob, bd_t *bd) { char *cpu_path = "/cpus/" OF_CPU; sys_info_t sys_info; - int offset; - int i; get_sys_info(&sys_info); @@ -86,47 +54,10 @@ void ft_cpu_setup(void *blob, bd_t *bd) */ do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", gd->uart_clk, 1); -#ifdef USES_FDT_ALIASES /* - * The aliases needed for this generic etherne MAC address - * fixup function are not in place yet. So don't use this - * approach for now. This will be enabled later. + * Fixup all ethernet nodes + * Note: aliases in the dts are required for this */ fdt_fixup_ethernet(blob, bd); -#else - offset = -1; - for (i = 0; i < 4; i++) { - /* - * FIXME: This will cause problems with emac3 compatible - * devices, like on 405GP. But hopefully when we deal - * with those devices, the aliases stuff will be in - * place. - */ - offset = fdt_node_offset_by_compatible(blob, offset, "ibm,emac4"); - if (offset < 0) - break; - - switch (i) { - case 0: - do_fixup_macaddr(blob, offset, bd->bi_enetaddr, 0); - break; -#ifdef CONFIG_HAS_ETH1 - case 1: - do_fixup_macaddr(blob, offset, bd->bi_enet1addr, 1); - break; -#endif -#ifdef CONFIG_HAS_ETH2 - case 2: - do_fixup_macaddr(blob, offset, bd->bi_enet2addr, 2); - break; -#endif -#ifdef CONFIG_HAS_ETH3 - case 3: - do_fixup_macaddr(blob, offset, bd->bi_enet3addr, 3); - break; -#endif - } - } -#endif /* USES_FDT_ALIASES */ } #endif /* CONFIG_OF_LIBFDT */ -- cgit v1.3.1 From ba79fde58a48c0a6ff8e2a96caba951594142203 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 14 Dec 2007 11:19:56 +0100 Subject: ppc4xx: fix flush + invalidate_dcache_range arguments flush + invalidate_dcache_range() expect the start and stop+1 address. So the stop address is the first address behind (!) the range. Signed-off-by: Matthias Fuchs --- cpu/ppc4xx/4xx_enet.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index c20dc730ef0..bfe0864d11b 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -849,7 +849,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) } #ifdef CONFIG_4xx_DCACHE - flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE - 1); + flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE); bd_uncached = bis->bi_memsize; program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE, TLB_WORD2_I_ENABLE); @@ -1064,7 +1064,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */ memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len); - flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len - 1); + flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len); /*-----------------------------------------------------------------------+ * set TX Buffer busy, and send it @@ -1566,7 +1566,7 @@ static int ppc_4xx_eth_rx (struct eth_device *dev) /* NetReceive(NetRxPackets[i], length); */ invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr, (u32)hw_p->rx[user_index].data_ptr + - length - 4 - 1); + length - 4); NetReceive (NetRxPackets[user_index], length - 4); /* Free Recv Buffer */ hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY; -- cgit v1.3.1 From 85dc2a7f82d11e17f0ca2a448118aed7f7a4b85d Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Fri, 30 Nov 2007 18:35:11 +0100 Subject: PPC4xx: Minimal changes to add vxWorks support Signed-off-by: Niklaus Giger --- cpu/ppc4xx/start.S | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index f5a135f1a01..645ac0b8dd7 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1356,7 +1356,11 @@ relocate_code: dccci 0,0 /* Invalidate data cache, now no longer our stack */ sync isync - addi r1,r0,0x0000 /* TLB entry #0 */ +#ifdef CFG_TLB_FOR_BOOT_FLASH + addi r1,r0,CFG_TLB_FOR_BOOT_FLASH /* Use defined TLB */ +#else + addi r1,r0,0x0000 /* Default TLB entry is #0 */ +#endif tlbre r0,r1,0x0002 /* Read contents */ ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ tlbwe r0,r1,0x0002 /* Save it out */ -- cgit v1.3.1 From 42ed33ffe135f618680f9d6e9712eb35a85bcb62 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Wed, 5 Dec 2007 17:43:20 +0100 Subject: Fix ppc4xx clear_bss() code ppc4xx clear_bss() fails if BSS segment size is not divisible by 4 without remainder. This patch provides fix for this problem. Signed-off-by: Anatolij Gustschin --- cpu/ppc4xx/start.S | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 645ac0b8dd7..52601ed7003 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1494,16 +1494,25 @@ clear_bss: lwz r4,GOT(_end) cmplw 0, r3, r4 - beq 6f + beq 7f li r0, 0 -5: + + andi. r5, r4, 3 + beq 6f + sub r4, r4, r5 + mtctr r5 + mr r5, r4 +5: stb r0, 0(r5) + addi r5, r5, 1 + bdnz 5b +6: stw r0, 0(r3) addi r3, r3, 4 cmplw 0, r3, r4 - bne 5b -6: + bne 6b +7: mr r3, r9 /* Init Data pointer */ mr r4, r10 /* Destination Address */ bl board_init_r -- cgit v1.3.1 From 328a340392a5df9aaf00792be989df73e750859e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 18 Dec 2007 08:44:51 +0100 Subject: ppc4xx: fdt: Cleanup setup of cpu node setup Now the cpu node setup ("timebase-frequency" and "clock-frequency") is without using the absolute path to the cpu node. This makes it possible to use this U-Boot version with both versions of cpu-node naming "cpu@0" and the former "PowerPC,440EPx@0". Signed-off-by: Stefan Roese --- cpu/ppc4xx/fdt.c | 7 ++++--- include/configs/kilauea.h | 1 - include/configs/sequoia.h | 1 - 3 files changed, 4 insertions(+), 5 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c index f351b8bf3c0..afcb9740685 100644 --- a/cpu/ppc4xx/fdt.c +++ b/cpu/ppc4xx/fdt.c @@ -36,13 +36,14 @@ DECLARE_GLOBAL_DATA_PTR; void ft_cpu_setup(void *blob, bd_t *bd) { - char *cpu_path = "/cpus/" OF_CPU; sys_info_t sys_info; get_sys_info(&sys_info); - do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", bd->bi_intfreq, 1); - do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", + bd->bi_intfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", + bd->bi_intfreq, 1); do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1); do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1); do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency", diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index bec9fde73aa..f3e8601d850 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -519,6 +519,5 @@ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "cpu@0" #endif /* __CONFIG_H */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 419ee733498..48a64e3fd83 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -492,6 +492,5 @@ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "cpu@0" #endif /* __CONFIG_H */ -- cgit v1.3.1 From c348578bf612d0c56d8d376d23cae16defbd86af Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Thu, 27 Dec 2007 10:50:55 -0500 Subject: Add Ethernet 1000BASE-X support for PPC4xx This patch adds a new switch: "CONFIG_PHY_DYNAMIC_ANEG". When this symbol is defined, the PHY will advertise it's capabilities for autonegotiation based on the capabilities shown in the PHY's status registers, including 1000BASE-X. When "CONFIG_PHY_DYNAMIC_ANEG" is not defined, the PHY will advertise hard-coded capabilities, as before. Signed-off-by: Larry Johnson --- cpu/ppc4xx/miiphy.c | 166 ++++++++++++++++++++++++++++++++++++---------------- 1 file changed, 114 insertions(+), 52 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index 98ba0a7b356..4216f0bd41b 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -27,19 +27,6 @@ | | Author: Mark Wisner | - | Change Activity- - | - | Date Description of Change BY - | --------- --------------------- --- - | 05-May-99 Created MKW - | 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to - | better match OPB speed. Also modified delay times. JWB - | 29-Jul-99 Added Full duplex support MKW - | 24-Aug-99 Removed printf from dp83843_duplex() JWB - | 19-Jul-00 Ported to esd cpci405 sr - | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS - | - | +-----------------------------------------------------------------------------*/ #include @@ -61,7 +48,6 @@ void miiphy_dump (char *devname, unsigned char addr) unsigned long i; unsigned short data; - for (i = 0; i < 0x1A; i++) { if (miiphy_read (devname, addr, i, &data)) { printf ("read error for reg %lx\n", i); @@ -76,15 +62,86 @@ void miiphy_dump (char *devname, unsigned char addr) } /* end for loop */ } /* end dump */ - /***********************************************************/ /* (Re)start autonegotiation */ /***********************************************************/ int phy_setup_aneg (char *devname, unsigned char addr) { - unsigned short ctl, adv; + u16 bmcr; + +#if defined(CONFIG_PHY_DYNAMIC_ANEG) + /* + * Set up advertisement based on capablilities reported by the PHY. + * This should work for both copper and fiber. + */ + u16 bmsr; +#if defined(CONFIG_PHY_GIGE) + u16 exsr = 0x0000; +#endif + + miiphy_read (devname, addr, PHY_BMSR, &bmsr); + +#if defined(CONFIG_PHY_GIGE) + if (bmsr & PHY_BMSR_EXT_STAT) + miiphy_read (devname, addr, PHY_EXSR, &exsr); + + if (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH)) { + /* 1000BASE-X */ + u16 anar = 0x0000; + + if (exsr & PHY_EXSR_1000XF) + anar |= PHY_X_ANLPAR_FD; + + if (exsr & PHY_EXSR_1000XH) + anar |= PHY_X_ANLPAR_HD; + + miiphy_write (devname, addr, PHY_ANAR, anar); + } else +#endif + { + u16 anar, btcr; + + miiphy_read (devname, addr, PHY_ANAR, &anar); + anar &= ~(0x5000 | PHY_ANLPAR_T4 | PHY_ANLPAR_TXFD | + PHY_ANLPAR_TX | PHY_ANLPAR_10FD | PHY_ANLPAR_10); + + miiphy_read (devname, addr, PHY_1000BTCR, &btcr); + btcr &= ~(0x00FF | PHY_1000BTCR_1000FD | PHY_1000BTCR_1000HD); + + if (bmsr & PHY_BMSR_100T4) + anar |= PHY_ANLPAR_T4; + + if (bmsr & PHY_BMSR_100TXF) + anar |= PHY_ANLPAR_TXFD; + + if (bmsr & PHY_BMSR_100TXH) + anar |= PHY_ANLPAR_TX; + + if (bmsr & PHY_BMSR_10TF) + anar |= PHY_ANLPAR_10FD; + + if (bmsr & PHY_BMSR_10TH) + anar |= PHY_ANLPAR_10; + + miiphy_write (devname, addr, PHY_ANAR, anar); + +#if defined(CONFIG_PHY_GIGE) + if (exsr & PHY_EXSR_1000TF) + btcr |= PHY_1000BTCR_1000FD; + + if (exsr & PHY_EXSR_1000TH) + btcr |= PHY_1000BTCR_1000HD; + + miiphy_write (devname, addr, PHY_1000BTCR, btcr); +#endif + } + +#else /* defined(CONFIG_PHY_DYNAMIC_ANEG) */ + /* + * Set up standard advertisement + */ + u16 adv; - /* Setup standard advertise */ miiphy_read (devname, addr, PHY_ANAR, &adv); adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 | PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | @@ -95,15 +152,16 @@ int phy_setup_aneg (char *devname, unsigned char addr) adv |= (0x0300); miiphy_write (devname, addr, PHY_1000BTCR, adv); +#endif /* defined(CONFIG_PHY_DYNAMIC_ANEG) */ + /* Start/Restart aneg */ - miiphy_read (devname, addr, PHY_BMCR, &ctl); - ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - miiphy_write (devname, addr, PHY_BMCR, ctl); + miiphy_read (devname, addr, PHY_BMCR, &bmcr); + bmcr |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + miiphy_write (devname, addr, PHY_BMCR, bmcr); return 0; } - /***********************************************************/ /* read a phy reg and return the value with a rc */ /***********************************************************/ @@ -116,19 +174,23 @@ unsigned int miiphy_getemac_offset (void) /* Need to find out which mdi port we're using */ zmii = in_be32((void *)ZMII_FER); - if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) { + if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) /* using port 0 */ eoffset = 0; - } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) { + + else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) /* using port 1 */ eoffset = 0x100; - } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) { + + else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) /* using port 2 */ eoffset = 0x400; - } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) { + + else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) /* using port 3 */ eoffset = 0x600; - } else { + + else { /* None of the mdi ports are enabled! */ /* enable port 0 */ zmii |= ZMII_FER_MDI << ZMII_FER_V (0); @@ -156,21 +218,20 @@ unsigned int miiphy_getemac_offset (void) #endif } - -int emac4xx_miiphy_read (char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) +int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) { unsigned long sta_reg; /* STA scratch area */ unsigned long i; unsigned long emac_reg; - emac_reg = miiphy_getemac_offset (); /* see if it is ready for 1000 nsec */ i = 0; /* see if it is ready for sec */ - while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { + while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == + EMAC_STACR_OC_MASK) { udelay (7); if (i > 5) { #ifdef ET_DEBUG @@ -187,10 +248,10 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EX) -#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ - sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ; +#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ + sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ; #else - sta_reg |= EMAC_STACR_READ; + sta_reg |= EMAC_STACR_READ; #endif #else sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ; @@ -211,37 +272,34 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, sta_reg = in_be32((void *)EMAC_STACR + emac_reg); #ifdef ET_DEBUG - printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ + printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif i = 0; while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { udelay (7); - if (i > 5) { + if (i > 5) return -1; - } + i++; sta_reg = in_be32((void *)EMAC_STACR + emac_reg); #ifdef ET_DEBUG printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif } - if ((sta_reg & EMAC_STACR_PHYE) != 0) { + if ((sta_reg & EMAC_STACR_PHYE) != 0) return -1; - } - *value = *(short *) (&sta_reg); + *value = *(short *)(&sta_reg); return 0; - } /* phy_read */ - /***********************************************************/ /* write a phy reg and return the value with a rc */ /***********************************************************/ -int emac4xx_miiphy_write (char *devname, unsigned char addr, - unsigned char reg, unsigned short value) +int emac4xx_miiphy_write (char *devname, unsigned char addr, unsigned char reg, + unsigned short value) { unsigned long sta_reg; /* STA scratch area */ unsigned long i; @@ -251,9 +309,11 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, /* see if it is ready for 1000 nsec */ i = 0; - while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { + while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == + EMAC_STACR_OC_MASK) { if (i > 5) return -1; + udelay (7); i++; } @@ -263,10 +323,10 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EX) -#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ - sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE; +#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ + sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE; #else - sta_reg |= EMAC_STACR_WRITE; + sta_reg |= EMAC_STACR_WRITE; #endif #else sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ; @@ -278,8 +338,8 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, !defined(CONFIG_405EX) sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */ #endif - sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */ - sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ + sta_reg = sta_reg | ((unsigned long)addr << 5); /* Phy address */ + sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ memcpy (&sta_reg, &value, 2); /* put in data */ out_be32((void *)EMAC_STACR + emac_reg, sta_reg); @@ -288,12 +348,13 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, i = 0; sta_reg = in_be32((void *)EMAC_STACR + emac_reg); #ifdef ET_DEBUG - printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ + printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { udelay (7); if (i > 5) return -1; + i++; sta_reg = in_be32((void *)EMAC_STACR + emac_reg); #ifdef ET_DEBUG @@ -303,6 +364,7 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, if ((sta_reg & EMAC_STACR_PHYE) != 0) return -1; + return 0; -} /* phy_write */ +} /* phy_write */ -- cgit v1.3.1 From 8a24a6963002cb867d5a6b70e3560f0b1467f55f Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Sat, 22 Dec 2007 15:15:30 -0500 Subject: Copy 440EPx/GRx SDRAM data-eye search to common directory This patch creates a non-board-specific file for performing the SDRAM data-eye search. It also adds ECC error checking to the test of valid data on readback when ECC is enabled. Signed-off-by: Larry Johnson --- cpu/ppc4xx/denali_data_eye.c | 396 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 396 insertions(+) create mode 100644 cpu/ppc4xx/denali_data_eye.c (limited to 'cpu') diff --git a/cpu/ppc4xx/denali_data_eye.c b/cpu/ppc4xx/denali_data_eye.c new file mode 100644 index 00000000000..6c949a0fe15 --- /dev/null +++ b/cpu/ppc4xx/denali_data_eye.c @@ -0,0 +1,396 @@ +/* + * cpu/ppc4xx/denali_data_eye.c + * Extracted from board/amcc/sequoia/sdram.c by Larry Johnson . + * + * (C) Copyright 2006 + * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com + * + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + +#include +#include +#include +#include + +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +/*-----------------------------------------------------------------------------+ + * denali_wait_for_dlllock. + +----------------------------------------------------------------------------*/ +int denali_wait_for_dlllock(void) +{ + u32 val; + int wait; + + /* -----------------------------------------------------------+ + * Wait for the DCC master delay line to finish calibration + * ----------------------------------------------------------*/ + for (wait = 0; wait != 0xffff; ++wait) { + mfsdram(DDR0_17, val); + if (DDR0_17_DLLLOCKREG_DECODE(val)) { + /* dlllockreg bit on */ + return 0; + } + } + debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val); + debug("Waiting for dlllockreg bit to raise\n"); + return -1; +} + +#if defined(CONFIG_DDR_DATA_EYE) +#define DDR_DCR_BASE 0x10 +#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ +#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ + +/*-----------------------------------------------------------------------------+ + * wait_for_dram_init_complete. + +----------------------------------------------------------------------------*/ +static int wait_for_dram_init_complete(void) +{ + unsigned long val; + int wait = 0; + + /* --------------------------------------------------------------+ + * Wait for 'DRAM initialization complete' bit in status register + * -------------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_00); + + while (wait != 0xffff) { + val = mfdcr(ddrcfgd); + if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6) + /* 'DRAM initialization complete' bit */ + return 0; + else + wait++; + } + debug("DRAM initialization complete bit in status register did not " + "rise\n"); + return -1; +} + +#define NUM_TRIES 64 +#define NUM_READS 10 + +/*-----------------------------------------------------------------------------+ + * denali_core_search_data_eye. + +----------------------------------------------------------------------------*/ +/* + * Avoid conflict with implementations of denali_core_search_data_eye in board- + * specific code. + */ +void denali_core_search_data_eye(void) + __attribute__ ((weak, alias("__denali_core_search_data_eye"))); + +void __denali_core_search_data_eye(void) +{ + int k, j; + u32 val; + u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X; + u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0; + u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0; + u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0; + volatile u32 *ram_pointer; + u32 test[NUM_TRIES] = { + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 + }; + + ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE); + + for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) { + /* for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) { */ + + /* -----------------------------------------------------------+ + * De-assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | + DDR0_02_START_OFF; + mtdcr(ddrcfgd, val); + + /* -----------------------------------------------------------+ + * Set 'wr_dqs_shift' + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_09); + val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) | + DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); + mtdcr(ddrcfgd, val); + + /* -----------------------------------------------------------+ + * Set 'dqs_out_shift' = wr_dqs_shift + 32 + * ----------------------------------------------------------*/ + dqs_out_shift = wr_dqs_shift + 32; + mtdcr(ddrcfga, DDR0_22); + val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) | + DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); + mtdcr(ddrcfgd, val); + + passing_cases = 0; + + for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; + dll_dqs_delay_X++) { + /* for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; + dll_dqs_delay_X++) { */ + /* -----------------------------------------------------------+ + * Set 'dll_dqs_delay_X'. + * ----------------------------------------------------------*/ + /* dll_dqs_delay_0 */ + mtdcr(ddrcfga, DDR0_17); + val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) + | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + /* dll_dqs_delay_1 to dll_dqs_delay_4 */ + mtdcr(ddrcfga, DDR0_18); + val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) + | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + /* dll_dqs_delay_5 to dll_dqs_delay_8 */ + mtdcr(ddrcfga, DDR0_19); + val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) + | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + /* clear any ECC errors */ + mtdcr(ddrcfga, DDR0_00); + mtdcr(ddrcfgd, + mfdcr(ddrcfgd) | DDR0_00_INT_ACK_ENCODE(0x3C)); + + sync(); + eieio(); + + /* -----------------------------------------------------------+ + * Assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | + DDR0_02_START_ON; + mtdcr(ddrcfgd, val); + + sync(); + eieio(); + + /* -----------------------------------------------------------+ + * Wait for the DCC master delay line to finish calibration + * ----------------------------------------------------------*/ + if (denali_wait_for_dlllock() != 0) { + printf("dll lock did not occur !!!\n"); + printf("denali_core_search_data_eye!!!\n"); + printf("wr_dqs_shift = %d - dll_dqs_delay_X = " + "%d\n", wr_dqs_shift, dll_dqs_delay_X); + hang(); + } + sync(); + eieio(); + + if (wait_for_dram_init_complete() != 0) { + printf("dram init complete did not occur!!!\n"); + printf("denali_core_search_data_eye!!!\n"); + printf("wr_dqs_shift = %d - dll_dqs_delay_X = " + "%d\n", wr_dqs_shift, dll_dqs_delay_X); + hang(); + } + udelay(100); /* wait 100us to ensure init is really completed !!! */ + + /* write values */ + for (j = 0; j < NUM_TRIES; j++) { + ram_pointer[j] = test[j]; + + /* clear any cache at ram location */ + __asm__("dcbf 0,%0": :"r"(&ram_pointer[j])); + } + + /* read values back */ + for (j = 0; j < NUM_TRIES; j++) { + for (k = 0; k < NUM_READS; k++) { + /* clear any cache at ram location */ + __asm__("dcbf 0,%0": :"r"(&ram_pointer + [j])); + + if (ram_pointer[j] != test[j]) + break; + } + + /* read error */ + if (k != NUM_READS) + break; + } + + /* See if the dll_dqs_delay_X value passed. */ + mtdcr(ddrcfga, DDR0_00); + if (j < NUM_TRIES + || (DDR0_00_INT_STATUS_DECODE(mfdcr(ddrcfgd)) & + 0x3F)) { + /* Failed */ + passing_cases = 0; + /* break; */ + } else { + /* Passed */ + if (passing_cases == 0) + dll_dqs_delay_X_sw_val = + dll_dqs_delay_X; + passing_cases++; + if (passing_cases >= max_passing_cases) { + max_passing_cases = passing_cases; + wr_dqs_shift_with_max_passing_cases = + wr_dqs_shift; + dll_dqs_delay_X_start_window = + dll_dqs_delay_X_sw_val; + dll_dqs_delay_X_end_window = + dll_dqs_delay_X; + } + } + + /* -----------------------------------------------------------+ + * De-assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | + DDR0_02_START_OFF; + mtdcr(ddrcfgd, val); + } /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */ + } /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */ + + /* -----------------------------------------------------------+ + * Largest passing window is now detected. + * ----------------------------------------------------------*/ + + /* Compute dll_dqs_delay_X value */ + dll_dqs_delay_X = (dll_dqs_delay_X_end_window + + dll_dqs_delay_X_start_window) / 2; + wr_dqs_shift = wr_dqs_shift_with_max_passing_cases; + + debug("DQS calibration - Window detected:\n"); + debug("max_passing_cases = %d\n", max_passing_cases); + debug("wr_dqs_shift = %d\n", wr_dqs_shift); + debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X); + debug("dll_dqs_delay_X window = %d - %d\n", + dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window); + + /* -----------------------------------------------------------+ + * De-assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; + mtdcr(ddrcfgd, val); + + /* -----------------------------------------------------------+ + * Set 'wr_dqs_shift' + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_09); + val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) + | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); + mtdcr(ddrcfgd, val); + debug("DDR0_09=0x%08lx\n", val); + + /* -----------------------------------------------------------+ + * Set 'dqs_out_shift' = wr_dqs_shift + 32 + * ----------------------------------------------------------*/ + dqs_out_shift = wr_dqs_shift + 32; + mtdcr(ddrcfga, DDR0_22); + val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) + | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); + mtdcr(ddrcfgd, val); + debug("DDR0_22=0x%08lx\n", val); + + /* -----------------------------------------------------------+ + * Set 'dll_dqs_delay_X'. + * ----------------------------------------------------------*/ + /* dll_dqs_delay_0 */ + mtdcr(ddrcfga, DDR0_17); + val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) + | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + debug("DDR0_17=0x%08lx\n", val); + + /* dll_dqs_delay_1 to dll_dqs_delay_4 */ + mtdcr(ddrcfga, DDR0_18); + val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) + | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + debug("DDR0_18=0x%08lx\n", val); + + /* dll_dqs_delay_5 to dll_dqs_delay_8 */ + mtdcr(ddrcfga, DDR0_19); + val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) + | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + debug("DDR0_19=0x%08lx\n", val); + + /* -----------------------------------------------------------+ + * Assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON; + mtdcr(ddrcfgd, val); + + sync(); + eieio(); + + /* -----------------------------------------------------------+ + * Wait for the DCC master delay line to finish calibration + * ----------------------------------------------------------*/ + if (denali_wait_for_dlllock() != 0) { + printf("dll lock did not occur !!!\n"); + hang(); + } + sync(); + eieio(); + + if (wait_for_dram_init_complete() != 0) { + printf("dram init complete did not occur !!!\n"); + hang(); + } + udelay(100); /* wait 100us to ensure init is really completed !!! */ +} +#endif /* defined(CONFIG_DDR_DATA_EYE) */ +#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ -- cgit v1.3.1 From aba19604d848b2838cfb9ebe818909e6a216058e Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Thu, 27 Dec 2007 10:54:48 -0500 Subject: Add 440EPx DDR2 SPD DIMM support This patch adds SPD DDR2 support for the 440EPx ("Denali") SDRAM controller. It should also work on the 440GRx. It is based on the DDR2 SPD code for the 440EP/440EPx, but makes no provision for DDR1 support. This code has been tested on prototype Korat boards with three Kingston DIMMS: 512 MiB ECC (one rank), 512 MiB non-ECC (one rank) and 1 GiB ECC (two ranks). The Korat board has a single DIMM socket, but support has been provided (though not tested) for boards with two DIMM sockets. Signed-off-by: Larry Johnson --- cpu/ppc4xx/denali_spd_ddr2.c | 1254 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 1254 insertions(+) create mode 100644 cpu/ppc4xx/denali_spd_ddr2.c (limited to 'cpu') diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c new file mode 100644 index 00000000000..825bc2139c7 --- /dev/null +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -0,0 +1,1254 @@ +/* + * cpu/ppc4xx/denali_spd_ddr2.c + * This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core + * DDR2 controller, specifically the 440EPx/GRx. + * + * (C) Copyright 2007 + * Larry Johnson, lrj@acm.org. + * + * Based primarily on cpu/ppc4xx/4xx_spd_ddr2.c, which is... + * + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * COPYRIGHT AMCC CORPORATION 2004 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_SPD_EEPROM) && \ + (defined(CONFIG_440EPX) || defined(CONFIG_440GRX)) + +/*-----------------------------------------------------------------------------+ + * Defines + *-----------------------------------------------------------------------------*/ +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#define MAXDIMMS 2 +#define MAXRANKS 2 + +#define ONE_BILLION 1000000000 + +#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d)) + +#define DLL_DQS_DELAY 0x19 +#define DLL_DQS_BYPASS 0x0B +#define DQS_OUT_SHIFT 0x7F + +/* + * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory + * region. Right now the cache should still be disabled in U-Boot because of the + * EMAC driver, that need it's buffer descriptor to be located in non cached + * memory. + * + * If at some time this restriction doesn't apply anymore, just define + * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup + * everything correctly. + */ +#if defined(CFG_ENABLE_SDRAM_CACHE) +#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ +#else +#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ +#endif + +/*-----------------------------------------------------------------------------+ + * Prototypes + *-----------------------------------------------------------------------------*/ +extern int denali_wait_for_dlllock(void); +extern void denali_core_search_data_eye(void); +extern void dcbz_area(u32 start_address, u32 num_bytes); +extern void dflush(void); + +/* + * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed + */ +void __spd_ddr_init_hang(void) +{ + hang(); +} +void spd_ddr_init_hang(void) + __attribute__ ((weak, alias("__spd_ddr_init_hang"))); + +#if defined(DEBUG) +static void print_mcsr(void) +{ + printf("MCSR = 0x%08X\n", mfspr(SPRN_MCSR)); +} + +static void denali_sdram_register_dump(void) +{ + unsigned int sdram_data; + + printf("\n Register Dump:\n"); + mfsdram(DDR0_00, sdram_data); + printf(" DDR0_00 = 0x%08X", sdram_data); + mfsdram(DDR0_01, sdram_data); + printf(" DDR0_01 = 0x%08X\n", sdram_data); + mfsdram(DDR0_02, sdram_data); + printf(" DDR0_02 = 0x%08X", sdram_data); + mfsdram(DDR0_03, sdram_data); + printf(" DDR0_03 = 0x%08X\n", sdram_data); + mfsdram(DDR0_04, sdram_data); + printf(" DDR0_04 = 0x%08X", sdram_data); + mfsdram(DDR0_05, sdram_data); + printf(" DDR0_05 = 0x%08X\n", sdram_data); + mfsdram(DDR0_06, sdram_data); + printf(" DDR0_06 = 0x%08X", sdram_data); + mfsdram(DDR0_07, sdram_data); + printf(" DDR0_07 = 0x%08X\n", sdram_data); + mfsdram(DDR0_08, sdram_data); + printf(" DDR0_08 = 0x%08X", sdram_data); + mfsdram(DDR0_09, sdram_data); + printf(" DDR0_09 = 0x%08X\n", sdram_data); + mfsdram(DDR0_10, sdram_data); + printf(" DDR0_10 = 0x%08X", sdram_data); + mfsdram(DDR0_11, sdram_data); + printf(" DDR0_11 = 0x%08X\n", sdram_data); + mfsdram(DDR0_12, sdram_data); + printf(" DDR0_12 = 0x%08X", sdram_data); + mfsdram(DDR0_14, sdram_data); + printf(" DDR0_14 = 0x%08X\n", sdram_data); + mfsdram(DDR0_17, sdram_data); + printf(" DDR0_17 = 0x%08X", sdram_data); + mfsdram(DDR0_18, sdram_data); + printf(" DDR0_18 = 0x%08X\n", sdram_data); + mfsdram(DDR0_19, sdram_data); + printf(" DDR0_19 = 0x%08X", sdram_data); + mfsdram(DDR0_20, sdram_data); + printf(" DDR0_20 = 0x%08X\n", sdram_data); + mfsdram(DDR0_21, sdram_data); + printf(" DDR0_21 = 0x%08X", sdram_data); + mfsdram(DDR0_22, sdram_data); + printf(" DDR0_22 = 0x%08X\n", sdram_data); + mfsdram(DDR0_23, sdram_data); + printf(" DDR0_23 = 0x%08X", sdram_data); + mfsdram(DDR0_24, sdram_data); + printf(" DDR0_24 = 0x%08X\n", sdram_data); + mfsdram(DDR0_25, sdram_data); + printf(" DDR0_25 = 0x%08X", sdram_data); + mfsdram(DDR0_26, sdram_data); + printf(" DDR0_26 = 0x%08X\n", sdram_data); + mfsdram(DDR0_27, sdram_data); + printf(" DDR0_27 = 0x%08X", sdram_data); + mfsdram(DDR0_28, sdram_data); + printf(" DDR0_28 = 0x%08X\n", sdram_data); + mfsdram(DDR0_31, sdram_data); + printf(" DDR0_31 = 0x%08X", sdram_data); + mfsdram(DDR0_32, sdram_data); + printf(" DDR0_32 = 0x%08X\n", sdram_data); + mfsdram(DDR0_33, sdram_data); + printf(" DDR0_33 = 0x%08X", sdram_data); + mfsdram(DDR0_34, sdram_data); + printf(" DDR0_34 = 0x%08X\n", sdram_data); + mfsdram(DDR0_35, sdram_data); + printf(" DDR0_35 = 0x%08X", sdram_data); + mfsdram(DDR0_36, sdram_data); + printf(" DDR0_36 = 0x%08X\n", sdram_data); + mfsdram(DDR0_37, sdram_data); + printf(" DDR0_37 = 0x%08X", sdram_data); + mfsdram(DDR0_38, sdram_data); + printf(" DDR0_38 = 0x%08X\n", sdram_data); + mfsdram(DDR0_39, sdram_data); + printf(" DDR0_39 = 0x%08X", sdram_data); + mfsdram(DDR0_40, sdram_data); + printf(" DDR0_40 = 0x%08X\n", sdram_data); + mfsdram(DDR0_41, sdram_data); + printf(" DDR0_41 = 0x%08X", sdram_data); + mfsdram(DDR0_42, sdram_data); + printf(" DDR0_42 = 0x%08X\n", sdram_data); + mfsdram(DDR0_43, sdram_data); + printf(" DDR0_43 = 0x%08X", sdram_data); + mfsdram(DDR0_44, sdram_data); + printf(" DDR0_44 = 0x%08X\n", sdram_data); +} +#else +static inline void denali_sdram_register_dump(void) +{ +} + +inline static void print_mcsr(void) +{ +} +#endif /* defined(DEBUG) */ + +static int is_ecc_enabled(void) +{ + u32 val; + + mfsdram(DDR0_22, val); + return 0x3 == DDR0_22_CTRL_RAW_DECODE(val); +} + +static unsigned char spd_read(u8 chip, unsigned int addr) +{ + u8 data[2]; + + if (0 != i2c_probe(chip) || 0 != i2c_read(chip, addr, 1, data, 1)) { + debug("spd_read(0x%02X, 0x%02X) failed\n", chip, addr); + return 0; + } + debug("spd_read(0x%02X, 0x%02X) returned 0x%02X\n", + chip, addr, data[0]); + return data[0]; +} + +static unsigned long get_tcyc(unsigned char reg) +{ + /* + * Byte 9, et al: Cycle time for CAS Latency=X, is split into two + * nibbles: the higher order nibble (bits 4-7) designates the cycle time + * to a granularity of 1ns; the value presented by the lower order + * nibble (bits 0-3) has a granularity of .1ns and is added to the value + * designated by the higher nibble. In addition, four lines of the lower + * order nibble are assigned to support +.25, +.33, +.66, and +.75. + */ + + unsigned char subfield_b = reg & 0x0F; + + switch (subfield_b & 0x0F) { + case 0x0: + case 0x1: + case 0x2: + case 0x3: + case 0x4: + case 0x5: + case 0x6: + case 0x7: + case 0x8: + case 0x9: + return 1000 * (reg >> 4) + 100 * subfield_b; + case 0xA: + return 1000 * (reg >> 4) + 250; + case 0xB: + return 1000 * (reg >> 4) + 333; + case 0xC: + return 1000 * (reg >> 4) + 667; + case 0xD: + return 1000 * (reg >> 4) + 750; + } + return 0; +} + +/*------------------------------------------------------------------ + * Find the installed DIMMs, make sure that the are DDR2, and fill + * in the dimm_ranks array. Then dimm_ranks[dimm_num] > 0 iff the + * DIMM and dimm_num is present. + * Note: Because there are only two chip-select lines, it is assumed + * that a board with a single socket can support two ranks on that + * socket, while a board with two sockets can support only one rank + * on each socket. + *-----------------------------------------------------------------*/ +static void get_spd_info(unsigned long dimm_ranks[], + unsigned long *ranks, + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long dimm_found = FALSE; + unsigned long const max_ranks_per_dimm = (1 == num_dimm_banks) ? 2 : 1; + unsigned char num_of_bytes; + unsigned char total_size; + + *ranks = 0; + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + num_of_bytes = 0; + total_size = 0; + + num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0); + total_size = spd_read(iic0_dimm_addr[dimm_num], 1); + if ((num_of_bytes != 0) && (total_size != 0)) { + unsigned char const dimm_type = + spd_read(iic0_dimm_addr[dimm_num], 2); + + unsigned long ranks_on_dimm = + (spd_read(iic0_dimm_addr[dimm_num], 5) & 0x07) + 1; + + if (8 != dimm_type) { + switch (dimm_type) { + case 1: + printf("ERROR: Standard Fast Page Mode " + "DRAM DIMM"); + break; + case 2: + printf("ERROR: EDO DIMM"); + break; + case 3: + printf("ERROR: Pipelined Nibble DIMM"); + break; + case 4: + printf("ERROR: SDRAM DIMM"); + break; + case 5: + printf("ERROR: Multiplexed ROM DIMM"); + break; + case 6: + printf("ERROR: SGRAM DIMM"); + break; + case 7: + printf("ERROR: DDR1 DIMM"); + break; + default: + printf("ERROR: Unknown DIMM (type %d)", + (unsigned int)dimm_type); + break; + } + printf(" detected in slot %lu.\n", dimm_num); + printf("Only DDR2 SDRAM DIMMs are supported." + "\n"); + printf("Replace the module with a DDR2 DIMM." + "\n\n"); + spd_ddr_init_hang(); + } + dimm_found = TRUE; + debug("DIMM slot %lu: populated with %lu-rank DDR2 DIMM" + "\n", dimm_num, ranks_on_dimm); + if (ranks_on_dimm > max_ranks_per_dimm) { + printf("WARNING: DRAM DIMM in slot %lu has %lu " + "ranks.\n"); + if (1 == max_ranks_per_dimm) { + printf("Only one rank will be used.\n"); + } else { + printf + ("Only two ranks will be used.\n"); + } + ranks_on_dimm = max_ranks_per_dimm; + } + dimm_ranks[dimm_num] = ranks_on_dimm; + *ranks += ranks_on_dimm; + } else { + dimm_ranks[dimm_num] = 0; + debug("DIMM slot %lu: Not populated\n", dimm_num); + } + } + if (dimm_found == FALSE) { + printf("ERROR: No memory installed.\n"); + printf("Install at least one DDR2 DIMM.\n\n"); + spd_ddr_init_hang(); + } + debug("Total number of ranks = %d\n", *ranks); +} + +/*------------------------------------------------------------------ + * For the memory DIMMs installed, this routine verifies that + * frequency previously calculated is supported. + *-----------------------------------------------------------------*/ +static void check_frequency(unsigned long *dimm_ranks, + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq) +{ + unsigned long dimm_num; + unsigned long cycle_time; + unsigned long calc_cycle_time; + + /* + * calc_cycle_time is calculated from DDR frequency set by board/chip + * and is expressed in picoseconds to match the way DIMM cycle time is + * calculated below. + */ + calc_cycle_time = MULDIV64(ONE_BILLION, 1000, sdram_freq); + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_ranks[dimm_num]) { + cycle_time = + get_tcyc(spd_read(iic0_dimm_addr[dimm_num], 9)); + debug("cycle_time=%d ps\n", cycle_time); + + if (cycle_time > (calc_cycle_time + 10)) { + /* + * the provided sdram cycle_time is too small + * for the available DIMM cycle_time. The + * additionnal 10ps is here to accept a small + * incertainty. + */ + printf + ("ERROR: DRAM DIMM detected with cycle_time %d ps in " + "slot %d \n while calculated cycle time is %d ps.\n", + (unsigned int)cycle_time, + (unsigned int)dimm_num, + (unsigned int)calc_cycle_time); + printf + ("Replace the DIMM, or change DDR frequency via " + "strapping bits.\n\n"); + spd_ddr_init_hang(); + } + } + } +} + +/*------------------------------------------------------------------ + * This routine gets size information for the installed memory + * DIMMs. + *-----------------------------------------------------------------*/ +static void get_dimm_size(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long *const rows, + unsigned long *const banks, + unsigned long *const cols, unsigned long *const width) +{ + unsigned long dimm_num; + + *rows = 0; + *banks = 0; + *cols = 0; + *width = 0; + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_ranks[dimm_num]) { + unsigned long t; + + /* Rows */ + t = spd_read(iic0_dimm_addr[dimm_num], 3); + if (0 == *rows) { + *rows = t; + } else if (t != *rows) { + printf("ERROR: DRAM DIMM modules do not all " + "have the same number of rows.\n\n"); + spd_ddr_init_hang(); + } + /* Banks */ + t = spd_read(iic0_dimm_addr[dimm_num], 17); + if (0 == *banks) { + *banks = t; + } else if (t != *banks) { + printf("ERROR: DRAM DIMM modules do not all " + "have the same number of banks.\n\n"); + spd_ddr_init_hang(); + } + /* Columns */ + t = spd_read(iic0_dimm_addr[dimm_num], 4); + if (0 == *cols) { + *cols = t; + } else if (t != *cols) { + printf("ERROR: DRAM DIMM modules do not all " + "have the same number of columns.\n\n"); + spd_ddr_init_hang(); + } + /* Data width */ + t = spd_read(iic0_dimm_addr[dimm_num], 6); + if (0 == *width) { + *width = t; + } else if (t != *width) { + printf("ERROR: DRAM DIMM modules do not all " + "have the same data width.\n\n"); + spd_ddr_init_hang(); + } + } + } + debug("Number of rows = %d\n", *rows); + debug("Number of columns = %d\n", *cols); + debug("Number of banks = %d\n", *banks); + debug("Data width = %d\n", *width); + if (*rows > 14) { + printf("ERROR: DRAM DIMM modules have %lu address rows.\n", + *rows); + printf("Only modules with 14 or fewer rows are supported.\n\n"); + spd_ddr_init_hang(); + } + if (4 != *banks && 8 != *banks) { + printf("ERROR: DRAM DIMM modules have %lu banks.\n", *banks); + printf("Only modules with 4 or 8 banks are supported.\n\n"); + spd_ddr_init_hang(); + } + if (*cols > 12) { + printf("ERROR: DRAM DIMM modules have %lu address columns.\n", + *cols); + printf("Only modules with 12 or fewer columns are " + "supported.\n\n"); + spd_ddr_init_hang(); + } + if (32 != *width && 40 != *width && 64 != *width && 72 != *width) { + printf("ERROR: DRAM DIMM modules have a width of %lu bit.\n", + *width); + printf("Only modules with widths of 32, 40, 64, and 72 bits " + "are supported.\n\n"); + spd_ddr_init_hang(); + } +} + +/*------------------------------------------------------------------ + * Only 1.8V modules are supported. This routine verifies this. + *-----------------------------------------------------------------*/ +static void check_voltage_type(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long voltage_type; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_ranks[dimm_num]) { + voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8); + if (0x05 != voltage_type) { /* 1.8V for DDR2 */ + printf("ERROR: Slot %lu provides 1.8V for DDR2 " + "DIMMs.\n", dimm_num); + switch (voltage_type) { + case 0x00: + printf("This DIMM is 5.0 Volt/TTL.\n"); + break; + case 0x01: + printf("This DIMM is LVTTL.\n"); + break; + case 0x02: + printf("This DIMM is 1.5 Volt.\n"); + break; + case 0x03: + printf("This DIMM is 3.3 Volt/TTL.\n"); + break; + case 0x04: + printf("This DIMM is 2.5 Volt.\n"); + break; + default: + printf("This DIMM is an unknown " + "voltage.\n"); + break; + } + printf("Replace it with a 1.8V DDR2 DIMM.\n\n"); + spd_ddr_init_hang(); + } + } + } +} + +static void program_ddr0_03(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq, + unsigned long rows, unsigned long *cas_latency) +{ + unsigned long dimm_num; + unsigned long cas_index; + unsigned long cycle_2_0_clk; + unsigned long cycle_3_0_clk; + unsigned long cycle_4_0_clk; + unsigned long cycle_5_0_clk; + unsigned long max_2_0_tcyc_ps = 100; + unsigned long max_3_0_tcyc_ps = 100; + unsigned long max_4_0_tcyc_ps = 100; + unsigned long max_5_0_tcyc_ps = 100; + unsigned char cas_available = 0x3C; /* value for DDR2 */ + u32 ddr0_03 = DDR0_03_BSTLEN_ENCODE(0x2) | DDR0_03_INITAREF_ENCODE(0x2); + unsigned int const tcyc_addr[3] = { 9, 23, 25 }; + + /*------------------------------------------------------------------ + * Get the board configuration info. + *-----------------------------------------------------------------*/ + debug("sdram_freq = %d\n", sdram_freq); + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + unsigned char const cas_bit = + spd_read(iic0_dimm_addr[dimm_num], 18); + unsigned char cas_mask; + + cas_available &= cas_bit; + for (cas_mask = 0x80; cas_mask; cas_mask >>= 1) { + if (cas_bit & cas_mask) + break; + } + debug("cas_bit (SPD byte 18) = %02X, cas_mask = %02X\n", + cas_bit, cas_mask); + + for (cas_index = 0; cas_index < 3; + cas_mask >>= 1, cas_index++) { + unsigned long cycle_time_ps; + + if (!(cas_available & cas_mask)) { + continue; + } + cycle_time_ps = + get_tcyc(spd_read(iic0_dimm_addr[dimm_num], + tcyc_addr[cas_index])); + + debug("cas_index = %d: cycle_time_ps = %d\n", + cas_index, cycle_time_ps); + /* + * DDR2 devices use the following bitmask for CAS latency: + * Bit 7 6 5 4 3 2 1 0 + * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD + */ + switch (cas_mask) { + case 0x20: + max_5_0_tcyc_ps = + max(max_5_0_tcyc_ps, cycle_time_ps); + break; + case 0x10: + max_4_0_tcyc_ps = + max(max_4_0_tcyc_ps, cycle_time_ps); + break; + case 0x08: + max_3_0_tcyc_ps = + max(max_3_0_tcyc_ps, cycle_time_ps); + break; + case 0x04: + max_2_0_tcyc_ps = + max(max_2_0_tcyc_ps, cycle_time_ps); + break; + } + } + } + } + debug("cas_available (bit map) = 0x%02X\n", cas_available); + + /*------------------------------------------------------------------ + * Set the SDRAM mode, SDRAM_MMODE + *-----------------------------------------------------------------*/ + + /* add 10 here because of rounding problems */ + cycle_2_0_clk = MULDIV64(ONE_BILLION, 1000, max_2_0_tcyc_ps) + 10; + cycle_3_0_clk = MULDIV64(ONE_BILLION, 1000, max_3_0_tcyc_ps) + 10; + cycle_4_0_clk = MULDIV64(ONE_BILLION, 1000, max_4_0_tcyc_ps) + 10; + cycle_5_0_clk = MULDIV64(ONE_BILLION, 1000, max_5_0_tcyc_ps) + 10; + debug("cycle_2_0_clk = %d\n", cycle_2_0_clk); + debug("cycle_3_0_clk = %d\n", cycle_3_0_clk); + debug("cycle_4_0_clk = %d\n", cycle_4_0_clk); + debug("cycle_5_0_clk = %d\n", cycle_5_0_clk); + + if ((cas_available & 0x04) && (sdram_freq <= cycle_2_0_clk)) { + *cas_latency = 2; + ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x2) | + DDR0_03_CASLAT_LIN_ENCODE(0x4); + } else if ((cas_available & 0x08) && (sdram_freq <= cycle_3_0_clk)) { + *cas_latency = 3; + ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x3) | + DDR0_03_CASLAT_LIN_ENCODE(0x6); + } else if ((cas_available & 0x10) && (sdram_freq <= cycle_4_0_clk)) { + *cas_latency = 4; + ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x4) | + DDR0_03_CASLAT_LIN_ENCODE(0x8); + } else if ((cas_available & 0x20) && (sdram_freq <= cycle_5_0_clk)) { + *cas_latency = 5; + ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x5) | + DDR0_03_CASLAT_LIN_ENCODE(0xA); + } else { + printf("ERROR: Cannot find a supported CAS latency with the " + "installed DIMMs.\n"); + printf("Only DDR2 DIMMs with CAS latencies of 2.0, 3.0, 4.0, " + "and 5.0 are supported.\n"); + printf("Make sure the PLB speed is within the supported range " + "of the DIMMs.\n"); + printf("sdram_freq=%d cycle2=%d cycle3=%d cycle4=%d " + "cycle5=%d\n\n", sdram_freq, cycle_2_0_clk, + cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk); + spd_ddr_init_hang(); + } + debug("CAS latency = %d\n", *cas_latency); + mtsdram(DDR0_03, ddr0_03); +} + +static void program_ddr0_04(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq) +{ + unsigned long dimm_num; + unsigned long t_rc_ps = 0; + unsigned long t_rrd_ps = 0; + unsigned long t_rtp_ps = 0; + unsigned long t_rc_clk; + unsigned long t_rrd_clk; + unsigned long t_rtp_clk; + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + unsigned long ps; + + /* tRC */ + ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 41); + switch (spd_read(iic0_dimm_addr[dimm_num], 40) >> 4) { + case 0x1: + ps += 250; + break; + case 0x2: + ps += 333; + break; + case 0x3: + ps += 500; + break; + case 0x4: + ps += 667; + break; + case 0x5: + ps += 750; + break; + } + t_rc_ps = max(t_rc_ps, ps); + /* tRRD */ + ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 28); + t_rrd_ps = max(t_rrd_ps, ps); + /* tRTP */ + ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 38); + t_rtp_ps = max(t_rtp_ps, ps); + } + } + debug("t_rc_ps = %d\n", t_rc_ps); + t_rc_clk = (MULDIV64(sdram_freq, t_rc_ps, ONE_BILLION) + 999) / 1000; + debug("t_rrd_ps = %d\n", t_rrd_ps); + t_rrd_clk = (MULDIV64(sdram_freq, t_rrd_ps, ONE_BILLION) + 999) / 1000; + debug("t_rtp_ps = %d\n", t_rtp_ps); + t_rtp_clk = (MULDIV64(sdram_freq, t_rtp_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_04, DDR0_04_TRC_ENCODE(t_rc_clk) | + DDR0_04_TRRD_ENCODE(t_rrd_clk) | + DDR0_04_TRTP_ENCODE(t_rtp_clk)); +} + +static void program_ddr0_05(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq) +{ + unsigned long dimm_num; + unsigned long t_rp_ps = 0; + unsigned long t_ras_ps = 0; + unsigned long t_rp_clk; + unsigned long t_ras_clk; + u32 ddr0_05 = DDR0_05_TMRD_ENCODE(0x2) | DDR0_05_TEMRS_ENCODE(0x2); + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + unsigned long ps; + + /* tRP */ + ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 27); + t_rp_ps = max(t_rp_ps, ps); + /* tRAS */ + ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 30); + t_ras_ps = max(t_ras_ps, ps); + } + } + debug("t_rp_ps = %d\n", t_rp_ps); + t_rp_clk = (MULDIV64(sdram_freq, t_rp_ps, ONE_BILLION) + 999) / 1000; + debug("t_ras_ps = %d\n", t_ras_ps); + t_ras_clk = (MULDIV64(sdram_freq, t_ras_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_05, ddr0_05 | DDR0_05_TRP_ENCODE(t_rp_clk) | + DDR0_05_TRAS_MIN_ENCODE(t_ras_clk)); +} + +static void program_ddr0_06(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq) +{ + unsigned long dimm_num; + unsigned char spd_40; + unsigned long t_wtr_ps = 0; + unsigned long t_rfc_ps = 0; + unsigned long t_wtr_clk; + unsigned long t_rfc_clk; + u32 ddr0_06 = + DDR0_06_WRITEINTERP_ENCODE(0x1) | DDR0_06_TDLL_ENCODE(200); + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + unsigned long ps; + + /* tWTR */ + ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 37); + t_wtr_ps = max(t_wtr_ps, ps); + /* tRFC */ + ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 42); + spd_40 = spd_read(iic0_dimm_addr[dimm_num], 40); + ps += 256000 * (spd_40 & 0x01); + switch ((spd_40 & 0x0E) >> 1) { + case 0x1: + ps += 250; + break; + case 0x2: + ps += 333; + break; + case 0x3: + ps += 500; + break; + case 0x4: + ps += 667; + break; + case 0x5: + ps += 750; + break; + } + t_rfc_ps = max(t_rfc_ps, ps); + } + } + debug("t_wtr_ps = %d\n", t_wtr_ps); + t_wtr_clk = (MULDIV64(sdram_freq, t_wtr_ps, ONE_BILLION) + 999) / 1000; + debug("t_rfc_ps = %d\n", t_rfc_ps); + t_rfc_clk = (MULDIV64(sdram_freq, t_rfc_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_06, ddr0_06 | DDR0_06_TWTR_ENCODE(t_wtr_clk) | + DDR0_06_TRFC_ENCODE(t_rfc_clk)); +} + +static void program_ddr0_10(unsigned long dimm_ranks[], unsigned long ranks) +{ + unsigned long csmap; + + if (2 == ranks) { + /* Both chip selects in use */ + csmap = 0x03; + } else { + /* One chip select in use */ + csmap = (1 == dimm_ranks[0]) ? 0x1 : 0x2; + } + mtsdram(DDR0_10, DDR0_10_WRITE_MODEREG_ENCODE(0x0) | + DDR0_10_CS_MAP_ENCODE(csmap) | + DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(0)); +} + +static void program_ddr0_11(unsigned long sdram_freq) +{ + unsigned long const t_xsnr_ps = 200000; /* 200 ns */ + unsigned long t_xsnr_clk; + + debug("t_xsnr_ps = %d\n", t_xsnr_ps); + t_xsnr_clk = + (MULDIV64(sdram_freq, t_xsnr_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_11, DDR0_11_SREFRESH_ENCODE(0) | + DDR0_11_TXSNR_ENCODE(t_xsnr_clk) | DDR0_11_TXSR_ENCODE(200)); +} + +static void program_ddr0_22(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, unsigned long width) +{ +#if defined(CONFIG_DDR_ECC) + unsigned long dimm_num; + unsigned long ecc_available = width >= 64; + u32 ddr0_22 = DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) | + DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) | + DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS); + + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + /* Check for ECC */ + if (0 == (spd_read(iic0_dimm_addr[dimm_num], 11) & + 0x02)) { + ecc_available = FALSE; + } + } + } + if (ecc_available) { + debug("ECC found on all DIMMs present\n"); + mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x3)); + } else { + debug("ECC not found on some or all DIMMs present\n"); + mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x0)); + } +#else + mtsdram(DDR0_22, DDR0_22_CTRL_RAW_ENCODE(0x0) | + DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) | + DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) | + DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS)); +#endif /* defined(CONFIG_DDR_ECC) */ +} + +static void program_ddr0_24(unsigned long ranks) +{ + u32 ddr0_24 = DDR0_24_RTT_PAD_TERMINATION_ENCODE(0x1) | /* 75 ohm */ + DDR0_24_ODT_RD_MAP_CS1_ENCODE(0x0); + + if (2 == ranks) { + /* Both chip selects in use */ + ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x1) | + DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x2); + } else { + /* One chip select in use */ + /* One of the two fields added to ddr0_24 is a "don't care" */ + ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x2) | + DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x1); + } + mtsdram(DDR0_24, ddr0_24); +} + +static void program_ddr0_26(unsigned long sdram_freq) +{ + unsigned long const t_ref_ps = 7800000; /* 7.8 us. refresh */ + /* TODO: check definition of tRAS_MAX */ + unsigned long const t_ras_max_ps = 9 * t_ref_ps; + unsigned long t_ras_max_clk; + unsigned long t_ref_clk; + + /* Round down t_ras_max_clk and t_ref_clk */ + debug("t_ras_max_ps = %d\n", t_ras_max_ps); + t_ras_max_clk = MULDIV64(sdram_freq, t_ras_max_ps, ONE_BILLION) / 1000; + debug("t_ref_ps = %d\n", t_ref_ps); + t_ref_clk = MULDIV64(sdram_freq, t_ref_ps, ONE_BILLION) / 1000; + mtsdram(DDR0_26, DDR0_26_TRAS_MAX_ENCODE(t_ras_max_clk) | + DDR0_26_TREF_ENCODE(t_ref_clk)); +} + +static void program_ddr0_27(unsigned long sdram_freq) +{ + unsigned long const t_init_ps = 200000000; /* 200 us. init */ + unsigned long t_init_clk; + + debug("t_init_ps = %d\n", t_init_ps); + t_init_clk = + (MULDIV64(sdram_freq, t_init_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_27, DDR0_27_EMRS_DATA_ENCODE(0x0000) | + DDR0_27_TINIT_ENCODE(t_init_clk)); +} + +static void program_ddr0_43(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq, + unsigned long cols, unsigned long banks) +{ + unsigned long dimm_num; + unsigned long t_wr_ps = 0; + unsigned long t_wr_clk; + u32 ddr0_43 = DDR0_43_APREBIT_ENCODE(10) | + DDR0_43_COLUMN_SIZE_ENCODE(12 - cols) | + DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0); + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + unsigned long ps; + + ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 36); + t_wr_ps = max(t_wr_ps, ps); + } + } + debug("t_wr_ps = %d\n", t_wr_ps); + t_wr_clk = (MULDIV64(sdram_freq, t_wr_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_43, ddr0_43 | DDR0_43_TWR_ENCODE(t_wr_clk)); +} + +static void program_ddr0_44(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq) +{ + unsigned long dimm_num; + unsigned long t_rcd_ps = 0; + unsigned long t_rcd_clk; + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + unsigned long ps; + + ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 29); + t_rcd_ps = max(t_rcd_ps, ps); + } + } + debug("t_rcd_ps = %d\n", t_rcd_ps); + t_rcd_clk = (MULDIV64(sdram_freq, t_rcd_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_44, DDR0_44_TRCD_ENCODE(t_rcd_clk)); +} + +/*-----------------------------------------------------------------------------+ + * initdram. Initializes the 440EPx/GPx DDR SDRAM controller. + * Note: This routine runs from flash with a stack set up in the chip's + * sram space. It is important that the routine does not require .sbss, .bss or + * .data sections. It also cannot call routines that require these sections. + *-----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------- + * Function: initdram + * Description: Configures SDRAM memory banks for DDR operation. + * Auto Memory Configuration option reads the DDR SDRAM EEPROMs + * via the IIC bus and then configures the DDR SDRAM memory + * banks appropriately. If Auto Memory Configuration is + * not used, it is assumed that no DIMM is plugged + *-----------------------------------------------------------------------------*/ +long int initdram(int board_type) +{ + unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; + unsigned long dimm_ranks[MAXDIMMS]; + unsigned long ranks; + unsigned long rows; + unsigned long banks; + unsigned long cols; + unsigned long width; + unsigned long const sdram_freq = get_bus_freq(0); + unsigned long const num_dimm_banks = sizeof(iic0_dimm_addr); /* on board dimm banks */ + unsigned long cas_latency = 0; /* to quiet initialization warning */ + unsigned long dram_size; + + debug("\nEntering initdram()\n"); + + /*------------------------------------------------------------------ + * Stop the DDR-SDRAM controller. + *-----------------------------------------------------------------*/ + mtsdram(DDR0_02, DDR0_02_START_ENCODE(0)); + + /* + * Make sure I2C controller is initialized + * before continuing. + */ + /* switch to correct I2C bus */ + I2C_SET_BUS(CFG_SPD_BUS_NUM); + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + + /*------------------------------------------------------------------ + * Clear out the serial presence detect buffers. + * Perform IIC reads from the dimm. Fill in the spds. + * Check to see if the dimm slots are populated + *-----------------------------------------------------------------*/ + get_spd_info(dimm_ranks, &ranks, iic0_dimm_addr, num_dimm_banks); + + /*------------------------------------------------------------------ + * Check the frequency supported for the dimms plugged. + *-----------------------------------------------------------------*/ + check_frequency(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); + + /*------------------------------------------------------------------ + * Check and get size information. + *-----------------------------------------------------------------*/ + get_dimm_size(dimm_ranks, iic0_dimm_addr, num_dimm_banks, &rows, &banks, + &cols, &width); + + /*------------------------------------------------------------------ + * Check the voltage type for the dimms plugged. + *-----------------------------------------------------------------*/ + check_voltage_type(dimm_ranks, iic0_dimm_addr, num_dimm_banks); + + /*------------------------------------------------------------------ + * Program registers for SDRAM controller. + *-----------------------------------------------------------------*/ + mtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) | + DDR0_00_DLL_START_POINT_DECODE(0x0A)); + + mtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x01) | + DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0x00) | + DDR0_01_INT_MASK_ENCODE(0xFF)); + + program_ddr0_03(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq, + rows, &cas_latency); + + program_ddr0_04(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); + + program_ddr0_05(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); + + program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); + + /*------------------------------------------------------------------ + * TODO: tFAW not found in SPD. Value of 13 taken from Sequoia + * board SDRAM, but may be overly concervate. + *-----------------------------------------------------------------*/ + mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) | + DDR0_07_TFAW_ENCODE(13) | + DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) | + DDR0_07_AREFRESH_ENCODE(0)); + + mtsdram(DDR0_08, DDR0_08_WRLAT_ENCODE(cas_latency - 1) | + DDR0_08_TCPD_ENCODE(200) | DDR0_08_DQS_N_EN_ENCODE(0) | + DDR0_08_DDRII_ENCODE(1)); + + mtsdram(DDR0_09, DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(0x00) | + DDR0_09_RTT_0_ENCODE(0x1) | + DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(0x1D) | + DDR0_09_WR_DQS_SHIFT_ENCODE(DQS_OUT_SHIFT - 0x20)); + + program_ddr0_10(dimm_ranks, ranks); + + program_ddr0_11(sdram_freq); + + mtsdram(DDR0_12, DDR0_12_TCKE_ENCODE(3)); + + mtsdram(DDR0_14, DDR0_14_DLL_BYPASS_MODE_ENCODE(0) | + DDR0_14_REDUC_ENCODE(width <= 40 ? 1 : 0) | + DDR0_14_REG_DIMM_ENABLE_ENCODE(0)); + + mtsdram(DDR0_17, DDR0_17_DLL_DQS_DELAY_0_ENCODE(DLL_DQS_DELAY)); + + mtsdram(DDR0_18, DDR0_18_DLL_DQS_DELAY_4_ENCODE(DLL_DQS_DELAY) | + DDR0_18_DLL_DQS_DELAY_3_ENCODE(DLL_DQS_DELAY) | + DDR0_18_DLL_DQS_DELAY_2_ENCODE(DLL_DQS_DELAY) | + DDR0_18_DLL_DQS_DELAY_1_ENCODE(DLL_DQS_DELAY)); + + mtsdram(DDR0_19, DDR0_19_DLL_DQS_DELAY_8_ENCODE(DLL_DQS_DELAY) | + DDR0_19_DLL_DQS_DELAY_7_ENCODE(DLL_DQS_DELAY) | + DDR0_19_DLL_DQS_DELAY_6_ENCODE(DLL_DQS_DELAY) | + DDR0_19_DLL_DQS_DELAY_5_ENCODE(DLL_DQS_DELAY)); + + mtsdram(DDR0_20, DDR0_20_DLL_DQS_BYPASS_3_ENCODE(DLL_DQS_BYPASS) | + DDR0_20_DLL_DQS_BYPASS_2_ENCODE(DLL_DQS_BYPASS) | + DDR0_20_DLL_DQS_BYPASS_1_ENCODE(DLL_DQS_BYPASS) | + DDR0_20_DLL_DQS_BYPASS_0_ENCODE(DLL_DQS_BYPASS)); + + mtsdram(DDR0_21, DDR0_21_DLL_DQS_BYPASS_7_ENCODE(DLL_DQS_BYPASS) | + DDR0_21_DLL_DQS_BYPASS_6_ENCODE(DLL_DQS_BYPASS) | + DDR0_21_DLL_DQS_BYPASS_5_ENCODE(DLL_DQS_BYPASS) | + DDR0_21_DLL_DQS_BYPASS_4_ENCODE(DLL_DQS_BYPASS)); + + program_ddr0_22(dimm_ranks, iic0_dimm_addr, num_dimm_banks, width); + + mtsdram(DDR0_23, DDR0_23_ODT_RD_MAP_CS0_ENCODE(0x0) | + DDR0_23_FWC_ENCODE(0)); + + program_ddr0_24(ranks); + + program_ddr0_26(sdram_freq); + + program_ddr0_27(sdram_freq); + + mtsdram(DDR0_28, DDR0_28_EMRS3_DATA_ENCODE(0x0000) | + DDR0_28_EMRS2_DATA_ENCODE(0x0000)); + + mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000)); + + mtsdram(DDR0_42, DDR0_42_ADDR_PINS_DECODE(14 - rows) | + DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency)); + + program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq, + cols, banks); + + program_ddr0_44(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); + + denali_sdram_register_dump(); + + dram_size = (width >= 64) ? 8 : 4; + dram_size *= 1 << cols; + dram_size *= banks; + dram_size *= 1 << rows; + dram_size *= ranks; + debug("dram_size = %lu\n", dram_size); + + /* Start the SDRAM controler */ + mtsdram(DDR0_02, DDR0_02_START_ENCODE(1)); + denali_wait_for_dlllock(); + +#if defined(CONFIG_DDR_DATA_EYE) + /* -----------------------------------------------------------+ + * Perform data eye search if requested. + * ----------------------------------------------------------*/ + program_tlb(0, CFG_SDRAM_BASE, dram_size, TLB_WORD2_I_ENABLE); + denali_core_search_data_eye(); + denali_sdram_register_dump(); + remove_tlb(CFG_SDRAM_BASE, dram_size); +#endif + +#if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) + program_tlb(0, CFG_SDRAM_BASE, dram_size, 0); + sync(); + eieio(); + /* Zero the memory */ + debug("Zeroing SDRAM..."); + dcbz_area(CFG_SDRAM_BASE, dram_size); + dflush(); + debug("Completed\n"); + sync(); + eieio(); + remove_tlb(CFG_SDRAM_BASE, dram_size); + +#if defined(CONFIG_DDR_ECC) + /* + * If ECC is enabled, clear and enable interrupts + */ + if (is_ecc_enabled()) { + u32 val; + + sync(); + eieio(); + /* Clear error status */ + mfsdram(DDR0_00, val); + mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); + /* Set 'int_mask' parameter to functionnal value */ + mfsdram(DDR0_01, val); + mtsdram(DDR0_01, (val & ~DDR0_01_INT_MASK_MASK) | + DDR0_01_INT_MASK_ALL_OFF); +#if defined(CONFIG_DDR_DATA_EYE) + /* + * Running denali_core_search_data_eye() when ECC is enabled + * causes non-ECC machine checks. This clears them. + */ + print_mcsr(); + mtspr(SPRN_MCSR, mfspr(SPRN_MCSR)); + print_mcsr(); +#endif + sync(); + eieio(); + } +#endif /* defined(CONFIG_DDR_ECC) */ +#endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */ + + program_tlb(0, CFG_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE); + return dram_size; +} + +void board_add_ram_info(int use_default) +{ + u32 val; + + printf(" (ECC"); + if (!is_ecc_enabled()) { + printf(" not"); + } + printf(" enabled, %d MHz", (2 * get_bus_freq(0)) / 1000000); + + mfsdram(DDR0_03, val); + printf(", CL%d)", DDR0_03_CASLAT_LIN_DECODE(val) >> 1); +} +#endif /* CONFIG_SPD_EEPROM */ -- cgit v1.3.1 From 8eb52d5d982b764b39c88d9d1064d56c5397bfa5 Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Sat, 22 Dec 2007 15:16:11 -0500 Subject: Add denali_data_eye.o and denali_spd_ddr2.o to PPC4xx Makefile Signed-off-by: Larry Johnson --- cpu/ppc4xx/Makefile | 2 ++ 1 file changed, 2 insertions(+) (limited to 'cpu') diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 9155e9a98d1..178c5c67425 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -43,6 +43,8 @@ COBJS += bedbug_405.o COBJS += commproc.o COBJS += cpu.o COBJS += cpu_init.o +COBJS += denali_data_eye.o +COBJS += denali_spd_ddr2.o COBJS += fdt.o COBJS += gpio.o COBJS += i2c.o -- cgit v1.3.1 From bec9264616fb78273a1d93e87ff4b0b67c7bec1b Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 28 Dec 2007 15:53:46 +0100 Subject: ppc4xx: Fix bug in cpu_init.c (405EP instead of 450EP) Signed-off-by: Stefan Roese Acked-by: Matthias Fuchs --- cpu/ppc4xx/cpu_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 01ab523c512..9c6f79ea99a 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -136,7 +136,7 @@ cpu_init_f (void) out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ #endif -#if defined (CONFIG_450EP) +#if defined (CONFIG_405EP) /* * Set EMAC noise filter bits */ -- cgit v1.3.1 From c05569066dbcba3fdf36d4d1943df265dc316a86 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 28 Dec 2007 16:08:08 +0100 Subject: ppc4xx: Enable 405EP PCI arbiter per default on all boards In an attmemt to clean up the 4xx start.S file, I removed the enabling of the internal 405EP PCI arbiter. This is needed for multiple other 405EP platforms, like most of the esd 405EP. Now the internal PCI arbiter is enabled again per default as it has been before. Signed-off-by: Stefan Roese Acked-by: Matthias Fuchs --- cpu/ppc4xx/cpu_init.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'cpu') diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 9c6f79ea99a..2e0dd6f062f 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -141,6 +141,11 @@ cpu_init_f (void) * Set EMAC noise filter bits */ mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); + + /* + * Enable the internal PCI arbiter + */ + mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); #endif /* CONFIG_405EP */ #endif /* CONFIG_405EP */ -- cgit v1.3.1