From f5a24259190c388c2527bdc49fee34577d862cc7 Mon Sep 17 00:00:00 2001 From: Wheatley Travis Date: Fri, 2 May 2008 13:35:15 -0700 Subject: 7450 and 86xx L2 cache invalidate bug corrections The 7610 and related parts have an L2IP bit in the L2CR that is monitored to signal when the L2 cache invalidate is complete whereas the 7450 and related parts utilize L2I for this purpose. However, the current code does not account for this difference. Additionally the 86xx L2 cache invalidate code used an "andi" instruction where an "andis" instruction should have been used. This patch addresses both of these bugs. Signed-off-by: Travis Wheatley Acked-By: Jon Loeliger --- cpu/74xx_7xx/cache.S | 21 ++++++++++++++++++++- cpu/mpc86xx/cache.S | 2 +- 2 files changed, 21 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/74xx_7xx/cache.S b/cpu/74xx_7xx/cache.S index a793d799d1b..3a745cbe031 100644 --- a/cpu/74xx_7xx/cache.S +++ b/cpu/74xx_7xx/cache.S @@ -329,14 +329,28 @@ _GLOBAL(dcache_status) blr /* - * Invalidate L2 cache using L2I and polling L2IP + * Invalidate L2 cache using L2I and polling L2IP or L2I */ _GLOBAL(l2cache_invalidate) sync + mfspr r3, l2cr oris r3, r3, L2CR_L2I@h sync mtspr l2cr, r3 sync + mfspr r3, PVR + sync + rlwinm r3, r3, 16,16,31 + cmpli 0,r3,0x8000 /* 7451, 7441 */ + beq 0,inv_7450 + cmpli 0,r3,0x8001 /* 7455, 7445 */ + beq 0,inv_7450 + cmpli 0,r3,0x8002 /* 7457, 7447 */ + beq 0,inv_7450 + cmpli 0,r3,0x8003 /* 7447A */ + beq 0,inv_7450 + cmpli 0,r3,0x8004 /* 7448 */ + beq 0,inv_7450 invl2: mfspr r3, l2cr andi. r3, r3, L2CR_L2IP @@ -348,6 +362,11 @@ invl2: mtspr l2cr, r3 sync blr +inv_7450: + mfspr r3, l2cr + andis. r3, r3, L2CR_L2I@h + bne inv_7450 + blr /* * Enable L2 cache diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S index f316b3ec13f..2e4ea0239f1 100644 --- a/cpu/mpc86xx/cache.S +++ b/cpu/mpc86xx/cache.S @@ -338,7 +338,7 @@ _GLOBAL(l2cache_invalidate) invl2: mfspr r3, l2cr - andi. r3, r3, L2CR_L2I@h + andis. r3, r3, L2CR_L2I@h bne invl2 blr -- cgit v1.3.1 From 8fbc985bdad09b23b7eb4df1d2ea589619d8db4c Mon Sep 17 00:00:00 2001 From: Adrian Filipi Date: Tue, 6 May 2008 16:46:37 -0400 Subject: Fix some typos This patch fixes three typos. The first is a repetition of CONFIG_CMD_BSP. The second makes the #endif comment match its #if. The third is a spelling error. Signed-off-by: Adrian Filipi --- README | 1 - cpu/arm920t/s3c24x0/usb.c | 2 +- doc/README.nand-boot-ppc440 | 2 +- 3 files changed, 2 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/README b/README index 5e2bca41c1a..f14fb7bad2a 100644 --- a/README +++ b/README @@ -623,7 +623,6 @@ The following options need to be configured: CONFIG_CMD_SPI * SPI serial bus support CONFIG_CMD_USB * USB support CONFIG_CMD_VFD * VFD support (TRAB) - CONFIG_CMD_BSP * Board SPecific functions CONFIG_CMD_CDP * Cisco Discover Protocol support CONFIG_CMD_FSL * Microblaze FSL support diff --git a/cpu/arm920t/s3c24x0/usb.c b/cpu/arm920t/s3c24x0/usb.c index ef5d5bf71b1..421ebb4373f 100644 --- a/cpu/arm920t/s3c24x0/usb.c +++ b/cpu/arm920t/s3c24x0/usb.c @@ -69,4 +69,4 @@ int usb_cpu_init_fail (void) } # endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */ -#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ +#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) */ diff --git a/doc/README.nand-boot-ppc440 b/doc/README.nand-boot-ppc440 index a1c1d8c4447..1e9c102644b 100644 --- a/doc/README.nand-boot-ppc440 +++ b/doc/README.nand-boot-ppc440 @@ -9,7 +9,7 @@ The PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH, completely without NOR FLASH. This can be done by using the NAND boot feature of the 440 NAND flash controller (NDFC). -Here a short desciption of the different boot stages: +Here a short description of the different boot stages: a) IPL (Initial Program Loader, integrated inside CPU) ------------------------------------------------------ -- cgit v1.3.1