From 24e37645e7378b20fa8f20e2996c8fb8e90c70c9 Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Tue, 23 May 2006 10:33:11 +0200 Subject: More cleanup for the delta board and the generic usb_ohci driver. Added CFG_USB_BOARD_INIT and CFG_USB_CPU_INIT for enabling board and cpu specific initialization and cleanup hooks respectively. --- cpu/pxa/Makefile | 2 +- cpu/pxa/usb.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+), 1 deletion(-) create mode 100644 cpu/pxa/usb.c (limited to 'cpu') diff --git a/cpu/pxa/Makefile b/cpu/pxa/Makefile index 1af53d6ad1d..bd476f150d9 100644 --- a/cpu/pxa/Makefile +++ b/cpu/pxa/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(CPU).a START = start.o -OBJS = serial.o interrupts.o cpu.o i2c.o pxafb.o mmc.o +OBJS = serial.o interrupts.o cpu.o i2c.o pxafb.o mmc.o usb.o all: .depend $(START) $(LIB) diff --git a/cpu/pxa/usb.c b/cpu/pxa/usb.c new file mode 100644 index 00000000000..e89391cf541 --- /dev/null +++ b/cpu/pxa/usb.c @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2006 + * Markus Klotzbuecher, DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifdef CFG_USB_CPU_INIT +# ifdef CONFIG_CPU_MONAHANS +int usb_cpu_init() +{ + /* Enable USB host clock. */ + CKENA |= (CKENA_2_USBHOST | CKENA_20_UDC); + udelay(100); + + /* Configure Port 2 for Host (USB Client Registers) */ + UP2OCR = 0x3000c; + +#if 0 + GPIO2_2 = 0x801; /* USBHPEN - Alt. Fkt. 1 */ + GPIO3_2 = 0x801; /* USBHPWR - Alt. Fkt. 1 */ +#endif + + UHCHR |= UHCHR_FHR; + wait_ms(11); + UHCHR &= ~UHCHR_FHR; + + UHCHR |= UHCHR_FSBIR; + while (UHCHR & UHCHR_FSBIR) + udelay(1); + +#if 0 + UHCHR |= UHCHR_PCPL; /* USBHPEN is active low */ + UHCHR |= UHCHR_PSPL; /* USBHPWR is active low */ +#endif + + UHCHR &= ~UHCHR_SSEP0; + UHCHR &= ~UHCHR_SSEP1; + UHCHR &= ~UHCHR_SSE; + + return 0; +} + +int usb_cpu_stop() +{ + /* may not want to do this */ + /* CKENA &= ~(CKENA_2_USBHOST | CKENA_20_UDC); */ + + return 0; +} +# endif /* CONFIG_CPU_MONAHANS */ +#endif /* CFG_USB_CPU_INIT */ -- cgit v1.3.1 From 301f1aa384d0edcae6a22fd9adb933ad71695ecc Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Tue, 23 May 2006 13:38:35 +0200 Subject: Changed the mp2usb (at91rm9200) board to use the generic OHCI driver. Some fixes to the latter. --- cpu/arm920t/at91rm9200/Makefile | 2 +- cpu/arm920t/at91rm9200/usb.c | 47 ++ cpu/arm920t/at91rm9200/usb_ohci.c | 1635 ------------------------------------- cpu/arm920t/at91rm9200/usb_ohci.h | 419 ---------- cpu/pxa/usb.c | 8 +- drivers/usb_ohci.c | 18 +- include/configs/delta.h | 6 +- include/configs/mp2usb.h | 11 +- 8 files changed, 73 insertions(+), 2073 deletions(-) create mode 100644 cpu/arm920t/at91rm9200/usb.c delete mode 100644 cpu/arm920t/at91rm9200/usb_ohci.c delete mode 100644 cpu/arm920t/at91rm9200/usb_ohci.h (limited to 'cpu') diff --git a/cpu/arm920t/at91rm9200/Makefile b/cpu/arm920t/at91rm9200/Makefile index aec9cb64093..f9fccbc06e7 100644 --- a/cpu/arm920t/at91rm9200/Makefile +++ b/cpu/arm920t/at91rm9200/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(SOC).a OBJS = bcm5221.o dm9161.o ether.o i2c.o interrupts.o \ - lxt972.o serial.o usb_ohci.o + lxt972.o serial.o usb.o SOBJS = lowlevel_init.o all: .depend $(LIB) diff --git a/cpu/arm920t/at91rm9200/usb.c b/cpu/arm920t/at91rm9200/usb.c new file mode 100644 index 00000000000..7b83f23eb38 --- /dev/null +++ b/cpu/arm920t/at91rm9200/usb.c @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2006 + * DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) +# ifdef CONFIG_AT91RM9200 + +#include + +int usb_cpu_init() +{ + /* Enable USB host clock. */ + *AT91C_PMC_SCER = AT91C_PMC_UHP; /* 48MHz clock enabled for UHP */ + *AT91C_PMC_PCER = 1 << AT91C_ID_UHP; /* Peripheral Clock Enable Register */ + return 0; +} + +int usb_cpu_stop() +{ + /* Initialization failed */ + *AT91C_PMC_PCDR = 1 << AT91C_ID_UHP; /* Peripheral Clock Disable Register */ + *AT91C_PMC_SCDR = AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */ + return 0; +} +# endif /* CONFIG_AT91RM9200 */ +#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ diff --git a/cpu/arm920t/at91rm9200/usb_ohci.c b/cpu/arm920t/at91rm9200/usb_ohci.c deleted file mode 100644 index 5b2c56cffc4..00000000000 --- a/cpu/arm920t/at91rm9200/usb_ohci.c +++ /dev/null @@ -1,1635 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200. - * - * (C) Copyright 2003 - * Gary Jennejohn, DENX Software Engineering - * - * Note: Much of this code has been derived from Linux 2.4 - * (C) Copyright 1999 Roman Weissgaerber - * (C) Copyright 2000-2002 David Brownell - * - * Modified for the MP2USB by (C) Copyright 2005 Eric Benard - * ebenard@eukrea.com - based on s3c24x0's driver - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -/* - * IMPORTANT NOTES - * 1 - you MUST define LITTLEENDIAN in the configuration file for the - * board or this driver will NOT work! - * 2 - this driver is intended for use with USB Mass Storage Devices - * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! - * 3 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG - * to activate workaround for bug #41 or this driver will NOT work! - */ - -#include -/* #include no PCI on the S3C24X0 */ - -#ifdef CONFIG_USB_OHCI - -#include - -#include -#include -#include "usb_ohci.h" - -#define OHCI_USE_NPS /* force NoPowerSwitching mode */ -#undef OHCI_VERBOSE_DEBUG /* not always helpful */ - -/* For initializing controller (mask in an HCFS mode too) */ -#define OHCI_CONTROL_INIT \ - (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE - -#define readl(a) (*((vu_long *)(a))) -#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a)) - -#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) - -#undef DEBUG -#ifdef DEBUG -#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) -#else -#define dbg(format, arg...) do {} while(0) -#endif /* DEBUG */ -#define err(format, arg...) printf("ERROR: " format "\n", ## arg) -#undef SHOW_INFO -#ifdef SHOW_INFO -#define info(format, arg...) printf("INFO: " format "\n", ## arg) -#else -#define info(format, arg...) do {} while(0) -#endif - -#define m16_swap(x) swap_16(x) -#define m32_swap(x) swap_32(x) - -/* global ohci_t */ -static ohci_t gohci; -/* this must be aligned to a 256 byte boundary */ -struct ohci_hcca ghcca[1]; -/* a pointer to the aligned storage */ -struct ohci_hcca *phcca; -/* this allocates EDs for all possible endpoints */ -struct ohci_device ohci_dev; -/* urb_priv */ -urb_priv_t urb_priv; -/* RHSC flag */ -int got_rhsc; -/* device which was disconnected */ -struct usb_device *devgone; - -/*-------------------------------------------------------------------------*/ - -/* AMD-756 (D2 rev) reports corrupt register contents in some cases. - * The erratum (#4) description is incorrect. AMD's workaround waits - * till some bits (mostly reserved) are clear; ok for all revs. - */ -#define OHCI_QUIRK_AMD756 0xabcd -#define read_roothub(hc, register, mask) ({ \ - u32 temp = readl (&hc->regs->roothub.register); \ - if (hc->flags & OHCI_QUIRK_AMD756) \ - while (temp & mask) \ - temp = readl (&hc->regs->roothub.register); \ - temp; }) - -static u32 roothub_a (struct ohci *hc) - { return read_roothub (hc, a, 0xfc0fe000); } -static inline u32 roothub_b (struct ohci *hc) - { return readl (&hc->regs->roothub.b); } -static inline u32 roothub_status (struct ohci *hc) - { return readl (&hc->regs->roothub.status); } -static u32 roothub_portstatus (struct ohci *hc, int i) - { return read_roothub (hc, portstatus [i], 0xffe0fce0); } - - -/* forward declaration */ -static int hc_interrupt (void); -static void -td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, - int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); - -/*-------------------------------------------------------------------------* - * URB support functions - *-------------------------------------------------------------------------*/ - -/* free HCD-private data associated with this URB */ - -static void urb_free_priv (urb_priv_t * urb) -{ - int i; - int last; - struct td * td; - - last = urb->length - 1; - if (last >= 0) { - for (i = 0; i <= last; i++) { - td = urb->td[i]; - if (td) { - td->usb_dev = NULL; - urb->td[i] = NULL; - } - } - } -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -static int sohci_get_current_frame_number (struct usb_device * dev); - -/* debug| print the main components of an URB - * small: 0) header + data packets 1) just header */ - -static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, - int transfer_len, struct devrequest * setup, char * str, int small) -{ - urb_priv_t * purb = &urb_priv; - - dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", - str, - sohci_get_current_frame_number (dev), - usb_pipedevice (pipe), - usb_pipeendpoint (pipe), - usb_pipeout (pipe)? 'O': 'I', - usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): - (usb_pipecontrol (pipe)? "CTRL": "BULK"), - purb->actual_length, - transfer_len, dev->status); -#ifdef OHCI_VERBOSE_DEBUG - if (!small) { - int i, len; - - if (usb_pipecontrol (pipe)) { - printf (__FILE__ ": cmd(8):"); - for (i = 0; i < 8 ; i++) - printf (" %02x", ((__u8 *) setup) [i]); - printf ("\n"); - } - if (transfer_len > 0 && buffer) { - printf (__FILE__ ": data(%d/%d):", - purb->actual_length, - transfer_len); - len = usb_pipeout (pipe)? - transfer_len: purb->actual_length; - for (i = 0; i < 16 && i < len; i++) - printf (" %02x", ((__u8 *) buffer) [i]); - printf ("%s\n", i < len? "...": ""); - } - } -#endif -} - -/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ -void ep_print_int_eds (ohci_t *ohci, char * str) { - int i, j; - __u32 * ed_p; - for (i= 0; i < 32; i++) { - j = 5; - ed_p = &(ohci->hcca->int_table [i]); - if (*ed_p == 0) - continue; - printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); - while (*ed_p != 0 && j--) { - ed_t *ed = (ed_t *)m32_swap(ed_p); - printf (" ed: %4x;", ed->hwINFO); - ed_p = &ed->hwNextED; - } - printf ("\n"); - } -} - -static void ohci_dump_intr_mask (char *label, __u32 mask) -{ - dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", - label, - mask, - (mask & OHCI_INTR_MIE) ? " MIE" : "", - (mask & OHCI_INTR_OC) ? " OC" : "", - (mask & OHCI_INTR_RHSC) ? " RHSC" : "", - (mask & OHCI_INTR_FNO) ? " FNO" : "", - (mask & OHCI_INTR_UE) ? " UE" : "", - (mask & OHCI_INTR_RD) ? " RD" : "", - (mask & OHCI_INTR_SF) ? " SF" : "", - (mask & OHCI_INTR_WDH) ? " WDH" : "", - (mask & OHCI_INTR_SO) ? " SO" : "" - ); -} - -static void maybe_print_eds (char *label, __u32 value) -{ - ed_t *edp = (ed_t *)value; - - if (value) { - dbg ("%s %08x", label, value); - dbg ("%08x", edp->hwINFO); - dbg ("%08x", edp->hwTailP); - dbg ("%08x", edp->hwHeadP); - dbg ("%08x", edp->hwNextED); - } -} - -static char * hcfs2string (int state) -{ - switch (state) { - case OHCI_USB_RESET: return "reset"; - case OHCI_USB_RESUME: return "resume"; - case OHCI_USB_OPER: return "operational"; - case OHCI_USB_SUSPEND: return "suspend"; - } - return "?"; -} - -/* dump control and status registers */ -static void ohci_dump_status (ohci_t *controller) -{ - struct ohci_regs *regs = controller->regs; - __u32 temp; - - temp = readl (®s->revision) & 0xff; - if (temp != 0x10) - dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); - - temp = readl (®s->control); - dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, - (temp & OHCI_CTRL_RWE) ? " RWE" : "", - (temp & OHCI_CTRL_RWC) ? " RWC" : "", - (temp & OHCI_CTRL_IR) ? " IR" : "", - hcfs2string (temp & OHCI_CTRL_HCFS), - (temp & OHCI_CTRL_BLE) ? " BLE" : "", - (temp & OHCI_CTRL_CLE) ? " CLE" : "", - (temp & OHCI_CTRL_IE) ? " IE" : "", - (temp & OHCI_CTRL_PLE) ? " PLE" : "", - temp & OHCI_CTRL_CBSR - ); - - temp = readl (®s->cmdstatus); - dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, - (temp & OHCI_SOC) >> 16, - (temp & OHCI_OCR) ? " OCR" : "", - (temp & OHCI_BLF) ? " BLF" : "", - (temp & OHCI_CLF) ? " CLF" : "", - (temp & OHCI_HCR) ? " HCR" : "" - ); - - ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); - ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); - - maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); - - maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); - maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); - - maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); - maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); - - maybe_print_eds ("donehead", readl (®s->donehead)); -} - -static void ohci_dump_roothub (ohci_t *controller, int verbose) -{ - __u32 temp, ndp, i; - - temp = roothub_a (controller); - ndp = (temp & RH_A_NDP); -#ifdef CONFIG_AT91C_PQFP_UHPBUG - ndp = (ndp == 2) ? 1:0; -#endif - if (verbose) { - dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, - ((temp & RH_A_POTPGT) >> 24) & 0xff, - (temp & RH_A_NOCP) ? " NOCP" : "", - (temp & RH_A_OCPM) ? " OCPM" : "", - (temp & RH_A_DT) ? " DT" : "", - (temp & RH_A_NPS) ? " NPS" : "", - (temp & RH_A_PSM) ? " PSM" : "", - ndp - ); - temp = roothub_b (controller); - dbg ("roothub.b: %08x PPCM=%04x DR=%04x", - temp, - (temp & RH_B_PPCM) >> 16, - (temp & RH_B_DR) - ); - temp = roothub_status (controller); - dbg ("roothub.status: %08x%s%s%s%s%s%s", - temp, - (temp & RH_HS_CRWE) ? " CRWE" : "", - (temp & RH_HS_OCIC) ? " OCIC" : "", - (temp & RH_HS_LPSC) ? " LPSC" : "", - (temp & RH_HS_DRWE) ? " DRWE" : "", - (temp & RH_HS_OCI) ? " OCI" : "", - (temp & RH_HS_LPS) ? " LPS" : "" - ); - } - - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus (controller, i); - dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", - i, - temp, - (temp & RH_PS_PRSC) ? " PRSC" : "", - (temp & RH_PS_OCIC) ? " OCIC" : "", - (temp & RH_PS_PSSC) ? " PSSC" : "", - (temp & RH_PS_PESC) ? " PESC" : "", - (temp & RH_PS_CSC) ? " CSC" : "", - - (temp & RH_PS_LSDA) ? " LSDA" : "", - (temp & RH_PS_PPS) ? " PPS" : "", - (temp & RH_PS_PRS) ? " PRS" : "", - (temp & RH_PS_POCI) ? " POCI" : "", - (temp & RH_PS_PSS) ? " PSS" : "", - - (temp & RH_PS_PES) ? " PES" : "", - (temp & RH_PS_CCS) ? " CCS" : "" - ); - } -} - -static void ohci_dump (ohci_t *controller, int verbose) -{ - dbg ("OHCI controller usb-%s state", controller->slot_name); - - /* dumps some of the state we know about */ - ohci_dump_status (controller); - if (verbose) - ep_print_int_eds (controller, "hcca"); - dbg ("hcca frame #%04x", controller->hcca->frame_no); - ohci_dump_roothub (controller, 1); -} - - -#endif /* DEBUG */ - -/*-------------------------------------------------------------------------* - * Interface functions (URB) - *-------------------------------------------------------------------------*/ - -/* get a transfer request */ - -int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - ohci_t *ohci; - ed_t * ed; - urb_priv_t *purb_priv; - int i, size = 0; - - ohci = &gohci; - - /* when controller's hung, permit only roothub cleanup attempts - * such as powering down ports */ - if (ohci->disabled) { - err("sohci_submit_job: EPIPE"); - return -1; - } - - /* every endpoint has a ed, locate and fill it */ - if (!(ed = ep_add_ed (dev, pipe))) { - err("sohci_submit_job: ENOMEM"); - return -1; - } - - /* for the private part of the URB we need the number of TDs (size) */ - switch (usb_pipetype (pipe)) { - case PIPE_BULK: /* one TD for every 4096 Byte */ - size = (transfer_len - 1) / 4096 + 1; - break; - case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ - size = (transfer_len == 0)? 2: - (transfer_len - 1) / 4096 + 3; - break; - } - - if (size >= (N_URB_TD - 1)) { - err("need %d TDs, only have %d", size, N_URB_TD); - return -1; - } - purb_priv = &urb_priv; - purb_priv->pipe = pipe; - - /* fill the private part of the URB */ - purb_priv->length = size; - purb_priv->ed = ed; - purb_priv->actual_length = 0; - - /* allocate the TDs */ - /* note that td[0] was allocated in ep_add_ed */ - for (i = 0; i < size; i++) { - purb_priv->td[i] = td_alloc (dev); - if (!purb_priv->td[i]) { - purb_priv->length = i; - urb_free_priv (purb_priv); - err("sohci_submit_job: ENOMEM"); - return -1; - } - } - - if (ed->state == ED_NEW || (ed->state & ED_DEL)) { - urb_free_priv (purb_priv); - err("sohci_submit_job: EINVAL"); - return -1; - } - - /* link the ed into a chain if is not already */ - if (ed->state != ED_OPER) - ep_link (ohci, ed); - - /* fill the TDs and link it to the ed */ - td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -/* tell us the current USB frame number */ - -static int sohci_get_current_frame_number (struct usb_device *usb_dev) -{ - ohci_t *ohci = &gohci; - - return m16_swap (ohci->hcca->frame_no); -} -#endif - -/*-------------------------------------------------------------------------* - * ED handling functions - *-------------------------------------------------------------------------*/ - -/* link an ed into one of the HC chains */ - -static int ep_link (ohci_t *ohci, ed_t *edi) -{ - volatile ed_t *ed = edi; - - ed->state = ED_OPER; - - switch (ed->type) { - case PIPE_CONTROL: - ed->hwNextED = 0; - if (ohci->ed_controltail == NULL) { - writel (ed, &ohci->regs->ed_controlhead); - } else { - ohci->ed_controltail->hwNextED = m32_swap (ed); - } - ed->ed_prev = ohci->ed_controltail; - if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_CLE; - writel (ohci->hc_control, &ohci->regs->control); - } - ohci->ed_controltail = edi; - break; - - case PIPE_BULK: - ed->hwNextED = 0; - if (ohci->ed_bulktail == NULL) { - writel (ed, &ohci->regs->ed_bulkhead); - } else { - ohci->ed_bulktail->hwNextED = m32_swap (ed); - } - ed->ed_prev = ohci->ed_bulktail; - if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_BLE; - writel (ohci->hc_control, &ohci->regs->control); - } - ohci->ed_bulktail = edi; - break; - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* unlink an ed from one of the HC chains. - * just the link to the ed is unlinked. - * the link from the ed still points to another operational ed or 0 - * so the HC can eventually finish the processing of the unlinked ed */ - -static int ep_unlink (ohci_t *ohci, ed_t *ed) -{ - ed->hwINFO |= m32_swap (OHCI_ED_SKIP); - - switch (ed->type) { - case PIPE_CONTROL: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_CLE; - writel (ohci->hc_control, &ohci->regs->control); - } - writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_controltail == ed) { - ohci->ed_controltail = ed->ed_prev; - } else { - ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; - } - break; - - case PIPE_BULK: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_BLE; - writel (ohci->hc_control, &ohci->regs->control); - } - writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_bulktail == ed) { - ohci->ed_bulktail = ed->ed_prev; - } else { - ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; - } - break; - } - ed->state = ED_UNLINK; - return 0; -} - - -/*-------------------------------------------------------------------------*/ - -/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, - * but the USB stack is a little bit stateless so we do it at every transaction - * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK - * in all other cases the state is left unchanged - * the ed info fields are setted anyway even though most of them should not change */ - -static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) -{ - td_t *td; - ed_t *ed_ret; - volatile ed_t *ed; - - ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | - (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; - - if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { - err("ep_add_ed: pending delete"); - /* pending delete request */ - return NULL; - } - - if (ed->state == ED_NEW) { - ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */ - /* dummy td; end of td list for ed */ - td = td_alloc (usb_dev); - ed->hwTailP = m32_swap (td); - ed->hwHeadP = ed->hwTailP; - ed->state = ED_UNLINK; - ed->type = usb_pipetype (pipe); - ohci_dev.ed_cnt++; - } - - ed->hwINFO = m32_swap (usb_pipedevice (pipe) - | usb_pipeendpoint (pipe) << 7 - | (usb_pipeisoc (pipe)? 0x8000: 0) - | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) - | usb_pipeslow (pipe) << 13 - | usb_maxpacket (usb_dev, pipe) << 16); - - return ed_ret; -} - -/*-------------------------------------------------------------------------* - * TD handling functions - *-------------------------------------------------------------------------*/ - -/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ - -static void td_fill (ohci_t *ohci, unsigned int info, - void *data, int len, - struct usb_device *dev, int index, urb_priv_t *urb_priv) -{ - volatile td_t *td, *td_pt; -#ifdef OHCI_FILL_TRACE - int i; -#endif - - if (index > urb_priv->length) { - err("index > length"); - return; - } - /* use this td as the next dummy */ - td_pt = urb_priv->td [index]; - td_pt->hwNextTD = 0; - - /* fill the old dummy TD */ - td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf); - - td->ed = urb_priv->ed; - td->next_dl_td = NULL; - td->index = index; - td->data = (__u32)data; -#ifdef OHCI_FILL_TRACE - if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) { - for (i = 0; i < len; i++) - printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]); - printf("\n"); - } -#endif - if (!len) - data = 0; - - td->hwINFO = m32_swap (info); - td->hwCBP = m32_swap (data); - if (data) - td->hwBE = m32_swap (data + len - 1); - else - td->hwBE = 0; - td->hwNextTD = m32_swap (td_pt); - td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000); - - /* append to queue */ - td->ed->hwTailP = td->hwNextTD; -} - -/*-------------------------------------------------------------------------*/ - -/* prepare all TDs of a transfer */ - -static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) -{ - ohci_t *ohci = &gohci; - int data_len = transfer_len; - void *data; - int cnt = 0; - __u32 info = 0; - unsigned int toggle = 0; - - /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ - if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { - toggle = TD_T_TOGGLE; - } else { - toggle = TD_T_DATA0; - usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); - } - urb->td_cnt = 0; - if (data_len) - data = buffer; - else - data = 0; - - switch (usb_pipetype (pipe)) { - case PIPE_BULK: - info = usb_pipeout (pipe)? - TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; - while(data_len > 4096) { - td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); - data += 4096; data_len -= 4096; cnt++; - } - info = usb_pipeout (pipe)? - TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; - td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); - cnt++; - - if (!ohci->sleeping) - writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ - break; - - case PIPE_CONTROL: - info = TD_CC | TD_DP_SETUP | TD_T_DATA0; - td_fill (ohci, info, setup, 8, dev, cnt++, urb); - if (data_len > 0) { - info = usb_pipeout (pipe)? - TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; - /* NOTE: mishandles transfers >8K, some >4K */ - td_fill (ohci, info, data, data_len, dev, cnt++, urb); - } - info = usb_pipeout (pipe)? - TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; - td_fill (ohci, info, data, 0, dev, cnt++, urb); - if (!ohci->sleeping) - writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ - break; - } - if (urb->length != cnt) - dbg("TD LENGTH %d != CNT %d", urb->length, cnt); -} - -/*-------------------------------------------------------------------------* - * Done List handling functions - *-------------------------------------------------------------------------*/ - - -/* calculate the transfer length and update the urb */ - -static void dl_transfer_length(td_t * td) -{ - __u32 tdINFO, tdBE, tdCBP; - urb_priv_t *lurb_priv = &urb_priv; - - tdINFO = m32_swap (td->hwINFO); - tdBE = m32_swap (td->hwBE); - tdCBP = m32_swap (td->hwCBP); - - - if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL && - ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { - if (tdBE != 0) { - if (td->hwCBP == 0) - lurb_priv->actual_length += tdBE - td->data + 1; - else - lurb_priv->actual_length += tdCBP - td->data; - } - } -} - -/*-------------------------------------------------------------------------*/ - -/* replies to the request have to be on a FIFO basis so - * we reverse the reversed done-list */ - -static td_t * dl_reverse_done_list (ohci_t *ohci) -{ - __u32 td_list_hc; - td_t *td_rev = NULL; - td_t *td_list = NULL; - urb_priv_t *lurb_priv = NULL; - - td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0; - ohci->hcca->done_head = 0; - - while (td_list_hc) { - td_list = (td_t *)td_list_hc; - - if (TD_CC_GET (m32_swap (td_list->hwINFO))) { - lurb_priv = &urb_priv; - dbg(" USB-error/status: %x : %p", - TD_CC_GET (m32_swap (td_list->hwINFO)), td_list); - if (td_list->ed->hwHeadP & m32_swap (0x1)) { - if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { - td_list->ed->hwHeadP = - (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) | - (td_list->ed->hwHeadP & m32_swap (0x2)); - lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; - } else - td_list->ed->hwHeadP &= m32_swap (0xfffffff2); - } - } - - td_list->next_dl_td = td_rev; - td_rev = td_list; - td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0; - } - return td_list; -} - -/*-------------------------------------------------------------------------*/ - -/* td done list */ -static int dl_done_list (ohci_t *ohci, td_t *td_list) -{ - td_t *td_list_next = NULL; - ed_t *ed; - int cc = 0; - int stat = 0; - /* urb_t *urb; */ - urb_priv_t *lurb_priv; - __u32 tdINFO, edHeadP, edTailP; - - while (td_list) { - td_list_next = td_list->next_dl_td; - - lurb_priv = &urb_priv; - tdINFO = m32_swap (td_list->hwINFO); - - ed = td_list->ed; - - dl_transfer_length(td_list); - - /* error code of transfer */ - cc = TD_CC_GET (tdINFO); - if (cc != 0) { - dbg("ConditionCode %#x", cc); - stat = cc_to_error[cc]; - } - - if (ed->state != ED_NEW) { - edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0; - edTailP = m32_swap (ed->hwTailP); - - /* unlink eds if they are not busy */ - if ((edHeadP == edTailP) && (ed->state == ED_OPER)) - ep_unlink (ohci, ed); - } - - td_list = td_list_next; - } - return stat; -} - -/*-------------------------------------------------------------------------* - * Virtual Root Hub - *-------------------------------------------------------------------------*/ - -/* Device descriptor */ -static __u8 root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'O', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; - -/* Hub class-specific descriptor is constructed dynamically */ - - -/*-------------------------------------------------------------------------*/ - -#define OK(x) len = (x); break -#ifdef DEBUG -#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} -#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} -#else -#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) -#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) -#endif -#define RD_RH_STAT roothub_status(&gohci) -#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) - -/* request to virtual root hub */ - -int rh_check_port_status(ohci_t *controller) -{ - __u32 temp, ndp, i; - int res; - - res = -1; - temp = roothub_a (controller); - ndp = (temp & RH_A_NDP); -#ifdef CONFIG_AT91C_PQFP_UHPBUG - ndp = (ndp == 2) ? 1:0; -#endif - - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus (controller, i); - /* check for a device disconnect */ - if (((temp & (RH_PS_PESC | RH_PS_CSC)) == - (RH_PS_PESC | RH_PS_CSC)) && - ((temp & RH_PS_CCS) == 0)) { - res = i; - break; - } - } - return res; -} - -static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, struct devrequest *cmd) -{ - void * data = buffer; - int leni = transfer_len; - int len = 0; - int stat = 0; - __u32 datab[4]; - __u8 *data_buf = (__u8 *)datab; - __u16 bmRType_bReq; - __u16 wValue; - __u16 wIndex; - __u16 wLength; - -#ifdef DEBUG -urb_priv.actual_length = 0; -pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); -#else - wait_ms(1); -#endif - if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { - info("Root-Hub submit IRQ: NOT implemented"); - return 0; - } - - bmRType_bReq = cmd->requesttype | (cmd->request << 8); - wValue = m16_swap (cmd->value); - wIndex = m16_swap (cmd->index); - wLength = m16_swap (cmd->length); - - info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", - dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); - - switch (bmRType_bReq) { - /* Request Destination: - without flags: Device, - RH_INTERFACE: interface, - RH_ENDPOINT: endpoint, - RH_CLASS means HUB here, - RH_OTHER | RH_CLASS almost ever means HUB_PORT here - */ - - case RH_GET_STATUS: - *(__u16 *) data_buf = m16_swap (1); OK (2); - case RH_GET_STATUS | RH_INTERFACE: - *(__u16 *) data_buf = m16_swap (0); OK (2); - case RH_GET_STATUS | RH_ENDPOINT: - *(__u16 *) data_buf = m16_swap (0); OK (2); - case RH_GET_STATUS | RH_CLASS: - *(__u32 *) data_buf = m32_swap ( - RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); - OK (4); - case RH_GET_STATUS | RH_OTHER | RH_CLASS: - *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); - - case RH_CLEAR_FEATURE | RH_ENDPOINT: - switch (wValue) { - case (RH_ENDPOINT_STALL): OK (0); - } - break; - - case RH_CLEAR_FEATURE | RH_CLASS: - switch (wValue) { - case RH_C_HUB_LOCAL_POWER: - OK(0); - case (RH_C_HUB_OVER_CURRENT): - WR_RH_STAT(RH_HS_OCIC); OK (0); - } - break; - - case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_ENABLE): - WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_POCI); OK (0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); - case (RH_C_PORT_CONNECTION): - WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); - case (RH_C_PORT_ENABLE): - WR_RH_PORTSTAT (RH_PS_PESC); OK (0); - case (RH_C_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); - case (RH_C_PORT_OVER_CURRENT): - WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); - case (RH_C_PORT_RESET): - WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); - } - break; - - case RH_SET_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); - case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT (RH_PS_PRS); - OK (0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); - case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT (RH_PS_PES ); - OK (0); - } - break; - - case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); - - case RH_GET_DESCRIPTOR: - switch ((wValue & 0xff00) >> 8) { - case (0x01): /* device descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_dev_des), - wLength)); - data_buf = root_hub_dev_des; OK(len); - case (0x02): /* configuration descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_config_des), - wLength)); - data_buf = root_hub_config_des; OK(len); - case (0x03): /* string descriptors */ - if(wValue==0x0300) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_str_index0), - wLength)); - data_buf = root_hub_str_index0; - OK(len); - } - if(wValue==0x0301) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_str_index1), - wLength)); - data_buf = root_hub_str_index1; - OK(len); - } - default: - stat = USB_ST_STALLED; - } - break; - - case RH_GET_DESCRIPTOR | RH_CLASS: - { - __u32 temp = roothub_a (&gohci); - - data_buf [0] = 9; /* min length; */ - data_buf [1] = 0x29; - data_buf [2] = temp & RH_A_NDP; -#ifdef CONFIG_AT91C_PQFP_UHPBUG - data_buf [2] = (data_buf [2] == 2) ? 1:0; -#endif - data_buf [3] = 0; - if (temp & RH_A_PSM) /* per-port power switching? */ - data_buf [3] |= 0x1; - if (temp & RH_A_NOCP) /* no overcurrent reporting? */ - data_buf [3] |= 0x10; - else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ - data_buf [3] |= 0x8; - - /* corresponds to data_buf[4-7] */ - datab [1] = 0; - data_buf [5] = (temp & RH_A_POTPGT) >> 24; - temp = roothub_b (&gohci); - data_buf [7] = temp & RH_B_DR; - if (data_buf [2] < 7) { - data_buf [8] = 0xff; - } else { - data_buf [0] += 2; - data_buf [8] = (temp & RH_B_DR) >> 8; - data_buf [10] = data_buf [9] = 0xff; - } - - len = min_t(unsigned int, leni, - min_t(unsigned int, data_buf [0], wLength)); - OK (len); - } - - case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); - - case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); - - default: - dbg ("unsupported root hub command"); - stat = USB_ST_STALLED; - } - -#ifdef DEBUG - ohci_dump_roothub (&gohci, 1); -#else - wait_ms(1); -#endif - - len = min_t(int, len, leni); - if (data != data_buf) - memcpy (data, data_buf, len); - dev->act_len = len; - dev->status = stat; - -#ifdef DEBUG - if (transfer_len) - urb_priv.actual_length = transfer_len; - pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); -#else - wait_ms(1); -#endif - - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/* common code for handling submit messages - used for all but root hub */ -/* accesses. */ -int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - int stat = 0; - int maxsize = usb_maxpacket(dev, pipe); - int timeout; - - /* device pulled? Shortcut the action. */ - if (devgone == dev) { - dev->status = USB_ST_CRC_ERR; - return 0; - } - -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); -#else - wait_ms(1); -#endif - if (!maxsize) { - err("submit_common_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - - if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { - err("sohci_submit_job failed"); - return -1; - } - - wait_ms(10); - /* ohci_dump_status(&gohci); */ - - /* allow more time for a BULK device to react - some are slow */ -#define BULK_TO 5000 /* timeout in milliseconds */ - if (usb_pipetype (pipe) == PIPE_BULK) - timeout = BULK_TO; - else - timeout = 100; - - /* wait for it to complete */ - for (;;) { - /* check whether the controller is done */ - stat = hc_interrupt(); - if (stat < 0) { - stat = USB_ST_CRC_ERR; - break; - } - if (stat >= 0 && stat != 0xff) { - /* 0xff is returned for an SF-interrupt */ - break; - } - if (--timeout) { - wait_ms(1); - } else { - err("CTL:TIMEOUT "); - stat = USB_ST_CRC_ERR; - break; - } - } - /* we got an Root Hub Status Change interrupt */ - if (got_rhsc) { -#ifdef DEBUG - ohci_dump_roothub (&gohci, 1); -#endif - got_rhsc = 0; - /* abuse timeout */ - timeout = rh_check_port_status(&gohci); - if (timeout >= 0) { -#if 0 /* this does nothing useful, but leave it here in case that changes */ - /* the called routine adds 1 to the passed value */ - usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); -#endif - /* - * XXX - * This is potentially dangerous because it assumes - * that only one device is ever plugged in! - */ - devgone = dev; - } - } - - dev->status = stat; - dev->act_len = transfer_len; - -#ifdef DEBUG - pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); -#else - wait_ms(1); -#endif - - /* free TDs in urb_priv */ - urb_free_priv (&urb_priv); - return 0; -} - -/* submit routines called from usb.c */ -int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len) -{ - info("submit_bulk_msg"); - return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); -} - -int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup) -{ - int maxsize = usb_maxpacket(dev, pipe); - - info("submit_control_msg"); -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); -#else - wait_ms(1); -#endif - if (!maxsize) { - err("submit_control_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { - gohci.rh.dev = dev; - /* root hub - redirect */ - return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, - setup); - } - - return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); -} - -int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, int interval) -{ - info("submit_int_msg"); - return -1; -} - -/*-------------------------------------------------------------------------* - * HC functions - *-------------------------------------------------------------------------*/ - -/* reset the HC and BUS */ - -static int hc_reset (ohci_t *ohci) -{ - int timeout = 30; - int smm_timeout = 50; /* 0,5 sec */ - - dbg("%s\n", __FUNCTION__); - - if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ - writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ - info("USB HC TakeOver from SMM"); - while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { - wait_ms (10); - if (--smm_timeout == 0) { - err("USB HC TakeOver failed!"); - return -1; - } - } - } - - /* Disable HC interrupts */ - writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); - - dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n", - ohci->slot_name, - readl(&ohci->regs->control)); - - /* Reset USB (needed by some controllers) */ - writel (0, &ohci->regs->control); - - /* HC Reset requires max 10 us delay */ - writel (OHCI_HCR, &ohci->regs->cmdstatus); - while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { - if (--timeout == 0) { - err("USB HC reset timed out!"); - return -1; - } - udelay (1); - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* Start an OHCI controller, set the BUS operational - * enable interrupts - * connect the virtual root hub */ - -static int hc_start (ohci_t * ohci) -{ - __u32 mask; - unsigned int fminterval; - - ohci->disabled = 1; - - /* Tell the controller where the control and bulk lists are - * The lists are empty now. */ - - writel (0, &ohci->regs->ed_controlhead); - writel (0, &ohci->regs->ed_bulkhead); - - writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ - - fminterval = 0x2edf; - writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); - fminterval |= ((((fminterval - 210) * 6) / 7) << 16); - writel (fminterval, &ohci->regs->fminterval); - writel (0x628, &ohci->regs->lsthresh); - - /* start controller operations */ - ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; - ohci->disabled = 0; - writel (ohci->hc_control, &ohci->regs->control); - - /* disable all interrupts */ - mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | - OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | - OHCI_INTR_OC | OHCI_INTR_MIE); - writel (mask, &ohci->regs->intrdisable); - /* clear all interrupts */ - mask &= ~OHCI_INTR_MIE; - writel (mask, &ohci->regs->intrstatus); - /* Choose the interrupts we care about now - but w/o MIE */ - mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; - writel (mask, &ohci->regs->intrenable); - -#ifdef OHCI_USE_NPS - /* required for AMD-756 and some Mac platforms */ - writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, - &ohci->regs->roothub.a); - writel (RH_HS_LPSC, &ohci->regs->roothub.status); -#endif /* OHCI_USE_NPS */ - -#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);}) - /* POTPGT delay is bits 24-31, in 2 ms units. */ - mdelay ((roothub_a (ohci) >> 23) & 0x1fe); - - /* connect the virtual root hub */ - ohci->rh.devnum = 0; - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* an interrupt happens */ - -static int -hc_interrupt (void) -{ - ohci_t *ohci = &gohci; - struct ohci_regs *regs = ohci->regs; - int ints; - int stat = -1; - - if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) { - ints = OHCI_INTR_WDH; - } else { - ints = readl (®s->intrstatus); - } - - /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ - - if (ints & OHCI_INTR_RHSC) { - got_rhsc = 1; - } - - if (ints & OHCI_INTR_UE) { - ohci->disabled++; - err ("OHCI Unrecoverable Error, controller usb-%s disabled", - ohci->slot_name); - /* e.g. due to PCI Master/Target Abort */ - -#ifdef DEBUG - ohci_dump (ohci, 1); -#else - wait_ms(1); -#endif - /* FIXME: be optimistic, hope that bug won't repeat often. */ - /* Make some non-interrupt context restart the controller. */ - /* Count and limit the retries though; either hardware or */ - /* software errors can go forever... */ - hc_reset (ohci); - return -1; - } - - if (ints & OHCI_INTR_WDH) { - wait_ms(1); - writel (OHCI_INTR_WDH, ®s->intrdisable); - stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); - writel (OHCI_INTR_WDH, ®s->intrenable); - } - - if (ints & OHCI_INTR_SO) { - dbg("USB Schedule overrun\n"); - writel (OHCI_INTR_SO, ®s->intrenable); - stat = -1; - } - - /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ - if (ints & OHCI_INTR_SF) { - unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1; - wait_ms(1); - writel (OHCI_INTR_SF, ®s->intrdisable); - if (ohci->ed_rm_list[frame] != NULL) - writel (OHCI_INTR_SF, ®s->intrenable); - stat = 0xff; - } - - writel (ints, ®s->intrstatus); - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/*-------------------------------------------------------------------------*/ - -/* De-allocate all resources.. */ - -static void hc_release_ohci (ohci_t *ohci) -{ - dbg ("USB HC release ohci usb-%s", ohci->slot_name); - - if (!ohci->disabled) - hc_reset (ohci); -} - -/*-------------------------------------------------------------------------*/ - -/* - * low level initalisation routine, called from usb.c - */ -static char ohci_inited = 0; - -int usb_lowlevel_init(void) -{ - /* - * Enable USB host clock. - */ - *AT91C_PMC_SCER = AT91C_PMC_UHP; /* 48MHz clock enabled for UHP */ - *AT91C_PMC_PCER = 1 << AT91C_ID_UHP; /* Peripheral Clock Enable Register */ - - memset (&gohci, 0, sizeof (ohci_t)); - memset (&urb_priv, 0, sizeof (urb_priv_t)); - - /* align the storage */ - if ((__u32)&ghcca[0] & 0xff) { - err("HCCA not aligned!!"); - return -1; - } - phcca = &ghcca[0]; - info("aligned ghcca %p", phcca); - memset(&ohci_dev, 0, sizeof(struct ohci_device)); - if ((__u32)&ohci_dev.ed[0] & 0x7) { - err("EDs not aligned!!"); - return -1; - } - memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); - if ((__u32)gtd & 0x7) { - err("TDs not aligned!!"); - return -1; - } - ptd = gtd; - gohci.hcca = phcca; - memset (phcca, 0, sizeof (struct ohci_hcca)); - - gohci.disabled = 1; - gohci.sleeping = 0; - gohci.irq = -1; - gohci.regs = (struct ohci_regs *)AT91_USB_HOST_BASE; - - gohci.flags = 0; - gohci.slot_name = "at91rm9200"; - - if (hc_reset (&gohci) < 0) { - hc_release_ohci (&gohci); - /* Initialization failed */ - *AT91C_PMC_PCER = AT91C_ID_UHP; - *AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */ - return -1; - } - - /* FIXME this is a second HC reset; why?? */ -/* writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control); - wait_ms (10);*/ - - if (hc_start (&gohci) < 0) { - err ("can't start usb-%s", gohci.slot_name); - hc_release_ohci (&gohci); - /* Initialization failed */ - *AT91C_PMC_PCER = AT91C_ID_UHP; - *AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */ - return -1; - } - -#ifdef DEBUG - ohci_dump (&gohci, 1); -#else - wait_ms(1); -#endif - ohci_inited = 1; - return 0; -} - -int usb_lowlevel_stop(void) -{ - /* this gets called really early - before the controller has */ - /* even been initialized! */ - if (!ohci_inited) - return 0; - /* TODO release any interrupts, etc. */ - /* call hc_release_ohci() here ? */ - hc_reset (&gohci); - /* may not want to do this */ - *AT91C_PMC_PCER = 1 << AT91C_ID_UHP; - *AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */ - return 0; -} - -#endif /* CONFIG_USB_OHCI */ diff --git a/cpu/arm920t/at91rm9200/usb_ohci.h b/cpu/arm920t/at91rm9200/usb_ohci.h deleted file mode 100644 index ecb4e937b18..00000000000 --- a/cpu/arm920t/at91rm9200/usb_ohci.h +++ /dev/null @@ -1,419 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB. - * - * (C) Copyright 1999 Roman Weissgaerber - * (C) Copyright 2000-2001 David Brownell - * - * usb-ohci.h - */ - - -static int cc_to_error[16] = { - -/* mapping of the OHCI CC status to error codes */ - /* No Error */ 0, - /* CRC Error */ USB_ST_CRC_ERR, - /* Bit Stuff */ USB_ST_BIT_ERR, - /* Data Togg */ USB_ST_CRC_ERR, - /* Stall */ USB_ST_STALLED, - /* DevNotResp */ -1, - /* PIDCheck */ USB_ST_BIT_ERR, - /* UnExpPID */ USB_ST_BIT_ERR, - /* DataOver */ USB_ST_BUF_ERR, - /* DataUnder */ USB_ST_BUF_ERR, - /* reservd */ -1, - /* reservd */ -1, - /* BufferOver */ USB_ST_BUF_ERR, - /* BuffUnder */ USB_ST_BUF_ERR, - /* Not Access */ -1, - /* Not Access */ -1 -}; - -/* ED States */ - -#define ED_NEW 0x00 -#define ED_UNLINK 0x01 -#define ED_OPER 0x02 -#define ED_DEL 0x04 -#define ED_URB_DEL 0x08 - -/* usb_ohci_ed */ -struct ed { - __u32 hwINFO; - __u32 hwTailP; - __u32 hwHeadP; - __u32 hwNextED; - - struct ed *ed_prev; - __u8 int_period; - __u8 int_branch; - __u8 int_load; - __u8 int_interval; - __u8 state; - __u8 type; - __u16 last_iso; - struct ed *ed_rm_list; - - struct usb_device *usb_dev; - __u32 unused[3]; -} __attribute((aligned(16))); -typedef struct ed ed_t; - - -/* TD info field */ -#define TD_CC 0xf0000000 -#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) -#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) -#define TD_EC 0x0C000000 -#define TD_T 0x03000000 -#define TD_T_DATA0 0x02000000 -#define TD_T_DATA1 0x03000000 -#define TD_T_TOGGLE 0x00000000 -#define TD_R 0x00040000 -#define TD_DI 0x00E00000 -#define TD_DI_SET(X) (((X) & 0x07)<< 21) -#define TD_DP 0x00180000 -#define TD_DP_SETUP 0x00000000 -#define TD_DP_IN 0x00100000 -#define TD_DP_OUT 0x00080000 - -#define TD_ISO 0x00010000 -#define TD_DEL 0x00020000 - -/* CC Codes */ -#define TD_CC_NOERROR 0x00 -#define TD_CC_CRC 0x01 -#define TD_CC_BITSTUFFING 0x02 -#define TD_CC_DATATOGGLEM 0x03 -#define TD_CC_STALL 0x04 -#define TD_DEVNOTRESP 0x05 -#define TD_PIDCHECKFAIL 0x06 -#define TD_UNEXPECTEDPID 0x07 -#define TD_DATAOVERRUN 0x08 -#define TD_DATAUNDERRUN 0x09 -#define TD_BUFFEROVERRUN 0x0C -#define TD_BUFFERUNDERRUN 0x0D -#define TD_NOTACCESSED 0x0F - - -#define MAXPSW 1 - -struct td { - __u32 hwINFO; - __u32 hwCBP; /* Current Buffer Pointer */ - __u32 hwNextTD; /* Next TD Pointer */ - __u32 hwBE; /* Memory Buffer End Pointer */ - - __u16 hwPSW[MAXPSW]; - __u8 unused; - __u8 index; - struct ed *ed; - struct td *next_dl_td; - struct usb_device *usb_dev; - int transfer_len; - __u32 data; - - __u32 unused2[2]; -} __attribute((aligned(32))); -typedef struct td td_t; - -#define OHCI_ED_SKIP (1 << 14) - -/* - * The HCCA (Host Controller Communications Area) is a 256 byte - * structure defined in the OHCI spec. that the host controller is - * told the base address of. It must be 256-byte aligned. - */ - -#define NUM_INTS 32 /* part of the OHCI standard */ -struct ohci_hcca { - __u32 int_table[NUM_INTS]; /* Interrupt ED table */ - __u16 frame_no; /* current frame number */ - __u16 pad1; /* set to 0 on each frame_no change */ - __u32 done_head; /* info returned for an interrupt */ - u8 reserved_for_hc[116]; -} __attribute((aligned(256))); - - -/* - * Maximum number of root hub ports. - */ -#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ - -/* - * This is the structure of the OHCI controller's memory mapped I/O - * region. This is Memory Mapped I/O. You must use the readl() and - * writel() macros defined in asm/io.h to access these!! - */ -struct ohci_regs { - /* control and status registers */ - __u32 revision; - __u32 control; - __u32 cmdstatus; - __u32 intrstatus; - __u32 intrenable; - __u32 intrdisable; - /* memory pointers */ - __u32 hcca; - __u32 ed_periodcurrent; - __u32 ed_controlhead; - __u32 ed_controlcurrent; - __u32 ed_bulkhead; - __u32 ed_bulkcurrent; - __u32 donehead; - /* frame counters */ - __u32 fminterval; - __u32 fmremaining; - __u32 fmnumber; - __u32 periodicstart; - __u32 lsthresh; - /* Root hub ports */ - struct ohci_roothub_regs { - __u32 a; - __u32 b; - __u32 status; - __u32 portstatus[MAX_ROOT_PORTS]; - } roothub; -} __attribute((aligned(32))); - - -/* OHCI CONTROL AND STATUS REGISTER MASKS */ - -/* - * HcControl (control) register masks - */ -#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ -#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ -#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ -#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ -#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ -#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ -#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ -#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ -#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ - -/* pre-shifted values for HCFS */ -# define OHCI_USB_RESET (0 << 6) -# define OHCI_USB_RESUME (1 << 6) -# define OHCI_USB_OPER (2 << 6) -# define OHCI_USB_SUSPEND (3 << 6) - -/* - * HcCommandStatus (cmdstatus) register masks - */ -#define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ -#define OHCI_SOC (3 << 16) /* scheduling overrun count */ - -/* - * masks used with interrupt registers: - * HcInterruptStatus (intrstatus) - * HcInterruptEnable (intrenable) - * HcInterruptDisable (intrdisable) - */ -#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ -#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ -#define OHCI_INTR_SF (1 << 2) /* start frame */ -#define OHCI_INTR_RD (1 << 3) /* resume detect */ -#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ -#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ -#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ -#define OHCI_INTR_OC (1 << 30) /* ownership change */ -#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ - - -/* Virtual Root HUB */ -struct virt_root_hub { - int devnum; /* Address of Root Hub endpoint */ - void *dev; /* was urb */ - void *int_addr; - int send; - int interval; -}; - -/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ - -/* destination of request */ -#define RH_INTERFACE 0x01 -#define RH_ENDPOINT 0x02 -#define RH_OTHER 0x03 - -#define RH_CLASS 0x20 -#define RH_VENDOR 0x40 - -/* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 -#define RH_SET_ADDRESS 0x0500 -#define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 -#define RH_GET_CONFIGURATION 0x0880 -#define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 -/* Our Vendor Specific Request */ -#define RH_SET_EP 0x2000 - - -/* Hub port features */ -#define RH_PORT_CONNECTION 0x00 -#define RH_PORT_ENABLE 0x01 -#define RH_PORT_SUSPEND 0x02 -#define RH_PORT_OVER_CURRENT 0x03 -#define RH_PORT_RESET 0x04 -#define RH_PORT_POWER 0x08 -#define RH_PORT_LOW_SPEED 0x09 - -#define RH_C_PORT_CONNECTION 0x10 -#define RH_C_PORT_ENABLE 0x11 -#define RH_C_PORT_SUSPEND 0x12 -#define RH_C_PORT_OVER_CURRENT 0x13 -#define RH_C_PORT_RESET 0x14 - -/* Hub features */ -#define RH_C_HUB_LOCAL_POWER 0x00 -#define RH_C_HUB_OVER_CURRENT 0x01 - -#define RH_DEVICE_REMOTE_WAKEUP 0x00 -#define RH_ENDPOINT_STALL 0x01 - -#define RH_ACK 0x01 -#define RH_REQ_ERR -1 -#define RH_NACK 0x00 - - -/* OHCI ROOT HUB REGISTER MASKS */ - -/* roothub.portstatus [i] bits */ -#define RH_PS_CCS 0x00000001 /* current connect status */ -#define RH_PS_PES 0x00000002 /* port enable status*/ -#define RH_PS_PSS 0x00000004 /* port suspend status */ -#define RH_PS_POCI 0x00000008 /* port over current indicator */ -#define RH_PS_PRS 0x00000010 /* port reset status */ -#define RH_PS_PPS 0x00000100 /* port power status */ -#define RH_PS_LSDA 0x00000200 /* low speed device attached */ -#define RH_PS_CSC 0x00010000 /* connect status change */ -#define RH_PS_PESC 0x00020000 /* port enable status change */ -#define RH_PS_PSSC 0x00040000 /* port suspend status change */ -#define RH_PS_OCIC 0x00080000 /* over current indicator change */ -#define RH_PS_PRSC 0x00100000 /* port reset status change */ - -/* roothub.status bits */ -#define RH_HS_LPS 0x00000001 /* local power status */ -#define RH_HS_OCI 0x00000002 /* over current indicator */ -#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ -#define RH_HS_LPSC 0x00010000 /* local power status change */ -#define RH_HS_OCIC 0x00020000 /* over current indicator change */ -#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ - -/* roothub.b masks */ -#define RH_B_DR 0x0000ffff /* device removable flags */ -#define RH_B_PPCM 0xffff0000 /* port power control mask */ - -/* roothub.a masks */ -#define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ -#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ - -/* urb */ -#define N_URB_TD 48 -typedef struct -{ - ed_t *ed; - __u16 length; /* number of tds associated with this request */ - __u16 td_cnt; /* number of tds already serviced */ - int state; - unsigned long pipe; - int actual_length; - td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ -} urb_priv_t; -#define URB_DEL 1 - -/* - * This is the full ohci controller description - * - * Note how the "proper" USB information is just - * a subset of what the full implementation needs. (Linus) - */ - - -typedef struct ohci { - struct ohci_hcca *hcca; /* hcca */ - /*dma_addr_t hcca_dma;*/ - - int irq; - int disabled; /* e.g. got a UE, we're hung */ - int sleeping; - unsigned long flags; /* for HC bugs */ - - struct ohci_regs *regs; /* OHCI controller's memory */ - - ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ - ed_t *ed_bulktail; /* last endpoint of bulk list */ - ed_t *ed_controltail; /* last endpoint of control list */ - int intrstatus; - __u32 hc_control; /* copy of the hc control reg */ - struct usb_device *dev[32]; - struct virt_root_hub rh; - - const char *slot_name; -} ohci_t; - -#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ - -struct ohci_device { - ed_t ed[NUM_EDS]; - int ed_cnt; -}; - -/* hcd */ -/* endpoint */ -static int ep_link(ohci_t * ohci, ed_t * ed); -static int ep_unlink(ohci_t * ohci, ed_t * ed); -static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); - -/*-------------------------------------------------------------------------*/ - -/* we need more TDs than EDs */ -#define NUM_TD 64 - -/* +1 so we can align the storage */ -td_t gtd[NUM_TD+1]; -/* pointers to aligned storage */ -td_t *ptd; - -/* TDs ... */ -static inline struct td * -td_alloc (struct usb_device *usb_dev) -{ - int i; - struct td *td; - - td = NULL; - for (i = 0; i < NUM_TD; i++) - { - if (ptd[i].usb_dev == NULL) - { - td = &ptd[i]; - td->usb_dev = usb_dev; - break; - } - } - - return td; -} - -static inline void -ed_free (struct ed *ed) -{ - ed->usb_dev = NULL; -} diff --git a/cpu/pxa/usb.c b/cpu/pxa/usb.c index e89391cf541..17161570439 100644 --- a/cpu/pxa/usb.c +++ b/cpu/pxa/usb.c @@ -22,10 +22,12 @@ */ #include -#include -#ifdef CFG_USB_CPU_INIT +#if defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) # ifdef CONFIG_CPU_MONAHANS + +#include + int usb_cpu_init() { /* Enable USB host clock. */ @@ -68,4 +70,4 @@ int usb_cpu_stop() return 0; } # endif /* CONFIG_CPU_MONAHANS */ -#endif /* CFG_USB_CPU_INIT */ +#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ diff --git a/drivers/usb_ohci.c b/drivers/usb_ohci.c index f5af7192f9f..c32245a2497 100644 --- a/drivers/usb_ohci.c +++ b/drivers/usb_ohci.c @@ -1552,13 +1552,13 @@ static char ohci_inited = 0; int usb_lowlevel_init(void) { -#if CFG_USB_CPU_INIT +#if CFG_USB_OHCI_CPU_INIT /* cpu dependant init */ if(usb_cpu_init()) return -1; #endif -#if CFG_USB_BOARD_INIT +#if CFG_USB_OHCI_BOARD_INIT /* board dependant init */ if(usb_board_init()) return -1; @@ -1593,18 +1593,18 @@ int usb_lowlevel_init(void) gohci.regs = (struct ohci_regs *)CFG_USB_OHCI_REGS_BASE; gohci.flags = 0; - gohci.slot_name = CFG_USB_SLOT_NAME; + gohci.slot_name = CFG_USB_OHCI_SLOT_NAME; if (hc_reset (&gohci) < 0) { hc_release_ohci (&gohci); err ("can't reset usb-%s", gohci.slot_name); /* Initialization failed disable clocks */ -#if CFG_USB_BOARD_INIT +#if CFG_USB_OHCI_BOARD_INIT /* board dependant cleanup */ usb_board_stop(); #endif -#if CFG_USB_CPU_INIT +#if CFG_USB_OHCI_CPU_INIT /* cpu dependant cleanup */ usb_cpu_stop(); #endif @@ -1618,12 +1618,12 @@ int usb_lowlevel_init(void) err ("can't start usb-%s", gohci.slot_name); hc_release_ohci (&gohci); /* Initialization failed */ -#if CFG_USB_BOARD_INIT +#if CFG_USB_OHCI_BOARD_INIT /* board dependant cleanup */ usb_board_stop(); #endif -#if CFG_USB_CPU_INIT +#if CFG_USB_OHCI_CPU_INIT /* cpu dependant cleanup */ usb_cpu_stop(); #endif @@ -1649,13 +1649,13 @@ int usb_lowlevel_stop(void) /* call hc_release_ohci() here ? */ hc_reset (&gohci); -#if CFG_USB_BOARD_INIT +#if CFG_USB_OHCI_BOARD_INIT /* board dependant cleanup */ if(usb_board_stop()) return -1; #endif -#if CFG_USB_CPU_INIT +#if CFG_USB_OHCI_CPU_INIT /* cpu dependant cleanup */ if(usb_cpu_stop()) return -1; diff --git a/include/configs/delta.h b/include/configs/delta.h index e6b05e05952..fea821ab9af 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -107,10 +107,10 @@ #define CONFIG_USB_STORAGE 1 #define CONFIG_DOS_PARTITION 1 -#undef CFG_USB_BOARD_INIT -#define CFG_USB_CPU_INIT 1 +#undef CFG_USB_OHCI_BOARD_INIT +#define CFG_USB_OHCI_CPU_INIT 1 #define CFG_USB_OHCI_REGS_BASE OHCI_REGS_BASE -#define CFG_USB_SLOT_NAME "delta" +#define CFG_USB_OHCI_SLOT_NAME "delta" #define LITTLEENDIAN 1 /* used by usb_ohci.c */ diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h index 04f1f240808..edb20f8d88e 100644 --- a/include/configs/mp2usb.h +++ b/include/configs/mp2usb.h @@ -107,6 +107,11 @@ #define CONFIG_DOS_PARTITION 1 #define CONFIG_AT91C_PQFP_UHPBUG 1 +#undef CFG_USB_OHCI_BOARD_INIT +#define CFG_USB_OHCI_CPU_INIT 1 +#define CFG_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE +#define CFG_USB_OHCI_SLOT_NAME "at91rm9200" + #undef CONFIG_HARD_I2C #ifdef CONFIG_HARD_I2C @@ -127,7 +132,7 @@ #define CONFIG_COMMANDS \ ((CONFIG_CMD_DFL | \ CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ + CFG_CMD_DHCP | \ CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_NFS | \ @@ -136,7 +141,7 @@ #else #define CONFIG_COMMANDS \ ((CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ + CFG_CMD_DHCP | \ CFG_CMD_NFS | \ CFG_CMD_SNTP | \ CFG_CMD_USB | \ @@ -156,7 +161,7 @@ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ +#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ #define CFG_MEMTEST_START PHYS_SDRAM #define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 -- cgit v1.3.1 From ddf83a2fcef1a670c45fc585119dcc1fe062c4a9 Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Tue, 30 May 2006 16:56:14 +0200 Subject: Support generic OHCI support for the s3c24x0 cpu. --- cpu/arm920t/at91rm9200/usb.c | 6 ++ cpu/arm920t/s3c24x0/Makefile | 2 +- cpu/arm920t/s3c24x0/usb.c | 72 +++++++++++++++++++++++ cpu/pxa/usb.c | 5 ++ drivers/usb_ohci.c | 133 +++++++++++++++++++++++++++++++++++-------- drivers/usb_ohci.h | 2 + include/configs/trab.h | 5 ++ 7 files changed, 199 insertions(+), 26 deletions(-) create mode 100644 cpu/arm920t/s3c24x0/usb.c (limited to 'cpu') diff --git a/cpu/arm920t/at91rm9200/usb.c b/cpu/arm920t/at91rm9200/usb.c index 7b83f23eb38..98e3cdd58a7 100644 --- a/cpu/arm920t/at91rm9200/usb.c +++ b/cpu/arm920t/at91rm9200/usb.c @@ -43,5 +43,11 @@ int usb_cpu_stop() *AT91C_PMC_SCDR = AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */ return 0; } + +int usb_cpu_init_fail() +{ + usb_cpu_stop(); +} + # endif /* CONFIG_AT91RM9200 */ #endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ diff --git a/cpu/arm920t/s3c24x0/Makefile b/cpu/arm920t/s3c24x0/Makefile index af9e4effce6..f81f84dd276 100644 --- a/cpu/arm920t/s3c24x0/Makefile +++ b/cpu/arm920t/s3c24x0/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(SOC).a OBJS = i2c.o interrupts.o serial.o speed.o \ - usb_ohci.o + usb.o all: .depend $(LIB) diff --git a/cpu/arm920t/s3c24x0/usb.c b/cpu/arm920t/s3c24x0/usb.c new file mode 100644 index 00000000000..8114034cc13 --- /dev/null +++ b/cpu/arm920t/s3c24x0/usb.c @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2006 + * DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) +# if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) + +#if defined(CONFIG_S3C2400) +# include +#elif defined(CONFIG_S3C2410) +# include +#endif + +int usb_cpu_init() +{ + + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + /* + * Set the 48 MHz UPLL clocking. Values are taken from + * "PLL value selection guide", 6-23, s3c2400_UM.pdf. + */ + clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2); + gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */ + + /* + * Enable USB host clock. + */ + clk_power->CLKCON |= (1 << 4); + + return 0; +} + +int usb_cpu_stop() +{ + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + /* may not want to do this */ + clk_power->CLKCON &= ~(1 << 4); + return 0; +} + +int usb_cpu_init_fail() +{ + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + clk_power->CLKCON &= ~(1 << 4); + return 0; +} + +# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */ +#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ diff --git a/cpu/pxa/usb.c b/cpu/pxa/usb.c index 17161570439..bff5bfb6ae9 100644 --- a/cpu/pxa/usb.c +++ b/cpu/pxa/usb.c @@ -66,8 +66,13 @@ int usb_cpu_stop() { /* may not want to do this */ /* CKENA &= ~(CKENA_2_USBHOST | CKENA_20_UDC); */ + return 0; +} +int usb_cpu_init_fail() +{ return 0; } + # endif /* CONFIG_CPU_MONAHANS */ #endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ diff --git a/drivers/usb_ohci.c b/drivers/usb_ohci.c index c32245a2497..9b3ca1232da 100644 --- a/drivers/usb_ohci.c +++ b/drivers/usb_ohci.c @@ -21,7 +21,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -45,13 +45,25 @@ #ifdef CONFIG_USB_OHCI -#include +#if defined(CONFIG_S3C2400) +# include +#elif defined(CONFIG_S3C2410) +# include +#elif defined(CONFIG_ARM920T) +# include +#elif defined(CONFIG_CPU_MONAHANS) +# include +#endif #include #include #include "usb_ohci.h" -#ifdef CONFIG_ARM920T +#undef S3C24X0_merge + +#if defined(CONFIG_ARM920T) || \ + defined(CONFIG_S3C2400) || \ + defined(CONFIG_S3C2410) # define OHCI_USE_NPS /* force NoPowerSwitching mode */ #endif @@ -98,6 +110,12 @@ int got_rhsc; /* device which was disconnected */ struct usb_device *devgone; +#ifdef S3C24X0_merge +/* flag guarding URB transation */ +int urb_finished = 0; +#endif + + /*-------------------------------------------------------------------------*/ /* AMD-756 (D2 rev) reports corrupt register contents in some cases. @@ -402,6 +420,17 @@ int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, err("sohci_submit_job: EPIPE"); return -1; } +#ifdef S3C24X0_merge + /* if we have an unfinished URB from previous transaction let's + * fail and scream as quickly as possible so as not to corrupt + * further communication */ + if (!urb_finished) { + err("sohci_submit_job: URB NOT FINISHED"); + return -1; + } + /* we're about to begin a new transaction here so mark the URB unfinished */ + urb_finished = 0; +#endif /* every endpoint has a ed, locate and fill it */ if (!(ed = ep_add_ed (dev, pipe))) { @@ -574,12 +603,14 @@ static int ep_unlink (ohci_t *ohci, ed_t *ed) /*-------------------------------------------------------------------------*/ -/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, - * but the USB stack is a little bit stateless so we do it at every transaction - * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK - * in all other cases the state is left unchanged - * the ed info fields are setted anyway even though most of them should not change */ - +/* add/reinit an endpoint; this should be done once at the + * usb_set_configuration command, but the USB stack is a little bit + * stateless so we do it at every transaction if the state of the ed + * is ED_NEW then a dummy td is added and the state is changed to + * ED_UNLINK in all other cases the state is left unchanged the ed + * info fields are setted anyway even though most of them should not + * change + */ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) { td_t *td; @@ -663,7 +694,9 @@ static void td_fill (ohci_t *ohci, unsigned int info, else td->hwBE = 0; td->hwNextTD = m32_swap (td_pt); +#ifndef S3C24X0_merge td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000); +#endif /* append to queue */ td->ed->hwTailP = td->hwNextTD; @@ -830,7 +863,18 @@ static int dl_done_list (ohci_t *ohci, td_t *td_list) dbg("ConditionCode %#x", cc); stat = cc_to_error[cc]; } - +#ifdef S3C24X0_merge + /* see if this done list makes for all TD's of current URB, + * and mark the URB finished if so */ + if (++(lurb_priv->td_cnt) == lurb_priv->length) { + if ((ed->state & (ED_OPER | ED_UNLINK))) + urb_finished = 1; + else + dbg("dl_done_list: strange.., ED state %x, ed->state\n"); + } else + dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt, + lurb_priv->length); +#endif if (ed->state != ED_NEW) { edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0; edTailP = m32_swap (ed->hwTailP); @@ -1172,7 +1216,7 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); } len = min_t(unsigned int, leni, - min_t(unsigned int, data_buf [0], wLength)); + min_t(unsigned int, data_buf [0], wLength)); OK (len); } @@ -1260,18 +1304,38 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, stat = USB_ST_CRC_ERR; break; } + +#ifdef S3C24X0_merge + /* NOTE: since we are not interrupt driven in U-Boot and always + * handle only one URB at a time, we cannot assume the + * transaction finished on the first successful return from + * hc_interrupt().. unless the flag for current URB is set, + * meaning that all TD's to/from device got actually + * transferred and processed. If the current URB is not + * finished we need to re-iterate this loop so as + * hc_interrupt() gets called again as there needs to be some + * more TD's to process still */ + if ((stat >= 0) && (stat != 0xff) && (urb_finished)) { +#else if (stat >= 0 && stat != 0xff) { +#endif /* 0xff is returned for an SF-interrupt */ break; } + if (--timeout) { wait_ms(1); } else { err("CTL:TIMEOUT "); +#ifdef S3C24X0_merge + dbg("submit_common_msg: TO status %x\n", stat); + urb_finished = 1; +#endif stat = USB_ST_CRC_ERR; break; } } +#ifndef S3C24X0_merge /* we got an Root Hub Status Change interrupt */ if (got_rhsc) { #ifdef DEBUG @@ -1293,6 +1357,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, devgone = dev; } } +#endif /* S3C24X0_merge */ dev->status = stat; dev->act_len = transfer_len; @@ -1462,24 +1527,40 @@ static int hc_start (ohci_t * ohci) /* an interrupt happens */ -static int -hc_interrupt (void) +static int hc_interrupt (void) { ohci_t *ohci = &gohci; struct ohci_regs *regs = ohci->regs; int ints; int stat = -1; +#ifdef S3C24X0_merge + + if ((ohci->hcca->done_head != 0) && + !(m32_swap (ohci->hcca->done_head) & 0x01)) { + ints = OHCI_INTR_WDH; + } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) { + ohci->disabled++; + err ("%s device removed!", ohci->slot_name); + return -1; + } else if ((ints &= readl (®s->intrenable)) == 0) { + dbg("hc_interrupt: returning..\n"); + return 0xff; + } +#else if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) { ints = OHCI_INTR_WDH; } else { ints = readl (®s->intrstatus); } - +#endif /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ if (ints & OHCI_INTR_RHSC) { got_rhsc = 1; +#ifdef S3C24X0_merge + stat = 0xff; +#endif } if (ints & OHCI_INTR_UE) { @@ -1552,13 +1633,13 @@ static char ohci_inited = 0; int usb_lowlevel_init(void) { -#if CFG_USB_OHCI_CPU_INIT +#ifdef CFG_USB_OHCI_CPU_INIT /* cpu dependant init */ if(usb_cpu_init()) return -1; #endif -#if CFG_USB_OHCI_BOARD_INIT +#ifdef CFG_USB_OHCI_BOARD_INIT /* board dependant init */ if(usb_board_init()) return -1; @@ -1598,15 +1679,14 @@ int usb_lowlevel_init(void) if (hc_reset (&gohci) < 0) { hc_release_ohci (&gohci); err ("can't reset usb-%s", gohci.slot_name); - /* Initialization failed disable clocks */ -#if CFG_USB_OHCI_BOARD_INIT +#ifdef CFG_USB_OHCI_BOARD_INIT /* board dependant cleanup */ - usb_board_stop(); + usb_board_init_fail(); #endif -#if CFG_USB_OHCI_CPU_INIT +#ifdef CFG_USB_OHCI_CPU_INIT /* cpu dependant cleanup */ - usb_cpu_stop(); + usb_cpu_init_fail(); #endif return -1; } @@ -1618,12 +1698,12 @@ int usb_lowlevel_init(void) err ("can't start usb-%s", gohci.slot_name); hc_release_ohci (&gohci); /* Initialization failed */ -#if CFG_USB_OHCI_BOARD_INIT +#ifdef CFG_USB_OHCI_BOARD_INIT /* board dependant cleanup */ usb_board_stop(); #endif -#if CFG_USB_OHCI_CPU_INIT +#ifdef CFG_USB_OHCI_CPU_INIT /* cpu dependant cleanup */ usb_cpu_stop(); #endif @@ -1634,6 +1714,9 @@ int usb_lowlevel_init(void) ohci_dump (&gohci, 1); #else wait_ms(1); +# ifdef S3C24X0_merge + urb_finished = 1; +# endif #endif ohci_inited = 1; return 0; @@ -1649,13 +1732,13 @@ int usb_lowlevel_stop(void) /* call hc_release_ohci() here ? */ hc_reset (&gohci); -#if CFG_USB_OHCI_BOARD_INIT +#ifdef CFG_USB_OHCI_BOARD_INIT /* board dependant cleanup */ if(usb_board_stop()) return -1; #endif -#if CFG_USB_OHCI_CPU_INIT +#ifdef CFG_USB_OHCI_CPU_INIT /* cpu dependant cleanup */ if(usb_cpu_stop()) return -1; diff --git a/drivers/usb_ohci.h b/drivers/usb_ohci.h index c37b5f6005c..a1b36ed83cc 100644 --- a/drivers/usb_ohci.h +++ b/drivers/usb_ohci.h @@ -11,11 +11,13 @@ #ifdef CFG_USB_BOARD_INIT extern int usb_board_init(void); extern int usb_board_stop(void); +extern int usb_cpu_init_fail(void); #endif #ifdef CFG_USB_CPU_INIT extern int usb_cpu_init(void); extern int usb_cpu_stop(void); +extern int usb_cpu_init_fail(void); #endif diff --git a/include/configs/trab.h b/include/configs/trab.h index 85ee756e05f..b6d4bcf1788 100644 --- a/include/configs/trab.h +++ b/include/configs/trab.h @@ -84,6 +84,11 @@ #define CONFIG_USB_STORAGE 1 #define CONFIG_DOS_PARTITION 1 +#undef CFG_USB_OHCI_BOARD_INIT +#define CFG_USB_OHCI_CPU_INIT 1 +#define CFG_USB_OHCI_REGS_BASE S3C24X0_USB_HOST_BASE +#define CFG_USB_OHCI_SLOT_NAME "s3c2400" + /* * Size of malloc() pool */ -- cgit v1.3.1 From 99d70e3a47affb9bae041a2caece7cd516e213b3 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 26 Jun 2006 11:06:00 +0200 Subject: More code cleanup --- cpu/arm920t/s3c24x0/usb.c | 6 +++--- drivers/usb_ohci.h | 6 +----- 2 files changed, 4 insertions(+), 8 deletions(-) (limited to 'cpu') diff --git a/cpu/arm920t/s3c24x0/usb.c b/cpu/arm920t/s3c24x0/usb.c index 8114034cc13..4bc7961a019 100644 --- a/cpu/arm920t/s3c24x0/usb.c +++ b/cpu/arm920t/s3c24x0/usb.c @@ -32,7 +32,7 @@ # include #endif -int usb_cpu_init() +int usb_cpu_init (void) { S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); @@ -53,7 +53,7 @@ int usb_cpu_init() return 0; } -int usb_cpu_stop() +int usb_cpu_stop (void) { S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); /* may not want to do this */ @@ -61,7 +61,7 @@ int usb_cpu_stop() return 0; } -int usb_cpu_init_fail() +int usb_cpu_init_fail (void) { S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); clk_power->CLKCON &= ~(1 << 4); diff --git a/drivers/usb_ohci.h b/drivers/usb_ohci.h index a1b36ed83cc..68dd4ecafee 100644 --- a/drivers/usb_ohci.h +++ b/drivers/usb_ohci.h @@ -7,18 +7,14 @@ * usb-ohci.h */ -/* functions for doing board specific setup/cleanup */ -#ifdef CFG_USB_BOARD_INIT +/* functions for doing board or CPU specific setup/cleanup */ extern int usb_board_init(void); extern int usb_board_stop(void); extern int usb_cpu_init_fail(void); -#endif -#ifdef CFG_USB_CPU_INIT extern int usb_cpu_init(void); extern int usb_cpu_stop(void); extern int usb_cpu_init_fail(void); -#endif static int cc_to_error[16] = { -- cgit v1.3.1 From 53e336e9ffc51035bdc4e5867631b3378761b4df Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Mon, 27 Nov 2006 11:43:09 +0100 Subject: Modified the mpc5xxx and the ppc4xx cpu to use the generic OHCI driver and adapted board configs TQM5200 and yosemite accordingly. This commit also makes the maximum number of root hub ports configurable (CFG_USB_OHCI_MAX_ROOT_PORTS). --- cpu/mpc5xxx/Makefile | 2 +- cpu/ppc4xx/Makefile | 3 ++- drivers/usb_ohci.c | 13 +++++++++++-- drivers/usb_ohci.h | 13 +++++++++++-- include/configs/TQM5200.h | 7 +++++++ include/configs/delta.h | 1 + include/configs/mp2usb.h | 1 + include/configs/trab.h | 1 + include/configs/yosemite.h | 6 ++++++ 9 files changed, 41 insertions(+), 6 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc5xxx/Makefile b/cpu/mpc5xxx/Makefile index a97b625171e..94f82b225a8 100644 --- a/cpu/mpc5xxx/Makefile +++ b/cpu/mpc5xxx/Makefile @@ -28,7 +28,7 @@ LIB = lib$(CPU).a START = start.o ASOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o OBJS = i2c.o traps.o cpu.o cpu_init.o fec.o ide.o interrupts.o \ - loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o + loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o usb.o all: .depend $(START) $(ASOBJS) $(LIB) diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index c5634570054..ca68599f7c7 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -31,7 +31,8 @@ COBJS = 405gp_pci.o 4xx_enet.o \ bedbug_405.o commproc.o \ cpu.o cpu_init.o i2c.o interrupts.o \ miiphy.o sdram.o serial.o \ - spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o + spd_sdram.o speed.o traps.o \ + usb_ohci.o usbdev.o usb.o OBJS = $(AOBJS) $(COBJS) diff --git a/drivers/usb_ohci.c b/drivers/usb_ohci.c index 9b3ca1232da..be1a615ebeb 100644 --- a/drivers/usb_ohci.c +++ b/drivers/usb_ohci.c @@ -45,6 +45,7 @@ #ifdef CONFIG_USB_OHCI +/* mk: are these really required? */ #if defined(CONFIG_S3C2400) # include #elif defined(CONFIG_S3C2410) @@ -53,6 +54,8 @@ # include #elif defined(CONFIG_CPU_MONAHANS) # include +#elif defined(CONFIG_MPC5200) +# include #endif #include @@ -557,8 +560,10 @@ static int ep_link (ohci_t *ohci, ed_t *edi) * the link from the ed still points to another operational ed or 0 * so the HC can eventually finish the processing of the unlinked ed */ -static int ep_unlink (ohci_t *ohci, ed_t *ed) +static int ep_unlink (ohci_t *ohci, ed_t *edi) { + volatile ed_t *ed = edi; + ed->hwINFO |= m32_swap (OHCI_ED_SKIP); switch (ed->type) { @@ -825,6 +830,9 @@ static td_t * dl_reverse_done_list (ohci_t *ohci) } else td_list->ed->hwHeadP &= m32_swap (0xfffffff2); } +#ifdef CONFIG_MPC5200 + td_list->hwNextTD = 0; +#endif } td_list->next_dl_td = td_rev; @@ -1448,7 +1456,8 @@ static int hc_reset (ohci_t *ohci) readl(&ohci->regs->control)); /* Reset USB (needed by some controllers) */ - writel (0, &ohci->regs->control); + ohci->hc_control = 0; + writel (ohci->hc_control, &ohci->regs->control); /* HC Reset requires max 10 us delay */ writel (OHCI_HCR, &ohci->regs->cmdstatus); diff --git a/drivers/usb_ohci.h b/drivers/usb_ohci.h index 68dd4ecafee..95fbc446549 100644 --- a/drivers/usb_ohci.h +++ b/drivers/usb_ohci.h @@ -113,7 +113,9 @@ struct td { __u32 hwNextTD; /* Next TD Pointer */ __u32 hwBE; /* Memory Buffer End Pointer */ +/* #ifndef CONFIG_MPC5200 /\* this seems wrong *\/ */ __u16 hwPSW[MAXPSW]; +/* #endif */ __u8 unused; __u8 index; struct ed *ed; @@ -137,8 +139,13 @@ typedef struct td td_t; #define NUM_INTS 32 /* part of the OHCI standard */ struct ohci_hcca { __u32 int_table[NUM_INTS]; /* Interrupt ED table */ +#if defined(CONFIG_MPC5200) + __u16 pad1; /* set to 0 on each frame_no change */ + __u16 frame_no; /* current frame number */ +#else __u16 frame_no; /* current frame number */ __u16 pad1; /* set to 0 on each frame_no change */ +#endif __u32 done_head; /* info returned for an interrupt */ u8 reserved_for_hc[116]; } __attribute((aligned(256))); @@ -147,7 +154,9 @@ struct ohci_hcca { /* * Maximum number of root hub ports. */ -#define MAX_ROOT_PORTS 3 /* maximum OHCI root hub ports */ +#ifndef CFG_USB_OHCI_MAX_ROOT_PORTS +# error "CFG_USB_OHCI_MAX_ROOT_PORTS undefined!" +#endif /* * This is the structure of the OHCI controller's memory mapped I/O @@ -181,7 +190,7 @@ struct ohci_regs { __u32 a; __u32 b; __u32 status; - __u32 portstatus[MAX_ROOT_PORTS]; + __u32 portstatus[CFG_USB_OHCI_MAX_ROOT_PORTS]; } roothub; } __attribute((aligned(32))); diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index be83b676720..832dcdde586 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -128,6 +128,13 @@ #define CONFIG_USB_OHCI #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE + +#undef CFG_USB_OHCI_BOARD_INIT +#define CFG_USB_OHCI_CPU_INIT +#define CFG_USB_OHCI_REGS_BASE MPC5XXX_USB +#define CFG_USB_OHCI_SLOT_NAME "mpc5200" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 + #else #define ADD_USB_CMD 0 #endif diff --git a/include/configs/delta.h b/include/configs/delta.h index fea821ab9af..0617ad864e7 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -111,6 +111,7 @@ #define CFG_USB_OHCI_CPU_INIT 1 #define CFG_USB_OHCI_REGS_BASE OHCI_REGS_BASE #define CFG_USB_OHCI_SLOT_NAME "delta" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 3 #define LITTLEENDIAN 1 /* used by usb_ohci.c */ diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h index edb20f8d88e..d182d49488a 100644 --- a/include/configs/mp2usb.h +++ b/include/configs/mp2usb.h @@ -111,6 +111,7 @@ #define CFG_USB_OHCI_CPU_INIT 1 #define CFG_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE #define CFG_USB_OHCI_SLOT_NAME "at91rm9200" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 #undef CONFIG_HARD_I2C diff --git a/include/configs/trab.h b/include/configs/trab.h index ae979475b93..33617cdcd49 100644 --- a/include/configs/trab.h +++ b/include/configs/trab.h @@ -88,6 +88,7 @@ #define CFG_USB_OHCI_CPU_INIT 1 #define CFG_USB_OHCI_REGS_BASE S3C24X0_USB_HOST_BASE #define CFG_USB_OHCI_SLOT_NAME "s3c2400" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 /* * Size of malloc() pool diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index a81cf34f11d..e6a02c6316c 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -216,6 +216,12 @@ #define CONFIG_USB_OHCI #define CONFIG_USB_STORAGE +#undef CFG_USB_OHCI_BOARD_INIT +#define CFG_USB_OHCI_CPU_INIT 1 +#define CFG_USB_OHCI_REGS_BASE (CFG_PERIPHERAL_BASE | 0x1000) +#define CFG_USB_OHCI_SLOT_NAME "ppc440" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 + /*Comment this out to enable USB 1.1 device*/ #define USB_2_0_DEVICE #endif /*CONFIG_440EP*/ -- cgit v1.3.1 From 7b59b3c7a8ce2e4b567abf99c1cd667bf35b9418 Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Mon, 27 Nov 2006 11:44:58 +0100 Subject: Introduced the configuration option CONFIG_USB_OHCI_NEW in order to be able to choose between the old and the generic OHCI drivers. --- board/trab/auto_update.c | 2 +- cpu/arm920t/at91rm9200/usb.c | 2 +- cpu/arm920t/s3c24x0/usb.c | 2 +- cpu/pxa/usb.c | 2 +- drivers/usb_ohci.c | 4 ++-- include/configs/TQM5200.h | 2 +- include/configs/delta.h | 2 +- include/configs/mp2usb.h | 2 +- include/configs/trab.h | 2 +- include/configs/yosemite.h | 2 +- include/usb.h | 2 +- 11 files changed, 12 insertions(+), 12 deletions(-) (limited to 'cpu') diff --git a/board/trab/auto_update.c b/board/trab/auto_update.c index d2c8d44a79f..7684499c246 100644 --- a/board/trab/auto_update.c +++ b/board/trab/auto_update.c @@ -34,7 +34,7 @@ #ifdef CONFIG_AUTO_UPDATE -#ifndef CONFIG_USB_OHCI +#ifndef CONFIG_USB_OHCI_NEW #error "must define CONFIG_USB_OHCI" #endif diff --git a/cpu/arm920t/at91rm9200/usb.c b/cpu/arm920t/at91rm9200/usb.c index 98e3cdd58a7..366262e4ccd 100644 --- a/cpu/arm920t/at91rm9200/usb.c +++ b/cpu/arm920t/at91rm9200/usb.c @@ -23,7 +23,7 @@ #include -#if defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) +#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) # ifdef CONFIG_AT91RM9200 #include diff --git a/cpu/arm920t/s3c24x0/usb.c b/cpu/arm920t/s3c24x0/usb.c index 4bc7961a019..ef5d5bf71b1 100644 --- a/cpu/arm920t/s3c24x0/usb.c +++ b/cpu/arm920t/s3c24x0/usb.c @@ -23,7 +23,7 @@ #include -#if defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) +#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) # if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) #if defined(CONFIG_S3C2400) diff --git a/cpu/pxa/usb.c b/cpu/pxa/usb.c index bff5bfb6ae9..5d273cb3518 100644 --- a/cpu/pxa/usb.c +++ b/cpu/pxa/usb.c @@ -23,7 +23,7 @@ #include -#if defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) +#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) # ifdef CONFIG_CPU_MONAHANS #include diff --git a/drivers/usb_ohci.c b/drivers/usb_ohci.c index be1a615ebeb..482633fc67e 100644 --- a/drivers/usb_ohci.c +++ b/drivers/usb_ohci.c @@ -43,7 +43,7 @@ #include /* #include no PCI on the S3C24X0 */ -#ifdef CONFIG_USB_OHCI +#ifdef CONFIG_USB_OHCI_NEW /* mk: are these really required? */ #if defined(CONFIG_S3C2400) @@ -1756,4 +1756,4 @@ int usb_lowlevel_stop(void) return 0; } -#endif /* CONFIG_USB_OHCI */ +#endif /* CONFIG_USB_OHCI_NEW */ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 832dcdde586..6c8712b68d0 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -125,7 +125,7 @@ /* USB */ #ifdef CONFIG_STK52XX -#define CONFIG_USB_OHCI +#define CONFIG_USB_OHCI_NEW #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE diff --git a/include/configs/delta.h b/include/configs/delta.h index 0617ad864e7..4038f219602 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -103,7 +103,7 @@ #endif /* USB */ -#define CONFIG_USB_OHCI 1 +#define CONFIG_USB_OHCI_NEW 1 #define CONFIG_USB_STORAGE 1 #define CONFIG_DOS_PARTITION 1 diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h index d182d49488a..2cf78a3b150 100644 --- a/include/configs/mp2usb.h +++ b/include/configs/mp2usb.h @@ -101,7 +101,7 @@ #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ -#define CONFIG_USB_OHCI 1 +#define CONFIG_USB_OHCI_NEW 1 #define CONFIG_USB_KEYBOARD 1 #define CONFIG_USB_STORAGE 1 #define CONFIG_DOS_PARTITION 1 diff --git a/include/configs/trab.h b/include/configs/trab.h index 33617cdcd49..acf86d08ad2 100644 --- a/include/configs/trab.h +++ b/include/configs/trab.h @@ -80,7 +80,7 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* USB stuff */ -#define CONFIG_USB_OHCI 1 +#define CONFIG_USB_OHCI_NEW 1 #define CONFIG_USB_STORAGE 1 #define CONFIG_DOS_PARTITION 1 diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index e6a02c6316c..7f434e93f8d 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -213,7 +213,7 @@ #ifdef CONFIG_440EP /* USB */ -#define CONFIG_USB_OHCI +#define CONFIG_USB_OHCI_NEW #define CONFIG_USB_STORAGE #undef CFG_USB_OHCI_BOARD_INIT diff --git a/include/usb.h b/include/usb.h index bf715540417..fafac8934ad 100644 --- a/include/usb.h +++ b/include/usb.h @@ -169,7 +169,7 @@ struct usb_device { * this is how the lowlevel part communicate with the outer world */ -#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined (CONFIG_USB_SL811HS) +#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined (CONFIG_USB_SL811HS) || defined(CONFIG_USB_OHCI_NEW) int usb_lowlevel_init(void); int usb_lowlevel_stop(void); int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len); -- cgit v1.3.1 From ae00bb4b2944dc64a485ed72a19754b11af7c223 Mon Sep 17 00:00:00 2001 From: Rodolfo Giometti Date: Mon, 26 Mar 2007 12:03:36 +0200 Subject: PXA: pxa27x USB OHCI support Signed-off-by: Rodolfo Giometti --- README | 1 + cpu/pxa/usb.c | 15 +++++++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/README b/README index 13ff3ffcfc6..73a3e80161e 100644 --- a/README +++ b/README @@ -248,6 +248,7 @@ The following options need to be configured: CONFIG_SA1110 CONFIG_ARM7 CONFIG_PXA250 + CONFIG_PXA27X CONFIG_CPU_MONAHANS MicroBlaze based CPUs: diff --git a/cpu/pxa/usb.c b/cpu/pxa/usb.c index 5d273cb3518..4ef3ac76796 100644 --- a/cpu/pxa/usb.c +++ b/cpu/pxa/usb.c @@ -24,15 +24,21 @@ #include #if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) -# ifdef CONFIG_CPU_MONAHANS +# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) #include int usb_cpu_init() { +#if defined(CONFIG_CPU_MONAHANS) /* Enable USB host clock. */ CKENA |= (CKENA_2_USBHOST | CKENA_20_UDC); udelay(100); +#endif +#if defined(CONFIG_PXA27X) + /* Enable USB host clock. */ + CKEN |= CKEN10_USBHOST; +#endif /* Configure Port 2 for Host (USB Client Registers) */ UP2OCR = 0x3000c; @@ -55,7 +61,12 @@ int usb_cpu_init() UHCHR |= UHCHR_PSPL; /* USBHPWR is active low */ #endif +#if defined(CONFIG_CPU_MONAHANS) UHCHR &= ~UHCHR_SSEP0; +#endif +#if defined(CONFIG_PXA27X) + UHCHR &= ~UHCHR_SSEP2; +#endif UHCHR &= ~UHCHR_SSEP1; UHCHR &= ~UHCHR_SSE; @@ -74,5 +85,5 @@ int usb_cpu_init_fail() return 0; } -# endif /* CONFIG_CPU_MONAHANS */ +# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */ #endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ -- cgit v1.3.1 From edf5851be6c17c031d4f71dd5b0a12040b7c50c8 Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Tue, 3 Apr 2007 14:27:08 +0200 Subject: USB: cleanup monahans usb support. Remove dead code. Signed-off-by: Markus Klotzbuecher --- cpu/pxa/usb.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) (limited to 'cpu') diff --git a/cpu/pxa/usb.c b/cpu/pxa/usb.c index 4ef3ac76796..65f457fe59d 100644 --- a/cpu/pxa/usb.c +++ b/cpu/pxa/usb.c @@ -40,12 +40,9 @@ int usb_cpu_init() CKEN |= CKEN10_USBHOST; #endif +#if defined(CONFIG_CPU_MONAHANS) /* Configure Port 2 for Host (USB Client Registers) */ UP2OCR = 0x3000c; - -#if 0 - GPIO2_2 = 0x801; /* USBHPEN - Alt. Fkt. 1 */ - GPIO3_2 = 0x801; /* USBHPWR - Alt. Fkt. 1 */ #endif UHCHR |= UHCHR_FHR; @@ -56,11 +53,6 @@ int usb_cpu_init() while (UHCHR & UHCHR_FSBIR) udelay(1); -#if 0 - UHCHR |= UHCHR_PCPL; /* USBHPEN is active low */ - UHCHR |= UHCHR_PSPL; /* USBHPWR is active low */ -#endif - #if defined(CONFIG_CPU_MONAHANS) UHCHR &= ~UHCHR_SSEP0; #endif @@ -75,8 +67,6 @@ int usb_cpu_init() int usb_cpu_stop() { - /* may not want to do this */ - /* CKENA &= ~(CKENA_2_USBHOST | CKENA_20_UDC); */ return 0; } -- cgit v1.3.1 From 72657570b61635c74fa0c3f0e9e7d0671a9d08df Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Wed, 6 Jun 2007 11:49:43 +0200 Subject: USB: ohci fixes and cleanup for mpc5xxx and IceCube board config --- cpu/mpc5xxx/usb.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++ include/configs/IceCube.h | 9 ++------ 2 files changed, 56 insertions(+), 7 deletions(-) create mode 100644 cpu/mpc5xxx/usb.c (limited to 'cpu') diff --git a/cpu/mpc5xxx/usb.c b/cpu/mpc5xxx/usb.c new file mode 100644 index 00000000000..ce709fc652c --- /dev/null +++ b/cpu/mpc5xxx/usb.c @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2007 + * Markus Klotzbuecher, DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) + +#include + +int usb_cpu_init() +{ + /* Set the USB Clock */ + *(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK; + + /* remove all USB bits first before ORing in ours */ + *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00807000; + + /* Activate USB port */ + *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= CONFIG_USB_CONFIG; + + return 0; +} + +int usb_cpu_stop() +{ + return 0; +} + +int usb_cpu_init_fail() +{ + return 0; +} + +#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 4132f4ac7ea..551a6099825 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -93,21 +93,16 @@ #define CONFIG_ISO_PARTITION /* USB */ -#if 1 #define CONFIG_USB_OHCI_NEW #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE - +#define CFG_OHCI_BE_CONTROLLER #undef CFG_USB_OHCI_BOARD_INIT -#define CFG_USB_OHCI_CPU_INIT +#define CFG_USB_OHCI_CPU_INIT 1 #define CFG_USB_OHCI_REGS_BASE MPC5XXX_USB #define CFG_USB_OHCI_SLOT_NAME "mpc5200" #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 -#else -#define ADD_USB_CMD 0 -#endif - #define CONFIG_TIMESTAMP /* Print image info with timestamp */ /* -- cgit v1.3.1 From dace45acd1c1357daa9322099d07c9a9e08b0024 Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Wed, 6 Jun 2007 11:49:43 +0200 Subject: USB: ohci fixes and cleanup for ppc4xx and yosemite board. --- cpu/ppc4xx/Makefile | 2 +- cpu/ppc4xx/usb.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++ include/configs/yosemite.h | 1 + 3 files changed, 52 insertions(+), 1 deletion(-) create mode 100644 cpu/ppc4xx/usb.c (limited to 'cpu') diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 66fd02ccd8d..af9da5b95fd 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -32,7 +32,7 @@ COBJS = 405gp_pci.o 440spe_pcie.o 4xx_enet.o \ cpu.o cpu_init.o gpio.o i2c.o interrupts.o \ miiphy.o ndfc.o sdram.o serial.o \ 40x_spd_sdram.o 44x_spd_ddr.o 44x_spd_ddr2.o speed.o \ - tlb.o traps.o usb_ohci.o usbdev.o usb.o \ + tlb.o traps.o usb_ohci.o usb.o usbdev.o \ 440spe_pcie.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/ppc4xx/usb.c b/cpu/ppc4xx/usb.c new file mode 100644 index 00000000000..2837b37c58e --- /dev/null +++ b/cpu/ppc4xx/usb.c @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2007 + * Markus Klotzbuecher, DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) + +#include "usbdev.h" + +int usb_cpu_init() +{ + +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) + usb_dev_init(); +#endif + + return 0; +} + +int usb_cpu_stop() +{ + return 0; +} + +int usb_cpu_init_fail() +{ + return 0; +} + +#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 0a41dff5fbd..1d127581ee6 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -234,6 +234,7 @@ /* USB */ #define CONFIG_USB_OHCI_NEW #define CONFIG_USB_STORAGE +#define CFG_OHCI_BE_CONTROLLER #undef CFG_USB_OHCI_BOARD_INIT #define CFG_USB_OHCI_CPU_INIT 1 -- cgit v1.3.1 From f48070fe5fe440dfb5ee5268c920de70e48ea327 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 11 Jun 2007 19:03:08 -0500 Subject: cpu/mpc*/ : Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). This is a compatibility step that allows both the older form and the new form to co-exist for a while until the older can be removed entirely. All transformations are of the form: Before: #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) After: #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) Signed-off-by: Jon Loeliger --- cpu/mpc5xx/interrupts.c | 2 +- cpu/mpc5xx/traps.c | 16 ++++++++-------- cpu/mpc5xxx/cpu_init.c | 2 +- cpu/mpc5xxx/fec.c | 6 +++--- cpu/mpc5xxx/interrupts.c | 2 +- cpu/mpc5xxx/traps.c | 16 ++++++++-------- cpu/mpc8220/cpu_init.c | 2 +- cpu/mpc8220/fec.c | 6 +++--- cpu/mpc8220/traps.c | 16 ++++++++-------- cpu/mpc824x/traps.c | 4 ++-- cpu/mpc8260/bedbug_603e.c | 3 ++- cpu/mpc8260/ether_fcc.c | 6 +++--- cpu/mpc8260/ether_scc.c | 2 +- cpu/mpc8260/interrupts.c | 2 +- cpu/mpc8260/kgdb.S | 2 +- cpu/mpc8260/traps.c | 16 ++++++++-------- cpu/mpc83xx/interrupts.c | 2 +- cpu/mpc83xx/traps.c | 14 +++++++------- cpu/mpc85xx/ether_fcc.c | 6 +++--- cpu/mpc85xx/interrupts.c | 2 +- cpu/mpc85xx/traps.c | 14 +++++++------- cpu/mpc86xx/traps.c | 12 ++++++------ cpu/mpc8xx/bedbug_860.c | 2 +- cpu/mpc8xx/fec.c | 14 +++++++------- cpu/mpc8xx/kgdb.S | 2 +- cpu/mpc8xx/scc.c | 2 +- cpu/mpc8xx/serial.c | 2 +- cpu/mpc8xx/traps.c | 16 ++++++++-------- 28 files changed, 96 insertions(+), 95 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc5xx/interrupts.c b/cpu/mpc5xx/interrupts.c index 7f6e1363e74..70803cf36d7 100644 --- a/cpu/mpc5xx/interrupts.c +++ b/cpu/mpc5xx/interrupts.c @@ -178,7 +178,7 @@ void timer_interrupt_cpu (struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) || defined(CONFIG_CMD_IRQ) /******************************************************************************* * * irqinfo - print information about IRQs diff --git a/cpu/mpc5xx/traps.c b/cpu/mpc5xx/traps.c index 14fd59e4fad..26a253f823e 100644 --- a/cpu/mpc5xx/traps.c +++ b/cpu/mpc5xx/traps.c @@ -36,11 +36,11 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -131,7 +131,7 @@ void MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -165,7 +165,7 @@ void MachineCheckException(struct pt_regs *regs) */ void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -179,7 +179,7 @@ void AlignmentException(struct pt_regs *regs) */ void ProgramCheckException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -193,7 +193,7 @@ void ProgramCheckException(struct pt_regs *regs) */ void SoftEmuException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -208,7 +208,7 @@ void SoftEmuException(struct pt_regs *regs) */ void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -224,7 +224,7 @@ void DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c index d7440308a45..7ec3594dc0c 100644 --- a/cpu/mpc5xxx/cpu_init.c +++ b/cpu/mpc5xxx/cpu_init.c @@ -198,7 +198,7 @@ int cpu_init_r (void) /* route critical ints to normal ints */ *(vu_long *)MPC5XXX_ICTL_EXT |= 0x00000001; -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC) +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(CONFIG_MPC5xxx_FEC) /* load FEC microcode */ loadtask(0, 2); #endif diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c index 813636655b2..5f9d6adca3d 100644 --- a/cpu/mpc5xxx/fec.c +++ b/cpu/mpc5xxx/fec.c @@ -18,10 +18,10 @@ DECLARE_GLOBAL_DATA_PTR; /* #define DEBUG 0x28 */ -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(CONFIG_NET_MULTI) && \ defined(CONFIG_MPC5xxx_FEC) -#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) +#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) #error "CONFIG_MII has to be defined!" #endif @@ -917,7 +917,7 @@ int mpc5xxx_fec_initialize(bd_t * bis) sprintf(dev->name, "FEC ETHERNET"); eth_register(dev); -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) miiphy_register (dev->name, fec5xxx_miiphy_read, fec5xxx_miiphy_write); #endif diff --git a/cpu/mpc5xxx/interrupts.c b/cpu/mpc5xxx/interrupts.c index beeb222636e..4b414eae311 100644 --- a/cpu/mpc5xxx/interrupts.c +++ b/cpu/mpc5xxx/interrupts.c @@ -310,7 +310,7 @@ void irq_free_handler(int irq) /****************************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) || defined(CONFIG_CMD_IRQ) void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) { int irq, re_enable; diff --git a/cpu/mpc5xxx/traps.c b/cpu/mpc5xxx/traps.c index 2ee782b9c86..8810a764ac4 100644 --- a/cpu/mpc5xxx/traps.c +++ b/cpu/mpc5xxx/traps.c @@ -37,7 +37,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -123,7 +123,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -158,7 +158,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -170,7 +170,7 @@ AlignmentException(struct pt_regs *regs) void ProgramCheckException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -182,7 +182,7 @@ ProgramCheckException(struct pt_regs *regs) void SoftEmuException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -195,7 +195,7 @@ SoftEmuException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -204,7 +204,7 @@ UnknownException(struct pt_regs *regs) _exception(0, regs); } -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -214,7 +214,7 @@ DebugException(struct pt_regs *regs) printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc8220/cpu_init.c b/cpu/mpc8220/cpu_init.c index 3cf5f66a130..db47a4b5f29 100644 --- a/cpu/mpc8220/cpu_init.c +++ b/cpu/mpc8220/cpu_init.c @@ -128,7 +128,7 @@ int cpu_init_r (void) /* route critical ints to normal ints */ *(vu_long *) 0xf0000710 |= 0x00000001; -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC8220_FEC) +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(CONFIG_MPC8220_FEC) /* load FEC microcode */ loadtask (0, 2); #endif diff --git a/cpu/mpc8220/fec.c b/cpu/mpc8220/fec.c index 1201e794df4..144d623bfc3 100644 --- a/cpu/mpc8220/fec.c +++ b/cpu/mpc8220/fec.c @@ -15,10 +15,10 @@ #include "fec.h" #undef DEBUG -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(CONFIG_NET_MULTI) && \ defined(CONFIG_MPC8220_FEC) -#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) +#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) #error "CONFIG_MII has to be defined!" #endif @@ -847,7 +847,7 @@ int mpc8220_fec_initialize (bd_t * bis) sprintf (dev->name, "FEC ETHERNET"); eth_register (dev); -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) miiphy_register (dev->name, fec8220_miiphy_read, fec8220_miiphy_write); #endif diff --git a/cpu/mpc8220/traps.c b/cpu/mpc8220/traps.c index cdee2be78b5..e921cdde3a8 100644 --- a/cpu/mpc8220/traps.c +++ b/cpu/mpc8220/traps.c @@ -37,7 +37,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler) (struct pt_regs *) = 0; #endif @@ -118,7 +118,7 @@ void MachineCheckException (struct pt_regs *regs) regs->nip = fixup; return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; @@ -152,7 +152,7 @@ void MachineCheckException (struct pt_regs *regs) void AlignmentException (struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; @@ -164,7 +164,7 @@ void AlignmentException (struct pt_regs *regs) void ProgramCheckException (struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; @@ -176,7 +176,7 @@ void ProgramCheckException (struct pt_regs *regs) void SoftEmuException (struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; @@ -189,7 +189,7 @@ void SoftEmuException (struct pt_regs *regs) void UnknownException (struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; @@ -199,7 +199,7 @@ void UnknownException (struct pt_regs *regs) _exception (0, regs); } -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) extern void do_bedbug_breakpoint (struct pt_regs *); #endif @@ -208,7 +208,7 @@ void DebugException (struct pt_regs *regs) printf ("Debugger trap at @ %lx\n", regs->nip); show_regs (regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) do_bedbug_breakpoint (regs); #endif } diff --git a/cpu/mpc824x/traps.c b/cpu/mpc824x/traps.c index 071d003f8c3..e93cffbf517 100644 --- a/cpu/mpc824x/traps.c +++ b/cpu/mpc824x/traps.c @@ -175,7 +175,7 @@ UnknownException(struct pt_regs *regs) _exception(0, regs); } -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -185,7 +185,7 @@ DebugException(struct pt_regs *regs) printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc8260/bedbug_603e.c b/cpu/mpc8260/bedbug_603e.c index be09cfb5c61..7ca193d46c4 100644 --- a/cpu/mpc8260/bedbug_603e.c +++ b/cpu/mpc8260/bedbug_603e.c @@ -10,7 +10,8 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && (defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260)) +#if ((CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG)) \ + && (defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260)) #define MAX_BREAK_POINTS 1 diff --git a/cpu/mpc8260/ether_fcc.c b/cpu/mpc8260/ether_fcc.c index 584c40f17a1..51d0de2c00e 100644 --- a/cpu/mpc8260/ether_fcc.c +++ b/cpu/mpc8260/ether_fcc.c @@ -47,13 +47,13 @@ #include #include -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) #include #endif DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \ +#if defined(CONFIG_ETHER_ON_FCC) && ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && \ defined(CONFIG_NET_MULTI) static struct ether_fcc_info_s @@ -393,7 +393,7 @@ int fec_initialize(bd_t *bis) eth_register(dev); -#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \ +#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) \ && defined(CONFIG_BITBANGMII) miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write); diff --git a/cpu/mpc8260/ether_scc.c b/cpu/mpc8260/ether_scc.c index a733b45c011..ec682ec25ec 100644 --- a/cpu/mpc8260/ether_scc.c +++ b/cpu/mpc8260/ether_scc.c @@ -36,7 +36,7 @@ #include #include -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_COMMANDS & CFG_CMD_NET) +#if defined(CONFIG_ETHER_ON_SCC) && ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) #if (CONFIG_ETHER_INDEX == 1) # define PROFF_ENET PROFF_SCC1 diff --git a/cpu/mpc8260/interrupts.c b/cpu/mpc8260/interrupts.c index 56e9a721373..6e5ab4c4e64 100644 --- a/cpu/mpc8260/interrupts.c +++ b/cpu/mpc8260/interrupts.c @@ -246,7 +246,7 @@ void timer_interrupt_cpu (struct pt_regs *regs) /****************************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) || defined(CONFIG_CMD_IRQ) /* ripped this out of ppc4xx/interrupts.c */ diff --git a/cpu/mpc8260/kgdb.S b/cpu/mpc8260/kgdb.S index 2a250249b89..fc1ebe2a39b 100644 --- a/cpu/mpc8260/kgdb.S +++ b/cpu/mpc8260/kgdb.S @@ -34,7 +34,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) /* * cache flushing routines for kgdb diff --git a/cpu/mpc8260/traps.c b/cpu/mpc8260/traps.c index 0c39e434ed3..07be0fac6de 100644 --- a/cpu/mpc8260/traps.c +++ b/cpu/mpc8260/traps.c @@ -37,7 +37,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -150,7 +150,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -186,7 +186,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -198,7 +198,7 @@ AlignmentException(struct pt_regs *regs) void ProgramCheckException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -210,7 +210,7 @@ ProgramCheckException(struct pt_regs *regs) void SoftEmuException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -223,7 +223,7 @@ SoftEmuException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -232,7 +232,7 @@ UnknownException(struct pt_regs *regs) _exception(0, regs); } -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -242,7 +242,7 @@ DebugException(struct pt_regs *regs) printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc83xx/interrupts.c b/cpu/mpc83xx/interrupts.c index bb1fe1af3f3..26040663f9a 100644 --- a/cpu/mpc83xx/interrupts.c +++ b/cpu/mpc83xx/interrupts.c @@ -81,7 +81,7 @@ void timer_interrupt_cpu (struct pt_regs *regs) } -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) || defined(CONFIG_CMD_IRQ) /* ripped this out of ppc4xx/interrupts.c */ diff --git a/cpu/mpc83xx/traps.c b/cpu/mpc83xx/traps.c index 152fa735612..83dcec36e7c 100644 --- a/cpu/mpc83xx/traps.c +++ b/cpu/mpc83xx/traps.c @@ -140,7 +140,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -176,7 +176,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -188,7 +188,7 @@ AlignmentException(struct pt_regs *regs) void ProgramCheckException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -200,7 +200,7 @@ ProgramCheckException(struct pt_regs *regs) void SoftEmuException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -213,7 +213,7 @@ SoftEmuException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -222,7 +222,7 @@ UnknownException(struct pt_regs *regs) _exception(0, regs); } -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -231,7 +231,7 @@ DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c index d15d2424929..a6b2ae3fbeb 100644 --- a/cpu/mpc85xx/ether_fcc.c +++ b/cpu/mpc85xx/ether_fcc.c @@ -48,13 +48,13 @@ #include #include -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) #include #endif #if defined(CONFIG_CPM2) -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \ +#if defined(CONFIG_ETHER_ON_FCC) && ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && \ defined(CONFIG_NET_MULTI) static struct ether_fcc_info_s @@ -458,7 +458,7 @@ int fec_initialize(bd_t *bis) eth_register(dev); -#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \ +#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) || \ && defined(CONFIG_BITBANGMII) miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write); diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c index 832781bab8f..ed15c466674 100644 --- a/cpu/mpc85xx/interrupts.c +++ b/cpu/mpc85xx/interrupts.c @@ -144,7 +144,7 @@ void set_timer (ulong t) timestamp = t; } -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) || defined(CONFIG_CMD_IRQ) /******************************************************************************* * diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c index 904f0523396..fc0c0aa5a7c 100644 --- a/cpu/mpc85xx/traps.c +++ b/cpu/mpc85xx/traps.c @@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -74,7 +74,7 @@ static __inline__ unsigned long get_esr(void) #define ESR_DIZ 0x00400000 #define ESR_U0F 0x00008000 -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -159,7 +159,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -192,7 +192,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -207,7 +207,7 @@ ProgramCheckException(struct pt_regs *regs) { long esr_val; -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -244,7 +244,7 @@ PITException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -259,7 +259,7 @@ DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c index 8ea14e575f2..06334b719b9 100644 --- a/cpu/mpc86xx/traps.c +++ b/cpu/mpc86xx/traps.c @@ -34,7 +34,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -122,7 +122,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif @@ -155,7 +155,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif @@ -170,7 +170,7 @@ ProgramCheckException(struct pt_regs *regs) unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL; int i, j; -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif @@ -193,7 +193,7 @@ ProgramCheckException(struct pt_regs *regs) void SoftEmuException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif @@ -205,7 +205,7 @@ SoftEmuException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif diff --git a/cpu/mpc8xx/bedbug_860.c b/cpu/mpc8xx/bedbug_860.c index e91a1006f7b..4516f2f48ea 100644 --- a/cpu/mpc8xx/bedbug_860.c +++ b/cpu/mpc8xx/bedbug_860.c @@ -10,7 +10,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && defined(CONFIG_8xx) +#if ((CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG)) && defined(CONFIG_8xx) #define MAX_BREAK_POINTS 2 diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c index 6d2755e8304..520953cc82b 100644 --- a/cpu/mpc8xx/fec.c +++ b/cpu/mpc8xx/fec.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; #undef ET_DEBUG -#if (CONFIG_COMMANDS & CFG_CMD_NET) && \ +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && \ (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)) /* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */ @@ -49,7 +49,7 @@ DECLARE_GLOBAL_DATA_PTR; #if defined(WANT_MII) #include -#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) +#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) #error "CONFIG_MII has to be defined!" #endif @@ -182,7 +182,7 @@ int fec_initialize(bd_t *bis) eth_register(dev); -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) miiphy_register(dev->name, fec8xx_miiphy_read, fec8xx_miiphy_write); #endif @@ -268,7 +268,7 @@ static int fec_recv (struct eth_device *dev) length -= 4; -#if (CONFIG_COMMANDS & CFG_CMD_CDP) +#if (CONFIG_COMMANDS & CFG_CMD_CDP) || defined(CONFIG_CMD_CDP) if ((rx[0] & 1) != 0 && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0 && memcmp ((uchar *) rx, NetCDPAddr, 6) != 0) @@ -608,7 +608,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd) fecp->fec_addr_high = (ea[4] << 8) | (ea[5]); #undef ea -#if (CONFIG_COMMANDS & CFG_CMD_CDP) +#if (CONFIG_COMMANDS & CFG_CMD_CDP) || defined(CONFIG_CMD_CDP) /* * Turn on multicast address hash table */ @@ -787,7 +787,7 @@ static void fec_halt(struct eth_device* dev) efis->initialized = 0; } -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) /* Make MII read/write commands for the FEC. */ @@ -926,7 +926,7 @@ static int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) && !defined(CONFIG_BITBANGMII) +#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII) /**************************************************************************** * mii_init -- Initialize the MII for MII command without ethernet diff --git a/cpu/mpc8xx/kgdb.S b/cpu/mpc8xx/kgdb.S index 11c3c69339e..c12074494bf 100644 --- a/cpu/mpc8xx/kgdb.S +++ b/cpu/mpc8xx/kgdb.S @@ -34,7 +34,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) /* * cache flushing routines for kgdb diff --git a/cpu/mpc8xx/scc.c b/cpu/mpc8xx/scc.c index 6b9110f1301..0aa597666b9 100644 --- a/cpu/mpc8xx/scc.c +++ b/cpu/mpc8xx/scc.c @@ -38,7 +38,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(SCC_ENET) +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(SCC_ENET) /* Ethernet Transmit and Receive Buffers */ #define DBUF_LENGTH 1520 diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c index ffc898c5876..62af1295336 100644 --- a/cpu/mpc8xx/serial.c +++ b/cpu/mpc8xx/serial.c @@ -666,7 +666,7 @@ void enable_putc(void) } #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) void kgdb_serial_init(void) diff --git a/cpu/mpc8xx/traps.c b/cpu/mpc8xx/traps.c index 67b75cce2f7..ce955d78b68 100644 --- a/cpu/mpc8xx/traps.c +++ b/cpu/mpc8xx/traps.c @@ -36,11 +36,11 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -126,7 +126,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -159,7 +159,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -171,7 +171,7 @@ AlignmentException(struct pt_regs *regs) void ProgramCheckException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -183,7 +183,7 @@ ProgramCheckException(struct pt_regs *regs) void SoftEmuException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -196,7 +196,7 @@ SoftEmuException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -210,7 +210,7 @@ DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } -- cgit v1.3.1 From 737184114ec9c9e0ab94d6713536126073bd2472 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 11 Jun 2007 19:03:15 -0500 Subject: cpu/ non-mpc*: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). This is a compatibility step that allows both the older form and the new form to co-exist for a while until the older can be removed entirely. All transformations are of the form: Before: #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) After: #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) Signed-off-by: Jon Loeliger --- cpu/74xx_7xx/kgdb.S | 2 +- cpu/74xx_7xx/traps.c | 12 ++++++------ cpu/arm920t/at91rm9200/bcm5221.c | 2 +- cpu/arm920t/at91rm9200/dm9161.c | 2 +- cpu/arm920t/at91rm9200/ether.c | 6 +++--- cpu/arm920t/at91rm9200/lxt972.c | 2 +- cpu/i386/serial.c | 2 +- cpu/ixp/cpu.c | 2 +- cpu/ixp/npe/npe.c | 2 +- cpu/mcf52x2/fec.c | 10 +++++----- cpu/microblaze/cache.c | 2 +- cpu/microblaze/interrupts.c | 2 +- cpu/mips/au1x00_eth.c | 6 +++--- cpu/nios/interrupts.c | 2 +- cpu/nios2/interrupts.c | 2 +- cpu/ppc4xx/4xx_enet.c | 8 ++++---- cpu/ppc4xx/bedbug_405.c | 2 +- cpu/ppc4xx/interrupts.c | 2 +- cpu/ppc4xx/kgdb.S | 2 +- cpu/ppc4xx/ndfc.c | 2 +- cpu/ppc4xx/serial.c | 2 +- cpu/ppc4xx/traps.c | 14 +++++++------- cpu/ppc4xx/usbdev.c | 2 +- 23 files changed, 45 insertions(+), 45 deletions(-) (limited to 'cpu') diff --git a/cpu/74xx_7xx/kgdb.S b/cpu/74xx_7xx/kgdb.S index e838513c1df..5d2ce85e9c0 100644 --- a/cpu/74xx_7xx/kgdb.S +++ b/cpu/74xx_7xx/kgdb.S @@ -31,7 +31,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) /* * cache flushing routines for kgdb diff --git a/cpu/74xx_7xx/traps.c b/cpu/74xx_7xx/traps.c index 50c5eeb4835..e7658bbf270 100644 --- a/cpu/74xx_7xx/traps.c +++ b/cpu/74xx_7xx/traps.c @@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -133,7 +133,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -166,7 +166,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -181,7 +181,7 @@ ProgramCheckException(struct pt_regs *regs) unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL; int i, j; -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -204,7 +204,7 @@ ProgramCheckException(struct pt_regs *regs) void SoftEmuException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -217,7 +217,7 @@ SoftEmuException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif diff --git a/cpu/arm920t/at91rm9200/bcm5221.c b/cpu/arm920t/at91rm9200/bcm5221.c index 6db143562c8..b0d87954dc5 100644 --- a/cpu/arm920t/at91rm9200/bcm5221.c +++ b/cpu/arm920t/at91rm9200/bcm5221.c @@ -32,7 +32,7 @@ #ifdef CONFIG_DRIVER_ETHER -#if (CONFIG_COMMANDS & CFG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET) /* * Name: diff --git a/cpu/arm920t/at91rm9200/dm9161.c b/cpu/arm920t/at91rm9200/dm9161.c index 4b13c237c70..eaa6ccb4535 100644 --- a/cpu/arm920t/at91rm9200/dm9161.c +++ b/cpu/arm920t/at91rm9200/dm9161.c @@ -27,7 +27,7 @@ #ifdef CONFIG_DRIVER_ETHER -#if (CONFIG_COMMANDS & CFG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET) /* * Name: diff --git a/cpu/arm920t/at91rm9200/ether.c b/cpu/arm920t/at91rm9200/ether.c index 67008d0b911..f0ec8312165 100644 --- a/cpu/arm920t/at91rm9200/ether.c +++ b/cpu/arm920t/at91rm9200/ether.c @@ -50,7 +50,7 @@ typedef struct { #ifdef CONFIG_DRIVER_ETHER -#if (CONFIG_COMMANDS & CFG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET) /* alignment as per Errata #11 (64 bytes) is insufficient! */ rbf_t rbfdt[RBF_FRAMEMAX] __attribute((aligned(512))); @@ -265,7 +265,7 @@ void eth_halt (void) { }; -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) int at91rm9200_miiphy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short * value) { @@ -288,7 +288,7 @@ int at91rm9200_miiphy_write(char *devname, unsigned char addr, int at91rm9200_miiphy_initialize(bd_t *bis) { -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write); #endif return 0; diff --git a/cpu/arm920t/at91rm9200/lxt972.c b/cpu/arm920t/at91rm9200/lxt972.c index f12c59c158d..c3ddb6d42ae 100644 --- a/cpu/arm920t/at91rm9200/lxt972.c +++ b/cpu/arm920t/at91rm9200/lxt972.c @@ -33,7 +33,7 @@ #ifdef CONFIG_DRIVER_ETHER -#if (CONFIG_COMMANDS & CFG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET) /* * Name: diff --git a/cpu/i386/serial.c b/cpu/i386/serial.c index e7299a7ebb0..a5725b98b6b 100644 --- a/cpu/i386/serial.c +++ b/cpu/i386/serial.c @@ -394,7 +394,7 @@ int serial_buffered_tstc(void) #endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) /* AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port number 0 or number 1 diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c index 7f9f3344b3f..ef6c55273a7 100644 --- a/cpu/ixp/cpu.c +++ b/cpu/ixp/cpu.c @@ -85,7 +85,7 @@ int cpu_init (void) FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; #endif -#if (CONFIG_COMMANDS & CFG_CMD_PCI) || defined (CONFIG_PCI) +#if (CONFIG_COMMANDS & CFG_CMD_PCI) || defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI) pci_init(); #endif return 0; diff --git a/cpu/ixp/npe/npe.c b/cpu/ixp/npe/npe.c index ab7ca8bef04..57a707bf738 100644 --- a/cpu/ixp/npe/npe.c +++ b/cpu/ixp/npe/npe.c @@ -682,7 +682,7 @@ int npe_initialize(bd_t * bis) eth_register(dev); -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) miiphy_register(dev->name, npe_miiphy_read, npe_miiphy_write); #endif diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c index b6540b55af6..36270712e0a 100644 --- a/cpu/mcf52x2/fec.c +++ b/cpu/mcf52x2/fec.c @@ -53,7 +53,7 @@ #undef ET_DEBUG #undef MII_DEBUG -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET) +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(FEC_ENET) #ifdef CFG_DISCOVER_PHY #include @@ -363,7 +363,7 @@ void eth_halt (void) } -#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) static int phyaddr = -1; /* didn't find a PHY yet */ static uint phytype; @@ -485,7 +485,7 @@ static void mii_discover_phy (void) } #endif /* CFG_DISCOVER_PHY */ -#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) +#if ((CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII) static int mii_init_done = 0; @@ -596,8 +596,8 @@ int mcf52x2_miiphy_write (char *devname, unsigned char addr, int mcf52x2_miiphy_initialize(bd_t *bis) { -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET) -#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(FEC_ENET) +#if ((CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII) miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write); #endif #endif diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c index 4f36a84ec4b..2921551ff91 100755 --- a/cpu/microblaze/cache.c +++ b/cpu/microblaze/cache.c @@ -25,7 +25,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_CACHE) +#if (CONFIG_COMMANDS & CFG_CMD_CACHE) || defined(CONFIG_CMD_CACHE) int dcache_status (void) { diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c index b61153f8e6f..b97465aee63 100755 --- a/cpu/microblaze/interrupts.c +++ b/cpu/microblaze/interrupts.c @@ -190,7 +190,7 @@ void interrupt_handler (void) } #endif -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) || defined(CONFIG_CMD_IRQ) #ifdef CFG_INTC_0 int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c index 078e8328b62..de13b054712 100644 --- a/cpu/mips/au1x00_eth.c +++ b/cpu/mips/au1x00_eth.c @@ -63,7 +63,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_MII) +#if (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) #include #endif @@ -241,7 +241,7 @@ int au1x00_enet_initialize(bd_t *bis){ eth_register(dev); -#if (CONFIG_COMMANDS & CFG_CMD_MII) +#if (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) miiphy_register(dev->name, au1x00_miiphy_read, au1x00_miiphy_write); #endif @@ -249,7 +249,7 @@ int au1x00_enet_initialize(bd_t *bis){ return 1; } -#if (CONFIG_COMMANDS & CFG_CMD_MII) +#if (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) int au1x00_miiphy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short * value) { diff --git a/cpu/nios/interrupts.c b/cpu/nios/interrupts.c index 48fc81e5848..cb607999126 100644 --- a/cpu/nios/interrupts.c +++ b/cpu/nios/interrupts.c @@ -173,7 +173,7 @@ void irq_install_handler (int vec, interrupt_handler_t *handler, void *arg) } /*************************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) || defined(CONFIG_CMD_IRQ) int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int vec; diff --git a/cpu/nios2/interrupts.c b/cpu/nios2/interrupts.c index 4685161b88a..d0855502cf4 100644 --- a/cpu/nios2/interrupts.c +++ b/cpu/nios2/interrupts.c @@ -204,7 +204,7 @@ int interrupt_init (void) /*************************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) || defined(CONFIG_CMD_IRQ) int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int i; diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 1200d021af6..5a8f790f51b 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -94,9 +94,9 @@ * network support enabled. * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller! */ -#if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480) +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && !defined(CONFIG_405) && !defined(CONFIG_IOP480) -#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) +#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) #error "CONFIG_MII has to be defined!" #endif @@ -1683,7 +1683,7 @@ int ppc_4xx_eth_initialize (bd_t * bis) #endif #if defined(CONFIG_NET_MULTI) -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) miiphy_register (dev->name, emac4xx_miiphy_read, emac4xx_miiphy_write); #endif @@ -1724,7 +1724,7 @@ int eth_rx(void) int emac4xx_miiphy_initialize (bd_t * bis) { -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) miiphy_register ("ppc_4xx_eth0", emac4xx_miiphy_read, emac4xx_miiphy_write); #endif diff --git a/cpu/ppc4xx/bedbug_405.c b/cpu/ppc4xx/bedbug_405.c index a3c2119764c..f646ea6f346 100644 --- a/cpu/ppc4xx/bedbug_405.c +++ b/cpu/ppc4xx/bedbug_405.c @@ -10,7 +10,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && defined(CONFIG_4xx) +#if ((CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG)) && defined(CONFIG_4xx) #define MAX_BREAK_POINTS 4 diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index c5a9f02566a..b39aad8d231 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -628,7 +628,7 @@ void timer_interrupt_cpu (struct pt_regs *regs) /****************************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) || defined(CONFIG_CMD_IRQ) /******************************************************************************* * diff --git a/cpu/ppc4xx/kgdb.S b/cpu/ppc4xx/kgdb.S index be283403e92..339a0cd0bd4 100644 --- a/cpu/ppc4xx/kgdb.S +++ b/cpu/ppc4xx/kgdb.S @@ -34,7 +34,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) /* * cache flushing routines for kgdb */ diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c index f63fc79f6cb..4debe53c090 100644 --- a/cpu/ppc4xx/ndfc.c +++ b/cpu/ppc4xx/ndfc.c @@ -31,7 +31,7 @@ #include -#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \ +#if ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) && !defined(CFG_NAND_LEGACY) && \ (defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EZ)) diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index e62dd9dac51..67c8a8b0a36 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -843,7 +843,7 @@ int serial_buffered_tstc (void) #endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) /* AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port number 0 or number 1 diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c index eb9420e57a8..96a06412118 100755 --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -78,7 +78,7 @@ static __inline__ unsigned long get_esr(void) #define ESR_DIZ 0x00400000 #define ESR_U0F 0x00008000 -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -158,7 +158,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -297,7 +297,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -312,7 +312,7 @@ ProgramCheckException(struct pt_regs *regs) { long esr_val; -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -349,7 +349,7 @@ DecrementerPITException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -364,7 +364,7 @@ DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c index 6140d2a9089..edaafbf11b1 100644 --- a/cpu/ppc4xx/usbdev.c +++ b/cpu/ppc4xx/usbdev.c @@ -3,7 +3,7 @@ #include #include -#if (defined(CONFIG_440EP) || defined(CONFIG_440EPX)) && (CONFIG_COMMANDS & CFG_CMD_USB) +#if (defined(CONFIG_440EP) || defined(CONFIG_440EPX)) && ((CONFIG_COMMANDS & CFG_CMD_USB) || defined(CONFIG_CMD_USB)) #include #include "usbdev.h" -- cgit v1.3.1 From 52b8704d0245e589f86d462e9ec25aeb7ecbbbdd Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 4 Jul 2007 00:43:53 +0200 Subject: Fix a few file permission problems. Signed-off-by: Wolfgang Denk --- board/siemens/SMN42/flash.c | 0 board/xilinx/ml401/xparameters.h | 0 cpu/microblaze/cache.c | 0 cpu/microblaze/interrupts.c | 0 cpu/microblaze/irq.S | 0 cpu/ppc4xx/traps.c | 0 drivers/enc28j60.c | 0 include/asm-microblaze/asm.h | 0 include/configs/SMN42.h | 0 include/configs/lpc2292sodimm.h | 0 10 files changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 board/siemens/SMN42/flash.c mode change 100755 => 100644 board/xilinx/ml401/xparameters.h mode change 100755 => 100644 cpu/microblaze/cache.c mode change 100755 => 100644 cpu/microblaze/interrupts.c mode change 100755 => 100644 cpu/microblaze/irq.S mode change 100755 => 100644 cpu/ppc4xx/traps.c mode change 100755 => 100644 drivers/enc28j60.c mode change 100755 => 100644 include/asm-microblaze/asm.h mode change 100755 => 100644 include/configs/SMN42.h mode change 100755 => 100644 include/configs/lpc2292sodimm.h (limited to 'cpu') diff --git a/board/siemens/SMN42/flash.c b/board/siemens/SMN42/flash.c old mode 100755 new mode 100644 diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h old mode 100755 new mode 100644 diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c old mode 100755 new mode 100644 diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c old mode 100755 new mode 100644 diff --git a/cpu/microblaze/irq.S b/cpu/microblaze/irq.S old mode 100755 new mode 100644 diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c old mode 100755 new mode 100644 diff --git a/drivers/enc28j60.c b/drivers/enc28j60.c old mode 100755 new mode 100644 diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h old mode 100755 new mode 100644 diff --git a/include/configs/SMN42.h b/include/configs/SMN42.h old mode 100755 new mode 100644 diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h old mode 100755 new mode 100644 -- cgit v1.3.1 From 287ac924adb7291bebe5086652a362a30ab28b13 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 3 Jul 2007 00:32:53 -0600 Subject: Consolidate mpc5xx linker scripts Signed-off-by: Grant Likely --- cpu/mpc5xx/config.mk | 3 ++ cpu/mpc5xx/u-boot.lds | 140 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 143 insertions(+) create mode 100644 cpu/mpc5xx/u-boot.lds (limited to 'cpu') diff --git a/cpu/mpc5xx/config.mk b/cpu/mpc5xx/config.mk index 5b26a76b3e8..64cd60071ad 100644 --- a/cpu/mpc5xx/config.mk +++ b/cpu/mpc5xx/config.mk @@ -31,3 +31,6 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -ffixed-r29 -mpowerpc -msoft-float + +# Use default linker script. Board port can override in board/*/config.mk +LDSCRIPT := $(SRCTREE)/cpu/mpc5xx/u-boot.lds diff --git a/cpu/mpc5xx/u-boot.lds b/cpu/mpc5xx/u-boot.lds new file mode 100644 index 00000000000..5b03fef66c7 --- /dev/null +++ b/cpu/mpc5xx/u-boot.lds @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de + * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc5xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +/* . = env_start; + .ppcenv : + { + common/environment.o (.ppcenv) + } +*/ +} -- cgit v1.3.1 From d181c9a15cd41863fe24840d17848429f27d3c8c Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 3 Jul 2007 00:32:58 -0600 Subject: Consolidate mpc5xxx linker scripts Signed-off-by: Grant Likely --- board/hmi1001/config.mk | 1 + board/inka4x0/config.mk | 1 + board/uc101/config.mk | 1 + cpu/mpc5xxx/config.mk | 3 + cpu/mpc5xxx/u-boot-customlayout.lds | 136 ++++++++++++++++++++++++++++++++++++ cpu/mpc5xxx/u-boot.lds | 125 +++++++++++++++++++++++++++++++++ 6 files changed, 267 insertions(+) create mode 100644 cpu/mpc5xxx/u-boot-customlayout.lds create mode 100644 cpu/mpc5xxx/u-boot.lds (limited to 'cpu') diff --git a/board/hmi1001/config.mk b/board/hmi1001/config.mk index 51e8e84c5c3..4fe18316e5f 100644 --- a/board/hmi1001/config.mk +++ b/board/hmi1001/config.mk @@ -39,3 +39,4 @@ TEXT_BASE = 0xFFF00000 endif PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board +LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot-customlayout.lds diff --git a/board/inka4x0/config.mk b/board/inka4x0/config.mk index cb19a7daeff..fc70efeeed4 100644 --- a/board/inka4x0/config.mk +++ b/board/inka4x0/config.mk @@ -39,3 +39,4 @@ TEXT_BASE = 0xFFE00000 endif PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board +LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot-customlayout.lds diff --git a/board/uc101/config.mk b/board/uc101/config.mk index 51e8e84c5c3..4fe18316e5f 100644 --- a/board/uc101/config.mk +++ b/board/uc101/config.mk @@ -39,3 +39,4 @@ TEXT_BASE = 0xFFF00000 endif PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board +LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot-customlayout.lds diff --git a/cpu/mpc5xxx/config.mk b/cpu/mpc5xxx/config.mk index ecd94e9b34a..0df51babd70 100644 --- a/cpu/mpc5xxx/config.mk +++ b/cpu/mpc5xxx/config.mk @@ -25,3 +25,6 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 -ffixed-r29 \ -mstring -mcpu=603e -mmultiple + +# Use default linker script. Board port can override in board/*/config.mk +LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot.lds diff --git a/cpu/mpc5xxx/u-boot-customlayout.lds b/cpu/mpc5xxx/u-boot-customlayout.lds new file mode 100644 index 00000000000..123a14c5aa0 --- /dev/null +++ b/cpu/mpc5xxx/u-boot-customlayout.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc5xxx/start.o (.text) + cpu/mpc5xxx/traps.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.ppcenv) + + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/mpc5xxx/u-boot.lds b/cpu/mpc5xxx/u-boot.lds new file mode 100644 index 00000000000..78818a49ebd --- /dev/null +++ b/cpu/mpc5xxx/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} -- cgit v1.3.1 From 9c757b789a59a855db57b448dd825329c4e9c4a0 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 3 Jul 2007 00:33:03 -0600 Subject: Consolidate mpc8220 linker scripts Signed-off-by: Grant Likely --- cpu/mpc8220/config.mk | 3 ++ cpu/mpc8220/u-boot.lds | 125 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 128 insertions(+) create mode 100644 cpu/mpc8220/u-boot.lds (limited to 'cpu') diff --git a/cpu/mpc8220/config.mk b/cpu/mpc8220/config.mk index 6fec5dfe60c..8e3ba54287c 100644 --- a/cpu/mpc8220/config.mk +++ b/cpu/mpc8220/config.mk @@ -25,3 +25,6 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 -ffixed-r29 \ -mstring -mcpu=603e -mmultiple + +# Use default linker script. Board port can override in board/*/config.mk +LDSCRIPT := $(SRCTREE)/cpu/mpc8220/u-boot.lds diff --git a/cpu/mpc8220/u-boot.lds b/cpu/mpc8220/u-boot.lds new file mode 100644 index 00000000000..889bc77d2f8 --- /dev/null +++ b/cpu/mpc8220/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8220/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} -- cgit v1.3.1 From 737f9eb02d7335df2b3e4d7a4d3348784d1da207 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 3 Jul 2007 00:33:08 -0600 Subject: Consolidate mpc824x linker scripts Signed-off-by: Grant Likely --- board/mousse/config.mk | 2 + cpu/mpc824x/config.mk | 3 ++ cpu/mpc824x/u-boot.lds | 125 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 130 insertions(+) create mode 100644 cpu/mpc824x/u-boot.lds (limited to 'cpu') diff --git a/board/mousse/config.mk b/board/mousse/config.mk index 64cffa4ee2d..933e6b32a07 100644 --- a/board/mousse/config.mk +++ b/board/mousse/config.mk @@ -26,3 +26,5 @@ # TEXT_BASE = 0xFFF00000 PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) + +LDSCRIPT := $(SRCTREE)/board/mousse/u-boot.lds diff --git a/cpu/mpc824x/config.mk b/cpu/mpc824x/config.mk index dac61d8d3e3..66207f4354d 100644 --- a/cpu/mpc824x/config.mk +++ b/cpu/mpc824x/config.mk @@ -24,3 +24,6 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -msoft-float + +# Use default linker script. Board port can override in board/*/config.mk +LDSCRIPT := $(SRCTREE)/cpu/mpc824x/u-boot.lds diff --git a/cpu/mpc824x/u-boot.lds b/cpu/mpc824x/u-boot.lds new file mode 100644 index 00000000000..c90d1e9457e --- /dev/null +++ b/cpu/mpc824x/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} -- cgit v1.3.1 From 5fc59175b92883ed5d2666a04e6bc49e70a4a365 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 3 Jul 2007 00:33:13 -0600 Subject: Consolidate mpc8260 linker scripts Signed-off-by: Grant Likely --- board/cogent/config.mk | 2 + board/hymod/config.mk | 2 + board/rsdproto/config.mk | 2 + cpu/mpc8260/config.mk | 3 ++ cpu/mpc8260/u-boot.lds | 125 +++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 134 insertions(+) create mode 100644 cpu/mpc8260/u-boot.lds (limited to 'cpu') diff --git a/board/cogent/config.mk b/board/cogent/config.mk index ee779394bbe..35a5ed3d06a 100644 --- a/board/cogent/config.mk +++ b/board/cogent/config.mk @@ -29,3 +29,5 @@ TEXT_BASE = 0xfff00000 PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) + +LDSCRIPT := $(SRCTREE)/board/cogent/u-boot.lds diff --git a/board/hymod/config.mk b/board/hymod/config.mk index 0a9985f337c..2df321fdde7 100644 --- a/board/hymod/config.mk +++ b/board/hymod/config.mk @@ -30,3 +30,5 @@ TEXT_BASE = 0x40000000 PLATFORM_CPPFLAGS += -I$(TOPDIR) OBJCFLAGS = --remove-section=.ppcenv + +LDSCRIPT := $(SRCTREE)/board/hymod/u-boot.lds diff --git a/board/rsdproto/config.mk b/board/rsdproto/config.mk index 5844ec1ea4c..35c3d8c7688 100644 --- a/board/rsdproto/config.mk +++ b/board/rsdproto/config.mk @@ -31,3 +31,5 @@ TEXT_BASE = 0xff000000 /*TEXT_BASE = 0x00200000 */ + +LDSCRIPT := $(SRCTREE)/board/rsdproto/u-boot.lds diff --git a/cpu/mpc8260/config.mk b/cpu/mpc8260/config.mk index dd7a71fdf36..683b6fbf2b2 100644 --- a/cpu/mpc8260/config.mk +++ b/cpu/mpc8260/config.mk @@ -25,3 +25,6 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 -ffixed-r29 \ -mstring -mcpu=603e -mmultiple + +# Use default linker script. Board port can override in board/*/config.mk +LDSCRIPT := $(SRCTREE)/cpu/mpc8260/u-boot.lds diff --git a/cpu/mpc8260/u-boot.lds b/cpu/mpc8260/u-boot.lds new file mode 100644 index 00000000000..3e84f234d72 --- /dev/null +++ b/cpu/mpc8260/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} -- cgit v1.3.1 From 416a0b6d40f6eba3a2fc547253c16bda28d922f7 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 3 Jul 2007 00:33:18 -0600 Subject: Consolidate mpc83xx linker scripts Signed-off-by: Grant Likely --- cpu/mpc83xx/config.mk | 3 ++ cpu/mpc83xx/u-boot.lds | 123 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 126 insertions(+) create mode 100644 cpu/mpc83xx/u-boot.lds (limited to 'cpu') diff --git a/cpu/mpc83xx/config.mk b/cpu/mpc83xx/config.mk index 8b4ff92b19c..ecf8a60bbef 100644 --- a/cpu/mpc83xx/config.mk +++ b/cpu/mpc83xx/config.mk @@ -24,3 +24,6 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC83XX -DCONFIG_E300 \ -ffixed-r2 -ffixed-r29 -msoft-float + +# Use default linker script. Board port can override in board/*/config.mk +LDSCRIPT := $(SRCTREE)/cpu/mpc83xx/u-boot.lds diff --git a/cpu/mpc83xx/u-boot.lds b/cpu/mpc83xx/u-boot.lds new file mode 100644 index 00000000000..937c87a27cd --- /dev/null +++ b/cpu/mpc83xx/u-boot.lds @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc83xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) -- cgit v1.3.1 From 3649cd99ba815b6601868735765602f00ef3692b Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 3 Jul 2007 00:34:24 -0600 Subject: Correct relocation fixup for mpc5xx Signed-off-by: Grant Likely --- cpu/mpc5xx/config.mk | 2 +- cpu/mpc5xx/u-boot.lds | 1 - include/common.h | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc5xx/config.mk b/cpu/mpc5xx/config.mk index 64cd60071ad..e95b8a1a855 100644 --- a/cpu/mpc5xx/config.mk +++ b/cpu/mpc5xx/config.mk @@ -28,7 +28,7 @@ # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -ffixed-r29 -mpowerpc -msoft-float diff --git a/cpu/mpc5xx/u-boot.lds b/cpu/mpc5xx/u-boot.lds index 5b03fef66c7..10001b1c1de 100644 --- a/cpu/mpc5xx/u-boot.lds +++ b/cpu/mpc5xx/u-boot.lds @@ -59,7 +59,6 @@ SECTIONS cpu/mpc5xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/include/common.h b/include/common.h index d8b6b469e5f..7319c549392 100644 --- a/include/common.h +++ b/include/common.h @@ -63,6 +63,7 @@ typedef volatile unsigned char vu_char; #endif #elif defined(CONFIG_5xx) #include +#define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_MPC5xxx) #include #elif defined(CONFIG_MPC8220) -- cgit v1.3.1 From 6f7576b20ecf0d040c3ac3b032b5cbc860e38a90 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 3 Jul 2007 00:34:29 -0600 Subject: Correct fixup relocation for MPC5xxx Signed-off-by: Grant Likely --- cpu/mpc5xxx/config.mk | 2 +- cpu/mpc5xxx/u-boot-customlayout.lds | 1 - cpu/mpc5xxx/u-boot.lds | 1 - include/common.h | 1 + 4 files changed, 2 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc5xxx/config.mk b/cpu/mpc5xxx/config.mk index 0df51babd70..0e861c4a0f8 100644 --- a/cpu/mpc5xxx/config.mk +++ b/cpu/mpc5xxx/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 -ffixed-r29 \ -mstring -mcpu=603e -mmultiple diff --git a/cpu/mpc5xxx/u-boot-customlayout.lds b/cpu/mpc5xxx/u-boot-customlayout.lds index 123a14c5aa0..11079430d57 100644 --- a/cpu/mpc5xxx/u-boot-customlayout.lds +++ b/cpu/mpc5xxx/u-boot-customlayout.lds @@ -66,7 +66,6 @@ SECTIONS common/environment.o (.ppcenv) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.rodata) diff --git a/cpu/mpc5xxx/u-boot.lds b/cpu/mpc5xxx/u-boot.lds index 78818a49ebd..a28a3afc71c 100644 --- a/cpu/mpc5xxx/u-boot.lds +++ b/cpu/mpc5xxx/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS { cpu/mpc5xxx/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.rodata) diff --git a/include/common.h b/include/common.h index 7319c549392..a905072ae3c 100644 --- a/include/common.h +++ b/include/common.h @@ -66,6 +66,7 @@ typedef volatile unsigned char vu_char; #define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_MPC5xxx) #include +#define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_MPC8220) #include #elif defined(CONFIG_8260) -- cgit v1.3.1 From a85dd254c0577fca13627c46e93fc2ad4c4f1f00 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 3 Jul 2007 00:34:34 -0600 Subject: Correct fixup relocation for mpc8220 Signed-off-by: Grant Likely --- cpu/mpc8220/config.mk | 2 +- cpu/mpc8220/u-boot.lds | 1 - include/common.h | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc8220/config.mk b/cpu/mpc8220/config.mk index 8e3ba54287c..c41cafe97fe 100644 --- a/cpu/mpc8220/config.mk +++ b/cpu/mpc8220/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 -ffixed-r29 \ -mstring -mcpu=603e -mmultiple diff --git a/cpu/mpc8220/u-boot.lds b/cpu/mpc8220/u-boot.lds index 889bc77d2f8..a199a64f131 100644 --- a/cpu/mpc8220/u-boot.lds +++ b/cpu/mpc8220/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS { cpu/mpc8220/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.rodata) diff --git a/include/common.h b/include/common.h index a905072ae3c..93ddfb85eab 100644 --- a/include/common.h +++ b/include/common.h @@ -69,6 +69,7 @@ typedef volatile unsigned char vu_char; #define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_MPC8220) #include +#define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_8260) #if defined(CONFIG_MPC8247) \ || defined(CONFIG_MPC8248) \ -- cgit v1.3.1 From f3a52fe05923935db86985daf9438e2f70ac39aa Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 3 Jul 2007 00:34:39 -0600 Subject: Correct fixup relocation for mpc824x Signed-off-by: Grant Likely --- board/mousse/u-boot.lds | 1 - cpu/mpc824x/config.mk | 2 +- cpu/mpc824x/u-boot.lds | 1 - include/common.h | 2 ++ 4 files changed, 3 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds index 57358b8a49d..eb4d8e4e2b6 100644 --- a/board/mousse/u-boot.lds +++ b/board/mousse/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS lib_generic/crc32.o (.text) lib_generic/zlib.o (.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.rodata) diff --git a/cpu/mpc824x/config.mk b/cpu/mpc824x/config.mk index 66207f4354d..17fdb21d35a 100644 --- a/cpu/mpc824x/config.mk +++ b/cpu/mpc824x/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing -mrelocatable PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -msoft-float diff --git a/cpu/mpc824x/u-boot.lds b/cpu/mpc824x/u-boot.lds index c90d1e9457e..8cbef4aed43 100644 --- a/cpu/mpc824x/u-boot.lds +++ b/cpu/mpc824x/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS { cpu/mpc824x/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.rodata) diff --git a/include/common.h b/include/common.h index 93ddfb85eab..4c50053c021 100644 --- a/include/common.h +++ b/include/common.h @@ -70,6 +70,8 @@ typedef volatile unsigned char vu_char; #elif defined(CONFIG_MPC8220) #include #define CONFIG_RELOC_FIXUP_WORKS +#elif defined(CONFIG_824X) +#define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_8260) #if defined(CONFIG_MPC8247) \ || defined(CONFIG_MPC8248) \ -- cgit v1.3.1 From 5af61b2f4b838a05f79be274f3e5a66edd2d9c96 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 3 Jul 2007 00:34:44 -0600 Subject: Correct fixup relocation for mpc8260 Signed-off-by: Grant Likely --- board/cogent/u-boot.lds | 1 - board/hymod/u-boot.lds | 1 - board/rsdproto/u-boot.lds | 1 - cpu/mpc8260/config.mk | 2 +- cpu/mpc8260/u-boot.lds | 1 - include/common.h | 1 + 6 files changed, 2 insertions(+), 5 deletions(-) (limited to 'cpu') diff --git a/board/cogent/u-boot.lds b/board/cogent/u-boot.lds index 5ce2694cbf7..d87a39b2496 100644 --- a/board/cogent/u-boot.lds +++ b/board/cogent/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS { *(.text) common/environment.o(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds index 337a3954d2d..9bf0f0938a2 100644 --- a/board/hymod/u-boot.lds +++ b/board/hymod/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS common/environment.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds index 70fc3a5d279..9bd62480952 100644 --- a/board/rsdproto/u-boot.lds +++ b/board/rsdproto/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS { cpu/mpc8260/start.o (.text) *(.text) - *(.fixup) *(.got1) /*. = env_offset; */ } diff --git a/cpu/mpc8260/config.mk b/cpu/mpc8260/config.mk index 683b6fbf2b2..d401e4ca04f 100644 --- a/cpu/mpc8260/config.mk +++ b/cpu/mpc8260/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 -ffixed-r29 \ -mstring -mcpu=603e -mmultiple diff --git a/cpu/mpc8260/u-boot.lds b/cpu/mpc8260/u-boot.lds index 3e84f234d72..b8abc17d413 100644 --- a/cpu/mpc8260/u-boot.lds +++ b/cpu/mpc8260/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS { cpu/mpc8260/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.rodata) diff --git a/include/common.h b/include/common.h index 4c50053c021..b224e06976b 100644 --- a/include/common.h +++ b/include/common.h @@ -83,6 +83,7 @@ typedef volatile unsigned char vu_char; #define CONFIG_MPC8260 1 #endif #include +#define CONFIG_RELOC_FIXUP_WORKS #endif #ifdef CONFIG_MPC86xx #include -- cgit v1.3.1 From 057004f4a4863554d56cc56268bfa7c7d9738e27 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 3 Jul 2007 00:34:49 -0600 Subject: Correct fixup relocation for mpc83xx Signed-off-by: Grant Likely --- cpu/mpc83xx/config.mk | 2 +- cpu/mpc83xx/u-boot.lds | 1 - include/common.h | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/config.mk b/cpu/mpc83xx/config.mk index ecf8a60bbef..2ec395d4ca9 100644 --- a/cpu/mpc83xx/config.mk +++ b/cpu/mpc83xx/config.mk @@ -20,7 +20,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable PLATFORM_CPPFLAGS += -DCONFIG_MPC83XX -DCONFIG_E300 \ -ffixed-r2 -ffixed-r29 -msoft-float diff --git a/cpu/mpc83xx/u-boot.lds b/cpu/mpc83xx/u-boot.lds index 937c87a27cd..ca663bc87bf 100644 --- a/cpu/mpc83xx/u-boot.lds +++ b/cpu/mpc83xx/u-boot.lds @@ -52,7 +52,6 @@ SECTIONS { cpu/mpc83xx/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.rodata) diff --git a/include/common.h b/include/common.h index b224e06976b..d89617ae2c9 100644 --- a/include/common.h +++ b/include/common.h @@ -96,6 +96,7 @@ typedef volatile unsigned char vu_char; #ifdef CONFIG_MPC83XX #include #include +#define CONFIG_RELOC_FIXUP_WORKS #endif #ifdef CONFIG_4xx #include -- cgit v1.3.1 From 56b304ac2091689506088a9ae67f63fd6300cf16 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 13 Jun 2007 13:21:37 -0500 Subject: Fix #if typo in CONFIG_CMD_* changes. Signed-off-by: Jon Loeliger --- cpu/mpc85xx/ether_fcc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c index a6b2ae3fbeb..ec3990cb8d8 100644 --- a/cpu/mpc85xx/ether_fcc.c +++ b/cpu/mpc85xx/ether_fcc.c @@ -458,7 +458,7 @@ int fec_initialize(bd_t *bis) eth_register(dev); -#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) || \ +#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) \ && defined(CONFIG_BITBANGMII) miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write); -- cgit v1.3.1 From b24629fa377214d63bb40d1360e354b6d3e4af56 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 13 Jun 2007 13:23:15 -0500 Subject: mpc86xx: Remove old CFG_CMD_* references. Signed-off-by: Jon Loeliger --- cpu/mpc86xx/traps.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c index 06334b719b9..fab1975834e 100644 --- a/cpu/mpc86xx/traps.c +++ b/cpu/mpc86xx/traps.c @@ -34,7 +34,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -122,7 +122,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif @@ -155,7 +155,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif @@ -170,7 +170,7 @@ ProgramCheckException(struct pt_regs *regs) unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL; int i, j; -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif @@ -193,7 +193,7 @@ ProgramCheckException(struct pt_regs *regs) void SoftEmuException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif @@ -205,7 +205,7 @@ SoftEmuException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif -- cgit v1.3.1 From e4dbe1b215f5c6c462e76909d240bd96472b84de Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 5 Jul 2007 17:56:27 +0200 Subject: Fixing some typos etc. introduced mainly by cfg patches. Signed-off-by: Wolfgang Denk --- cpu/mpc8260/cpu_init.c | 2 +- fs/jffs2/jffs2_1pass.c | 9 ++++++--- include/configs/MPC8260ADS.h | 4 ++-- include/configs/Total5200.h | 2 +- include/configs/ZPC1900.h | 12 ++++++------ include/configs/lwmon.h | 2 +- 6 files changed, 17 insertions(+), 14 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c index 380d7af13d3..36fc1eba5fd 100644 --- a/cpu/mpc8260/cpu_init.c +++ b/cpu/mpc8260/cpu_init.c @@ -182,7 +182,7 @@ void cpu_init_f (volatile immap_t * immr) #endif /* now restrict to preliminary range */ - /* the PS came from the HRCW, don´t change it */ + /* the PS came from the HRCW, don´t change it */ memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CFG_BR0_PRELIM, BRx_PS_MSK); memctl->memc_or0 = CFG_OR0_PRELIM; diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c index 6a7d7f7fac6..af2a8e28067 100644 --- a/fs/jffs2/jffs2_1pass.c +++ b/fs/jffs2/jffs2_1pass.c @@ -143,7 +143,8 @@ /* keeps pointer to currentlu processed partition */ static struct part_info *current_part; -#if (defined(CONFIG_JFFS2_NAND) && ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) +#if (defined(CONFIG_JFFS2_NAND) && \ + ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) ) #if defined(CFG_NAND_LEGACY) #include #else @@ -334,7 +335,8 @@ static inline void *get_node_mem(u32 off) return get_node_mem_nor(off); #endif -#if defined(CONFIG_JFFS2_NAND) && ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND) +#if defined(CONFIG_JFFS2_NAND) && \ + (CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND) if (id->type == MTD_DEV_TYPE_NAND) return get_node_mem_nand(off); #endif @@ -345,7 +347,8 @@ static inline void *get_node_mem(u32 off) static inline void put_fl_mem(void *buf) { -#if defined(CONFIG_JFFS2_NAND) && ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND) +#if defined(CONFIG_JFFS2_NAND) && \ + (CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND) struct mtdids *id = current_part->dev->id; if (id->type == MTD_DEV_TYPE_NAND) diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index eceeb5e3973..69d4c28f03d 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -250,7 +250,7 @@ #define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/mtdblock2" -#if defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) || (CONFIG_COMMANDS & CFG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -268,7 +268,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) || (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index ba2daf73cd7..2a1cb89ad4f 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -115,7 +115,7 @@ */ #include -#if definded(CONFIG_MPC5200) +#if defined(CONFIG_MPC5200) #define CONFIG_CMD_PCI #endif diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h index a5085cfb79d..2b02fe75093 100644 --- a/include/configs/ZPC1900.h +++ b/include/configs/ZPC1900.h @@ -248,18 +248,18 @@ #define CFG_LSRT 0x0F #define CFG_MPTPR 0x4000 -#define CFG_PSDRAM_BR CFG_SDRAM_BASE | 0x00000041 +#define CFG_PSDRAM_BR (CFG_SDRAM_BASE | 0x00000041) #define CFG_PSDRAM_OR 0xFC0028C0 -#define CFG_LSDRAM_BR CFG_LSDRAM_BASE | 0x00001861 +#define CFG_LSDRAM_BR (CFG_LSDRAM_BASE | 0x00001861) #define CFG_LSDRAM_OR 0xFF803480 -#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00000801 +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00000801) #define CFG_OR0_PRELIM 0xFFE00856 -#define CFG_BR5_PRELIM CFG_EEPROM | 0x00000801 +#define CFG_BR5_PRELIM (CFG_EEPROM | 0x00000801) #define CFG_OR5_PRELIM 0xFFFF03F6 -#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00001801 +#define CFG_BR6_PRELIM (CFG_FLSIMM_BASE | 0x00001801) #define CFG_OR6_PRELIM 0xFF000856 -#define CFG_BR7_PRELIM CFG_BCSR | 0x00000801 +#define CFG_BR7_PRELIM (CFG_BCSR | 0x00000801) #define CFG_OR7_PRELIM 0xFFFF83F6 #define CFG_RESET_ADDRESS 0xC0000000 diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h index 627bc9cf41e..3dc7a8eb650 100644 --- a/include/configs/lwmon.h +++ b/include/configs/lwmon.h @@ -279,7 +279,7 @@ */ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0x40000000 -#if defined(DEBUG) || defiend(CONFIG_CMD_IDE) +#if defined(DEBUG) || defined(CONFIG_CMD_IDE) #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #else #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -- cgit v1.3.1 From 6b0a174a1e6f55e1f5a1fbb223cdad7645a4646e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 6 Jul 2007 09:45:47 +0200 Subject: Fix problem with get/setdcr commands introduced by cfg patches Signed-off-by: Stefan Roese --- cpu/ppc4xx/dcr.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/dcr.S b/cpu/ppc4xx/dcr.S index 7102364ebdf..554db1bc77f 100644 --- a/cpu/ppc4xx/dcr.S +++ b/cpu/ppc4xx/dcr.S @@ -22,7 +22,7 @@ */ #include -#if defined(CONFIG_4xx) && defined(CFG_CMD_SETGETDCR) +#if defined(CONFIG_4xx) && ((CONFIG_COMMANDS & CFG_CMD_SETGETDCR) || defined(CONFIG_CMD_SETGETDCR)) #include -- cgit v1.3.1 From 3a1ed1e1f922c419bb71f7df4949d783ade369fa Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 9 Jul 2007 18:57:22 -0500 Subject: cpu/[7a-ln-z]*: Remove obsolete references to CONFIG_COMMANDS Signed-off-by: Jon Loeliger --- cpu/74xx_7xx/kgdb.S | 2 +- cpu/74xx_7xx/traps.c | 12 ++++++------ cpu/arm920t/at91rm9200/bcm5221.c | 4 ++-- cpu/arm920t/at91rm9200/dm9161.c | 4 ++-- cpu/arm920t/at91rm9200/ether.c | 10 +++++----- cpu/arm920t/at91rm9200/lxt972.c | 4 ++-- cpu/i386/serial.c | 2 +- cpu/ixp/cpu.c | 2 +- cpu/ixp/npe/npe.c | 2 +- cpu/nios/interrupts.c | 4 ++-- cpu/nios2/interrupts.c | 4 ++-- cpu/ppc4xx/4xx_enet.c | 10 +++++----- cpu/ppc4xx/bedbug_405.c | 2 +- cpu/ppc4xx/dcr.S | 2 +- cpu/ppc4xx/interrupts.c | 4 ++-- cpu/ppc4xx/kgdb.S | 2 +- cpu/ppc4xx/ndfc.c | 2 +- cpu/ppc4xx/serial.c | 2 +- cpu/ppc4xx/traps.c | 14 +++++++------- cpu/ppc4xx/usbdev.c | 2 +- 20 files changed, 45 insertions(+), 45 deletions(-) (limited to 'cpu') diff --git a/cpu/74xx_7xx/kgdb.S b/cpu/74xx_7xx/kgdb.S index 5d2ce85e9c0..cd8869c2006 100644 --- a/cpu/74xx_7xx/kgdb.S +++ b/cpu/74xx_7xx/kgdb.S @@ -31,7 +31,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) /* * cache flushing routines for kgdb diff --git a/cpu/74xx_7xx/traps.c b/cpu/74xx_7xx/traps.c index e7658bbf270..b0662276969 100644 --- a/cpu/74xx_7xx/traps.c +++ b/cpu/74xx_7xx/traps.c @@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -133,7 +133,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -166,7 +166,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -181,7 +181,7 @@ ProgramCheckException(struct pt_regs *regs) unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL; int i, j; -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -204,7 +204,7 @@ ProgramCheckException(struct pt_regs *regs) void SoftEmuException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -217,7 +217,7 @@ SoftEmuException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif diff --git a/cpu/arm920t/at91rm9200/bcm5221.c b/cpu/arm920t/at91rm9200/bcm5221.c index b0d87954dc5..b52c615864c 100644 --- a/cpu/arm920t/at91rm9200/bcm5221.c +++ b/cpu/arm920t/at91rm9200/bcm5221.c @@ -32,7 +32,7 @@ #ifdef CONFIG_DRIVER_ETHER -#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET) +#if defined(CONFIG_CMD_NET) /* * Name: @@ -227,6 +227,6 @@ unsigned char bcm5221_AutoNegotiate (AT91PS_EMAC p_mac, int *status) return FALSE; } -#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ +#endif #endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm920t/at91rm9200/dm9161.c b/cpu/arm920t/at91rm9200/dm9161.c index eaa6ccb4535..968f653081f 100644 --- a/cpu/arm920t/at91rm9200/dm9161.c +++ b/cpu/arm920t/at91rm9200/dm9161.c @@ -27,7 +27,7 @@ #ifdef CONFIG_DRIVER_ETHER -#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET) +#if defined(CONFIG_CMD_NET) /* * Name: @@ -220,6 +220,6 @@ UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status) return FALSE; } -#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ +#endif #endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm920t/at91rm9200/ether.c b/cpu/arm920t/at91rm9200/ether.c index f0ec8312165..c8f56aa52de 100644 --- a/cpu/arm920t/at91rm9200/ether.c +++ b/cpu/arm920t/at91rm9200/ether.c @@ -50,7 +50,7 @@ typedef struct { #ifdef CONFIG_DRIVER_ETHER -#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET) +#if defined(CONFIG_CMD_NET) /* alignment as per Errata #11 (64 bytes) is insufficient! */ rbf_t rbfdt[RBF_FRAMEMAX] __attribute((aligned(512))); @@ -265,7 +265,7 @@ void eth_halt (void) { }; -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) int at91rm9200_miiphy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short * value) { @@ -284,16 +284,16 @@ int at91rm9200_miiphy_write(char *devname, unsigned char addr, return 0; } -#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */ +#endif int at91rm9200_miiphy_initialize(bd_t *bis) { -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write); #endif return 0; } -#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ +#endif #endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm920t/at91rm9200/lxt972.c b/cpu/arm920t/at91rm9200/lxt972.c index c3ddb6d42ae..4edcc9a1b9d 100644 --- a/cpu/arm920t/at91rm9200/lxt972.c +++ b/cpu/arm920t/at91rm9200/lxt972.c @@ -33,7 +33,7 @@ #ifdef CONFIG_DRIVER_ETHER -#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET) +#if defined(CONFIG_CMD_NET) /* * Name: @@ -186,6 +186,6 @@ UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status) return (lxt972_GetLinkSpeed (p_mac)); } -#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ +#endif #endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/i386/serial.c b/cpu/i386/serial.c index a5725b98b6b..4933d23fd41 100644 --- a/cpu/i386/serial.c +++ b/cpu/i386/serial.c @@ -394,7 +394,7 @@ int serial_buffered_tstc(void) #endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) /* AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port number 0 or number 1 diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c index ef6c55273a7..2c7d5a01be7 100644 --- a/cpu/ixp/cpu.c +++ b/cpu/ixp/cpu.c @@ -85,7 +85,7 @@ int cpu_init (void) FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; #endif -#if (CONFIG_COMMANDS & CFG_CMD_PCI) || defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI) +#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI) pci_init(); #endif return 0; diff --git a/cpu/ixp/npe/npe.c b/cpu/ixp/npe/npe.c index 57a707bf738..7e4af441054 100644 --- a/cpu/ixp/npe/npe.c +++ b/cpu/ixp/npe/npe.c @@ -682,7 +682,7 @@ int npe_initialize(bd_t * bis) eth_register(dev); -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register(dev->name, npe_miiphy_read, npe_miiphy_write); #endif diff --git a/cpu/nios/interrupts.c b/cpu/nios/interrupts.c index cb607999126..75e491d8436 100644 --- a/cpu/nios/interrupts.c +++ b/cpu/nios/interrupts.c @@ -173,7 +173,7 @@ void irq_install_handler (int vec, interrupt_handler_t *handler, void *arg) } /*************************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) || defined(CONFIG_CMD_IRQ) +#if defined(CONFIG_CMD_IRQ) int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int vec; @@ -193,4 +193,4 @@ int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return (0); } -#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ +#endif diff --git a/cpu/nios2/interrupts.c b/cpu/nios2/interrupts.c index d0855502cf4..aeb5b65b330 100644 --- a/cpu/nios2/interrupts.c +++ b/cpu/nios2/interrupts.c @@ -204,7 +204,7 @@ int interrupt_init (void) /*************************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) || defined(CONFIG_CMD_IRQ) +#if defined(CONFIG_CMD_IRQ) int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int i; @@ -228,4 +228,4 @@ int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return (0); } -#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ +#endif diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 5a8f790f51b..d78279171e2 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -94,9 +94,9 @@ * network support enabled. * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller! */ -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && !defined(CONFIG_405) && !defined(CONFIG_IOP480) +#if defined(CONFIG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480) -#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) +#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) #error "CONFIG_MII has to be defined!" #endif @@ -1683,7 +1683,7 @@ int ppc_4xx_eth_initialize (bd_t * bis) #endif #if defined(CONFIG_NET_MULTI) -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register (dev->name, emac4xx_miiphy_read, emac4xx_miiphy_write); #endif @@ -1724,7 +1724,7 @@ int eth_rx(void) int emac4xx_miiphy_initialize (bd_t * bis) { -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register ("ppc_4xx_eth0", emac4xx_miiphy_read, emac4xx_miiphy_write); #endif @@ -1733,4 +1733,4 @@ int emac4xx_miiphy_initialize (bd_t * bis) } #endif /* !defined(CONFIG_NET_MULTI) */ -#endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */ +#endif diff --git a/cpu/ppc4xx/bedbug_405.c b/cpu/ppc4xx/bedbug_405.c index f646ea6f346..5ef5607918d 100644 --- a/cpu/ppc4xx/bedbug_405.c +++ b/cpu/ppc4xx/bedbug_405.c @@ -10,7 +10,7 @@ #include #include -#if ((CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG)) && defined(CONFIG_4xx) +#if defined(CONFIG_CMD_BEDBUG) && defined(CONFIG_4xx) #define MAX_BREAK_POINTS 4 diff --git a/cpu/ppc4xx/dcr.S b/cpu/ppc4xx/dcr.S index 554db1bc77f..fe136e0fa29 100644 --- a/cpu/ppc4xx/dcr.S +++ b/cpu/ppc4xx/dcr.S @@ -22,7 +22,7 @@ */ #include -#if defined(CONFIG_4xx) && ((CONFIG_COMMANDS & CFG_CMD_SETGETDCR) || defined(CONFIG_CMD_SETGETDCR)) +#if defined(CONFIG_4xx) && defined(CONFIG_CMD_SETGETDCR) #include diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index b39aad8d231..ca565cc3e07 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -628,7 +628,7 @@ void timer_interrupt_cpu (struct pt_regs *regs) /****************************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) || defined(CONFIG_CMD_IRQ) +#if defined(CONFIG_CMD_IRQ) /******************************************************************************* * @@ -698,4 +698,4 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } -#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ +#endif diff --git a/cpu/ppc4xx/kgdb.S b/cpu/ppc4xx/kgdb.S index 339a0cd0bd4..cd12727be3c 100644 --- a/cpu/ppc4xx/kgdb.S +++ b/cpu/ppc4xx/kgdb.S @@ -34,7 +34,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) /* * cache flushing routines for kgdb */ diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c index 4debe53c090..398457726f4 100644 --- a/cpu/ppc4xx/ndfc.c +++ b/cpu/ppc4xx/ndfc.c @@ -31,7 +31,7 @@ #include -#if ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) && !defined(CFG_NAND_LEGACY) && \ +#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \ (defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EZ)) diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index 67c8a8b0a36..aefa4cabab6 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -843,7 +843,7 @@ int serial_buffered_tstc (void) #endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) /* AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port number 0 or number 1 diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c index 96a06412118..899cdbd1f44 100644 --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -78,7 +78,7 @@ static __inline__ unsigned long get_esr(void) #define ESR_DIZ 0x00400000 #define ESR_U0F 0x00008000 -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) +#if defined(CONFIG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -158,7 +158,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -297,7 +297,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -312,7 +312,7 @@ ProgramCheckException(struct pt_regs *regs) { long esr_val; -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -349,7 +349,7 @@ DecrementerPITException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -364,7 +364,7 @@ DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) +#if defined(CONFIG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c index edaafbf11b1..5924a6cb847 100644 --- a/cpu/ppc4xx/usbdev.c +++ b/cpu/ppc4xx/usbdev.c @@ -3,7 +3,7 @@ #include #include -#if (defined(CONFIG_440EP) || defined(CONFIG_440EPX)) && ((CONFIG_COMMANDS & CFG_CMD_USB) || defined(CONFIG_CMD_USB)) +#if (defined(CONFIG_440EP) || defined(CONFIG_440EPX)) && defined(CONFIG_CMD_USB) #include #include "usbdev.h" -- cgit v1.3.1 From 4431283c7e6d54ae180d466e51bf2d97471a0ad9 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 9 Jul 2007 19:06:00 -0500 Subject: cpu/m*: Remove obsolete references to CONFIG_COMMANDS Signed-off-by: Jon Loeliger --- cpu/mcf52x2/fec.c | 14 +++++++------- cpu/microblaze/cache.c | 2 +- cpu/microblaze/interrupts.c | 4 ++-- cpu/mips/au1x00_eth.c | 8 ++++---- cpu/mpc5xx/interrupts.c | 4 ++-- cpu/mpc5xx/traps.c | 16 ++++++++-------- cpu/mpc5xxx/cpu_init.c | 2 +- cpu/mpc5xxx/fec.c | 6 +++--- cpu/mpc5xxx/interrupts.c | 2 +- cpu/mpc5xxx/traps.c | 16 ++++++++-------- cpu/mpc8220/cpu_init.c | 2 +- cpu/mpc8220/fec.c | 6 +++--- cpu/mpc8220/traps.c | 16 ++++++++-------- cpu/mpc824x/traps.c | 4 ++-- cpu/mpc8260/bedbug_603e.c | 2 +- cpu/mpc8260/ether_fcc.c | 6 +++--- cpu/mpc8260/ether_scc.c | 2 +- cpu/mpc8260/interrupts.c | 4 ++-- cpu/mpc8260/kgdb.S | 2 +- cpu/mpc8260/traps.c | 16 ++++++++-------- cpu/mpc83xx/interrupts.c | 4 ++-- cpu/mpc83xx/traps.c | 14 +++++++------- cpu/mpc85xx/ether_fcc.c | 6 +++--- cpu/mpc85xx/interrupts.c | 4 ++-- cpu/mpc85xx/traps.c | 14 +++++++------- cpu/mpc8xx/bedbug_860.c | 2 +- cpu/mpc8xx/fec.c | 18 +++++++++--------- cpu/mpc8xx/kgdb.S | 2 +- cpu/mpc8xx/scc.c | 2 +- cpu/mpc8xx/serial.c | 2 +- cpu/mpc8xx/traps.c | 16 ++++++++-------- 31 files changed, 109 insertions(+), 109 deletions(-) (limited to 'cpu') diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c index 36270712e0a..255b3d8b7bc 100644 --- a/cpu/mcf52x2/fec.c +++ b/cpu/mcf52x2/fec.c @@ -53,7 +53,7 @@ #undef ET_DEBUG #undef MII_DEBUG -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(FEC_ENET) +#if defined(CONFIG_CMD_NET) && defined(FEC_ENET) #ifdef CFG_DISCOVER_PHY #include @@ -363,7 +363,7 @@ void eth_halt (void) } -#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) static int phyaddr = -1; /* didn't find a PHY yet */ static uint phytype; @@ -419,7 +419,7 @@ static uint mii_send (uint mii_cmd) #endif return (mii_reply & 0xffff); /* data read from phy */ } -#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ +#endif #if defined(CFG_DISCOVER_PHY) static void mii_discover_phy (void) @@ -485,7 +485,7 @@ static void mii_discover_phy (void) } #endif /* CFG_DISCOVER_PHY */ -#if ((CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII) +#if defined(CONFIG_CMD_MII) && !defined(CONFIG_BITBANGMII) static int mii_init_done = 0; @@ -591,13 +591,13 @@ int mcf52x2_miiphy_write (char *devname, unsigned char addr, return 0; } -#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) */ +#endif #endif /* CFG_CMD_NET, FEC_ENET */ int mcf52x2_miiphy_initialize(bd_t *bis) { -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(FEC_ENET) -#if ((CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII) +#if defined(CONFIG_CMD_NET) && defined(FEC_ENET) +#if defined(CONFIG_CMD_MII) && !defined(CONFIG_BITBANGMII) miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write); #endif #endif diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c index 2921551ff91..6ce0b55b243 100644 --- a/cpu/microblaze/cache.c +++ b/cpu/microblaze/cache.c @@ -25,7 +25,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_CACHE) || defined(CONFIG_CMD_CACHE) +#if defined(CONFIG_CMD_CACHE) int dcache_status (void) { diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c index b97465aee63..3f04b299838 100644 --- a/cpu/microblaze/interrupts.c +++ b/cpu/microblaze/interrupts.c @@ -190,7 +190,7 @@ void interrupt_handler (void) } #endif -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) || defined(CONFIG_CMD_IRQ) +#if defined(CONFIG_CMD_IRQ) #ifdef CFG_INTC_0 int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { @@ -217,4 +217,4 @@ int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) puts ("Undefined interrupt controller\n"); } #endif -#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ +#endif diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c index de13b054712..b69741ae683 100644 --- a/cpu/mips/au1x00_eth.c +++ b/cpu/mips/au1x00_eth.c @@ -63,7 +63,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_CMD_MII) #include #endif @@ -241,7 +241,7 @@ int au1x00_enet_initialize(bd_t *bis){ eth_register(dev); -#if (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_CMD_MII) miiphy_register(dev->name, au1x00_miiphy_read, au1x00_miiphy_write); #endif @@ -249,7 +249,7 @@ int au1x00_enet_initialize(bd_t *bis){ return 1; } -#if (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_CMD_MII) int au1x00_miiphy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short * value) { @@ -306,6 +306,6 @@ int au1x00_miiphy_write(char *devname, unsigned char addr, *mii_control_reg = mii_control; return 0; } -#endif /* CONFIG_COMMANDS & CFG_CMD_MII */ +#endif #endif /* CONFIG_AU1X00 */ diff --git a/cpu/mpc5xx/interrupts.c b/cpu/mpc5xx/interrupts.c index 70803cf36d7..a4f47c74b5d 100644 --- a/cpu/mpc5xx/interrupts.c +++ b/cpu/mpc5xx/interrupts.c @@ -178,7 +178,7 @@ void timer_interrupt_cpu (struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) || defined(CONFIG_CMD_IRQ) +#if defined(CONFIG_CMD_IRQ) /******************************************************************************* * * irqinfo - print information about IRQs @@ -204,4 +204,4 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } -#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ +#endif diff --git a/cpu/mpc5xx/traps.c b/cpu/mpc5xx/traps.c index 26a253f823e..d22b89a1f52 100644 --- a/cpu/mpc5xx/traps.c +++ b/cpu/mpc5xx/traps.c @@ -36,11 +36,11 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) +#if defined(CONFIG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -131,7 +131,7 @@ void MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -165,7 +165,7 @@ void MachineCheckException(struct pt_regs *regs) */ void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -179,7 +179,7 @@ void AlignmentException(struct pt_regs *regs) */ void ProgramCheckException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -193,7 +193,7 @@ void ProgramCheckException(struct pt_regs *regs) */ void SoftEmuException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -208,7 +208,7 @@ void SoftEmuException(struct pt_regs *regs) */ void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -224,7 +224,7 @@ void DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) +#if defined(CONFIG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c index 7ec3594dc0c..bc6201ec0ac 100644 --- a/cpu/mpc5xxx/cpu_init.c +++ b/cpu/mpc5xxx/cpu_init.c @@ -198,7 +198,7 @@ int cpu_init_r (void) /* route critical ints to normal ints */ *(vu_long *)MPC5XXX_ICTL_EXT |= 0x00000001; -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(CONFIG_MPC5xxx_FEC) +#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC) /* load FEC microcode */ loadtask(0, 2); #endif diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c index 5f9d6adca3d..727f954e3ae 100644 --- a/cpu/mpc5xxx/fec.c +++ b/cpu/mpc5xxx/fec.c @@ -18,10 +18,10 @@ DECLARE_GLOBAL_DATA_PTR; /* #define DEBUG 0x28 */ -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(CONFIG_NET_MULTI) && \ +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ defined(CONFIG_MPC5xxx_FEC) -#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) +#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) #error "CONFIG_MII has to be defined!" #endif @@ -917,7 +917,7 @@ int mpc5xxx_fec_initialize(bd_t * bis) sprintf(dev->name, "FEC ETHERNET"); eth_register(dev); -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register (dev->name, fec5xxx_miiphy_read, fec5xxx_miiphy_write); #endif diff --git a/cpu/mpc5xxx/interrupts.c b/cpu/mpc5xxx/interrupts.c index 4b414eae311..8816dd1e2dc 100644 --- a/cpu/mpc5xxx/interrupts.c +++ b/cpu/mpc5xxx/interrupts.c @@ -310,7 +310,7 @@ void irq_free_handler(int irq) /****************************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) || defined(CONFIG_CMD_IRQ) +#if defined(CONFIG_CMD_IRQ) void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) { int irq, re_enable; diff --git a/cpu/mpc5xxx/traps.c b/cpu/mpc5xxx/traps.c index 8810a764ac4..daa1ec6b589 100644 --- a/cpu/mpc5xxx/traps.c +++ b/cpu/mpc5xxx/traps.c @@ -37,7 +37,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -123,7 +123,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -158,7 +158,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -170,7 +170,7 @@ AlignmentException(struct pt_regs *regs) void ProgramCheckException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -182,7 +182,7 @@ ProgramCheckException(struct pt_regs *regs) void SoftEmuException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -195,7 +195,7 @@ SoftEmuException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -204,7 +204,7 @@ UnknownException(struct pt_regs *regs) _exception(0, regs); } -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) +#if defined(CONFIG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -214,7 +214,7 @@ DebugException(struct pt_regs *regs) printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) +#if defined(CONFIG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc8220/cpu_init.c b/cpu/mpc8220/cpu_init.c index db47a4b5f29..0daac5bbd4b 100644 --- a/cpu/mpc8220/cpu_init.c +++ b/cpu/mpc8220/cpu_init.c @@ -128,7 +128,7 @@ int cpu_init_r (void) /* route critical ints to normal ints */ *(vu_long *) 0xf0000710 |= 0x00000001; -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(CONFIG_MPC8220_FEC) +#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC8220_FEC) /* load FEC microcode */ loadtask (0, 2); #endif diff --git a/cpu/mpc8220/fec.c b/cpu/mpc8220/fec.c index 144d623bfc3..992e0ffbc46 100644 --- a/cpu/mpc8220/fec.c +++ b/cpu/mpc8220/fec.c @@ -15,10 +15,10 @@ #include "fec.h" #undef DEBUG -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(CONFIG_NET_MULTI) && \ +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ defined(CONFIG_MPC8220_FEC) -#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) +#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) #error "CONFIG_MII has to be defined!" #endif @@ -847,7 +847,7 @@ int mpc8220_fec_initialize (bd_t * bis) sprintf (dev->name, "FEC ETHERNET"); eth_register (dev); -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register (dev->name, fec8220_miiphy_read, fec8220_miiphy_write); #endif diff --git a/cpu/mpc8220/traps.c b/cpu/mpc8220/traps.c index e921cdde3a8..89cca1d2237 100644 --- a/cpu/mpc8220/traps.c +++ b/cpu/mpc8220/traps.c @@ -37,7 +37,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler) (struct pt_regs *) = 0; #endif @@ -118,7 +118,7 @@ void MachineCheckException (struct pt_regs *regs) regs->nip = fixup; return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; @@ -152,7 +152,7 @@ void MachineCheckException (struct pt_regs *regs) void AlignmentException (struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; @@ -164,7 +164,7 @@ void AlignmentException (struct pt_regs *regs) void ProgramCheckException (struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; @@ -176,7 +176,7 @@ void ProgramCheckException (struct pt_regs *regs) void SoftEmuException (struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; @@ -189,7 +189,7 @@ void SoftEmuException (struct pt_regs *regs) void UnknownException (struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; @@ -199,7 +199,7 @@ void UnknownException (struct pt_regs *regs) _exception (0, regs); } -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) +#if defined(CONFIG_CMD_BEDBUG) extern void do_bedbug_breakpoint (struct pt_regs *); #endif @@ -208,7 +208,7 @@ void DebugException (struct pt_regs *regs) printf ("Debugger trap at @ %lx\n", regs->nip); show_regs (regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) +#if defined(CONFIG_CMD_BEDBUG) do_bedbug_breakpoint (regs); #endif } diff --git a/cpu/mpc824x/traps.c b/cpu/mpc824x/traps.c index e93cffbf517..0a7243020b6 100644 --- a/cpu/mpc824x/traps.c +++ b/cpu/mpc824x/traps.c @@ -175,7 +175,7 @@ UnknownException(struct pt_regs *regs) _exception(0, regs); } -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) +#if defined(CONFIG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -185,7 +185,7 @@ DebugException(struct pt_regs *regs) printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) +#if defined(CONFIG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc8260/bedbug_603e.c b/cpu/mpc8260/bedbug_603e.c index 7ca193d46c4..f1be485e8eb 100644 --- a/cpu/mpc8260/bedbug_603e.c +++ b/cpu/mpc8260/bedbug_603e.c @@ -10,7 +10,7 @@ #include #include -#if ((CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG)) \ +#if defined(CONFIG_CMD_BEDBUG) \ && (defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260)) #define MAX_BREAK_POINTS 1 diff --git a/cpu/mpc8260/ether_fcc.c b/cpu/mpc8260/ether_fcc.c index 51d0de2c00e..08d2847b96b 100644 --- a/cpu/mpc8260/ether_fcc.c +++ b/cpu/mpc8260/ether_fcc.c @@ -47,13 +47,13 @@ #include #include -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) #include #endif DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_ETHER_ON_FCC) && ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && \ +#if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) && \ defined(CONFIG_NET_MULTI) static struct ether_fcc_info_s @@ -393,7 +393,7 @@ int fec_initialize(bd_t *bis) eth_register(dev); -#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) \ +#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \ && defined(CONFIG_BITBANGMII) miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write); diff --git a/cpu/mpc8260/ether_scc.c b/cpu/mpc8260/ether_scc.c index ec682ec25ec..b9ae0826687 100644 --- a/cpu/mpc8260/ether_scc.c +++ b/cpu/mpc8260/ether_scc.c @@ -36,7 +36,7 @@ #include #include -#if defined(CONFIG_ETHER_ON_SCC) && ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) +#if defined(CONFIG_ETHER_ON_SCC) && defined(CONFIG_CMD_NET) #if (CONFIG_ETHER_INDEX == 1) # define PROFF_ENET PROFF_SCC1 diff --git a/cpu/mpc8260/interrupts.c b/cpu/mpc8260/interrupts.c index 6e5ab4c4e64..bf0d4d0d59f 100644 --- a/cpu/mpc8260/interrupts.c +++ b/cpu/mpc8260/interrupts.c @@ -246,7 +246,7 @@ void timer_interrupt_cpu (struct pt_regs *regs) /****************************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) || defined(CONFIG_CMD_IRQ) +#if defined(CONFIG_CMD_IRQ) /* ripped this out of ppc4xx/interrupts.c */ @@ -276,4 +276,4 @@ do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) enable_interrupts (); } -#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ +#endif diff --git a/cpu/mpc8260/kgdb.S b/cpu/mpc8260/kgdb.S index fc1ebe2a39b..5a7d0b7b2bb 100644 --- a/cpu/mpc8260/kgdb.S +++ b/cpu/mpc8260/kgdb.S @@ -34,7 +34,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) /* * cache flushing routines for kgdb diff --git a/cpu/mpc8260/traps.c b/cpu/mpc8260/traps.c index 07be0fac6de..b5d416c9741 100644 --- a/cpu/mpc8260/traps.c +++ b/cpu/mpc8260/traps.c @@ -37,7 +37,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -150,7 +150,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -186,7 +186,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -198,7 +198,7 @@ AlignmentException(struct pt_regs *regs) void ProgramCheckException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -210,7 +210,7 @@ ProgramCheckException(struct pt_regs *regs) void SoftEmuException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -223,7 +223,7 @@ SoftEmuException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -232,7 +232,7 @@ UnknownException(struct pt_regs *regs) _exception(0, regs); } -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) +#if defined(CONFIG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -242,7 +242,7 @@ DebugException(struct pt_regs *regs) printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) +#if defined(CONFIG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc83xx/interrupts.c b/cpu/mpc83xx/interrupts.c index 26040663f9a..98ed21ccfa6 100644 --- a/cpu/mpc83xx/interrupts.c +++ b/cpu/mpc83xx/interrupts.c @@ -81,7 +81,7 @@ void timer_interrupt_cpu (struct pt_regs *regs) } -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) || defined(CONFIG_CMD_IRQ) +#if defined(CONFIG_CMD_IRQ) /* ripped this out of ppc4xx/interrupts.c */ @@ -94,4 +94,4 @@ do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { } -#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ +#endif diff --git a/cpu/mpc83xx/traps.c b/cpu/mpc83xx/traps.c index 83dcec36e7c..dfd6c038642 100644 --- a/cpu/mpc83xx/traps.c +++ b/cpu/mpc83xx/traps.c @@ -140,7 +140,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -176,7 +176,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -188,7 +188,7 @@ AlignmentException(struct pt_regs *regs) void ProgramCheckException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -200,7 +200,7 @@ ProgramCheckException(struct pt_regs *regs) void SoftEmuException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -213,7 +213,7 @@ SoftEmuException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -222,7 +222,7 @@ UnknownException(struct pt_regs *regs) _exception(0, regs); } -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) +#if defined(CONFIG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -231,7 +231,7 @@ DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) +#if defined(CONFIG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c index ec3990cb8d8..4448cc3b8f5 100644 --- a/cpu/mpc85xx/ether_fcc.c +++ b/cpu/mpc85xx/ether_fcc.c @@ -48,13 +48,13 @@ #include #include -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) #include #endif #if defined(CONFIG_CPM2) -#if defined(CONFIG_ETHER_ON_FCC) && ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && \ +#if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) && \ defined(CONFIG_NET_MULTI) static struct ether_fcc_info_s @@ -458,7 +458,7 @@ int fec_initialize(bd_t *bis) eth_register(dev); -#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) \ +#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \ && defined(CONFIG_BITBANGMII) miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write); diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c index ed15c466674..dc246dca028 100644 --- a/cpu/mpc85xx/interrupts.c +++ b/cpu/mpc85xx/interrupts.c @@ -144,7 +144,7 @@ void set_timer (ulong t) timestamp = t; } -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) || defined(CONFIG_CMD_IRQ) +#if defined(CONFIG_CMD_IRQ) /******************************************************************************* * @@ -159,4 +159,4 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } -#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ +#endif diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c index fc0c0aa5a7c..9cd621c3ac4 100644 --- a/cpu/mpc85xx/traps.c +++ b/cpu/mpc85xx/traps.c @@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -74,7 +74,7 @@ static __inline__ unsigned long get_esr(void) #define ESR_DIZ 0x00400000 #define ESR_U0F 0x00008000 -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) +#if defined(CONFIG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -159,7 +159,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -192,7 +192,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -207,7 +207,7 @@ ProgramCheckException(struct pt_regs *regs) { long esr_val; -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -244,7 +244,7 @@ PITException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -259,7 +259,7 @@ DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) +#if defined(CONFIG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc8xx/bedbug_860.c b/cpu/mpc8xx/bedbug_860.c index 4516f2f48ea..5d523663924 100644 --- a/cpu/mpc8xx/bedbug_860.c +++ b/cpu/mpc8xx/bedbug_860.c @@ -10,7 +10,7 @@ #include #include -#if ((CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG)) && defined(CONFIG_8xx) +#if defined(CONFIG_CMD_BEDBUG) && defined(CONFIG_8xx) #define MAX_BREAK_POINTS 2 diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c index 520953cc82b..10d825f5729 100644 --- a/cpu/mpc8xx/fec.c +++ b/cpu/mpc8xx/fec.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; #undef ET_DEBUG -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && \ +#if defined(CONFIG_CMD_NET) && \ (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)) /* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */ @@ -49,7 +49,7 @@ DECLARE_GLOBAL_DATA_PTR; #if defined(WANT_MII) #include -#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) +#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) #error "CONFIG_MII has to be defined!" #endif @@ -182,7 +182,7 @@ int fec_initialize(bd_t *bis) eth_register(dev); -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register(dev->name, fec8xx_miiphy_read, fec8xx_miiphy_write); #endif @@ -268,7 +268,7 @@ static int fec_recv (struct eth_device *dev) length -= 4; -#if (CONFIG_COMMANDS & CFG_CMD_CDP) || defined(CONFIG_CMD_CDP) +#if defined(CONFIG_CMD_CDP) if ((rx[0] & 1) != 0 && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0 && memcmp ((uchar *) rx, NetCDPAddr, 6) != 0) @@ -608,7 +608,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd) fecp->fec_addr_high = (ea[4] << 8) | (ea[5]); #undef ea -#if (CONFIG_COMMANDS & CFG_CMD_CDP) || defined(CONFIG_CMD_CDP) +#if defined(CONFIG_CMD_CDP) /* * Turn on multicast address hash table */ @@ -787,7 +787,7 @@ static void fec_halt(struct eth_device* dev) efis->initialized = 0; } -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) /* Make MII read/write commands for the FEC. */ @@ -852,7 +852,7 @@ mii_send(uint mii_cmd) #endif return (mii_reply & 0xffff); /* data read from phy */ } -#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ +#endif #if defined(CFG_DISCOVER_PHY) static int mii_discover_phy(struct eth_device *dev) @@ -926,7 +926,7 @@ static int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII) +#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII) /**************************************************************************** * mii_init -- Initialize the MII for MII command without ethernet @@ -1020,6 +1020,6 @@ int fec8xx_miiphy_write(char *devname, unsigned char addr, #endif return 0; } -#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)*/ +#endif #endif /* CFG_CMD_NET, FEC_ENET */ diff --git a/cpu/mpc8xx/kgdb.S b/cpu/mpc8xx/kgdb.S index c12074494bf..d4c77e79668 100644 --- a/cpu/mpc8xx/kgdb.S +++ b/cpu/mpc8xx/kgdb.S @@ -34,7 +34,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) /* * cache flushing routines for kgdb diff --git a/cpu/mpc8xx/scc.c b/cpu/mpc8xx/scc.c index 0aa597666b9..a0ec5d78706 100644 --- a/cpu/mpc8xx/scc.c +++ b/cpu/mpc8xx/scc.c @@ -38,7 +38,7 @@ #include #include -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(SCC_ENET) +#if defined(CONFIG_CMD_NET) && defined(SCC_ENET) /* Ethernet Transmit and Receive Buffers */ #define DBUF_LENGTH 1520 diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c index 62af1295336..6e08b53525b 100644 --- a/cpu/mpc8xx/serial.c +++ b/cpu/mpc8xx/serial.c @@ -666,7 +666,7 @@ void enable_putc(void) } #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) void kgdb_serial_init(void) diff --git a/cpu/mpc8xx/traps.c b/cpu/mpc8xx/traps.c index ce955d78b68..e1ec88961ab 100644 --- a/cpu/mpc8xx/traps.c +++ b/cpu/mpc8xx/traps.c @@ -36,11 +36,11 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) +#if defined(CONFIG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -126,7 +126,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -159,7 +159,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -171,7 +171,7 @@ AlignmentException(struct pt_regs *regs) void ProgramCheckException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -183,7 +183,7 @@ ProgramCheckException(struct pt_regs *regs) void SoftEmuException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -196,7 +196,7 @@ SoftEmuException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -210,7 +210,7 @@ DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) || defined(CONFIG_CMD_BEDBUG) +#if defined(CONFIG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } -- cgit v1.3.1 From 068b60a0eb7e73b243ca55399f2a7df76e2c3f3d Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Jul 2007 10:27:39 -0500 Subject: cpu/ rtc/ include/: Remove lingering references to CFG_CMD_* symbols. Signed-off-by: Jon Loeliger --- cpu/74xx_7xx/kgdb.S | 2 +- cpu/i386/serial.c | 2 +- cpu/mcf52x2/fec.c | 2 +- cpu/mpc5xxx/ide.c | 4 ++-- cpu/mpc8260/ether_fcc.c | 2 +- cpu/mpc8260/ether_scc.c | 2 +- cpu/mpc8260/kgdb.S | 2 +- cpu/mpc85xx/ether_fcc.c | 2 +- cpu/mpc8xx/fec.c | 2 +- cpu/mpc8xx/kgdb.S | 2 +- cpu/mpc8xx/scc.c | 2 +- cpu/mpc8xx/serial.c | 2 +- cpu/ppc4xx/dcr.S | 2 +- cpu/ppc4xx/kgdb.S | 2 +- cpu/ppc4xx/serial.c | 2 +- include/_exports.h | 2 +- include/exports.h | 2 +- include/pcmcia.h | 2 +- rtc/bf5xx_rtc.c | 2 +- rtc/date.c | 2 +- rtc/ds1307.c | 2 +- rtc/ds1337.c | 2 +- rtc/ds1374.c | 2 +- rtc/ds1556.c | 2 +- rtc/ds164x.c | 2 +- rtc/ds174x.c | 2 +- rtc/m41t11.c | 2 +- rtc/m48t35ax.c | 2 +- rtc/max6900.c | 2 +- rtc/mc146818.c | 2 +- rtc/mpc5xxx.c | 2 +- rtc/mpc8xx.c | 4 +--- rtc/pcf8563.c | 2 +- rtc/s3c24x0_rtc.c | 4 +--- 34 files changed, 35 insertions(+), 39 deletions(-) (limited to 'cpu') diff --git a/cpu/74xx_7xx/kgdb.S b/cpu/74xx_7xx/kgdb.S index cd8869c2006..4f231228c22 100644 --- a/cpu/74xx_7xx/kgdb.S +++ b/cpu/74xx_7xx/kgdb.S @@ -74,4 +74,4 @@ kgdb_flush_cache_range: SYNC blr -#endif /* CFG_CMD_KGDB */ +#endif diff --git a/cpu/i386/serial.c b/cpu/i386/serial.c index 4933d23fd41..baf35e53d57 100644 --- a/cpu/i386/serial.c +++ b/cpu/i386/serial.c @@ -500,4 +500,4 @@ void kgdb_interruptible(int yes) return; } #endif /* (CONFIG_KGDB_SER_INDEX & 2) */ -#endif /* CFG_CMD_KGDB */ +#endif diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c index 255b3d8b7bc..ef9c7984ca3 100644 --- a/cpu/mcf52x2/fec.c +++ b/cpu/mcf52x2/fec.c @@ -592,7 +592,7 @@ int mcf52x2_miiphy_write (char *devname, unsigned char addr, return 0; } #endif -#endif /* CFG_CMD_NET, FEC_ENET */ +#endif int mcf52x2_miiphy_initialize(bd_t *bis) { diff --git a/cpu/mpc5xxx/ide.c b/cpu/mpc5xxx/ide.c index 29b99f6b15d..087ddac109d 100644 --- a/cpu/mpc5xxx/ide.c +++ b/cpu/mpc5xxx/ide.c @@ -24,7 +24,7 @@ */ #include -#ifdef CFG_CMD_IDE +#if defined(CONFIG_CMD_IDE) #include DECLARE_GLOBAL_DATA_PTR; @@ -85,4 +85,4 @@ int ide_preinit (void) return (0); } -#endif /* CFG_CMD_IDE */ +#endif diff --git a/cpu/mpc8260/ether_fcc.c b/cpu/mpc8260/ether_fcc.c index 08d2847b96b..37bf4456ed1 100644 --- a/cpu/mpc8260/ether_fcc.c +++ b/cpu/mpc8260/ether_fcc.c @@ -1187,4 +1187,4 @@ eth_loopback_test (void) #endif /* CONFIG_ETHER_LOOPBACK_TEST */ -#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */ +#endif diff --git a/cpu/mpc8260/ether_scc.c b/cpu/mpc8260/ether_scc.c index b9ae0826687..e56839d3aad 100644 --- a/cpu/mpc8260/ether_scc.c +++ b/cpu/mpc8260/ether_scc.c @@ -353,4 +353,4 @@ void restart(void) } #endif -#endif /* CONFIG_ETHER_ON_SCC && CFG_CMD_NET */ +#endif diff --git a/cpu/mpc8260/kgdb.S b/cpu/mpc8260/kgdb.S index 5a7d0b7b2bb..dae87bb97c7 100644 --- a/cpu/mpc8260/kgdb.S +++ b/cpu/mpc8260/kgdb.S @@ -69,4 +69,4 @@ kgdb_flush_cache_range: SYNC blr -#endif /* CFG_CMD_KGDB */ +#endif diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c index 4448cc3b8f5..5b23a80e1ca 100644 --- a/cpu/mpc85xx/ether_fcc.c +++ b/cpu/mpc85xx/ether_fcc.c @@ -468,6 +468,6 @@ int fec_initialize(bd_t *bis) return 1; } -#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */ +#endif #endif /* CONFIG_CPM2 */ diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c index 10d825f5729..08a3715812d 100644 --- a/cpu/mpc8xx/fec.c +++ b/cpu/mpc8xx/fec.c @@ -1022,4 +1022,4 @@ int fec8xx_miiphy_write(char *devname, unsigned char addr, } #endif -#endif /* CFG_CMD_NET, FEC_ENET */ +#endif diff --git a/cpu/mpc8xx/kgdb.S b/cpu/mpc8xx/kgdb.S index d4c77e79668..812baa3ecd4 100644 --- a/cpu/mpc8xx/kgdb.S +++ b/cpu/mpc8xx/kgdb.S @@ -71,4 +71,4 @@ kgdb_flush_cache_range: SYNC blr -#endif /* CFG_CMD_KGDB */ +#endif diff --git a/cpu/mpc8xx/scc.c b/cpu/mpc8xx/scc.c index a0ec5d78706..744dcdde91f 100644 --- a/cpu/mpc8xx/scc.c +++ b/cpu/mpc8xx/scc.c @@ -567,4 +567,4 @@ void restart (void) (SCC_GSMRL_ENR | SCC_GSMRL_ENT); } #endif -#endif /* CFG_CMD_NET, SCC_ENET */ +#endif diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c index 6e08b53525b..68804cc4394 100644 --- a/cpu/mpc8xx/serial.c +++ b/cpu/mpc8xx/serial.c @@ -723,6 +723,6 @@ kgdb_interruptible (int yes) { return; } -#endif /* CFG_CMD_KGDB */ +#endif #endif /* CONFIG_8xx_CONS_NONE */ diff --git a/cpu/ppc4xx/dcr.S b/cpu/ppc4xx/dcr.S index fe136e0fa29..93465a3b513 100644 --- a/cpu/ppc4xx/dcr.S +++ b/cpu/ppc4xx/dcr.S @@ -195,4 +195,4 @@ set_dcr: blr /* Return to calling function */ .Lfe4: .size set_dcr,.Lfe4-set_dcr /* end set_dcr() */ -#endif /* CONFIG_4xx & CFG_CMD_SETGETDCR */ +#endif diff --git a/cpu/ppc4xx/kgdb.S b/cpu/ppc4xx/kgdb.S index cd12727be3c..8c4bbf2e4de 100644 --- a/cpu/ppc4xx/kgdb.S +++ b/cpu/ppc4xx/kgdb.S @@ -75,4 +75,4 @@ kgdb_flush_cache_range: SYNC blr -#endif /* CFG_CMD_KGDB */ +#endif diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index aefa4cabab6..3f67136be53 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -949,7 +949,7 @@ void kgdb_interruptible (int yes) return; } #endif /* (CONFIG_KGDB_SER_INDEX & 2) */ -#endif /* CFG_CMD_KGDB */ +#endif #if defined(CONFIG_SERIAL_MULTI) diff --git a/include/_exports.h b/include/_exports.h index eeb65f40ae4..a0fbf2aba36 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -18,4 +18,4 @@ EXPORT_FUNC(simple_strtoul) #if defined(CONFIG_CMD_I2C) EXPORT_FUNC(i2c_write) EXPORT_FUNC(i2c_read) -#endif /* CFG_CMD_I2C */ +#endif diff --git a/include/exports.h b/include/exports.h index ad20502a67a..704b1330b89 100644 --- a/include/exports.h +++ b/include/exports.h @@ -26,7 +26,7 @@ void setenv (char *varname, char *varvalue); #if defined(CONFIG_CMD_I2C) int i2c_write (uchar, uint, int , uchar* , int); int i2c_read (uchar, uint, int , uchar* , int); -#endif /* CFG_CMD_I2C */ +#endif void app_startup(char **); diff --git a/include/pcmcia.h b/include/pcmcia.h index c028ab735db..7305805e40c 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -306,7 +306,7 @@ typedef struct { #define CISTPL_IDE_HAS_INDEX 0x20 #define CISTPL_IDE_IOIS16 0x40 -#endif /* CFG_CMD_PCMCIA || CFG_CMD_IDE && (CONFIG_IDE_8xx_PCCARD || CONFIG_IDE_8xx_DIRECT) */ +#endif #ifdef CONFIG_8xx extern u_int *pcmcia_pgcrx[]; diff --git a/rtc/bf5xx_rtc.c b/rtc/bf5xx_rtc.c index 17a19eb4f1d..8856bb9b5f8 100644 --- a/rtc/bf5xx_rtc.c +++ b/rtc/bf5xx_rtc.c @@ -140,4 +140,4 @@ void rtc_get(struct rtc_time *tmp) MIN_TO_SECS(tm_min) + HRS_TO_SECS(tm_hour) + DAYS_TO_SECS(tm_day); to_tm(time_in_sec, tmp); } -#endif /* CONFIG_RTC_BFIN && CFG_CMD_DATE */ +#endif diff --git a/rtc/date.c b/rtc/date.c index d00b1444807..a83a7235ab6 100644 --- a/rtc/date.c +++ b/rtc/date.c @@ -153,4 +153,4 @@ mktime (unsigned int year, unsigned int mon, )*60 + sec; /* finally seconds */ } -#endif /* CFG_CMD_DATE */ +#endif diff --git a/rtc/ds1307.c b/rtc/ds1307.c index a2a86337848..c882d7989a0 100644 --- a/rtc/ds1307.c +++ b/rtc/ds1307.c @@ -201,4 +201,4 @@ static unsigned char bin2bcd (unsigned int n) return (((n / 10) << 4) | (n % 10)); } -#endif /* (CONFIG_RTC_DS1307 || CONFIG_RTC_DS1338) && (CFG_COMMANDS & CFG_CMD_DATE) */ +#endif diff --git a/rtc/ds1337.c b/rtc/ds1337.c index b871d079502..c636ac5948f 100644 --- a/rtc/ds1337.c +++ b/rtc/ds1337.c @@ -188,4 +188,4 @@ static unsigned char bin2bcd (unsigned int n) return (((n / 10) << 4) | (n % 10)); } -#endif /* CONFIG_RTC_DS1337 && (CFG_COMMANDS & CFG_CMD_DATE) */ +#endif diff --git a/rtc/ds1374.c b/rtc/ds1374.c index 6ee7ab4b980..e773dd92615 100644 --- a/rtc/ds1374.c +++ b/rtc/ds1374.c @@ -250,4 +250,4 @@ static void rtc_write_raw (uchar reg, uchar val) { i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); } -#endif /* (CONFIG_RTC_DS1374) && (CFG_COMMANDS & CFG_CMD_DATE) */ +#endif diff --git a/rtc/ds1556.c b/rtc/ds1556.c index 440d43aef3b..4365cfb9813 100644 --- a/rtc/ds1556.c +++ b/rtc/ds1556.c @@ -203,4 +203,4 @@ static unsigned char bin2bcd (unsigned int n) return (((n / 10) << 4) | (n % 10)); } -#endif /* CONFIG_RTC_DS1556 && CFG_CMD_DATE */ +#endif diff --git a/rtc/ds164x.c b/rtc/ds164x.c index e82ca591636..bff22b9a058 100644 --- a/rtc/ds164x.c +++ b/rtc/ds164x.c @@ -197,4 +197,4 @@ static unsigned char bin2bcd (unsigned int n) return (((n / 10) << 4) | (n % 10)); } -#endif /* CONFIG_RTC_DS164x && CFG_CMD_DATE */ +#endif diff --git a/rtc/ds174x.c b/rtc/ds174x.c index e3028e2540b..5f85a68170b 100644 --- a/rtc/ds174x.c +++ b/rtc/ds174x.c @@ -199,4 +199,4 @@ static unsigned char bin2bcd (unsigned int n) return (((n / 10) << 4) | (n % 10)); } -#endif /* CONFIG_RTC_MC146818 && CFG_CMD_DATE */ +#endif diff --git a/rtc/m41t11.c b/rtc/m41t11.c index 1e35b068e61..81da33a31e1 100644 --- a/rtc/m41t11.c +++ b/rtc/m41t11.c @@ -199,4 +199,4 @@ int rtc_recall(int addr, unsigned char* data, int size) return i2c_read( CFG_I2C_RTC_ADDR, REG_CNT+addr, 1, data, size ); } -#endif /* CONFIG_RTC_M41T11 && CFG_I2C_RTC_ADDR && CFG_CMD_DATE */ +#endif diff --git a/rtc/m48t35ax.c b/rtc/m48t35ax.c index 6133b46acd4..0a0ffa8aac1 100644 --- a/rtc/m48t35ax.c +++ b/rtc/m48t35ax.c @@ -163,4 +163,4 @@ static unsigned char bin2bcd (unsigned int n) return (((n / 10) << 4) | (n % 10)); } -#endif /* CONFIG_RTC_M48T35A && CFG_CMD_DATE */ +#endif diff --git a/rtc/max6900.c b/rtc/max6900.c index 63f643c1a71..c75a8e04c24 100644 --- a/rtc/max6900.c +++ b/rtc/max6900.c @@ -128,4 +128,4 @@ void rtc_reset (void) { } -#endif /* CONFIG_RTC_MAX6900 && CFG_CMD_DATE */ +#endif diff --git a/rtc/mc146818.c b/rtc/mc146818.c index bbb6486cf92..ab377ed73e5 100644 --- a/rtc/mc146818.c +++ b/rtc/mc146818.c @@ -175,4 +175,4 @@ static unsigned char bin2bcd (unsigned int n) return (((n / 10) << 4) | (n % 10)); } -#endif /* CONFIG_RTC_MC146818 && CFG_CMD_DATE */ +#endif diff --git a/rtc/mpc5xxx.c b/rtc/mpc5xxx.c index 72f3111957e..216386aba05 100644 --- a/rtc/mpc5xxx.c +++ b/rtc/mpc5xxx.c @@ -137,4 +137,4 @@ void rtc_reset (void) return; /* nothing to do */ } -#endif /* CONFIG_RTC_MPC5200 && CFG_CMD_DATE */ +#endif diff --git a/rtc/mpc8xx.c b/rtc/mpc8xx.c index 716cd53eac4..8d10c0e465e 100644 --- a/rtc/mpc8xx.c +++ b/rtc/mpc8xx.c @@ -70,6 +70,4 @@ void rtc_reset (void) return; /* nothing to do */ } -/* ------------------------------------------------------------------------- */ - -#endif /* CONFIG_RTC_MPC8xx && CFG_CMD_DATE */ +#endif diff --git a/rtc/pcf8563.c b/rtc/pcf8563.c index 5e868367c8c..2d73d5d7ef9 100644 --- a/rtc/pcf8563.c +++ b/rtc/pcf8563.c @@ -141,4 +141,4 @@ static unsigned char bin2bcd (unsigned int n) return (((n / 10) << 4) | (n % 10)); } -#endif /* CONFIG_RTC_PCF8563 && CFG_CMD_DATE */ +#endif diff --git a/rtc/s3c24x0_rtc.c b/rtc/s3c24x0_rtc.c index 902b737410a..7f8b4fad0dd 100644 --- a/rtc/s3c24x0_rtc.c +++ b/rtc/s3c24x0_rtc.c @@ -175,6 +175,4 @@ void rtc_reset (void) rtc->RTCCON &= ~(0x08|0x01); } -/* ------------------------------------------------------------------------- */ - -#endif /* CONFIG_RTC_S3C24X0 && CFG_CMD_DATE */ +#endif -- cgit v1.3.1 From 8993e54b6f397973794f3d6f47d3b3c0c98dd4f6 Mon Sep 17 00:00:00 2001 From: Rafal Jaworowski Date: Fri, 27 Jul 2007 14:43:59 +0200 Subject: [ADS5121] Support for the ADS5121 board The following MPC5121e subsystems are supported: - low-level CPU init - NOR Boot Flash (common CFI driver) - DDR SDRAM - FEC - I2C - Watchdog Signed-off-by: Grzegorz Bernacki Signed-off-by: Rafal Jaworowski Signed-off-by: Jan Wrobel --- MAKEALL | 10 +- Makefile | 7 + board/ads5121/Makefile | 50 +++ board/ads5121/ads5121.c | 188 ++++++++++ board/ads5121/config.mk | 23 ++ board/ads5121/u-boot.lds | 122 +++++++ cpu/mpc512x/Makefile | 46 +++ cpu/mpc512x/config.mk | 25 ++ cpu/mpc512x/cpu.c | 127 +++++++ cpu/mpc512x/cpu_init.c | 87 +++++ cpu/mpc512x/fec.c | 801 ++++++++++++++++++++++++++++++++++++++++++ cpu/mpc512x/fec.h | 224 ++++++++++++ cpu/mpc512x/i2c.c | 431 +++++++++++++++++++++++ cpu/mpc512x/interrupts.c | 61 ++++ cpu/mpc512x/serial.c | 197 +++++++++++ cpu/mpc512x/speed.c | 135 +++++++ cpu/mpc512x/start.S | 780 ++++++++++++++++++++++++++++++++++++++++ cpu/mpc512x/traps.c | 205 +++++++++++ include/asm-ppc/e300.h | 1 + include/asm-ppc/global_data.h | 4 + include/asm-ppc/immap_512x.h | 569 ++++++++++++++++++++++++++++++ include/common.h | 8 +- include/configs/ads5121.h | 410 +++++++++++++++++++++ include/mpc512x.h | 398 +++++++++++++++++++++ net/eth.c | 4 + 25 files changed, 4911 insertions(+), 2 deletions(-) create mode 100644 board/ads5121/Makefile create mode 100644 board/ads5121/ads5121.c create mode 100644 board/ads5121/config.mk create mode 100644 board/ads5121/u-boot.lds create mode 100644 cpu/mpc512x/Makefile create mode 100644 cpu/mpc512x/config.mk create mode 100644 cpu/mpc512x/cpu.c create mode 100644 cpu/mpc512x/cpu_init.c create mode 100644 cpu/mpc512x/fec.c create mode 100644 cpu/mpc512x/fec.h create mode 100644 cpu/mpc512x/i2c.c create mode 100644 cpu/mpc512x/interrupts.c create mode 100644 cpu/mpc512x/serial.c create mode 100644 cpu/mpc512x/speed.c create mode 100644 cpu/mpc512x/start.S create mode 100644 cpu/mpc512x/traps.c create mode 100644 include/asm-ppc/immap_512x.h create mode 100644 include/configs/ads5121.h create mode 100644 include/mpc512x.h (limited to 'cpu') diff --git a/MAKEALL b/MAKEALL index 127faa83a32..2a03b687083 100755 --- a/MAKEALL +++ b/MAKEALL @@ -43,6 +43,14 @@ LIST_5xxx=" \ TQM5200S v38b \ " +######################################################################### +## MPC512x Systems +######################################################################### + +LIST_512x=" \ + ads5121 \ +" + ######################################################################### ## MPC8xx Systems ######################################################################### @@ -365,7 +373,7 @@ do microblaze| \ mips|mips_el| \ nios|nios2| \ - ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \ + ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \ x86|I486) for target in `eval echo '$LIST_'${arg}` do diff --git a/Makefile b/Makefile index 3af9962e678..5b87aad5b9f 100644 --- a/Makefile +++ b/Makefile @@ -641,6 +641,13 @@ motionpro_config: unconfig @$(MKCONFIG) motionpro ppc mpc5xxx motionpro +######################################################################### +## MPC512x Systems +######################################################################### +ads5121_config: unconfig + @$(MKCONFIG) ads5121 ppc mpc512x ads5121 + + ######################################################################### ## MPC8xx Systems ######################################################################### diff --git a/board/ads5121/Makefile b/board/ads5121/Makefile new file mode 100644 index 00000000000..cd8148c43ea --- /dev/null +++ b/board/ads5121/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c new file mode 100644 index 00000000000..0a99a34ac05 --- /dev/null +++ b/board/ads5121/ads5121.c @@ -0,0 +1,188 @@ +/* + * (C) Copyright 2007 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include + +/* Clocks in use */ +#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ + CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ + CLOCK_SCCR1_PSCFIFO_EN | \ + CLOCK_SCCR1_DDR_EN | \ + CLOCK_SCCR1_FEC_EN) + +#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ + CLOCK_SCCR2_SPDIF_EN | \ + CLOCK_SCCR2_I2C_EN) + +#define CSAW_START(start) ((start) & 0xFFFF0000) +#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) + +long int fixed_sdram(void); + +int board_early_init_f (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 lpcaw; + + /* + * Initialize Local Window for the CPLD registers access (CS2 selects + * the CPLD chip) + */ + im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) | + CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE); + im->lpc.cs_cfg[2] = CFG_CS2_CFG; + + /* + * According to MPC5121e RM, configuring local access windows should + * be followed by a dummy read of the config register that was + * modified last and an isync + */ + lpcaw = im->sysconf.lpcs2aw; + __asm__ __volatile__ ("isync"); + + /* + * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control + * + * Without this the flash identification routine fails, as it needs to issue + * write commands in order to establish the device ID. + */ + *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1; + + /* + * Enable clocks + */ + im->clk.sccr[0] = SCCR1_CLOCKS_EN; + im->clk.sccr[1] = SCCR2_CLOCKS_EN; + + return 0; +} + +long int initdram (int board_type) +{ + u32 msize = 0; + + puts ("Initializing\n"); + msize = fixed_sdram (); + puts (" DDR RAM: "); + + return msize; +} + +/* + * fixed sdram init -- the board doesn't use memory modules that have serial presence + * detect or similar mechanism for discovery of the DRAM settings + */ +long int fixed_sdram (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = CFG_DDR_SIZE * 1024 * 1024; + u32 msize_log2 = __ilog2 (msize); + u32 i; + + /* Initialize IO Control */ + im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR; + + /* Initialize DDR Local Window */ + im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000; + im->sysconf.ddrlaw.ar = msize_log2 - 1; + + /* + * According to MPC5121e RM, configuring local access windows should + * be followed by a dummy read of the config register that was + * modified last and an isync + */ + i = im->sysconf.ddrlaw.ar; + __asm__ __volatile__ ("isync"); + + /* Enable DDR */ + im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN; + + /* Initialize DDR Priority Manager */ + im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1; + im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2; + im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG; + im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU; + im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU; + im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU; + im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU; + im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU; + im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML; + im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML; + im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML; + im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML; + im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML; + im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU; + im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU; + im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU; + im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU; + im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU; + im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AU; + im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL; + im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL; + im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL; + im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL; + + /* Initialize MDDRC */ + im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG; + im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0; + im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1; + im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2; + + /* Initialize DDR */ + for (i = 0; i < 10; i++) + im->mddrc.ddr_command = CFG_MICRON_NOP; + + im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; + im->mddrc.ddr_command = CFG_MICRON_EM2; + im->mddrc.ddr_command = CFG_MICRON_EM3; + im->mddrc.ddr_command = CFG_MICRON_EN_DLL; + im->mddrc.ddr_command = CFG_MICRON_RST_DLL; + im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; + im->mddrc.ddr_command = CFG_MICRON_RFSH; + im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT; + im->mddrc.ddr_command = CFG_MICRON_OCD_EXIT; + + for (i = 0; i < 10; i++) + im->mddrc.ddr_command = CFG_MICRON_NOP; + + /* Start MDDRC */ + im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN; + im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN; + + return msize; +} + +int checkboard (void) +{ + ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00); + uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02); + + printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n", + brd_rev, cpld_rev); + return 0; +} diff --git a/board/ads5121/config.mk b/board/ads5121/config.mk new file mode 100644 index 00000000000..14998f47506 --- /dev/null +++ b/board/ads5121/config.mk @@ -0,0 +1,23 @@ +# +# (C) Copyright 2007 DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFF00000 diff --git a/board/ads5121/u-boot.lds b/board/ads5121/u-boot.lds new file mode 100644 index 00000000000..038d8495531 --- /dev/null +++ b/board/ads5121/u-boot.lds @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2007 DENX Software Engineering. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc512x/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/cpu/mpc512x/Makefile b/cpu/mpc512x/Makefile new file mode 100644 index 00000000000..2be35b2bc62 --- /dev/null +++ b/cpu/mpc512x/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2007 DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/mpc512x/config.mk b/cpu/mpc512x/config.mk new file mode 100644 index 00000000000..8a07c5a3b67 --- /dev/null +++ b/cpu/mpc512x/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2007 DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi + +PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \ + -ffixed-r2 -ffixed-r29 -msoft-float -mcpu=603e diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c new file mode 100644 index 00000000000..3be565ad034 --- /dev/null +++ b/cpu/mpc512x/cpu.c @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * (C) Copyright 2007 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code for the MPC512x family. + * + * Derived from the MPC83xx code. + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkcpu (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + ulong clock = gd->cpu_clk; + u32 pvr = get_pvr (); + u32 spridr = immr->sysconf.spridr; + char buf[32]; + + puts("CPU: "); + + switch (spridr & 0xffff0000) { + case SPR_5121E: + puts ("MPC5121e "); + break; + default: + printf ("Unknown part ID %08x ", spridr & 0xffff0000); + } + printf ("rev. %d.%d, Core ", SVR_MJREV (spridr), SVR_MNREV (spridr)); + + switch (pvr & 0xffff0000) { + case PVR_E300C4: + puts ("e300c4 "); + break; + default: + puts ("unknown "); + } + printf ("at %s MHz, CSB at %3d MHz\n", strmhz(buf, clock), + gd->csb_clk / 1000000); + return 0; +} + + +int +do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong msr; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + /* Interrupts and MMU off */ + __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); + + msr &= ~( MSR_EE | MSR_IR | MSR_DR); + __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); + + /* + * Enable Reset Control Reg - "RSTE" is the magic word that let us go + */ + immap->reset.rpr = 0x52535445; + + /* Verify Reset Control Reg is enabled */ + while (!((immap->reset.rcer) & RCER_CRE)) + ; + + printf ("Resetting the board.\n"); + udelay(200); + + /* Perform reset */ + immap->reset.rcr = RCR_SWHR; + + /* Unreached... */ + return 1; +} + + +/* + * Get timebase clock frequency (like cpu_clk in Hz) + */ +unsigned long get_tbclk (void) +{ + ulong tbclk; + + tbclk = (gd->bus_clk + 3L) / 4L; + + return tbclk; +} + + +#if defined(CONFIG_WATCHDOG) +void watchdog_reset (void) +{ + int re_enable = disable_interrupts (); + + /* Reset watchdog */ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + immr->wdt.swsrr = 0x556c; + immr->wdt.swsrr = 0xaa39; + + if (re_enable) + enable_interrupts (); +} +#endif diff --git a/cpu/mpc512x/cpu_init.c b/cpu/mpc512x/cpu_init.c new file mode 100644 index 00000000000..566e08b0ddd --- /dev/null +++ b/cpu/mpc512x/cpu_init.c @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * (C) Copyright 2007 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Derived from the MPC83xx code. + * + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Set up the memory map, initialize registers, + */ +void cpu_init_f (volatile immap_t * im) +{ + u32 ips_div; + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + + /* system performance tweaking */ + +#ifdef CFG_ACR_PIPE_DEP + /* Arbiter pipeline depth */ + im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | + (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); +#endif + +#ifdef CFG_ACR_RPTCNT + /* Arbiter repeat count */ + im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | + (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT)); +#endif + + /* RSR - Reset Status Register - clear all status */ + gd->reset_status = im->reset.rsr; + im->reset.rsr = ~(RSR_RES); + + /* + * RMR - Reset Mode Register - enable checkstop reset + */ + im->reset.rmr = (RMR_CSRE & (1 << RMR_CSRE_SHIFT)); + + /* Set IPS-CSB divider: IPS = 1/2 CSB */ + ips_div = im->clk.scfr[0]; + ips_div &= ~(SCFR1_IPS_DIV_MASK); + ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT; + im->clk.scfr[0] = ips_div; + + /* + * Enable Time Base/Decrementer + * + * NOTICE: TB needs to be enabled as early as possible in order to + * have udelay() working; if not enabled, usually leads to a hang, like + * during FLASH chip identification etc. + */ + im->sysconf.spcr |= SPCR_TBEN; +} + +int cpu_init_r (void) +{ + return 0; +} diff --git a/cpu/mpc512x/fec.c b/cpu/mpc512x/fec.c new file mode 100644 index 00000000000..f1b7a2563ed --- /dev/null +++ b/cpu/mpc512x/fec.c @@ -0,0 +1,801 @@ +/* + * (C) Copyright 2003-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Derived from the MPC8xx FEC driver. + * Adapted for MPC512x by Grzegorz Bernacki + */ + +#include +#include +#include +#include +#include +#include "fec.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define DEBUG 0 + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_MPC512x_FEC) + +#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) +#error "CONFIG_MII has to be defined!" +#endif + +#if (DEBUG & 0x40) +static uint32 local_crc32(char *string, unsigned int crc_value, int len); +#endif + +int fec512x_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal); +int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data); +int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis); + +/********************************************************************/ +#if (DEBUG & 0x2) +static void mpc512x_fec_phydump (char *devname) +{ + uint16 phyStatus, i; + uint8 phyAddr = CONFIG_PHY_ADDR; + uint8 reg_mask[] = { + /* regs to print: 0...8, 21,27,31 */ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, + }; + + for (i = 0; i < 32; i++) { + if (reg_mask[i]) { + miiphy_read (devname, phyAddr, i, &phyStatus); + printf ("Mii reg %d: 0x%04x\n", i, phyStatus); + } + } +} +#endif + +/********************************************************************/ +static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec) +{ + int ix; + + /* + * Receive BDs init + */ + for (ix = 0; ix < FEC_RBD_NUM; ix++) { + fec->bdBase->rbd[ix].dataPointer = (uint32)&fec->bdBase->recv_frames[ix]; + fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY; + fec->bdBase->rbd[ix].dataLength = 0; + } + + /* + * have the last RBD to close the ring + */ + fec->bdBase->rbd[ix - 1].status |= FEC_RBD_WRAP; + fec->rbdIndex = 0; + + /* + * Trasmit BDs init + */ + for (ix = 0; ix < FEC_TBD_NUM; ix++) { + fec->bdBase->tbd[ix].status = 0; + } + + /* + * Have the last TBD to close the ring + */ + fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP; + + /* + * Initialize some indices + */ + fec->tbdIndex = 0; + fec->usedTbdIndex = 0; + fec->cleanTbdNum = FEC_TBD_NUM; + + return 0; +} + +/********************************************************************/ +static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, volatile FEC_RBD * pRbd) +{ + /* + * Reset buffer descriptor as empty + */ + if ((fec->rbdIndex) == (FEC_RBD_NUM - 1)) + pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY); + else + pRbd->status = FEC_RBD_EMPTY; + + pRbd->dataLength = 0; + + /* + * Increment BD count + */ + fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM; + + /* + * Now, we have an empty RxBD, notify FEC + */ + fec->eth->r_des_active = 0x01000000; /* Descriptor polling active */ +} + +/********************************************************************/ +static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec) +{ + volatile FEC_TBD *pUsedTbd; + +#if (DEBUG & 0x1) + printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n", + fec->cleanTbdNum, fec->usedTbdIndex); +#endif + + /* + * process all the consumed TBDs + */ + while (fec->cleanTbdNum < FEC_TBD_NUM) { + pUsedTbd = &fec->bdBase->tbd[fec->usedTbdIndex]; + if (pUsedTbd->status & FEC_TBD_READY) { +#if (DEBUG & 0x20) + printf ("Cannot clean TBD %d, in use\n", fec->usedTbdIndex); +#endif + return; + } + + /* + * clean this buffer descriptor + */ + if (fec->usedTbdIndex == (FEC_TBD_NUM - 1)) + pUsedTbd->status = FEC_TBD_WRAP; + else + pUsedTbd->status = 0; + + /* + * update some indeces for a correct handling of the TBD ring + */ + fec->cleanTbdNum++; + fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM; + } +} + +/********************************************************************/ +static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, char *mac) +{ + uint8 currByte; /* byte for which to compute the CRC */ + int byte; /* loop - counter */ + int bit; /* loop - counter */ + uint32 crc = 0xffffffff; /* initial value */ + + /* + * The algorithm used is the following: + * we loop on each of the six bytes of the provided address, + * and we compute the CRC by left-shifting the previous + * value by one position, so that each bit in the current + * byte of the address may contribute the calculation. If + * the latter and the MSB in the CRC are different, then + * the CRC value so computed is also ex-ored with the + * "polynomium generator". The current byte of the address + * is also shifted right by one bit at each iteration. + * This is because the CRC generatore in hardware is implemented + * as a shift-register with as many ex-ores as the radixes + * in the polynomium. This suggests that we represent the + * polynomiumm itself as a 32-bit constant. + */ + for (byte = 0; byte < 6; byte++) { + currByte = mac[byte]; + for (bit = 0; bit < 8; bit++) { + if ((currByte & 0x01) ^ (crc & 0x01)) { + crc >>= 1; + crc = crc ^ 0xedb88320; + } else { + crc >>= 1; + } + currByte >>= 1; + } + } + + crc = crc >> 26; + + /* + * Set individual hash table register + */ + if (crc >= 32) { + fec->eth->iaddr1 = (1 << (crc - 32)); + fec->eth->iaddr2 = 0; + } else { + fec->eth->iaddr1 = 0; + fec->eth->iaddr2 = (1 << crc); + } + + /* + * Set physical address + */ + fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3]; + fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808; +} + +/********************************************************************/ +static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) +{ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + +#if (DEBUG & 0x1) + printf ("mpc512x_fec_init... Begin\n"); +#endif + + /* Set interrupt mask register */ + fec->eth->imask = 0x00000000; + + /* Clear FEC-Lite interrupt event register(IEVENT) */ + fec->eth->ievent = 0xffffffff; + + /* Set transmit fifo watermark register(X_WMRK), default = 64 */ + fec->eth->x_wmrk = 0x0; + + /* Set Opcode/Pause Duration Register */ + fec->eth->op_pause = 0x00010020; + + /* Frame length=1518; MII mode */ + fec->eth->r_cntrl = 0x05ee000c; + + /* Half-duplex, heartbeat disabled */ + fec->eth->x_cntrl = 0x00000000; + + /* Enable MIB counters */ + fec->eth->mib_control = 0x0; + + /* Setup recv fifo start and buff size */ + fec->eth->r_fstart = 0x500; + fec->eth->r_buff_size = 0x5e0; + + /* Setup BD base addresses */ + fec->eth->r_des_start = (uint32)fec->bdBase->rbd; + fec->eth->x_des_start = (uint32)fec->bdBase->tbd; + + /* DMA Control */ + fec->eth->dma_control = 0xc0000000; + + /* Enable FEC */ + fec->eth->ecntrl |= 0x00000006; + + /* Initilize addresses and status words of BDs */ + mpc512x_fec_bd_init (fec); + + /* Descriptor polling active */ + fec->eth->r_des_active = 0x01000000; + +#if (DEBUG & 0x1) + printf("mpc512x_fec_init... Done \n"); +#endif + return 1; +} + +/********************************************************************/ +int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis) +{ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */ + int timeout = 1; + uint16 phyStatus; + +#if (DEBUG & 0x1) + printf ("mpc512x_fec_init_phy... Begin\n"); +#endif + + /* + * Clear FEC-Lite interrupt event register(IEVENT) + */ + fec->eth->ievent = 0xffffffff; + + /* + * Set interrupt mask register + */ + fec->eth->imask = 0x00000000; + + if (fec->xcv_type != SEVENWIRE) { + /* + * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock + * and do not drop the Preamble. + */ + fec->eth->mii_speed = (((gd->ipb_clk / 1000000) / 5) + 1) << 1; + + /* + * Reset PHY, then delay 300ns + */ + miiphy_write (dev->name, phyAddr, 0x0, 0x8000); + udelay (1000); + + if (fec->xcv_type == MII10) { + /* + * Force 10Base-T, FDX operation + */ +#if (DEBUG & 0x2) + printf ("Forcing 10 Mbps ethernet link... "); +#endif + miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); + + miiphy_write (dev->name, phyAddr, 0x0, 0x0180); + + timeout = 20; + do { /* wait for link status to go down */ + udelay (10000); + if ((timeout--) == 0) { +#if (DEBUG & 0x2) + printf ("hmmm, should not have waited..."); +#endif + break; + } + miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); +#if (DEBUG & 0x2) + printf ("="); +#endif + } while ((phyStatus & 0x0004)); /* !link up */ + + timeout = 1000; + do { /* wait for link status to come back up */ + udelay (10000); + if ((timeout--) == 0) { + printf ("failed. Link is down.\n"); + break; + } + miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); +#if (DEBUG & 0x2) + printf ("+"); +#endif + } while (!(phyStatus & 0x0004)); /* !link up */ + +#if (DEBUG & 0x2) + printf ("done.\n"); +#endif + } else { /* MII100 */ + /* + * Set the auto-negotiation advertisement register bits + */ + miiphy_write (dev->name, phyAddr, 0x4, 0x01e1); + + /* + * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation + */ + miiphy_write (dev->name, phyAddr, 0x0, 0x1200); + + /* + * Wait for AN completion + */ + timeout = 50000; + do { + udelay (1000); + + if ((timeout--) == 0) { +#if (DEBUG & 0x2) + printf ("PHY auto neg 0 failed...\n"); +#endif + return -1; + } + + if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) != 0) { +#if (DEBUG & 0x2) + printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus); +#endif + return -1; + } + } while (!(phyStatus & 0x0004)); + +#if (DEBUG & 0x2) + printf ("PHY auto neg complete! \n"); +#endif + } + } + +#if (DEBUG & 0x2) + if (fec->xcv_type != SEVENWIRE) + mpc512x_fec_phydump (dev->name); +#endif + +#if (DEBUG & 0x1) + printf ("mpc512x_fec_init_phy... Done \n"); +#endif + return 1; +} + +/********************************************************************/ +static void mpc512x_fec_halt (struct eth_device *dev) +{ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + int counter = 0xffff; + +#if (DEBUG & 0x2) + if (fec->xcv_type != SEVENWIRE) + mpc512x_fec_phydump (dev->name); +#endif + + /* + * mask FEC chip interrupts + */ + fec->eth->imask = 0; + + /* + * issue graceful stop command to the FEC transmitter if necessary + */ + fec->eth->x_cntrl |= 0x00000001; + + /* + * wait for graceful stop to register + */ + while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ; + + /* + * Disable the Ethernet Controller + */ + fec->eth->ecntrl &= 0xfffffffd; + + /* + * Issue a reset command to the FEC chip + */ + fec->eth->ecntrl |= 0x1; + + /* + * wait at least 16 clock cycles + */ + udelay (10); +#if (DEBUG & 0x3) + printf ("Ethernet task stopped\n"); +#endif +} + +/********************************************************************/ + +static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data, + int data_length) +{ + /* + * This routine transmits one frame. This routine only accepts + * 6-byte Ethernet addresses. + */ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + volatile FEC_TBD *pTbd; + +#if (DEBUG & 0x20) + printf("tbd status: 0x%04x\n", fec->tbdBase[fec->tbdIndex].status); +#endif + + /* + * Clear Tx BD ring at first + */ + mpc512x_fec_tbd_scrub (fec); + + /* + * Check for valid length of data. + */ + if ((data_length > 1500) || (data_length <= 0)) { + return -1; + } + + /* + * Check the number of vacant TxBDs. + */ + if (fec->cleanTbdNum < 1) { +#if (DEBUG & 0x20) + printf ("No available TxBDs ...\n"); +#endif + return -1; + } + + /* + * Get the first TxBD to send the mac header + */ + pTbd = &fec->bdBase->tbd[fec->tbdIndex]; + pTbd->dataLength = data_length; + pTbd->dataPointer = (uint32)eth_data; + pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; + fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM; + + /* Activate transmit Buffer Descriptor polling */ + fec->eth->x_des_active = 0x01000000; /* Descriptor polling active */ + +#if (DEBUG & 0x8) + printf ( "+" ); +#endif + + fec->cleanTbdNum -= 1; + + /* + * wait until frame is sent . + */ + while (pTbd->status & FEC_TBD_READY) { + udelay (10); +#if (DEBUG & 0x8) + printf ("TDB status = %04x\n", pTbd->status); +#endif + } + + return 0; +} + + +/********************************************************************/ +static int mpc512x_fec_recv (struct eth_device *dev) +{ + /* + * This command pulls one frame from the card + */ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex]; + unsigned long ievent; + int frame_length, len = 0; + uchar buff[FEC_MAX_PKT_SIZE]; + +#if (DEBUG & 0x1) + printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex); +#endif +#if (DEBUG & 0x8) + printf( "-" ); +#endif + + /* + * Check if any critical events have happened + */ + ievent = fec->eth->ievent; + fec->eth->ievent = ievent; + if (ievent & 0x20060000) { + /* BABT, Rx/Tx FIFO errors */ + mpc512x_fec_halt (dev); + mpc512x_fec_init (dev, NULL); + return 0; + } + if (ievent & 0x80000000) { + /* Heartbeat error */ + fec->eth->x_cntrl |= 0x00000001; + } + if (ievent & 0x10000000) { + /* Graceful stop complete */ + if (fec->eth->x_cntrl & 0x00000001) { + mpc512x_fec_halt (dev); + fec->eth->x_cntrl &= ~0x00000001; + mpc512x_fec_init (dev, NULL); + } + } + + if (!(pRbd->status & FEC_RBD_EMPTY)) { + if ((pRbd->status & FEC_RBD_LAST) && + !(pRbd->status & FEC_RBD_ERR) && + ((pRbd->dataLength - 4) > 14)) { + + /* + * Get buffer size + */ + frame_length = pRbd->dataLength - 4; + +#if (DEBUG & 0x20) + { + int i; + printf ("recv data hdr:"); + for (i = 0; i < 14; i++) + printf ("%x ", *((uint8*)pRbd->dataPointer + i)); + printf("\n"); + } +#endif + + /* + * Fill the buffer and pass it to upper layers + */ + memcpy (buff, (void*)pRbd->dataPointer, frame_length); + NetReceive ((uchar*)buff, frame_length); + len = frame_length; + } + + /* + * Reset buffer descriptor as empty + */ + mpc512x_fec_rbd_clean (fec, pRbd); + } + + /* Try to fill Buffer Descriptors */ + fec->eth->r_des_active = 0x01000000; /* Descriptor polling active */ + return len; +} + +/********************************************************************/ +int mpc512x_fec_initialize (bd_t * bis) +{ + + immap_t *im = (immap_t*) CFG_IMMR; + mpc512x_fec_priv *fec; + struct eth_device *dev; + int i; + char *tmp, *end, env_enetaddr[6]; + uint32 *reg; + void * bd; + + fec = (mpc512x_fec_priv *) malloc (sizeof(*fec)); + dev = (struct eth_device *) malloc (sizeof(*dev)); + memset (dev, 0, sizeof *dev); + + fec->eth = (ethernet_regs *) MPC512X_FEC; + +# ifndef CONFIG_FEC_10MBIT + fec->xcv_type = MII100; +# else + fec->xcv_type = MII10; +# endif + dev->priv = (void *)fec; + dev->iobase = MPC512X_FEC; + dev->init = mpc512x_fec_init; + dev->halt = mpc512x_fec_halt; + dev->send = mpc512x_fec_send; + dev->recv = mpc512x_fec_recv; + + sprintf (dev->name, "FEC ETHERNET"); + eth_register (dev); + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_register (dev->name, + fec512x_miiphy_read, fec512x_miiphy_write); +#endif + + /* + * Initialize I\O pins + */ + reg = (uint32 *) &(im->io_ctrl.regs[PSC0_0_IDX]); + + for (i = 0; i < 15; i++) + reg[i] = IOCTRL_MUX_FEC | 0x00000001; + + im->io_ctrl.regs[SPDIF_TXCLOCK_IDX] = IOCTRL_MUX_FEC | 0x00000001; + im->io_ctrl.regs[SPDIF_TX_IDX] = IOCTRL_MUX_FEC | 0x00000001; + im->io_ctrl.regs[SPDIF_RX_IDX] = IOCTRL_MUX_FEC | 0x00000001; + + /* Clean up space FEC's MIB and FIFO RAM ...*/ + memset ((void *) MPC512X_FEC + 0x200, 0x00, 0x400); + + /* + * Malloc space for BDs (must be quad word-aligned) + * this pointer is lost, so cannot be freed + */ + bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f); + fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0); + memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f); + + /* + * Set interrupt mask register + */ + fec->eth->imask = 0x00000000; + + /* + * Clear FEC-Lite interrupt event register(IEVENT) + */ + fec->eth->ievent = 0xffffffff; + + /* + * Try to set the mac address now. The fec mac address is + * a garbage after reset. When not using fec for booting + * the Linux fec driver will try to work with this garbage. + */ + tmp = getenv ("ethaddr"); + if (tmp) { + for (i=0; i<6; i++) { + env_enetaddr[i] = tmp ? simple_strtoul (tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + mpc512x_fec_set_hwaddr (fec, env_enetaddr); + fec->eth->gaddr1 = 0x00000000; + fec->eth->gaddr2 = 0x00000000; + } + + mpc512x_fec_init_phy (dev, bis); + + return 1; +} + +/* MII-interface related functions */ +/********************************************************************/ +int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal) +{ + ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC; + uint32 reg; /* convenient holder for the PHY register */ + uint32 phy; /* convenient holder for the PHY */ + int timeout = 0xffff; + + /* + * reading from any PHY's register is done by properly + * programming the FEC's MII data register. + */ + reg = regAddr << FEC_MII_DATA_RA_SHIFT; + phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + + eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg); + + /* + * wait for the related interrupt + */ + while ((timeout--) && (!(eth->ievent & 0x00800000))) ; + + if (timeout == 0) { +#if (DEBUG & 0x2) + printf ("Read MDIO failed...\n"); +#endif + return -1; + } + + /* + * clear mii interrupt bit + */ + eth->ievent = 0x00800000; + + /* + * it's now safe to read the PHY's register + */ + *retVal = (uint16) eth->mii_data; + + return 0; +} + +/********************************************************************/ +int fec512x_miiphy_write (char *devname, uint8 phyAddr, uint8 regAddr, uint16 data) +{ + ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC; + uint32 reg; /* convenient holder for the PHY register */ + uint32 phy; /* convenient holder for the PHY */ + int timeout = 0xffff; + + reg = regAddr << FEC_MII_DATA_RA_SHIFT; + phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + + eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | + FEC_MII_DATA_TA | phy | reg | data); + + /* + * wait for the MII interrupt + */ + while ((timeout--) && (!(eth->ievent & 0x00800000))) ; + + if (timeout == 0) { +#if (DEBUG & 0x2) + printf ("Write MDIO failed...\n"); +#endif + return -1; + } + + /* + * clear MII interrupt bit + */ + eth->ievent = 0x00800000; + + return 0; +} + +#if (DEBUG & 0x40) +static uint32 local_crc32 (char *string, unsigned int crc_value, int len) +{ + int i; + char c; + unsigned int crc, count; + + /* + * crc32 algorithm + */ + /* + * crc = 0xffffffff; * The initialized value should be 0xffffffff + */ + crc = crc_value; + + for (i = len; --i >= 0;) { + c = *string++; + for (count = 0; count < 8; count++) { + if ((c & 0x01) ^ (crc & 0x01)) { + crc >>= 1; + crc = crc ^ 0xedb88320; + } else { + crc >>= 1; + } + c >>= 1; + } + } + + /* + * In big endian system, do byte swaping for crc value + */ + /**/ return crc; +} +#endif /* DEBUG */ + +#endif /* CONFIG_MPC512x_FEC */ diff --git a/cpu/mpc512x/fec.h b/cpu/mpc512x/fec.h new file mode 100644 index 00000000000..71459197a51 --- /dev/null +++ b/cpu/mpc512x/fec.h @@ -0,0 +1,224 @@ +/* + * (C) Copyright 2003 - 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Derived from the MPC8xx driver's header file. + */ + +#ifndef __MPC512X_FEC_H +#define __MPC512X_FEC_H + +#include +#include + +typedef unsigned long uint32; +typedef unsigned short uint16; +typedef unsigned char uint8; + +typedef struct ethernet_register_set { + +/* [10:2]addr = 00 */ + +/* Control and status Registers (offset 000-1FF) */ + + volatile uint32 fec_id; /* MBAR_ETH + 0x000 */ + volatile uint32 ievent; /* MBAR_ETH + 0x004 */ + volatile uint32 imask; /* MBAR_ETH + 0x008 */ + + volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */ + volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */ + volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */ + + volatile uint32 RES1[3]; /* MBAR_ETH + 0x018-020 */ + volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */ + + volatile uint32 RES2[6]; /* MBAR_ETH + 0x028-03C */ + volatile uint32 mii_data; /* MBAR_ETH + 0x040 */ + volatile uint32 mii_speed; /* MBAR_ETH + 0x044 */ + + volatile uint32 RES3[7]; /* MBAR_ETH + 0x048-060 */ + volatile uint32 mib_control; /* MBAR_ETH + 0x064 */ + + volatile uint32 RES4[7]; /* MBAR_ETH + 0x068-80 */ + volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */ + volatile uint32 r_hash; /* MBAR_ETH + 0x088 */ + + volatile uint32 RES5[14]; /* MBAR_ETH + 0x08c-0C0 */ + volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */ + + volatile uint32 RES6[7]; /* MBAR_ETH + 0x0C8-0E0 */ + volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */ + volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */ + volatile uint32 op_pause; /* MBAR_ETH + 0x0EC */ + + volatile uint32 RES7[10]; /* MBAR_ETH + 0x0F0-114 */ + volatile uint32 iaddr1; /* MBAR_ETH + 0x118 */ + volatile uint32 iaddr2; /* MBAR_ETH + 0x11C */ + volatile uint32 gaddr1; /* MBAR_ETH + 0x120 */ + volatile uint32 gaddr2; /* MBAR_ETH + 0x124 */ + + volatile uint32 RES8[6]; /* MBAR_ETH + 0x128-13C */ + volatile uint32 fifo_id; /* MBAR_ETH + 0x140 */ + volatile uint32 x_wmrk; /* MBAR_ETH + 0x144 */ + volatile uint32 RES9[1]; /* MBAR_ETH + 0x148 */ + volatile uint32 r_bound; /* MBAR_ETH + 0x14C */ + volatile uint32 r_fstart; /* MBAR_ETH + 0x150 */ + + volatile uint32 RES10[11]; /* MBAR_ETH + 0x154-17C */ + volatile uint32 r_des_start; /* MBAR_ETH + 0x180 */ + volatile uint32 x_des_start; /* MBAR_ETH + 0x184 */ + volatile uint32 r_buff_size; /* MBAR_ETH + 0x188 */ + volatile uint32 RES11[26]; /* MBAR_ETH + 0x18C-1F0 */ + volatile uint32 dma_control; /* MBAR_ETH + 0x1F4 */ + volatile uint32 RES12[2]; /* MBAR_ETH + 0x1F8-1FC */ + +/* MIB COUNTERS (Offset 200-2FF) */ + + volatile uint32 rmon_t_drop; /* MBAR_ETH + 0x200 */ + volatile uint32 rmon_t_packets; /* MBAR_ETH + 0x204 */ + volatile uint32 rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */ + volatile uint32 rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */ + volatile uint32 rmon_t_crc_align; /* MBAR_ETH + 0x210 */ + volatile uint32 rmon_t_undersize; /* MBAR_ETH + 0x214 */ + volatile uint32 rmon_t_oversize; /* MBAR_ETH + 0x218 */ + volatile uint32 rmon_t_frag; /* MBAR_ETH + 0x21C */ + volatile uint32 rmon_t_jab; /* MBAR_ETH + 0x220 */ + volatile uint32 rmon_t_col; /* MBAR_ETH + 0x224 */ + volatile uint32 rmon_t_p64; /* MBAR_ETH + 0x228 */ + volatile uint32 rmon_t_p65to127; /* MBAR_ETH + 0x22C */ + volatile uint32 rmon_t_p128to255; /* MBAR_ETH + 0x230 */ + volatile uint32 rmon_t_p256to511; /* MBAR_ETH + 0x234 */ + volatile uint32 rmon_t_p512to1023; /* MBAR_ETH + 0x238 */ + volatile uint32 rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */ + volatile uint32 rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */ + volatile uint32 rmon_t_octets; /* MBAR_ETH + 0x244 */ + volatile uint32 ieee_t_drop; /* MBAR_ETH + 0x248 */ + volatile uint32 ieee_t_frame_ok; /* MBAR_ETH + 0x24C */ + volatile uint32 ieee_t_1col; /* MBAR_ETH + 0x250 */ + volatile uint32 ieee_t_mcol; /* MBAR_ETH + 0x254 */ + volatile uint32 ieee_t_def; /* MBAR_ETH + 0x258 */ + volatile uint32 ieee_t_lcol; /* MBAR_ETH + 0x25C */ + volatile uint32 ieee_t_excol; /* MBAR_ETH + 0x260 */ + volatile uint32 ieee_t_macerr; /* MBAR_ETH + 0x264 */ + volatile uint32 ieee_t_cserr; /* MBAR_ETH + 0x268 */ + volatile uint32 ieee_t_sqe; /* MBAR_ETH + 0x26C */ + volatile uint32 t_fdxfc; /* MBAR_ETH + 0x270 */ + volatile uint32 ieee_t_octets_ok; /* MBAR_ETH + 0x274 */ + + volatile uint32 RES13[2]; /* MBAR_ETH + 0x278-27C */ + volatile uint32 rmon_r_drop; /* MBAR_ETH + 0x280 */ + volatile uint32 rmon_r_packets; /* MBAR_ETH + 0x284 */ + volatile uint32 rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */ + volatile uint32 rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */ + volatile uint32 rmon_r_crc_align; /* MBAR_ETH + 0x290 */ + volatile uint32 rmon_r_undersize; /* MBAR_ETH + 0x294 */ + volatile uint32 rmon_r_oversize; /* MBAR_ETH + 0x298 */ + volatile uint32 rmon_r_frag; /* MBAR_ETH + 0x29C */ + volatile uint32 rmon_r_jab; /* MBAR_ETH + 0x2A0 */ + + volatile uint32 rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */ + + volatile uint32 rmon_r_p64; /* MBAR_ETH + 0x2A8 */ + volatile uint32 rmon_r_p65to127; /* MBAR_ETH + 0x2AC */ + volatile uint32 rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */ + volatile uint32 rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */ + volatile uint32 rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */ + volatile uint32 rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */ + volatile uint32 rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */ + volatile uint32 rmon_r_octets; /* MBAR_ETH + 0x2C4 */ + volatile uint32 ieee_r_drop; /* MBAR_ETH + 0x2C8 */ + volatile uint32 ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */ + volatile uint32 ieee_r_crc; /* MBAR_ETH + 0x2D0 */ + volatile uint32 ieee_r_align; /* MBAR_ETH + 0x2D4 */ + volatile uint32 r_macerr; /* MBAR_ETH + 0x2D8 */ + volatile uint32 r_fdxfc; /* MBAR_ETH + 0x2DC */ + volatile uint32 ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */ + + volatile uint32 RES14[6]; /* MBAR_ETH + 0x2E4-2FC */ + + volatile uint32 RES15[64]; /* MBAR_ETH + 0x300-3FF */ +} ethernet_regs; + +/* Receive & Transmit Buffer Descriptor definitions */ +typedef struct BufferDescriptor { + uint16 status; + uint16 dataLength; + uint32 dataPointer; +} FEC_RBD; + +typedef struct { + uint16 status; + uint16 dataLength; + uint32 dataPointer; +} FEC_TBD; + +/* private structure */ +typedef enum { + SEVENWIRE, /* 7-wire */ + MII10, /* MII 10Mbps */ + MII100 /* MII 100Mbps */ +} xceiver_type; + +/* BD Numer definitions */ +#define FEC_TBD_NUM 48 /* The user can adjust this value */ +#define FEC_RBD_NUM 32 /* The user can adjust this value */ + +/* packet size limit */ +#define FEC_MAX_PKT_SIZE 1536 + +typedef struct { + uint8 frame[FEC_MAX_PKT_SIZE]; +} mpc512x_frame; + +typedef struct { + FEC_RBD rbd[FEC_RBD_NUM]; /* RBD ring */ + FEC_TBD tbd[FEC_TBD_NUM]; /* TBD ring */ + mpc512x_frame recv_frames[FEC_RBD_NUM]; /* receive buff */ +} mpc512x_buff_descs; + +typedef struct { + ethernet_regs *eth; + xceiver_type xcv_type; /* transceiver type */ + mpc512x_buff_descs *bdBase; /* BD rings and recv buffer */ + uint16 rbdIndex; /* next receive BD to read */ + uint16 tbdIndex; /* next transmit BD to send */ + uint16 usedTbdIndex; /* next transmit BD to clean */ + uint16 cleanTbdNum; /* the number of available transmit BDs */ +} mpc512x_fec_priv; + +/* RBD bits definitions */ +#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */ +#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */ +#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */ +#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */ +#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */ +#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */ +#define FEC_RBD_LG 0x0020 /* Frame length violation */ +#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */ +#define FEC_RBD_SH 0x0008 /* Short frame */ +#define FEC_RBD_CR 0x0004 /* CRC error */ +#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */ +#define FEC_RBD_TR 0x0001 /* Frame is truncated */ +#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \ + FEC_RBD_OV | FEC_RBD_TR) + +/* TBD bits definitions */ +#define FEC_TBD_READY 0x8000 /* Buffer is ready */ +#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */ +#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */ +#define FEC_TBD_TC 0x0400 /* Transmit the CRC */ +#define FEC_TBD_ABC 0x0200 /* Append bad CRC */ + +/* MII-related definitios */ +#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ +#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ +#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ +#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ +#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ +#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */ +#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ + +#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ +#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ + +#endif /* __MPC512X_FEC_H */ diff --git a/cpu/mpc512x/i2c.c b/cpu/mpc512x/i2c.c new file mode 100644 index 00000000000..00e28d6404d --- /dev/null +++ b/cpu/mpc512x/i2c.c @@ -0,0 +1,431 @@ +/* + * (C) Copyright 2003 - 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Based on the MPC5xxx code. + */ + +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_HARD_I2C + +#include +#include + +#define immr ((immap_t *)CFG_IMMR) + +/* by default set I2C bus 0 active */ +static unsigned int bus_num = 0; + +#define I2C_TIMEOUT 100 +#define I2C_RETRIES 3 + +struct mpc512x_i2c_tap { + int scl2tap; + int tap2tap; +}; + +static int mpc_reg_in(volatile u32 *reg); +static void mpc_reg_out(volatile u32 *reg, int val, int mask); +static int wait_for_bb(void); +static int wait_for_pin(int *status); +static int do_address(uchar chip, char rdwr_flag); +static int send_bytes(uchar chip, char *buf, int len); +static int receive_bytes(uchar chip, char *buf, int len); +static int mpc_get_fdr(int); + +static int mpc_reg_in (volatile u32 *reg) +{ + int ret = *reg >> 24; + __asm__ __volatile__ ("eieio"); + return ret; +} + +static void mpc_reg_out (volatile u32 *reg, int val, int mask) +{ + int tmp; + + if (!mask) { + *reg = val << 24; + } else { + tmp = mpc_reg_in (reg); + *reg = ((tmp & ~mask) | (val & mask)) << 24; + } + __asm__ __volatile__ ("eieio"); + + return; +} + +static int wait_for_bb (void) +{ + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int timeout = I2C_TIMEOUT; + int status; + + status = mpc_reg_in (®s->msr); + + while (timeout-- && (status & I2C_BB)) { + volatile int temp; + mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); + temp = mpc_reg_in (®s->mdr); + mpc_reg_out (®s->mcr, 0, I2C_STA); + mpc_reg_out (®s->mcr, 0, 0); + mpc_reg_out (®s->mcr, I2C_EN, 0); + + udelay (1000); + status = mpc_reg_in (®s->msr); + } + + return (status & I2C_BB); +} + +static int wait_for_pin (int *status) +{ + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int timeout = I2C_TIMEOUT; + + *status = mpc_reg_in (®s->msr); + + while (timeout-- && !(*status & I2C_IF)) { + udelay (1000); + *status = mpc_reg_in (®s->msr); + } + + if (!(*status & I2C_IF)) { + return -1; + } + + mpc_reg_out (®s->msr, 0, I2C_IF); + + return 0; +} + +static int do_address (uchar chip, char rdwr_flag) +{ + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int status; + + chip <<= 1; + + if (rdwr_flag) { + chip |= 1; + } + + mpc_reg_out (®s->mcr, I2C_TX, I2C_TX); + mpc_reg_out (®s->mdr, chip, 0); + + if (wait_for_pin (&status)) { + return -2; + } + + if (status & I2C_RXAK) { + return -3; + } + + return 0; +} + +static int send_bytes (uchar chip, char *buf, int len) +{ + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int wrcount; + int status; + + for (wrcount = 0; wrcount < len; ++wrcount) { + + mpc_reg_out (®s->mdr, buf[wrcount], 0); + + if (wait_for_pin (&status)) { + break; + } + + if (status & I2C_RXAK) { + break; + } + + } + + return !(wrcount == len); +} + +static int receive_bytes (uchar chip, char *buf, int len) +{ + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int dummy = 1; + int rdcount = 0; + int status; + int i; + + mpc_reg_out (®s->mcr, 0, I2C_TX); + + for (i = 0; i < len; ++i) { + buf[rdcount] = mpc_reg_in (®s->mdr); + + if (dummy) { + dummy = 0; + } else { + rdcount++; + } + + if (wait_for_pin (&status)) { + return -4; + } + } + + mpc_reg_out (®s->mcr, I2C_TXAK, I2C_TXAK); + buf[rdcount++] = mpc_reg_in (®s->mdr); + + if (wait_for_pin (&status)) { + return -5; + } + + mpc_reg_out (®s->mcr, 0, I2C_TXAK); + + return 0; +} + +/**************** I2C API ****************/ + +void i2c_init (int speed, int saddr) +{ + int i; + for(i = 0; i < I2C_BUS_CNT; i++){ + i2c512x_dev_t *regs = &immr->i2c.dev[i]; + mpc_reg_out (®s->mcr, 0, 0); + + /* Set clock */ + mpc_reg_out (®s->mfdr, mpc_get_fdr (speed), 0); + mpc_reg_out (®s->madr, saddr << 1, 0); + + /* Enable module */ + mpc_reg_out (®s->mcr, I2C_EN, I2C_INIT_MASK); + mpc_reg_out (®s->msr, 0, I2C_IF); + } + + /* Disable interrupts */ + immr->i2c.icr = 0; + /* Turn off filters */ + immr->i2c.mifr = 0; + return; +} + +static int mpc_get_fdr (int speed) +{ + static int fdr = -1; + + if (fdr == -1) { + ulong best_speed = 0; + ulong divider; + ulong ipb, scl; + ulong bestmatch = 0xffffffffUL; + int best_i = 0, best_j = 0, i, j; + int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8}; + struct mpc512x_i2c_tap scltap[] = { + {4, 1}, + {4, 2}, + {6, 4}, + {6, 8}, + {14, 16}, + {30, 32}, + {62, 64}, + {126, 128} + }; + + ipb = gd->ipb_clk; + for (i = 7; i >= 0; i--) { + for (j = 7; j >= 0; j--) { + scl = 2 * (scltap[j].scl2tap + + (SCL_Tap[i] - 1) * scltap[j].tap2tap + + 2); + if (ipb <= speed*scl) { + if ((speed*scl - ipb) < bestmatch) { + bestmatch = speed*scl - ipb; + best_i = i; + best_j = j; + best_speed = ipb/scl; + } + } + } + } + divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2); + if (gd->flags & GD_FLG_RELOC) { + fdr = divider; + } else { + debug("%ld kHz, \n", best_speed / 1000); + return divider; + } + } + + return fdr; +} + +int i2c_probe (uchar chip) +{ + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int i; + + for (i = 0; i < I2C_RETRIES; i++) { + mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); + + if (! do_address (chip, 0)) { + mpc_reg_out (®s->mcr, 0, I2C_STA); + udelay (500); + break; + } + + mpc_reg_out (®s->mcr, 0, I2C_STA); + udelay (500); + } + + return (i == I2C_RETRIES); +} + +int i2c_read (uchar chip, uint addr, int alen, uchar *buf, int len) +{ + char xaddr[4]; + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int ret = -1; + + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + + if (wait_for_bb ()) { + printf ("i2c_read: bus is busy\n"); + goto Done; + } + + mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); + if (do_address (chip, 0)) { + printf ("i2c_read: failed to address chip\n"); + goto Done; + } + + if (send_bytes (chip, &xaddr[4-alen], alen)) { + printf ("i2c_read: send_bytes failed\n"); + goto Done; + } + + mpc_reg_out (®s->mcr, I2C_RSTA, I2C_RSTA); + if (do_address (chip, 1)) { + printf ("i2c_read: failed to address chip\n"); + goto Done; + } + + if (receive_bytes (chip, (char *)buf, len)) { + printf ("i2c_read: receive_bytes failed\n"); + goto Done; + } + + ret = 0; +Done: + mpc_reg_out (®s->mcr, 0, I2C_STA); + return ret; +} + +int i2c_write (uchar chip, uint addr, int alen, uchar *buf, int len) +{ + char xaddr[4]; + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int ret = -1; + + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + + if (wait_for_bb ()) { + printf ("i2c_write: bus is busy\n"); + goto Done; + } + + mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); + if (do_address (chip, 0)) { + printf ("i2c_write: failed to address chip\n"); + goto Done; + } + + if (send_bytes (chip, &xaddr[4-alen], alen)) { + printf ("i2c_write: send_bytes failed\n"); + goto Done; + } + + if (send_bytes (chip, (char *)buf, len)) { + printf ("i2c_write: send_bytes failed\n"); + goto Done; + } + + ret = 0; +Done: + mpc_reg_out (®s->mcr, 0, I2C_STA); + return ret; +} + +uchar i2c_reg_read (uchar chip, uchar reg) +{ + uchar buf; + + i2c_read (chip, reg, 1, &buf, 1); + + return buf; +} + +void i2c_reg_write (uchar chip, uchar reg, uchar val) +{ + i2c_write (chip, reg, 1, &val, 1); + + return; +} + + +int i2c_set_bus_num (unsigned int bus) +{ + if (bus >= I2C_BUS_CNT) { + return -1; + } + bus_num = bus; + + return 0; +} + +unsigned int i2c_get_bus_num (void) +{ + return bus_num; +} + +/* TODO */ +unsigned int i2c_get_bus_speed (void) +{ + return -1; +} + +int i2c_set_bus_speed (unsigned int speed) +{ + if (speed != CFG_I2C_SPEED) + return -1; + + return 0; +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc512x/interrupts.c b/cpu/mpc512x/interrupts.c new file mode 100644 index 00000000000..8cc241c8998 --- /dev/null +++ b/cpu/mpc512x/interrupts.c @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2000-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright 2004 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Derived from the MPC83xx code. + */ + +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct irq_action { + interrupt_handler_t *handler; + void *arg; + ulong count; +}; + +int interrupt_init_cpu (unsigned *decrementer_count) +{ + *decrementer_count = get_tbclk () / CFG_HZ; + + return 0; +} + +/* + * Install and free an interrupt handler. + */ +void +irq_install_handler (int irq, interrupt_handler_t * handler, void *arg) +{ +} + +void irq_free_handler (int irq) +{ +} + +void timer_interrupt_cpu (struct pt_regs *regs) +{ + /* nothing to do here */ + return; +} diff --git a/cpu/mpc512x/serial.c b/cpu/mpc512x/serial.c new file mode 100644 index 00000000000..200ff2c4964 --- /dev/null +++ b/cpu/mpc512x/serial.c @@ -0,0 +1,197 @@ +/* + * (C) Copyright 2000 - 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Based ont the MPC5200 PSC driver. + * Adapted for MPC512x by Jan Wrobel + */ + +/* + * Minimal serial functions needed to use one of the PSC ports + * as serial console interface. + */ + +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_PSC_CONSOLE) + +static void fifo_init (volatile psc512x_t *psc) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + + /* reset Rx & Tx fifo slice */ + psc->rfcmd = PSC_FIFO_RESET_SLICE; + psc->tfcmd = PSC_FIFO_RESET_SLICE; + + /* disable Tx & Rx FIFO interrupts */ + psc->rfintmask = 0; + psc->tfintmask = 0; + + psc->tfsize = CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16); + psc->rfsize = CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16); + + /* enable Tx & Rx FIFO slice */ + psc->rfcmd = PSC_FIFO_ENABLE_SLICE; + psc->tfcmd = PSC_FIFO_ENABLE_SLICE; + + im->fifoc.fifoc_cmd = FIFOC_DISABLE_CLOCK_GATE; + __asm__ volatile ("sync"); +} + +int serial_init(void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + unsigned long baseclk; + int div; + + fifo_init (psc); + + /* set MR register to point to MR1 */ + psc->command = PSC_SEL_MODE_REG_1; + + /* disable Tx/Rx */ + psc->command = PSC_TX_DISABLE | PSC_RX_DISABLE; + + /* choose the prescaler by 16 for the Tx/Rx clock generation */ + psc->psc_clock_select = 0xdd00; + + /* switch to UART mode */ + psc->sicr = 0; + + /* mode register points to mr1 */ + /* configure parity, bit length and so on in mode register 1*/ + psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; + /* now, mode register points to mr2 */ + psc->mode = PSC_MODE_1_STOPBIT; + + /* calculate dividor for setting PSC CTUR and CTLR registers */ + baseclk = (gd->ipb_clk + 8) / 16; + div = (baseclk + (gd->baudrate / 2)) / gd->baudrate; + + psc->ctur = (div >> 8) & 0xff; + /* set baudrate */ + psc->ctlr = div & 0xff; + + /* disable all interrupts */ + psc->psc_imr = 0; + + /* reset and enable Rx/Tx */ + psc->command = PSC_RST_RX; + psc->command = PSC_RST_TX; + psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE; + + return 0; +} + +void serial_putc (const char c) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + + if (c == '\n') + serial_putc ('\r'); + + /* Wait for last character to go. */ + while (!(psc->psc_status & PSC_SR_TXEMP)) + ; + + psc->tfdata_8 = c; +} + +void serial_putc_raw (const char c) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + + /* Wait for last character to go. */ + while (!(psc->psc_status & PSC_SR_TXEMP)) + ; + + psc->tfdata_8 = c; +} + + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int serial_getc (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + + /* Wait for a character to arrive. */ + while (psc->rfstat & PSC_FIFO_EMPTY) + ; + + return psc->rfdata_8; +} + +int serial_tstc (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + + return !(psc->rfstat & PSC_FIFO_EMPTY); +} + +void serial_setbrg (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + unsigned long baseclk, div; + + baseclk = (gd->csb_clk + 8) / 16; + div = (baseclk + (gd->baudrate / 2)) / gd->baudrate; + + psc->ctur = (div >> 8) & 0xFF; + psc->ctlr = div & 0xff; /* set baudrate */ +} + +void serial_setrts(int s) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + + if (s) { + /* Assert RTS (become LOW) */ + psc->op1 = 0x1; + } + else { + /* Negate RTS (become HIGH) */ + psc->op0 = 0x1; + } +} + +int serial_getcts(void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + + return (psc->ip & 0x1) ? 0 : 1; +} +#endif /* CONFIG_PSC_CONSOLE */ diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c new file mode 100644 index 00000000000..9a31155ed2d --- /dev/null +++ b/cpu/mpc512x/speed.c @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2000-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Based on the MPC83xx code. + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static int spmf_mult[] = { + 68, 1, 12, 16, + 20, 24, 28, 32, + 36, 40, 44, 48, + 52, 56, 60, 64 +}; + +static int cpmf_mult[][2] = { + {0, 1}, {0, 1}, /* 0 and 1 are not valid */ + {1, 1}, {3, 2}, + {2, 1}, {5, 2}, + {3, 1}, {7, 2}, + {0, 1}, {0, 1}, /* and all above 7 are not valid too */ + {0, 1}, {0, 1}, + {0, 1}, {0, 1}, + {0, 1}, {0, 1} +}; + +static int sys_dividors[][2] = { + {2, 1}, {5, 2}, {3, 1}, {7, 2}, {4, 1}, + {9, 2}, {5, 1}, {7, 1}, {6, 1}, {8, 1}, + {9, 1}, {11, 1}, {10, 1}, {12, 1}, {13, 1}, + {15, 1}, {14, 1}, {16, 1}, {17, 1}, {19, 1}, + {18, 1}, {20, 1}, {21, 1}, {23, 1}, {22, 1}, + {24, 1}, {25, 1}, {27, 1}, {26, 1}, {28, 1}, + {29, 1}, {31, 1}, {30, 1}, {32, 1}, {33, 1} +}; + +int get_clocks (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u8 spmf; + u8 cpmf; + u8 sys_div; + u8 ips_div; + u32 ref_clk = CFG_MPC512X_CLKIN; + u32 spll; + u32 sys_clk; + u32 core_clk; + u32 csb_clk; + u32 ips_clk; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; + spll = ref_clk * spmf_mult[spmf]; + + sys_div = (im->clk.scfr[1] & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT; + sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0]; + + csb_clk = sys_clk / 2; + + cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT; + core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1]; + + ips_div = (im->clk.scfr[0] & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT; + if (ips_div != 0) { + ips_clk = csb_clk / ips_div; + } else { + /* in case we cannot get a sane IPS divisor, fail gracefully */ + ips_clk = 0; + } + + gd->ipb_clk = ips_clk; + gd->csb_clk = csb_clk; + gd->cpu_clk = core_clk; + gd->bus_clk = csb_clk; + return 0; + +} + +/******************************************** + * get_bus_freq + * return system bus freq in Hz + *********************************************/ +ulong get_bus_freq (ulong dummy) +{ + return gd->csb_clk; +} + +int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + printf ("Clock configuration:\n"); + printf (" CPU: %4d MHz\n", gd->cpu_clk / 1000000); + printf (" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000); + printf (" IPS Bus: %4d MHz\n", gd->ipb_clk / 1000000); + printf (" DDR: %4d MHz\n", 2 * gd->csb_clk / 1000000); + return 0; +} + +U_BOOT_CMD(clocks, 1, 0, do_clocks, + "clocks - print clock configuration\n", + " clocks\n" +); + +int prt_mpc512x_clks (void) +{ + do_clocks (NULL, 0, 0, NULL); + return (0); +} diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S new file mode 100644 index 00000000000..8b749ac54e9 --- /dev/null +++ b/cpu/mpc512x/start.S @@ -0,0 +1,780 @@ +/* + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2000, 2001, 2002, 2007 Wolfgang Denk + * Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Based on the MPC83xx code. + */ + +/* + * U-Boot - Startup Code for MPC512x based Embedded Boards + */ + +#include +#include +#include + +#define CONFIG_521X 1 /* needed for Linux kernel header files*/ + +#include +#include + +#include +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "MPC512X" +#endif + +/* + * Floating Point enable, Machine Check and Recoverable Interr. + */ +#undef MSR_KERNEL +#ifdef DEBUG +#define MSR_KERNEL (MSR_FP|MSR_RI) +#else +#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) +#endif + +/* Macros for manipulating CSx_START/STOP */ +#define START_REG(start) ((start) >> 16) +#define STOP_REG(start, size) (((start) + (size) - 1) >> 16) + +/* + * Set up GOT: Global Offset Table + * + * Use r14 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) + + GOT_ENTRY(__init_end) + GOT_ENTRY(_end) + GOT_ENTRY(__bss_start) + END_GOT + +/* + * Magic number and version string + */ + .long 0x27051956 /* U-Boot Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii " ", CONFIG_IDENT_STRING, "\0" + +/* + * Vector Table + */ + .text + . = EXC_OFF_SYS_RESET + + .globl _start + /* Start from here after reset/power on */ +_start: + li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */ + b boot_cold + + .globl _start_of_vectors +_start_of_vectors: + +/* Machine check */ + STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) + +/* Data Storage exception. */ + STD_EXCEPTION(0x300, DataStorage, UnknownException) + +/* Instruction Storage exception. */ + STD_EXCEPTION(0x400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x500, ExtInterrupt, UnknownException) + +/* Alignment exception. */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG(SRR0, SRR1) + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_Alignment: + .long AlignmentException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + +/* Program check exception */ + . = 0x700 +ProgramCheck: + EXCEPTION_PROLOG(SRR0, SRR1) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_ProgramCheck: + .long ProgramCheckException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + +/* Floating Point Unit unavailable exception */ + STD_EXCEPTION(0x800, FPUnavailable, UnknownException) + +/* Decrementer */ + STD_EXCEPTION(0x900, Decrementer, timer_interrupt) + +/* Critical interrupt */ + STD_EXCEPTION(0xa00, Critical, UnknownException) + +/* System Call */ + STD_EXCEPTION(0xc00, SystemCall, UnknownException) + +/* Trace interrupt */ + STD_EXCEPTION(0xd00, Trace, UnknownException) + +/* Performance Monitor interrupt */ + STD_EXCEPTION(0xf00, PerfMon, UnknownException) + +/* Intruction Translation Miss */ + STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) + +/* Data Load Translation Miss */ + STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) + +/* Data Store Translation Miss */ + STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) + +/* Instruction Address Breakpoint */ + STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException) + +/* System Management interrupt */ + STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException) + + .globl _end_of_vectors +_end_of_vectors: + + . = 0x3000 +boot_cold: + /* Save msr contents */ + mfmsr r5 + + /* Set IMMR area to our preferred location */ + lis r4, CONFIG_DEFAULT_IMMR@h + lis r3, CFG_IMMR@h + ori r3, r3, CFG_IMMR@l + stw r3, IMMRBAR(r4) + mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */ + + /* Initialise the machine */ + bl cpu_early_init + + /* + * Set up Local Access Windows: + * + * 1) Boot/CS0 (boot FLASH) + * 2) On-chip SRAM (initial stack purposes) + */ + + /* Boot CS/CS0 window range */ + lis r3, CFG_IMMR@h + ori r3, r3, CFG_IMMR@l + + lis r4, START_REG(CFG_FLASH_BASE) + ori r4, r4, STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE) + stw r4, LPCS0AW(r3) + + /* + * The SRAM window has a fixed size (256K), so only the start address + * is necessary + */ + lis r4, START_REG(CFG_SRAM_BASE) & 0xff00 + stw r4, SRAMBAR(r3) + + /* + * According to MPC5121e RM, configuring local access windows should + * be followed by a dummy read of the config register that was + * modified last and an isync + */ + lwz r4, SRAMBAR(r3) + isync + + /* + * Set configuration of the Boot/CS0, the SRAM window does not have a + * config register so no params can be set for it + */ + lis r3, (CFG_IMMR + LPC_OFFSET)@h + ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l + + lis r4, CFG_CS0_CFG@h + ori r4, r4, CFG_CS0_CFG@l + stw r4, CS0_CONFIG(r3) + + /* Master enable all CS's */ + lis r4, CS_CTRL_ME@h + ori r4, r4, CS_CTRL_ME@l + stw r4, CS_CTRL(r3) + + lis r4, (CFG_MONITOR_BASE)@h + ori r4, r4, (CFG_MONITOR_BASE)@l + addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET + mtlr r5 + blr + +in_flash: + lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h + ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l + + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + + /* let the C-code set up the rest */ + /* */ + /* Be careful to keep code relocatable & stack humble */ + /*------------------------------------------------------*/ + + GET_GOT /* initialize GOT access */ + + /* r3: IMMR */ + lis r3, CFG_IMMR@h + /* run low-level CPU init code (in Flash) */ + bl cpu_init_f + + /* r3: BOOTFLAG */ + mr r3, r21 + /* run 1st part of board init code (in Flash) */ + bl board_init_f + + /* NOTREACHED - board_init_f() does not return */ + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + +/* + * This code initialises the machine, it expects original MSR contents to be in r5. + */ +cpu_early_init: + /* Initialize machine status; enable machine check interrupt */ + /*-----------------------------------------------------------*/ + + li r3, MSR_KERNEL /* Set ME and RI flags */ + rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */ +#ifdef DEBUG + rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */ +#endif + mtmsr r3 + SYNC + mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */ + + lis r3, CFG_IMMR@h + +#if defined(CONFIG_WATCHDOG) + /* Initialise the watchdog and reset it */ + /*--------------------------------------*/ + lis r4, CFG_WATCHDOG_VALUE + ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) + stw r4, SWCRR(r3) + + /* reset */ + li r4, 0x556C + sth r4, SWSRR@l(r3) + li r4, 0x0 + ori r4, r4, 0xAA39 + sth r4, SWSRR@l(r3) +#else + /* Disable the watchdog */ + /*----------------------*/ + lwz r4, SWCRR(r3) + /* + * Check to see if it's enabled for disabling: once disabled by s/w + * it's not possible to re-enable it + */ + andi. r4, r4, 0x4 + beq 1f + xor r4, r4, r4 + stw r4, SWCRR(r3) +1: +#endif /* CONFIG_WATCHDOG */ + + /* Initialize the Hardware Implementation-dependent Registers */ + /* HID0 also contains cache control */ + /*------------------------------------------------------*/ + lis r3, CFG_HID0_INIT@h + ori r3, r3, CFG_HID0_INIT@l + SYNC + mtspr HID0, r3 + + lis r3, CFG_HID0_FINAL@h + ori r3, r3, CFG_HID0_FINAL@l + SYNC + mtspr HID0, r3 + + lis r3, CFG_HID2@h + ori r3, r3, CFG_HID2@l + SYNC + mtspr HID2, r3 + sync + blr + + +/* Cache functions. + * + * Note: requires that all cache bits in + * HID0 are in the low half word. + */ + .globl icache_enable +icache_enable: + mfspr r3, HID0 + ori r3, r3, HID0_ICE + lis r4, 0 + ori r4, r4, HID0_ILOCK + andc r3, r3, r4 + ori r4, r3, HID0_ICFI + isync + mtspr HID0, r4 /* sets enable and invalidate, clears lock */ + isync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl icache_disable +icache_disable: + mfspr r3, HID0 + lis r4, 0 + ori r4, r4, HID0_ICE|HID0_ILOCK + andc r3, r3, r4 + ori r4, r3, HID0_ICFI + isync + mtspr HID0, r4 /* sets invalidate, clears enable and lock*/ + isync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl icache_status +icache_status: + mfspr r3, HID0 + rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 + blr + + .globl dcache_enable +dcache_enable: + mfspr r3, HID0 + li r5, HID0_DCFI|HID0_DLOCK + andc r3, r3, r5 + mtspr HID0, r3 /* no invalidate, unlock */ + ori r3, r3, HID0_DCE + ori r5, r3, HID0_DCFI + mtspr HID0, r5 /* enable + invalidate */ + mtspr HID0, r3 /* enable */ + sync + blr + + .globl dcache_disable +dcache_disable: + mfspr r3, HID0 + lis r4, 0 + ori r4, r4, HID0_DCE|HID0_DLOCK + andc r3, r3, r4 + ori r4, r3, HID0_DCI + sync + mtspr HID0, r4 /* sets invalidate, clears enable and lock */ + sync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl dcache_status +dcache_status: + mfspr r3, HID0 + rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 + blr + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbf */ +/* Description: Data Cache block flush */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbf +ppcDcbf: + dcbf r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbi */ +/* Description: Data Cache block Invalidate */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbi +ppcDcbi: + dcbi r0,r3 + blr + +/*-------------------------------------------------------------------------- + * Function: ppcDcbz + * Description: Data Cache block zero. + * Input: r3 = effective address + * Output: none. + *-------------------------------------------------------------------------- */ + + .globl ppcDcbz +ppcDcbz: + dcbz r0,r3 + blr + + .globl ppcDWstore +ppcDWstore: + lfd 1, 0(r4) + stfd 1, 0(r3) + blr + + .globl ppcDWload +ppcDWload: + lfd 1, 0(r3) + stfd 1, 0(r4) + blr + +/*-------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + mr r1, r3 /* Set new stack pointer */ + mr r9, r4 /* Save copy of Global Data pointer */ + mr r10, r5 /* Save copy of Destination Address */ + + mr r3, r5 /* Destination Address */ + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + * + Destination Address + * + * Offset: + */ + sub r15, r10, r4 + + /* First our own GOT */ + add r14, r14, r15 + /* then the one used by the C code */ + add r30, r30, r15 + + /* + * Now relocate code + */ + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + la r8,-4(r4) + la r7,-4(r3) + + /* copy */ +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + + addi r0,r5,3 + srwi. r0,r0,2 + mtctr r0 + la r8,-4(r4) + la r7,-4(r3) + + /* and compare */ +20: lwzu r20,4(r8) + lwzu r21,4(r7) + xor. r22, r20, r21 + bne 30f + bdnz 20b + b 4f + + /* compare failed */ +30: li r3, 0 + blr + +2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b + +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* Wait for all dcbst to complete on bus */ + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + mtlr r0 + blr + +in_ram: + /* + * Relocation Function, r14 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + add r0,r0,r11 + stw r0,0(r3) + bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ +2: li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + add r0,r0,r11 + stw r10,0(r3) + stw r0,0(r4) + bdnz 3b +4: +clear_bss: + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) + lwz r4,GOT(_end) + + cmplw 0, r3, r4 + beq 6f + + li r0, 0 +5: + stw r0, 0(r3) + addi r3, r3, 4 + cmplw 0, r3, r4 + bne 5b +6: + mr r3, r9 /* Global Data pointer */ + mr r4, r10 /* Destination Address */ + bl board_init_r + + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + lwz r7, GOT(_start) + lwz r8, GOT(_end_of_vectors) + + li r9, 0x100 /* reset vector at 0x100 */ + + cmplw 0, r7, r8 + bgelr /* return if r7>=r8 - just in case */ + + mflr r4 /* save link register */ +1: + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + li r8, Alignment - _start + EXC_OFF_SYS_RESET +2: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 2b + + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + li r8, SystemCall - _start + EXC_OFF_SYS_RESET +3: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 3b + + li r7, .L_Trace - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET +4: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 4b + + mfmsr r3 /* now that the vectors have */ + lis r7, MSR_IP@h /* relocated into low memory */ + ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ + andc r3, r3, r7 /* (if it was on) */ + SYNC /* Some chip revs need this... */ + mtmsr r3 + SYNC + + mtlr r4 /* restore link register */ + blr + + /* + * Function: relocate entries for one exception vector + */ +trap_reloc: + lwz r0, 0(r7) /* hdlr ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 0(r7) + + lwz r0, 4(r7) /* int_return ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 4(r7) + + blr diff --git a/cpu/mpc512x/traps.c b/cpu/mpc512x/traps.c new file mode 100644 index 00000000000..40281a2cbb4 --- /dev/null +++ b/cpu/mpc512x/traps.c @@ -0,0 +1,205 @@ +/* + * (C) Copyright 2000 - 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Derived from the MPC83xx code. + */ + +/* + * This file handles the architecture-dependent parts of hardware + * exceptions + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +extern unsigned long search_exception_table(unsigned long); + +#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) + +/* + * Trap & Exception support + */ + +void +print_backtrace (unsigned long *sp) +{ + int cnt = 0; + unsigned long i; + + puts ("Call backtrace: "); + while (sp) { + if ((uint)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + putc ('\n'); + printf ("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *) *sp; + } + putc ('\n'); +} + +void show_regs (struct pt_regs * regs) +{ + int i; + + printf ("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + printf ("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr & MSR_EE ? 1 : 0, regs->msr & MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0,regs->msr & MSR_ME ? 1 : 0, + regs->msr & MSR_IR ? 1 : 0, + regs->msr & MSR_DR ? 1 : 0); + + putc ('\n'); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) { + printf ("GPR%02d: ", i); + } + + printf ("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) { + putc ('\n'); + } + } +} + + +void +_exception (int signr, struct pt_regs *regs) +{ + show_regs (regs); + print_backtrace ((unsigned long *)regs->gpr[1]); + panic ("Exception at pc %lx signal %d", regs->nip,signr); +} + + +void +MachineCheckException (struct pt_regs *regs) +{ + unsigned long fixup; + + if ((fixup = search_exception_table (regs->nip)) != 0) { + regs->nip = fixup; + return; + } + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + puts ("Machine check.\nCaused by (from msr): "); + printf ("regs %p ",regs); + switch (regs->msr & 0x00FF0000) { + case (0x80000000 >> 10): + puts ("Instruction cache parity signal\n"); + break; + case (0x80000000 >> 11): + puts ("Data cache parity signal\n"); + break; + case (0x80000000 >> 12): + puts ("Machine check signal\n"); + break; + case (0x80000000 >> 13): + puts ("Transfer error ack signal\n"); + break; + case (0x80000000 >> 14): + puts ("Data parity signal\n"); + break; + case (0x80000000 >> 15): + puts ("Address parity signal\n"); + break; + default: + puts ("Unknown values in msr\n"); + } + show_regs (regs); + print_backtrace ((unsigned long *)regs->gpr[1]); + + panic ("machine check"); +} + +void +AlignmentException (struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs (regs); + print_backtrace ((unsigned long *)regs->gpr[1]); + panic ("Alignment Exception"); +} + +void +ProgramCheckException (struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs (regs); + print_backtrace ((unsigned long *)regs->gpr[1]); + panic ("Program Check Exception"); +} + +void +SoftEmuException (struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs (regs); + print_backtrace ((unsigned long *)regs->gpr[1]); + panic ("Software Emulation Exception"); +} + + +void +UnknownException (struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + printf ("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception (0, regs); +} + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +extern void do_bedbug_breakpoint (struct pt_regs *); +#endif + +void +DebugException (struct pt_regs *regs) +{ + printf ("Debugger trap at @ %lx\n", regs->nip ); + show_regs (regs); +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) + do_bedbug_breakpoint (regs); +#endif +} diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h index d1bb159aefa..de8239965aa 100644 --- a/include/asm-ppc/e300.h +++ b/include/asm-ppc/e300.h @@ -9,6 +9,7 @@ #define PVR_E300C1 0x80830000 #define PVR_E300C2 0x80840000 #define PVR_E300C3 0x80850000 +#define PVR_E300C4 0x80860000 /* * Hardware Implementation-Dependent Register 0 (HID0) diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index cd2463643ce..bbaeb3f575f 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -85,6 +85,10 @@ typedef struct global_data { unsigned long ipb_clk; unsigned long pci_clk; #endif +#if defined(CONFIG_MPC512X) + u32 ipb_clk; + u32 csb_clk; +#endif /* CONFIG_MPC512X */ #if defined(CONFIG_MPC8220) unsigned long bExtUart; unsigned long inp_clk; diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h new file mode 100644 index 00000000000..23d10d4eb41 --- /dev/null +++ b/include/asm-ppc/immap_512x.h @@ -0,0 +1,569 @@ +/* + * (C) Copyright 2007 DENX Software Engineering + * + * MPC512x Internal Memory Map + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Based on the MPC83xx header. + */ + +#ifndef __IMMAP_512x__ +#define __IMMAP_512x__ + +#include + +typedef struct law512x { + u32 bar; /* Base Addr Register */ + u32 ar; /* Attributes Register */ +} law521x_t; + +/* + * System configuration registers + */ +typedef struct sysconf512x { + u32 immrbar; /* Internal memory map base address register */ + u8 res0[0x1c]; + u32 lpbaw; /* LP Boot Access Window */ + u32 lpcs0aw; /* LP CS0 Access Window */ + u32 lpcs1aw; /* LP CS1 Access Window */ + u32 lpcs2aw; /* LP CS2 Access Window */ + u32 lpcs3aw; /* LP CS3 Access Window */ + u32 lpcs4aw; /* LP CS4 Access Window */ + u32 lpcs5aw; /* LP CS5 Access Window */ + u32 lpcs6aw; /* LP CS6 Access Window */ + u32 lpcs7aw; /* LP CS7 Access Window */ + u8 res1[0x1c]; + law521x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */ + u8 res2[0x28]; + law521x_t ddrlaw; /* DDR Local Access Window */ + u8 res3[0x18]; + u32 mbxbar; /* MBX Base Address */ + u32 srambar; /* SRAM Base Address */ + u32 nfcbar; /* NFC Base Address */ + u8 res4[0x34]; + u32 spridr; /* System Part and Revision ID Register */ + u32 spcr; /* System Priority Configuration Register */ + u8 res5[0xf8]; +} sysconf512x_t; + +/* + * Watch Dog Timer (WDT) Registers + */ +typedef struct wdt512x { + u8 res0[4]; + u32 swcrr; /* System watchdog control register */ + u32 swcnr; /* System watchdog count register */ + u8 res1[2]; + u16 swsrr; /* System watchdog service register */ + u8 res2[0xF0]; +} wdt512x_t; + +/* + * RTC Module Registers + */ +typedef struct rtclk512x { + u8 fixme[0x100]; +} rtclk512x_t; + +/* + * General Purpose Timer + */ +typedef struct gpt512x { + u8 fixme[0x100]; +} gpt512x_t; + +/* + * Integrated Programmable Interrupt Controller + */ +typedef struct ipic512x { + u8 fixme[0x100]; +} ipic512x_t; + +/* + * System Arbiter Registers + */ +typedef struct arbiter512x { + u32 acr; /* Arbiter Configuration Register */ + u32 atr; /* Arbiter Timers Register */ + u32 ater; /* Arbiter Transfer Error Register */ + u32 aer; /* Arbiter Event Register */ + u32 aidr; /* Arbiter Interrupt Definition Register */ + u32 amr; /* Arbiter Mask Register */ + u32 aeatr; /* Arbiter Event Attributes Register */ + u32 aeadr; /* Arbiter Event Address Register */ + u32 aerr; /* Arbiter Event Response Register */ + u8 res1[0xDC]; +} arbiter512x_t; + +/* + * Reset Module + */ +typedef struct reset512x { + u32 rcwl; /* Reset Configuration Word Low Register */ + u32 rcwh; /* Reset Configuration Word High Register */ + u8 res0[8]; + u32 rsr; /* Reset Status Register */ + u32 rmr; /* Reset Mode Register */ + u32 rpr; /* Reset protection Register */ + u32 rcr; /* Reset Control Register */ + u32 rcer; /* Reset Control Enable Register */ + u8 res1[0xDC]; +} reset512x_t; + +/* + * Clock Module + */ +typedef struct clk512x { + u32 spmr; /* System PLL Mode Register */ + u32 sccr[2]; /* System Clock Control Registers */ + u32 scfr[2]; /* System Clock Frequency Registers */ + u8 res0[4]; + u32 bcr; /* Bread Crumb Register */ + u32 pscccr[12]; /* PSC0-11 Clock Control Registers */ + u32 spccr; /* SPDIF Clock Control Registers */ + u32 cccr; /* CFM Clock Control Registers */ + u32 dccr; /* DIU Clock Control Registers */ + u8 res1[0xa8]; +} clk512x_t; + +/* + * Power Management Control Module + */ +typedef struct pmc512x { + u8 fixme[0x100]; +} pmc512x_t; + +/* + * General purpose I/O module + */ +typedef struct gpio512x { + u8 fixme[0x100]; +} gpio512x_t; + +/* + * DDR Memory Controller Memory Map + */ +typedef struct ddr512x { + u32 ddr_sys_config; /* System Configuration Register */ + u32 ddr_time_config0; /* Timing Configuration Register */ + u32 ddr_time_config1; /* Timing Configuration Register */ + u32 ddr_time_config2; /* Timing Configuration Register */ + u32 ddr_command; /* Command Register */ + u32 ddr_compact_command; /* Compact Command Register */ + u32 self_refresh_cmd_0; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_1; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_2; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_3; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_4; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */ + u32 DQS_config_offset_count; /* DQS Config Offset Count */ + u32 DQS_config_offset_time; /* DQS Config Offset Time */ + u32 DQS_delay_status; /* DQS Delay Status */ + u32 res0[0xF]; + u32 prioman_config1; /* Priority Manager Configuration */ + u32 prioman_config2; /* Priority Manager Configuration */ + u32 hiprio_config; /* High Priority Configuration */ + u32 lut_table0_main_upper; /* LUT0 Main Upper */ + u32 lut_table1_main_upper; /* LUT1 Main Upper */ + u32 lut_table2_main_upper; /* LUT2 Main Upper */ + u32 lut_table3_main_upper; /* LUT3 Main Upper */ + u32 lut_table4_main_upper; /* LUT4 Main Upper */ + u32 lut_table0_main_lower; /* LUT0 Main Lower */ + u32 lut_table1_main_lower; /* LUT1 Main Lower */ + u32 lut_table2_main_lower; /* LUT2 Main Lower */ + u32 lut_table3_main_lower; /* LUT3 Main Lower */ + u32 lut_table4_main_lower; /* LUT4 Main Lower */ + u32 lut_table0_alternate_upper; /* LUT0 Alternate Upper */ + u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */ + u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */ + u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */ + u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */ + u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */ + u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */ + u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */ + u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */ + u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */ + u32 performance_monitor_config; + u32 event_time_counter; + u32 event_time_preset; + u32 performance_monitor1_address_low; + u32 performance_monitor2_address_low; + u32 performance_monitor1_address_hi; + u32 performance_monitor2_address_hi; + u32 res1[2]; + u32 performance_monitor1_read_counter; + u32 performance_monitor2_read_counter; + u32 performance_monitor1_write_counter; + u32 performance_monitor2_write_counter; + u32 granted_ack_counter0; + u32 granted_ack_counter1; + u32 granted_ack_counter2; + u32 granted_ack_counter3; + u32 granted_ack_counter4; + u32 cumulative_wait_counter0; + u32 cumulative_wait_counter1; + u32 cumulative_wait_counter2; + u32 cumulative_wait_counter3; + u32 cumulative_wait_counter4; + u32 summed_priority_counter0; + u32 summed_priority_counter1; + u32 summed_priority_counter2; + u32 summed_priority_counter3; + u32 summed_priority_counter4; + u32 res2[0x3AD]; +} ddr512x_t; + + +/* + * DMA/Messaging Unit + */ +typedef struct dma512x { + u8 fixme[0x1800]; +} dma512x_t; + +/* + * PCI Software Configuration Registers + */ +typedef struct pciconf512x { + u8 fixme[0x80]; +} pciconf512x_t; + +/* + * Sequencer + */ +typedef struct ios512x { + u8 fixme[0x100]; +} ios512x_t; + +/* + * PCI Controller + */ +typedef struct pcictrl512x { + u8 fixme[0x100]; +} pcictrl512x_t; + + +/* + * MSCAN + */ +typedef struct mscan512x { + u8 fixme[0x100]; +} mscan512x_t; + +/* + * BDLC + */ +typedef struct bdlc512x { + u8 fixme[0x100]; +} bdlc512x_t; + +/* + * SDHC + */ +typedef struct sdhc512x { + u8 fixme[0x100]; +} sdhc512x_t; + +/* + * SPDIF + */ +typedef struct spdif512x { + u8 fixme[0x100]; +} spdif512x_t; + +/* + * I2C + */ +typedef struct i2c512x_dev { + volatile u32 madr; /* I2Cn + 0x00 */ + volatile u32 mfdr; /* I2Cn + 0x04 */ + volatile u32 mcr; /* I2Cn + 0x08 */ + volatile u32 msr; /* I2Cn + 0x0C */ + volatile u32 mdr; /* I2Cn + 0x10 */ + u8 res0[0x0C]; +} i2c512x_dev_t; + +typedef struct i2c512x { + i2c512x_dev_t dev[3]; + volatile u32 icr; + volatile u32 mifr; + u8 res0[0x98]; +} i2c512x_t; + +/* + * AXE + */ +typedef struct axe512x { + u8 fixme[0x100]; +} axe512x_t; + +/* + * DIU + */ +typedef struct diu512x { + u8 fixme[0x100]; +} diu512x_t; + +/* + * CFM + */ +typedef struct cfm512x { + u8 fixme[0x100]; +} cfm512x_t; + +/* + * FEC + */ +typedef struct fec512x { + u8 fixme[0x800]; +} fec512x_t; + +/* + * ULPI + */ +typedef struct ulpi512x { + u8 fixme[0x600]; +} ulpi512x_t; + +/* + * UTMI + */ +typedef struct utmi512x { + u8 fixme[0x3000]; +} utmi512x_t; + +/* + * PCI DMA + */ +typedef struct pcidma512x { + u8 fixme[0x300]; +} pcidma512x_t; + +/* + * IO Control + */ +typedef struct ioctrl512x { + u32 regs[0x400]; +} ioctrl512x_t; + +/* + * IIM + */ +typedef struct iim512x { + u8 fixme[0x1000]; +} iim512x_t; + +/* + * LPC + */ +typedef struct lpc512x { + u32 cs_cfg[8]; /* Chip Select N Configuration Registers + No dedicated entry for CS Boot as == CS0 */ + u32 cs_cr; /* Chip Select Control Register */ + u32 cs_sr; /* Chip Select Status Register */ + u32 cs_bcr; /* Chip Select Burst Control Register */ + u32 cs_dccr; /* Chip Select Deadcycle Control Register */ + u32 cs_hccr; /* Chip Select Holdcycle Control Register */ + u8 res0[0xcc]; + u32 sclpc_psr; /* SCLPC Packet Size Register */ + u32 sclpc_sar; /* SCLPC Start Address Register */ + u32 sclpc_cr; /* SCLPC Control Register */ + u32 sclpc_er; /* SCLPC Enable Register */ + u32 sclpc_nar; /* SCLPC NextAddress Register */ + u32 sclpc_sr; /* SCLPC Status Register */ + u32 sclpc_bdr; /* SCLPC Bytes Done Register */ + u32 emb_scr; /* EMB Share Counter Register */ + u32 emb_pcr; /* EMB Pause Control Register */ + u8 res1[0x1c]; + u32 lpc_fdwr; /* LPC RX/TX FIFO Data Word Register */ + u32 lpc_fsr; /* LPC RX/TX FIFO Status Register */ + u32 lpc_cr; /* LPC RX/TX FIFO Control Register */ + u32 lpc_ar; /* LPC RX/TX FIFO Alarm Register */ + u8 res2[0xb0]; +} lpc512x_t; + +/* + * PATA + */ +typedef struct pata512x { + u8 fixme[0x100]; +} pata512x_t; + +/* + * PSC + */ +typedef struct psc512x { + volatile u8 mode; /* PSC + 0x00 */ + volatile u8 res0[3]; + union { /* PSC + 0x04 */ + volatile u16 status; + volatile u16 clock_select; + } sr_csr; +#define psc_status sr_csr.status +#define psc_clock_select sr_csr.clock_select + volatile u16 res1; + volatile u8 command; /* PSC + 0x08 */ + volatile u8 res2[3]; + union { /* PSC + 0x0c */ + volatile u8 buffer_8; + volatile u16 buffer_16; + volatile u32 buffer_32; + } buffer; +#define psc_buffer_8 buffer.buffer_8 +#define psc_buffer_16 buffer.buffer_16 +#define psc_buffer_32 buffer.buffer_32 + union { /* PSC + 0x10 */ + volatile u8 ipcr; + volatile u8 acr; + } ipcr_acr; +#define psc_ipcr ipcr_acr.ipcr +#define psc_acr ipcr_acr.acr + volatile u8 res3[3]; + union { /* PSC + 0x14 */ + volatile u16 isr; + volatile u16 imr; + } isr_imr; +#define psc_isr isr_imr.isr +#define psc_imr isr_imr.imr + volatile u16 res4; + volatile u8 ctur; /* PSC + 0x18 */ + volatile u8 res5[3]; + volatile u8 ctlr; /* PSC + 0x1c */ + volatile u8 res6[3]; + volatile u32 ccr; /* PSC + 0x20 */ + volatile u8 res7[12]; + volatile u8 ivr; /* PSC + 0x30 */ + volatile u8 res8[3]; + volatile u8 ip; /* PSC + 0x34 */ + volatile u8 res9[3]; + volatile u8 op1; /* PSC + 0x38 */ + volatile u8 res10[3]; + volatile u8 op0; /* PSC + 0x3c */ + volatile u8 res11[3]; + volatile u32 sicr; /* PSC + 0x40 */ + volatile u8 res12[60]; + volatile u32 tfcmd; /* PSC + 0x80 */ + volatile u32 tfalarm; /* PSC + 0x84 */ + volatile u32 tfstat; /* PSC + 0x88 */ + volatile u32 tfintstat; /* PSC + 0x8C */ + volatile u32 tfintmask; /* PSC + 0x90 */ + volatile u32 tfcount; /* PSC + 0x94 */ + volatile u16 tfwptr; /* PSC + 0x98 */ + volatile u16 tfrptr; /* PSC + 0x9A */ + volatile u32 tfsize; /* PSC + 0x9C */ + volatile u8 res13[28]; + union { /* PSC + 0xBC */ + volatile u8 buffer_8; + volatile u16 buffer_16; + volatile u32 buffer_32; + } tfdata_buffer; +#define tfdata_8 tfdata_buffer.buffer_8 +#define tfdata_16 tfdata_buffer.buffer_16 +#define tfdata_32 tfdata_buffer.buffer_32 + + volatile u32 rfcmd; /* PSC + 0xC0 */ + volatile u32 rfalarm; /* PSC + 0xC4 */ + volatile u32 rfstat; /* PSC + 0xC8 */ + volatile u32 rfintstat; /* PSC + 0xCC */ + volatile u32 rfintmask; /* PSC + 0xD0 */ + volatile u32 rfcount; /* PSC + 0xD4 */ + volatile u16 rfwptr; /* PSC + 0xD8 */ + volatile u16 rfrptr; /* PSC + 0xDA */ + volatile u32 rfsize; /* PSC + 0xDC */ + volatile u8 res18[28]; + union { /* PSC + 0xFC */ + volatile u8 buffer_8; + volatile u16 buffer_16; + volatile u32 buffer_32; + } rfdata_buffer; +#define rfdata_8 rfdata_buffer.buffer_8 +#define rfdata_16 rfdata_buffer.buffer_16 +#define rfdata_32 rfdata_buffer.buffer_32 +} psc512x_t; + +/* + * FIFOC + */ +typedef struct fifoc512x { + u32 fifoc_cmd; + u32 fifoc_int; + u32 fifoc_dma; + u32 fifoc_axe; + u32 fifoc_debug; + u8 fixme[0xEC]; +} fifoc512x_t; + +/* + * SATA + */ +typedef struct sata512x { + u8 fixme[0x2000]; +} sata512x_t; + +typedef struct immap { + sysconf512x_t sysconf; /* System configuration */ + u8 res0[0x700]; + wdt512x_t wdt; /* Watch Dog Timer (WDT) */ + rtclk512x_t rtc; /* Real Time Clock Module */ + gpt512x_t gpt; /* General Purpose Timer */ + ipic512x_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter512x_t arbiter; /* CSB Arbiter */ + reset512x_t reset; /* Reset Module */ + clk512x_t clk; /* Clock Module */ + pmc512x_t pmc; /* Power Management Control Module */ + gpio512x_t gpio; /* General purpose I/O module */ + u8 res1[0x100]; + mscan512x_t mscan; /* MSCAN */ + bdlc512x_t bdlc; /* BDLC */ + sdhc512x_t sdhc; /* SDHC */ + spdif512x_t spdif; /* SPDIF */ + i2c512x_t i2c; /* I2C Controllers */ + u8 res2[0x800]; + axe512x_t axe; /* AXE */ + diu512x_t diu; /* Display Interface Unit */ + cfm512x_t cfm; /* Clock Frequency Measurement */ + u8 res3[0x500]; + fec512x_t fec; /* Fast Ethernet Controller */ + ulpi512x_t ulpi; /* USB ULPI */ + u8 res4[0xa00]; + utmi512x_t utmi; /* USB UTMI */ + u8 res5[0x1000]; + pcidma512x_t pci_dma; /* PCI DMA */ + pciconf512x_t pci_conf; /* PCI Configuration */ + u8 res6[0x80]; + ios512x_t ios; /* PCI Sequencer */ + pcictrl512x_t pci_ctrl; /* PCI Controller Control and Status */ + u8 res7[0xa00]; + ddr512x_t mddrc; /* Multi-port DDR Memory Controller */ + ioctrl512x_t io_ctrl; /* IO Control */ + iim512x_t iim; /* IC Identification module */ + u8 res8[0x4000]; + lpc512x_t lpc; /* LocalPlus Controller */ + pata512x_t pata; /* Parallel ATA */ + u8 res9[0xd00]; + psc512x_t psc[12]; /* PSCs */ + u8 res10[0x300]; + fifoc512x_t fifoc; /* FIFO Controller */ + u8 res11[0x2000]; + dma512x_t dma; /* DMA */ + u8 res12[0xa800]; + sata512x_t sata; /* Serial ATA */ + u8 res13[0xde000]; +} immap_t; +#endif /* __IMMAP_512x__ */ diff --git a/include/common.h b/include/common.h index 23f93907ee4..d823733b67f 100644 --- a/include/common.h +++ b/include/common.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2004 + * (C) Copyright 2000-2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -65,6 +65,9 @@ typedef volatile unsigned char vu_char; #include #elif defined(CONFIG_MPC5xxx) #include +#elif defined(CONFIG_MPC512X) +#include +#include #elif defined(CONFIG_MPC8220) #include #elif defined(CONFIG_8260) @@ -448,6 +451,9 @@ int prt_8260_clks (void); #elif defined(CONFIG_MPC5xxx) int prt_mpc5xxx_clks (void); #endif +#if defined(CONFIG_MPC512x) +int prt_mpc512xxx_clks (void); +#endif #if defined(CONFIG_MPC8220) int prt_mpc8220_clks (void); #endif diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h new file mode 100644 index 00000000000..a1b8eefa02c --- /dev/null +++ b/include/configs/ads5121.h @@ -0,0 +1,410 @@ +/* + * (C) Copyright 2007 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * ADS5121 board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define DEBUG +#undef DEBUG + +/* + * Memory map for the ADS5121 board: + * + * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB) + * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) + * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) + * 0x8200_0000 - 0x8200_001F CPLD (32 B) + * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) + */ + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC512X 1 /* MPC512X family */ + +#undef CONFIG_PCI + +#define CFG_MPC512X_CLKIN 66000000 /* in Hz */ + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ + +#define CFG_IMMR 0x80000000 + +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + +/* + * DDR Setup - manually set all parameters as there's no SPD etc. + */ +#define CFG_DDR_SIZE 256 /* MB */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE + +/* DDR Controller Configuration + +SYS_CFG: + [31:31] MDDRC Soft Reset: Diabled + [30:30] DRAM CKE pin: Enabled + [29:29] DRAM CLK: Enabled + [28:28] Command Mode: Enabled (For initialization only) + [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] + [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] + [20:19] Read Test: DON'T USE + [18:18] Self Refresh: Enabled + [17:17] 16bit Mode: Disabled + [16:13] Ready Delay: 2 + [12:12] Half DQS Delay: Disabled + [11:11] Quarter DQS Delay: Disabled + [10:08] Write Delay: 2 + [07:07] Early ODT: Disabled + [06:06] On DIE Termination: Disabled + [05:05] FIFO Overflow Clear: DON'T USE here + [04:04] FIFO Underflow Clear: DON'T USE here + [03:03] FIFO Overflow Pending: DON'T USE here + [02:02] FIFO Underlfow Pending: DON'T USE here + [01:01] FIFO Overlfow Enabled: Enabled + [00:00] FIFO Underflow Enabled: Enabled + TIME_CFG0 + [31:16] DRAM Refresh Time: 0 CSB clocks + [15:8] DRAM Command Time: 0 CSB clocks + [07:00] DRAM Precharge Time: 0 CSB clocks + TIME_CFG1 + [31:26] DRAM tRFC: + [25:21] DRAM tWR1: + [20:17] DRAM tWRT1: + [16:11] DRAM tDRR: + [10:05] DRAM tRC: + [04:00] DRAM tRAS: + TIME_CFG2 + [31:28] DRAM tRCD: + [27:23] DRAM tFAW: + [22:19] DRAM tRTW1: + [18:15] DRAM tCCD: + [14:10] DRAM tRTP: + [09:05] DRAM tRP: + [04:00] DRAM tRPA */ + +#define CFG_MDDRC_SYS_CFG 0xF8604200 +#define CFG_MDDRC_SYS_CFG_RUN 0xE8604200 +#define CFG_MDDRC_SYS_CFG_EN 0x30000000 +#define CFG_MDDRC_TIME_CFG0 0x0000281E +#define CFG_MDDRC_TIME_CFG0_RUN 0x01F4281E +#define CFG_MDDRC_TIME_CFG1 0x54EC1168 +#define CFG_MDDRC_TIME_CFG2 0x35210864 + +#define CFG_MICRON_NOP 0x01380000 +#define CFG_MICRON_PCHG_ALL 0x01100400 +#define CFG_MICRON_MR 0x01000022 +#define CFG_MICRON_EM2 0x01020000 +#define CFG_MICRON_EM3 0x01030000 +#define CFG_MICRON_EN_DLL 0x01010000 +#define CFG_MICRON_RST_DLL 0x01000932 +#define CFG_MICRON_RFSH 0x01080000 +#define CFG_MICRON_INIT_DEV_OP 0x01000832 +#define CFG_MICRON_OCD_DEFAULT 0x01010780 +#define CFG_MICRON_OCD_EXIT 0x01010400 + +/* DDR Priority Manager Configuration */ +#define CFG_MDDRCGRP_PM_CFG1 0x000777AA +#define CFG_MDDRCGRP_PM_CFG2 0x00000055 +#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000000 +#define CFG_MDDRCGRP_LUT0_MU 0x11111117 +#define CFG_MDDRCGRP_LUT0_ML 0x7777777A +#define CFG_MDDRCGRP_LUT1_MU 0x4444EEEE +#define CFG_MDDRCGRP_LUT1_ML 0xEEEEEEEE +#define CFG_MDDRCGRP_LUT2_MU 0x44444444 +#define CFG_MDDRCGRP_LUT2_ML 0x44444444 +#define CFG_MDDRCGRP_LUT3_MU 0x55555555 +#define CFG_MDDRCGRP_LUT3_ML 0x55555558 +#define CFG_MDDRCGRP_LUT4_MU 0x11111111 +#define CFG_MDDRCGRP_LUT4_ML 0x1111117C +#define CFG_MDDRCGRP_LUT0_AU 0x33333377 +#define CFG_MDDRCGRP_LUT0_AL 0x7777EEEE +#define CFG_MDDRCGRP_LUT1_AU 0x11111111 +#define CFG_MDDRCGRP_LUT1_AL 0x11111111 +#define CFG_MDDRCGRP_LUT2_AU 0x11111111 +#define CFG_MDDRCGRP_LUT2_AL 0x11111111 +#define CFG_MDDRCGRP_LUT3_AU 0x11111111 +#define CFG_MDDRCGRP_LUT3_AL 0x11111111 +#define CFG_MDDRCGRP_LUT4_AU 0x11111111 +#define CFG_MDDRCGRP_LUT4_AL 0x11111111 + +/* + * NOR FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFC000000 /* start of FLASH */ +#define CFG_FLASH_SIZE 0x04000000 /* max flash size in bytes */ +#define CFG_FLASH_USE_BUFFER_WRITE + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ + +#undef CFG_FLASH_CHECKSUM + +/* + * CPLD registers area is really only 32 bytes in size, but the smallest possible LP + * window is 64KB + */ +#define CFG_CPLD_BASE 0x82000000 +#define CFG_CPLD_SIZE 0x00010000 /* 64 KB */ + +#define CFG_SRAM_BASE 0x30000000 +#define CFG_SRAM_SIZE 0x00020000 /* 128 KB */ + +#define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */ +#define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */ + +/* Use SRAM for initial stack */ +#define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END CFG_SRAM_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ +#if CONFIG_PSC_CONSOLE != 3 +#error CONFIG_PSC_CONSOLE must be 3 +#endif +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE +#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR +#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE +#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#if 0 +#define CFG_I2C_NOPROBES {{0,0x69}} * Don't probe these addrs */ +#endif + +/* + * Ethernet configuration + */ +#define CONFIG_MPC512x_FEC 1 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_ADDR 0x1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_ETHADDR 00:e0:5e:00:e5:14 + +#if 0 +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ +#endif + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +/* This has to be a multiple of the Flash sector size */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_NET \ + | CFG_CMD_PING \ + ) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_NET \ + | CFG_CMD_PING \ + | CFG_CMD_MII \ + | CFG_CMD_I2C) +#endif + +#include + +/* + * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock. + * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set + * to 0xFFFF, watchdog timeouts after about 64s. For details refer + * to chapter 36 of the MPC5121e Reference Manual. + */ +#define CONFIG_WATCHDOG /* enable watchdog */ +#define CFG_WATCHDOG_VALUE 0xFFFF + + /* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + + +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CFG_HID2 HID2_HBE + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_HOSTNAME ads5121 +#define CONFIG_ROOTPATH /nfsroot/rootfs +#define CONFIG_BOOTFILE uImage + +#define CONFIG_IPADDR 192.168.160.77 +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.0.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +//#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#define CONFIG_BOOTDELAY -1 +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "load=tftp 100000 /tftpboot/ads5121/u-boot.bin\0" \ + "update=protect off fff00000 fff3ffff; " \ + "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ + "upd=run load;run update\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#endif /* __CONFIG_H */ diff --git a/include/mpc512x.h b/include/mpc512x.h new file mode 100644 index 00000000000..03e0e9a1473 --- /dev/null +++ b/include/mpc512x.h @@ -0,0 +1,398 @@ +/* + * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * (C) Copyright 2007 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * Derived from the MPC83xx header. + */ + +#ifndef __MPC512X_H__ +#define __MPC512X_H__ + +#include +#if defined(CONFIG_E300) +#include +#endif + +/* System reset offset (PowerPC standard) + */ +#define EXC_OFF_SYS_RESET 0x0100 +#define _START_OFFSET EXC_OFF_SYS_RESET + + +/* IMMRBAR - Internal Memory Register Base Address + */ +#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ +#define IMMRBAR 0x0000 /* Register offset to immr */ +#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ +#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) + +/* LAWBAR - Local Access Window Base Address Register + */ +#define LPBAW 0x0020 /* Register offset to immr */ +#define LPCS0AW 0x0024 +#define LPCS1AW 0x0028 +#define LPCS2AW 0x002C +#define LPCS3AW 0x0030 +#define LPCS4AW 0x0034 +#define LPCS5AW 0x0038 +#define LPCS6AW 0x003C +#define LPCA7AW 0x0040 +#define SRAMBAR 0x00C4 + +#define LPC_OFFSET 0x10000 + +#define CS0_CONFIG 0x00000 +#define CS1_CONFIG 0x00004 +#define CS2_CONFIG 0x00008 +#define CS3_CONFIG 0x0000C +#define CS4_CONFIG 0x00010 +#define CS5_CONFIG 0x00014 +#define CS6_CONFIG 0x00018 +#define CS7_CONFIG 0x0001C + +#define CS_CTRL 0x00020 +#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */ +#define CS_CTRL_IE 0x08000000 /* CS Interrupt Enable bit */ + +/* SPRIDR - System Part and Revision ID Register + */ +#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */ +#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ + +#define SPR_5121E 0x80180000 + +/* SPCR - System Priority Configuration Register + */ +#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ +#define SPCR_PCIHPE_SHIFT (31-3) +#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ +#define SPCR_PCIPR_SHIFT (31-7) +#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ +#define SPCR_TBEN_SHIFT (31-9) +#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ +#define SPCR_COREPR_SHIFT (31-11) + +/* SWCRR - System Watchdog Control Register + */ +#define SWCRR 0x0904 /* Register offset to immr */ +#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ +#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ +#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ +#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ +#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) + +/* SWCNR - System Watchdog Counter Register + */ +#define SWCNR 0x0908 /* Register offset to immr */ +#define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ +#define SWCNR_RES ~(SWCNR_SWCN) + +/* SWSRR - System Watchdog Service Register + */ +#define SWSRR 0x090E /* Register offset to immr */ + +/* ACR - Arbiter Configuration Register + */ +#define ACR_COREDIS 0x10000000 /* Core disable */ +#define ACR_COREDIS_SHIFT (31-7) +#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ +#define ACR_PIPE_DEP_SHIFT (31-15) +#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ +#define ACR_PCI_RPTCNT_SHIFT (31-19) +#define ACR_RPTCNT 0x00000700 /* Repeat count */ +#define ACR_RPTCNT_SHIFT (31-23) +#define ACR_APARK 0x00000030 /* Address parking */ +#define ACR_APARK_SHIFT (31-27) +#define ACR_PARKM 0x0000000F /* Parking master */ +#define ACR_PARKM_SHIFT (31-31) + +/* ATR - Arbiter Timers Register + */ +#define ATR_DTO 0x00FF0000 /* Data time out */ +#define ATR_ATO 0x000000FF /* Address time out */ + +/* AER - Arbiter Event Register + */ +#define AER_ETEA 0x00000020 /* Transfer error */ +#define AER_RES 0x00000010 /* Reserved transfer type */ +#define AER_ECW 0x00000008 /* External control word transfer type */ +#define AER_AO 0x00000004 /* Address Only transfer type */ +#define AER_DTO 0x00000002 /* Data time out */ +#define AER_ATO 0x00000001 /* Address time out */ + +/* AEATR - Arbiter Event Address Register + */ +#define AEATR_EVENT 0x07000000 /* Event type */ +#define AEATR_MSTR_ID 0x001F0000 /* Master Id */ +#define AEATR_TBST 0x00000800 /* Transfer burst */ +#define AEATR_TSIZE 0x00000700 /* Transfer Size */ +#define AEATR_TTYPE 0x0000001F /* Transfer Type */ + +/* RSR - Reset Status Register + */ +#define RSR_SWSR 0x00002000 /* software soft reset */ +#define RSR_SWSR_SHIFT 13 +#define RSR_SWHR 0x00001000 /* software hard reset */ +#define RSR_SWHR_SHIFT 12 +#define RSR_JHRS 0x00000200 /* jtag hreset */ +#define RSR_JHRS_SHIFT 9 +#define RSR_JSRS 0x00000100 /* jtag sreset status */ +#define RSR_JSRS_SHIFT 8 +#define RSR_CSHR 0x00000010 /* checkstop reset status */ +#define RSR_CSHR_SHIFT 4 +#define RSR_SWRS 0x00000008 /* software watchdog reset status */ +#define RSR_SWRS_SHIFT 3 +#define RSR_BMRS 0x00000004 /* bus monitop reset status */ +#define RSR_BMRS_SHIFT 2 +#define RSR_SRS 0x00000002 /* soft reset status */ +#define RSR_SRS_SHIFT 1 +#define RSR_HRS 0x00000001 /* hard reset status */ +#define RSR_HRS_SHIFT 0 +#define RSR_RES ~(RSR_SWSR | RSR_SWHR |\ + RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ + RSR_BMRS | RSR_SRS | RSR_HRS) +/* RMR - Reset Mode Register + */ +#define RMR_CSRE 0x00000001 /* checkstop reset enable */ +#define RMR_CSRE_SHIFT 0 +#define RMR_RES ~(RMR_CSRE) + +/* RCR - Reset Control Register + */ +#define RCR_SWHR 0x00000002 /* software hard reset */ +#define RCR_SWSR 0x00000001 /* software soft reset */ +#define RCR_RES ~(RCR_SWHR | RCR_SWSR) + +/* RCER - Reset Control Enable Register + */ +#define RCER_CRE 0x00000001 /* software hard reset */ +#define RCER_RES ~(RCER_CRE) + +/* SPMR - System PLL Mode Register + */ +#define SPMR_SPMF 0x0F000000 +#define SPMR_SPMF_SHIFT 24 +#define SPMR_CPMF 0x000F0000 +#define SPMR_CPMF_SHIFT 16 + +/* SCFR1 System Clock Frequency Register 1 + */ +#define SCFR1_IPS_DIV 0x2 +#define SCFR1_IPS_DIV_MASK 0x03800000 +#define SCFR1_IPS_DIV_SHIFT 23 + +/* SCFR2 System Clock Frequency Register 2 + */ +#define SCFR2_SYS_DIV 0xFC000000 +#define SCFR2_SYS_DIV_SHIFT 26 + +/* SCCR - System Clock Control Registers + */ + +/* System Clock Control Register 1 commands */ +#define CLOCK_SCCR1_CFG_EN 0x80000000 +#define CLOCK_SCCR1_LPC_EN 0x40000000 +#define CLOCK_SCCR1_NFC_EN 0x20000000 +#define CLOCK_SCCR1_PATA_EN 0x10000000 +#define CLOCK_SCCR1_PSC_EN(cn) (0x08000000 >> (cn)) +#define CLOCK_SCCR1_PSCFIFO_EN 0x00008000 +#define CLOCK_SCCR1_SATA_EN 0x00004000 +#define CLOCK_SCCR1_FEC_EN 0x00002000 +#define CLOCK_SCCR1_TPR_EN 0x00001000 +#define CLOCK_SCCR1_PCI_EN 0x00000800 +#define CLOCK_SCCR1_DDR_EN 0x00000400 + +/* System Clock Control Register 2 commands */ +#define CLOCK_SCCR2_DIU_EN 0x80000000 +#define CLOCK_SCCR2_AXE_EN 0x40000000 +#define CLOCK_SCCR2_MEM_EN 0x20000000 +#define CLOCK_SCCR2_USB2_EN 0x10000000 +#define CLOCK_SCCR2_USB1_EN 0x08000000 +#define CLOCK_SCCR2_I2C_EN 0x04000000 +#define CLOCK_SCCR2_BDLC_EN 0x02000000 +#define CLOCK_SCCR2_SDHC_EN 0x01000000 +#define CLOCK_SCCR2_SPDIF_EN 0x00800000 +#define CLOCK_SCCR2_MBX_BUS_EN 0x00400000 +#define CLOCK_SCCR2_MBX_EN 0x00200000 +#define CLOCK_SCCR2_MBX_3D_EN 0x00100000 +#define CLOCK_SCCR2_IIM_EN 0x00080000 + +/* PSC FIFO Command values */ +#define PSC_FIFO_RESET_SLICE 0x80 +#define PSC_FIFO_ENABLE_SLICE 0x01 + +/* PSC FIFO Controller Command values */ +#define FIFOC_ENABLE_CLOCK_GATE 0x01 +#define FIFOC_DISABLE_CLOCK_GATE 0x00 + +/* PSC FIFO status */ +#define PSC_FIFO_EMPTY 0x01 + +/* PSC Command values */ +#define PSC_RX_ENABLE 0x01 +#define PSC_RX_DISABLE 0x02 +#define PSC_TX_ENABLE 0x04 +#define PSC_TX_DISABLE 0x08 +#define PSC_SEL_MODE_REG_1 0x10 +#define PSC_RST_RX 0x20 +#define PSC_RST_TX 0x30 +#define PSC_RST_ERR_STAT 0x40 +#define PSC_RST_BRK_CHG_INT 0x50 +#define PSC_START_BRK 0x60 +#define PSC_STOP_BRK 0x70 + +/* PSC status register bits */ +#define PSC_SR_CDE 0x0080 +#define PSC_SR_TXEMP 0x0800 +#define PSC_SR_OE 0x1000 +#define PSC_SR_PE 0x2000 +#define PSC_SR_FE 0x4000 +#define PSC_SR_RB 0x8000 + +/* PSC mode fields */ +#define PSC_MODE_5_BITS 0x00 +#define PSC_MODE_6_BITS 0x01 +#define PSC_MODE_7_BITS 0x02 +#define PSC_MODE_8_BITS 0x03 +#define PSC_MODE_PAREVEN 0x00 +#define PSC_MODE_PARODD 0x04 +#define PSC_MODE_PARFORCE 0x08 +#define PSC_MODE_PARNONE 0x10 +#define PSC_MODE_ENTIMEOUT 0x20 +#define PSC_MODE_RXRTS 0x80 +#define PSC_MODE_1_STOPBIT 0x07 + +/* + * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs + * + * NOTE: individual PSC units are free to use whatever area (and size) of the + * FIFOC internal memory, so make sure memory areas for FIFO slices used by + * different PSCs do not overlap! + * + * Overall size of FIFOC memory is not documented in the MPC5121e RM, but + * tests indicate that it is 1024 words total. + */ +#define FIFOC_PSC0_TX_SIZE 0x0 /* number of 4-byte words for FIFO slice */ +#define FIFOC_PSC0_TX_ADDR 0x0 +#define FIFOC_PSC0_RX_SIZE 0x0 +#define FIFOC_PSC0_RX_ADDR 0x0 + +#define FIFOC_PSC1_TX_SIZE 0x0 +#define FIFOC_PSC1_TX_ADDR 0x0 +#define FIFOC_PSC1_RX_SIZE 0x0 +#define FIFOC_PSC1_RX_ADDR 0x0 + +#define FIFOC_PSC2_TX_SIZE 0x0 +#define FIFOC_PSC2_TX_ADDR 0x0 +#define FIFOC_PSC2_RX_SIZE 0x0 +#define FIFOC_PSC2_RX_ADDR 0x0 + +#define FIFOC_PSC3_TX_SIZE 0x04 +#define FIFOC_PSC3_TX_ADDR 0x0 +#define FIFOC_PSC3_RX_SIZE 0x04 +#define FIFOC_PSC3_RX_ADDR 0x10 + +#define FIFOC_PSC4_TX_SIZE 0x0 +#define FIFOC_PSC4_TX_ADDR 0x0 +#define FIFOC_PSC4_RX_SIZE 0x0 +#define FIFOC_PSC4_RX_ADDR 0x0 + +#define FIFOC_PSC5_TX_SIZE 0x0 +#define FIFOC_PSC5_TX_ADDR 0x0 +#define FIFOC_PSC5_RX_SIZE 0x0 +#define FIFOC_PSC5_RX_ADDR 0x0 + +#define FIFOC_PSC6_TX_SIZE 0x0 +#define FIFOC_PSC6_TX_ADDR 0x0 +#define FIFOC_PSC6_RX_SIZE 0x0 +#define FIFOC_PSC6_RX_ADDR 0x0 + +#define FIFOC_PSC7_TX_SIZE 0x0 +#define FIFOC_PSC7_TX_ADDR 0x0 +#define FIFOC_PSC7_RX_SIZE 0x0 +#define FIFOC_PSC7_RX_ADDR 0x0 + +#define FIFOC_PSC8_TX_SIZE 0x0 +#define FIFOC_PSC8_TX_ADDR 0x0 +#define FIFOC_PSC8_RX_SIZE 0x0 +#define FIFOC_PSC8_RX_ADDR 0x0 + +#define FIFOC_PSC9_TX_SIZE 0x0 +#define FIFOC_PSC9_TX_ADDR 0x0 +#define FIFOC_PSC9_RX_SIZE 0x0 +#define FIFOC_PSC9_RX_ADDR 0x0 + +#define FIFOC_PSC10_TX_SIZE 0x0 +#define FIFOC_PSC10_TX_ADDR 0x0 +#define FIFOC_PSC10_RX_SIZE 0x0 +#define FIFOC_PSC10_RX_ADDR 0x0 + +#define FIFOC_PSC11_TX_SIZE 0x0 +#define FIFOC_PSC11_TX_ADDR 0x0 +#define FIFOC_PSC11_RX_SIZE 0x0 +#define FIFOC_PSC11_RX_ADDR 0x0 + +/* IO Control Register + */ + +/* Indexes in regs array */ +#define MEM_IDX 0x00 +#define SPDIF_TXCLOCK_IDX 0x73 +#define SPDIF_TX_IDX 0x74 +#define SPDIF_RX_IDX 0x75 +#define PSC0_0_IDX 0x83 +#define PSC0_1_IDX 0x84 +#define PSC0_2_IDX 0x85 +#define PSC0_3_IDX 0x86 +#define PSC0_4_IDX 0x87 +#define PSC1_0_IDX 0x88 +#define PSC1_1_IDX 0x89 +#define PSC1_2_IDX 0x8a +#define PSC1_3_IDX 0x8b +#define PSC1_4_IDX 0x8c +#define PSC2_0_IDX 0x8d +#define PSC2_1_IDX 0x8e +#define PSC2_2_IDX 0x8f +#define PSC2_3_IDX 0x90 +#define PSC2_4_IDX 0x91 + +#define IOCTRL_FUNCMUX_SHIFT 7 +#define IOCTRL_FUNCMUX_FEC 1 +#define IOCTRL_MUX_FEC (IOCTRL_FUNCMUX_FEC << IOCTRL_FUNCMUX_SHIFT) + +/* Set for DDR */ +#define IOCTRL_MUX_DDR 0x00000036 + + /* Register Offset Base */ +#define MPC512X_FEC (CFG_IMMR + 0x02800) + +/* Number of I2C buses */ +#define I2C_BUS_CNT 3 + +/* I2Cn control register bits */ +#define I2C_EN 0x80 +#define I2C_IEN 0x40 +#define I2C_STA 0x20 +#define I2C_TX 0x10 +#define I2C_TXAK 0x08 +#define I2C_RSTA 0x04 +#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA) + +/* I2Cn status register bits */ +#define I2C_CF 0x80 +#define I2C_AAS 0x40 +#define I2C_BB 0x20 +#define I2C_AL 0x10 +#define I2C_SRW 0x04 +#define I2C_IF 0x02 +#define I2C_RXAK 0x01 + +#endif /* __MPC512X_H__ */ diff --git a/net/eth.c b/net/eth.c index 9fb3a10edb8..68e2c54b2ea 100644 --- a/net/eth.c +++ b/net/eth.c @@ -40,6 +40,7 @@ extern int eth_3com_initialize(bd_t*); extern int fec_initialize(bd_t*); extern int inca_switch_initialize(bd_t*); extern int mpc5xxx_fec_initialize(bd_t*); +extern int mpc512x_fec_initialize(bd_t*); extern int mpc8220_fec_initialize(bd_t*); extern int mv6436x_eth_initialize(bd_t *); extern int mv6446x_eth_initialize(bd_t *); @@ -168,6 +169,9 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_MPC5xxx_FEC) mpc5xxx_fec_initialize(bis); #endif +#if defined(CONFIG_MPC512x_FEC) + mpc512x_fec_initialize (bis); +#endif #if defined(CONFIG_MPC8220_FEC) mpc8220_fec_initialize(bis); #endif -- cgit v1.3.1 From cdd917a43da6fa7fc8f54a3cc9f420ce5ecf3197 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 2 Aug 2007 00:48:45 +0200 Subject: Fix build errors and warnings / code cleanup. Signed-off-by: Wolfgang Denk --- MAKEALL | 5 +- Makefile | 74 +++++++------ board/esd/cpci750/sdram_init.c | 2 +- board/freescale/common/pixis.c | 8 +- board/mpc8641hpcn/mpc8641hpcn.c | 3 +- board/mpc8641hpcn/sys_eeprom.c | 16 +-- board/spc1920/hpi.c | 8 ++ cpu/mpc86xx/interrupts.c | 6 +- include/configs/GEN860T.h | 2 +- include/configs/LANTEC.h | 1 + include/configs/MPC8260ADS.h | 5 +- include/configs/MPC8266ADS.h | 1 + include/configs/MPC8313ERDB.h | 2 +- include/configs/RBC823.h | 1 + include/configs/ep8260.h | 1 + include/configs/gw8260.h | 2 +- include/configs/hymod.h | 1 + include/configs/mpc7448hpc2.h | 4 +- include/configs/ppmc7xx.h | 237 ++++++++++++++++++++-------------------- include/configs/sbc8349.h | 2 +- 20 files changed, 202 insertions(+), 179 deletions(-) (limited to 'cpu') diff --git a/MAKEALL b/MAKEALL index a53500053e9..0721472c0ec 100755 --- a/MAKEALL +++ b/MAKEALL @@ -133,8 +133,9 @@ LIST_8260=" \ ######################################################################### LIST_83xx=" \ - MPC8313ERDB MPC832XEMDS MPC8349EMDS MPC8349ITX \ - MPC8349ITXGP MPC8360EMDS sbc8349 TQM834x \ + MPC8313ERDB_33 MPC8313ERDB_66 MPC832XEMDS MPC8349EMDS \ + MPC8349ITX MPC8349ITXGP MPC8360EMDS sbc8349 \ + TQM834x \ " diff --git a/Makefile b/Makefile index 3b71b21e22e..97dfb9d2ed8 100644 --- a/Makefile +++ b/Makefile @@ -1646,14 +1646,15 @@ r5200_config : unconfig MPC8313ERDB_33_config \ MPC8313ERDB_66_config: unconfig - @echo "" >include/config.h ; \ + @mkdir -p $(obj)include + @echo "" >$(obj)include/config.h ; \ if [ "$(findstring _33_,$@)" ] ; then \ - echo -n "...33M ..." ; \ - echo "#define CFG_33MHZ" >>include/config.h ; \ + echo "...33M ..." ; \ + echo "#define CFG_33MHZ" >>$(obj)include/config.h ; \ fi ; \ if [ "$(findstring _66_,$@)" ] ; then \ - echo -n "...66M..." ; \ - echo "#define CFG_66MHZ" >>include/config.h ; \ + echo "...66M..." ; \ + echo "#define CFG_66MHZ" >>$(obj)include/config.h ; \ fi ; @$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb @@ -1661,23 +1662,24 @@ MPC832XEMDS_config \ MPC832XEMDS_HOST_33_config \ MPC832XEMDS_HOST_66_config \ MPC832XEMDS_SLAVE_config: unconfig - @echo "" >include/config.h ; \ + @mkdir -p $(obj)include + @echo "" >$(obj)include/config.h ; \ if [ "$(findstring _HOST_,$@)" ] ; then \ - echo -n "... PCI HOST " ; \ - echo "#define CONFIG_PCI" >>include/config.h ; \ + echo "... PCI HOST " ; \ + echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ fi ; \ if [ "$(findstring _SLAVE_,$@)" ] ; then \ echo "...PCI SLAVE 66M" ; \ - echo "#define CONFIG_PCI" >>include/config.h ; \ - echo "#define CONFIG_PCISLAVE" >>include/config.h ; \ + echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ + echo "#define CONFIG_PCISLAVE" >>$(obj)include/config.h ; \ fi ; \ if [ "$(findstring _33_,$@)" ] ; then \ - echo -n "...33M ..." ; \ - echo "#define PCI_33M" >>include/config.h ; \ + echo "...33M ..." ; \ + echo "#define PCI_33M" >>$(obj)include/config.h ; \ fi ; \ if [ "$(findstring _66_,$@)" ] ; then \ - echo -n "...66M..." ; \ - echo "#define PCI_66M" >>include/config.h ; \ + echo "...66M..." ; \ + echo "#define PCI_66M" >>$(obj)include/config.h ; \ fi ; @$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds @@ -1702,23 +1704,24 @@ MPC8360EMDS_config \ MPC8360EMDS_HOST_33_config \ MPC8360EMDS_HOST_66_config \ MPC8360EMDS_SLAVE_config: unconfig - @echo "" >include/config.h ; \ + @mkdir -p $(obj)include + @echo "" >$(obj)include/config.h ; \ if [ "$(findstring _HOST_,$@)" ] ; then \ - echo -n "... PCI HOST " ; \ - echo "#define CONFIG_PCI" >>include/config.h ; \ + echo "... PCI HOST " ; \ + echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ fi ; \ if [ "$(findstring _SLAVE_,$@)" ] ; then \ echo "...PCI SLAVE 66M" ; \ - echo "#define CONFIG_PCI" >>include/config.h ; \ - echo "#define CONFIG_PCISLAVE" >>include/config.h ; \ + echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ + echo "#define CONFIG_PCISLAVE" >>$(obj)include/config.h ; \ fi ; \ if [ "$(findstring _33_,$@)" ] ; then \ - echo -n "...33M ..." ; \ - echo "#define PCI_33M" >>include/config.h ; \ + echo "...33M ..." ; \ + echo "#define PCI_33M" >>$(obj)include/config.h ; \ fi ; \ if [ "$(findstring _66_,$@)" ] ; then \ - echo -n "...66M..." ; \ - echo "#define PCI_66M" >>include/config.h ; \ + echo "...66M..." ; \ + echo "#define PCI_66M" >>$(obj)include/config.h ; \ fi ; @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds @@ -1744,10 +1747,10 @@ MPC8540EVAL_66_slave_config: unconfig @mkdir -p $(obj)include @echo "" >$(obj)include/config.h ; \ if [ "$(findstring _33_,$@)" ] ; then \ - echo -n "... 33 MHz PCI" ; \ + echo "... 33 MHz PCI" ; \ else \ echo "#define CONFIG_SYSCLK_66M" >>$(obj)include/config.h ; \ - echo -n "... 66 MHz PCI" ; \ + echo "... 66 MHz PCI" ; \ fi ; \ if [ "$(findstring _slave_,$@)" ] ; then \ echo "#define CONFIG_PCI_SLAVE" >>$(obj)include/config.h ; \ @@ -2008,13 +2011,13 @@ omap1610h2_cs3boot_config \ omap1610h2_cs_autoboot_config: unconfig @mkdir -p $(obj)include @if [ "$(findstring _cs0boot_, $@)" ] ; then \ - echo "#define CONFIG_CS0_BOOT" >> .$(obj)/include/config.h ; \ + echo "#define CONFIG_CS0_BOOT" >> .$(obj)include/config.h ; \ echo "... configured for CS0 boot"; \ elif [ "$(findstring _cs_autoboot_, $@)" ] ; then \ - echo "#define CONFIG_CS_AUTOBOOT" >> $(obj)./include/config.h ; \ + echo "#define CONFIG_CS_AUTOBOOT" >> $(obj)include/config.h ; \ echo "... configured for CS_AUTO boot"; \ else \ - echo "#define CONFIG_CS3_BOOT" >> $(obj)./include/config.h ; \ + echo "#define CONFIG_CS3_BOOT" >> $(obj)include/config.h ; \ echo "... configured for CS3 boot"; \ fi; @$(MKCONFIG) -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn NULL omap @@ -2183,11 +2186,12 @@ logodl_config : unconfig pdnb3_config \ scpu_config: unconfig + @mkdir -p $(obj)include @if [ "$(findstring scpu_,$@)" ] ; then \ - echo "#define CONFIG_SCPU" >>include/config.h ; \ + echo "#define CONFIG_SCPU" >>$(obj)include/config.h ; \ echo "... on SCPU board variant" ; \ else \ - >include/config.h ; \ + >$(obj)include/config.h ; \ fi @$(MKCONFIG) -a pdnb3 arm ixp pdnb3 prodrive @@ -2409,13 +2413,15 @@ suzaku_config: unconfig @$(MKCONFIG) -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno ml401_config: unconfig - @ >include/config.h - @echo "#define CONFIG_ML401 1" >> include/config.h + @mkdir -p $(obj)include + @ >$(obj)include/config.h + @echo "#define CONFIG_ML401 1" >> $(obj)include/config.h @$(MKCONFIG) -a $(@:_config=) microblaze microblaze ml401 xilinx xupv2p_config: unconfig - @ >include/config.h - @echo "#define CONFIG_XUPV2P 1" >> include/config.h + @mkdir -p $(obj)include + @ >$(obj)include/config.h + @echo "#define CONFIG_XUPV2P 1" >> $(obj)include/config.h @$(MKCONFIG) -a $(@:_config=) microblaze microblaze xupv2p xilinx ######################################################################### diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c index c094755351c..78d18801854 100644 --- a/board/esd/cpci750/sdram_init.c +++ b/board/esd/cpci750/sdram_init.c @@ -1252,7 +1252,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) /* sets up the GT properly with information passed in */ int setup_sdram (AUX_MEM_DIMM_INFO * info) { - ulong tmp, check; + ulong tmp; ulong tmp_sdram_mode = 0; /* 0x141c */ ulong tmp_dunit_control_low = 0; /* 0x1404 */ int i; diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index af98157dfd7..99cc2ee197e 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -321,10 +321,10 @@ static ulong strfractoint(uchar *strptr) mulconst = 1; for (i = 0; i < decarr_len; i++) mulconst *= 10; - decval = simple_strtoul(decarr, NULL, 10); + decval = simple_strtoul((char *)decarr, NULL, 10); } - intval = simple_strtoul(intarr, NULL, 10); + intval = simple_strtoul((char *)intarr, NULL, 10); intval = intval * mulconst; retval = intval + decval; @@ -362,7 +362,7 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10)); - corepll = strfractoint(argv[3]); + corepll = strfractoint((uchar *)argv[3]); val = val + set_px_corepll(corepll); val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10)); if (val == 3) { @@ -410,7 +410,7 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) read_from_px_regs(0); read_from_px_regs_altbank(0); val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10)); - corepll = strfractoint(argv[4]); + corepll = strfractoint((uchar *)argv[4]); val = val + set_px_corepll(corepll); val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10)); diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index 7d7e2afad31..5e02cc5a5e6 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -63,9 +63,10 @@ int checkboard(void) uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; +#ifdef DEBUG uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); - +#endif if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || io_sel == 7 || io_sel == 0xF) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { diff --git a/board/mpc8641hpcn/sys_eeprom.c b/board/mpc8641hpcn/sys_eeprom.c index 74e2a3d46ff..7bc663bba46 100644 --- a/board/mpc8641hpcn/sys_eeprom.c +++ b/board/mpc8641hpcn/sys_eeprom.c @@ -68,7 +68,7 @@ int mac_show(void) mac_data.date[5], mac_data.date[6]); for (i = 0; i < 8; i++) { - sprintf(ethaddr[i], + sprintf((char *)ethaddr[i], "%02x:%02x:%02x:%02x:%02x:%02x", mac_data.mac[i][0], mac_data.mac[i][1], @@ -79,10 +79,10 @@ int mac_show(void) printf("MAC %d %s\n", i, ethaddr[i]); } - setenv("ethaddr", ethaddr[0]); - setenv("eth1addr", ethaddr[1]); - setenv("eth2addr", ethaddr[2]); - setenv("eth3addr", ethaddr[3]); + setenv("ethaddr", (char *)ethaddr[0]); + setenv("eth1addr", (char *)ethaddr[1]); + setenv("eth2addr", (char *)ethaddr[2]); + setenv("eth3addr", (char *)ethaddr[3]); return 0; } @@ -236,7 +236,7 @@ int mac_read_from_eeprom(void) } else { for (i = 0; i < 4; i++) { if (memcmp(&mac_data.mac[i], "\0\0\0\0\0\0", 6)) { - sprintf(ethaddr[i], + sprintf((char *)ethaddr[i], "%02x:%02x:%02x:%02x:%02x:%02x", mac_data.mac[i][0], mac_data.mac[i][1], @@ -244,10 +244,10 @@ int mac_read_from_eeprom(void) mac_data.mac[i][3], mac_data.mac[i][4], mac_data.mac[i][5]); - sprintf(enetvar, + sprintf((char *)enetvar, i ? "eth%daddr" : "ethaddr", i); - setenv(enetvar, ethaddr[i]); + setenv((char *)enetvar, (char *)ethaddr[i]); } } } diff --git a/board/spc1920/hpi.c b/board/spc1920/hpi.c index 3c36f7911bc..cd7799b277b 100644 --- a/board/spc1920/hpi.c +++ b/board/spc1920/hpi.c @@ -122,7 +122,9 @@ const uint dsp_table_fast[] = #define TINY_AUTOINC_BASE_ADDR 0x0 static int hpi_activate(void); +#if 0 static void hpi_inactivate(void); +#endif static void dsp_reset(void); static int hpi_write_inc(u32 addr, u32 *data, u32 count); @@ -133,7 +135,9 @@ static u32 hpi_read_noinc(u32 addr); int hpi_test(void); static int hpi_write_addr_test(u32 addr); static int hpi_read_write_test(u32 addr, u32 data); +#ifdef DO_TINY_TEST static int hpi_tiny_autoinc_test(void); +#endif /* DO_TINY_TEST */ #endif /* CONFIG_SPC1920_HPI_TEST */ @@ -185,6 +189,7 @@ static int hpi_activate(void) return 0; } +#if 0 /* turn off the host port interface */ static void hpi_inactivate(void) { @@ -200,6 +205,7 @@ static void hpi_inactivate(void) /* currently always on TBD */ } +#endif /* reset the DSP */ static void dsp_reset(void) @@ -570,6 +576,7 @@ static int hpi_read_write_test(u32 addr, u32 data) return 0; } +#ifdef DO_TINY_TEST static int hpi_tiny_autoinc_test(void) { int i; @@ -599,5 +606,6 @@ static int hpi_tiny_autoinc_test(void) } return 0; } +#endif /* DO_TINY_TEST */ #endif /* CONFIG_SPC1920_HPI_TEST */ diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index 49820bbd811..08e0675fee4 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -71,7 +71,7 @@ static __inline__ void set_dec(unsigned long val) } /* interrupt is not supported yet */ -int interrupt_init_cpu(unsigned *decrementer_count) +int interrupt_init_cpu(unsigned long *decrementer_count) { return 0; } @@ -107,7 +107,7 @@ int interrupt_init(void) return ret; decrementer_count = get_tbclk() / CFG_HZ; - debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", + debug("interrupt init: tbclk() = %d MHz, decrementer_count = %ld\n", (get_tbclk() / 1000000), decrementer_count); @@ -158,7 +158,7 @@ void timer_interrupt(struct pt_regs *regs) timestamp++; - ppcDcbf(×tamp); + ppcDcbf((unsigned long)×tamp); /* Restore Decrementer Count */ set_dec(decrementer_count); diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h index d88124a3b42..bfbf3a839cf 100644 --- a/include/configs/GEN860T.h +++ b/include/configs/GEN860T.h @@ -248,7 +248,7 @@ #endif #ifdef CONFIG_POST -u #define CONFIG_CMD_DIAG +#define CONFIG_CMD_DIAG #endif /* diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h index 2191c7b99c1..46edd08a91f 100644 --- a/include/configs/LANTEC.h +++ b/include/configs/LANTEC.h @@ -106,6 +106,7 @@ #undef CONFIG_CMD_IRQ #undef CONFIG_CMD_JFFS2 #undef CONFIG_CMD_KGDB +#undef CONFIG_CMD_MFSL #undef CONFIG_CMD_MII #undef CONFIG_CMD_MMC #undef CONFIG_CMD_NAND diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index f3e5330c779..713518d0da2 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -227,6 +227,7 @@ #undef CONFIG_CMD_HWFLOW #undef CONFIG_CMD_IDE #undef CONFIG_CMD_KGDB +#undef CONFIG_CMD_MFSL #undef CONFIG_CMD_MMC #undef CONFIG_CMD_NAND #undef CONFIG_CMD_PCMCIA @@ -405,9 +406,9 @@ #define CFG_BCR 0x100C0000 #define CFG_SIUMCR 0x0A200000 #define CFG_SCCR SCCR_DFBRG01 -#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00001801 +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801) #define CFG_OR0_PRELIM 0xFF800876 -#define CFG_BR1_PRELIM CFG_BCSR | 0x00001801 +#define CFG_BR1_PRELIM (CFG_BCSR | 0x00001801) #define CFG_OR1_PRELIM 0xFFFF8010 /*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/ diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h index 3a6c977a606..14b041e3aec 100644 --- a/include/configs/MPC8266ADS.h +++ b/include/configs/MPC8266ADS.h @@ -165,6 +165,7 @@ #undef CONFIG_CMD_IDE #undef CONFIG_CMD_JFFS2 #undef CONFIG_CMD_KGDB +#undef CONFIG_CMD_MFSL #undef CONFIG_CMD_MMC #undef CONFIG_CMD_NAND #undef CONFIG_CMD_PCMCIA diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 45a7d81792d..81db96f4661 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -265,7 +265,7 @@ #define CONFIG_I2C_CMD_TREE #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h index 5e12dabecf7..2f6de815514 100644 --- a/include/configs/RBC823.h +++ b/include/configs/RBC823.h @@ -119,6 +119,7 @@ #undef CONFIG_CMD_IRQ #undef CONFIG_CMD_JFFS2 #undef CONFIG_CMD_MII +#undef CONFIG_CMD_MFSL #undef CONFIG_CMD_MMC #undef CONFIG_CMD_NAND #undef CONFIG_CMD_PCI diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h index f412ec8ed80..025c24960d2 100644 --- a/include/configs/ep8260.h +++ b/include/configs/ep8260.h @@ -321,6 +321,7 @@ #undef CONFIG_CMD_JFFS2 #undef CONFIG_CMD_KGDB #undef CONFIG_CMD_MII +#undef CONFIG_CMD_MFSL #undef CONFIG_CMD_MMC #undef CONFIG_CMD_NAND #undef CONFIG_CMD_PCI diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h index 79e6aa1ba6c..ff5724082d0 100644 --- a/include/configs/gw8260.h +++ b/include/configs/gw8260.h @@ -294,7 +294,7 @@ #define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_BOOTFILESIZE -#definef CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS /* undef this to save memory */ #define CFG_LONGHELP diff --git a/include/configs/hymod.h b/include/configs/hymod.h index b789067f81d..2f64ec238c6 100644 --- a/include/configs/hymod.h +++ b/include/configs/hymod.h @@ -199,6 +199,7 @@ #undef CONFIG_CMD_IDE #undef CONFIG_CMD_JFFS2 #undef CONFIG_CMD_NAND +#undef CONFIG_CMD_MFSL #undef CONFIG_CMD_MMC #undef CONFIG_CMD_PCMCIA #undef CONFIG_CMD_PCI diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 4237228bebe..f4f33f3e089 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -375,9 +375,9 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1/* Flash can be at one of two addresses */ +#define CFG_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */ #define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ -#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, /* CFG_FLASH_BASE2 */ } #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h index 6e451d8b6cb..fe7de7bed0f 100644 --- a/include/configs/ppmc7xx.h +++ b/include/configs/ppmc7xx.h @@ -25,29 +25,30 @@ /* * Debug * - * DEBUG - Define this is you want extra debug info - * GTREGREAD - Required to build with debug - * do_bdinfo - Required to build with debug + * DEBUG - Define this is you want extra debug info + * GTREGREAD - Required to build with debug + * do_bdinfo - Required to build with debug */ #undef DEBUG -#define GTREGREAD(x) 0xFFFFFFFF +#ifdef DEBUG +#define GTREGREAD(x) 0xFFFFFFFF #define do_bdinfo(a,b,c,d) - +#endif /* * CPU type * - * CONFIG_7xx - We have a 750 or 755 CPU - * CONFIG_74xx - We have a 7400 CPU - * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400) - * CONFIG_BUS_CLK - System bus clock in Hz + * CONFIG_7xx - We have a 750 or 755 CPU + * CONFIG_74xx - We have a 7400 CPU + * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400) + * CONFIG_BUS_CLK - System bus clock in Hz */ #define CONFIG_7xx #undef CONFIG_74xx #undef CONFIG_ALTIVEC -#define CONFIG_BUS_CLK 66000000 +#define CONFIG_BUS_CLK 66000000 /* @@ -97,18 +98,18 @@ * Serial configuration * * CONFIG_CONS_INDEX - Serial console port number (COM1) - * CONFIG_BAUDRATE - Serial speed + * CONFIG_BAUDRATE - Serial speed */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 9600 /* * PCI config * - * CONFIG_PCI - Enable PCI bus - * CONFIG_PCI_PNP - Enable Plug & Play support + * CONFIG_PCI - Enable PCI bus + * CONFIG_PCI_PNP - Enable Plug & Play support * CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup */ @@ -120,9 +121,9 @@ /* * Network config * - * CONFIG_NET_MULTI - Support for multiple network interfaces - * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller - * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM + * CONFIG_NET_MULTI - Support for multiple network interfaces + * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller + * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM */ #define CONFIG_NET_MULTI @@ -145,7 +146,7 @@ * Boot config * * CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot - * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec) + * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec) */ #define CONFIG_BOOTCOMMAND \ @@ -169,79 +170,79 @@ * * This board runs in a standard CHRP (Map-B) configuration. * - * Type Start End Size Width Chip Sel + * Type Start End Size Width Chip Sel * ----------- ----------- ----------- ------- ------- -------- - * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0 - * User LED's 0x78000000 RCS3 - * UART 0x7C000000 RCS2 - * Mailbox 0xFF000000 RCS1 - * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0 + * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0 + * User LED's 0x78000000 RCS3 + * UART 0x7C000000 RCS2 + * Mailbox 0xFF000000 RCS1 + * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0 * * Flash sectors are laid out as follows. * - * Sector Start End Size Comments + * Sector Start End Size Comments * ------- ----------- ----------- ------- ----------- - * 0 0xFFC00000 0xFFC3FFFF 256KB - * 1 0xFFC40000 0xFFC7FFFF 256KB - * 2 0xFFC80000 0xFFCBFFFF 256KB - * 3 0xFFCC0000 0xFFCFFFFF 256KB - * 4 0xFFD00000 0xFFD3FFFF 256KB - * 5 0xFFD40000 0xFFD7FFFF 256KB - * 6 0xFFD80000 0xFFDBFFFF 256KB - * 7 0xFFDC0000 0xFFDFFFFF 256KB - * 8 0xFFE00000 0xFFE3FFFF 256KB - * 9 0xFFE40000 0xFFE7FFFF 256KB - * 10 0xFFE80000 0xFFEBFFFF 256KB - * 11 0xFFEC0000 0xFFEFFFFF 256KB - * 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here - * 13 0xFFF40000 0xFFF7FFFF 256KB - * 14 0xFFF80000 0xFFFBFFFF 256KB - * 15 0xFFFC0000 0xFFFDFFFF 128KB - * 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here - * 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here - * 18 0xFFFF0000 0xFFFFFFFF 64KB + * 0 0xFFC00000 0xFFC3FFFF 256KB + * 1 0xFFC40000 0xFFC7FFFF 256KB + * 2 0xFFC80000 0xFFCBFFFF 256KB + * 3 0xFFCC0000 0xFFCFFFFF 256KB + * 4 0xFFD00000 0xFFD3FFFF 256KB + * 5 0xFFD40000 0xFFD7FFFF 256KB + * 6 0xFFD80000 0xFFDBFFFF 256KB + * 7 0xFFDC0000 0xFFDFFFFF 256KB + * 8 0xFFE00000 0xFFE3FFFF 256KB + * 9 0xFFE40000 0xFFE7FFFF 256KB + * 10 0xFFE80000 0xFFEBFFFF 256KB + * 11 0xFFEC0000 0xFFEFFFFF 256KB + * 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here + * 13 0xFFF40000 0xFFF7FFFF 256KB + * 14 0xFFF80000 0xFFFBFFFF 256KB + * 15 0xFFFC0000 0xFFFDFFFF 128KB + * 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here + * 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here + * 18 0xFFFF0000 0xFFFFFFFF 64KB */ /* * SDRAM config - see memory map details above. * - * CFG_SDRAM_BASE - Start address of SDRAM, this _must_ be zero! - * CFG_SDRAM_SIZE - Total size of contiguous SDRAM bank(s) + * CFG_SDRAM_BASE - Start address of SDRAM, this _must_ be zero! + * CFG_SDRAM_SIZE - Total size of contiguous SDRAM bank(s) */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 0x04000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 0x04000000 /* * Flash config - see memory map details above. * - * CFG_FLASH_BASE - Start address of flash memory - * CFG_FLASH_SIZE - Total size of contiguous flash mem + * CFG_FLASH_BASE - Start address of flash memory + * CFG_FLASH_SIZE - Total size of contiguous flash mem * CFG_FLASH_ERASE_TOUT - Erase timeout in ms * CFG_FLASH_WRITE_TOUT - Write timeout in ms * CFG_MAX_FLASH_BANKS - Number of banks of flash on board * CFG_MAX_FLASH_SECT - Number of sectors in a bank */ -#define CFG_FLASH_BASE 0xFFC00000 -#define CFG_FLASH_SIZE 0x00400000 +#define CFG_FLASH_BASE 0xFFC00000 +#define CFG_FLASH_SIZE 0x00400000 #define CFG_FLASH_ERASE_TOUT 250000 #define CFG_FLASH_WRITE_TOUT 5000 -#define CFG_MAX_FLASH_BANKS 1 -#define CFG_MAX_FLASH_SECT 19 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 19 /* * Monitor config - see memory map details above * - * CFG_MONITOR_BASE - Base address of monitor code - * CFG_MALLOC_LEN - Size of malloc pool (128KB) + * CFG_MONITOR_BASE - Base address of monitor code + * CFG_MALLOC_LEN - Size of malloc pool (128KB) */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_LEN 0x20000 +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_LEN 0x20000 /* @@ -259,16 +260,16 @@ * CFG_PROMPT - Prompt string */ -#define CFG_BARGSIZE 1024 -#define CFG_BOOTMAPSZ 0x800000 -#define CFG_CBSIZE 1024 -#define CFG_LOAD_ADDR 0x100000 +#define CFG_BARGSIZE 1024 +#define CFG_BOOTMAPSZ 0x800000 +#define CFG_CBSIZE 1024 +#define CFG_LOAD_ADDR 0x100000 #define CFG_LONGHELP -#define CFG_MAXARGS 16 -#define CFG_MEMTEST_START 0x00040000 -#define CFG_MEMTEST_END 0x00040100 -#define CFG_PBSIZE 1024 -#define CFG_PROMPT "=> " +#define CFG_MAXARGS 16 +#define CFG_MEMTEST_START 0x00040000 +#define CFG_MEMTEST_END 0x00040100 +#define CFG_PBSIZE 1024 +#define CFG_PROMPT "=> " /* @@ -280,12 +281,12 @@ * CFG_ENV_SECT_SIZE - Size of sector containing env vars (32KB) */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0xFFFE0000 -#define CFG_ENV_SIZE 0x1000 -#define CFG_ENV_ADDR_REDUND 0xFFFE8000 -#define CFG_ENV_SIZE_REDUND 0x1000 -#define CFG_ENV_SECT_SIZE 0x8000 +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0xFFFE0000 +#define CFG_ENV_SIZE 0x1000 +#define CFG_ENV_ADDR_REDUND 0xFFFE8000 +#define CFG_ENV_SIZE_REDUND 0x1000 +#define CFG_ENV_SECT_SIZE 0x8000 /* @@ -296,15 +297,15 @@ * copied to top of RAM by the init code. * * CFG_INIT_RAM_ADDR - Address of Init RAM, above exception vect - * CFG_INIT_RAM_END - Size of Init RAM + * CFG_INIT_RAM_END - Size of Init RAM * CFG_GBL_DATA_SIZE - Ammount of RAM to reserve for global data * CFG_GBL_DATA_OFFSET - Start of global data, top of stack */ -#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + 0x4000) -#define CFG_INIT_RAM_END 0x4000 -#define CFG_GBL_DATA_SIZE 128 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + 0x4000) +#define CFG_INIT_RAM_END 0x4000 +#define CFG_GBL_DATA_SIZE 128 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) /* @@ -341,71 +342,71 @@ * Cache config * * CFG_CACHELINE_SIZE - Size of a cache line (CPU specific) - * CFG_L2 - L2 cache enabled if defined - * L2_INIT - L2 cache init flags - * L2_ENABLE - L2 cache enable flags + * CFG_L2 - L2 cache enabled if defined + * L2_INIT - L2 cache init flags + * L2_ENABLE - L2 cache enable flags */ -#define CFG_CACHELINE_SIZE 32 +#define CFG_CACHELINE_SIZE 32 #undef CFG_L2 -#define L2_INIT 0 -#define L2_ENABLE 0 +#define L2_INIT 0 +#define L2_ENABLE 0 /* * Clocks config * - * CFG_BUS_HZ - Bus clock frequency in Hz - * CFG_BUS_CLK - As above (?) - * CFG_HZ - Decrementer freq in Hz + * CFG_BUS_HZ - Bus clock frequency in Hz + * CFG_BUS_CLK - As above (?) + * CFG_HZ - Decrementer freq in Hz */ -#define CFG_BUS_HZ CONFIG_BUS_CLK -#define CFG_BUS_CLK CONFIG_BUS_CLK -#define CFG_HZ 1000 +#define CFG_BUS_HZ CONFIG_BUS_CLK +#define CFG_BUS_CLK CONFIG_BUS_CLK +#define CFG_HZ 1000 /* * Serial port config * * CFG_BAUDRATE_TABLE - List of valid baud rates - * CFG_NS16550 - Include the NS16550 driver + * CFG_NS16550 - Include the NS16550 driver * CFG_NS16550_SERIAL - Include the serial (wrapper) driver - * CFG_NS16550_CLK - Frequency of reference clock + * CFG_NS16550_CLK - Frequency of reference clock * CFG_NS16550_REG_SIZE - 64-bit accesses to 8-bit port - * CFG_NS16550_COM1 - Base address of 1st serial port + * CFG_NS16550_COM1 - Base address of 1st serial port */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CFG_NS16550 #define CFG_NS16550_SERIAL -#define CFG_NS16550_CLK 3686400 +#define CFG_NS16550_CLK 3686400 #define CFG_NS16550_REG_SIZE -8 -#define CFG_NS16550_COM1 0x7C000000 +#define CFG_NS16550_COM1 0x7C000000 /* * PCI Config - Address Map B (CHRP) */ -#define CFG_PCI_MEMORY_BUS 0x00000000 -#define CFG_PCI_MEMORY_PHYS 0x00000000 -#define CFG_PCI_MEMORY_SIZE 0x40000000 -#define CFG_PCI_MEM_BUS 0x80000000 -#define CFG_PCI_MEM_PHYS 0x80000000 -#define CFG_PCI_MEM_SIZE 0x7D000000 -#define CFG_ISA_MEM_BUS 0x00000000 -#define CFG_ISA_MEM_PHYS 0xFD000000 -#define CFG_ISA_MEM_SIZE 0x01000000 -#define CFG_PCI_IO_BUS 0x00800000 -#define CFG_PCI_IO_PHYS 0xFE800000 -#define CFG_PCI_IO_SIZE 0x00400000 -#define CFG_ISA_IO_BUS 0x00000000 -#define CFG_ISA_IO_PHYS 0xFE000000 -#define CFG_ISA_IO_SIZE 0x00800000 +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x40000000 +#define CFG_PCI_MEM_BUS 0x80000000 +#define CFG_PCI_MEM_PHYS 0x80000000 +#define CFG_PCI_MEM_SIZE 0x7D000000 +#define CFG_ISA_MEM_BUS 0x00000000 +#define CFG_ISA_MEM_PHYS 0xFD000000 +#define CFG_ISA_MEM_SIZE 0x01000000 +#define CFG_PCI_IO_BUS 0x00800000 +#define CFG_PCI_IO_PHYS 0xFE800000 +#define CFG_PCI_IO_SIZE 0x00400000 +#define CFG_ISA_IO_BUS 0x00000000 +#define CFG_ISA_IO_PHYS 0xFE000000 +#define CFG_ISA_IO_SIZE 0x00800000 #define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS -#define CFG_ISA_IO CFG_ISA_IO_PHYS -#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS +#define CFG_ISA_IO CFG_ISA_IO_PHYS +#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS /* @@ -420,12 +421,12 @@ /* * Boot flags * - * BOOTFLAG_COLD - Indicates a power-on boot - * BOOTFLAG_WARM - Indicates a software reset + * BOOTFLAG_COLD - Indicates a power-on boot + * BOOTFLAG_WARM - Indicates a software reset */ -#define BOOTFLAG_COLD 0x01 -#define BOOTFLAG_WARM 0x02 +#define BOOTFLAG_COLD 0x01 +#define BOOTFLAG_WARM 0x02 #endif /* __CONFIG_H */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 83a81fec139..1831bef0de1 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -328,7 +328,7 @@ #define CONFIG_I2C_CMD_TREE #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ #define CFG_I2C1_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 #define CFG_I2C_OFFSET CFG_I2C2_OFFSET -- cgit v1.3.1 From b1b54e352028ed370c3aa95d6fdeb9d64c5d2f86 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 2 Aug 2007 21:27:46 +0200 Subject: Coding style cleanup, update CHANGELOG Signed-off-by: Wolfgang Denk --- CHANGELOG | 46 ++++++++++++++++++ board/ads5121/ads5121.c | 4 +- cpu/mpc512x/cpu_init.c | 2 +- cpu/mpc512x/fec.c | 52 ++++++++++----------- cpu/mpc512x/fec.h | 8 ++-- cpu/mpc512x/speed.c | 6 +-- cpu/mpc512x/start.S | 18 +++---- include/configs/ads5121.h | 117 +++++++++++++++++++++++----------------------- include/mpc512x.h | 2 +- 9 files changed, 151 insertions(+), 104 deletions(-) (limited to 'cpu') diff --git a/CHANGELOG b/CHANGELOG index bcbf36e78d2..f8a04e6207e 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,49 @@ +commit 8993e54b6f397973794f3d6f47d3b3c0c98dd4f6 +Author: Rafal Jaworowski +Date: Fri Jul 27 14:43:59 2007 +0200 + + [ADS5121] Support for the ADS5121 board + + The following MPC5121e subsystems are supported: + + - low-level CPU init + - NOR Boot Flash (common CFI driver) + - DDR SDRAM + - FEC + - I2C + - Watchdog + + Signed-off-by: Grzegorz Bernacki + Signed-off-by: Rafal Jaworowski + Signed-off-by: Jan Wrobel + +commit 1863cfb7b100ba0ee3401799457a01dc058745f8 +Author: Rafal Jaworowski +Date: Fri Jul 27 14:22:04 2007 +0200 + + [PPC] Remove unused MSR_USER definition + + Signed-off-by: Rafal Jaworowski + +commit cc3023b9f95d7ac959a764471a65001062aecf41 +Author: Rafal Jaworowski +Date: Thu Jul 19 17:12:28 2007 +0200 + + Fix breakage of 8xx boards from recent commit. + + This patch fixes the negative consequences for 8xx of the recent + "ppc4xx: Clean up 440 exceptions handling" commit. + + Signed-off-by: Rafal Jaworowski + +commit 3a6cab844cf74f76639d795e0be8717e02c86af7 +Author: Wolfgang Denk +Date: Sat Jul 14 22:51:02 2007 +0200 + + Update CHANGELOG + + Signed-off-by: Wolfgang Denk + commit 011595307731a7a67a7445d107c279d031e8ab97 Author: Heiko Schocher Date: Sat Jul 14 01:06:58 2007 +0200 diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 0a99a34ac05..c8bfdb86921 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -114,7 +114,7 @@ long int fixed_sdram (void) * According to MPC5121e RM, configuring local access windows should * be followed by a dummy read of the config register that was * modified last and an isync - */ + */ i = im->sysconf.ddrlaw.ar; __asm__ __volatile__ ("isync"); @@ -183,6 +183,6 @@ int checkboard (void) uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02); printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n", - brd_rev, cpld_rev); + brd_rev, cpld_rev); return 0; } diff --git a/cpu/mpc512x/cpu_init.c b/cpu/mpc512x/cpu_init.c index 566e08b0ddd..d6949f6bba0 100644 --- a/cpu/mpc512x/cpu_init.c +++ b/cpu/mpc512x/cpu_init.c @@ -76,7 +76,7 @@ void cpu_init_f (volatile immap_t * im) * * NOTICE: TB needs to be enabled as early as possible in order to * have udelay() working; if not enabled, usually leads to a hang, like - * during FLASH chip identification etc. + * during FLASH chip identification etc. */ im->sysconf.spcr |= SPCR_TBEN; } diff --git a/cpu/mpc512x/fec.c b/cpu/mpc512x/fec.c index f1b7a2563ed..1c87a53859d 100644 --- a/cpu/mpc512x/fec.c +++ b/cpu/mpc512x/fec.c @@ -77,20 +77,20 @@ static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec) * Trasmit BDs init */ for (ix = 0; ix < FEC_TBD_NUM; ix++) { - fec->bdBase->tbd[ix].status = 0; - } + fec->bdBase->tbd[ix].status = 0; + } - /* - * Have the last TBD to close the ring - */ - fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP; + /* + * Have the last TBD to close the ring + */ + fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP; - /* - * Initialize some indices - */ - fec->tbdIndex = 0; - fec->usedTbdIndex = 0; - fec->cleanTbdNum = FEC_TBD_NUM; + /* + * Initialize some indices + */ + fec->tbdIndex = 0; + fec->usedTbdIndex = 0; + fec->cleanTbdNum = FEC_TBD_NUM; return 0; } @@ -238,7 +238,7 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) fec->eth->r_cntrl = 0x05ee000c; /* Half-duplex, heartbeat disabled */ - fec->eth->x_cntrl = 0x00000000; + fec->eth->x_cntrl = 0x00000000; /* Enable MIB counters */ fec->eth->mib_control = 0x0; @@ -260,7 +260,7 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) /* Initilize addresses and status words of BDs */ mpc512x_fec_bd_init (fec); - /* Descriptor polling active */ + /* Descriptor polling active */ fec->eth->r_des_active = 0x01000000; #if (DEBUG & 0x1) @@ -296,7 +296,7 @@ int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis) * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock * and do not drop the Preamble. */ - fec->eth->mii_speed = (((gd->ipb_clk / 1000000) / 5) + 1) << 1; + fec->eth->mii_speed = (((gd->ipb_clk / 1000000) / 5) + 1) << 1; /* * Reset PHY, then delay 300ns @@ -312,7 +312,7 @@ int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis) printf ("Forcing 10 Mbps ethernet link... "); #endif miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); - + miiphy_write (dev->name, phyAddr, 0x0, 0x0180); timeout = 20; @@ -346,7 +346,7 @@ int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis) #if (DEBUG & 0x2) printf ("done.\n"); #endif - } else { /* MII100 */ + } else { /* MII100 */ /* * Set the auto-negotiation advertisement register bits */ @@ -487,7 +487,7 @@ static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data, pTbd->dataPointer = (uint32)eth_data; pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM; - + /* Activate transmit Buffer Descriptor polling */ fec->eth->x_des_active = 0x01000000; /* Descriptor polling active */ @@ -529,7 +529,7 @@ static int mpc512x_fec_recv (struct eth_device *dev) #if (DEBUG & 0x8) printf( "-" ); #endif - + /* * Check if any critical events have happened */ @@ -555,10 +555,10 @@ static int mpc512x_fec_recv (struct eth_device *dev) } if (!(pRbd->status & FEC_RBD_EMPTY)) { - if ((pRbd->status & FEC_RBD_LAST) && + if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) && ((pRbd->dataLength - 4) > 14)) { - + /* * Get buffer size */ @@ -635,7 +635,7 @@ int mpc512x_fec_initialize (bd_t * bis) * Initialize I\O pins */ reg = (uint32 *) &(im->io_ctrl.regs[PSC0_0_IDX]); - + for (i = 0; i < 15; i++) reg[i] = IOCTRL_MUX_FEC | 0x00000001; @@ -645,13 +645,13 @@ int mpc512x_fec_initialize (bd_t * bis) /* Clean up space FEC's MIB and FIFO RAM ...*/ memset ((void *) MPC512X_FEC + 0x200, 0x00, 0x400); - - /* + + /* * Malloc space for BDs (must be quad word-aligned) - * this pointer is lost, so cannot be freed + * this pointer is lost, so cannot be freed */ bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f); - fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0); + fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0); memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f); /* diff --git a/cpu/mpc512x/fec.h b/cpu/mpc512x/fec.h index 71459197a51..d2d877aa528 100644 --- a/cpu/mpc512x/fec.h +++ b/cpu/mpc512x/fec.h @@ -28,7 +28,7 @@ typedef struct ethernet_register_set { volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */ volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */ volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */ - + volatile uint32 RES1[3]; /* MBAR_ETH + 0x018-020 */ volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */ @@ -42,10 +42,10 @@ typedef struct ethernet_register_set { volatile uint32 RES4[7]; /* MBAR_ETH + 0x068-80 */ volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */ volatile uint32 r_hash; /* MBAR_ETH + 0x088 */ - + volatile uint32 RES5[14]; /* MBAR_ETH + 0x08c-0C0 */ volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */ - + volatile uint32 RES6[7]; /* MBAR_ETH + 0x0C8-0E0 */ volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */ volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */ @@ -63,7 +63,7 @@ typedef struct ethernet_register_set { volatile uint32 RES9[1]; /* MBAR_ETH + 0x148 */ volatile uint32 r_bound; /* MBAR_ETH + 0x14C */ volatile uint32 r_fstart; /* MBAR_ETH + 0x150 */ - + volatile uint32 RES10[11]; /* MBAR_ETH + 0x154-17C */ volatile uint32 r_des_start; /* MBAR_ETH + 0x180 */ volatile uint32 x_des_start; /* MBAR_ETH + 0x184 */ diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c index 9a31155ed2d..a609827387b 100644 --- a/cpu/mpc512x/speed.c +++ b/cpu/mpc512x/speed.c @@ -79,14 +79,14 @@ int get_clocks (void) spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; spll = ref_clk * spmf_mult[spmf]; - + sys_div = (im->clk.scfr[1] & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT; sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0]; csb_clk = sys_clk / 2; - cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT; - core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1]; + cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT; + core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1]; ips_div = (im->clk.scfr[0] & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT; if (ips_div != 0) { diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S index 8b749ac54e9..244c69b8124 100644 --- a/cpu/mpc512x/start.S +++ b/cpu/mpc512x/start.S @@ -208,8 +208,8 @@ boot_cold: */ /* Boot CS/CS0 window range */ - lis r3, CFG_IMMR@h - ori r3, r3, CFG_IMMR@l + lis r3, CFG_IMMR@h + ori r3, r3, CFG_IMMR@l lis r4, START_REG(CFG_FLASH_BASE) ori r4, r4, STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE) @@ -222,11 +222,11 @@ boot_cold: lis r4, START_REG(CFG_SRAM_BASE) & 0xff00 stw r4, SRAMBAR(r3) - /* + /* * According to MPC5121e RM, configuring local access windows should - * be followed by a dummy read of the config register that was + * be followed by a dummy read of the config register that was * modified last and an isync - */ + */ lwz r4, SRAMBAR(r3) isync @@ -235,11 +235,11 @@ boot_cold: * config register so no params can be set for it */ lis r3, (CFG_IMMR + LPC_OFFSET)@h - ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l + ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l - lis r4, CFG_CS0_CFG@h - ori r4, r4, CFG_CS0_CFG@l - stw r4, CS0_CONFIG(r3) + lis r4, CFG_CS0_CFG@h + ori r4, r4, CFG_CS0_CFG@l + stw r4, CS0_CONFIG(r3) /* Master enable all CS's */ lis r4, CS_CTRL_ME@h diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index a1b8eefa02c..89564a90e9e 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -65,48 +65,49 @@ #define CFG_SDRAM_BASE CFG_DDR_BASE /* DDR Controller Configuration - -SYS_CFG: - [31:31] MDDRC Soft Reset: Diabled - [30:30] DRAM CKE pin: Enabled - [29:29] DRAM CLK: Enabled - [28:28] Command Mode: Enabled (For initialization only) - [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] - [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] - [20:19] Read Test: DON'T USE - [18:18] Self Refresh: Enabled - [17:17] 16bit Mode: Disabled - [16:13] Ready Delay: 2 - [12:12] Half DQS Delay: Disabled - [11:11] Quarter DQS Delay: Disabled - [10:08] Write Delay: 2 - [07:07] Early ODT: Disabled - [06:06] On DIE Termination: Disabled - [05:05] FIFO Overflow Clear: DON'T USE here - [04:04] FIFO Underflow Clear: DON'T USE here - [03:03] FIFO Overflow Pending: DON'T USE here - [02:02] FIFO Underlfow Pending: DON'T USE here - [01:01] FIFO Overlfow Enabled: Enabled - [00:00] FIFO Underflow Enabled: Enabled - TIME_CFG0 - [31:16] DRAM Refresh Time: 0 CSB clocks - [15:8] DRAM Command Time: 0 CSB clocks - [07:00] DRAM Precharge Time: 0 CSB clocks - TIME_CFG1 - [31:26] DRAM tRFC: - [25:21] DRAM tWR1: - [20:17] DRAM tWRT1: - [16:11] DRAM tDRR: - [10:05] DRAM tRC: - [04:00] DRAM tRAS: - TIME_CFG2 - [31:28] DRAM tRCD: - [27:23] DRAM tFAW: - [22:19] DRAM tRTW1: - [18:15] DRAM tCCD: - [14:10] DRAM tRTP: - [09:05] DRAM tRP: - [04:00] DRAM tRPA */ + * + * SYS_CFG: + * [31:31] MDDRC Soft Reset: Diabled + * [30:30] DRAM CKE pin: Enabled + * [29:29] DRAM CLK: Enabled + * [28:28] Command Mode: Enabled (For initialization only) + * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] + * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] + * [20:19] Read Test: DON'T USE + * [18:18] Self Refresh: Enabled + * [17:17] 16bit Mode: Disabled + * [16:13] Ready Delay: 2 + * [12:12] Half DQS Delay: Disabled + * [11:11] Quarter DQS Delay: Disabled + * [10:08] Write Delay: 2 + * [07:07] Early ODT: Disabled + * [06:06] On DIE Termination: Disabled + * [05:05] FIFO Overflow Clear: DON'T USE here + * [04:04] FIFO Underflow Clear: DON'T USE here + * [03:03] FIFO Overflow Pending: DON'T USE here + * [02:02] FIFO Underlfow Pending: DON'T USE here + * [01:01] FIFO Overlfow Enabled: Enabled + * [00:00] FIFO Underflow Enabled: Enabled + * TIME_CFG0 + * [31:16] DRAM Refresh Time: 0 CSB clocks + * [15:8] DRAM Command Time: 0 CSB clocks + * [07:00] DRAM Precharge Time: 0 CSB clocks + * TIME_CFG1 + * [31:26] DRAM tRFC: + * [25:21] DRAM tWR1: + * [20:17] DRAM tWRT1: + * [16:11] DRAM tDRR: + * [10:05] DRAM tRC: + * [04:00] DRAM tRAS: + * TIME_CFG2 + * [31:28] DRAM tRCD: + * [27:23] DRAM tFAW: + * [22:19] DRAM tRTW1: + * [18:15] DRAM tCCD: + * [14:10] DRAM tRTP: + * [09:05] DRAM tRP: + * [04:00] DRAM tRPA + */ #define CFG_MDDRC_SYS_CFG 0xF8604200 #define CFG_MDDRC_SYS_CFG_RUN 0xE8604200 @@ -276,7 +277,7 @@ SYS_CFG: #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_NET \ | CFG_CMD_PING \ - | CFG_CMD_MII \ + | CFG_CMD_MII \ | CFG_CMD_I2C) #endif @@ -384,26 +385,26 @@ SYS_CFG: "bootm\0" \ "load=tftp 100000 /tftpboot/ads5121/u-boot.bin\0" \ "update=protect off fff00000 fff3ffff; " \ - "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ + "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ "upd=run load;run update\0" \ "" -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/mpc512x.h b/include/mpc512x.h index 03e0e9a1473..a100b22daf8 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -60,7 +60,7 @@ #define CS_CTRL 0x00020 #define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */ -#define CS_CTRL_IE 0x08000000 /* CS Interrupt Enable bit */ +#define CS_CTRL_IE 0x08000000 /* CS Interrupt Enable bit */ /* SPRIDR - System Part and Revision ID Register */ -- cgit v1.3.1 From 86b116b1b1e165ca4840daefed36d2e3b8460173 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Fri, 3 Aug 2007 12:08:16 +0200 Subject: cm1_qp1 -> cm5200: single U-Boot image for modules from the cm5200 family. Add the ability for modules from the Schindler cm5200 family to use a single U-Boot image: - rename cm1_qp1 to cm5200 - add run-time module detection - parametrize SDRAM configuration according to the module we are running on Few minor, board-specific fixes included in this patch: - better MAC address handling - updated default environment ('update' command uses +{filesize} now) - improved error messages in the auto-update code - allow booting U-Boot from RAM (CFG_RAMBOOT) Signed-off-by: Grzegorz Bernacki Signed-off-by: Piotr Kruszynski Signed-off-by: Bartlomiej Sieka --- MAKEALL | 2 +- Makefile | 9 +- board/cm1_qp1/Makefile | 50 ----- board/cm1_qp1/cm1_qp1.c | 222 ---------------------- board/cm1_qp1/cmd_cm1_qp1.c | 446 ------------------------------------------- board/cm1_qp1/config.mk | 26 --- board/cm1_qp1/fwupdate.c | 187 ------------------ board/cm1_qp1/fwupdate.h | 47 ----- board/cm1_qp1/u-boot.lds | 123 ------------ board/cm5200/Makefile | 50 +++++ board/cm5200/cm5200.c | 425 +++++++++++++++++++++++++++++++++++++++++ board/cm5200/cm5200.h | 184 ++++++++++++++++++ board/cm5200/cmd_cm5200.c | 448 ++++++++++++++++++++++++++++++++++++++++++++ board/cm5200/config.mk | 26 +++ board/cm5200/fwupdate.c | 200 ++++++++++++++++++++ board/cm5200/fwupdate.h | 47 +++++ board/cm5200/u-boot.lds | 123 ++++++++++++ cpu/mpc5xxx/fec.c | 2 +- include/configs/cm1_qp1.h | 358 ----------------------------------- include/configs/cm5200.h | 362 +++++++++++++++++++++++++++++++++++ 20 files changed, 1869 insertions(+), 1468 deletions(-) delete mode 100644 board/cm1_qp1/Makefile delete mode 100644 board/cm1_qp1/cm1_qp1.c delete mode 100644 board/cm1_qp1/cmd_cm1_qp1.c delete mode 100644 board/cm1_qp1/config.mk delete mode 100644 board/cm1_qp1/fwupdate.c delete mode 100644 board/cm1_qp1/fwupdate.h delete mode 100644 board/cm1_qp1/u-boot.lds create mode 100644 board/cm5200/Makefile create mode 100644 board/cm5200/cm5200.c create mode 100644 board/cm5200/cm5200.h create mode 100644 board/cm5200/cmd_cm5200.c create mode 100644 board/cm5200/config.mk create mode 100644 board/cm5200/fwupdate.c create mode 100644 board/cm5200/fwupdate.h create mode 100644 board/cm5200/u-boot.lds delete mode 100644 include/configs/cm1_qp1.h create mode 100644 include/configs/cm5200.h (limited to 'cpu') diff --git a/MAKEALL b/MAKEALL index 2a03b687083..c69dc1b3c47 100755 --- a/MAKEALL +++ b/MAKEALL @@ -35,7 +35,7 @@ LIST_5xx=" \ ######################################################################### LIST_5xxx=" \ - BC3450 cm1_qp1 cpci5200 EVAL5200 \ + BC3450 cm5200 cpci5200 EVAL5200 \ fo300 icecube_5100 icecube_5200 lite5200b \ mcc200 mecp5200 motionpro o2dnt \ pf5200 PM520 TB5200 Total5100 \ diff --git a/Makefile b/Makefile index 5b87aad5b9f..7f5aefe4734 100644 --- a/Makefile +++ b/Makefile @@ -532,13 +532,8 @@ PM520_ROMBOOT_DDR_config: unconfig smmaco4_config: unconfig @$(MKCONFIG) -a smmaco4 ppc mpc5xxx tqm5200 -cm1_qp1_config: unconfig - @ >include/config.h - @[ -z "$(findstring cm1_qp1,$@)" ] || \ - { echo "... with 64 MByte SDRAM" ; \ - echo "... with 32 MByte Flash" ; \ - } - @./mkconfig -a cm1_qp1 ppc mpc5xxx cm1_qp1 +cm5200_config: unconfig + @./mkconfig -a cm5200 ppc mpc5xxx cm5200 spieval_config: unconfig @$(MKCONFIG) -a spieval ppc mpc5xxx tqm5200 diff --git a/board/cm1_qp1/Makefile b/board/cm1_qp1/Makefile deleted file mode 100644 index e7393267e7a..00000000000 --- a/board/cm1_qp1/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2003-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := $(BOARD).o cmd_cm1_qp1.o fwupdate.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/cm1_qp1/cm1_qp1.c b/board/cm1_qp1/cm1_qp1.c deleted file mode 100644 index b49298f64b6..00000000000 --- a/board/cm1_qp1/cm1_qp1.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * (C) Copyright 2003-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2004-2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#ifdef CONFIG_OF_FLAT_TREE -#include -#endif /* CONFIG_OF_FLAT_TREE */ - -#include "fwupdate.h" - -#ifndef CFG_RAMBOOT -/* - * Helper function to initialize SDRAM controller. - */ -static void sdram_start(int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | - hi_addr_bit; - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | - hi_addr_bit; - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | - hi_addr_bit; - - /* auto refresh, second time */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | - hi_addr_bit; - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; -} -#endif /* CFG_RAMBOOT */ - -/* - * Initalize SDRAM - configure SDRAM controller, detect memory size. - */ -long int initdram(int board_type) -{ - ulong dramsize = 0; -#ifndef CFG_RAMBOOT - ulong test1, test2; - - /* configure SDRAM start/end for detection */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else - dramsize = test2; - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + - __builtin_ffs(dramsize >> 20) - 1; - } else - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ -#else /* CFG_RAMBOOT */ - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) - dramsize = (1 << (dramsize - 0x13)) << 20; - else - dramsize = 0; -#endif /* CFG_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Refer to chapter 8.7.5 SDelay--MBAR + 0x0190 of - * the MPC5200B User's Manual. - */ - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; - __asm__ volatile ("sync"); - - return dramsize; -} - - -int checkboard(void) -{ - puts("Board: CM1.QP1\n"); - return 0; -} - - -int board_early_init_r(void) -{ - /* - * Now, when we are in RAM, enable flash write access for detection - * process. Note that CS_BOOT cannot be cleared when executing in - * flash. - */ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ - return 0; -} - - -#ifdef CONFIG_POST -int post_hotkeys_pressed(void) -{ - return 0; -} -#endif /* CONFIG_POST */ - - -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) -void post_word_store(ulong a) -{ - vu_long *save_addr = (vu_long *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); - *save_addr = a; -} - - -ulong post_word_load(void) -{ - vu_long *save_addr = (vu_long *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); - return *save_addr; -} -#endif /* CONFIG_POST || CONFIG_LOGBUFFER */ - - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) - uchar buf[6]; - char str[18]; - - /* Read ethaddr from EEPROM */ - if (i2c_read(CFG_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) { - sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", - buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); - /* Check if MAC addr is owned by Schindler */ - if (strstr(str, "00:06:C3") != str) { - printf(LOG_PREFIX "Warning - Illegal MAC address (%s)" - " in EEPROM.\n", str); - printf(LOG_PREFIX "Using MAC from environment\n"); - } else { - printf(LOG_PREFIX "Using MAC (%s) from I2C EEPROM\n", - str); - setenv("ethaddr", str); - } - } else { - printf(LOG_PREFIX "Warning - Unable to read MAC from I2C" - " device at address %02X:%04X\n", CFG_I2C_EEPROM, - CONFIG_MAC_OFFSET); - printf(LOG_PREFIX "Using MAC from environment\n"); - } - return 0; -#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) */ -} -#endif /* CONFIG_MISC_INIT_R */ - - -#ifdef CONFIG_LAST_STAGE_INIT -int last_stage_init(void) -{ -#ifdef CONFIG_USB_STORAGE - cm1_fwupdate(); -#endif /* CONFIG_USB_STORAGE */ - return 0; -} -#endif /* CONFIG_LAST_STAGE_INIT */ - - -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -} -#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/cm1_qp1/cmd_cm1_qp1.c b/board/cm1_qp1/cmd_cm1_qp1.c deleted file mode 100644 index 4a01d2a7f4c..00000000000 --- a/board/cm1_qp1/cmd_cm1_qp1.c +++ /dev/null @@ -1,446 +0,0 @@ -/* - * (C) Copyright 2007 Markus Kappeler - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_BSP) - -int do_i2c(char *argv[]) -{ - unsigned char temp, temp1; - - printf("Starting I2C Test\n" - "Please set Jumper:\nI2C SDA 2-3\nI2C SCL 2-3\n\n" - "Please press any key to start\n\n"); - getc(); - - temp = 0xf0; /* set io 0-4 as output */ - i2c_write(CFG_I2C_IO, 3, 1, (uchar *)&temp, 1); - - printf("Press I2C4-7. LED I2C0-3 should have the same state\n\n" - "Press any key to stop\n\n"); - - while (!tstc()) { - i2c_read(CFG_I2C_IO, 0, 1, (uchar *)&temp, 1); - temp1 = (temp >> 4) & 0x03; - temp1 |= (temp >> 3) & 0x08; /* S302 -> LED303 */ - temp1 |= (temp >> 5) & 0x04; /* S303 -> LED302 */ - temp = temp1; - i2c_write(CFG_I2C_IO, 1, 1, (uchar *)&temp, 1); - } - getc(); - - return 0; -} - -int do_usbtest(char *argv[]) -{ - int i; - static int usb_stor_curr_dev = -1; /* current device */ - - printf("Starting USB Test\n" - "Please insert USB Memmory Stick\n\n" - "Please press any key to start\n\n"); - getc(); - - usb_stop(); - printf("(Re)start USB...\n"); - i = usb_init(); -#ifdef CONFIG_USB_STORAGE - /* try to recognize storage devices immediately */ - if (i >= 0) - usb_stor_curr_dev = usb_stor_scan(1); -#endif /* CONFIG_USB_STORAGE */ - if (usb_stor_curr_dev >= 0) - printf("Found USB Storage Dev continue with Test...\n"); - else { - printf("No USB Storage Device detected.. Stop Test\n"); - return 1; - } - - usb_stor_info(); - - printf("stopping USB..\n"); - usb_stop(); - - return 0; -} - -int do_led(char *argv[]) -{ - int i = 0; - struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; - - printf("Starting LED Test\n" - "Please set Switch S500 all off\n\n" - "Please press any key to start\n\n"); - getc(); - - /* configure timer 2-3 for simple GPIO output High */ - gpt->gpt2.emsr |= 0x00000034; - gpt->gpt3.emsr |= 0x00000034; - - (*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x80000000; - (*(vu_long *)MPC5XXX_WU_GPIO_DIR) |= 0x80000000; - printf("Please press any key to stop\n\n"); - while (!tstc()) { - if (i == 1) { - (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000; - gpt->gpt2.emsr &= ~0x00000010; - gpt->gpt3.emsr &= ~0x00000010; - } else if (i == 2) { - (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000; - gpt->gpt2.emsr &= ~0x00000010; - gpt->gpt3.emsr |= 0x00000010; - } else if (i >= 3) { - (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000; - gpt->gpt3.emsr &= ~0x00000010; - gpt->gpt2.emsr |= 0x00000010; - i = 0; - } - i++; - udelay(200000); - } - getc(); - - (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000; - gpt->gpt2.emsr |= 0x00000010; - gpt->gpt3.emsr |= 0x00000010; - - return 0; -} - -int do_rs232(char *argv[]) -{ - int error_status = 0; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1; - - /* Configure PSC 2-3-6 as GPIO */ - gpio->port_config &= 0xFF0FF80F; - - switch (simple_strtoul(argv[2], NULL, 10)) { - case 1: - /* check RTS <-> CTS loop */ - /* set rts to 0 */ - printf("Uart 1 test: RX TX tested by using U-Boot\n" - "Please connect RTS with CTS on Uart1 plug\n\n" - "Press any key to start\n\n"); - getc(); - - psc1->op1 |= 0x01; - - /* wait some time before requesting status */ - udelay(10); - - /* check status at cts */ - if ((psc1->ip & 0x01) != 0) { - error_status = 3; - printf("%s: failure at rs232_1, cts status is %d " - "(should be 0)\n", - __FUNCTION__, (psc1->ip & 0x01)); - } - - /* set rts to 1 */ - psc1->op0 |= 0x01; - - /* wait some time before requesting status */ - udelay(10); - - /* check status at cts */ - if ((psc1->ip & 0x01) != 1) { - error_status = 3; - printf("%s: failure at rs232_1, cts status is %d " - "(should be 1)\n", - __FUNCTION__, (psc1->ip & 0x01)); - } - break; - case 2: - /* set PSC2_0, PSC2_2 as output and PSC2_1, PSC2_3 as input */ - printf("Uart 2 test: Please use RS232 Loopback plug on UART2\n" - "\nPress any key to start\n\n"); - getc(); - - gpio->simple_gpioe &= ~(0x000000F0); - gpio->simple_gpioe |= 0x000000F0; - gpio->simple_ddr &= ~(0x000000F0); - gpio->simple_ddr |= 0x00000050; - - /* check TXD <-> RXD loop */ - /* set TXD to 1 */ - gpio->simple_dvo |= (1 << 4); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000020) != 0x00000020) { - error_status = 2; - printf("%s: failure at rs232_2, rxd status is %d " - "(should be 1)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000020) >> 5); - } - - /* set TXD to 0 */ - gpio->simple_dvo &= ~(1 << 4); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000020) != 0x00000000) { - error_status = 2; - printf("%s: failure at rs232_2, rxd status is %d " - "(should be 0)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000020) >> 5); - } - - /* check RTS <-> CTS loop */ - /* set RTS to 1 */ - gpio->simple_dvo |= (1 << 6); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000080) != 0x00000080) { - error_status = 3; - printf("%s: failure at rs232_2, cts status is %d " - "(should be 1)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000080) >> 7); - } - - /* set RTS to 0 */ - gpio->simple_dvo &= ~(1 << 6); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000080) != 0x00000000) { - error_status = 3; - printf("%s: failure at rs232_2, cts status is %d " - "(should be 0)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000080) >> 7); - } - break; - case 3: - /* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */ - printf("Uart 3 test: Please use RS232 Loopback plug on UART2\n" - "\nPress any key to start\n\n"); - getc(); - - gpio->simple_gpioe &= ~(0x00000F00); - gpio->simple_gpioe |= 0x00000F00; - - gpio->simple_ddr &= ~(0x00000F00); - gpio->simple_ddr |= 0x00000500; - - /* check TXD <-> RXD loop */ - /* set TXD to 1 */ - gpio->simple_dvo |= (1 << 8); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000200) != 0x00000200) { - error_status = 2; - printf("%s: failure at rs232_3, rxd status is %d " - "(should be 1)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000200) >> 9); - } - - /* set TXD to 0 */ - gpio->simple_dvo &= ~(1 << 8); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000200) != 0x00000000) { - error_status = 2; - printf("%s: failure at rs232_3, rxd status is %d " - "(should be 0)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000200) >> 9); - } - - /* check RTS <-> CTS loop */ - /* set RTS to 1 */ - gpio->simple_dvo |= (1 << 10); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000800) != 0x00000800) { - error_status = 3; - printf("%s: failure at rs232_3, cts status is %d " - "(should be 1)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000800) >> 11); - } - - /* set RTS to 0 */ - gpio->simple_dvo &= ~(1 << 10); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000800) != 0x00000000) { - error_status = 3; - printf("%s: failure at rs232_3, cts status is %d " - "(should be 0)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000800) >> 11); - } - break; - case 4: - /* set PSC6_2, PSC6_3 as output and PSC6_0, PSC6_1 as input */ - printf("Uart 4 test: Please use RS232 Loopback plug on UART2\n" - "\nPress any key to start\n\n"); - getc(); - - gpio->simple_gpioe &= ~(0xF0000000); - gpio->simple_gpioe |= 0x30000000; - - gpio->simple_ddr &= ~(0xf0000000); - gpio->simple_ddr |= 0x30000000; - - (*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x30000000; - (*(vu_long *)MPC5XXX_WU_GPIO_DIR) &= ~(0x30000000); - - /* check TXD <-> RXD loop */ - /* set TXD to 1 */ - gpio->simple_dvo |= (1 << 28); - - /* wait some time before requesting status */ - udelay(10); - - if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) != - 0x10000000) { - error_status = 2; - printf("%s: failure at rs232_4, rxd status is %d " - "(should be 1)\n", __FUNCTION__, - ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & - 0x10000000) >> 28); - } - - /* set TXD to 0 */ - gpio->simple_dvo &= ~(1 << 28); - - /* wait some time before requesting status */ - udelay(10); - - if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) != - 0x00000000) { - error_status = 2; - printf("%s: failure at rs232_4, rxd status is %d " - "(should be 0)\n", __FUNCTION__, - ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & - 0x10000000) >> 28); - } - - /* check RTS <-> CTS loop */ - /* set RTS to 1 */ - gpio->simple_dvo |= (1 << 29); - - /* wait some time before requesting status */ - udelay(10); - - if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) != - 0x20000000) { - error_status = 3; - printf("%s: failure at rs232_4, cts status is %d " - "(should be 1)\n", __FUNCTION__, - ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & - 0x20000000) >> 29); - } - - /* set RTS to 0 */ - gpio->simple_dvo &= ~(1 << 29); - - /* wait some time before requesting status */ - udelay(10); - - if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) != - 0x00000000) { - error_status = 3; - printf("%s: failure at rs232_4, cts status is %d " - "(should be 0)\n", __FUNCTION__, - ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & - 0x20000000) >> 29); - } - break; - default: - printf("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]); - error_status = 1; - break; - } - gpio->port_config |= (CFG_GPS_PORT_CONFIG & 0xFF0FF80F); - - return error_status; -} - -int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int rcode = -1; - - switch (argc) { - case 2: - if (strncmp(argv[1], "i2c", 3) == 0) - rcode = do_i2c(argv); - else if (strncmp(argv[1], "led", 3) == 0) - rcode = do_led(argv); - else if (strncmp(argv[1], "usb", 3) == 0) - rcode = do_usbtest(argv); - break; - case 3: - if (strncmp(argv[1], "rs232", 3) == 0) - rcode = do_rs232(argv); - break; - } - - switch (rcode) { - case -1: - printf("Usage:\n" - "fkt { i2c | led | usb }\n" - "fkt rs232 number\n"); - rcode = 1; - break; - case 0: - printf("Test passed\n"); - break; - default: - printf("Test failed with code: %d\n", rcode); - } - - return rcode; -} - -U_BOOT_CMD( - fkt, 4, 1, cmd_fkt, - "fkt - Function test routines\n", - "i2c\n" - " - Test I2C communication\n" - "fkt led\n" - " - Test LEDs\n" - "fkt rs232 number\n" - " - Test RS232 (loopback plug(s) for RS232 required)\n" - "fkt usb\n" - " - Test USB communication\n" -); -#endif /* CFG_CMD_BSP */ diff --git a/board/cm1_qp1/config.mk b/board/cm1_qp1/config.mk deleted file mode 100644 index 7f061391a24..00000000000 --- a/board/cm1_qp1/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0xfc000000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/cm1_qp1/fwupdate.c b/board/cm1_qp1/fwupdate.c deleted file mode 100644 index 637375e5989..00000000000 --- a/board/cm1_qp1/fwupdate.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * (C) Copyright 2007 Schindler Lift Inc. - * (C) Copyright 2007 Semihalf - * - * Author: Michel Marti - * Adapted for U-Boot 1.2 by Piotr Kruszynski : - * - code clean-up - * - bugfix for overwriting bootargs by user - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -#include "fwupdate.h" - -extern int do_bootm(cmd_tbl_t *, int, int, char *[]); -extern long do_fat_read(const char *, void *, unsigned long, int); -extern int do_fat_fsload(cmd_tbl_t *, int, int, char *[]); - -static int load_rescue_image(ulong); - -void cm1_fwupdate(void) -{ - cmd_tbl_t *bcmd; - char *rsargs; - char *tmp = NULL; - char ka[16]; - char *argv[3] = { "bootm", ka, NULL }; - - /* Check if rescue system is disabled... */ - if (getenv("norescue")) { - printf(LOG_PREFIX "Rescue System disabled.\n"); - return; - } - - /* Check if we have a USB storage device and load image */ - if (load_rescue_image(LOAD_ADDR)) - return; - - bcmd = find_cmd("bootm"); - if (!bcmd) - return; - - sprintf(ka, "%lx", LOAD_ADDR); - - /* prepare our bootargs */ - rsargs = getenv("rs-args"); - if (!rsargs) - rsargs = RS_BOOTARGS; - else { - tmp = malloc(strlen(rsargs+1)); - if (!tmp) { - printf(LOG_PREFIX "Memory allocation failed\n"); - return; - } - strcpy(tmp, rsargs); - rsargs = tmp; - } - - setenv("bootargs", rsargs); - - if (rsargs == tmp) - free(rsargs); - - printf(LOG_PREFIX "Starting update system (bootargs=%s)...\n", rsargs); - do_bootm(bcmd, 0, 2, argv); -} - -static int load_rescue_image(ulong addr) -{ - disk_partition_t info; - int devno; - int partno; - int i; - char fwdir[64]; - char nxri[128]; - char *tmp; - char dev[7]; - char addr_str[16]; - char *argv[6] = { "fatload", "usb", dev, addr_str, nxri, NULL }; - block_dev_desc_t *stor_dev = NULL; - cmd_tbl_t *bcmd; - - /* Get name of firmware directory */ - tmp = getenv("fw-dir"); - - /* Copy it into fwdir */ - strncpy(fwdir, tmp ? tmp : FW_DIR, sizeof(fwdir)); - fwdir[sizeof(fwdir) - 1] = 0; /* Terminate string */ - - printf(LOG_PREFIX "Checking for firmware image directory '%s' on USB" - " storage...\n", fwdir); - usb_stop(); - if (usb_init() != 0) - return 1; - - /* Check for storage device */ - if (usb_stor_scan(1) != 0) { - usb_stop(); - return 1; - } - - /* Detect storage device */ - for (devno = 0; devno < USB_MAX_STOR_DEV; devno++) { - stor_dev = usb_stor_get_dev(devno); - if (stor_dev->type != DEV_TYPE_UNKNOWN) - break; - } - if (!stor_dev || stor_dev->type == DEV_TYPE_UNKNOWN) { - printf(LOG_PREFIX "No valid storage device found...\n"); - usb_stop(); - return 1; - } - - /* Detect partition */ - for (partno = -1, i = 0; i < 6; i++) { - if (get_partition_info(stor_dev, i, &info) == 0) { - if (fat_register_device(stor_dev, i) == 0) { - /* Check if rescue image is present */ - FW_DEBUG("Looking for firmware directory '%s'" - " on partition %d\n", fwdir, i); - if (do_fat_read(fwdir, NULL, 0, LS_NO) == -1) { - FW_DEBUG("No NX rescue image on " - "partition %d.\n", i); - } else { - partno = i; - FW_DEBUG("Partition %d contains " - "firmware directory\n", partno); - break; - } - } - } - } - - if (partno == -1) { - printf(LOG_PREFIX "Error: No valid (FAT) partition detected\n"); - usb_stop(); - return 1; - } - - /* Load the rescue image */ - bcmd = find_cmd("fatload"); - if (!bcmd) { - printf(LOG_PREFIX "Error - 'fatload' command not present.\n"); - usb_stop(); - return 1; - } - - tmp = getenv("nx-rescue-image"); - sprintf(nxri, "%s/%s", fwdir, tmp ? tmp : RESCUE_IMAGE); - sprintf(dev, "%d:%d", devno, partno); - sprintf(addr_str, "%lx", addr); - - FW_DEBUG("fat_fsload device='%s', addr='%s', file: %s\n", - dev, addr_str, nxri); - - if (do_fat_fsload(bcmd, 0, 5, argv) != 0) { - usb_stop(); - return 1; - } - - /* Stop USB */ - usb_stop(); - return 0; -} diff --git a/board/cm1_qp1/fwupdate.h b/board/cm1_qp1/fwupdate.h deleted file mode 100644 index 119c2d691c8..00000000000 --- a/board/cm1_qp1/fwupdate.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2007 Schindler Lift Inc. - * - * Author: Michel Marti - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __FW_UPDATE_H -#define __FW_UPDATE_H - -/* Default prefix for output messages */ -#define LOG_PREFIX "CM1: " - -/* Extra debug macro */ -#ifdef CONFIG_FWUPDATE_DEBUG -#define FW_DEBUG(fmt...) printf(LOG_PREFIX fmt) -#else -#define FW_DEBUG(fmt...) -#endif - -/* Name of the directory holding firmware images */ -#define FW_DIR "nx-fw" -#define RESCUE_IMAGE "nxrs.img" -#define LOAD_ADDR 0x400000 -#define RS_BOOTARGS "ramdisk=8192K" - -/* Main function for fwupdate */ -void cm1_fwupdate(void); - -#endif /* __FW_UPDATE_H */ diff --git a/board/cm1_qp1/u-boot.lds b/board/cm1_qp1/u-boot.lds deleted file mode 100644 index 8fa9c0f7ed5..00000000000 --- a/board/cm1_qp1/u-boot.lds +++ /dev/null @@ -1,123 +0,0 @@ -/* - * (C) Copyright 2003-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc5xxx/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/cm5200/Makefile b/board/cm5200/Makefile new file mode 100644 index 00000000000..8ebdb1aa28b --- /dev/null +++ b/board/cm5200/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2003-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o cmd_cm5200.o fwupdate.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c new file mode 100644 index 00000000000..6804e33c27e --- /dev/null +++ b/board/cm5200/cm5200.c @@ -0,0 +1,425 @@ +/* + * (C) Copyright 2003-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * (C) Copyright 2004-2005 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * Adapted to U-Boot 1.2 by: + * Bartlomiej Sieka : + * - HW ID readout from EEPROM + * - module detection + * Grzegorz Bernacki : + * - run-time SDRAM controller configuration + * - LIBFDT support + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_OF_LIBFDT +#include +#include +#include +#endif /* CONFIG_OF_LIBFDT */ + + +#include "cm5200.h" +#include "fwupdate.h" + +DECLARE_GLOBAL_DATA_PTR; + +static hw_id_t hw_id; + + +#ifndef CFG_RAMBOOT +/* + * Helper function to initialize SDRAM controller. + */ +static void sdram_start(int hi_addr, mem_conf_t *mem_conf) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000000 | + hi_addr_bit; + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000002 | + hi_addr_bit; + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 | + hi_addr_bit; + + /* auto refresh, second time */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 | + hi_addr_bit; + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = mem_conf->mode; + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | hi_addr_bit; +} +#endif /* CFG_RAMBOOT */ + + +/* + * Retrieve memory configuration for a given module. board_type is the index + * in hw_id_list[] corresponding to the module we are executing on; we return + * SDRAM controller settings approprate for this module. + */ +static mem_conf_t* get_mem_config(int board_type) +{ + switch(board_type){ + case CM1_QA: + return memory_config[0]; + case CM11_QA: + case CMU1_QA: + return memory_config[1]; + default: + printf("ERROR: Unknown module, using a default SDRAM " + "configuration - things may not work!!!.\n"); + return memory_config[0]; + } +} + + +/* + * Initalize SDRAM - configure SDRAM controller, detect memory size. + */ +long int initdram(int board_type) +{ + ulong dramsize = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + mem_conf_t *mem_conf; + + mem_conf = get_mem_config(board_type); + + /* configure SDRAM start/end for detection */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = mem_conf->config1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = mem_conf->config2; + + sdram_start(0, mem_conf); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1, mem_conf); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0, mem_conf); + dramsize = test1; + } else + dramsize = test2; + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) + dramsize = 0; + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + + __builtin_ffs(dramsize >> 20) - 1; + } else + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ +#else /* CFG_RAMBOOT */ + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) + dramsize = (1 << (dramsize - 0x13)) << 20; + else + dramsize = 0; +#endif /* !CFG_RAMBOOT */ + + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Refer to chapter 8.7.5 SDelay--MBAR + 0x0190 of + * the MPC5200B User's Manual. + */ + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + + return dramsize; +} + + +/* + * Read module hardware identification data from the I2C EEPROM. + */ +static void read_hw_id(hw_id_t hw_id) +{ + int i; + for (i = 0; i < HW_ID_ELEM_COUNT; ++i) + if (i2c_read(CFG_I2C_EEPROM, + hw_id_format[i].offset, + 2, + (uchar *)&hw_id[i][0], + hw_id_format[i].length) != 0) + printf("ERROR: can't read HW ID from EEPROM\n"); +} + + +/* + * Identify module we are running on, set gd->board_type to the index in + * hw_id_list[] corresponding to the module identifed, or to + * CM5200_UNKNOWN_MODULE if we can't identify the module. + */ +static void identify_module(hw_id_t hw_id) +{ + int i, j, element; + char match; + gd->board_type = CM5200_UNKNOWN_MODULE; + for (i = 0; i < sizeof (hw_id_list) / sizeof (char **); ++i) { + match = 1; + for (j = 0; j < sizeof (hw_id_identify) / sizeof (int); ++j) { + element = hw_id_identify[j]; + if (strncmp(hw_id_list[i][element], + &hw_id[element][0], + hw_id_format[element].length) != 0) { + match = 0; + break; + } + } + if (match) { + gd->board_type = i; + break; + } + } +} + + +/* + * Compose string with module name. + * buf is assumed to have enough space, and be null-terminated. + */ +static void compose_module_name(hw_id_t hw_id, char *buf) +{ + char tmp[MODULE_NAME_MAXLEN]; + strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length); + strncat(buf, ".", 1); + strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length); + strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length); + strncat(buf, " (", 2); + strncat(buf, &hw_id[IDENTIFICATION_NUMBER][0], + hw_id_format[IDENTIFICATION_NUMBER].length); + sprintf(tmp, " / %u.%u)", + hw_id[MAJOR_SW_VERSION][0], + hw_id[MINOR_SW_VERSION][0]); + strcat(buf, tmp); +} + + +/* + * Compose string with hostname. + * buf is assumed to have enough space, and be null-terminated. + */ +static void compose_hostname(hw_id_t hw_id, char *buf) +{ + char *p; + strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length); + strncat(buf, "_", 1); + strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length); + strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length); + for (p = buf; *p; ++p) + *p = tolower(*p); + +} + + +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +/* + * Update 'model' and 'memory' properties in the blob according to the module + * that we are running on. + */ +static void ft_blob_update(void *blob, bd_t *bd) +{ + int len, ret, nodeoffset = 0; + char module_name[MODULE_NAME_MAXLEN] = {0}; + ulong memory_data[2] = {0}; + + compose_module_name(hw_id, module_name); + len = strlen(module_name) + 1; + + ret = fdt_setprop(blob, nodeoffset, "model", module_name, len); + if (ret < 0) + printf("ft_blob_update(): cannot set /model property err:%s\n", + fdt_strerror(ret)); + + memory_data[0] = cpu_to_be32(bd->bi_memstart); + memory_data[1] = cpu_to_be32(bd->bi_memsize); + + nodeoffset = fdt_find_node_by_path (blob, "/memory"); + if (nodeoffset >= 0) { + ret = fdt_setprop(blob, nodeoffset, "reg", memory_data, + sizeof(memory_data)); + if (ret < 0) + printf("ft_blob_update): cannot set /memory/reg " + "property err:%s\n", fdt_strerror(ret)); + } + else { + /* memory node is required in dts */ + printf("ft_blob_update(): cannot find /memory node " + "err:%s\n", fdt_strerror(nodeoffset)); + } +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ + + +/* + * Read HW ID from I2C EEPROM and detect the modue we are running on. Note + * that we need to use local variable for readout, because global data is not + * writable yet (and we'll have to redo the readout later on). + */ +int checkboard(void) +{ + hw_id_t hw_id_tmp; + char module_name_tmp[MODULE_NAME_MAXLEN] = ""; + + /* + * We need I2C to access HW ID data from EEPROM, so we call i2c_init() + * here despite the fact that it will be called again later on. We + * also use a little trick to silence I2C-related output. + */ + gd->flags |= GD_FLG_SILENT; + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + gd->flags &= ~GD_FLG_SILENT; + + read_hw_id(hw_id_tmp); + identify_module(hw_id_tmp); /* this sets gd->board_type */ + compose_module_name(hw_id_tmp, module_name_tmp); + + if (gd->board_type != CM5200_UNKNOWN_MODULE) + printf("Board: %s\n", module_name_tmp); + else + printf("Board: unrecognized cm5200 module (%s)\n", + module_name_tmp); + + return 0; +} + + +int board_early_init_r(void) +{ + /* + * Now, when we are in RAM, enable flash write access for detection + * process. Note that CS_BOOT cannot be cleared when executing in + * flash. + */ + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ + + /* Now that we can write to global data, read HW ID again. */ + read_hw_id(hw_id); + return 0; +} + + +#ifdef CONFIG_POST +int post_hotkeys_pressed(void) +{ + return 0; +} +#endif /* CONFIG_POST */ + + +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) +void post_word_store(ulong a) +{ + vu_long *save_addr = (vu_long *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); + *save_addr = a; +} + + +ulong post_word_load(void) +{ + vu_long *save_addr = (vu_long *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); + return *save_addr; +} +#endif /* CONFIG_POST || CONFIG_LOGBUFFER */ + + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) + uchar buf[6]; + char str[18]; + char hostname[MODULE_NAME_MAXLEN]; + + /* Read ethaddr from EEPROM */ + if (i2c_read(CFG_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) { + sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); + /* Check if MAC addr is owned by Schindler */ + if (strstr(str, "00:06:C3") != str) + printf(LOG_PREFIX "Warning - Illegal MAC address (%s)" + " in EEPROM.\n", str); + else { + printf(LOG_PREFIX "Using MAC (%s) from I2C EEPROM\n", + str); + setenv("ethaddr", str); + } + } else { + printf(LOG_PREFIX "Warning - Unable to read MAC from I2C" + " device at address %02X:%04X\n", CFG_I2C_EEPROM, + CONFIG_MAC_OFFSET); + } +#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) */ + if (!getenv("ethaddr")) + printf(LOG_PREFIX "MAC address not set, networking is not " + "operational\n"); + + /* set the hostname appropriate to the module we're running on */ + compose_hostname(hw_id, hostname); + setenv("hostname", hostname); + + return 0; +} +#endif /* CONFIG_MISC_INIT_R */ + + +#ifdef CONFIG_LAST_STAGE_INIT +int last_stage_init(void) +{ +#ifdef CONFIG_USB_STORAGE + cm5200_fwupdate(); +#endif /* CONFIG_USB_STORAGE */ + return 0; +} +#endif /* CONFIG_LAST_STAGE_INIT */ + + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + ft_blob_update(blob, bd); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/cm5200/cm5200.h b/board/cm5200/cm5200.h new file mode 100644 index 00000000000..a6cbc88f47c --- /dev/null +++ b/board/cm5200/cm5200.h @@ -0,0 +1,184 @@ +/* + * (C) Copyright 2007 DENX Software Engineering + * + * Author: Bartlomiej Sieka + * Author: Grzegorz Bernacki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _CM5200_H +#define _CM5200_H + + +/* + * Definitions and declarations for the modules of the cm5200 platform. Mostly + * related to reading the hardware identification data (HW ID) from the I2C + * EEPROM, detection of the particular module we are executing on, and + * appropriate SDRAM controller initialization. + */ + + +#define CM5200_UNKNOWN_MODULE 0xffffffff + +enum { + DEVICE_NAME, /* 0 */ + GENERATION, /* 1 */ + PCB_NAME, /* 2 */ + FORM, /* 3 */ + VERSION, /* 4 */ + IDENTIFICATION_NUMBER, /* 5 */ + MAJOR_SW_VERSION, /* 6 */ + MINOR_SW_VERSION, /* 7 */ + /* add new alements above this line */ + HW_ID_ELEM_COUNT /* count */ +}; + +/* + * Sect. 4.1 "CM1.Q/CMU1.Q Supervisory Microcontroller Interface Definition" + */ + +#define DEVICE_NAME_OFFSET 0x02 +#define GENERATION_OFFSET 0x0b +#define PCB_NAME_OFFSET 0x0c +#define FORM_OFFSET 0x15 +#define VERSION_OFFSET 0x16 +#define IDENTIFICATION_NUMBER_OFFSET 0x19 +#define MAJOR_SW_VERSION_OFFSET 0x0480 +#define MINOR_SW_VERSION_OFFSET 0x0481 + + +#define DEVICE_NAME_LEN 0x09 +#define GENERATION_LEN 0x01 +#define PCB_NAME_LEN 0x09 +#define FORM_LEN 0x01 +#define VERSION_LEN 0x03 +#define IDENTIFICATION_NUMBER_LEN 0x09 +#define MAJOR_SW_VERSION_LEN 0x01 +#define MINOR_SW_VERSION_LEN 0x01 + +#define HW_ID_ELEM_MAXLEN 0x09 /* MAX(XXX_LEN) */ + +/* entire HW ID in EEPROM is 64 bytes, so longer module name is unlikely */ +#define MODULE_NAME_MAXLEN 64 + + +/* storage for HW ID read from EEPROM */ +typedef char hw_id_t[HW_ID_ELEM_COUNT][HW_ID_ELEM_MAXLEN]; + + +/* HW ID layout in EEPROM */ +static struct { + unsigned int offset; + unsigned int length; +} hw_id_format[HW_ID_ELEM_COUNT] = { + {DEVICE_NAME_OFFSET, DEVICE_NAME_LEN}, + {GENERATION_OFFSET, GENERATION_LEN}, + {PCB_NAME_OFFSET, PCB_NAME_LEN}, + {FORM_OFFSET, FORM_LEN}, + {VERSION_OFFSET, VERSION_LEN}, + {IDENTIFICATION_NUMBER_OFFSET, IDENTIFICATION_NUMBER_LEN}, + {MAJOR_SW_VERSION_OFFSET, MAJOR_SW_VERSION_LEN}, + {MINOR_SW_VERSION_OFFSET, MINOR_SW_VERSION_LEN}, +}; + + +/* HW ID data found in EEPROM on supported modules */ +static char *cm1_qa_hw_id[HW_ID_ELEM_COUNT] = { + "CM", /* DEVICE_NAME */ + "1", /* GENERATION */ + "CM1", /* PCB_NAME */ + "Q", /* FORM */ + "A", /* VERSION */ + "591881", /* IDENTIFICATION_NUMBER */ + "", /* MAJOR_SW_VERSION */ + "", /* MINOR_SW_VERSION */ +}; + +static char *cm11_qa_hw_id[HW_ID_ELEM_COUNT] = { + "CM", /* DEVICE_NAME */ + "1", /* GENERATION */ + "CM11", /* PCB_NAME */ + "Q", /* FORM */ + "A", /* VERSION */ + "594200", /* IDENTIFICATION_NUMBER */ + "", /* MAJOR_SW_VERSION */ + "", /* MINOR_SW_VERSION */ +}; + +static char *cmu1_qa_hw_id[HW_ID_ELEM_COUNT] = { + "CMU", /* DEVICE_NAME */ + "1", /* GENERATION */ + "CMU1", /* PCB_NAME */ + "Q", /* FORM */ + "A", /* VERSION */ + "594128", /* IDENTIFICATION_NUMBER */ + "", /* MAJOR_SW_VERSION */ + "", /* MINOR_SW_VERSION */ +}; + + +/* list of known modules */ +static char **hw_id_list[] = { + cm1_qa_hw_id, + cm11_qa_hw_id, + cmu1_qa_hw_id, +}; + +/* indices to the above list - keep in sync */ +enum { + CM1_QA, + CM11_QA, + CMU1_QA, +}; + + +/* identify modules based on these hw id elements */ +static int hw_id_identify[] = { + PCB_NAME, + FORM, + VERSION, +}; + + +/* Registers' settings for SDRAM controller intialization */ +typedef struct { + ulong mode; + ulong control; + ulong config1; + ulong config2; +} mem_conf_t; + +static mem_conf_t k4s561632E = { + 0x00CD0000, /* CASL 3, burst length 8 */ + 0x514F0000, + 0xE2333900, + 0x8EE70000 +}; + +static mem_conf_t mt48lc32m16a2 = { + 0x00CD0000, /* CASL 3, burst length 8 */ + 0x514F0000, + 0xD2322800, + 0x8AD70000 +}; + +static mem_conf_t* memory_config[] = { + &k4s561632E, + &mt48lc32m16a2 +}; + +#endif /* _CM5200_H */ diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c new file mode 100644 index 00000000000..5119a99ca23 --- /dev/null +++ b/board/cm5200/cmd_cm5200.c @@ -0,0 +1,448 @@ +/* + * (C) Copyright 2007 Markus Kappeler + * + * Adapted for U-Boot 1.2 by Piotr Kruszynski + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +int do_i2c(char *argv[]) +{ + unsigned char temp, temp1; + + printf("Starting I2C Test\n" + "Please set Jumper:\nI2C SDA 2-3\nI2C SCL 2-3\n\n" + "Please press any key to start\n\n"); + getc(); + + temp = 0xf0; /* set io 0-4 as output */ + i2c_write(CFG_I2C_IO, 3, 1, (uchar *)&temp, 1); + + printf("Press I2C4-7. LED I2C0-3 should have the same state\n\n" + "Press any key to stop\n\n"); + + while (!tstc()) { + i2c_read(CFG_I2C_IO, 0, 1, (uchar *)&temp, 1); + temp1 = (temp >> 4) & 0x03; + temp1 |= (temp >> 3) & 0x08; /* S302 -> LED303 */ + temp1 |= (temp >> 5) & 0x04; /* S303 -> LED302 */ + temp = temp1; + i2c_write(CFG_I2C_IO, 1, 1, (uchar *)&temp, 1); + } + getc(); + + return 0; +} + +int do_usbtest(char *argv[]) +{ + int i; + static int usb_stor_curr_dev = -1; /* current device */ + + printf("Starting USB Test\n" + "Please insert USB Memmory Stick\n\n" + "Please press any key to start\n\n"); + getc(); + + usb_stop(); + printf("(Re)start USB...\n"); + i = usb_init(); +#ifdef CONFIG_USB_STORAGE + /* try to recognize storage devices immediately */ + if (i >= 0) + usb_stor_curr_dev = usb_stor_scan(1); +#endif /* CONFIG_USB_STORAGE */ + if (usb_stor_curr_dev >= 0) + printf("Found USB Storage Dev continue with Test...\n"); + else { + printf("No USB Storage Device detected.. Stop Test\n"); + return 1; + } + + usb_stor_info(); + + printf("stopping USB..\n"); + usb_stop(); + + return 0; +} + +int do_led(char *argv[]) +{ + int i = 0; + struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; + + printf("Starting LED Test\n" + "Please set Switch S500 all off\n\n" + "Please press any key to start\n\n"); + getc(); + + /* configure timer 2-3 for simple GPIO output High */ + gpt->gpt2.emsr |= 0x00000034; + gpt->gpt3.emsr |= 0x00000034; + + (*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x80000000; + (*(vu_long *)MPC5XXX_WU_GPIO_DIR) |= 0x80000000; + printf("Please press any key to stop\n\n"); + while (!tstc()) { + if (i == 1) { + (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000; + gpt->gpt2.emsr &= ~0x00000010; + gpt->gpt3.emsr &= ~0x00000010; + } else if (i == 2) { + (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000; + gpt->gpt2.emsr &= ~0x00000010; + gpt->gpt3.emsr |= 0x00000010; + } else if (i >= 3) { + (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000; + gpt->gpt3.emsr &= ~0x00000010; + gpt->gpt2.emsr |= 0x00000010; + i = 0; + } + i++; + udelay(200000); + } + getc(); + + (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000; + gpt->gpt2.emsr |= 0x00000010; + gpt->gpt3.emsr |= 0x00000010; + + return 0; +} + +int do_rs232(char *argv[]) +{ + int error_status = 0; + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1; + + /* Configure PSC 2-3-6 as GPIO */ + gpio->port_config &= 0xFF0FF80F; + + switch (simple_strtoul(argv[2], NULL, 10)) { + case 1: + /* check RTS <-> CTS loop */ + /* set rts to 0 */ + printf("Uart 1 test: RX TX tested by using U-Boot\n" + "Please connect RTS with CTS on Uart1 plug\n\n" + "Press any key to start\n\n"); + getc(); + + psc1->op1 |= 0x01; + + /* wait some time before requesting status */ + udelay(10); + + /* check status at cts */ + if ((psc1->ip & 0x01) != 0) { + error_status = 3; + printf("%s: failure at rs232_1, cts status is %d " + "(should be 0)\n", + __FUNCTION__, (psc1->ip & 0x01)); + } + + /* set rts to 1 */ + psc1->op0 |= 0x01; + + /* wait some time before requesting status */ + udelay(10); + + /* check status at cts */ + if ((psc1->ip & 0x01) != 1) { + error_status = 3; + printf("%s: failure at rs232_1, cts status is %d " + "(should be 1)\n", + __FUNCTION__, (psc1->ip & 0x01)); + } + break; + case 2: + /* set PSC2_0, PSC2_2 as output and PSC2_1, PSC2_3 as input */ + printf("Uart 2 test: Please use RS232 Loopback plug on UART2\n" + "\nPress any key to start\n\n"); + getc(); + + gpio->simple_gpioe &= ~(0x000000F0); + gpio->simple_gpioe |= 0x000000F0; + gpio->simple_ddr &= ~(0x000000F0); + gpio->simple_ddr |= 0x00000050; + + /* check TXD <-> RXD loop */ + /* set TXD to 1 */ + gpio->simple_dvo |= (1 << 4); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000020) != 0x00000020) { + error_status = 2; + printf("%s: failure at rs232_2, rxd status is %d " + "(should be 1)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000020) >> 5); + } + + /* set TXD to 0 */ + gpio->simple_dvo &= ~(1 << 4); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000020) != 0x00000000) { + error_status = 2; + printf("%s: failure at rs232_2, rxd status is %d " + "(should be 0)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000020) >> 5); + } + + /* check RTS <-> CTS loop */ + /* set RTS to 1 */ + gpio->simple_dvo |= (1 << 6); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000080) != 0x00000080) { + error_status = 3; + printf("%s: failure at rs232_2, cts status is %d " + "(should be 1)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000080) >> 7); + } + + /* set RTS to 0 */ + gpio->simple_dvo &= ~(1 << 6); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000080) != 0x00000000) { + error_status = 3; + printf("%s: failure at rs232_2, cts status is %d " + "(should be 0)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000080) >> 7); + } + break; + case 3: + /* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */ + printf("Uart 3 test: Please use RS232 Loopback plug on UART2\n" + "\nPress any key to start\n\n"); + getc(); + + gpio->simple_gpioe &= ~(0x00000F00); + gpio->simple_gpioe |= 0x00000F00; + + gpio->simple_ddr &= ~(0x00000F00); + gpio->simple_ddr |= 0x00000500; + + /* check TXD <-> RXD loop */ + /* set TXD to 1 */ + gpio->simple_dvo |= (1 << 8); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000200) != 0x00000200) { + error_status = 2; + printf("%s: failure at rs232_3, rxd status is %d " + "(should be 1)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000200) >> 9); + } + + /* set TXD to 0 */ + gpio->simple_dvo &= ~(1 << 8); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000200) != 0x00000000) { + error_status = 2; + printf("%s: failure at rs232_3, rxd status is %d " + "(should be 0)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000200) >> 9); + } + + /* check RTS <-> CTS loop */ + /* set RTS to 1 */ + gpio->simple_dvo |= (1 << 10); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000800) != 0x00000800) { + error_status = 3; + printf("%s: failure at rs232_3, cts status is %d " + "(should be 1)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000800) >> 11); + } + + /* set RTS to 0 */ + gpio->simple_dvo &= ~(1 << 10); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000800) != 0x00000000) { + error_status = 3; + printf("%s: failure at rs232_3, cts status is %d " + "(should be 0)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000800) >> 11); + } + break; + case 4: + /* set PSC6_2, PSC6_3 as output and PSC6_0, PSC6_1 as input */ + printf("Uart 4 test: Please use RS232 Loopback plug on UART2\n" + "\nPress any key to start\n\n"); + getc(); + + gpio->simple_gpioe &= ~(0xF0000000); + gpio->simple_gpioe |= 0x30000000; + + gpio->simple_ddr &= ~(0xf0000000); + gpio->simple_ddr |= 0x30000000; + + (*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x30000000; + (*(vu_long *)MPC5XXX_WU_GPIO_DIR) &= ~(0x30000000); + + /* check TXD <-> RXD loop */ + /* set TXD to 1 */ + gpio->simple_dvo |= (1 << 28); + + /* wait some time before requesting status */ + udelay(10); + + if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) != + 0x10000000) { + error_status = 2; + printf("%s: failure at rs232_4, rxd status is %d " + "(should be 1)\n", __FUNCTION__, + ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & + 0x10000000) >> 28); + } + + /* set TXD to 0 */ + gpio->simple_dvo &= ~(1 << 28); + + /* wait some time before requesting status */ + udelay(10); + + if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) != + 0x00000000) { + error_status = 2; + printf("%s: failure at rs232_4, rxd status is %d " + "(should be 0)\n", __FUNCTION__, + ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & + 0x10000000) >> 28); + } + + /* check RTS <-> CTS loop */ + /* set RTS to 1 */ + gpio->simple_dvo |= (1 << 29); + + /* wait some time before requesting status */ + udelay(10); + + if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) != + 0x20000000) { + error_status = 3; + printf("%s: failure at rs232_4, cts status is %d " + "(should be 1)\n", __FUNCTION__, + ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & + 0x20000000) >> 29); + } + + /* set RTS to 0 */ + gpio->simple_dvo &= ~(1 << 29); + + /* wait some time before requesting status */ + udelay(10); + + if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) != + 0x00000000) { + error_status = 3; + printf("%s: failure at rs232_4, cts status is %d " + "(should be 0)\n", __FUNCTION__, + ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & + 0x20000000) >> 29); + } + break; + default: + printf("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]); + error_status = 1; + break; + } + gpio->port_config |= (CFG_GPS_PORT_CONFIG & 0xFF0FF80F); + + return error_status; +} + +int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rcode = -1; + + switch (argc) { + case 2: + if (strncmp(argv[1], "i2c", 3) == 0) + rcode = do_i2c(argv); + else if (strncmp(argv[1], "led", 3) == 0) + rcode = do_led(argv); + else if (strncmp(argv[1], "usb", 3) == 0) + rcode = do_usbtest(argv); + break; + case 3: + if (strncmp(argv[1], "rs232", 3) == 0) + rcode = do_rs232(argv); + break; + } + + switch (rcode) { + case -1: + printf("Usage:\n" + "fkt { i2c | led | usb }\n" + "fkt rs232 number\n"); + rcode = 1; + break; + case 0: + printf("Test passed\n"); + break; + default: + printf("Test failed with code: %d\n", rcode); + } + + return rcode; +} + +U_BOOT_CMD( + fkt, 4, 1, cmd_fkt, + "fkt - Function test routines\n", + "i2c\n" + " - Test I2C communication\n" + "fkt led\n" + " - Test LEDs\n" + "fkt rs232 number\n" + " - Test RS232 (loopback plug(s) for RS232 required)\n" + "fkt usb\n" + " - Test USB communication\n" +); +#endif /* CFG_CMD_BSP */ diff --git a/board/cm5200/config.mk b/board/cm5200/config.mk new file mode 100644 index 00000000000..7f061391a24 --- /dev/null +++ b/board/cm5200/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xfc000000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/cm5200/fwupdate.c b/board/cm5200/fwupdate.c new file mode 100644 index 00000000000..19aa94a5a03 --- /dev/null +++ b/board/cm5200/fwupdate.c @@ -0,0 +1,200 @@ +/* + * (C) Copyright 2007 Schindler Lift Inc. + * (C) Copyright 2007 DENX Software Engineering + * + * Author: Michel Marti + * Adapted for U-Boot 1.2 by Piotr Kruszynski : + * - code clean-up + * - bugfix for overwriting bootargs by user + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include "fwupdate.h" + +extern int do_bootm(cmd_tbl_t *, int, int, char *[]); +extern long do_fat_read(const char *, void *, unsigned long, int); +extern int do_fat_fsload(cmd_tbl_t *, int, int, char *[]); + +static int load_rescue_image(ulong); + +void cm5200_fwupdate(void) +{ + cmd_tbl_t *bcmd; + char *rsargs; + char *tmp = NULL; + char ka[16]; + char *argv[3] = { "bootm", ka, NULL }; + + /* Check if rescue system is disabled... */ + if (getenv("norescue")) { + printf(LOG_PREFIX "Rescue System disabled.\n"); + return; + } + + /* Check if we have a USB storage device and load image */ + if (load_rescue_image(LOAD_ADDR)) + return; + + bcmd = find_cmd("bootm"); + if (!bcmd) + return; + + sprintf(ka, "%lx", LOAD_ADDR); + + /* prepare our bootargs */ + rsargs = getenv("rs-args"); + if (!rsargs) + rsargs = RS_BOOTARGS; + else { + tmp = malloc(strlen(rsargs+1)); + if (!tmp) { + printf(LOG_PREFIX "Memory allocation failed\n"); + return; + } + strcpy(tmp, rsargs); + rsargs = tmp; + } + + setenv("bootargs", rsargs); + + if (rsargs == tmp) + free(rsargs); + + printf(LOG_PREFIX "Starting update system (bootargs=%s)...\n", rsargs); + do_bootm(bcmd, 0, 2, argv); +} + +static int load_rescue_image(ulong addr) +{ + disk_partition_t info; + int devno; + int partno; + int i; + char fwdir[64]; + char nxri[128]; + char *tmp; + char dev[7]; + char addr_str[16]; + char *argv[6] = { "fatload", "usb", dev, addr_str, nxri, NULL }; + block_dev_desc_t *stor_dev = NULL; + cmd_tbl_t *bcmd; + + /* Get name of firmware directory */ + tmp = getenv("fw-dir"); + + /* Copy it into fwdir */ + strncpy(fwdir, tmp ? tmp : FW_DIR, sizeof(fwdir)); + fwdir[sizeof(fwdir) - 1] = 0; /* Terminate string */ + + printf(LOG_PREFIX "Checking for firmware image directory '%s' on USB" + " storage...\n", fwdir); + usb_stop(); + if (usb_init() != 0) + return 1; + + /* Check for storage device */ + if (usb_stor_scan(1) != 0) { + usb_stop(); + return 1; + } + + /* Detect storage device */ + for (devno = 0; devno < USB_MAX_STOR_DEV; devno++) { + stor_dev = usb_stor_get_dev(devno); + if (stor_dev->type != DEV_TYPE_UNKNOWN) + break; + } + if (!stor_dev || stor_dev->type == DEV_TYPE_UNKNOWN) { + printf(LOG_PREFIX "No valid storage device found...\n"); + usb_stop(); + return 1; + } + + /* Detect partition */ + for (partno = -1, i = 0; i < 6; i++) { + if (get_partition_info(stor_dev, i, &info) == 0) { + if (fat_register_device(stor_dev, i) == 0) { + /* Check if rescue image is present */ + FW_DEBUG("Looking for firmware directory '%s'" + " on partition %d\n", fwdir, i); + if (do_fat_read(fwdir, NULL, 0, LS_NO) == -1) { + FW_DEBUG("No NX rescue image on " + "partition %d.\n", i); + partno = -2; + } else { + partno = i; + FW_DEBUG("Partition %d contains " + "firmware directory\n", partno); + break; + } + } + } + } + + if (partno < 0) { + switch (partno) { + case -1: + printf(LOG_PREFIX "Error: No valid (FAT) partition " + "detected\n"); + break; + case -2: + printf(LOG_PREFIX "Error: No NX rescue image on FAT " + "partition\n"); + break; + default: + printf(LOG_PREFIX "Error: Failed with code %d\n", + partno); + } + usb_stop(); + return 1; + } + + /* Load the rescue image */ + bcmd = find_cmd("fatload"); + if (!bcmd) { + printf(LOG_PREFIX "Error - 'fatload' command not present.\n"); + usb_stop(); + return 1; + } + + tmp = getenv("nx-rescue-image"); + sprintf(nxri, "%s/%s", fwdir, tmp ? tmp : RESCUE_IMAGE); + sprintf(dev, "%d:%d", devno, partno); + sprintf(addr_str, "%lx", addr); + + FW_DEBUG("fat_fsload device='%s', addr='%s', file: %s\n", + dev, addr_str, nxri); + + if (do_fat_fsload(bcmd, 0, 5, argv) != 0) { + usb_stop(); + return 1; + } + + /* Stop USB */ + usb_stop(); + return 0; +} diff --git a/board/cm5200/fwupdate.h b/board/cm5200/fwupdate.h new file mode 100644 index 00000000000..4e3f1e164aa --- /dev/null +++ b/board/cm5200/fwupdate.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2007 Schindler Lift Inc. + * + * Author: Michel Marti + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FW_UPDATE_H +#define __FW_UPDATE_H + +/* Default prefix for output messages */ +#define LOG_PREFIX "CM5200:" + +/* Extra debug macro */ +#ifdef CONFIG_FWUPDATE_DEBUG +#define FW_DEBUG(fmt...) printf(LOG_PREFIX fmt) +#else +#define FW_DEBUG(fmt...) +#endif + +/* Name of the directory holding firmware images */ +#define FW_DIR "nx-fw" +#define RESCUE_IMAGE "nxrs.img" +#define LOAD_ADDR 0x400000 +#define RS_BOOTARGS "ramdisk=8192K" + +/* Main function for fwupdate */ +void cm5200_fwupdate(void); + +#endif /* __FW_UPDATE_H */ diff --git a/board/cm5200/u-boot.lds b/board/cm5200/u-boot.lds new file mode 100644 index 00000000000..8fa9c0f7ed5 --- /dev/null +++ b/board/cm5200/u-boot.lds @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2003-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c index 3d99d5c1ec6..2b5b5278dcf 100644 --- a/cpu/mpc5xxx/fec.c +++ b/cpu/mpc5xxx/fec.c @@ -890,7 +890,7 @@ int mpc5xxx_fec_initialize(bd_t * bis) fec->tbdBase = (FEC_TBD *)FEC_BD_BASE; fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD)); #if defined(CONFIG_CANMB) || \ - defined(CONFIG_CM1_QP1) || \ + defined(CONFIG_CM5200) || \ defined(CONFIG_HMI1001) || \ defined(CONFIG_ICECUBE) || \ defined(CONFIG_INKA4X0) || \ diff --git a/include/configs/cm1_qp1.h b/include/configs/cm1_qp1.h deleted file mode 100644 index effa41c0525..00000000000 --- a/include/configs/cm1_qp1.h +++ /dev/null @@ -1,358 +0,0 @@ -/* - * (C) Copyright 2003-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_CM1_QP1 1 /* ... on CM1.QP1 module */ - - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_I2C | \ - CFG_CMD_FLASH | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_DIAG | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP | \ - CFG_CMD_BSP | \ - CFG_CMD_USB | \ - CFG_CMD_FAT | \ - CFG_CMD_JFFS2) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 57600 /* ... at 57600 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */ -/* use misc_init_r() to read ethaddr from I2C EEPROM (see CFG_I2C_EEPROM) */ -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */ - - -/* - * POST support - */ -#define CONFIG_POST (CFG_POST_MEMORY | CFG_POST_CPU | CFG_POST_I2C) -#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) -/* List of I2C addresses to be verified by POST */ -#define I2C_ADDR_LIST { CFG_I2C_SLAVE, CFG_I2C_IO, CFG_I2C_EEPROM } - - -/* display image timestamps */ -#define CONFIG_TIMESTAMP 1 - - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \ - "echo" -#undef CONFIG_BOOTARGS - -/* - * Default environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=cm1_qp1\0" \ - "netmask=255.255.0.0\0" \ - "ipaddr=192.168.160.33\0" \ - "serverip=192.168.1.1\0" \ - "gatewayip=192.168.1.1\0" \ - "console=ttyPSC0\0" \ - "u-boot_addr=100000\0" \ - "kernel_addr=200000\0" \ - "kernel_addr_flash=fc0c0000\0" \ - "fdt_addr=400000\0" \ - "fdt_addr_flash=fc0a0000\0" \ - "ramdisk_addr=500000\0" \ - "rootpath=/opt/eldk-4.1/ppc_6xx\0" \ - "u-boot=/tftpboot/cm1_qp1/u-boot.bin\0" \ - "bootfile=/tftpboot/cm1_qp1/uImage\0" \ - "fdt_file=/tftpboot/cm1_qp1/cm1_qp1.dtb\0" \ - "load=tftp ${u-boot_addr} ${u-boot}\0" \ - "update=prot off fc000000 fc05ffff; era fc000000 fc05ffff; " \ - "cp.b ${u-boot_addr} fc000000 ${filesize}; " \ - "prot on fc000000 fc05ffff\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console},${baudrate}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off panic=1\0" \ - "flash_flash=run flashargs addinit addip addcons;" \ - "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \ - "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \ - "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \ - "addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_flash" - - -/* - * Low level configuration - */ - - -/* - * Clock configuration - */ -#define CFG_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */ -#define CFG_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */ - - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -#define CFG_LOWBOOT 1 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */ -#define CFG_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT 1 -#endif - - -/* - * Chip selects configuration - */ -/* Boot Chipselect */ -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */ -/* use board_early_init_r to enable flash write in CS_BOOT */ -#define CONFIG_BOARD_EARLY_INIT_R - -/* Flash memory addressing */ -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -/* No burst, dead cycle = 1 for CS0 (Flash) */ -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x00000001 - - -/* - * SDRAM configuration - * settings for k4s561632E-xx75, assuming XLB = 132 MHz - */ -#define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */ -#define SDRAM_CONTROL 0x514F0000 -#define SDRAM_CONFIG1 0xE2333900 -#define SDRAM_CONFIG2 0x8EE70000 - - -/* - * Flash configuration - */ -#define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 -#define CFG_FLASH_BASE TEXT_BASE -/* we need these despite using CFI */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CFG_MAX_FLASH_SECT 256 /* max num of sectors on one chip */ -#define CFG_FLASH_SIZE 0x02000000 /* 32 MiB */ - - -/* - * MTD configuration - */ -#define CONFIG_JFFS2_CMDLINE 1 -#define MTDIDS_DEFAULT "nor0=cm1qp1-0" -#define MTDPARTS_DEFAULT "mtdparts=cm1qp1-0:" \ - "384k(uboot),128k(env)," \ - "128k(redund_env),128k(dtb)," \ - "2m(kernel),27904k(rootfs)," \ - "-(config)" - - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 2 /* Select I2C module #2 */ -#define CFG_I2C_SPEED 40000 /* 40 kHz */ -#define CFG_I2C_SLAVE 0x0 -#define CFG_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */ -#define CFG_I2C_EEPROM 0x53 /* I2C EEPROM device address */ - - -/* - * RTC configuration - */ -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - - -/* - * USB configuration - */ -#define CONFIG_USB_OHCI 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 -/* Partitions (for USB) */ -#define CONFIG_MAC_PARTITION 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_ISO_PARTITION 1 - -/* - * Invoke our last_stage_init function - needed by fwupdate - */ -#define CONFIG_LAST_STAGE_INIT 1 - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x10000 -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) -/* Configuration of redundant environment */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - - -/* - * Pin multiplexing configuration - */ - -/* - * CS1/GPIO_WKUP_6: GPIO (default) - * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1 - * IRDA/PSC6: UART - * Ether: Ethernet 100Mbit with MD - * PCI_DIS: PCI controller disabled - * USB: USB - * PSC3: SPI with UART3 - * PSC2: UART - * PSC1: UART - */ -#define CFG_GPS_PORT_CONFIG 0x10559C44 - - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP 1 /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_ALT_MEMTEST 1 -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */ - -#define CONFIG_LOOPW 1 - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - - -/* - * Various low-level settings - */ -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_XLB_PIPELINING 1 /* enable transaction pipeling */ - - -/* - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - - -/* - * Flat Device Tree support - */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define OF_FLAT_TREE_MAX_SIZE 8192 /* max size of the flat tree (8K) */ -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" - -#endif /* __CONFIG_H */ diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h new file mode 100644 index 00000000000..76628560e5a --- /dev/null +++ b/include/configs/cm5200.h @@ -0,0 +1,362 @@ +/* + * (C) Copyright 2003-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_CM5200 1 /* ... on CM5200 platform */ + + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_I2C | \ + CFG_CMD_FLASH | \ + CFG_CMD_MII | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_DIAG | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SNTP | \ + CFG_CMD_BSP | \ + CFG_CMD_USB | \ + CFG_CMD_FAT | \ + CFG_CMD_JFFS2) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 57600 /* ... at 57600 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#define CONFIG_SILENT_CONSOLE 1 /* needed to silence i2c_init() */ + + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */ +/* use misc_init_r() to read ethaddr from I2C EEPROM (see CFG_I2C_EEPROM) */ +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */ + + +/* + * POST support + */ +#define CONFIG_POST (CFG_POST_MEMORY | CFG_POST_CPU | CFG_POST_I2C) +#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) +/* List of I2C addresses to be verified by POST */ +#define I2C_ADDR_LIST { CFG_I2C_SLAVE, CFG_I2C_IO, CFG_I2C_EEPROM } + + +/* display image timestamps */ +#define CONFIG_TIMESTAMP 1 + + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \ + "echo" +#undef CONFIG_BOOTARGS + +/* + * Default environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "netmask=255.255.0.0\0" \ + "ipaddr=192.168.160.33\0" \ + "serverip=192.168.1.1\0" \ + "gatewayip=192.168.1.1\0" \ + "console=ttyPSC0\0" \ + "u-boot_addr=100000\0" \ + "kernel_addr=200000\0" \ + "kernel_addr_flash=fc0c0000\0" \ + "fdt_addr=400000\0" \ + "fdt_addr_flash=fc0a0000\0" \ + "ramdisk_addr=500000\0" \ + "rootpath=/opt/eldk-4.1/ppc_6xx\0" \ + "u-boot=/tftpboot/cm5200/u-boot.bin\0" \ + "bootfile_fdt=/tftpboot/cm5200/uImage\0" \ + "fdt_file=/tftpboot/cm5200/cm5200.dtb\0" \ + "load=tftp ${u-boot_addr} ${u-boot}\0" \ + "update=prot off fc000000 +${filesize}; " \ + "era fc000000 +${filesize}; " \ + "cp.b ${u-boot_addr} fc000000 ${filesize}; " \ + "prot on fc000000 +${filesize}\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \ + "addcons=setenv bootargs ${bootargs} " \ + "console=${console},${baudrate}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off panic=1\0" \ + "flash_flash=run flashargs addinit addip addcons;" \ + "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \ + "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \ + "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \ + "addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_flash" + + +/* + * Low level configuration + */ + + +/* + * Clock configuration + */ +#define CFG_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */ +#define CFG_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */ + + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +#define CFG_LOWBOOT 1 + +/* Use ON-Chip SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#ifdef CONFIG_POST +/* preserve space for the post_word at end of on-chip SRAM */ +#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE +#else +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE +#endif + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CONFIG_BOARD_TYPES 1 /* we use board_type */ + +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ + +/* + * Flash configuration + */ +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#define CFG_FLASH_BASE 0xfc000000 +/* we need these despite using CFI */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 256 /* max num of sectors on one chip */ +#define CFG_FLASH_SIZE 0x02000000 /* 32 MiB */ + + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT 1 +#undef CFG_LOWBOOT +#endif + + +/* + * Chip selects configuration + */ +/* Boot Chipselect */ +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */ +/* use board_early_init_r to enable flash write in CS_BOOT */ +#define CONFIG_BOARD_EARLY_INIT_R + +/* Flash memory addressing */ +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +/* No burst, dead cycle = 1 for CS0 (Flash) */ +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x00000001 + + +/* + * SDRAM configuration + * settings for k4s561632E-xx75, assuming XLB = 132 MHz + */ +#define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */ +#define SDRAM_CONTROL 0x514F0000 +#define SDRAM_CONFIG1 0xE2333900 +#define SDRAM_CONFIG2 0x8EE70000 + + + +/* + * MTD configuration + */ +#define CONFIG_JFFS2_CMDLINE 1 +#define MTDIDS_DEFAULT "nor0=cm5200-0" +#define MTDPARTS_DEFAULT "mtdparts=cm5200-0:" \ + "384k(uboot),128k(env)," \ + "128k(redund_env),128k(dtb)," \ + "2m(kernel),27904k(rootfs)," \ + "-(config)" + + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #2 */ +#define CFG_I2C_SPEED 40000 /* 40 kHz */ +#define CFG_I2C_SLAVE 0x0 +#define CFG_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */ +#define CFG_I2C_EEPROM 0x53 /* I2C EEPROM device address */ + + +/* + * RTC configuration + */ +#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ + + +/* + * USB configuration + */ +#define CONFIG_USB_OHCI 1 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 +/* Partitions (for USB) */ +#define CONFIG_MAC_PARTITION 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_ISO_PARTITION 1 + +/* + * Invoke our last_stage_init function - needed by fwupdate + */ +#define CONFIG_LAST_STAGE_INIT 1 + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) +/* Configuration of redundant environment */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + + +/* + * Pin multiplexing configuration + */ + +/* + * CS1/GPIO_WKUP_6: GPIO (default) + * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1 + * IRDA/PSC6: UART + * Ether: Ethernet 100Mbit with MD + * PCI_DIS: PCI controller disabled + * USB: USB + * PSC3: SPI with UART3 + * PSC2: UART + * PSC1: UART + */ +#define CFG_GPS_PORT_CONFIG 0x10559C44 + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_ALT_MEMTEST 1 +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */ + +#define CONFIG_LOOPW 1 + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + + +/* + * Various low-level settings + */ +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_XLB_PIPELINING 1 /* enable transaction pipeling */ + + +/* + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + + +/* + * Flat Device Tree support + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define OF_CPU "PowerPC,5200@0" +#define OF_SOC "soc5200@f0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 63cec5814fab5d2b1c86982327433807a5ac0249 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Thu, 2 Aug 2007 14:09:49 -0500 Subject: Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout Signed-off-by: Zhang Wei Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/mpc8641hpcn.c | 165 +++++++++++++++++++++++++-------- board/mpc8641hpcn/u-boot.lds | 1 - cpu/mpc86xx/Makefile | 3 +- cpu/mpc86xx/pci.c | 146 ----------------------------- cpu/mpc86xx/pcie_indirect.c | 199 ---------------------------------------- drivers/Makefile | 2 +- drivers/ahci.c | 3 +- drivers/fsl_pci_init.c | 180 ++++++++++++++++++++++++++++++++++++ include/asm-ppc/immap_fsl_pci.h | 150 ++++++++++++++++++++++++++++++ include/configs/MPC8641HPCN.h | 44 +++++---- include/pci.h | 6 ++ 11 files changed, 493 insertions(+), 406 deletions(-) delete mode 100644 cpu/mpc86xx/pci.c delete mode 100644 cpu/mpc86xx/pcie_indirect.c create mode 100644 drivers/fsl_pci_init.c create mode 100644 include/asm-ppc/immap_fsl_pci.h (limited to 'cpu') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index 5e02cc5a5e6..d2182aba5f0 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -11,7 +11,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -55,37 +56,6 @@ int checkboard(void) { puts("Board: MPC8641HPCN\n"); -#ifdef CONFIG_PCI - - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_pex_t *pex1 = &immap->im_pex1; - - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; -#ifdef DEBUG - uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); -#endif - if ((io_sel == 2 || io_sel == 3 || io_sel == 5 - || io_sel == 6 || io_sel == 7 || io_sel == 0xF) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { - debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); - debug("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det); - if (pex1->pme_msg_det) { - pex1->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pex1->pme_msg_det); - } - debug("\n"); - } else { - puts("PCI-EXPRESS 1: Disabled\n"); - } - -#else - puts("PCI-EXPRESS1: Disabled\n"); -#endif - return 0; } @@ -220,21 +190,138 @@ static struct pci_config_table pci_fsl86xxads_config_table[] = { #endif -static struct pci_controller hose = { +static struct pci_controller pci1_hose = { #ifndef CONFIG_PCI_PNP - config_table:pci_mpc86xxcts_config_table, + config_table:pci_mpc86xxcts_config_table #endif }; - #endif /* CONFIG_PCI */ +#ifdef CONFIG_PCI2 +static struct pci_controller pci2_hose; +#endif /* CONFIG_PCI2 */ + +int first_free_busno = 0; + + void pci_init_board(void) { -#ifdef CONFIG_PCI - extern void pci_mpc86xx_init(struct pci_controller *hose); + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + +#ifdef CONFIG_PCI1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; +#ifdef DEBUG + uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); +#endif + if ((io_sel == 2 || io_sel == 3 || io_sel == 5 + || io_sel == 6 || io_sel == 7 || io_sel == 0xF) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); + debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + debug("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + /* + * Activate ULI1575 legacy chip by performing a fake + * memory access. Needed to make ULI RTC work. + */ + in_be32((unsigned *) CFG_PCI1_MEM_BASE + + CFG_PCI1_MEM_SIZE - 0x1000000); + + } else { + puts("PCI-EXPRESS 1: Disabled\n"); + } +} +#else + puts("PCI-EXPRESS1: Disabled\n"); +#endif /* CONFIG_PCI1 */ + +#ifdef CONFIG_PCI2 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci2_hose; + + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI2_MEM_BASE, + CFG_PCI2_MEM_PHYS, + CFG_PCI2_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI2_IO_BASE, + CFG_PCI2_IO_PHYS, + CFG_PCI2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); +} +#else + puts("PCI-EXPRESS 2: Disabled\n"); +#endif /* CONFIG_PCI2 */ - pci_mpc86xx_init(&hose); -#endif /* CONFIG_PCI */ } #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds index 34b50e4be20..e4792ef1998 100644 --- a/board/mpc8641hpcn/u-boot.lds +++ b/board/mpc8641hpcn/u-boot.lds @@ -57,7 +57,6 @@ SECTIONS cpu/mpc86xx/cpu_init.o (.text) cpu/mpc86xx/cpu.o (.text) cpu/mpc86xx/speed.o (.text) - cpu/mpc86xx/pci.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) diff --git a/cpu/mpc86xx/Makefile b/cpu/mpc86xx/Makefile index fffcfd24029..6d9300e22e7 100644 --- a/cpu/mpc86xx/Makefile +++ b/cpu/mpc86xx/Makefile @@ -1,4 +1,5 @@ # +# Copyright 2007 Freescale Semiconductor, Inc. # (C) Copyright 2002,2003 Motorola Inc. # Xianghua Xiao,X.Xiao@motorola.com # @@ -30,7 +31,7 @@ LIB = $(obj)lib$(CPU).a START = start.o #resetvec.o SOBJS = cache.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - pci.o pcie_indirect.o spd_sdram.o + spd_sdram.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc86xx/pci.c b/cpu/mpc86xx/pci.c deleted file mode 100644 index b86548db4f9..00000000000 --- a/cpu/mpc86xx/pci.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor,Inc. - * 2005, 2006. All rights reserved. - * - * Ed Swarthout (ed.swarthout@freescale.com) - * Jason Jin (Jason.jin@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * PCIE Configuration space access support for PCIE Bridge - */ -#include -#include - -#if defined(CONFIG_PCI) -void -pci_mpc86xx_init(struct pci_controller *hose) -{ - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_pex_t *pcie1 = &immap->im_pex1; - u16 temp16; - u32 temp32; - - volatile ccsr_gur_t *gur = &immap->im_gur; - uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; - uint pcie1_host = (host1_agent == 2) || (host1_agent == 3); - uint pcie1_agent = (host1_agent == 0) || (host1_agent == 1); - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; - - if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || - io_sel == 7 || io_sel == 0xf) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { - printf("PCI-EXPRESS 1: Configured as %s \n", - pcie1_agent ? "Agent" : "Host"); - if (pcie1_agent) - return; /*Don't scan bus when configured as agent */ - printf(" Scanning PCIE bus"); - debug("0x%08x=0x%08x ", - &pcie1->pme_msg_det, - pcie1->pme_msg_det); - if (pcie1->pme_msg_det) { - pcie1->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pcie1->pme_msg_det); - } - debug("\n"); - } else { - printf("PCI-EXPRESS 1 disabled!\n"); - return; - } - - /* - * Set first_bus=0 only skipped B0:D0:F0 which is - * a reserved device in M1575, but make it easy for - * most of the scan process. - */ - hose->first_busno = 0x00; - hose->last_busno = 0xfe; - - pcie_setup_indirect(hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004)); - - pci_hose_read_config_word(hose, - PCI_BDF(0, 0, 0), PCI_COMMAND, &temp16); - temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_hose_write_config_word(hose, - PCI_BDF(0, 0, 0), PCI_COMMAND, temp16); - - pci_hose_write_config_word(hose, PCI_BDF(0, 0, 0), PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, - PCI_BDF(0, 0, 0), PCI_LATENCY_TIMER, 0x80); - - pci_hose_read_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS, - &temp32); - temp32 = (temp32 & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16); - pci_hose_write_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS, - temp32); - - pcie1->powar1 = 0; - pcie1->powar2 = 0; - pcie1->piwar1 = 0; - pcie1->piwar1 = 0; - - pcie1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pcie1->powar1 = 0x8004401c; /* 512M MEM space */ - pcie1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pcie1->potear1 = 0x00000000; - - pcie1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; - pcie1->powar2 = 0x80088017; /* 16M IO space */ - pcie1->potar2 = 0x00000000; - pcie1->potear2 = 0x00000000; - - pcie1->pitar1 = 0x00000000; - pcie1->piwbar1 = 0x00000000; - /* Enable, Prefetch, Local Mem, * Snoop R/W, 2G */ - pcie1->piwar1 = 0xa0f5501e; - - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - pci_set_region(hose->regions + 1, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 3; - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); - debug("pcie_mpc86xx_init: last_busno %x\n", hose->last_busno); - debug("pcie_mpc86xx init: current_busno %x\n ", hose->current_busno); - - printf("....PCIE1 scan & enumeration done\n"); -} -#endif /* CONFIG_PCI */ diff --git a/cpu/mpc86xx/pcie_indirect.c b/cpu/mpc86xx/pcie_indirect.c deleted file mode 100644 index b00ad76ab89..00000000000 --- a/cpu/mpc86xx/pcie_indirect.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Support for indirect PCI bridges. - * - * Copyright (c) Freescale Semiconductor, Inc. - * 2006. All rights reserved. - * - * Jason Jin - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * partly derived from - * arch/powerpc/platforms/86xx/mpc86xx_pcie.c - */ - -#include - -#ifdef CONFIG_PCI - -#include -#include -#include - -#define PCI_CFG_OUT out_be32 -#define PEX_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff) - -static int -indirect_read_config_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - int len, - u32 *val) -{ - int bus = PCI_BUS(dev); - - volatile unsigned char *cfg_data; - u32 temp; - - PEX_FIX; - if (bus == 0xff) { - PCI_CFG_OUT(hose->cfg_addr, - dev | (offset & 0xfc) | 0x80000001); - } else { - PCI_CFG_OUT(hose->cfg_addr, - dev | (offset & 0xfc) | 0x80000000); - } - /* - * Note: the caller has already checked that offset is - * suitably aligned and that len is 1, 2 or 4. - */ - /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */ - cfg_data = hose->cfg_data; - PEX_FIX; - temp = in_le32((u32 *) cfg_data); - switch (len) { - case 1: - *val = (temp >> (((offset & 3)) * 8)) & 0xff; - break; - case 2: - *val = (temp >> (((offset & 3)) * 8)) & 0xffff; - break; - default: - *val = temp; - break; - } - - return 0; -} - -static int -indirect_write_config_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - int len, - u32 val) -{ - int bus = PCI_BUS(dev); - volatile unsigned char *cfg_data; - u32 temp; - - PEX_FIX; - if (bus == 0xff) { - PCI_CFG_OUT(hose->cfg_addr, - dev | (offset & 0xfc) | 0x80000001); - } else { - PCI_CFG_OUT(hose->cfg_addr, - dev | (offset & 0xfc) | 0x80000000); - } - - /* - * Note: the caller has already checked that offset is - * suitably aligned and that len is 1, 2 or 4. - */ - /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */ - cfg_data = hose->cfg_data; - switch (len) { - case 1: - PEX_FIX; - temp = in_le32((u32 *) cfg_data); - temp = (temp & ~(0xff << ((offset & 3) * 8))) | - (val << ((offset & 3) * 8)); - PEX_FIX; - out_le32((u32 *) cfg_data, temp); - break; - case 2: - PEX_FIX; - temp = in_le32((u32 *) cfg_data); - temp = (temp & ~(0xffff << ((offset & 3) * 8))); - temp |= (val << ((offset & 3) * 8)); - PEX_FIX; - out_le32((u32 *) cfg_data, temp); - break; - default: - PEX_FIX; - out_le32((u32 *) cfg_data, val); - break; - } - PEX_FIX; - return 0; -} - -static int -indirect_read_config_byte_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u8 *val) -{ - u32 val32; - indirect_read_config_pcie(hose, dev, offset, 1, &val32); - *val = (u8) val32; - return 0; -} - -static int -indirect_read_config_word_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u16 *val) -{ - u32 val32; - indirect_read_config_pcie(hose, dev, offset, 2, &val32); - *val = (u16) val32; - return 0; -} - -static int -indirect_read_config_dword_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u32 *val) -{ - return indirect_read_config_pcie(hose, dev, offset, 4, val); -} - -static int -indirect_write_config_byte_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u8 val) -{ - return indirect_write_config_pcie(hose, dev, offset, 1, (u32) val); -} - -static int -indirect_write_config_word_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - unsigned short val) -{ - return indirect_write_config_pcie(hose, dev, offset, 2, (u32) val); -} - -static int -indirect_write_config_dword_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u32 val) -{ - return indirect_write_config_pcie(hose, dev, offset, 4, val); -} - -void -pcie_setup_indirect(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) -{ - pci_set_ops(hose, - indirect_read_config_byte_pcie, - indirect_read_config_word_pcie, - indirect_read_config_dword_pcie, - indirect_write_config_byte_pcie, - indirect_write_config_word_pcie, - indirect_write_config_dword_pcie); - - hose->cfg_addr = (unsigned int *)cfg_addr; - hose->cfg_data = (unsigned char *)cfg_data; -} - -#endif /* CONFIG_PCI */ diff --git a/drivers/Makefile b/drivers/Makefile index 48fd4eaade0..fa2e86fd20f 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -52,7 +52,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o ata_piix.o atmel_usart.o \ ks8695eth.o \ pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \ rpx_pcmcia.o \ - fsl_i2c.o + fsl_i2c.o fsl_pci_init.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/ahci.c b/drivers/ahci.c index 8ceff00925f..ccd4d71e8ae 100644 --- a/drivers/ahci.c +++ b/drivers/ahci.c @@ -253,7 +253,8 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent) static int ahci_init_one(pci_dev_t pdev) { - u32 iobase, vendor; + u32 iobase; + u16 vendor; int rc; memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c new file mode 100644 index 00000000000..1d1f6df997a --- /dev/null +++ b/drivers/fsl_pci_init.c @@ -0,0 +1,180 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#define DEBUG +#include + +#ifdef CONFIG_FSL_PCI_INIT + +/* + * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's + * + * Initialize controller and call the common driver/pci pci_hose_scan to + * scan for bridges and devices. + * + * Hose fields which need to be pre-initialized by board specific code: + * regions[] + * first_busno + * + * Fields updated: + * last_busno + */ + +#include +#include + +void pciauto_prescan_setup_bridge(struct pci_controller *hose, + pci_dev_t dev, int sub_bus); +void pciauto_postscan_setup_bridge(struct pci_controller *hose, + pci_dev_t dev, int sub_bus); + +void pciauto_config_init(struct pci_controller *hose); +void +fsl_pci_init(struct pci_controller *hose) +{ + u16 temp16; + u32 temp32; + int busno = hose->first_busno; + int enabled; + u16 ltssm; + u8 temp8; + int r; + int bridge; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr; + pci_dev_t dev = PCI_BDF(busno,0,0); + + /* Initialize ATMU registers based on hose regions and flags */ + volatile pot_t *po=&pci->pot[1]; /* skip 0 */ + volatile pit_t *pi=&pci->pit[0]; /* ranges from: 3 to 1 */ + +#ifdef DEBUG + int neg_link_w; +#endif + + for (r=0; rregion_count; r++) { + if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */ + pi->pitar = (hose->regions[r].bus_start >> 12) & 0x000fffff; + pi->piwbar = (hose->regions[r].phys_start >> 12) & 0x000fffff; + pi->piwbear = 0; + pi->piwar = PIWAR_EN | PIWAR_PF | PIWAR_LOCAL | + PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | + (__ilog2(hose->regions[r].size) - 1); + pi++; + } else { /* Outbound */ + po->powbar = (hose->regions[r].phys_start >> 12) & 0x000fffff; + po->potar = (hose->regions[r].bus_start >> 12) & 0x000fffff; + po->potear = 0; + if (hose->regions[r].flags & PCI_REGION_IO) + po->powar = POWAR_EN | POWAR_IO_READ | POWAR_IO_WRITE | + (__ilog2(hose->regions[r].size) - 1); + else + po->powar = POWAR_EN | POWAR_MEM_READ | POWAR_MEM_WRITE | + (__ilog2(hose->regions[r].size) - 1); + po++; + } + } + + pci_register_hose(hose); + pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ + hose->current_busno = hose->first_busno; + + pci->pedr = 0xffffffff; /* Clear any errors */ + pci->peer = 0xffffffff; /* Enable Error Interupts */ + pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32); + temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ + pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); + + pci_hose_read_config_byte (hose, dev, PCI_HEADER_TYPE, &temp8); + bridge = temp8 & PCI_HEADER_TYPE_BRIDGE; /* Bridge, such as pcie */ + + if ( bridge ) { + + pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); + enabled = ltssm >= PCI_LTSSM_L0; + + if (!enabled) { + debug("....PCIE link error. Skipping scan." + "LTSSM=0x%02x\n", temp16); + hose->last_busno = hose->first_busno; + return; + } + + pci->pme_msg_det = 0xffffffff; + pci->pme_msg_int_en = 0xffffffff; +#ifdef DEBUG + pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); + neg_link_w = (temp16 & 0x3f0 ) >> 4; + debug("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", + ltssm, neg_link_w); +#endif + hose->current_busno++; /* Start scan with secondary */ + pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); + + } else { +#if 0 +/* done in pci_hose_config_device() */ + pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); + temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, temp16); + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); +#endif + } + + /* Call setup to allocate PCSRBAR window */ + pciauto_setup_device(hose, dev, 1, hose->pci_mem, + hose->pci_prefetch, hose->pci_io); + + printf (" Scanning PCI bus %02x\n", hose->current_busno); + hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno); + + if ( bridge ) { /* update limit regs and subordinate busno */ + pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); + } + + /* Clear all error indications */ + + if (pci->pme_msg_det && pci->pme_msg_det != 0xffffffff) { + debug("pci_fsl_init: pme_msg_det@%x=%x. Clearing\n", + &pci->pme_msg_det, pci->pme_msg_det); + pci->pme_msg_det = 0xffffffff; + } + + if (pci->pedr) { + debug("pci_fsl_init: pedr@%x=%x. Clearing\n", + &pci->pedr, pci->pedr); + pci->pedr = 0xffffffff; + } + + pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); + if (temp16) { + debug("pci_fsl_init: PCI_DSR@%x=%x. Clearing\n", + PCI_DSR, temp16); + pci_hose_write_config_word(hose, dev, + PCI_DSR, 0xffff); + } + + pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); + if (temp16) { + debug("pci_fsl_init: PCI_SEC_STATUS@%x=%x. Clearing\n", + PCI_SEC_STATUS, temp16); + pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); + } +} + +#endif /* CONFIG_FSL_PCI */ diff --git a/include/asm-ppc/immap_fsl_pci.h b/include/asm-ppc/immap_fsl_pci.h new file mode 100644 index 00000000000..bd732b66889 --- /dev/null +++ b/include/asm-ppc/immap_fsl_pci.h @@ -0,0 +1,150 @@ +/* (C) Copyright 2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __IMMAP_85xx_fsl_pci__ +#define __IMMAP_85xx_fsl_pci__ + +/* + * Common PCI/PCIE Register structure for mpc85xx and mpc86xx + */ + +/* + * PCI Translation Registers + */ +typedef struct pci_outbound_window { + u32 potar; /* 0x00 - Address */ + u32 potear; /* 0x04 - Address Extended */ + u32 powbar; /* 0x08 - Window Base Address */ + u32 res1; + u32 powar; /* 0x10 - Window Attributes */ +#define POWAR_EN 0x80000000 +#define POWAR_IO_READ 0x00080000 +#define POWAR_MEM_READ 0x00040000 +#define POWAR_IO_WRITE 0x00008000 +#define POWAR_MEM_WRITE 0x00004000 + u32 res2[3]; +} pot_t; + +typedef struct pci_inbound_window { + u32 pitar; /* 0x00 - Address */ + u32 res1; + u32 piwbar; /* 0x08 - Window Base Address */ + u32 piwbear; /* 0x0c - Window Base Address Extended */ + u32 piwar; /* 0x10 - Window Attributes */ +#define PIWAR_EN 0x80000000 +#define PIWAR_PF 0x20000000 +#define PIWAR_LOCAL 0x00f00000 +#define PIWAR_READ_SNOOP 0x00050000 +#define PIWAR_WRITE_SNOOP 0x00005000 + u32 res2[3]; +} pit_t; + +/* PCI/PCI Express Registers */ +typedef struct ccsr_pci { + u32 cfg_addr; /* 0x000 - PCI Configuration Address Register */ + u32 cfg_data; /* 0x004 - PCI Configuration Data Register */ + u32 int_ack; /* 0x008 - PCI Interrupt Acknowledge Register */ + u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */ + u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */ + u32 config; /* 0x014 - PCIE CONFIG Register */ + char res2[8]; + u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */ + u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */ + u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */ + u32 pm_command; /* 0x02c - PCIE PM Command register */ + char res4[3016]; /* (- #xbf8 #x30)3016 */ + u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */ + u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */ + + pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */ + u32 res5[64]; + pit_t pit[3]; /* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */ +#define PIT3 0 +#define PIT2 1 +#define PIT1 2 + +#if 0 + u32 potar0; /* 0xc00 - PCI Outbound Transaction Address Register 0 */ + u32 potear0; /* 0xc04 - PCI Outbound Translation Extended Address Register 0 */ + char res5[8]; + u32 powar0; /* 0xc10 - PCI Outbound Window Attributes Register 0 */ + char res6[12]; + u32 potar1; /* 0xc20 - PCI Outbound Transaction Address Register 1 */ + u32 potear1; /* 0xc24 - PCI Outbound Translation Extended Address Register 1 */ + u32 powbar1; /* 0xc28 - PCI Outbound Window Base Address Register 1 */ + char res7[4]; + u32 powar1; /* 0xc30 - PCI Outbound Window Attributes Register 1 */ + char res8[12]; + u32 potar2; /* 0xc40 - PCI Outbound Transaction Address Register 2 */ + u32 potear2; /* 0xc44 - PCI Outbound Translation Extended Address Register 2 */ + u32 powbar2; /* 0xc48 - PCI Outbound Window Base Address Register 2 */ + char res9[4]; + u32 powar2; /* 0xc50 - PCI Outbound Window Attributes Register 2 */ + char res10[12]; + u32 potar3; /* 0xc60 - PCI Outbound Transaction Address Register 3 */ + u32 potear3; /* 0xc64 - PCI Outbound Translation Extended Address Register 3 */ + u32 powbar3; /* 0xc68 - PCI Outbound Window Base Address Register 3 */ + char res11[4]; + u32 powar3; /* 0xc70 - PCI Outbound Window Attributes Register 3 */ + char res12[12]; + u32 potar4; /* 0xc80 - PCI Outbound Transaction Address Register 4 */ + u32 potear4; /* 0xc84 - PCI Outbound Translation Extended Address Register 4 */ + u32 powbar4; /* 0xc88 - PCI Outbound Window Base Address Register 4 */ + char res13[4]; + u32 powar4; /* 0xc90 - PCI Outbound Window Attributes Register 4 */ + char res14[268]; + u32 pitar3; /* 0xda0 - PCI Inbound Translation Address Register 3 */ + char res15[4]; + u32 piwbar3; /* 0xda8 - PCI Inbound Window Base Address Register 3 */ + u32 piwbear3; /* 0xdac - PCI Inbound Window Base Extended Address Register 3 */ + u32 piwar3; /* 0xdb0 - PCI Inbound Window Attributes Register 3 */ + char res16[12]; + u32 pitar2; /* 0xdc0 - PCI Inbound Translation Address Register 2 */ + char res17[4]; + u32 piwbar2; /* 0xdc8 - PCI Inbound Window Base Address Register 2 */ + u32 piwbear2; /* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */ + u32 piwar2; /* 0xdd0 - PCI Inbound Window Attributes Register 2 */ + char res18[12]; + u32 pitar1; /* 0xde0 - PCI Inbound Translation Address Register 1 */ + char res19[4]; + u32 piwbar1; /* 0xde8 - PCI Inbound Window Base Address Register 1 */ + char res20[4]; + u32 piwar1; /* 0xdf0 - PCI Inbound Window Attributes Register 1 */ + char res21[12]; +#endif + u32 pedr; /* 0xe00 - PCI Error Detect Register */ + u32 pecdr; /* 0xe04 - PCI Error Capture Disable Register */ + u32 peer; /* 0xe08 - PCI Error Interrupt Enable Register */ + u32 peattrcr; /* 0xe0c - PCI Error Attributes Capture Register */ + u32 peaddrcr; /* 0xe10 - PCI Error Address Capture Register */ +/* u32 perr_disr * 0xe10 - PCIE Erorr Disable Register */ + u32 peextaddrcr; /* 0xe14 - PCI Error Extended Address Capture Register */ + u32 pedlcr; /* 0xe18 - PCI Error Data Low Capture Register */ + u32 pedhcr; /* 0xe1c - PCI Error Error Data High Capture Register */ + u32 gas_timr; /* 0xe20 - PCI Gasket Timer Register */ +/* u32 perr_cap_stat; * 0xe20 - PCIE Error Capture Status Register */ + char res22[4]; + u32 perr_cap0; /* 0xe28 - PCIE Error Capture Register 0 */ + u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */ + u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */ + u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */ + char res23[456]; /* (- #x1000 #xe38) 456 */ +} ccsr_fsl_pci_t; + +#endif /*__IMMAP_fsl_pci__*/ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 808c19f7673..5a511e53244 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -46,8 +46,10 @@ #define CFG_RESET_ADDRESS 0xfff00100 -/*#undef CONFIG_PCI*/ -#define CONFIG_PCI +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ +#define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -76,6 +78,9 @@ #define L2_ENABLE (L2CR_L2E) #ifndef CONFIG_SYS_CLK_FREQ +#ifndef __ASSEMBLY__ +extern unsigned long get_board_sys_clk(unsigned long dummy); +#endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) #endif @@ -93,6 +98,9 @@ #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ +#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) +#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) + /* * DDR Setup */ @@ -296,9 +304,9 @@ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ /* PCI view of System Memory */ #define CFG_PCI_MEMORY_BUS 0x00000000 @@ -311,10 +319,10 @@ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe3000000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) @@ -396,20 +404,20 @@ * 0xa000_0000 512M PCI-Express 2 Memory * Changed it for operating from 0xd0000000 */ -#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ +#define CFG_DBAT1L ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_DBAT1U (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP) +#define CFG_IBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT1U CFG_DBAT1U /* * BAT2 512M Cache-inhibited, guarded * 0xc000_0000 512M RapidIO Memory */ -#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ +#define CFG_DBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) -#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_DBAT2U (CFG_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT2U CFG_DBAT2U /* @@ -428,10 +436,10 @@ * 0xe300_0000 16M PCI-Express 2 I/0 * Note that this is at 0xe0000000 */ -#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ +#define CFG_DBAT4L ( CFG_PCI1_IO_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) -#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_DBAT4U (CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT4U CFG_DBAT4U /* diff --git a/include/pci.h b/include/pci.h index 7c9a0e34410..8e5dacc0df6 100644 --- a/include/pci.h +++ b/include/pci.h @@ -302,6 +302,12 @@ #define PCI_MAX_PCI_DEVICES 32 #define PCI_MAX_PCI_FUNCTIONS 8 +#define PCI_DCR 0x54 /* PCIe Device Control Register */ +#define PCI_DSR 0x56 /* PCIe Device Status Register */ +#define PCI_LSR 0x5e /* PCIe Link Status Register */ +#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ +#define PCI_LTSSM_L0 0x16 /* L0 state */ + /* Include the ID list */ #include -- cgit v1.3.1 From 5728be389e65fd47f34b33c2596271eb4db751ae Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 6 Aug 2007 01:01:49 +0200 Subject: Coding style cleanup. Update CHANGELOG. Signed-off-by: Wolfgang Denk --- CHANGELOG | 931 ++++++++++++++++++++++++++++++++++++++++++--- cpu/ppc4xx/44x_spd_ddr.c | 2 +- drivers/tsec.c | 62 +-- include/configs/ADNPESC1.h | 6 +- include/configs/APC405.h | 2 +- include/configs/Adder.h | 8 +- include/configs/BAB7xx.h | 6 +- include/configs/BC3450.h | 2 +- include/configs/CANBT.h | 2 +- include/configs/CPCI750.h | 24 +- include/configs/CU824.h | 2 +- 11 files changed, 931 insertions(+), 116 deletions(-) (limited to 'cpu') diff --git a/CHANGELOG b/CHANGELOG index 207f1bc653e..58ef66ecdc4 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,830 @@ +commit 8092fef4c29b395958bb649647da7e3775731517 +Author: Martin Krause +Date: Tue Dec 12 14:26:01 2006 +0100 + + Add functions to list of exported functions + + Additionally export the following fuctions (to make trab_config build again): + - simple_strtol() + - strcmp() + + Also bump the ABI version to reflect this change + + Signed-off-by: Martin Krause + +commit 63cec5814fab5d2b1c86982327433807a5ac0249 +Author: Ed Swarthout +Date: Thu Aug 2 14:09:49 2007 -0500 + + Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. + + All of the PCI/PCI-Express driver and initialization code that + was in the MPC8641HPCN port has now been moved into the common + drivers/fsl_pci_init.c. In a subsequent patch, this will be + utilized by the 85xx ports as well. + + Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. + + Also enable the second PCI-Express controller on 8641 + by getting its BATS and CFG_ setup right. + + Fixed a u16 vendor compiler warning in AHCI driver too. + + Signed-off-by: Ed Swarthout + Signed-off-by: Zhang Wei + Signed-off-by: Jon Loeliger + +commit c7e717ebc2b044d7a71062552c9dc0f54ea9b779 +Author: Andy Fleming +Date: Fri Aug 3 04:05:25 2007 -0500 + + Add Marvell 1149 PHY support to the TSEC + +commit 63e22764d2f8653f68888c667eb65b3996b52680 +Author: Wolfgang Denk +Date: Thu Aug 2 10:11:18 2007 +0200 + + Minor cleanup of _nand build rules. + +commit cdd917a43da6fa7fc8f54a3cc9f420ce5ecf3197 +Author: Wolfgang Denk +Date: Thu Aug 2 00:48:45 2007 +0200 + + Fix build errors and warnings / code cleanup. + + Signed-off-by: Wolfgang Denk + +commit 5a56af3b522ba47fb33a3fee84d23bf1e5429654 +Author: Andy Fleming +Date: Fri Jun 8 16:41:18 2007 -0500 + + Remove erroneous errata code from Marvel 88E1111S driver + + The Marvel 88E1111S driver for the TSEC was copied from the + 88E1101 driver, and included a fix for an erratum which does not + exist on that part. Now it is removed + + Signed-off-by: Andy Fleming + +commit 982efcf23fd03647e01e2fbe28a7a36239156cc0 +Author: Andy Fleming +Date: Tue Jun 5 16:38:44 2007 -0500 + + From: eran liberty + + adds the reset register to 85xx immap + + Signed-off-by: Eran Liberty + Signed-off-by: Andy Fleming + +commit d3ec0d943a045bdb99e159e7bbc77430e09f11d7 +Author: Andy Fleming +Date: Thu May 10 17:50:01 2007 -0500 + + Polished the 85xx ADS config files + + Made the boot commands use device trees by default. + Also moved the ramdisk to 1000000 (I think the previous address + was getting overridden during boot). + + Signed-off-by: Andy Fleming + +commit bfb37b32d1b0b03f18077dba49cc66a6e76fa038 +Author: Ed Swarthout +Date: Wed May 9 11:03:32 2007 -0500 + + 8544ds: Fix Makefile after moving pixis to board/freescale. + + The OBJTREE != SRCTREE build scenario was broken. + This fixes it. + + Signed-off-by: Ed Swarthout + Signed-off-by: Jon Loeliger + +commit 2a3cee43c3b71fa5b8d91db19f05067865290f3e +Author: Andy Fleming +Date: Wed May 9 00:54:20 2007 -0500 + + tsec: Fix PHY code to match first driver + + Jarrold Wen noticed that the generic PHY code always matches + under the current implementation. Change it so the first match + wins, and *only* unknown PHYs trigger the generic driver + + Signed-off-by: Andy Fleming + +commit ccc091aac61a38cd998d575d92f7232e256d6312 +Author: Andy Fleming +Date: Tue May 8 17:27:43 2007 -0500 + + Add support for CPM device tree configuration to 8560 ADS + + * Adds code to modify CPM frequencies + * Cleans up the config file to #define TSEC and (for now) #undef FCC + * Adds the MII command for all 8560 ADS configurations + * Updates config file to provide convenience commands for booting + with a device tree + + Signed-off-by: Vitaly Bordug + Signed-off-by: Andy Fleming + +commit 7507d56ccaf7aae1c474342a9a5540165cd7e9d9 +Author: Andy Fleming +Date: Tue May 8 17:23:02 2007 -0500 + + Fix Marvell 88e1145 PHY init code + + Fix a bug in the Marvell 88e1145 PHY init code in the TSEC driver + where the reset was being done after the errata code instead of + before. + + Signed-off-by: Haiying Wang + Signed-off-by: Andy Fleming + +commit 5dc210dec5bace98a50b6ba905347890091a9bb0 +Author: Ed Swarthout +Date: Wed Jul 11 14:52:16 2007 -0500 + + Add simple agent/end-point configuration in PCI AutoConfig for PCI_CLASS_PROCESSOR_POWERPC. + + Signed-off-by: Ed Swarthout + +commit e8b85f3ba4cd8930e0a2fea2100c815d64201765 +Author: Ed Swarthout +Date: Wed Jul 11 14:52:08 2007 -0500 + + pciauto setup bridge + + The P2P bridge bus numbers programmed into the device are relative to + hose->first_busno. + + Signed-off-by: Ed Swarthout + +commit 571f49fa717004ca4268b4e24057efc7bf9f987b +Author: Ed Swarthout +Date: Wed Jul 11 14:52:01 2007 -0500 + + Support PCIe extended config registers + + FSL PCIe block has extended cfg registers in the 100 and 400 range. + For example, to read the LTSSM register: pci display .0 404 1 + + Signed-off-by: Ed Swarthout + +commit ba5feb12581bb2912ce301e4866b71f846e9fc07 +Author: Ed Swarthout +Date: Wed Jul 11 14:51:48 2007 -0500 + + Minor improvements to drivers/pci_auto.c + + - Make pciauto_{pre,post}scan_setup_bridge non-static + - Added physical address display in debug messages. + + Signed-off-by: Ed Swarthout + +commit 40e81addab7bb74d20ddf681ce9babc880a828ee +Author: Ed Swarthout +Date: Wed Jul 11 14:51:35 2007 -0500 + + Start pci hose scan from hose->current_busno. + + Ensure hose->current_busno is not less than first_busno. This fixes + broken board code which leaves current_busno=0 when first_busno is + greater than 0 for the cases with multiple controllers. + + Signed-off-by: Ed Swarthout + +commit 3865b1fb7843a08ad49a6319a36415752276ff48 +Author: Stefan Roese +Date: Wed Jul 11 12:13:53 2007 +0200 + + Fix some compile problems introduced by the latest CFG_CMD_xxx cleanup + + Signed-off-by: Stefan Roese + +commit e9514751cfa5cce61ea699fa0d3eb37898a5eeb5 +Author: Stefan Roese +Date: Sun Jul 8 13:44:27 2007 +0200 + + Fix malloc problem introduced with the relocation fixup for the PPC platform + + The relocation fixup didn't handle the malloc pointer initialization + correctly. This patch fixes this problem. Tested successfully on 4xx. + The relocation fixup patches for 4xx will follow soon. + + Signed-off-by: Stefan Roese + +commit b3aff0cb9ecf236d7e8c93761dd1dadf6837a582 +Author: Jon Loeliger +Date: Tue Jul 10 11:19:50 2007 -0500 + + disk/ doc/ lib_*/ and tools/: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit ddb5d86f0215bcb6c293510c50eb050e92883b7a +Author: Jon Loeliger +Date: Tue Jul 10 11:13:21 2007 -0500 + + drivers/: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit f40a7f3e3888b42a43674b099e5470022c8c544c +Author: Jon Loeliger +Date: Tue Jul 10 11:07:56 2007 -0500 + + fs/: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit 610f2e9c28a9c101e09fa1b78143cf5f00ed1593 +Author: Jon Loeliger +Date: Tue Jul 10 11:05:02 2007 -0500 + + net/: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit 902531788376046da212afd1661cffb62f3daa1c +Author: Jon Loeliger +Date: Tue Jul 10 11:02:44 2007 -0500 + + common/: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit d39b57415838c73fb0a37eca84de3c68ba990586 +Author: Jon Loeliger +Date: Tue Jul 10 10:48:22 2007 -0500 + + board/[j-z]*: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit 77a318545d57aefa844752465b94c7e09a3f26d0 +Author: Jon Loeliger +Date: Tue Jul 10 10:39:10 2007 -0500 + + board/[A-Za-i]*: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit 068b60a0eb7e73b243ca55399f2a7df76e2c3f3d +Author: Jon Loeliger +Date: Tue Jul 10 10:27:39 2007 -0500 + + cpu/ rtc/ include/: Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit 079a136c3588814784561d6e4856970ee82d6e2a +Author: Jon Loeliger +Date: Tue Jul 10 10:12:10 2007 -0500 + + include/configs/[p-z]* + misc: Cleanup BOOTP and lingering CFG_CMD_*. + + Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h + used to be included but CONFIG_BOOTP_MASK was not defined. + + Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit 7f5c01577400c74cc5bac74f41dd0d3c79df623c +Author: Jon Loeliger +Date: Tue Jul 10 09:38:02 2007 -0500 + + include/configs/[g-o]*: Cleanup BOOTP and lingering CFG_CMD_*. + + Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h + used to be included but CONFIG_BOOTP_MASK was not defined. + + Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit 80ff4f99b84b64edca3fd10da365ec1493be1c95 +Author: Jon Loeliger +Date: Tue Jul 10 09:29:01 2007 -0500 + + include/configs/[a-e]*: Cleanup BOOTP and lingering CFG_CMD_*. + + Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h + used to be included but CONFIG_BOOTP_MASK was not defined. + + Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit a1aa0bb502e25fd598b5e0ccdfb2c174921d714a +Author: Jon Loeliger +Date: Tue Jul 10 09:22:23 2007 -0500 + + include/configs/[P-Z]*: Cleanup BOOTP and lingering CFG_CMD_*. + + Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h + used to be included but CONFIG_BOOTP_MASK was not defined. + + Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit 659e2f6736232a08acca8785c206e2b4d9cd07d7 +Author: Jon Loeliger +Date: Tue Jul 10 09:10:49 2007 -0500 + + include/configs/[J-O]*: Cleanup BOOTP and lingering CFG_CMD_*. + + Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h + used to be included but CONFIG_BOOTP_MASK was not defined. + + Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit 11799434c5ff15a612577bb1ad1f4ea1a0595e4b +Author: Jon Loeliger +Date: Tue Jul 10 09:02:57 2007 -0500 + + include/configs/[A-I]*: Cleanup BOOTP and lingering CFG_CMD_*. + + Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h + used to be included but CONFIG_BOOTP_MASK was not defined. + + Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit 1fe80d79c5c4e52d3410a7ab4b8515da095cdab3 +Author: Jon Loeliger +Date: Mon Jul 9 22:08:34 2007 -0500 + + Finally retire cmd_confdefs.h and CONFIG_BOOTP_MASK! + + All of the choices for CONFIG_BOOTP_ are now documented in + the README file. You must now individually select exactly + the set that you want using a series of + #define CONFIG_BOOTP_ + statements in the board port config files now. + + Signed-off-by: Jon Loeliger + +commit d3b8c1a743dcd31625c99e6a44590f207eb00028 +Author: Jon Loeliger +Date: Mon Jul 9 21:57:31 2007 -0500 + + include/configs/[m-z]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. + + Signed-off-by: Jon Loeliger + +commit 2fd90ce575b02d189cbf443c85309bcd001aa393 +Author: Jon Loeliger +Date: Mon Jul 9 21:48:26 2007 -0500 + + include/configs/[a-m]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. + + Signed-off-by: Jon Loeliger + +commit 37d4bb70586659dedef1658ce1bed071be098aec +Author: Jon Loeliger +Date: Mon Jul 9 21:38:02 2007 -0500 + + include/configs/[T-Z]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. + + Signed-off-by: Jon Loeliger + +commit 18225e8dd1950bd6dbf35011e436db7f474c187d +Author: Jon Loeliger +Date: Mon Jul 9 21:31:24 2007 -0500 + + include/configs/[P-S]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. + + Signed-off-by: Jon Loeliger + +commit 7be044e4ea644b0ef1c486dadc1a4c2665b4374d +Author: Jon Loeliger +Date: Mon Jul 9 21:24:19 2007 -0500 + + include/configs/[H-N]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. + + Signed-off-by: Jon Loeliger + +commit 5d2ebe1b3ef0055c661bb1a0d252bf252380069f +Author: Jon Loeliger +Date: Mon Jul 9 21:16:53 2007 -0500 + + include/configs/[A-G]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. + + Signed-off-by: Jon Loeliger + +commit f55f7f8d83f36021ab1f0e3d738f5d8c8083a7e3 +Author: Jon Loeliger +Date: Mon Jul 9 19:12:30 2007 -0500 + + Retire CONFIG_COMMANDS finally. + Strip old CFG_CMD_* symbols out. + + Signed-off-by: Jon Loeliger + +commit b5501f7d720fed99ab0b42c83f5dea52868ce007 +Author: Jon Loeliger +Date: Mon Jul 9 19:10:03 2007 -0500 + + Update README.* to reference new CONFIG_CMD_* names now. + + Signed-off-by: Jon Loeliger + +commit 4431283c7e6d54ae180d466e51bf2d97471a0ad9 +Author: Jon Loeliger +Date: Mon Jul 9 19:06:00 2007 -0500 + + cpu/m*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 3a1ed1e1f922c419bb71f7df4949d783ade369fa +Author: Jon Loeliger +Date: Mon Jul 9 18:57:22 2007 -0500 + + cpu/[7a-ln-z]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit ab3abcbabd840928fb1eb5122118ca466b5e5013 +Author: Jon Loeliger +Date: Mon Jul 9 18:45:16 2007 -0500 + + board/[q-z]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 3fe00109a5f12de55b6e25b1f98dfc24bc9090c9 +Author: Jon Loeliger +Date: Mon Jul 9 18:38:39 2007 -0500 + + board/[m-p]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit c508a4cefd8a953fc64957650506a035e6e3d9d1 +Author: Jon Loeliger +Date: Mon Jul 9 18:31:28 2007 -0500 + + board/[f-l]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit b9307262f8a9f3b5c9e15a6067eadc17407146f6 +Author: Jon Loeliger +Date: Mon Jul 9 18:24:55 2007 -0500 + + board/[d-e]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit fcec2eb93e126400009729328e797f12bc94f1fd +Author: Jon Loeliger +Date: Mon Jul 9 18:19:09 2007 -0500 + + board/[A-Za-c]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit a593814f2be0c9cdc3133cd550b167b8a988328f +Author: Jon Loeliger +Date: Mon Jul 9 18:10:50 2007 -0500 + + rtc/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 67350568f9d46e66c21829f3513b3db0caeb948b +Author: Jon Loeliger +Date: Mon Jul 9 18:05:38 2007 -0500 + + lib_{arm,avr32,blackfin,generic,i386}/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 7def6b34f910f08d7ef0a14646da067719237ca2 +Author: Jon Loeliger +Date: Mon Jul 9 18:02:11 2007 -0500 + + lib_{m68k,microblaze,mips,ppc}/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit dd60d1223b99a88a7216f3e041fe40634ad4c2bb +Author: Jon Loeliger +Date: Mon Jul 9 17:56:50 2007 -0500 + + fs/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit c91898bbc505aff3e12a807af88e76da18efb7ee +Author: Jon Loeliger +Date: Mon Jul 9 17:46:09 2007 -0500 + + tools/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 643d1ab23960950b52e0a2803c2d3ea4c558fa01 +Author: Jon Loeliger +Date: Mon Jul 9 17:45:14 2007 -0500 + + net/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit cb51c0bf88f95a1bca68324b0126f8eed8b43273 +Author: Jon Loeliger +Date: Mon Jul 9 17:39:42 2007 -0500 + + drivers/[n-z]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 07d38a17e964aec4c7827f0ee9a583bc8cc1ad6b +Author: Jon Loeliger +Date: Mon Jul 9 17:30:01 2007 -0500 + + drivers/[a-m]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit cde5c64d17cf4834aa7b5c373f288bc7dad27b29 +Author: Jon Loeliger +Date: Mon Jul 9 17:22:37 2007 -0500 + + disk/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 639221c76c88215bd55af83ad174fc30d1940f8f +Author: Jon Loeliger +Date: Mon Jul 9 17:15:49 2007 -0500 + + include/: Remove obsolete references to CONFIG_COMMANDS + Mostly removed from comments here. + + Signed-off-by: Jon Loeliger + +commit 4ef218f6fdf8d747f4589da5252b004e7d2c2876 +Author: Wolfgang Denk +Date: Tue Jul 10 00:01:28 2007 +0200 + + Coding style cleanup; update CHANGELOG. + + Signed-off-by: Wolfgang Denk + +commit c3517f919d0f61650cf3027fd4faf0f631142f6c +Author: Jon Loeliger +Date: Sun Jul 8 18:10:08 2007 -0500 + + common/* non-cmd*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit fd9bcaa35be64fe41a4223fdb6ecdbad52470b39 +Author: Jon Loeliger +Date: Sun Jul 8 18:05:39 2007 -0500 + + common/cmd_[p-x]*: Remove obsolete references to CONFIG_COMMANDS. + + Signed-off-by: Jon Loeliger + +commit c76fe47425afc7d5d670ff0539823c85d65d9c42 +Author: Jon Loeliger +Date: Sun Jul 8 18:02:23 2007 -0500 + + common/cmd_[i-n]*: Remove obsolete references to CONFIG_COMMANDS. + + Signed-off-by: Jon Loeliger + +commit baa26db4113679b80970ff447d91cc10217742a6 +Author: Jon Loeliger +Date: Sun Jul 8 17:51:39 2007 -0500 + + common/cmd_[af]*: Remove obsolete references to CONFIG_COMMANDS. + + Signed-off-by: Jon Loeliger + +commit af075ee96e52dda7b6bca6c937588aeaaec5f2cd +Author: Jon Loeliger +Date: Sun Jul 8 17:02:01 2007 -0500 + + Clear up confusion over the CMD_POST and POST_DIAG mess. + + For some reason, CONFIG_POST permeated as CONFIG_CMD_POST_DIAG + when it really means just CONFIG_CMD_DIAG. There is no CMD_POST. + Clear this mess up some. + + Signed-off-by: Jon Loeliger + +commit b3631487105a57ab7cbadfc26efbaf9676275018 +Author: Jon Loeliger +Date: Sun Jul 8 15:45:08 2007 -0500 + + Remove references to the old cmd_confdefs.h include file. + + Signed-off-by: Jon Loeliger + +commit a22d4da95e20049b4daa1c2a022f61e8a72f2fb6 +Author: Jon Loeliger +Date: Sun Jul 8 15:42:59 2007 -0500 + + include/configs: Catch some CONFIG_CMD_* conversion stragglers. + + Use new CONFIG_CMD_* in lwmon5.h board config file. + Fix CONFIG_CMD_* typo braindamage in omap1510inn.h + + Signed-off-by: Jon Loeliger + +commit a5562901661bd428f7e5feb333f796372cb81019 +Author: Jon Loeliger +Date: Sun Jul 8 15:31:57 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various [TUVWZYZ]* named board config files. + + Signed-off-by: Jon Loeliger + +commit fe7f782d5b8c64a0195c68c31a0a11d4f641355e +Author: Jon Loeliger +Date: Sun Jul 8 15:02:44 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various S* named board config files. + + Signed-off-by: Jon Loeliger + +commit e9a0f8f15c11f337967aa0600ad6e8af33037f50 +Author: Jon Loeliger +Date: Sun Jul 8 15:12:40 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various R* named board config files. + + Signed-off-by: Jon Loeliger + +commit 12aa9fd23d724bd6ab88e1baa0db35133a27303f +Author: Jon Loeliger +Date: Sun Jul 8 14:55:07 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various Q* named board config files. + + Signed-off-by: Jon Loeliger + +commit acf0269779422f3e147d2ddfb499c9f6ff10ad5e +Author: Jon Loeliger +Date: Sun Jul 8 14:49:44 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various P* named board config files. + + Signed-off-by: Jon Loeliger + +commit e18a1061a8630cb67995fdf99afd3fb50d1b187d +Author: Jon Loeliger +Date: Sun Jul 8 14:21:43 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various [NO]* named board config files. + + Signed-off-by: Jon Loeliger + +commit 8353e139bfad9059c54f5b2421f1a3090e15a2e2 +Author: Jon Loeliger +Date: Sun Jul 8 14:14:17 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various M* named board config files. + + Signed-off-by: Jon Loeliger + +commit 348f258f24253433e4a2302a0bbceb6740a67246 +Author: Jon Loeliger +Date: Sun Jul 8 13:46:18 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various [IJKL]* named board config files. + + Signed-off-by: Jon Loeliger + +commit 6c4f4da9bfc9f9403f54fce678ed0364b7c86a6a +Author: Jon Loeliger +Date: Sun Jul 8 10:09:35 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various H* named board config files. + + Signed-off-by: Jon Loeliger + +commit 60a0876b5106b34220e459c208bbf648073306c0 +Author: Jon Loeliger +Date: Sat Jul 7 21:04:26 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various F* and G* named board config files. + + Signed-off-by: Jon Loeliger + +commit dcaa71562826a2466e894c868d132509dcda8444 +Author: Jon Loeliger +Date: Sat Jul 7 20:56:05 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various E* named board config files. + + Signed-off-by: Jon Loeliger + +commit 3c3227f3c737502311b25b72084573901cbbf17d +Author: Jon Loeliger +Date: Sat Jul 7 20:40:43 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various D* named board config files. + + Signed-off-by: Jon Loeliger + +commit 49cf7e8ee7ef943fdfe866ce28410b0bfbf6a26c +Author: Jon Loeliger +Date: Thu Jul 5 19:52:35 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various C* named board config files. + + Signed-off-by: Jon Loeliger + +commit de8b2a6e33298dcdb10bdda48db25e53c3089eba +Author: Jon Loeliger +Date: Thu Jul 5 19:32:07 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various B* named board config files. + + Signed-off-by: Jon Loeliger + +commit 498ff9a228485bd4b9f23d066bada268f9add1dd +Author: Jon Loeliger +Date: Thu Jul 5 19:13:52 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various A* named board config files. + + Since ADS860.h includes "board/fads/fads.h" with ramifications + on the CONFIG_COMMAND treatment, it too has to be adjusted to + exclude already configured commands in this same commit. + + Signed-off-by: Jon Loeliger + +commit 6b0a174a1e6f55e1f5a1fbb223cdad7645a4646e +Author: Stefan Roese +Date: Fri Jul 6 09:45:47 2007 +0200 + + Fix problem with get/setdcr commands introduced by cfg patches + + Signed-off-by: Stefan Roese + +commit f1152f8c28db4a22087c21c618a3f7baa48e9a4f +Author: Wolfgang Denk +Date: Fri Jul 6 02:50:19 2007 +0200 + + Code cleanup and default config update for STC GP3 SSA board. + + Signed-off-by: Wolfgang Denk + +commit e4dbe1b215f5c6c462e76909d240bd96472b84de +Author: Wolfgang Denk +Date: Thu Jul 5 17:56:27 2007 +0200 + + Fixing some typos etc. introduced mainly by cfg patches. + + Signed-off-by: Wolfgang Denk + +commit b6b4684546809f89c8bac72863ca49b5fd8ac0cd +Author: Wolfgang Denk +Date: Thu Jul 5 11:12:16 2007 +0200 + + Minor coding style cleanup. Update CHANGELOG. + commit dca3b3d6d6396b67e5e84af53452164923c73443 Author: Jon Loeliger Date: Wed Jul 4 22:33:46 2007 -0500 @@ -198,6 +1025,14 @@ Date: Wed Jul 4 22:30:06 2007 -0500 Signed-off-by: Jon Loeliger +commit b44896215a09c60fa40cae906f7ed207bbc2c492 +Author: Sergei Poselenov +Date: Thu Jul 5 08:17:37 2007 +0200 + + Merged POST framework with the current TOT. + + Signed-off-by: Sergei Poselenov + commit b24629fa377214d63bb40d1360e354b6d3e4af56 Author: Jon Loeliger Date: Wed Jun 13 13:23:15 2007 -0500 @@ -232,6 +1067,28 @@ Date: Wed Jun 13 13:21:37 2007 -0500 Signed-off-by: Jon Loeliger +commit f780b83316d9af1f61d71cc88b1917b387b9b995 +Author: Niklaus Giger +Date: Wed Jun 27 18:11:38 2007 +0200 + + resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPX + + Signed-off-by: Niklaus Giger + +commit 04e6c38b766eaa2f3287561563c9e215e0c3a0d4 +Author: Stefan Roese +Date: Wed Jul 4 10:06:30 2007 +0200 + + ppc4xx: Update lwmon5 board + + - Add optional ECC generation routine to preserve existing + RAM values. This is needed for the Linux log-buffer support + - Add optional DDR2 setup with CL=4 + - GPIO50 not used anymore + - Lime register setup added + + Signed-off-by: Stefan Roese + commit 6810a34677dbc446334f5e451f1682426dd33b49 Author: Grant Likely Date: Tue Jul 3 00:17:28 2007 -0600 @@ -440,14 +1297,6 @@ Date: Tue Jul 3 00:32:53 2007 -0600 Signed-off-by: Grant Likely -commit f1152f8c28db4a22087c21c618a3f7baa48e9a4f -Author: Wolfgang Denk -Date: Fri Jul 6 02:50:19 2007 +0200 - - Code cleanup and default config update for STC GP3 SSA board. - - Signed-off-by: Wolfgang Denk - commit 52b8704d0245e589f86d462e9ec25aeb7ecbbbdd Author: Wolfgang Denk Date: Wed Jul 4 00:43:53 2007 +0200 @@ -456,14 +1305,6 @@ Date: Wed Jul 4 00:43:53 2007 +0200 Signed-off-by: Wolfgang Denk -commit b44896215a09c60fa40cae906f7ed207bbc2c492 -Author: Sergei Poselenov -Date: Thu Jul 5 08:17:37 2007 +0200 - - Merged POST framework with the current TOT. - - Signed-off-by: Sergei Poselenov - commit 78e0cf2de7be7f1eaeeb622eb61fd50e4d5e205c Author: Wolfgang Denk Date: Wed Jul 4 00:38:38 2007 +0200 @@ -478,14 +1319,6 @@ Date: Mon Jun 11 19:03:44 2007 -0500 Signed-off-by: Jon Loeliger -commit f780b83316d9af1f61d71cc88b1917b387b9b995 -Author: Niklaus Giger -Date: Wed Jun 27 18:11:38 2007 +0200 - - resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPX - - Signed-off-by: Niklaus Giger - commit 602ad3b33d9ceef83dbab46be68646d645d637ee Author: Jon Loeliger Date: Mon Jun 11 19:03:39 2007 -0500 @@ -494,20 +1327,6 @@ Date: Mon Jun 11 19:03:39 2007 -0500 Signed-off-by: Jon Loeliger -commit 04e6c38b766eaa2f3287561563c9e215e0c3a0d4 -Author: Stefan Roese -Date: Wed Jul 4 10:06:30 2007 +0200 - - ppc4xx: Update lwmon5 board - - - Add optional ECC generation routine to preserve existing - RAM values. This is needed for the Linux log-buffer support - - Add optional DDR2 setup with CL=4 - - GPIO50 not used anymore - - Lime register setup added - - Signed-off-by: Stefan Roese - commit 72a074cec68e5bad60d63206c050974e08afd804 Author: Jon Loeliger Date: Mon Jun 11 19:03:34 2007 -0500 @@ -1875,7 +2694,7 @@ Date: Sat May 5 08:12:30 2007 +0200 5xxx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -2017,7 +2836,7 @@ Date: Sat May 5 08:12:30 2007 +0200 5xxx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -2148,7 +2967,7 @@ Date: Mon Apr 30 13:59:50 2007 -0500 Fix memory initialization on MPC8349E-mITX Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP. - This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary + This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary on some ITX boards, notably those with a revision 3.1 CPU. Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into @@ -2305,7 +3124,7 @@ Date: Mon Feb 12 13:34:55 2007 -0600 85xx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -2614,7 +3433,7 @@ Date: Fri Apr 20 14:12:26 2007 -0500 mpc86xx; Write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -2667,7 +3486,7 @@ Date: Thu Apr 19 23:14:39 2007 -0400 What was suppose to be a stack variable was declared as a pointer, overwriting random memory. - Also moved the libfdt.a requirement into the main Makefile. That is + Also moved the libfdt.a requirement into the main Makefile. That is The U-Boot Way. commit d21686263574e95cb3e9e9b0496f968b1b897fdb @@ -3262,7 +4081,7 @@ Date: Sat Mar 31 12:22:10 2007 -0400 Add a flattened device tree (fdt) command (1 of 2) The fdt command uses David Gibson's libfdt library to manipulate as well - as print the flattened device tree. This patch is the new command, + as print the flattened device tree. This patch is the new command, the second part is the modifications to the existing code. commit 3af0d587d93e0be5f96e1b30fa41e662f8b0803e @@ -3963,7 +4782,7 @@ Date: Tue Feb 13 10:41:42 2007 -0600 mpc83xx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, this patch + and some have both. To support all of these device trees, this patch updates ftp_cpu_setup() to write the MAC address to mac-address if it exists. This function already updates local-mac-address. @@ -4186,7 +5005,7 @@ Date: Wed Dec 6 21:23:55 2006 -0500 mpc83xx: Put the version (and magic) after the HRCW. - Put the version (and magic) after the HRCW. This puts it in a fixed + Put the version (and magic) after the HRCW. This puts it in a fixed location in flash, not at the start of flash but as close as we can get. Signed-off-by: Jerry Van Baren @@ -4480,7 +5299,7 @@ Date: Tue Feb 20 09:05:31 2007 +0100 [PATCH 7_9] Replace ace_readw_ace_writeb functions with macros - Register read/write does not need to be wrapped in a full function. The + Register read/write does not need to be wrapped in a full function. The patch replaces them with macros. Signed-off-by: Grant Likely @@ -4783,7 +5602,7 @@ commit fdef388758506765d4d6a7155c8f1584c63ff581 Author: roy zang Date: Mon Jan 22 13:19:21 2007 +0800 - use CFG_WRITE_SWAPPED_DATA define instead of define CFG_FLASH_CFI_SWAP + use CFG_WRITE_SWAPPED_DATA define instead of define CFG_FLASH_CFI_SWAP The patch by Heiko Schocher on Jan, 19, 2007 fixes cfi_driver bug for mpc7448hpc2 board. The default cfi_driver can support mpc7448hpc2 board. @@ -5471,7 +6290,7 @@ Date: Mon Nov 27 17:04:06 2006 +0100 [PATCH] Allow CONFIG_OF_FLAT_TREE to boot a non-arch/powerpc kernel This patch allows an arch/ppc kernel to be booted by just passing 1 or 2 - arguments to bootm. It removes the getenv("disable_of") test that used + arguments to bootm. It removes the getenv("disable_of") test that used to be used for this purpose. Signed-off-by: Grant Likely @@ -6047,7 +6866,7 @@ Date: Thu Nov 2 19:08:55 2006 +0800 Gigabit Ethernet ports,E0 and E1. It uses a single Management interface to manage the two physical connection devices (PHYs). Each Ethernet port has its own statistics monitor that tracks and reports key interface - statistics. Each port supports a 256-entry hash table for address + statistics. Each port supports a 256-entry hash table for address filtering. In addition, each port is bridged to the Switch Fabric through a 2-Kbyte transmit FIFO and a 4-Kbyte Receive FIFO. @@ -6093,7 +6912,7 @@ commit 87c4db09699c6b89176b31004afcb83eb1585d47 Author: roy zang Date: Thu Nov 2 18:59:15 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. mpc7448hpc2 board support high level code:tsi108 init + mpc7448hpc2. Signed-off-by: Alexandre Bounine @@ -6103,7 +6922,7 @@ commit 27801b8ab11c61b577e45742a515bb3b23b80241 Author: roy zang Date: Thu Nov 2 18:57:21 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. Make ,config.mk and link file for the mpc7448hpc2 board. Signed-off-by: Alexandre Bounine @@ -6113,7 +6932,7 @@ commit c6411c0c3bbc79f9ba8aef58296a42d8f9d8a0a6 Author: roy zang Date: Thu Nov 2 18:55:04 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. The mpc7448hpc2 board support header file. Signed-off-by: Alexandre Bounine @@ -6123,7 +6942,7 @@ commit 625bb5ddb50b243f931262ca8c46956409471917 Author: roy zang Date: Thu Nov 2 18:52:21 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. The mpc7448hpc2 board support low level assemble language init code. Signed-off-by: Alexandre Bounine @@ -6348,7 +7167,7 @@ Date: Tue Oct 24 23:47:37 2006 -0500 If a Multi-Image file contains a third image we try to use it as a device tree. The device tree image is assumed to be uncompressed in the - image file. We automatically allocate space for the device tree in memory + image file. We automatically allocate space for the device tree in memory and provide an 8k pad to allow more than a reasonable amount of growth. Additionally, a device tree that was contained in flash will now automatically diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index 8c18d0f4e21..4a31d323039 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -1017,7 +1017,7 @@ static int short_mem_test(void) */ for (i = 0; i < NUMMEMTESTS; i++) { for (j = 0; j < NUMMEMWORDS; j++) { -//printf("bank enabled base:%x\n", &membase[j]); + /*printf("bank enabled base:%x\n", &membase[j]);*/ membase[j] = test[i][j]; ppcDcbf((unsigned long)&(membase[j])); } diff --git a/drivers/tsec.c b/drivers/tsec.c index 1399d076891..60bef9af394 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -899,36 +899,36 @@ static void tsec_halt(struct eth_device *dev) } struct phy_info phy_info_M88E1149S = { - 0x1410ca, - "Marvell 88E1149S", - 4, - (struct phy_cmd[]){ /* config */ - /* Reset and configure the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {0x1d, 0x1f, NULL}, - {0x1e, 0x200c, NULL}, - {0x1d, 0x5, NULL}, - {0x1e, 0x0, NULL}, - {0x1e, 0x100, NULL}, - {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, - {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_88E1011_PHY_STATUS, miim_read, - &mii_parse_88E1011_psr}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + 0x1410ca, + "Marvell 88E1149S", + 4, + (struct phy_cmd[]){ /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x1d, 0x1f, NULL}, + {0x1e, 0x200c, NULL}, + {0x1d, 0x5, NULL}, + {0x1e, 0x0, NULL}, + {0x1e, 0x100, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, + &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, }; /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ @@ -1351,7 +1351,7 @@ struct phy_info *phy_info[] = { &phy_info_M88E1011S, &phy_info_M88E1111S, &phy_info_M88E1145, - &phy_info_M88E1149S, + &phy_info_M88E1149S, &phy_info_dm9161, &phy_info_lxt971, &phy_info_VSC8244, diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h index d4ee14c837f..77938b140da 100644 --- a/include/configs/ADNPESC1.h +++ b/include/configs/ADNPESC1.h @@ -563,8 +563,6 @@ #define CONFIG_POST CFG_POST_RTC #define CFG_NIOS_POST_WORD_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) - - /* * BOOTP options */ @@ -585,7 +583,7 @@ #undef CONFIG_CMD_DOC #undef CONFIG_CMD_DTT #undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_ELF #undef CONFIG_CMD_FAT #undef CONFIG_CMD_FDC #undef CONFIG_CMD_FDOS @@ -610,7 +608,6 @@ #undef CONFIG_CMD_DATE #endif - /*------------------------------------------------------------------------ * KGDB *----------------------------------------------------------------------*/ @@ -657,7 +654,6 @@ #undef CFG_LOAD_ADDR /* force error break */ #endif - /* MEM test area */ #if (CFG_SDRAM_SIZE != 0) diff --git a/include/configs/APC405.h b/include/configs/APC405.h index 6dcfbc15d4c..f6495e4841a 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -92,7 +92,7 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_EEPROM #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/Adder.h b/include/configs/Adder.h index 5e076dcc41c..4304ecca7de 100644 --- a/include/configs/Adder.h +++ b/include/configs/Adder.h @@ -67,10 +67,10 @@ */ #include -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING #define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h index d8d09838eb4..c11e9c911d3 100644 --- a/include/configs/BAB7xx.h +++ b/include/configs/BAB7xx.h @@ -84,10 +84,10 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_SCSI +#define CONFIG_CMD_SCSI #define CONFIG_CMD_IDE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_FDC +#define CONFIG_CMD_DATE +#define CONFIG_CMD_FDC #define CONFIG_CMD_ELF diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 844bdc5d883..5c2bfc991f5 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -192,7 +192,7 @@ #ifdef CONFIG_BC3450_USB #define CONFIG_CMD_USB #endif - + #ifdef CONFIG_PCI #define CONFIG_CMD_PCI #endif diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h index 0e082b318bb..ae32f6b14ac 100644 --- a/include/configs/CANBT.h +++ b/include/configs/CANBT.h @@ -72,7 +72,7 @@ #include #define CONFIG_CMD_IRQ -#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_EEPROM #undef CONFIG_CMD_NET diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 8d04104e58a..48e29a20876 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -148,18 +148,18 @@ */ #include -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_PCI -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_PCI +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 #define CONFIG_DOS_PARTITION diff --git a/include/configs/CU824.h b/include/configs/CU824.h index f7fdd2d6ee8..68e816a7443 100644 --- a/include/configs/CU824.h +++ b/include/configs/CU824.h @@ -73,7 +73,7 @@ */ #include -#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_BEDBUG #define CONFIG_CMD_DHCP #define CONFIG_CMD_PCI #define CONFIG_CMD_NFS -- cgit v1.3.1 From 1ded0242e437259366792d52b7e9d1e1931d8fa5 Mon Sep 17 00:00:00 2001 From: Lee Nipper Date: Thu, 14 Jun 2007 20:07:33 -0500 Subject: mpc83xx: Add support for 8360 silicon revision 2.1 This change adds 8360 silicon revision 2.1 support to u-boot. Signed-off-by: Lee Nipper Signed-off-by: Kim Phillips --- board/mpc8360emds/mpc8360emds.c | 4 +++- cpu/mpc83xx/cpu.c | 5 ++++- include/mpc83xx.h | 2 ++ 3 files changed, 9 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index 562eb8b53af..de4ca1e7747 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -103,7 +103,9 @@ int board_early_init_f(void) /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */ if (immr->sysconf.spridr == SPR_8360_REV20 || - immr->sysconf.spridr == SPR_8360E_REV20) + immr->sysconf.spridr == SPR_8360E_REV20 || + immr->sysconf.spridr == SPR_8360_REV21 || + immr->sysconf.spridr == SPR_8360E_REV21) bcsr[0xe] = 0x30; return 0; diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 841fe82428d..bfac227d68e 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -113,12 +113,14 @@ int checkcpu(void) case SPR_8360E_REV11: case SPR_8360E_REV12: case SPR_8360E_REV20: + case SPR_8360E_REV21: puts("MPC8360E, "); break; case SPR_8360_REV10: case SPR_8360_REV11: case SPR_8360_REV12: case SPR_8360_REV20: + case SPR_8360_REV21: puts("MPC8360, "); break; case SPR_8323E_REV10: @@ -150,7 +152,8 @@ int checkcpu(void) puts("MPC8313E, "); break; default: - puts("Rev: Unknown revision number.\nWarning: Unsupported cpu revision!\n"); + printf("Rev: Unknown revision number:%08x\n" + "Warning: Unsupported cpu revision!\n",spridr); return 0; } diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 336c0ac4f22..01df06bf192 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -86,6 +86,8 @@ #define SPR_8360_REV12 0x80490012 #define SPR_8360E_REV20 0x80480020 #define SPR_8360_REV20 0x80490020 +#define SPR_8360E_REV21 0x80480021 +#define SPR_8360_REV21 0x80490021 #define SPR_8323E_REV10 0x80620010 #define SPR_8323_REV10 0x80630010 -- cgit v1.3.1 From df33f6b4d6d63693dd9200808b242de1b86cb8e8 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 3 Jul 2007 13:04:34 -0500 Subject: Update SCCR programming in cpu_init_f() to support all 83xx processors Update the cpu_init_f() function in cpu/mpc83xx/cpu_init.c to program the bitfields for all 83xx processors. The code to update some bitfields was compiled only on some processors. Now, the bitfields are programmed as long as the corresponding CFG_SCCR option is defined in the board header file. This means that the board header file should not define any CFG_SCCR macros for bitfields that don't exist on that processor, otherwise the SCCR will be programmed incorrectly. Signed-off-by: Timur Tabi Signed-off-by: Kim Phillips --- cpu/mpc83xx/cpu_init.c | 14 ++++++++++++-- include/mpc83xx.h | 2 ++ 2 files changed, 14 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 3ac91619c4b..53a5f594739 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -83,20 +83,30 @@ void cpu_init_f (volatile immap_t * im) im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT); #endif -#ifdef CONFIG_MPC834X #ifdef CFG_SCCR_TSEC1CM /* TSEC1 clock mode */ im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT); #endif + #ifdef CFG_SCCR_TSEC2CM /* TSEC2 & I2C1 clock mode */ im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT); #endif + +#ifdef CFG_SCCR_TSEC1ON + /* TSEC1 clock switch */ + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) | (CFG_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT); +#endif + +#ifdef CFG_SCCR_TSEC2ON + /* TSEC2 clock switch */ + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) | (CFG_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT); +#endif + #ifdef CFG_SCCR_USBMPHCM /* USB MPH clock mode */ im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT); #endif -#endif /* CONFIG_MPC834X */ #ifdef CFG_SCCR_PCICM /* PCI & DMA clock mode */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 01df06bf192..829dbf93878 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -602,7 +602,9 @@ #define SCCR_TSEC1CM_3 0xC0000000 #define SCCR_TSEC1ON 0x20000000 +#define SCCR_TSEC1ON_SHIFT 29 #define SCCR_TSEC2ON 0x10000000 +#define SCCR_TSEC2ON_SHIFT 28 #endif -- cgit v1.3.1 From 9be39a67c9f8fef7107f5df09d673005f04d0963 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Mon, 25 Jun 2007 10:41:56 +0800 Subject: mpc83xx: Add support for the display of reset status 83xx processor family has many reset sources, such as power on reset, software hard reset, software soft reset, JTAG, bus monitor, software watchdog, check stop reset, external hard reset, external software reset. sometimes, to figure out the fault of system, we need to know the cause of reset early before the prompt of u-boot present. Signed-off-by: Dave Liu Signed-off-by: Kim Phillips --- cpu/mpc83xx/cpu_init.c | 36 ++++++++++++++++++++++++++++++++++++ include/common.h | 2 ++ lib_ppc/board.c | 6 ++++-- 3 files changed, 42 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 53a5f594739..722497966a1 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -257,3 +257,39 @@ int cpu_init_r (void) #endif return 0; } + +/* + * Figure out the cause of the reset + */ +int prt_83xx_rsr(void) +{ + static struct { + ulong mask; + char *desc; + } bits[] = { + { + RSR_SWSR, "Software Soft"}, { + RSR_SWHR, "Software Hard"}, { + RSR_JSRS, "JTAG Soft"}, { + RSR_CSHR, "Check Stop"}, { + RSR_SWRS, "Software Watchdog"}, { + RSR_BMRS, "Bus Monitor"}, { + RSR_SRS, "External/Internal Soft"}, { + RSR_HRS, "External/Internal Hard"} + }; + static int n = sizeof bits / sizeof bits[0]; + ulong rsr = gd->reset_status; + int i; + char *sep; + + puts("Reset Status:"); + + sep = " "; + for (i = 0; i < n; i++) + if (rsr & bits[i].mask) { + printf("%s%s", sep, bits[i].desc); + sep = ", "; + } + puts("\n\n"); + return 0; +} diff --git a/include/common.h b/include/common.h index ac29d3aac6c..a822d28d390 100644 --- a/include/common.h +++ b/include/common.h @@ -526,6 +526,8 @@ void cpu_init_f (void); int cpu_init_r (void); #if defined(CONFIG_8260) int prt_8260_rsr (void); +#elif defined(CONFIG_MPC83XX) +int prt_83xx_rsr (void); #endif /* $(CPU)/interrupts.c */ diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 325f5c219ce..c87d46c3d62 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -309,7 +309,9 @@ init_fnc_t *init_sequence[] = { prt_8260_rsr, prt_8260_clks, #endif /* CONFIG_8260 */ - +#if defined(CONFIG_MPC83XX) + prt_83xx_rsr, +#endif checkcpu, #if defined(CONFIG_MPC5xxx) prt_mpc5xxx_clks, @@ -376,7 +378,7 @@ void board_init_f (ulong bootflag) /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("": : :"memory"); -#if !defined(CONFIG_CPM2) +#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC83XX) /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); #endif -- cgit v1.3.1 From 26d02c9bbac1751c5e19294f000100b48d43a920 Mon Sep 17 00:00:00 2001 From: Jerry Van Baren Date: Wed, 4 Jul 2007 21:27:30 -0400 Subject: mpc83xx: Replace fdt_node_offset() with fdt_find_node_by_path(). The new name matches more closely the kernel's name, which is also a much better description. These are the mpc83xx changes made necessary by the function name change. Signed-off-by: Wolfgang Grandegger Acked-by: Gerald Van Baren Signed-off-by: Kim Phillips --- board/mpc8360emds/mpc8360emds.c | 5 ++--- board/mpc8360emds/pci.c | 20 +++++++++----------- cpu/mpc83xx/cpu.c | 9 +++------ 3 files changed, 14 insertions(+), 20 deletions(-) (limited to 'cpu') diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index de4ca1e7747..f63d3ae6514 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -30,8 +30,7 @@ #endif #if defined(CONFIG_OF_FLAT_TREE) #include -#endif -#if defined(CONFIG_OF_LIBFDT) +#elif defined(CONFIG_OF_LIBFDT) #include #include #endif @@ -683,7 +682,7 @@ ft_board_setup(void *blob, bd_t *bd) int nodeoffset; int tmp[2]; - nodeoffset = fdt_path_offset (fdt, "/memory"); + nodeoffset = fdt_find_node_by_path(fdt, "/memory"); if (nodeoffset >= 0) { tmp[0] = cpu_to_be32(bd->bi_memstart); tmp[1] = cpu_to_be32(bd->bi_memsize); diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c index 158effe0a9f..8d34dbe0468 100644 --- a/board/mpc8360emds/pci.c +++ b/board/mpc8360emds/pci.c @@ -20,8 +20,7 @@ #include #if defined(CONFIG_OF_FLAT_TREE) #include -#endif -#if defined(CONFIG_OF_LIBFDT) +#elif defined(CONFIG_OF_LIBFDT) #include #include #endif @@ -207,7 +206,7 @@ void pci_init_board(void) /* Switch temporarily to I2C bus #2 */ orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); + i2c_set_bus_num(1); val8 = 0; i2c_write(0x23, 0x6, 1, &val8, 1); @@ -311,26 +310,25 @@ ft_pci_setup(void *blob, bd_t *bd) int err; int tmp[2]; - nodeoffset = fdt_path_offset (fdt, "/" OF_SOC "/pci@8500"); + nodeoffset = fdt_find_node_by_path(fdt, "/" OF_SOC "/pci@8500"); if (nodeoffset >= 0) { tmp[0] = cpu_to_be32(hose[0].first_busno); tmp[1] = cpu_to_be32(hose[0].last_busno); err = fdt_setprop(fdt, nodeoffset, "bus-range", tmp, sizeof(tmp)); } } -#endif /* CONFIG_OF_LIBFDT */ -#ifdef CONFIG_OF_FLAT_TREE +#elif defined(CONFIG_OF_FLAT_TREE) void ft_pci_setup(void *blob, bd_t *bd) { - u32 *p; - int len; + u32 *p; + int len; - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); - if (p != NULL) { + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); + if (p != NULL) { p[0] = hose[0].first_busno; p[1] = hose[0].last_busno; - } + } } #endif /* CONFIG_OF_FLAT_TREE */ #endif /* CONFIG_PCI */ diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index bfac227d68e..40e8d0c987b 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -33,8 +33,7 @@ #include #if defined(CONFIG_OF_FLAT_TREE) #include -#endif -#if defined(CONFIG_OF_LIBFDT) +#elif defined(CONFIG_OF_LIBFDT) #include #include #endif @@ -490,7 +489,7 @@ ft_cpu_setup(void *blob, bd_t *bd) int j; for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) { - nodeoffset = fdt_path_offset(fdt, fixup_props[j].node); + nodeoffset = fdt_find_node_by_path(fdt, fixup_props[j].node); if (nodeoffset >= 0) { err = (*fixup_props[j].set_fn)(blob, nodeoffset, fixup_props[j].prop, bd); if (err < 0) @@ -501,9 +500,7 @@ ft_cpu_setup(void *blob, bd_t *bd) } } } -#endif - -#if defined(CONFIG_OF_FLAT_TREE) +#elif defined(CONFIG_OF_FLAT_TREE) void ft_cpu_setup(void *blob, bd_t *bd) { -- cgit v1.3.1 From 8be404459a6b7395415a57bb35e8377e3b2b5acb Mon Sep 17 00:00:00 2001 From: Jerry Van Baren Date: Wed, 4 Jul 2007 21:34:24 -0400 Subject: mpc83xx: Fix errors when CONFIG_OF_LIBFDT is enabled Several node strings were not correct (trailing slashes and properties in the strings) Added setting of the timebase-frequency. Improved error messages and use debug() instead of printf(). Signed-off-by: Gerald Van Baren Signed-off-by: Kim Phillips --- cpu/mpc83xx/cpu.c | 74 ++++++++++++++++++++++++++++++++++--------------------- 1 file changed, 46 insertions(+), 28 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 40e8d0c987b..30ecb854537 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -339,7 +339,7 @@ static int fdt_set_eth0(void *fdt, int nodeoffset, const char *name, bd_t *bd) if (fdt_get_property(fdt, nodeoffset, name, 0)) { return fdt_setprop(fdt, nodeoffset, name, bd->bi_enetaddr, 6); } - return -FDT_ERR_NOTFOUND; + return 0; } #ifdef CONFIG_HAS_ETH1 /* second onboard ethernet port */ @@ -351,7 +351,7 @@ static int fdt_set_eth1(void *fdt, int nodeoffset, const char *name, bd_t *bd) if (fdt_get_property(fdt, nodeoffset, name, 0)) { return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet1addr, 6); } - return -FDT_ERR_NOTFOUND; + return 0; } #endif #ifdef CONFIG_HAS_ETH2 @@ -364,7 +364,7 @@ static int fdt_set_eth2(void *fdt, int nodeoffset, const char *name, bd_t *bd) if (fdt_get_property(fdt, nodeoffset, name, 0)) { return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet2addr, 6); } - return -FDT_ERR_NOTFOUND; + return 0; } #endif #ifdef CONFIG_HAS_ETH3 @@ -377,7 +377,7 @@ static int fdt_set_eth3(void *fdt, int nodeoffset, const char *name, bd_t *bd) if (fdt_get_property(fdt, nodeoffset, name, 0)) { return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet3addr, 6); } - return -FDT_ERR_NOTFOUND; + return 0; } #endif @@ -391,10 +391,19 @@ static int fdt_set_busfreq(void *fdt, int nodeoffset, const char *name, bd_t *bd return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); } +static int fdt_set_tbfreq(void *fdt, int nodeoffset, const char *name, bd_t *bd) +{ + u32 tmp; + /* + * Create or update the property. + */ + tmp = cpu_to_be32(OF_TBCLK); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + + /* - * Fixups to the fdt. If "create" is TRUE, the node is created - * unconditionally. If "create" is FALSE, the node is updated - * only if it already exists. + * Fixups to the fdt. */ static const struct { char *node; @@ -402,83 +411,87 @@ static const struct { int (*set_fn)(void *fdt, int nodeoffset, const char *name, bd_t *bd); } fixup_props[] = { { "/cpus/" OF_CPU, - "bus-frequency", - fdt_set_busfreq + "timebase-frequency", + fdt_set_tbfreq }, - { "/cpus/" OF_SOC, + { "/cpus/" OF_CPU, "bus-frequency", fdt_set_busfreq }, - { "/" OF_SOC "/serial@4500/", + { "/cpus/" OF_CPU, + "clock-frequency", + fdt_set_busfreq + }, + { "/" OF_SOC "/serial@4500", "clock-frequency", fdt_set_busfreq }, - { "/" OF_SOC "/serial@4600/", + { "/" OF_SOC "/serial@4600", "clock-frequency", fdt_set_busfreq }, #ifdef CONFIG_TSEC1 - { "/" OF_SOC "/ethernet@24000, + { "/" OF_SOC "/ethernet@24000", "mac-address", fdt_set_eth0 }, - { "/" OF_SOC "/ethernet@24000, + { "/" OF_SOC "/ethernet@24000", "local-mac-address", fdt_set_eth0 }, #endif #ifdef CONFIG_TSEC2 - { "/" OF_SOC "/ethernet@25000, + { "/" OF_SOC "/ethernet@25000", "mac-address", fdt_set_eth1 }, - { "/" OF_SOC "/ethernet@25000, + { "/" OF_SOC "/ethernet@25000", "local-mac-address", fdt_set_eth1 }, #endif #ifdef CONFIG_UEC_ETH1 #if CFG_UEC1_UCC_NUM == 0 /* UCC1 */ - { "/" OF_QE "/ucc@2000/mac-address", + { "/" OF_QE "/ucc@2000", "mac-address", fdt_set_eth0 }, - { "/" OF_QE "/ucc@2000/mac-address", + { "/" OF_QE "/ucc@2000", "local-mac-address", fdt_set_eth0 }, #elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */ - { "/" OF_QE "/ucc@2200/mac-address", + { "/" OF_QE "/ucc@2200", "mac-address", fdt_set_eth0 }, - { "/" OF_QE "/ucc@2200/mac-address", + { "/" OF_QE "/ucc@2200", "local-mac-address", fdt_set_eth0 }, #endif -#endif +#endif /* CONFIG_UEC_ETH1 */ #ifdef CONFIG_UEC_ETH2 #if CFG_UEC2_UCC_NUM == 1 /* UCC2 */ - { "/" OF_QE "/ucc@3000/mac-address", + { "/" OF_QE "/ucc@3000", "mac-address", fdt_set_eth1 }, - { "/" OF_QE "/ucc@3000/mac-address", + { "/" OF_QE "/ucc@3000", "local-mac-address", fdt_set_eth1 }, #elif CFG_UEC1_UCC_NUM == 3 /* UCC4 */ - { "/" OF_QE "/ucc@3200/mac-address", + { "/" OF_QE "/ucc@3200", "mac-address", fdt_set_eth1 }, - { "/" OF_QE "/ucc@3200/mac-address", + { "/" OF_QE "/ucc@3200", "local-mac-address", fdt_set_eth1 }, #endif -#endif +#endif /* CONFIG_UEC_ETH2 */ }; void @@ -491,12 +504,17 @@ ft_cpu_setup(void *blob, bd_t *bd) for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) { nodeoffset = fdt_find_node_by_path(fdt, fixup_props[j].node); if (nodeoffset >= 0) { - err = (*fixup_props[j].set_fn)(blob, nodeoffset, fixup_props[j].prop, bd); + err = fixup_props[j].set_fn(blob, nodeoffset, + fixup_props[j].prop, bd); if (err < 0) - printf("set_fn/libfdt: %s %s returned %s\n", + debug("Problem setting %s = %s: %s\n", fixup_props[j].node, fixup_props[j].prop, fdt_strerror(err)); + } else { + debug("Couldn't find %s: %s\n", + fixup_props[j].node, + fdt_strerror(nodeoffset)); } } } -- cgit v1.3.1 From f57ac7a7b37109245b69db80839ebee26179966a Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 25 Jul 2007 19:25:22 -0500 Subject: mpc83xx: fix 8360 and cpu functions to update fdt being passed ..and not the global fdt. Rename local fdt vars to blob so as not to be confused with the global var with the same three-letter name. Signed-off-by: Kim Phillips --- board/mpc8360emds/mpc8360emds.c | 4 ++-- board/mpc8360emds/pci.c | 4 ++-- cpu/mpc83xx/cpu.c | 36 ++++++++++++++++++------------------ 3 files changed, 22 insertions(+), 22 deletions(-) (limited to 'cpu') diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index f63d3ae6514..b109317be44 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -682,11 +682,11 @@ ft_board_setup(void *blob, bd_t *bd) int nodeoffset; int tmp[2]; - nodeoffset = fdt_find_node_by_path(fdt, "/memory"); + nodeoffset = fdt_find_node_by_path(blob, "/memory"); if (nodeoffset >= 0) { tmp[0] = cpu_to_be32(bd->bi_memstart); tmp[1] = cpu_to_be32(bd->bi_memsize); - fdt_setprop(fdt, nodeoffset, "reg", tmp, sizeof(tmp)); + fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp)); } #else u32 *p; diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c index 8d34dbe0468..8f904710ca8 100644 --- a/board/mpc8360emds/pci.c +++ b/board/mpc8360emds/pci.c @@ -310,11 +310,11 @@ ft_pci_setup(void *blob, bd_t *bd) int err; int tmp[2]; - nodeoffset = fdt_find_node_by_path(fdt, "/" OF_SOC "/pci@8500"); + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); if (nodeoffset >= 0) { tmp[0] = cpu_to_be32(hose[0].first_busno); tmp[1] = cpu_to_be32(hose[0].last_busno); - err = fdt_setprop(fdt, nodeoffset, "bus-range", tmp, sizeof(tmp)); + err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp)); } } #elif defined(CONFIG_OF_FLAT_TREE) diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 30ecb854537..adf80830103 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -331,74 +331,74 @@ void watchdog_reset (void) /* * "Setter" functions used to add/modify FDT entries. */ -static int fdt_set_eth0(void *fdt, int nodeoffset, const char *name, bd_t *bd) +static int fdt_set_eth0(void *blob, int nodeoffset, const char *name, bd_t *bd) { /* * Fix it up if it exists, don't create it if it doesn't exist. */ - if (fdt_get_property(fdt, nodeoffset, name, 0)) { - return fdt_setprop(fdt, nodeoffset, name, bd->bi_enetaddr, 6); + if (fdt_get_property(blob, nodeoffset, name, 0)) { + return fdt_setprop(blob, nodeoffset, name, bd->bi_enetaddr, 6); } return 0; } #ifdef CONFIG_HAS_ETH1 /* second onboard ethernet port */ -static int fdt_set_eth1(void *fdt, int nodeoffset, const char *name, bd_t *bd) +static int fdt_set_eth1(void *blob, int nodeoffset, const char *name, bd_t *bd) { /* * Fix it up if it exists, don't create it if it doesn't exist. */ - if (fdt_get_property(fdt, nodeoffset, name, 0)) { - return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet1addr, 6); + if (fdt_get_property(blob, nodeoffset, name, 0)) { + return fdt_setprop(blob, nodeoffset, name, bd->bi_enet1addr, 6); } return 0; } #endif #ifdef CONFIG_HAS_ETH2 /* third onboard ethernet port */ -static int fdt_set_eth2(void *fdt, int nodeoffset, const char *name, bd_t *bd) +static int fdt_set_eth2(void *blob, int nodeoffset, const char *name, bd_t *bd) { /* * Fix it up if it exists, don't create it if it doesn't exist. */ - if (fdt_get_property(fdt, nodeoffset, name, 0)) { - return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet2addr, 6); + if (fdt_get_property(blob, nodeoffset, name, 0)) { + return fdt_setprop(blob, nodeoffset, name, bd->bi_enet2addr, 6); } return 0; } #endif #ifdef CONFIG_HAS_ETH3 /* fourth onboard ethernet port */ -static int fdt_set_eth3(void *fdt, int nodeoffset, const char *name, bd_t *bd) +static int fdt_set_eth3(void *blob, int nodeoffset, const char *name, bd_t *bd) { /* * Fix it up if it exists, don't create it if it doesn't exist. */ - if (fdt_get_property(fdt, nodeoffset, name, 0)) { - return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet3addr, 6); + if (fdt_get_property(blob, nodeoffset, name, 0)) { + return fdt_setprop(blob, nodeoffset, name, bd->bi_enet3addr, 6); } return 0; } #endif -static int fdt_set_busfreq(void *fdt, int nodeoffset, const char *name, bd_t *bd) +static int fdt_set_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd) { u32 tmp; /* * Create or update the property. */ tmp = cpu_to_be32(bd->bi_busfreq); - return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); + return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp)); } -static int fdt_set_tbfreq(void *fdt, int nodeoffset, const char *name, bd_t *bd) +static int fdt_set_tbfreq(void *blob, int nodeoffset, const char *name, bd_t *bd) { u32 tmp; /* * Create or update the property. */ tmp = cpu_to_be32(OF_TBCLK); - return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); + return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp)); } @@ -408,7 +408,7 @@ static int fdt_set_tbfreq(void *fdt, int nodeoffset, const char *name, bd_t *bd) static const struct { char *node; char *prop; - int (*set_fn)(void *fdt, int nodeoffset, const char *name, bd_t *bd); + int (*set_fn)(void *blob, int nodeoffset, const char *name, bd_t *bd); } fixup_props[] = { { "/cpus/" OF_CPU, "timebase-frequency", @@ -502,7 +502,7 @@ ft_cpu_setup(void *blob, bd_t *bd) int j; for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) { - nodeoffset = fdt_find_node_by_path(fdt, fixup_props[j].node); + nodeoffset = fdt_find_node_by_path(blob, fixup_props[j].node); if (nodeoffset >= 0) { err = fixup_props[j].set_fn(blob, nodeoffset, fixup_props[j].prop, bd); -- cgit v1.3.1 From 343d91009d55fc5b3ff8cc940597af6c6aa1d359 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 25 Jul 2007 19:25:28 -0500 Subject: mpc83xx: fixup generic pci for libfdt add libfdt support to the generic 83xx pci code Signed-off-by: Kim Phillips --- cpu/mpc83xx/pci.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c index 785d6129daf..22982188708 100644 --- a/cpu/mpc83xx/pci.c +++ b/cpu/mpc83xx/pci.c @@ -25,7 +25,14 @@ #include #include + +#if defined(CONFIG_OF_LIBFDT) +#include +#include +#elif defined(CONFIG_OF_FLAT_TREE) #include +#endif + #include #ifdef CONFIG_83XX_GENERIC_PCI @@ -163,7 +170,34 @@ void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot) pci_init_bus(i, reg[i]); } -#ifdef CONFIG_OF_FLAT_TREE +#if defined(CONFIG_OF_LIBFDT) +void ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int err; + int tmp[2]; + + if (pci_num_buses < 1) + return; + + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp)); + } + + if (pci_num_buses < 2) + return; + + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8600"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp)); + } +} +#elif CONFIG_OF_FLAT_TREE void ft_pci_setup(void *blob, bd_t *bd) { u32 *p; -- cgit v1.3.1 From 036575c544cf1b69654d8fb334bda69c6ff3da36 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Sat, 4 Aug 2007 13:37:39 +0800 Subject: mpc83xx: Correct the burst length for DDR2 with 32 bits The burst length should be 4 for DDR2 with 32 bits bus Signed-off-by: Dave Liu --- cpu/mpc83xx/spd_sdram.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 647813f68d9..2c17cee31a5 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -574,7 +574,10 @@ long int spd_sdram() /* Check DIMM data bus width */ if (spd.dataw_lsb == 0x20) { - burstlen = 0x03; /* 32 bit data bus, burst len is 8 */ + if (spd.mem_type == SPD_MEMTYPE_DDR) + burstlen = 0x03; /* 32 bit data bus, burst len is 8 */ + if (spd.mem_type == SPD_MEMTYPE_DDR2) + burstlen = 0x02; /* 32 bit data bus, burst len is 4 */ printf("\n DDR DIMM: data bus width is 32 bit"); } else { burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */ @@ -730,8 +733,12 @@ long int spd_sdram() sdram_cfg |= 0x10000000; /* The DIMM is 32bit width */ - if (spd.dataw_lsb == 0x20) - sdram_cfg |= 0x000C0000; + if (spd.dataw_lsb == 0x20) { + if (spd.mem_type == SPD_MEMTYPE_DDR) + sdram_cfg |= 0x000C0000; + if (spd.mem_type == SPD_MEMTYPE_DDR2) + sdram_cfg |= 0x00080000; + } ddrc_ecc_enable = 0; -- cgit v1.3.1 From daab8c67d2defef73dc26ab07f0c3afd1b05d019 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Wed, 1 Aug 2007 15:00:15 +0800 Subject: mpc83xx: Consolidate the ECC support of 83xx Remove the duplicated source code of ecc command on the .c, for reused, move these code to cpu/mpc83xx directory. Signed-off-by: Dave Liu Signed-off-by: Kim Phillips --- board/mpc8349emds/mpc8349emds.c | 327 --------------------------------- board/mpc8360emds/mpc8360emds.c | 378 -------------------------------------- cpu/mpc83xx/Makefile | 2 +- cpu/mpc83xx/ecc.c | 390 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 391 insertions(+), 706 deletions(-) create mode 100644 cpu/mpc83xx/ecc.c (limited to 'cpu') diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c index 071591ed835..521d1bbd4ed 100644 --- a/board/mpc8349emds/mpc8349emds.c +++ b/board/mpc8349emds/mpc8349emds.c @@ -29,7 +29,6 @@ #include #include #include -#include #if defined(CONFIG_SPD_EEPROM) #include #endif @@ -258,332 +257,6 @@ void sdram_init(void) } #endif -#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) -/* - * ECC user commands - */ -void ecc_print_status(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ddr83xx_t *ddr = &immap->ddr; - - printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); - - /* Interrupts */ - printf("Memory Error Interrupt Enable:\n"); - printf(" Multiple-Bit Error Interrupt Enable: %d\n", - (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0); - printf(" Single-Bit Error Interrupt Enable: %d\n", - (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0); - printf(" Memory Select Error Interrupt Enable: %d\n\n", - (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0); - - /* Error disable */ - printf("Memory Error Disable:\n"); - printf(" Multiple-Bit Error Disable: %d\n", - (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0); - printf(" Sinle-Bit Error Disable: %d\n", - (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0); - printf(" Memory Select Error Disable: %d\n\n", - (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0); - - /* Error injection */ - printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n", - ddr->data_err_inject_hi, ddr->data_err_inject_lo); - - printf("Memory Data Path Error Injection Mask ECC:\n"); - printf(" ECC Mirror Byte: %d\n", - (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0); - printf(" ECC Injection Enable: %d\n", - (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0); - printf(" ECC Error Injection Mask: 0x%02x\n\n", - ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM); - - /* SBE counter/threshold */ - printf("Memory Single-Bit Error Management (0..255):\n"); - printf(" Single-Bit Error Threshold: %d\n", - (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT); - printf(" Single-Bit Error Counter: %d\n\n", - (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT); - - /* Error detect */ - printf("Memory Error Detect:\n"); - printf(" Multiple Memory Errors: %d\n", - (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0); - printf(" Multiple-Bit Error: %d\n", - (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0); - printf(" Single-Bit Error: %d\n", - (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0); - printf(" Memory Select Error: %d\n\n", - (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0); - - /* Capture data */ - printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address); - printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n", - ddr->capture_data_hi, ddr->capture_data_lo); - printf("Memory Data Path Read Capture ECC: 0x%02x\n\n", - ddr->capture_ecc & CAPTURE_ECC_ECE); - - printf("Memory Error Attributes Capture:\n"); - printf(" Data Beat Number: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT); - printf(" Transaction Size: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT); - printf(" Transaction Source: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT); - printf(" Transaction Type: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT); - printf(" Error Information Valid: %d\n\n", - ddr->capture_attributes & ECC_CAPT_ATTR_VLD); -} - -int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ddr83xx_t *ddr = &immap->ddr; - volatile u32 val; - u64 *addr, count, val64; - register u64 *i; - - if (argc > 4) { - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - if (argc == 2) { - if (strcmp(argv[1], "status") == 0) { - ecc_print_status(); - return 0; - } else if (strcmp(argv[1], "captureclear") == 0) { - ddr->capture_address = 0; - ddr->capture_data_hi = 0; - ddr->capture_data_lo = 0; - ddr->capture_ecc = 0; - ddr->capture_attributes = 0; - return 0; - } - } - - if (argc == 3) { - if (strcmp(argv[1], "sbecnt") == 0) { - val = simple_strtoul(argv[2], NULL, 10); - if (val > 255) { - printf("Incorrect Counter value, should be 0..255\n"); - return 1; - } - - val = (val << ECC_ERROR_MAN_SBEC_SHIFT); - val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET); - - ddr->err_sbe = val; - return 0; - } else if (strcmp(argv[1], "sbethr") == 0) { - val = simple_strtoul(argv[2], NULL, 10); - if (val > 255) { - printf("Incorrect Counter value, should be 0..255\n"); - return 1; - } - - val = (val << ECC_ERROR_MAN_SBET_SHIFT); - val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC); - - ddr->err_sbe = val; - return 0; - } else if (strcmp(argv[1], "errdisable") == 0) { - val = ddr->err_disable; - - if (strcmp(argv[2], "+sbe") == 0) { - val |= ECC_ERROR_DISABLE_SBED; - } else if (strcmp(argv[2], "+mbe") == 0) { - val |= ECC_ERROR_DISABLE_MBED; - } else if (strcmp(argv[2], "+mse") == 0) { - val |= ECC_ERROR_DISABLE_MSED; - } else if (strcmp(argv[2], "+all") == 0) { - val |= (ECC_ERROR_DISABLE_SBED | - ECC_ERROR_DISABLE_MBED | - ECC_ERROR_DISABLE_MSED); - } else if (strcmp(argv[2], "-sbe") == 0) { - val &= ~ECC_ERROR_DISABLE_SBED; - } else if (strcmp(argv[2], "-mbe") == 0) { - val &= ~ECC_ERROR_DISABLE_MBED; - } else if (strcmp(argv[2], "-mse") == 0) { - val &= ~ECC_ERROR_DISABLE_MSED; - } else if (strcmp(argv[2], "-all") == 0) { - val &= ~(ECC_ERROR_DISABLE_SBED | - ECC_ERROR_DISABLE_MBED | - ECC_ERROR_DISABLE_MSED); - } else { - printf("Incorrect err_disable field\n"); - return 1; - } - - ddr->err_disable = val; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - return 0; - } else if (strcmp(argv[1], "errdetectclr") == 0) { - val = ddr->err_detect; - - if (strcmp(argv[2], "mme") == 0) { - val |= ECC_ERROR_DETECT_MME; - } else if (strcmp(argv[2], "sbe") == 0) { - val |= ECC_ERROR_DETECT_SBE; - } else if (strcmp(argv[2], "mbe") == 0) { - val |= ECC_ERROR_DETECT_MBE; - } else if (strcmp(argv[2], "mse") == 0) { - val |= ECC_ERROR_DETECT_MSE; - } else if (strcmp(argv[2], "all") == 0) { - val |= (ECC_ERROR_DETECT_MME | - ECC_ERROR_DETECT_MBE | - ECC_ERROR_DETECT_SBE | - ECC_ERROR_DETECT_MSE); - } else { - printf("Incorrect err_detect field\n"); - return 1; - } - - ddr->err_detect = val; - return 0; - } else if (strcmp(argv[1], "injectdatahi") == 0) { - val = simple_strtoul(argv[2], NULL, 16); - - ddr->data_err_inject_hi = val; - return 0; - } else if (strcmp(argv[1], "injectdatalo") == 0) { - val = simple_strtoul(argv[2], NULL, 16); - - ddr->data_err_inject_lo = val; - return 0; - } else if (strcmp(argv[1], "injectecc") == 0) { - val = simple_strtoul(argv[2], NULL, 16); - if (val > 0xff) { - printf("Incorrect ECC inject mask, should be 0x00..0xff\n"); - return 1; - } - val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM); - - ddr->ecc_err_inject = val; - return 0; - } else if (strcmp(argv[1], "inject") == 0) { - val = ddr->ecc_err_inject; - - if (strcmp(argv[2], "en") == 0) - val |= ECC_ERR_INJECT_EIEN; - else if (strcmp(argv[2], "dis") == 0) - val &= ~ECC_ERR_INJECT_EIEN; - else - printf("Incorrect command\n"); - - ddr->ecc_err_inject = val; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - return 0; - } else if (strcmp(argv[1], "mirror") == 0) { - val = ddr->ecc_err_inject; - - if (strcmp(argv[2], "en") == 0) - val |= ECC_ERR_INJECT_EMB; - else if (strcmp(argv[2], "dis") == 0) - val &= ~ECC_ERR_INJECT_EMB; - else - printf("Incorrect command\n"); - - ddr->ecc_err_inject = val; - return 0; - } - } - - if (argc == 4) { - if (strcmp(argv[1], "test") == 0) { - addr = (u64 *)simple_strtoul(argv[2], NULL, 16); - count = simple_strtoul(argv[3], NULL, 16); - - if ((u32)addr % 8) { - printf("Address not alligned on double word boundary\n"); - return 1; - } - - disable_interrupts(); - icache_disable(); - - for (i = addr; i < addr + count; i++) { - /* enable injects */ - ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - - /* write memory location injecting errors */ - *i = 0x1122334455667788ULL; - __asm__ __volatile__ ("sync"); - - /* disable injects */ - ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - - /* read data, this generates ECC error */ - val64 = *i; - __asm__ __volatile__ ("sync"); - - /* disable errors for ECC */ - ddr->err_disable |= ~ECC_ERROR_ENABLE; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - - /* re-initialize memory, write the location again - * NOT injecting errors this time */ - *i = 0xcafecafecafecafeULL; - __asm__ __volatile__ ("sync"); - - /* enable errors for ECC */ - ddr->err_disable &= ECC_ERROR_ENABLE; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - } - - icache_enable(); - enable_interrupts(); - - return 0; - } - } - - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; -} - -U_BOOT_CMD( - ecc, 4, 0, do_ecc, - "ecc - support for DDR ECC features\n", - "status - print out status info\n" - "ecc captureclear - clear capture regs data\n" - "ecc sbecnt - set Single-Bit Error counter\n" - "ecc sbethr - set Single-Bit Threshold\n" - "ecc errdisable - clear/set disable Memory Error Disable, flag:\n" - " [-|+]sbe - Single-Bit Error\n" - " [-|+]mbe - Multiple-Bit Error\n" - " [-|+]mse - Memory Select Error\n" - " [-|+]all - all errors\n" - "ecc errdetectclr - clear Memory Error Detect, flag:\n" - " mme - Multiple Memory Errors\n" - " sbe - Single-Bit Error\n" - " mbe - Multiple-Bit Error\n" - " mse - Memory Select Error\n" - " all - all errors\n" - "ecc injectdatahi - set Memory Data Path Error Injection Mask High\n" - "ecc injectdatalo - set Memory Data Path Error Injection Mask Low\n" - "ecc injectecc - set ECC Error Injection Mask\n" - "ecc inject - enable/disable error injection\n" - "ecc mirror - enable/disable mirror byte\n" - "ecc test - test mem region:\n" - " - enables injects\n" - " - writes pattern injecting errors\n" - " - disables injects\n" - " - reads pattern back, generates error\n" - " - re-inits memory" -); -#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */ - #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index b109317be44..3fa093d1d55 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -1,8 +1,6 @@ /* * Copyright (C) 2006 Freescale Semiconductor, Inc. - * * Dave Liu - * based on board/mpc8349emds/mpc8349emds.c * * See file CREDITS for list of people who contributed to this * project. @@ -19,7 +17,6 @@ #include #include #include -#include #if defined(CONFIG_PCI) #include #endif @@ -288,381 +285,6 @@ void sdram_init(void) } #endif -#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) -/* - * ECC user commands - */ -void ecc_print_status(void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile ddr83xx_t *ddr = &immap->ddr; - - printf("\nECC mode: %s\n\n", - (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); - - /* Interrupts */ - printf("Memory Error Interrupt Enable:\n"); - printf(" Multiple-Bit Error Interrupt Enable: %d\n", - (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0); - printf(" Single-Bit Error Interrupt Enable: %d\n", - (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0); - printf(" Memory Select Error Interrupt Enable: %d\n\n", - (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0); - - /* Error disable */ - printf("Memory Error Disable:\n"); - printf(" Multiple-Bit Error Disable: %d\n", - (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0); - printf(" Sinle-Bit Error Disable: %d\n", - (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0); - printf(" Memory Select Error Disable: %d\n\n", - (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0); - - /* Error injection */ - printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n", - ddr->data_err_inject_hi, ddr->data_err_inject_lo); - - printf("Memory Data Path Error Injection Mask ECC:\n"); - printf(" ECC Mirror Byte: %d\n", - (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0); - printf(" ECC Injection Enable: %d\n", - (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0); - printf(" ECC Error Injection Mask: 0x%02x\n\n", - ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM); - - /* SBE counter/threshold */ - printf("Memory Single-Bit Error Management (0..255):\n"); - printf(" Single-Bit Error Threshold: %d\n", - (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT); - printf(" Single-Bit Error Counter: %d\n\n", - (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT); - - /* Error detect */ - printf("Memory Error Detect:\n"); - printf(" Multiple Memory Errors: %d\n", - (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0); - printf(" Multiple-Bit Error: %d\n", - (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0); - printf(" Single-Bit Error: %d\n", - (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0); - printf(" Memory Select Error: %d\n\n", - (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0); - - /* Capture data */ - printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address); - printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n", - ddr->capture_data_hi, ddr->capture_data_lo); - printf("Memory Data Path Read Capture ECC: 0x%02x\n\n", - ddr->capture_ecc & CAPTURE_ECC_ECE); - - printf("Memory Error Attributes Capture:\n"); - printf(" Data Beat Number: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> - ECC_CAPT_ATTR_BNUM_SHIFT); - printf(" Transaction Size: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> - ECC_CAPT_ATTR_TSIZ_SHIFT); - printf(" Transaction Source: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> - ECC_CAPT_ATTR_TSRC_SHIFT); - printf(" Transaction Type: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> - ECC_CAPT_ATTR_TTYP_SHIFT); - printf(" Error Information Valid: %d\n\n", - ddr->capture_attributes & ECC_CAPT_ATTR_VLD); -} - -int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile ddr83xx_t *ddr = &immap->ddr; - volatile u32 val; - u64 *addr; - u32 count; - register u64 *i; - u32 ret[2]; - u32 pattern[2]; - u32 writeback[2]; - - /* The pattern is written into memory to generate error */ - pattern[0] = 0xfedcba98UL; - pattern[1] = 0x76543210UL; - - /* After injecting error, re-initialize the memory with the value */ - writeback[0] = 0x01234567UL; - writeback[1] = 0x89abcdefUL; - - if (argc > 4) { - printf("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - if (argc == 2) { - if (strcmp(argv[1], "status") == 0) { - ecc_print_status(); - return 0; - } else if (strcmp(argv[1], "captureclear") == 0) { - ddr->capture_address = 0; - ddr->capture_data_hi = 0; - ddr->capture_data_lo = 0; - ddr->capture_ecc = 0; - ddr->capture_attributes = 0; - return 0; - } - } - if (argc == 3) { - if (strcmp(argv[1], "sbecnt") == 0) { - val = simple_strtoul(argv[2], NULL, 10); - if (val > 255) { - printf("Incorrect Counter value, " - "should be 0..255\n"); - return 1; - } - - val = (val << ECC_ERROR_MAN_SBEC_SHIFT); - val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET); - - ddr->err_sbe = val; - return 0; - } else if (strcmp(argv[1], "sbethr") == 0) { - val = simple_strtoul(argv[2], NULL, 10); - if (val > 255) { - printf("Incorrect Counter value, " - "should be 0..255\n"); - return 1; - } - - val = (val << ECC_ERROR_MAN_SBET_SHIFT); - val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC); - - ddr->err_sbe = val; - return 0; - } else if (strcmp(argv[1], "errdisable") == 0) { - val = ddr->err_disable; - - if (strcmp(argv[2], "+sbe") == 0) { - val |= ECC_ERROR_DISABLE_SBED; - } else if (strcmp(argv[2], "+mbe") == 0) { - val |= ECC_ERROR_DISABLE_MBED; - } else if (strcmp(argv[2], "+mse") == 0) { - val |= ECC_ERROR_DISABLE_MSED; - } else if (strcmp(argv[2], "+all") == 0) { - val |= (ECC_ERROR_DISABLE_SBED | - ECC_ERROR_DISABLE_MBED | - ECC_ERROR_DISABLE_MSED); - } else if (strcmp(argv[2], "-sbe") == 0) { - val &= ~ECC_ERROR_DISABLE_SBED; - } else if (strcmp(argv[2], "-mbe") == 0) { - val &= ~ECC_ERROR_DISABLE_MBED; - } else if (strcmp(argv[2], "-mse") == 0) { - val &= ~ECC_ERROR_DISABLE_MSED; - } else if (strcmp(argv[2], "-all") == 0) { - val &= ~(ECC_ERROR_DISABLE_SBED | - ECC_ERROR_DISABLE_MBED | - ECC_ERROR_DISABLE_MSED); - } else { - printf("Incorrect err_disable field\n"); - return 1; - } - - ddr->err_disable = val; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); - return 0; - } else if (strcmp(argv[1], "errdetectclr") == 0) { - val = ddr->err_detect; - - if (strcmp(argv[2], "mme") == 0) { - val |= ECC_ERROR_DETECT_MME; - } else if (strcmp(argv[2], "sbe") == 0) { - val |= ECC_ERROR_DETECT_SBE; - } else if (strcmp(argv[2], "mbe") == 0) { - val |= ECC_ERROR_DETECT_MBE; - } else if (strcmp(argv[2], "mse") == 0) { - val |= ECC_ERROR_DETECT_MSE; - } else if (strcmp(argv[2], "all") == 0) { - val |= (ECC_ERROR_DETECT_MME | - ECC_ERROR_DETECT_MBE | - ECC_ERROR_DETECT_SBE | - ECC_ERROR_DETECT_MSE); - } else { - printf("Incorrect err_detect field\n"); - return 1; - } - - ddr->err_detect = val; - return 0; - } else if (strcmp(argv[1], "injectdatahi") == 0) { - val = simple_strtoul(argv[2], NULL, 16); - - ddr->data_err_inject_hi = val; - return 0; - } else if (strcmp(argv[1], "injectdatalo") == 0) { - val = simple_strtoul(argv[2], NULL, 16); - - ddr->data_err_inject_lo = val; - return 0; - } else if (strcmp(argv[1], "injectecc") == 0) { - val = simple_strtoul(argv[2], NULL, 16); - if (val > 0xff) { - printf("Incorrect ECC inject mask, " - "should be 0x00..0xff\n"); - return 1; - } - val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM); - - ddr->ecc_err_inject = val; - return 0; - } else if (strcmp(argv[1], "inject") == 0) { - val = ddr->ecc_err_inject; - - if (strcmp(argv[2], "en") == 0) - val |= ECC_ERR_INJECT_EIEN; - else if (strcmp(argv[2], "dis") == 0) - val &= ~ECC_ERR_INJECT_EIEN; - else - printf("Incorrect command\n"); - - ddr->ecc_err_inject = val; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); - return 0; - } else if (strcmp(argv[1], "mirror") == 0) { - val = ddr->ecc_err_inject; - - if (strcmp(argv[2], "en") == 0) - val |= ECC_ERR_INJECT_EMB; - else if (strcmp(argv[2], "dis") == 0) - val &= ~ECC_ERR_INJECT_EMB; - else - printf("Incorrect command\n"); - - ddr->ecc_err_inject = val; - return 0; - } - } - if (argc == 4) { - if (strcmp(argv[1], "testdw") == 0) { - addr = (u64 *) simple_strtoul(argv[2], NULL, 16); - count = simple_strtoul(argv[3], NULL, 16); - - if ((u32) addr % 8) { - printf("Address not alligned on " - "double word boundary\n"); - return 1; - } - disable_interrupts(); - - for (i = addr; i < addr + count; i++) { - - /* enable injects */ - ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); - - /* write memory location injecting errors */ - ppcDWstore((u32 *) i, pattern); - __asm__ __volatile__("sync"); - - /* disable injects */ - ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); - - /* read data, this generates ECC error */ - ppcDWload((u32 *) i, ret); - __asm__ __volatile__("sync"); - - /* re-initialize memory, double word write the location again, - * generates new ECC code this time */ - ppcDWstore((u32 *) i, writeback); - __asm__ __volatile__("sync"); - } - enable_interrupts(); - return 0; - } - if (strcmp(argv[1], "testword") == 0) { - addr = (u64 *) simple_strtoul(argv[2], NULL, 16); - count = simple_strtoul(argv[3], NULL, 16); - - if ((u32) addr % 8) { - printf("Address not alligned on " - "double word boundary\n"); - return 1; - } - disable_interrupts(); - - for (i = addr; i < addr + count; i++) { - - /* enable injects */ - ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); - - /* write memory location injecting errors */ - *(u32 *) i = 0xfedcba98UL; - __asm__ __volatile__("sync"); - - /* sub double word write, - * bus will read-modify-write, - * generates ECC error */ - *((u32 *) i + 1) = 0x76543210UL; - __asm__ __volatile__("sync"); - - /* disable injects */ - ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); - - /* re-initialize memory, - * double word write the location again, - * generates new ECC code this time */ - ppcDWstore((u32 *) i, writeback); - __asm__ __volatile__("sync"); - } - enable_interrupts(); - return 0; - } - } - printf("Usage:\n%s\n", cmdtp->usage); - return 1; -} - -U_BOOT_CMD(ecc, 4, 0, do_ecc, - "ecc - support for DDR ECC features\n", - "status - print out status info\n" - "ecc captureclear - clear capture regs data\n" - "ecc sbecnt - set Single-Bit Error counter\n" - "ecc sbethr - set Single-Bit Threshold\n" - "ecc errdisable - clear/set disable Memory Error Disable, flag:\n" - " [-|+]sbe - Single-Bit Error\n" - " [-|+]mbe - Multiple-Bit Error\n" - " [-|+]mse - Memory Select Error\n" - " [-|+]all - all errors\n" - "ecc errdetectclr - clear Memory Error Detect, flag:\n" - " mme - Multiple Memory Errors\n" - " sbe - Single-Bit Error\n" - " mbe - Multiple-Bit Error\n" - " mse - Memory Select Error\n" - " all - all errors\n" - "ecc injectdatahi - set Memory Data Path Error Injection Mask High\n" - "ecc injectdatalo - set Memory Data Path Error Injection Mask Low\n" - "ecc injectecc - set ECC Error Injection Mask\n" - "ecc inject - enable/disable error injection\n" - "ecc mirror - enable/disable mirror byte\n" - "ecc testdw - test mem region with double word access:\n" - " - enables injects\n" - " - writes pattern injecting errors with double word access\n" - " - disables injects\n" - " - reads pattern back with double word access, generates error\n" - " - re-inits memory\n" - "ecc testword - test mem region with word access:\n" - " - enables injects\n" - " - writes pattern injecting errors with word access\n" - " - writes pattern with word access, generates error\n" - " - disables injects\n" " - re-inits memory"); -#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */ - #if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \ && defined(CONFIG_OF_BOARD_SETUP) diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile index bb96f774fe4..23299700510 100644 --- a/cpu/mpc83xx/Makefile +++ b/cpu/mpc83xx/Makefile @@ -29,7 +29,7 @@ LIB = $(obj)lib$(CPU).a START = start.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - spd_sdram.o qe_io.o pci.o + spd_sdram.o ecc.o qe_io.o pci.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc83xx/ecc.c b/cpu/mpc83xx/ecc.c new file mode 100644 index 00000000000..6f13094243a --- /dev/null +++ b/cpu/mpc83xx/ecc.c @@ -0,0 +1,390 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * Dave Liu + * based on the contribution of Marian Balakowicz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include +#include +#include + +#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) +void ecc_print_status(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ddr83xx_t *ddr = &immap->ddr; + + printf("\nECC mode: %s\n\n", + (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); + + /* Interrupts */ + printf("Memory Error Interrupt Enable:\n"); + printf(" Multiple-Bit Error Interrupt Enable: %d\n", + (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0); + printf(" Single-Bit Error Interrupt Enable: %d\n", + (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0); + printf(" Memory Select Error Interrupt Enable: %d\n\n", + (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0); + + /* Error disable */ + printf("Memory Error Disable:\n"); + printf(" Multiple-Bit Error Disable: %d\n", + (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0); + printf(" Sinle-Bit Error Disable: %d\n", + (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0); + printf(" Memory Select Error Disable: %d\n\n", + (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0); + + /* Error injection */ + printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n", + ddr->data_err_inject_hi, ddr->data_err_inject_lo); + + printf("Memory Data Path Error Injection Mask ECC:\n"); + printf(" ECC Mirror Byte: %d\n", + (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0); + printf(" ECC Injection Enable: %d\n", + (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0); + printf(" ECC Error Injection Mask: 0x%02x\n\n", + ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM); + + /* SBE counter/threshold */ + printf("Memory Single-Bit Error Management (0..255):\n"); + printf(" Single-Bit Error Threshold: %d\n", + (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT); + printf(" Single-Bit Error Counter: %d\n\n", + (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT); + + /* Error detect */ + printf("Memory Error Detect:\n"); + printf(" Multiple Memory Errors: %d\n", + (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0); + printf(" Multiple-Bit Error: %d\n", + (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0); + printf(" Single-Bit Error: %d\n", + (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0); + printf(" Memory Select Error: %d\n\n", + (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0); + + /* Capture data */ + printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address); + printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n", + ddr->capture_data_hi, ddr->capture_data_lo); + printf("Memory Data Path Read Capture ECC: 0x%02x\n\n", + ddr->capture_ecc & CAPTURE_ECC_ECE); + + printf("Memory Error Attributes Capture:\n"); + printf(" Data Beat Number: %d\n", + (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> + ECC_CAPT_ATTR_BNUM_SHIFT); + printf(" Transaction Size: %d\n", + (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> + ECC_CAPT_ATTR_TSIZ_SHIFT); + printf(" Transaction Source: %d\n", + (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> + ECC_CAPT_ATTR_TSRC_SHIFT); + printf(" Transaction Type: %d\n", + (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> + ECC_CAPT_ATTR_TTYP_SHIFT); + printf(" Error Information Valid: %d\n\n", + ddr->capture_attributes & ECC_CAPT_ATTR_VLD); +} + +int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ddr83xx_t *ddr = &immap->ddr; + volatile u32 val; + u64 *addr; + u32 count; + register u64 *i; + u32 ret[2]; + u32 pattern[2]; + u32 writeback[2]; + + /* The pattern is written into memory to generate error */ + pattern[0] = 0xfedcba98UL; + pattern[1] = 0x76543210UL; + + /* After injecting error, re-initialize the memory with the value */ + writeback[0] = 0x01234567UL; + writeback[1] = 0x89abcdefUL; + + if (argc > 4) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (argc == 2) { + if (strcmp(argv[1], "status") == 0) { + ecc_print_status(); + return 0; + } else if (strcmp(argv[1], "captureclear") == 0) { + ddr->capture_address = 0; + ddr->capture_data_hi = 0; + ddr->capture_data_lo = 0; + ddr->capture_ecc = 0; + ddr->capture_attributes = 0; + return 0; + } + } + if (argc == 3) { + if (strcmp(argv[1], "sbecnt") == 0) { + val = simple_strtoul(argv[2], NULL, 10); + if (val > 255) { + printf("Incorrect Counter value, " + "should be 0..255\n"); + return 1; + } + + val = (val << ECC_ERROR_MAN_SBEC_SHIFT); + val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET); + + ddr->err_sbe = val; + return 0; + } else if (strcmp(argv[1], "sbethr") == 0) { + val = simple_strtoul(argv[2], NULL, 10); + if (val > 255) { + printf("Incorrect Counter value, " + "should be 0..255\n"); + return 1; + } + + val = (val << ECC_ERROR_MAN_SBET_SHIFT); + val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC); + + ddr->err_sbe = val; + return 0; + } else if (strcmp(argv[1], "errdisable") == 0) { + val = ddr->err_disable; + + if (strcmp(argv[2], "+sbe") == 0) { + val |= ECC_ERROR_DISABLE_SBED; + } else if (strcmp(argv[2], "+mbe") == 0) { + val |= ECC_ERROR_DISABLE_MBED; + } else if (strcmp(argv[2], "+mse") == 0) { + val |= ECC_ERROR_DISABLE_MSED; + } else if (strcmp(argv[2], "+all") == 0) { + val |= (ECC_ERROR_DISABLE_SBED | + ECC_ERROR_DISABLE_MBED | + ECC_ERROR_DISABLE_MSED); + } else if (strcmp(argv[2], "-sbe") == 0) { + val &= ~ECC_ERROR_DISABLE_SBED; + } else if (strcmp(argv[2], "-mbe") == 0) { + val &= ~ECC_ERROR_DISABLE_MBED; + } else if (strcmp(argv[2], "-mse") == 0) { + val &= ~ECC_ERROR_DISABLE_MSED; + } else if (strcmp(argv[2], "-all") == 0) { + val &= ~(ECC_ERROR_DISABLE_SBED | + ECC_ERROR_DISABLE_MBED | + ECC_ERROR_DISABLE_MSED); + } else { + printf("Incorrect err_disable field\n"); + return 1; + } + + ddr->err_disable = val; + __asm__ __volatile__("sync"); + __asm__ __volatile__("isync"); + return 0; + } else if (strcmp(argv[1], "errdetectclr") == 0) { + val = ddr->err_detect; + + if (strcmp(argv[2], "mme") == 0) { + val |= ECC_ERROR_DETECT_MME; + } else if (strcmp(argv[2], "sbe") == 0) { + val |= ECC_ERROR_DETECT_SBE; + } else if (strcmp(argv[2], "mbe") == 0) { + val |= ECC_ERROR_DETECT_MBE; + } else if (strcmp(argv[2], "mse") == 0) { + val |= ECC_ERROR_DETECT_MSE; + } else if (strcmp(argv[2], "all") == 0) { + val |= (ECC_ERROR_DETECT_MME | + ECC_ERROR_DETECT_MBE | + ECC_ERROR_DETECT_SBE | + ECC_ERROR_DETECT_MSE); + } else { + printf("Incorrect err_detect field\n"); + return 1; + } + + ddr->err_detect = val; + return 0; + } else if (strcmp(argv[1], "injectdatahi") == 0) { + val = simple_strtoul(argv[2], NULL, 16); + + ddr->data_err_inject_hi = val; + return 0; + } else if (strcmp(argv[1], "injectdatalo") == 0) { + val = simple_strtoul(argv[2], NULL, 16); + + ddr->data_err_inject_lo = val; + return 0; + } else if (strcmp(argv[1], "injectecc") == 0) { + val = simple_strtoul(argv[2], NULL, 16); + if (val > 0xff) { + printf("Incorrect ECC inject mask, " + "should be 0x00..0xff\n"); + return 1; + } + val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM); + + ddr->ecc_err_inject = val; + return 0; + } else if (strcmp(argv[1], "inject") == 0) { + val = ddr->ecc_err_inject; + + if (strcmp(argv[2], "en") == 0) + val |= ECC_ERR_INJECT_EIEN; + else if (strcmp(argv[2], "dis") == 0) + val &= ~ECC_ERR_INJECT_EIEN; + else + printf("Incorrect command\n"); + + ddr->ecc_err_inject = val; + __asm__ __volatile__("sync"); + __asm__ __volatile__("isync"); + return 0; + } else if (strcmp(argv[1], "mirror") == 0) { + val = ddr->ecc_err_inject; + + if (strcmp(argv[2], "en") == 0) + val |= ECC_ERR_INJECT_EMB; + else if (strcmp(argv[2], "dis") == 0) + val &= ~ECC_ERR_INJECT_EMB; + else + printf("Incorrect command\n"); + + ddr->ecc_err_inject = val; + return 0; + } + } + if (argc == 4) { + if (strcmp(argv[1], "testdw") == 0) { + addr = (u64 *) simple_strtoul(argv[2], NULL, 16); + count = simple_strtoul(argv[3], NULL, 16); + + if ((u32) addr % 8) { + printf("Address not alligned on " + "double word boundary\n"); + return 1; + } + disable_interrupts(); + + for (i = addr; i < addr + count; i++) { + + /* enable injects */ + ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; + __asm__ __volatile__("sync"); + __asm__ __volatile__("isync"); + + /* write memory location injecting errors */ + ppcDWstore((u32 *) i, pattern); + __asm__ __volatile__("sync"); + + /* disable injects */ + ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; + __asm__ __volatile__("sync"); + __asm__ __volatile__("isync"); + + /* read data, this generates ECC error */ + ppcDWload((u32 *) i, ret); + __asm__ __volatile__("sync"); + + /* re-initialize memory, double word write the location again, + * generates new ECC code this time */ + ppcDWstore((u32 *) i, writeback); + __asm__ __volatile__("sync"); + } + enable_interrupts(); + return 0; + } + if (strcmp(argv[1], "testword") == 0) { + addr = (u64 *) simple_strtoul(argv[2], NULL, 16); + count = simple_strtoul(argv[3], NULL, 16); + + if ((u32) addr % 8) { + printf("Address not alligned on " + "double word boundary\n"); + return 1; + } + disable_interrupts(); + + for (i = addr; i < addr + count; i++) { + + /* enable injects */ + ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; + __asm__ __volatile__("sync"); + __asm__ __volatile__("isync"); + + /* write memory location injecting errors */ + *(u32 *) i = 0xfedcba98UL; + __asm__ __volatile__("sync"); + + /* sub double word write, + * bus will read-modify-write, + * generates ECC error */ + *((u32 *) i + 1) = 0x76543210UL; + __asm__ __volatile__("sync"); + + /* disable injects */ + ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; + __asm__ __volatile__("sync"); + __asm__ __volatile__("isync"); + + /* re-initialize memory, + * double word write the location again, + * generates new ECC code this time */ + ppcDWstore((u32 *) i, writeback); + __asm__ __volatile__("sync"); + } + enable_interrupts(); + return 0; + } + } + printf("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD(ecc, 4, 0, do_ecc, + "ecc - support for DDR ECC features\n", + "status - print out status info\n" + "ecc captureclear - clear capture regs data\n" + "ecc sbecnt - set Single-Bit Error counter\n" + "ecc sbethr - set Single-Bit Threshold\n" + "ecc errdisable - clear/set disable Memory Error Disable, flag:\n" + " [-|+]sbe - Single-Bit Error\n" + " [-|+]mbe - Multiple-Bit Error\n" + " [-|+]mse - Memory Select Error\n" + " [-|+]all - all errors\n" + "ecc errdetectclr - clear Memory Error Detect, flag:\n" + " mme - Multiple Memory Errors\n" + " sbe - Single-Bit Error\n" + " mbe - Multiple-Bit Error\n" + " mse - Memory Select Error\n" + " all - all errors\n" + "ecc injectdatahi - set Memory Data Path Error Injection Mask High\n" + "ecc injectdatalo - set Memory Data Path Error Injection Mask Low\n" + "ecc injectecc - set ECC Error Injection Mask\n" + "ecc inject - enable/disable error injection\n" + "ecc mirror - enable/disable mirror byte\n" + "ecc testdw - test mem region with double word access:\n" + " - enables injects\n" + " - writes pattern injecting errors with double word access\n" + " - disables injects\n" + " - reads pattern back with double word access, generates error\n" + " - re-inits memory\n" + "ecc testword - test mem region with word access:\n" + " - enables injects\n" + " - writes pattern injecting errors with word access\n" + " - writes pattern with word access, generates error\n" + " - disables injects\n" " - re-inits memory"); +#endif -- cgit v1.3.1 From cfc7a7f5bb3273c9951173c788001d45118f141f Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 2 Aug 2007 14:42:20 -0500 Subject: cpu/86xx fixes. Remove rev 1 fixes. Always set PICGCR_MODE. Enable machine check and provide board config option to set and handle SoC error interrupts. Include MSSSR0 in error message. Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT. Signed-off-by: Ed Swarthout Signed-off-by: Jon Loeliger --- cpu/mpc86xx/cpu_init.c | 4 +-- cpu/mpc86xx/interrupts.c | 51 ++++++++++++++------------ cpu/mpc86xx/start.S | 85 ++++++++------------------------------------ cpu/mpc86xx/traps.c | 8 +++-- include/asm-ppc/immap_86xx.h | 16 ++++++--- include/asm-ppc/processor.h | 3 +- 6 files changed, 65 insertions(+), 102 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index 4673d05e719..c8e46666949 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -104,8 +104,8 @@ void cpu_init_f(void) /* enable the timebase bit in HID0 */ set_hid0(get_hid0() | 0x4000000); - /* enable SYNCBE | ABE bits in HID1 */ - set_hid1(get_hid1() | 0x00000C00); + /* enable EMCP, SYNCBE | ABE bits in HID1 */ + set_hid1(get_hid1() | 0x80000C00); } /* diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index 08e0675fee4..d9f634fdab8 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -8,7 +8,7 @@ * (C) Copyright 2003 Motorola Inc. (MPC85xx port) * Xianghua Xiao (X.Xiao@motorola.com) * - * (C) Copyright 2004 Freescale Semiconductor. (MPC86xx Port) + * (C) Copyright 2004, 2007 Freescale Semiconductor. (MPC86xx Port) * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -80,25 +80,10 @@ int interrupt_init(void) { int ret; - /* - * The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to - * implement PEX10 errata. As INT is active high, it - * will cause core to take 0x500 interrupt. - * - * Due to the PIC's default pass through mode, as soon - * as interrupts are enabled (MSR[EE] = 1), an interrupt - * will be taken and u-boot will hang. This is due to a - * hardware change (per an errata fix) on new revisions - * of the board with Rev 2.x parts. - * - * Setting the PIC to mixed mode prevents the hang. - */ - if ((get_svr() & 0xf0) == 0x20) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; - immr->im_pic.gcr = MPC86xx_PICGCR_RST; - while (immr->im_pic.gcr & MPC86xx_PICGCR_RST); - immr->im_pic.gcr = MPC86xx_PICGCR_MODE; - } + volatile immap_t *immr = (immap_t *)CFG_IMMR; + immr->im_pic.gcr = MPC86xx_PICGCR_RST; + while (immr->im_pic.gcr & MPC86xx_PICGCR_RST); + immr->im_pic.gcr = MPC86xx_PICGCR_MODE; /* call cpu specific function from $(CPU)/interrupts.c */ ret = interrupt_init_cpu(&decrementer_count); @@ -119,6 +104,30 @@ int interrupt_init(void) get_msr(), get_dec()); +#ifdef CONFIG_INTERRUPTS + volatile ccsr_pic_t *pic = &immr->im_pic; + + pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */ + debug("iivpr1@%x = %x\n", &pic->iivpr1, pic->iivpr1); + + pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ + debug("iivpr2@%x = %x\n", &pic->iivpr2, pic->iivpr2); + + pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */ + debug("iivpr3@%x = %x\n", &pic->iivpr3, pic->iivpr3); + +#if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1) + pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */ + debug("iivpr8@%x = %x\n", &pic->iivpr8, pic->iivpr8); +#endif +#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2) + pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */ + debug("iivpr9@%x = %x\n", &pic->iivpr9, pic->iivpr9); +#endif + + pic->ctpr = 0; /* 40080 clear current task priority register */ +#endif + return 0; } @@ -158,8 +167,6 @@ void timer_interrupt(struct pt_regs *regs) timestamp++; - ppcDcbf((unsigned long)×tamp); - /* Restore Decrementer Count */ set_dec(decrementer_count); diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 412745bdaea..c83310a3339 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor. * Srikanth Srinivasan * * See file CREDITS for list of people who contributed to this @@ -44,11 +44,9 @@ #define CONFIG_IDENT_STRING "" #endif -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -/* Machine Check and Recoverable Interr. */ -#define MSR_KERNEL ( MSR_ME | MSR_RI ) +/* + * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions + */ /* * Set up GOT: Global Offset Table @@ -195,17 +193,21 @@ boot_warm: bl secondary_cpu_setup #endif +1: +#ifdef CFG_RAMBOOT /* disable everything */ -1: li r0, 0 + li r0, 0 mtspr HID0, r0 sync mtmsr 0 +#endif + bl invalidate_bats sync #ifdef CFG_L2 /* init the L2 cache */ - addis r3, r0, L2_INIT@h + lis r3, L2_INIT@h ori r3, r3, L2_INIT@l mtspr l2cr, r3 /* invalidate the L2 cache */ @@ -241,69 +243,9 @@ in_flash: bl setup_ccsrbar #endif - - /* -- MPC8641 Rev 1.0 MCM Errata fixups -- */ - - /* skip fixups if not Rev 1.0 */ - mfspr r4, SVR - rlwinm r4,r4,0,24,31 - cmpwi r4,0x10 - bne 1f - - lis r3,MCM_ABCR@ha - lwz r4,MCM_ABCR@l(r3) /* ABCR -> r4 */ - - /* set ABCR[A_STRM_CNT] = 0 */ - rlwinm r4,r4,0,0,29 - - /* set ABCR[ARB_POLICY] to 0x1 (round-robin) */ - addi r0,r0,1 - rlwimi r4,r0,12,18,19 - - stw r4,MCM_ABCR@l(r3) /* r4 -> ABCR */ - sync - - /* Set DBCR[ERD_DIS] */ - lis r3,MCM_DBCR@ha - lwz r4,MCM_DBCR@l(r3) - oris r4, r4, 0x4000 - stw r4,MCM_DBCR@l(r3) - sync -1: /* setup the law entries */ bl law_entry sync - - -#if (EMULATOR_RUN == 1) - /* On the emulator we want to adjust these ASAP */ - /* otherwise things are sloooow */ - /* Setup OR0 (LALE FIX)*/ - lis r3, CFG_CCSRBAR@h - ori r3, r3, 0x5004 - li r4, 0x0FF3 - stw r4, 0(r3) - sync - - /* Setup LCRR */ - lis r3, CFG_CCSRBAR@h - ori r3, r3, 0x50D4 - lis r4, 0x8000 - ori r4, r4, 0x0002 - stw r4, 0(r3) - sync -#endif -#if 1 - /* make sure timer enabled in guts register too */ - lis r3, CFG_CCSRBAR@h - oris r3,r3, 0xE - ori r3,r3,0x0070 - lwz r4, 0(r3) - lis r5,0xFFFC - ori r5,r5,0x5FFF - and r4,r4,r5 - stw r4,0(r3) -#endif /* * Cache must be enabled here for stack-in-cache trick. * This means we need to enable the BATS. @@ -346,8 +288,6 @@ in_flash: #ifdef RUN_DIAG - /* Sri: Code to run the diagnostic automatically */ - /* Load PX_AUX register address in r4 */ lis r4, 0xf810 ori r4, r4, 0x6 @@ -392,6 +332,7 @@ diag_done: .globl invalidate_bats invalidate_bats: + li r0, 0 /* invalidate BATs */ mtspr IBAT0U, r0 mtspr IBAT1U, r0 @@ -1040,6 +981,7 @@ trap_init: mfmsr r7 li r8,MSR_IP andc r7,r7,r8 + ori r7,r7,MSR_ME /* Enable Machine Check */ mtmsr r7 mtlr r4 /* restore link register */ @@ -1224,8 +1166,9 @@ secondary_cpu_setup: sync isync - /*SYNCBE|ABE in HID1*/ + /* MCP|SYNCBE|ABE in HID1 */ mfspr r4, HID1 + oris r4, r4, 0x8000 ori r4, r4, 0x0C00 mtspr HID1, r4 sync diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c index fab1975834e..c84bfbf6aaa 100644 --- a/cpu/mpc86xx/traps.c +++ b/cpu/mpc86xx/traps.c @@ -130,8 +130,11 @@ MachineCheckException(struct pt_regs *regs) printf("Machine check in kernel mode.\n"); printf("Caused by (from msr): "); printf("regs %p ", regs); - switch (regs->msr & 0x000F0000) { - case (0x80000000 >> 12): + switch ( regs->msr & 0x001F0000) { + case (0x80000000>>11): + printf("MSS error. MSSSR0: %08x\n", mfspr(SPRN_MSSSR0)); + break; + case (0x80000000>>12): printf("Machine check signal - probably due to mm fault\n" "with mmu off\n"); break; @@ -209,6 +212,7 @@ UnknownException(struct pt_regs *regs) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif + printf("UnknownException regs@%x\n", regs); printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", regs->nip, regs->msr, regs->trap); _exception(0, regs); diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 0e3fc3403d5..169725b9236 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -1257,9 +1257,12 @@ typedef struct ccsr_gur { uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ uint porbmsr; /* 0xe0004 - POR boot mode status register */ #define MPC86xx_PORBMSR_HA 0x00060000 +#define MPC85xx_PORBMSR_HA 0x00070000 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ -#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000 +#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000 +#define MPC85xx_PORDEVSR_IO_SEL 0x00380000 /* 85xx platform type */ +#define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */ uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ char res1[12]; uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ @@ -1273,8 +1276,11 @@ typedef struct ccsr_gur { uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ char res6[12]; uint devdisr; /* 0xe0070 - Device disable control */ -#define MPC86xx_DEVDISR_PCIEX1 0x80000000 -#define MPC86xx_DEVDISR_PCIEX2 0x40000000 +#define MPC86xx_DEVDISR_PCIEX1 0x80000000 +#define MPC86xx_DEVDISR_PCIEX2 0x40000000 +#define MPC86xx_DEVDISR_PCI1 0x80000000 +#define MPC86xx_DEVDISR_PCIE1 0x40000000 +#define MPC86xx_DEVDISR_PCIE2 0x20000000 char res7[12]; uint powmgtcsr; /* 0xe0080 - Power management status and control register */ char res8[12]; @@ -1282,7 +1288,9 @@ typedef struct ccsr_gur { char res9[12]; uint pvr; /* 0xe00a0 - Processor version register */ uint svr; /* 0xe00a4 - System version register */ - char res10[3416]; + char res10a[1880]; + uint clkdvdr; /* 0xe0800 - Clock Divide register */ + char res10b[1532]; uint clkocr; /* 0xe0e00 - Clock out select register */ char res11[12]; uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 71e2e847a46..b806cc09f1f 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -464,7 +464,8 @@ #define ESR_ST 0x00800000 /* Store Operation */ #if defined(CONFIG_MPC86xx) -#define SPRN_MSSCRO 0x3f6 +#define SPRN_MSSCR0 0x3f6 +#define SPRN_MSSSR0 0x3f7 #endif -- cgit v1.3.1 From c74b2108e31fe09bd1c5d291c3cf360510d4f13e Mon Sep 17 00:00:00 2001 From: Sergey Kubushyn Date: Fri, 10 Aug 2007 20:26:18 +0200 Subject: [ARM] TI DaVinci support, hopefully final Add support for the following DaVinci boards: - DV_EVM - SCHMOOGIE - SONATA Changes: - Split into separate board directories - Removed changes to MTD_DEBUG (or whatever it's called) - New CONFIG_CMD party line followed - Some cosmetic fixes, cleanup etc. - Patches against the latest U-Boot tree as of now. - Fixed CONFIG_CMD_NET in net files. - Fixed CONFIG_CMD_EEPROM for schmoogie. - Made sure it compiles and works (forceenv() link problem) on SCHMOOGIE and DV_EVM. Can't check if it works on SONATA, don't have a board any more, but it at least compiles. Here is an excerpt from session log on SCHMOOGIE... U-Boot 1.2.0-g6c33c785-dirty (Aug 7 2007 - 13:07:17) DRAM: 128 MB NAND: 128 MiB In: serial Out: serial Err: serial ARM Clock : 297MHz DDR Clock : 162MHz ETH PHY : DP83848 @ 0x01 U-Boot > iprobe Valid chip addresses: 1B 38 3A 3D 3F 50 5D 6F U-Boot > ping 192.168.253.10 host 192.168.253.10 is alive U-Boot > Signed-off-by: Sergey Kubushyn Acked-by: Dirk Behme Acked-by: Zach Sadecki Acked-by: Stefan Roese --- CREDITS | 4 + MAINTAINERS | 6 + MAKEALL | 3 +- Makefile | 9 + board/davinci/dv-evm/Makefile | 52 +++ board/davinci/dv-evm/board_init.S | 29 ++ board/davinci/dv-evm/config.mk | 39 ++ board/davinci/dv-evm/dv_board.c | 211 +++++++++ board/davinci/dv-evm/u-boot.lds | 52 +++ board/davinci/schmoogie/Makefile | 52 +++ board/davinci/schmoogie/board_init.S | 29 ++ board/davinci/schmoogie/config.mk | 39 ++ board/davinci/schmoogie/dv_board.c | 253 +++++++++++ board/davinci/schmoogie/u-boot.lds | 52 +++ board/davinci/sonata/Makefile | 52 +++ board/davinci/sonata/board_init.S | 100 +++++ board/davinci/sonata/config.mk | 39 ++ board/davinci/sonata/dv_board.c | 208 +++++++++ board/davinci/sonata/u-boot.lds | 52 +++ common/cmd_nvedit.c | 15 +- cpu/arm926ejs/davinci/Makefile | 49 +++ cpu/arm926ejs/davinci/dp83848.c | 156 +++++++ cpu/arm926ejs/davinci/ether.c | 652 ++++++++++++++++++++++++++++ cpu/arm926ejs/davinci/i2c.c | 351 +++++++++++++++ cpu/arm926ejs/davinci/lowlevel_init.S | 707 +++++++++++++++++++++++++++++++ cpu/arm926ejs/davinci/lxt972.c | 142 +++++++ cpu/arm926ejs/davinci/nand.c | 389 +++++++++++++++++ cpu/arm926ejs/davinci/reset.S | 77 ++++ cpu/arm926ejs/davinci/timer.c | 165 ++++++++ include/_exports.h | 3 + include/asm-arm/arch-davinci/emac_defs.h | 311 ++++++++++++++ include/asm-arm/arch-davinci/emif_defs.h | 61 +++ include/asm-arm/arch-davinci/hardware.h | 166 ++++++++ include/asm-arm/arch-davinci/i2c_defs.h | 94 ++++ include/asm-arm/arch-davinci/nand_defs.h | 161 +++++++ include/common.h | 3 + include/configs/davinci_dvevm.h | 214 ++++++++++ include/configs/davinci_schmoogie.h | 157 +++++++ include/configs/davinci_sonata.h | 209 +++++++++ include/dp83848.h | 88 ++++ include/exports.h | 3 + lib_arm/board.c | 7 + net/eth.c | 5 + 43 files changed, 5464 insertions(+), 2 deletions(-) create mode 100644 board/davinci/dv-evm/Makefile create mode 100644 board/davinci/dv-evm/board_init.S create mode 100644 board/davinci/dv-evm/config.mk create mode 100644 board/davinci/dv-evm/dv_board.c create mode 100644 board/davinci/dv-evm/u-boot.lds create mode 100644 board/davinci/schmoogie/Makefile create mode 100644 board/davinci/schmoogie/board_init.S create mode 100644 board/davinci/schmoogie/config.mk create mode 100644 board/davinci/schmoogie/dv_board.c create mode 100644 board/davinci/schmoogie/u-boot.lds create mode 100644 board/davinci/sonata/Makefile create mode 100644 board/davinci/sonata/board_init.S create mode 100644 board/davinci/sonata/config.mk create mode 100644 board/davinci/sonata/dv_board.c create mode 100644 board/davinci/sonata/u-boot.lds create mode 100644 cpu/arm926ejs/davinci/Makefile create mode 100644 cpu/arm926ejs/davinci/dp83848.c create mode 100644 cpu/arm926ejs/davinci/ether.c create mode 100644 cpu/arm926ejs/davinci/i2c.c create mode 100644 cpu/arm926ejs/davinci/lowlevel_init.S create mode 100644 cpu/arm926ejs/davinci/lxt972.c create mode 100644 cpu/arm926ejs/davinci/nand.c create mode 100644 cpu/arm926ejs/davinci/reset.S create mode 100644 cpu/arm926ejs/davinci/timer.c create mode 100644 include/asm-arm/arch-davinci/emac_defs.h create mode 100644 include/asm-arm/arch-davinci/emif_defs.h create mode 100644 include/asm-arm/arch-davinci/hardware.h create mode 100644 include/asm-arm/arch-davinci/i2c_defs.h create mode 100644 include/asm-arm/arch-davinci/nand_defs.h create mode 100644 include/configs/davinci_dvevm.h create mode 100644 include/configs/davinci_schmoogie.h create mode 100644 include/configs/davinci_sonata.h create mode 100644 include/dp83848.h (limited to 'cpu') diff --git a/CREDITS b/CREDITS index 7af1b806ab0..4c8b896f215 100644 --- a/CREDITS +++ b/CREDITS @@ -252,6 +252,10 @@ E: Raghu.Krishnaprasad@fci.com D: Support for Adder-II MPC852T evaluation board W: http://www.forcecomputers.com +N: Sergey Kubushyn +E: ksi@koi8.net +D: Support for various TI DaVinci based boards. + N: Bernhard Kuhn E: bkuhn@metrowerks.com D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards diff --git a/MAINTAINERS b/MAINTAINERS index 693b1157290..865f6fe0e12 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -444,6 +444,12 @@ Nishant Kamat omap1610h2 ARM926EJS +Sergey Kubushyn + + DV-EVM ARM926EJS + SONATA ARM926EJS + SCHMOOGIE ARM926EJS + Prakash Kumar cerf250 xscale diff --git a/MAKEALL b/MAKEALL index 3e186ccd5a3..c672b514be4 100755 --- a/MAKEALL +++ b/MAKEALL @@ -220,7 +220,8 @@ LIST_ARM9=" \ omap1610h2 omap1610inn omap730p2 sbc2410x \ scb9328 smdk2400 smdk2410 trab \ VCMA9 versatile versatileab versatilepb \ - voiceblue \ + voiceblue davinci_dvevm davinci_schmoogie \ + davinci_sonata " ######################################################################### diff --git a/Makefile b/Makefile index 0e6d3992dbe..87ddb1c933d 100644 --- a/Makefile +++ b/Makefile @@ -2018,6 +2018,15 @@ omap1510inn_config : unconfig omap5912osk_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs omap5912osk NULL omap +davinci_dvevm_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs dv-evm davinci davinci + +davinci_schmoogie_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs schmoogie davinci davinci + +davinci_sonata_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci + omap1610inn_config \ omap1610inn_cs0boot_config \ omap1610inn_cs3boot_config \ diff --git a/board/davinci/dv-evm/Makefile b/board/davinci/dv-evm/Makefile new file mode 100644 index 00000000000..fa0013811d4 --- /dev/null +++ b/board/davinci/dv-evm/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := dv_board.o +SOBJS := board_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/davinci/dv-evm/board_init.S b/board/davinci/dv-evm/board_init.S new file mode 100644 index 00000000000..22d8adc18ca --- /dev/null +++ b/board/davinci/dv-evm/board_init.S @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Board-specific low level initialization code. Called at the very end + * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * initialization required. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +.globl dv_board_init +dv_board_init: + + mov pc, lr diff --git a/board/davinci/dv-evm/config.mk b/board/davinci/dv-evm/config.mk new file mode 100644 index 00000000000..aa89d0ec8ae --- /dev/null +++ b/board/davinci/dv-evm/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# (C) Copyright 2003 +# Texas Instruments, +# Swaminathan +# +# Davinci EVM board (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Davinci EVM has 1 bank of 256 MB DDR RAM +# Physical Address: +# 8000'0000 to 9000'0000 +# +# Copyright (C) 2007 Sergey Kubushyn +# +# Visioneering Corp. Sonata board (ARM926EJS) cpu +# +# Sonata board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu +# +# Schmoogie board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) +# +# we load ourself to 8108 '0000 +# +# + +#Provide at least 16MB spacing between us and the Linux Kernel image +TEXT_BASE = 0x81080000 diff --git a/board/davinci/dv-evm/dv_board.c b/board/davinci/dv-evm/dv_board.c new file mode 100644 index 00000000000..94925ecfb14 --- /dev/null +++ b/board/davinci/dv-evm/dv_board.c @@ -0,0 +1,211 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Parts are shamelessly stolen from various TI sources, original copyright + * follows: + * ----------------------------------------------------------------- + * + * Copyright (C) 2004 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ + +#include +#include +#include +#include + +#define MACH_TYPE_DAVINCI_EVM 901 + +extern void i2c_init(int speed, int slaveaddr); +extern void timer_init(void); +extern int eth_hw_init(void); +extern phy_t phy; + + +/* Works on Always On power domain only (no PD argument) */ +void lpsc_on(unsigned int id) +{ + dv_reg_p mdstat, mdctl; + + if (id >= DAVINCI_LPSC_GEM) + return; /* Don't work on DSP Power Domain */ + + mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); + mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); + + while (REG(PSC_PTSTAT) & 0x01) {;} + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + /* Special treatment for some modules as for sprue14 p.7.4.2 */ + if ( (id == DAVINCI_LPSC_VPSSSLV) || + (id == DAVINCI_LPSC_EMAC) || + (id == DAVINCI_LPSC_EMAC_WRAPPER) || + (id == DAVINCI_LPSC_MDIO) || + (id == DAVINCI_LPSC_USB) || + (id == DAVINCI_LPSC_ATA) || + (id == DAVINCI_LPSC_VLYNQ) || + (id == DAVINCI_LPSC_UHPI) || + (id == DAVINCI_LPSC_DDR_EMIF) || + (id == DAVINCI_LPSC_AEMIF) || + (id == DAVINCI_LPSC_MMC_SD) || + (id == DAVINCI_LPSC_MEMSTICK) || + (id == DAVINCI_LPSC_McBSP) || + (id == DAVINCI_LPSC_GPIO) + ) + *mdctl |= 0x200; + + REG(PSC_PTCMD) = 0x01; + + while (REG(PSC_PTSTAT) & 0x03) {;} + while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ +} + +void dsp_on(void) +{ + int i; + + if (REG(PSC_PDSTAT1) & 0x1f) + return; /* Already on */ + + REG(PSC_GBLCTL) |= 0x01; + REG(PSC_PDCTL1) |= 0x01; + REG(PSC_PDCTL1) &= ~0x100; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; + REG(PSC_PTCMD) = 0x02; + + for (i = 0; i < 100; i++) { + if (REG(PSC_EPCPR) & 0x02) + break; + } + + REG(PSC_CHP_SHRTSW) = 0x01; + REG(PSC_PDCTL1) |= 0x100; + REG(PSC_EPCCR) = 0x02; + + for (i = 0; i < 100; i++) { + if (!(REG(PSC_PTSTAT) & 0x02)) + break; + } + + REG(PSC_GBLCTL) &= ~0x1f; +} + + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* Workaround for TMS320DM6446 errata 1.3.22 */ + REG(PSC_SILVER_BULLET) = 0; + + /* Power on required peripherals */ + lpsc_on(DAVINCI_LPSC_EMAC); + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); + lpsc_on(DAVINCI_LPSC_MDIO); + lpsc_on(DAVINCI_LPSC_I2C); + lpsc_on(DAVINCI_LPSC_UART0); + lpsc_on(DAVINCI_LPSC_TIMER1); + lpsc_on(DAVINCI_LPSC_GPIO); + + /* Powerup the DSP */ + dsp_on(); + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x0000e003; + + /* Enable GIO3.3V cells used for EMAC */ + REG(VDD3P3V_PWDN) = 0; + + /* Enable UART0 MUX lines */ + REG(PINMUX1) |= 1; + + /* Enable EMAC and AEMIF pins */ + REG(PINMUX0) = 0x80000c1f; + + /* Enable I2C pin Mux */ + REG(PINMUX1) |= (1 << 7); + + /* Set the Bus Priority Register to appropriate value */ + REG(VBPR) = 0x20; + + timer_init(); + + return(0); +} + +int misc_init_r (void) +{ + u_int8_t tmp[20], buf[10]; + int i = 0; + int clk = 0; + + clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); + + printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2); + printf ("DDR Clock : %dMHz\n", (clk / 2)); + + /* Set Ethernet MAC address from EEPROM */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) { + printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR); + } else { + tmp[0] = 0xff; + for (i = 0; i < 6; i++) + tmp[0] &= buf[i]; + + if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { + sprintf((char *)&tmp[0], "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); + setenv("ethaddr", (char *)&tmp[0]); + } + } + + if (!eth_hw_init()) { + printf("ethernet init failed!\n"); + } else { + printf("ETH PHY : %s\n", phy.name); + } + + i2c_read (0x39, 0x00, 1, (u_int8_t *)&i, 1); + + setenv ("videostd", ((i & 0x80) ? "pal" : "ntsc")); + + return(0); +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return(0); +} diff --git a/board/davinci/dv-evm/u-boot.lds b/board/davinci/dv-evm/u-boot.lds new file mode 100644 index 00000000000..710b2a2d6e6 --- /dev/null +++ b/board/davinci/dv-evm/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/davinci/schmoogie/Makefile b/board/davinci/schmoogie/Makefile new file mode 100644 index 00000000000..fa0013811d4 --- /dev/null +++ b/board/davinci/schmoogie/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := dv_board.o +SOBJS := board_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/davinci/schmoogie/board_init.S b/board/davinci/schmoogie/board_init.S new file mode 100644 index 00000000000..22d8adc18ca --- /dev/null +++ b/board/davinci/schmoogie/board_init.S @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Board-specific low level initialization code. Called at the very end + * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * initialization required. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +.globl dv_board_init +dv_board_init: + + mov pc, lr diff --git a/board/davinci/schmoogie/config.mk b/board/davinci/schmoogie/config.mk new file mode 100644 index 00000000000..aa89d0ec8ae --- /dev/null +++ b/board/davinci/schmoogie/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# (C) Copyright 2003 +# Texas Instruments, +# Swaminathan +# +# Davinci EVM board (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Davinci EVM has 1 bank of 256 MB DDR RAM +# Physical Address: +# 8000'0000 to 9000'0000 +# +# Copyright (C) 2007 Sergey Kubushyn +# +# Visioneering Corp. Sonata board (ARM926EJS) cpu +# +# Sonata board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu +# +# Schmoogie board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) +# +# we load ourself to 8108 '0000 +# +# + +#Provide at least 16MB spacing between us and the Linux Kernel image +TEXT_BASE = 0x81080000 diff --git a/board/davinci/schmoogie/dv_board.c b/board/davinci/schmoogie/dv_board.c new file mode 100644 index 00000000000..b15c5f71893 --- /dev/null +++ b/board/davinci/schmoogie/dv_board.c @@ -0,0 +1,253 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Parts are shamelessly stolen from various TI sources, original copyright + * follows: + * ----------------------------------------------------------------- + * + * Copyright (C) 2004 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ + +#include +#include +#include +#include + +#define MACH_TYPE_SCHMOOGIE 1255 + +extern void i2c_init(int speed, int slaveaddr); +extern void timer_init(void); +extern int eth_hw_init(void); +extern phy_t phy; + + +/* Works on Always On power domain only (no PD argument) */ +void lpsc_on(unsigned int id) +{ + dv_reg_p mdstat, mdctl; + + if (id >= DAVINCI_LPSC_GEM) + return; /* Don't work on DSP Power Domain */ + + mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); + mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); + + while (REG(PSC_PTSTAT) & 0x01) {;} + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + /* Special treatment for some modules as for sprue14 p.7.4.2 */ + if ( (id == DAVINCI_LPSC_VPSSSLV) || + (id == DAVINCI_LPSC_EMAC) || + (id == DAVINCI_LPSC_EMAC_WRAPPER) || + (id == DAVINCI_LPSC_MDIO) || + (id == DAVINCI_LPSC_USB) || + (id == DAVINCI_LPSC_ATA) || + (id == DAVINCI_LPSC_VLYNQ) || + (id == DAVINCI_LPSC_UHPI) || + (id == DAVINCI_LPSC_DDR_EMIF) || + (id == DAVINCI_LPSC_AEMIF) || + (id == DAVINCI_LPSC_MMC_SD) || + (id == DAVINCI_LPSC_MEMSTICK) || + (id == DAVINCI_LPSC_McBSP) || + (id == DAVINCI_LPSC_GPIO) + ) + *mdctl |= 0x200; + + REG(PSC_PTCMD) = 0x01; + + while (REG(PSC_PTSTAT) & 0x03) {;} + while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ +} + +void dsp_on(void) +{ + int i; + + if (REG(PSC_PDSTAT1) & 0x1f) + return; /* Already on */ + + REG(PSC_GBLCTL) |= 0x01; + REG(PSC_PDCTL1) |= 0x01; + REG(PSC_PDCTL1) &= ~0x100; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; + REG(PSC_PTCMD) = 0x02; + + for (i = 0; i < 100; i++) { + if (REG(PSC_EPCPR) & 0x02) + break; + } + + REG(PSC_CHP_SHRTSW) = 0x01; + REG(PSC_PDCTL1) |= 0x100; + REG(PSC_EPCCR) = 0x02; + + for (i = 0; i < 100; i++) { + if (!(REG(PSC_PTSTAT) & 0x02)) + break; + } + + REG(PSC_GBLCTL) &= ~0x1f; +} + + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_SCHMOOGIE; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* Workaround for TMS320DM6446 errata 1.3.22 */ + REG(PSC_SILVER_BULLET) = 0; + + /* Power on required peripherals */ + lpsc_on(DAVINCI_LPSC_EMAC); + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); + lpsc_on(DAVINCI_LPSC_MDIO); + lpsc_on(DAVINCI_LPSC_I2C); + lpsc_on(DAVINCI_LPSC_UART0); + lpsc_on(DAVINCI_LPSC_TIMER1); + lpsc_on(DAVINCI_LPSC_GPIO); + + /* Powerup the DSP */ + dsp_on(); + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x0000e003; + + /* Enable GIO3.3V cells used for EMAC */ + REG(VDD3P3V_PWDN) = 0; + + /* Enable UART0 MUX lines */ + REG(PINMUX1) |= 1; + + /* Enable EMAC and AEMIF pins */ + REG(PINMUX0) = 0x80000c1f; + + /* Enable I2C pin Mux */ + REG(PINMUX1) |= (1 << 7); + + /* Set the Bus Priority Register to appropriate value */ + REG(VBPR) = 0x20; + + timer_init(); + + return(0); +} + +int misc_init_r (void) +{ + u_int8_t tmp[20], buf[10]; + int i = 0; + int clk = 0; + + /* Set serial number from UID chip */ + u_int8_t crc_tbl[256] = { + 0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83, + 0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41, + 0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e, + 0x5f, 0x01, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc, + 0x23, 0x7d, 0x9f, 0xc1, 0x42, 0x1c, 0xfe, 0xa0, + 0xe1, 0xbf, 0x5d, 0x03, 0x80, 0xde, 0x3c, 0x62, + 0xbe, 0xe0, 0x02, 0x5c, 0xdf, 0x81, 0x63, 0x3d, + 0x7c, 0x22, 0xc0, 0x9e, 0x1d, 0x43, 0xa1, 0xff, + 0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5, + 0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x07, + 0xdb, 0x85, 0x67, 0x39, 0xba, 0xe4, 0x06, 0x58, + 0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a, + 0x65, 0x3b, 0xd9, 0x87, 0x04, 0x5a, 0xb8, 0xe6, + 0xa7, 0xf9, 0x1b, 0x45, 0xc6, 0x98, 0x7a, 0x24, + 0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b, + 0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x05, 0xe7, 0xb9, + 0x8c, 0xd2, 0x30, 0x6e, 0xed, 0xb3, 0x51, 0x0f, + 0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd, + 0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92, + 0xd3, 0x8d, 0x6f, 0x31, 0xb2, 0xec, 0x0e, 0x50, + 0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c, + 0x6d, 0x33, 0xd1, 0x8f, 0x0c, 0x52, 0xb0, 0xee, + 0x32, 0x6c, 0x8e, 0xd0, 0x53, 0x0d, 0xef, 0xb1, + 0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73, + 0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49, + 0x08, 0x56, 0xb4, 0xea, 0x69, 0x37, 0xd5, 0x8b, + 0x57, 0x09, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4, + 0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16, + 0xe9, 0xb7, 0x55, 0x0b, 0x88, 0xd6, 0x34, 0x6a, + 0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8, + 0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7, + 0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35 + }; + + clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); + + printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2); + printf ("DDR Clock : %dMHz\n", (clk / 2)); + + /* Set serial number from UID chip */ + if (i2c_read(CFG_UID_ADDR, 0, 1, buf, 8)) { + printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR); + forceenv("serial#", "FAILED"); + } else { + if (buf[0] != 0x70) { /* Device Family Code */ + printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR); + forceenv("serial#", "FAILED"); + } + } + /* Now check CRC */ + tmp[0] = 0; + for (i = 0; i < 8; i++) + tmp[0] = crc_tbl[tmp[0] ^ buf[i]]; + + if (tmp[0] != 0) { + printf("\nUID @ 0x%02x - BAD CRC!!!\n", CFG_UID_ADDR); + forceenv("serial#", "FAILED"); + } else { + /* CRC OK, set "serial" env variable */ + sprintf((char *)&tmp[0], "%02hhx%02hhx%02hhx%02hhx%02hhx%02hhx", + buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]); + forceenv("serial#", (char *)&tmp[0]); + } + + if (!eth_hw_init()) { + printf("ethernet init failed!\n"); + } else { + printf("ETH PHY : %s\n", phy.name); + } + + return(0); +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return(0); +} diff --git a/board/davinci/schmoogie/u-boot.lds b/board/davinci/schmoogie/u-boot.lds new file mode 100644 index 00000000000..710b2a2d6e6 --- /dev/null +++ b/board/davinci/schmoogie/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/davinci/sonata/Makefile b/board/davinci/sonata/Makefile new file mode 100644 index 00000000000..fa0013811d4 --- /dev/null +++ b/board/davinci/sonata/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := dv_board.o +SOBJS := board_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/davinci/sonata/board_init.S b/board/davinci/sonata/board_init.S new file mode 100644 index 00000000000..fbb9ea73e9f --- /dev/null +++ b/board/davinci/sonata/board_init.S @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Board-specific low level initialization code. Called at the very end + * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * initialization required. + * + * For _OLDER_ Sonata boards sets up GPIO4 to control NAND WP line. Newer + * Sonata boards, AFAIK, don't use this so it's just return by default. Ask + * Visioneering if they reinvented the wheel once again to make sure :) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +.globl dv_board_init +dv_board_init: +#ifdef SONATA_BOARD_GPIOWP + /* Set PINMUX0 to enable GPIO4 */ + ldr r0, _PINMUX0 + ldr r1, GPIO4_EN_MASK + ldr r2, [r0] + and r2, r2, r1 + str r2, [r0] + + /* Enable GPIO LPSC module */ + ldr r0, PTSTAT + +gpio_ptstat_loop1: + ldr r2, [r0] + tst r2, $0x00000001 + bne gpio_ptstat_loop1 + + ldr r1, MDCTL_GPIO + ldr r2, [r1] + and r2, r2, $0xfffffff8 + orr r2, r2, $0x00000003 + str r2, [r1] + + orr r2, r2, $0x00000200 + str r2, [r1] + + ldr r1, PTCMD + mov r2, $0x00000001 + str r2, [r1] + +gpio_ptstat_loop2: + ldr r2, [r0] + tst r2, $0x00000001 + bne gpio_ptstat_loop2 + + ldr r0, MDSTAT_GPIO +gpio_mdstat_loop: + ldr r2, [r0] + and r2, r2, $0x0000001f + teq r2, $0x00000003 + bne gpio_mdstat_loop + + /* GPIO4 -> output */ + ldr r0, GPIO_DIR01 + mov r1, $0x10 + ldr r2, [r0] + bic r2, r2, r0 + str r2, [r0] + + /* Set it to 0 (Write Protect) */ + ldr r0, GPIO_CLR_DATA01 + str r1, [r0] +#endif + + mov pc, lr + +#ifdef SONATA_BOARD_GPIOWP +.ltorg + +GPIO4_EN_MASK: + .word 0xf77fffff +MDCTL_GPIO: + .word 0x01c41a68 +MDSTAT_GPIO: + .word 0x01c41868 +GPIO_DIR01: + .word 0x01c67010 +GPIO_CLR_DATA01: + .word 0x01c6701c +#endif diff --git a/board/davinci/sonata/config.mk b/board/davinci/sonata/config.mk new file mode 100644 index 00000000000..aa89d0ec8ae --- /dev/null +++ b/board/davinci/sonata/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# (C) Copyright 2003 +# Texas Instruments, +# Swaminathan +# +# Davinci EVM board (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Davinci EVM has 1 bank of 256 MB DDR RAM +# Physical Address: +# 8000'0000 to 9000'0000 +# +# Copyright (C) 2007 Sergey Kubushyn +# +# Visioneering Corp. Sonata board (ARM926EJS) cpu +# +# Sonata board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu +# +# Schmoogie board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) +# +# we load ourself to 8108 '0000 +# +# + +#Provide at least 16MB spacing between us and the Linux Kernel image +TEXT_BASE = 0x81080000 diff --git a/board/davinci/sonata/dv_board.c b/board/davinci/sonata/dv_board.c new file mode 100644 index 00000000000..7b0a459fa31 --- /dev/null +++ b/board/davinci/sonata/dv_board.c @@ -0,0 +1,208 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Parts are shamelessly stolen from various TI sources, original copyright + * follows: + * ----------------------------------------------------------------- + * + * Copyright (C) 2004 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ + +#include +#include +#include +#include + +#define MACH_TYPE_SONATA 1254 + +extern void i2c_init(int speed, int slaveaddr); +extern void timer_init(void); +extern int eth_hw_init(void); +extern phy_t phy; + + +/* Works on Always On power domain only (no PD argument) */ +void lpsc_on(unsigned int id) +{ + dv_reg_p mdstat, mdctl; + + if (id >= DAVINCI_LPSC_GEM) + return; /* Don't work on DSP Power Domain */ + + mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); + mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); + + while (REG(PSC_PTSTAT) & 0x01) {;} + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + /* Special treatment for some modules as for sprue14 p.7.4.2 */ + if ( (id == DAVINCI_LPSC_VPSSSLV) || + (id == DAVINCI_LPSC_EMAC) || + (id == DAVINCI_LPSC_EMAC_WRAPPER) || + (id == DAVINCI_LPSC_MDIO) || + (id == DAVINCI_LPSC_USB) || + (id == DAVINCI_LPSC_ATA) || + (id == DAVINCI_LPSC_VLYNQ) || + (id == DAVINCI_LPSC_UHPI) || + (id == DAVINCI_LPSC_DDR_EMIF) || + (id == DAVINCI_LPSC_AEMIF) || + (id == DAVINCI_LPSC_MMC_SD) || + (id == DAVINCI_LPSC_MEMSTICK) || + (id == DAVINCI_LPSC_McBSP) || + (id == DAVINCI_LPSC_GPIO) + ) + *mdctl |= 0x200; + + REG(PSC_PTCMD) = 0x01; + + while (REG(PSC_PTSTAT) & 0x03) {;} + while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ +} + +void dsp_on(void) +{ + int i; + + if (REG(PSC_PDSTAT1) & 0x1f) + return; /* Already on */ + + REG(PSC_GBLCTL) |= 0x01; + REG(PSC_PDCTL1) |= 0x01; + REG(PSC_PDCTL1) &= ~0x100; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; + REG(PSC_PTCMD) = 0x02; + + for (i = 0; i < 100; i++) { + if (REG(PSC_EPCPR) & 0x02) + break; + } + + REG(PSC_CHP_SHRTSW) = 0x01; + REG(PSC_PDCTL1) |= 0x100; + REG(PSC_EPCCR) = 0x02; + + for (i = 0; i < 100; i++) { + if (!(REG(PSC_PTSTAT) & 0x02)) + break; + } + + REG(PSC_GBLCTL) &= ~0x1f; +} + + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_SONATA; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* Workaround for TMS320DM6446 errata 1.3.22 */ + REG(PSC_SILVER_BULLET) = 0; + + /* Power on required peripherals */ + lpsc_on(DAVINCI_LPSC_EMAC); + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); + lpsc_on(DAVINCI_LPSC_MDIO); + lpsc_on(DAVINCI_LPSC_I2C); + lpsc_on(DAVINCI_LPSC_UART0); + lpsc_on(DAVINCI_LPSC_TIMER1); + lpsc_on(DAVINCI_LPSC_GPIO); + + /* Powerup the DSP */ + dsp_on(); + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x0000e003; + + /* Enable GIO3.3V cells used for EMAC */ + REG(VDD3P3V_PWDN) = 0; + + /* Enable UART0 MUX lines */ + REG(PINMUX1) |= 1; + + /* Enable EMAC and AEMIF pins */ + REG(PINMUX0) = 0x80000c1f; + + /* Enable I2C pin Mux */ + REG(PINMUX1) |= (1 << 7); + + /* Set the Bus Priority Register to appropriate value */ + REG(VBPR) = 0x20; + + timer_init(); + + return(0); +} + +int misc_init_r (void) +{ + u_int8_t tmp[20], buf[10]; + int i = 0; + int clk = 0; + + + clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); + + printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2); + printf ("DDR Clock : %dMHz\n", (clk / 2)); + + /* Set Ethernet MAC address from EEPROM */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) { + printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR); + } else { + tmp[0] = 0xff; + for (i = 0; i < 6; i++) + tmp[0] &= buf[i]; + + if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { + sprintf((char *)&tmp[0], "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); + setenv("ethaddr", (char *)&tmp[0]); + } + } + + if (!eth_hw_init()) { + printf("ethernet init failed!\n"); + } else { + printf("ETH PHY : %s\n", phy.name); + } + + return(0); +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return(0); +} diff --git a/board/davinci/sonata/u-boot.lds b/board/davinci/sonata/u-boot.lds new file mode 100644 index 00000000000..710b2a2d6e6 --- /dev/null +++ b/board/davinci/sonata/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index de5a5148f69..1db0fc3c03b 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -193,7 +193,12 @@ int _do_setenv (int flag, int argc, char *argv[]) * Ethernet Address and serial# can be set only once, * ver is readonly. */ +#ifdef CONFIG_HAS_UID + /* Allow serial# forced overwrite with 0xdeaf4add flag */ + if ( ((strcmp (name, "serial#") == 0) && (flag != 0xdeaf4add)) || +#else if ( (strcmp (name, "serial#") == 0) || +#endif ((strcmp (name, "ethaddr") == 0) #if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR) && (strcmp ((char *)env_get_addr(oldval),MK_STR(CONFIG_ETHADDR)) != 0) @@ -397,7 +402,15 @@ void setenv (char *varname, char *varvalue) _do_setenv (0, 3, argv); } -int do_setenv ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +#ifdef CONFIG_HAS_UID +void forceenv (char *varname, char *varvalue) +{ + char *argv[4] = { "forceenv", varname, varvalue, NULL }; + _do_setenv (0xdeaf4add, 3, argv); +} +#endif + +int do_setenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { if (argc < 2) { printf ("Usage:\n%s\n", cmdtp->usage); diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile new file mode 100644 index 00000000000..0f77f402ed8 --- /dev/null +++ b/cpu/arm926ejs/davinci/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = timer.o ether.o lxt972.o dp83848.o i2c.o nand.o +SOBJS = lowlevel_init.o reset.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/davinci/dp83848.c b/cpu/arm926ejs/davinci/dp83848.c new file mode 100644 index 00000000000..5719845b340 --- /dev/null +++ b/cpu/arm926ejs/davinci/dp83848.c @@ -0,0 +1,156 @@ +/* + * National Semiconductor DP83848 PHY Driver for TI DaVinci + * (TMS320DM644x) based boards. + * + * Copyright (C) 2007 Sergey Kubushyn + * + * -------------------------------------------------------- + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifdef CONFIG_DRIVER_TI_EMAC + +#ifdef CONFIG_CMD_NET + +int dp83848_is_phy_connected(int phy_addr) +{ + u_int16_t id1, id2; + + if (!dm644x_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1)) + return(0); + if (!dm644x_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2)) + return(0); + + if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI)) + return(1); + + return(0); +} + +int dp83848_get_link_speed(int phy_addr) +{ + u_int16_t tmp; + volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR; + + if (!dm644x_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp)) + return(0); + + if (!(tmp & DP83848_LINK_STATUS)) /* link up? */ + return(0); + + if (!dm644x_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp)) + return(0); + + /* Speed doesn't matter, there is no setting for it in EMAC... */ + if (tmp & DP83848_SPEED) { + if (tmp & DP83848_DUPLEX) { + /* set DM644x EMAC for Full Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; + } else { + /*set DM644x EMAC for Half Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; + } + + return(1); + } else { + if (tmp & DP83848_DUPLEX) { + /* set DM644x EMAC for Full Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; + } else { + /*set DM644x EMAC for Half Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; + } + + return(1); + } + + return(0); +} + + +int dp83848_init_phy(int phy_addr) +{ + int ret = 1; + + if (!dp83848_get_link_speed(phy_addr)) { + /* Try another time */ + udelay(100000); + ret = dp83848_get_link_speed(phy_addr); + } + + /* Disable PHY Interrupts */ + dm644x_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0); + + return(ret); +} + + +int dp83848_auto_negotiate(int phy_addr) +{ + u_int16_t tmp; + + + if (!dm644x_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp)) + return(0); + + /* Restart Auto_negotiation */ + tmp &= ~DP83848_AUTONEG; /* remove autonegotiation enable */ + tmp |= DP83848_ISOLATE; /* Electrically isolate PHY */ + dm644x_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); + + /* Set the Auto_negotiation Advertisement Register + * MII advertising for Next page, 100BaseTxFD and HD, + * 10BaseTFD and HD, IEEE 802.3 + */ + tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX | + DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3; + dm644x_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp); + + + /* Read Control Register */ + if (!dm644x_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp)) + return(0); + + tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE; + dm644x_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); + + /* Restart Auto_negotiation */ + tmp |= DP83848_RESTART_AUTONEG; + dm644x_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); + + /*check AutoNegotiate complete */ + udelay(10000); + if (!dm644x_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp)) + return(0); + + if (!(tmp & DP83848_AUTONEG_COMP)) + return(0); + + return (dp83848_get_link_speed(phy_addr)); +} + +#endif /* CONFIG_CMD_NET */ + +#endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm926ejs/davinci/ether.c b/cpu/arm926ejs/davinci/ether.c new file mode 100644 index 00000000000..9ec1ee70bf7 --- /dev/null +++ b/cpu/arm926ejs/davinci/ether.c @@ -0,0 +1,652 @@ +/* + * Ethernet driver for TI TMS320DM644x (DaVinci) chips. + * + * Copyright (C) 2007 Sergey Kubushyn + * + * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright + * follows: + * + * ---------------------------------------------------------------------------- + * + * dm644x_emac.c + * + * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM + * + * Copyright (C) 2005 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + + * Modifications: + * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. + * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors + * + */ +#include +#include +#include +#include +#include + +#ifdef CONFIG_DRIVER_TI_EMAC + +#ifdef CONFIG_CMD_NET + +unsigned int emac_dbg = 0; +#define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) + +/* Internal static functions */ +static int dm644x_eth_hw_init (void); +static int dm644x_eth_open (void); +static int dm644x_eth_close (void); +static int dm644x_eth_send_packet (volatile void *packet, int length); +static int dm644x_eth_rcv_packet (void); +static void dm644x_eth_mdio_enable(void); + +static int gen_init_phy(int phy_addr); +static int gen_is_phy_connected(int phy_addr); +static int gen_get_link_speed(int phy_addr); +static int gen_auto_negotiate(int phy_addr); + +/* Wrappers exported to the U-Boot proper */ +int eth_hw_init(void) +{ + return(dm644x_eth_hw_init()); +} + +int eth_init(bd_t * bd) +{ + return(dm644x_eth_open()); +} + +void eth_halt(void) +{ + dm644x_eth_close(); +} + +int eth_send(volatile void *packet, int length) +{ + return(dm644x_eth_send_packet(packet, length)); +} + +int eth_rx(void) +{ + return(dm644x_eth_rcv_packet()); +} + +void eth_mdio_enable(void) +{ + dm644x_eth_mdio_enable(); +} +/* End of wrappers */ + + +static u_int8_t dm644x_eth_mac_addr[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + +/* + * This function must be called before emac_open() if you want to override + * the default mac address. + */ +void dm644x_eth_set_mac_addr(const u_int8_t *addr) +{ + int i; + + for (i = 0; i < sizeof (dm644x_eth_mac_addr); i++) { + dm644x_eth_mac_addr[i] = addr[i]; + } +} + +/* EMAC Addresses */ +static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; +static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; +static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR; + +/* EMAC descriptors */ +static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); +static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); +static volatile emac_desc *emac_rx_active_head = 0; +static volatile emac_desc *emac_rx_active_tail = 0; +static int emac_rx_queue_active = 0; + +/* Receive packet buffers */ +static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; + +/* PHY address for a discovered PHY (0xff - not found) */ +static volatile u_int8_t active_phy_addr = 0xff; + +phy_t phy; + +static void dm644x_eth_mdio_enable(void) +{ + u_int32_t clkdiv; + + clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + + adap_mdio->CONTROL = (clkdiv & 0xff) | + MDIO_CONTROL_ENABLE | + MDIO_CONTROL_FAULT | + MDIO_CONTROL_FAULT_ENABLE; + + while (adap_mdio->CONTROL & MDIO_CONTROL_IDLE) {;} +} + +/* + * Tries to find an active connected PHY. Returns 1 if address if found. + * If no active PHY (or more than one PHY) found returns 0. + * Sets active_phy_addr variable. + */ +static int dm644x_eth_phy_detect(void) +{ + u_int32_t phy_act_state; + int i; + + active_phy_addr = 0xff; + + if ((phy_act_state = adap_mdio->ALIVE) == 0) + return(0); /* No active PHYs */ + + debug_emac("dm644x_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); + + for (i = 0; i < 32; i++) { + if (phy_act_state & (1 << i)) { + if (phy_act_state & ~(1 << i)) + return(0); /* More than one PHY */ + else { + active_phy_addr = i; + return(1); + } + } + } + + return(0); /* Just to make GCC happy */ +} + + +/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ +int dm644x_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) +{ + int tmp; + + while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + + adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_READ | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16); + + /* Wait for command to complete */ + while ((tmp = adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) {;} + + if (tmp & MDIO_USERACCESS0_ACK) { + *data = tmp & 0xffff; + return(1); + } + + *data = -1; + return(0); +} + +/* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ +int dm644x_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) +{ + + while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + + adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_WRITE | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16) | + (data & 0xffff); + + /* Wait for command to complete */ + while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + + return(1); +} + +/* PHY functions for a generic PHY */ +static int gen_init_phy(int phy_addr) +{ + int ret = 1; + + if (gen_get_link_speed(phy_addr)) { + /* Try another time */ + ret = gen_get_link_speed(phy_addr); + } + + return(ret); +} + +static int gen_is_phy_connected(int phy_addr) +{ + u_int16_t dummy; + + return(dm644x_eth_phy_read(phy_addr, PHY_PHYIDR1, &dummy)); +} + +static int gen_get_link_speed(int phy_addr) +{ + u_int16_t tmp; + + if (dm644x_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && (tmp & 0x04)) + return(1); + + return(0); +} + +static int gen_auto_negotiate(int phy_addr) +{ + u_int16_t tmp; + + + if (!dm644x_eth_phy_read(phy_addr, PHY_BMCR, &tmp)) + return(0); + + /* Restart Auto_negotiation */ + tmp |= PHY_BMCR_AUTON; + dm644x_eth_phy_write(phy_addr, PHY_BMCR, tmp); + + /*check AutoNegotiate complete */ + udelay (10000); + if (!dm644x_eth_phy_read(phy_addr, PHY_BMSR, &tmp)) + return(0); + + if (!(tmp & PHY_BMSR_AUTN_COMP)) + return(0); + + return(gen_get_link_speed(phy_addr)); +} +/* End of generic PHY functions */ + + + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +static int dm644x_mii_phy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short *value) +{ + return(dm644x_eth_phy_read(addr, reg, value) ? 0 : 1); +} + +static int dm644x_mii_phy_write(char *devname, unsigned char addr, unsigned char reg, unsigned short value) +{ + return(dm644x_eth_phy_write(addr, reg, value) ? 0 : 1); +} + +int dm644x_eth_miiphy_initialize(bd_t *bis) +{ + miiphy_register(phy.name, dm644x_mii_phy_read, dm644x_mii_phy_write); + + return(1); +} +#endif + +/* + * This function initializes the emac hardware. It does NOT initialize + * EMAC modules power or pin multiplexors, that is done by board_init() + * much earlier in bootup process. Returns 1 on success, 0 otherwise. + */ +static int dm644x_eth_hw_init(void) +{ + u_int32_t phy_id; + u_int16_t tmp; + int i; + + dm644x_eth_mdio_enable(); + + for (i = 0; i < 256; i++) { + if (adap_mdio->ALIVE) + break; + udelay(10); + } + + if (i >= 256) { + printf("No ETH PHY detected!!!\n"); + return(0); + } + + /* Find if a PHY is connected and get it's address */ + if (!dm644x_eth_phy_detect()) + return(0); + + /* Get PHY ID and initialize phy_ops for a detected PHY */ + if (!dm644x_eth_phy_read(active_phy_addr, PHY_PHYIDR1, &tmp)) { + active_phy_addr = 0xff; + return(0); + } + + phy_id = (tmp << 16) & 0xffff0000; + + if (!dm644x_eth_phy_read(active_phy_addr, PHY_PHYIDR2, &tmp)) { + active_phy_addr = 0xff; + return(0); + } + + phy_id |= tmp & 0x0000ffff; + + switch (phy_id) { + case PHY_LXT972: + sprintf(phy.name, "LXT972 @ 0x%02x", active_phy_addr); + phy.init = lxt972_init_phy; + phy.is_phy_connected = lxt972_is_phy_connected; + phy.get_link_speed = lxt972_get_link_speed; + phy.auto_negotiate = lxt972_auto_negotiate; + break; + case PHY_DP83848: + sprintf(phy.name, "DP83848 @ 0x%02x", active_phy_addr); + phy.init = dp83848_init_phy; + phy.is_phy_connected = dp83848_is_phy_connected; + phy.get_link_speed = dp83848_get_link_speed; + phy.auto_negotiate = dp83848_auto_negotiate; + break; + default: + sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr); + phy.init = gen_init_phy; + phy.is_phy_connected = gen_is_phy_connected; + phy.get_link_speed = gen_get_link_speed; + phy.auto_negotiate = gen_auto_negotiate; + } + + return(1); +} + + +/* Eth device open */ +static int dm644x_eth_open(void) +{ + dv_reg_p addr; + u_int32_t clkdiv, cnt; + volatile emac_desc *rx_desc; + + debug_emac("+ emac_open\n"); + + /* Reset EMAC module and disable interrupts in wrapper */ + adap_emac->SOFTRESET = 1; + while (adap_emac->SOFTRESET != 0) {;} + adap_ewrap->EWCTL = 0; + for (cnt = 0; cnt < 5; cnt++) { + clkdiv = adap_ewrap->EWCTL; + } + + rx_desc = emac_rx_desc; + + adap_emac->TXCONTROL = 0x01; + adap_emac->RXCONTROL = 0x01; + + /* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast receive) */ + /* Using channel 0 only - other channels are disabled */ + adap_emac->MACINDEX = 0; + adap_emac->MACADDRHI = + (dm644x_eth_mac_addr[3] << 24) | + (dm644x_eth_mac_addr[2] << 16) | + (dm644x_eth_mac_addr[1] << 8) | + (dm644x_eth_mac_addr[0]); + adap_emac->MACADDRLO = + (dm644x_eth_mac_addr[5] << 8) | + (dm644x_eth_mac_addr[4]); + + adap_emac->MACHASH1 = 0; + adap_emac->MACHASH2 = 0; + + /* Set source MAC address - REQUIRED */ + adap_emac->MACSRCADDRHI = + (dm644x_eth_mac_addr[3] << 24) | + (dm644x_eth_mac_addr[2] << 16) | + (dm644x_eth_mac_addr[1] << 8) | + (dm644x_eth_mac_addr[0]); + adap_emac->MACSRCADDRLO = + (dm644x_eth_mac_addr[4] << 8) | + (dm644x_eth_mac_addr[5]); + + /* Set DMA 8 TX / 8 RX Head pointers to 0 */ + addr = &adap_emac->TX0HDP; + for(cnt = 0; cnt < 16; cnt++) + *addr++ = 0; + + addr = &adap_emac->RX0HDP; + for(cnt = 0; cnt < 16; cnt++) + *addr++ = 0; + + /* Clear Statistics (do this before setting MacControl register) */ + addr = &adap_emac->RXGOODFRAMES; + for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) + *addr++ = 0; + + /* No multicast addressing */ + adap_emac->MACHASH1 = 0; + adap_emac->MACHASH2 = 0; + + /* Create RX queue and set receive process in place */ + emac_rx_active_head = emac_rx_desc; + for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { + rx_desc->next = (u_int32_t)(rx_desc + 1); + rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; + rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; + rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; + rx_desc++; + } + + /* Set the last descriptor's "next" parameter to 0 to end the RX desc list */ + rx_desc--; + rx_desc->next = 0; + emac_rx_active_tail = rx_desc; + emac_rx_queue_active = 1; + + /* Enable TX/RX */ + adap_emac->RXMAXLEN = EMAC_MAX_ETHERNET_PKT_SIZE; + adap_emac->RXBUFFEROFFSET = 0; + + /* No fancy configs - Use this for promiscous for debug - EMAC_RXMBPENABLE_RXCAFEN_ENABLE */ + adap_emac->RXMBPENABLE = EMAC_RXMBPENABLE_RXBROADEN; + + /* Enable ch 0 only */ + adap_emac->RXUNICASTSET = 0x01; + + /* Enable MII interface and Full duplex mode */ + adap_emac->MACCONTROL = (EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE); + + /* Init MDIO & get link state */ + clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + adap_mdio->CONTROL = ((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT); + + if (!phy.get_link_speed(active_phy_addr)) + return(0); + + /* Start receive process */ + adap_emac->RX0HDP = (u_int32_t)emac_rx_desc; + + debug_emac("- emac_open\n"); + + return(1); +} + +/* EMAC Channel Teardown */ +static void dm644x_eth_ch_teardown(int ch) +{ + dv_reg dly = 0xff; + dv_reg cnt; + + debug_emac("+ emac_ch_teardown\n"); + + if (ch == EMAC_CH_TX) { + /* Init TX channel teardown */ + adap_emac->TXTEARDOWN = 1; + for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->TX0CP) { + /* Wait here for Tx teardown completion interrupt to occur + * Note: A task delay can be called here to pend rather than + * occupying CPU cycles - anyway it has been found that teardown + * takes very few cpu cycles and does not affect functionality */ + dly--; + udelay(1); + if (dly == 0) + break; + } + adap_emac->TX0CP = cnt; + adap_emac->TX0HDP = 0; + } else { + /* Init RX channel teardown */ + adap_emac->RXTEARDOWN = 1; + for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->RX0CP) { + /* Wait here for Rx teardown completion interrupt to occur + * Note: A task delay can be called here to pend rather than + * occupying CPU cycles - anyway it has been found that teardown + * takes very few cpu cycles and does not affect functionality */ + dly--; + udelay(1); + if (dly == 0) + break; + } + adap_emac->RX0CP = cnt; + adap_emac->RX0HDP = 0; + } + + debug_emac("- emac_ch_teardown\n"); +} + +/* Eth device close */ +static int dm644x_eth_close(void) +{ + debug_emac("+ emac_close\n"); + + dm644x_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ + dm644x_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ + + /* Reset EMAC module and disable interrupts in wrapper */ + adap_emac->SOFTRESET = 1; + adap_ewrap->EWCTL = 0; + + debug_emac("- emac_close\n"); + return(1); +} + +static int tx_send_loop = 0; + +/* + * This function sends a single packet on the network and returns + * positive number (number of bytes transmitted) or negative for error + */ +static int dm644x_eth_send_packet(volatile void *packet, int length) +{ + int ret_status = -1; + tx_send_loop = 0; + + /* Return error if no link */ + if (!phy.get_link_speed(active_phy_addr)) + { + printf("WARN: emac_send_packet: No link\n"); + return (ret_status); + } + + /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ + if (length < EMAC_MIN_ETHERNET_PKT_SIZE) + { + length = EMAC_MIN_ETHERNET_PKT_SIZE; + } + + /* Populate the TX descriptor */ + emac_tx_desc->next = 0; + emac_tx_desc->buffer = (u_int8_t *)packet; + emac_tx_desc->buff_off_len = (length & 0xffff); + emac_tx_desc->pkt_flag_len = ((length & 0xffff) | + EMAC_CPPI_SOP_BIT | + EMAC_CPPI_OWNERSHIP_BIT | + EMAC_CPPI_EOP_BIT); + /* Send the packet */ + adap_emac->TX0HDP = (unsigned int)emac_tx_desc; + + /* Wait for packet to complete or link down */ + while (1) { + if (!phy.get_link_speed(active_phy_addr)) { + dm644x_eth_ch_teardown(EMAC_CH_TX); + return (ret_status); + } + if (adap_emac->TXINTSTATRAW & 0x01) { + ret_status = length; + break; + } + tx_send_loop++; + } + + return(ret_status); +} + +/* + * This function handles receipt of a packet from the network + */ +static int dm644x_eth_rcv_packet(void) +{ + volatile emac_desc *rx_curr_desc; + volatile emac_desc *curr_desc; + volatile emac_desc *tail_desc; + int status, ret = -1; + + rx_curr_desc = emac_rx_active_head; + status = rx_curr_desc->pkt_flag_len; + if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { + if (status & EMAC_CPPI_RX_ERROR_FRAME) { + /* Error in packet - discard it and requeue desc */ + printf("WARN: emac_rcv_pkt: Error in packet\n"); + } else { + NetReceive(rx_curr_desc->buffer, (rx_curr_desc->buff_off_len & 0xffff)); + ret = rx_curr_desc->buff_off_len & 0xffff; + } + + /* Ack received packet descriptor */ + adap_emac->RX0CP = (unsigned int)rx_curr_desc; + curr_desc = rx_curr_desc; + emac_rx_active_head = (volatile emac_desc *)rx_curr_desc->next; + + if (status & EMAC_CPPI_EOQ_BIT) { + if (emac_rx_active_head) { + adap_emac->RX0HDP = (unsigned int)emac_rx_active_head; + } else { + emac_rx_queue_active = 0; + printf("INFO:emac_rcv_packet: RX Queue not active\n"); + } + } + + /* Recycle RX descriptor */ + rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; + rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; + rx_curr_desc->next = 0; + + if (emac_rx_active_head == 0) { + printf("INFO: emac_rcv_pkt: active queue head = 0\n"); + emac_rx_active_head = curr_desc; + emac_rx_active_tail = curr_desc; + if (emac_rx_queue_active != 0) { + adap_emac->RX0HDP = (unsigned int)emac_rx_active_head; + printf("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); + emac_rx_queue_active = 1; + } + } else { + tail_desc = emac_rx_active_tail; + emac_rx_active_tail = curr_desc; + tail_desc->next = (unsigned int)curr_desc; + status = tail_desc->pkt_flag_len; + if (status & EMAC_CPPI_EOQ_BIT) { + adap_emac->RX0HDP = (unsigned int)curr_desc; + status &= ~EMAC_CPPI_EOQ_BIT; + tail_desc->pkt_flag_len = status; + } + } + return(ret); + } + return(0); +} + +#endif /* CONFIG_CMD_NET */ + +#endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/cpu/arm926ejs/davinci/i2c.c b/cpu/arm926ejs/davinci/i2c.c new file mode 100644 index 00000000000..af9dc034c2a --- /dev/null +++ b/cpu/arm926ejs/davinci/i2c.c @@ -0,0 +1,351 @@ +/* + * TI DaVinci (TMS320DM644x) I2C driver. + * + * Copyright (C) 2007 Sergey Kubushyn + * + * -------------------------------------------------------- + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_DRIVER_DAVINCI_I2C + +#include +#include +#include + +#define CHECK_NACK() \ + do {\ + if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\ + REG(I2C_CON) = 0;\ + return(1);\ + }\ + } while (0) + + +static int wait_for_bus(void) +{ + int stat, timeout; + + REG(I2C_STAT) = 0xffff; + + for (timeout = 0; timeout < 10; timeout++) { + if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) { + REG(I2C_STAT) = 0xffff; + return(0); + } + + REG(I2C_STAT) = stat; + udelay(50000); + } + + REG(I2C_STAT) = 0xffff; + return(1); +} + + +static int poll_i2c_irq(int mask) +{ + int stat, timeout; + + for (timeout = 0; timeout < 10; timeout++) { + udelay(1000); + stat = REG(I2C_STAT); + if (stat & mask) { + return(stat); + } + } + + REG(I2C_STAT) = 0xffff; + return(stat | I2C_TIMEOUT); +} + + +void flush_rx(void) +{ + int dummy; + + while (1) { + if (!(REG(I2C_STAT) & I2C_STAT_RRDY)) + break; + + dummy = REG(I2C_DRR); + REG(I2C_STAT) = I2C_STAT_RRDY; + udelay(1000); + } +} + + +void i2c_init(int speed, int slaveadd) +{ + u_int32_t div, psc; + + if (REG(I2C_CON) & I2C_CON_EN) { + REG(I2C_CON) = 0; + udelay (50000); + } + + psc = 2; + div = (CFG_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */ + REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */ + REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */ + REG(I2C_SCLH) = div - REG(I2C_SCLL); + + REG(I2C_OA) = slaveadd; + REG(I2C_CNT) = 0; + + /* Interrupts must be enabled or I2C module won't work */ + REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE | + I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE; + + /* Now enable I2C controller (get it out of reset) */ + REG(I2C_CON) = I2C_CON_EN; + + udelay(1000); +} + + +int i2c_probe(u_int8_t chip) +{ + int rc = 1; + + if (chip == REG(I2C_OA)) { + return(rc); + } + + REG(I2C_CON) = 0; + if (wait_for_bus()) {return(1);} + + /* try to read one byte from current (or only) address */ + REG(I2C_CNT) = 1; + REG(I2C_SA) = chip; + REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP); + udelay (50000); + + if (!(REG(I2C_STAT) & I2C_STAT_NACK)) { + rc = 0; + flush_rx(); + REG(I2C_STAT) = 0xffff; + } else { + REG(I2C_STAT) = 0xffff; + REG(I2C_CON) |= I2C_CON_STP; + udelay(20000); + if (wait_for_bus()) {return(1);} + } + + flush_rx(); + REG(I2C_STAT) = 0xffff; + REG(I2C_CNT) = 0; + return(rc); +} + + +int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) +{ + u_int32_t tmp; + int i; + + if ((alen < 0) || (alen > 2)) { + printf("%s(): bogus address length %x\n", __FUNCTION__, alen); + return(1); + } + + if (wait_for_bus()) {return(1);} + + if (alen != 0) { + /* Start address phase */ + tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX; + REG(I2C_CNT) = alen; + REG(I2C_SA) = chip; + REG(I2C_CON) = tmp; + + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + + switch (alen) { + case 2: + /* Send address MSByte */ + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = (addr >> 8) & 0xff; + } else { + REG(I2C_CON) = 0; + return(1); + } + + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + /* No break, fall through */ + case 1: + /* Send address LSByte */ + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = addr & 0xff; + } else { + REG(I2C_CON) = 0; + return(1); + } + + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY); + + CHECK_NACK(); + + if (!(tmp & I2C_STAT_ARDY)) { + REG(I2C_CON) = 0; + return(1); + } + } + } + + /* Address phase is over, now read 'len' bytes and stop */ + tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP; + REG(I2C_CNT) = len & 0xffff; + REG(I2C_SA) = chip; + REG(I2C_CON) = tmp; + + for (i = 0; i < len; i++) { + tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR); + + CHECK_NACK(); + + if (tmp & I2C_STAT_RRDY) { + buf[i] = REG(I2C_DRR); + } else { + REG(I2C_CON) = 0; + return(1); + } + } + + tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); + + CHECK_NACK(); + + if (!(tmp & I2C_STAT_SCD)) { + REG(I2C_CON) = 0; + return(1); + } + + flush_rx(); + REG(I2C_STAT) = 0xffff; + REG(I2C_CNT) = 0; + REG(I2C_CON) = 0; + + return(0); +} + + +int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) +{ + u_int32_t tmp; + int i; + + if ((alen < 0) || (alen > 2)) { + printf("%s(): bogus address length %x\n", __FUNCTION__, alen); + return(1); + } + if (len < 0) { + printf("%s(): bogus length %x\n", __FUNCTION__, len); + return(1); + } + + if (wait_for_bus()) {return(1);} + + /* Start address phase */ + tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP; + REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen; + REG(I2C_SA) = chip; + REG(I2C_CON) = tmp; + + switch (alen) { + case 2: + /* Send address MSByte */ + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = (addr >> 8) & 0xff; + } else { + REG(I2C_CON) = 0; + return(1); + } + /* No break, fall through */ + case 1: + /* Send address LSByte */ + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = addr & 0xff; + } else { + REG(I2C_CON) = 0; + return(1); + } + } + + for (i = 0; i < len; i++) { + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = buf[i]; + } else { + return(1); + } + } + + tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); + + CHECK_NACK(); + + if (!(tmp & I2C_STAT_SCD)) { + REG(I2C_CON) = 0; + return(1); + } + + flush_rx(); + REG(I2C_STAT) = 0xffff; + REG(I2C_CNT) = 0; + REG(I2C_CON) = 0; + + return(0); +} + + +u_int8_t i2c_reg_read(u_int8_t chip, u_int8_t reg) +{ + u_int8_t tmp; + + i2c_read(chip, reg, 1, &tmp, 1); + return(tmp); +} + + +void i2c_reg_write(u_int8_t chip, u_int8_t reg, u_int8_t val) +{ + u_int8_t tmp; + + i2c_write(chip, reg, 1, &tmp, 1); +} + +#endif /* CONFIG_DRIVER_DAVINCI_I2C */ diff --git a/cpu/arm926ejs/davinci/lowlevel_init.S b/cpu/arm926ejs/davinci/lowlevel_init.S new file mode 100644 index 00000000000..bbc48ec4725 --- /dev/null +++ b/cpu/arm926ejs/davinci/lowlevel_init.S @@ -0,0 +1,707 @@ +/* + * Low-level board setup code for TI DaVinci SoC based boards. + * + * Copyright (C) 2007 Sergey Kubushyn + * + * Partially based on TI sources, original copyrights follow: + */ + +/* + * Board specific setup info + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 + * + * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004 + * See file CREDITS for list of people who contributed to this + * project. + * + * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005 + * See file CREDITS for list of people who contributed to this + * project. + * + * Modified for DV-EVM board by Swaminathan S, Nov 2005 + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +.globl lowlevel_init +lowlevel_init: + + /*-------------------------------------------------------* + * Mask all IRQs by setting all bits in the EINT default * + *-------------------------------------------------------*/ + mov r1, $0 + ldr r0, =EINT_ENABLE0 + str r1, [r0] + ldr r0, =EINT_ENABLE1 + str r1, [r0] + + /*------------------------------------------------------* + * Put the GEM in reset * + *------------------------------------------------------*/ + + /* Put the GEM in reset */ + ldr r8, PSC_GEM_FLAG_CLEAR + ldr r6, MDCTL_GEM + ldr r7, [r6] + and r7, r7, r8 + str r7, [r6] + + /* Enable the Power Domain Transition Command */ + ldr r6, PTCMD + ldr r7, [r6] + orr r7, r7, $0x02 + str r7, [r6] + + /* Check for Transition Complete(PTSTAT) */ +checkStatClkStopGem: + ldr r6, PTSTAT + ldr r7, [r6] + ands r7, r7, $0x02 + bne checkStatClkStopGem + + /* Check for GEM Reset Completion */ +checkGemStatClkStop: + ldr r6, MDSTAT_GEM + ldr r7, [r6] + ands r7, r7, $0x100 + bne checkGemStatClkStop + + /* Do this for enabling a WDT initiated reset this is a workaround + for a chip bug. Not required under normal situations */ + ldr r6, P1394 + mov r10, $0 + str r10, [r6] + + /*------------------------------------------------------* + * Enable L1 & L2 Memories in Fast mode * + *------------------------------------------------------*/ + ldr r6, DFT_ENABLE + mov r10, $0x01 + str r10, [r6] + + ldr r6, MMARG_BRF0 + ldr r10, MMARG_BRF0_VAL + str r10, [r6] + + ldr r6, DFT_ENABLE + mov r10, $0 + str r10, [r6] + + /*------------------------------------------------------* + * DDR2 PLL Initialization * + *------------------------------------------------------*/ + + /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */ + mov r10, $0 + ldr r6, PLL2_CTL + ldr r7, PLL_CLKSRC_MASK + ldr r8, [r6] + and r8, r8, r7 + mov r9, r10, lsl $8 + orr r8, r8, r9 + str r8, [r6] + + /* Select the PLLEN source */ + ldr r7, PLL_ENSRC_MASK + and r8, r8, r7 + str r8, [r6] + + /* Bypass the PLL */ + ldr r7, PLL_BYPASS_MASK + and r8, r8, r7 + str r8, [r6] + + /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */ + mov r10, $0x20 +WaitPPL2Loop: + subs r10, r10, $1 + bne WaitPPL2Loop + + /* Reset the PLL */ + ldr r7, PLL_RESET_MASK + and r8, r8, r7 + str r8, [r6] + + /* Power up the PLL */ + ldr r7, PLL_PWRUP_MASK + and r8, r8, r7 + str r8, [r6] + + /* Enable the PLL from Disable Mode */ + ldr r7, PLL_DISABLE_ENABLE_MASK + and r8, r8, r7 + str r8, [r6] + + /* Program the PLL Multiplier */ + ldr r6, PLL2_PLLM + mov r2, $0x17 /* 162 MHz */ + str r2, [r6] + + /* Program the PLL2 Divisor Value */ + ldr r6, PLL2_DIV2 + mov r3, $0x01 + str r3, [r6] + + /* Program the PLL2 Divisor Value */ + ldr r6, PLL2_DIV1 + mov r4, $0x0b /* 54 MHz */ + str r4, [r6] + + /* PLL2 DIV2 MMR */ + ldr r8, PLL2_DIV_MASK + ldr r6, PLL2_DIV2 + ldr r9, [r6] + and r8, r8, r9 + mov r9, $0x01 + mov r9, r9, lsl $15 + orr r8, r8, r9 + str r8, [r6] + + /* Program the GOSET bit to take new divider values */ + ldr r6, PLL2_PLLCMD + ldr r7, [r6] + orr r7, r7, $0x01 + str r7, [r6] + + /* Wait for Done */ + ldr r6, PLL2_PLLSTAT +doneLoop_0: + ldr r7, [r6] + ands r7, r7, $0x01 + bne doneLoop_0 + + /* PLL2 DIV1 MMR */ + ldr r8, PLL2_DIV_MASK + ldr r6, PLL2_DIV1 + ldr r9, [r6] + and r8, r8, r9 + mov r9, $0x01 + mov r9, r9, lsl $15 + orr r8, r8, r9 + str r8, [r6] + + /* Program the GOSET bit to take new divider values */ + ldr r6, PLL2_PLLCMD + ldr r7, [r6] + orr r7, r7, $0x01 + str r7, [r6] + + /* Wait for Done */ + ldr r6, PLL2_PLLSTAT +doneLoop: + ldr r7, [r6] + ands r7, r7, $0x01 + bne doneLoop + + /* Wait for PLL to Reset Properly */ + mov r10, $0x218 +ResetPPL2Loop: + subs r10, r10, $1 + bne ResetPPL2Loop + + /* Bring PLL out of Reset */ + ldr r6, PLL2_CTL + ldr r8, [r6] + orr r8, r8, $0x08 + str r8, [r6] + + /* Wait for PLL to Lock */ + ldr r10, PLL_LOCK_COUNT +PLL2Lock: + subs r10, r10, $1 + bne PLL2Lock + + /* Enable the PLL */ + ldr r6, PLL2_CTL + ldr r8, [r6] + orr r8, r8, $0x01 + str r8, [r6] + + /*------------------------------------------------------* + * Issue Soft Reset to DDR Module * + *------------------------------------------------------*/ + + /* Shut down the DDR2 LPSC Module */ + ldr r8, PSC_FLAG_CLEAR + ldr r6, MDCTL_DDR2 + ldr r7, [r6] + and r7, r7, r8 + orr r7, r7, $0x03 + str r7, [r6] + + /* Enable the Power Domain Transition Command */ + ldr r6, PTCMD + ldr r7, [r6] + orr r7, r7, $0x01 + str r7, [r6] + + /* Check for Transition Complete(PTSTAT) */ +checkStatClkStop: + ldr r6, PTSTAT + ldr r7, [r6] + ands r7, r7, $0x01 + bne checkStatClkStop + + /* Check for DDR2 Controller Enable Completion */ +checkDDRStatClkStop: + ldr r6, MDSTAT_DDR2 + ldr r7, [r6] + and r7, r7, $0x1f + cmp r7, $0x03 + bne checkDDRStatClkStop + + /*------------------------------------------------------* + * Program DDR2 MMRs for 162MHz Setting * + *------------------------------------------------------*/ + + /* Program PHY Control Register */ + ldr r6, DDRCTL + ldr r7, DDRCTL_VAL + str r7, [r6] + + /* Program SDRAM Bank Config Register */ + ldr r6, SDCFG + ldr r7, SDCFG_VAL + str r7, [r6] + + /* Program SDRAM TIM-0 Config Register */ + ldr r6, SDTIM0 + ldr r7, SDTIM0_VAL_162MHz + str r7, [r6] + + /* Program SDRAM TIM-1 Config Register */ + ldr r6, SDTIM1 + ldr r7, SDTIM1_VAL_162MHz + str r7, [r6] + + /* Program the SDRAM Bank Config Control Register */ + ldr r10, MASK_VAL + ldr r8, SDCFG + ldr r9, SDCFG_VAL + and r9, r9, r10 + str r9, [r8] + + /* Program SDRAM SDREF Config Register */ + ldr r6, SDREF + ldr r7, SDREF_VAL + str r7, [r6] + + /*------------------------------------------------------* + * Issue Soft Reset to DDR Module * + *------------------------------------------------------*/ + + /* Issue a Dummy DDR2 read/write */ + ldr r8, DDR2_START_ADDR + ldr r7, DUMMY_VAL + str r7, [r8] + ldr r7, [r8] + + /* Shut down the DDR2 LPSC Module */ + ldr r8, PSC_FLAG_CLEAR + ldr r6, MDCTL_DDR2 + ldr r7, [r6] + and r7, r7, r8 + orr r7, r7, $0x01 + str r7, [r6] + + /* Enable the Power Domain Transition Command */ + ldr r6, PTCMD + ldr r7, [r6] + orr r7, r7, $0x01 + str r7, [r6] + + /* Check for Transition Complete(PTSTAT) */ +checkStatClkStop2: + ldr r6, PTSTAT + ldr r7, [r6] + ands r7, r7, $0x01 + bne checkStatClkStop2 + + /* Check for DDR2 Controller Enable Completion */ +checkDDRStatClkStop2: + ldr r6, MDSTAT_DDR2 + ldr r7, [r6] + and r7, r7, $0x1f + cmp r7, $0x01 + bne checkDDRStatClkStop2 + + /*------------------------------------------------------* + * Turn DDR2 Controller Clocks On * + *------------------------------------------------------*/ + + /* Enable the DDR2 LPSC Module */ + ldr r6, MDCTL_DDR2 + ldr r7, [r6] + orr r7, r7, $0x03 + str r7, [r6] + + /* Enable the Power Domain Transition Command */ + ldr r6, PTCMD + ldr r7, [r6] + orr r7, r7, $0x01 + str r7, [r6] + + /* Check for Transition Complete(PTSTAT) */ +checkStatClkEn2: + ldr r6, PTSTAT + ldr r7, [r6] + ands r7, r7, $0x01 + bne checkStatClkEn2 + + /* Check for DDR2 Controller Enable Completion */ +checkDDRStatClkEn2: + ldr r6, MDSTAT_DDR2 + ldr r7, [r6] + and r7, r7, $0x1f + cmp r7, $0x03 + bne checkDDRStatClkEn2 + + /* DDR Writes and Reads */ + ldr r6, CFGTEST + mov r3, $0x01 + str r3, [r6] + + /*------------------------------------------------------* + * System PLL Initialization * + *------------------------------------------------------*/ + + /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */ + mov r2, $0 + ldr r6, PLL1_CTL + ldr r7, PLL_CLKSRC_MASK + ldr r8, [r6] + and r8, r8, r7 + mov r9, r2, lsl $8 + orr r8, r8, r9 + str r8, [r6] + + /* Select the PLLEN source */ + ldr r7, PLL_ENSRC_MASK + and r8, r8, r7 + str r8, [r6] + + /* Bypass the PLL */ + ldr r7, PLL_BYPASS_MASK + and r8, r8, r7 + str r8, [r6] + + /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */ + mov r10, $0x20 + +WaitLoop: + subs r10, r10, $1 + bne WaitLoop + + /* Reset the PLL */ + ldr r7, PLL_RESET_MASK + and r8, r8, r7 + str r8, [r6] + + /* Disable the PLL */ + orr r8, r8, $0x10 + str r8, [r6] + + /* Power up the PLL */ + ldr r7, PLL_PWRUP_MASK + and r8, r8, r7 + str r8, [r6] + + /* Enable the PLL from Disable Mode */ + ldr r7, PLL_DISABLE_ENABLE_MASK + and r8, r8, r7 + str r8, [r6] + + /* Program the PLL Multiplier */ + ldr r6, PLL1_PLLM + mov r3, $0x15 /* For 594MHz */ + str r3, [r6] + + /* Wait for PLL to Reset Properly */ + mov r10, $0xff + +ResetLoop: + subs r10, r10, $1 + bne ResetLoop + + /* Bring PLL out of Reset */ + ldr r6, PLL1_CTL + orr r8, r8, $0x08 + str r8, [r6] + + /* Wait for PLL to Lock */ + ldr r10, PLL_LOCK_COUNT + +PLL1Lock: + subs r10, r10, $1 + bne PLL1Lock + + /* Enable the PLL */ + orr r8, r8, $0x01 + str r8, [r6] + + nop + nop + nop + nop + + /*------------------------------------------------------* + * AEMIF configuration for NOR Flash (double check) * + *------------------------------------------------------*/ + ldr r0, _PINMUX0 + ldr r1, _DEV_SETTING + str r1, [r0] + + ldr r0, WAITCFG + ldr r1, WAITCFG_VAL + ldr r2, [r0] + orr r2, r2, r1 + str r2, [r0] + + ldr r0, ACFG3 + ldr r1, ACFG3_VAL + ldr r2, [r0] + and r1, r2, r1 + str r1, [r0] + + ldr r0, ACFG4 + ldr r1, ACFG4_VAL + ldr r2, [r0] + and r1, r2, r1 + str r1, [r0] + + ldr r0, ACFG5 + ldr r1, ACFG5_VAL + ldr r2, [r0] + and r1, r2, r1 + str r1, [r0] + + /*--------------------------------------* + * VTP manual Calibration * + *--------------------------------------*/ + ldr r0, VTPIOCR + ldr r1, VTP_MMR0 + str r1, [r0] + + ldr r0, VTPIOCR + ldr r1, VTP_MMR1 + str r1, [r0] + + /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */ + ldr r10, VTP_LOCK_COUNT +VTPLock: + subs r10, r10, $1 + bne VTPLock + + ldr r6, DFT_ENABLE + mov r10, $0x01 + str r10, [r6] + + ldr r6, DDRVTPR + ldr r7, [r6] + and r7, r7, $0x1f + and r8, r7, $0x3e0 + orr r8, r7, r8 + ldr r7, VTP_RECAL + orr r8, r7, r8 + ldr r7, VTP_EN + orr r8, r7, r8 + str r8, [r0] + + + /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */ + ldr r10, VTP_LOCK_COUNT +VTP1Lock: + subs r10, r10, $1 + bne VTP1Lock + + ldr r1, [r0] + ldr r2, VTP_MASK + and r2, r1, r2 + str r2, [r0] + + ldr r6, DFT_ENABLE + mov r10, $0 + str r10, [r6] + + /* + * Call board-specific lowlevel init. + * That MUST be present and THAT returns + * back to arch calling code with "mov pc, lr." + */ + b dv_board_init + +.ltorg + +_PINMUX0: + .word 0x01c40000 /* Device Configuration Registers */ +_PINMUX1: + .word 0x01c40004 /* Device Configuration Registers */ + +_DEV_SETTING: + .word 0x00000c1f + +WAITCFG: + .word 0x01e00004 +WAITCFG_VAL: + .word 0 +ACFG3: + .word 0x01e00014 +ACFG3_VAL: + .word 0x3ffffffd +ACFG4: + .word 0x01e00018 +ACFG4_VAL: + .word 0x3ffffffd +ACFG5: + .word 0x01e0001c +ACFG5_VAL: + .word 0x3ffffffd + +MDCTL_DDR2: + .word 0x01c41a34 +MDSTAT_DDR2: + .word 0x01c41834 + +PTCMD: + .word 0x01c41120 +PTSTAT: + .word 0x01c41128 + +EINT_ENABLE0: + .word 0x01c48018 +EINT_ENABLE1: + .word 0x01c4801c + +PSC_FLAG_CLEAR: + .word 0xffffffe0 +PSC_GEM_FLAG_CLEAR: + .word 0xfffffeff + +/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */ +DDRCTL: + .word 0x200000e4 +DDRCTL_VAL: + .word 0x50006405 +SDREF: + .word 0x2000000c +SDREF_VAL: + .word 0x000005c3 +SDCFG: + .word 0x20000008 +SDCFG_VAL: +#ifdef DDR_4BANKS + .word 0x00178622 +#elif defined DDR_8BANKS + .word 0x00178632 +#else +#error "Unknown DDR configuration!!!" +#endif +SDTIM0: + .word 0x20000010 +SDTIM0_VAL_162MHz: + .word 0x28923211 +SDTIM1: + .word 0x20000014 +SDTIM1_VAL_162MHz: + .word 0x0016c722 +VTPIOCR: + .word 0x200000f0 /* VTP IO Control register */ +DDRVTPR: + .word 0x01c42030 /* DDR VPTR MMR */ +VTP_MMR0: + .word 0x201f +VTP_MMR1: + .word 0xa01f +DFT_ENABLE: + .word 0x01c4004c +VTP_LOCK_COUNT: + .word 0x5b0 +VTP_MASK: + .word 0xffffdfff +VTP_RECAL: + .word 0x40000 +VTP_EN: + .word 0x02000 +CFGTEST: + .word 0x80010000 +MASK_VAL: + .word 0x00000fff + +/* GEM Power Up & LPSC Control Register */ +MDCTL_GEM: + .word 0x01c41a9c +MDSTAT_GEM: + .word 0x01c4189c + +/* For WDT reset chip bug */ +P1394: + .word 0x01c41a20 + +PLL_CLKSRC_MASK: + .word 0xfffffeff /* Mask the Clock Mode bit */ +PLL_ENSRC_MASK: + .word 0xffffffdf /* Select the PLLEN source */ +PLL_BYPASS_MASK: + .word 0xfffffffe /* Put the PLL in BYPASS */ +PLL_RESET_MASK: + .word 0xfffffff7 /* Put the PLL in Reset Mode */ +PLL_PWRUP_MASK: + .word 0xfffffffd /* PLL Power up Mask Bit */ +PLL_DISABLE_ENABLE_MASK: + .word 0xffffffef /* Enable the PLL from Disable */ +PLL_LOCK_COUNT: + .word 0x2000 + +/* PLL1-SYSTEM PLL MMRs */ +PLL1_CTL: + .word 0x01c40900 +PLL1_PLLM: + .word 0x01c40910 + +/* PLL2-SYSTEM PLL MMRs */ +PLL2_CTL: + .word 0x01c40d00 +PLL2_PLLM: + .word 0x01c40d10 +PLL2_DIV1: + .word 0x01c40d18 +PLL2_DIV2: + .word 0x01c40d1c +PLL2_PLLCMD: + .word 0x01c40d38 +PLL2_PLLSTAT: + .word 0x01c40d3c +PLL2_DIV_MASK: + .word 0xffff7fff + +MMARG_BRF0: + .word 0x01c42010 /* BRF margin mode 0 (R/W)*/ +MMARG_BRF0_VAL: + .word 0x00444400 + +DDR2_START_ADDR: + .word 0x80000000 +DUMMY_VAL: + .word 0xa55aa55a diff --git a/cpu/arm926ejs/davinci/lxt972.c b/cpu/arm926ejs/davinci/lxt972.c new file mode 100644 index 00000000000..6eeb6e5ee92 --- /dev/null +++ b/cpu/arm926ejs/davinci/lxt972.c @@ -0,0 +1,142 @@ +/* + * Intel LXT971/LXT972 PHY Driver for TI DaVinci + * (TMS320DM644x) based boards. + * + * Copyright (C) 2007 Sergey Kubushyn + * + * -------------------------------------------------------- + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifdef CONFIG_DRIVER_TI_EMAC + +#ifdef CONFIG_CMD_NET + +int lxt972_is_phy_connected(int phy_addr) +{ + u_int16_t id1, id2; + + if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_ID1, &id1)) + return(0); + if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_ID2, &id2)) + return(0); + + if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0)) + return(1); + + return(0); +} + +int lxt972_get_link_speed(int phy_addr) +{ + u_int16_t stat1, tmp; + volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR; + + if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1)) + return(0); + + if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link up? */ + return(0); + + if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp)) + return(0); + + tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE; + + dm644x_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp); + /* Read back */ + if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp)) + return(0); + + + /* Speed doesn't matter, there is no setting for it in EMAC... */ + if (stat1 & PHY_LXT971_STAT2_100BTX) { + if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { + /* set DM644x EMAC for Full Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; + } else { + /*set DM644x EMAC for Half Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; + } + + return(1); + } else { + if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { + /* set DM644x EMAC for Full Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; + } else { + /*set DM644x EMAC for Half Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; + } + + return(1); + } + + return(0); +} + + +int lxt972_init_phy(int phy_addr) +{ + int ret = 1; + + if (!lxt972_get_link_speed(phy_addr)) { + /* Try another time */ + ret = lxt972_get_link_speed(phy_addr); + } + + /* Disable PHY Interrupts */ + dm644x_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0); + + return(ret); +} + + +int lxt972_auto_negotiate(int phy_addr) +{ + u_int16_t tmp; + + + if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_CTRL, &tmp)) + return(0); + + /* Restart Auto_negotiation */ + tmp |= PHY_COMMON_CTRL_RES_AUTO; + dm644x_eth_phy_write(phy_addr, PHY_COMMON_CTRL, tmp); + + /*check AutoNegotiate complete */ + udelay (10000); + if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_STAT, &tmp)) + return(0); + + if (!(tmp & PHY_COMMON_STAT_AN_COMP)) + return(0); + + return (lxt972_get_link_speed(phy_addr)); +} + +#endif /* CONFIG_CMD_NET */ + +#endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c new file mode 100644 index 00000000000..127be9fcd43 --- /dev/null +++ b/cpu/arm926ejs/davinci/nand.c @@ -0,0 +1,389 @@ +/* + * NAND driver for TI DaVinci based boards. + * + * Copyright (C) 2007 Sergey Kubushyn + * + * Based on Linux DaVinci NAND driver by TI. Original copyright follows: + */ + +/* + * + * linux/drivers/mtd/nand/nand_davinci.c + * + * NAND Flash Driver + * + * Copyright (C) 2006 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + * + * Overview: + * This is a device driver for the NAND flash device found on the + * DaVinci board which utilizes the Samsung k9k2g08 part. + * + Modifications: + ver. 1.0: Feb 2005, Vinod/Sudhakar + - + * + */ + +#include + +#ifdef CFG_USE_NAND +#if !defined(CFG_NAND_LEGACY) + +#include +#include +#include + +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W; + + IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); + + switch (cmd) { + case NAND_CTL_SETCLE: + IO_ADDR_W |= MASK_CLE; + break; + case NAND_CTL_SETALE: + IO_ADDR_W |= MASK_ALE; + break; + } + + this->IO_ADDR_W = (void *)IO_ADDR_W; +} + +/* Set WP on deselect, write enable on select */ +static void nand_davinci_select_chip(struct mtd_info *mtd, int chip) +{ +#define GPIO_SET_DATA01 0x01c67018 +#define GPIO_CLR_DATA01 0x01c6701c +#define GPIO_NAND_WP (1 << 4) +#ifdef SONATA_BOARD_GPIOWP + if (chip < 0) { + REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP; + } else { + REG(GPIO_SET_DATA01) |= GPIO_NAND_WP; + } +#endif +} + +#ifdef CFG_NAND_HW_ECC +#ifdef CFG_NAND_LARGEPAGE +static struct nand_oobinfo davinci_nand_oobinfo = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 12, + .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, + .oobfree = { {2, 6}, {12, 12}, {28, 12}, {44, 12}, {60, 4} } +}; +#elif defined(CFG_NAND_SMALLPAGE) +static struct nand_oobinfo davinci_nand_oobinfo = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 3, + .eccpos = {0, 1, 2}, + .oobfree = { {6, 2}, {8, 8} } +}; +#else +#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!" +#endif + +static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) +{ + emifregs emif_addr; + int dummy; + + emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; + + dummy = emif_addr->NANDF1ECC; + dummy = emif_addr->NANDF2ECC; + dummy = emif_addr->NANDF3ECC; + dummy = emif_addr->NANDF4ECC; + + emif_addr->NANDFCR |= (1 << 8); +} + +static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) +{ + u_int32_t ecc = 0; + emifregs emif_base_addr; + + emif_base_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; + + if (region == 1) + ecc = emif_base_addr->NANDF1ECC; + else if (region == 2) + ecc = emif_base_addr->NANDF2ECC; + else if (region == 3) + ecc = emif_base_addr->NANDF3ECC; + else if (region == 4) + ecc = emif_base_addr->NANDF4ECC; + + return(ecc); +} + +static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) +{ + u_int32_t tmp; + int region, n; + struct nand_chip *this = mtd->priv; + + n = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1; + + region = 1; + while (n--) { + tmp = nand_davinci_readecc(mtd, region); + *ecc_code++ = tmp; + *ecc_code++ = tmp >> 16; + *ecc_code++ = ((tmp >> 8) & 0x0f) | ((tmp >> 20) & 0xf0); + region++; + } + return(0); +} + +static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf) +{ + u_int32_t tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8); + + ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); + ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); + ecc_buf[2] = ~( P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | P1e(tmp) | P2048o(tmp) | P2048e(tmp)); +} + +static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_int8_t *page_data) +{ + u_int32_t i; + u_int8_t tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; + u_int8_t comp0_bit[8], comp1_bit[8], comp2_bit[8]; + u_int8_t ecc_bit[24]; + u_int8_t ecc_sum = 0; + u_int8_t find_bit = 0; + u_int32_t find_byte = 0; + int is_ecc_ff; + + is_ecc_ff = ((*ecc_nand == 0xff) && (*(ecc_nand + 1) == 0xff) && (*(ecc_nand + 2) == 0xff)); + + nand_davinci_gen_true_ecc(ecc_nand); + nand_davinci_gen_true_ecc(ecc_calc); + + for (i = 0; i <= 2; i++) { + *(ecc_nand + i) = ~(*(ecc_nand + i)); + *(ecc_calc + i) = ~(*(ecc_calc + i)); + } + + for (i = 0; i < 8; i++) { + tmp0_bit[i] = *ecc_nand % 2; + *ecc_nand = *ecc_nand / 2; + } + + for (i = 0; i < 8; i++) { + tmp1_bit[i] = *(ecc_nand + 1) % 2; + *(ecc_nand + 1) = *(ecc_nand + 1) / 2; + } + + for (i = 0; i < 8; i++) { + tmp2_bit[i] = *(ecc_nand + 2) % 2; + *(ecc_nand + 2) = *(ecc_nand + 2) / 2; + } + + for (i = 0; i < 8; i++) { + comp0_bit[i] = *ecc_calc % 2; + *ecc_calc = *ecc_calc / 2; + } + + for (i = 0; i < 8; i++) { + comp1_bit[i] = *(ecc_calc + 1) % 2; + *(ecc_calc + 1) = *(ecc_calc + 1) / 2; + } + + for (i = 0; i < 8; i++) { + comp2_bit[i] = *(ecc_calc + 2) % 2; + *(ecc_calc + 2) = *(ecc_calc + 2) / 2; + } + + for (i = 0; i< 6; i++) + ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; + + for (i = 0; i < 8; i++) + ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; + + for (i = 0; i < 8; i++) + ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; + + ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; + ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; + + for (i = 0; i < 24; i++) + ecc_sum += ecc_bit[i]; + + switch (ecc_sum) { + case 0: + /* Not reached because this function is not called if + ECC values are equal */ + return 0; + case 1: + /* Uncorrectable error */ + DEBUG (MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n"); + return(-1); + case 12: + /* Correctable error */ + find_byte = (ecc_bit[23] << 8) + + (ecc_bit[21] << 7) + + (ecc_bit[19] << 6) + + (ecc_bit[17] << 5) + + (ecc_bit[15] << 4) + + (ecc_bit[13] << 3) + + (ecc_bit[11] << 2) + + (ecc_bit[9] << 1) + + ecc_bit[7]; + + find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; + + DEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at offset: %d, bit: %d\n", find_byte, find_bit); + + page_data[find_byte] ^= (1 << find_bit); + + return(0); + default: + if (is_ecc_ff) { + if (ecc_calc[0] == 0 && ecc_calc[1] == 0 && ecc_calc[2] == 0) + return(0); + } + DEBUG (MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n"); + return(-1); + } +} + +static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) +{ + struct nand_chip *this; + int block_count = 0, i, rc; + + this = mtd->priv; + block_count = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1; + for (i = 0; i < block_count; i++) { + if (memcmp(read_ecc, calc_ecc, 3) != 0) { + rc = nand_davinci_compare_ecc(read_ecc, calc_ecc, dat); + if (rc < 0) { + return(rc); + } + } + read_ecc += 3; + calc_ecc += 3; + dat += 512; + } + return(0); +} +#endif + +static int nand_davinci_dev_ready(struct mtd_info *mtd) +{ + emifregs emif_addr; + + emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; + + return(emif_addr->NANDFSR & 0x1); +} + +static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + while(!nand_davinci_dev_ready(mtd)) {;} + *NAND_CE0CLE = NAND_STATUS; + return(*NAND_CE0DATA); +} + +static void nand_flash_init(void) +{ + u_int32_t acfg1 = 0x3ffffffc; + u_int32_t acfg2 = 0x3ffffffc; + u_int32_t acfg3 = 0x3ffffffc; + u_int32_t acfg4 = 0x3ffffffc; + emifregs emif_regs; + + /*------------------------------------------------------------------* + * NAND FLASH CHIP TIMEOUT @ 459 MHz * + * * + * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz * + * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns * + * * + *------------------------------------------------------------------*/ + acfg1 = 0 + | (0 << 31 ) /* selectStrobe */ + | (0 << 30 ) /* extWait */ + | (1 << 26 ) /* writeSetup 10 ns */ + | (3 << 20 ) /* writeStrobe 40 ns */ + | (1 << 17 ) /* writeHold 10 ns */ + | (1 << 13 ) /* readSetup 10 ns */ + | (5 << 7 ) /* readStrobe 60 ns */ + | (1 << 4 ) /* readHold 10 ns */ + | (3 << 2 ) /* turnAround ?? ns */ + | (0 << 0 ) /* asyncSize 8-bit bus */ + ; + + emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; + + emif_regs->AWCCR |= 0x10000000; + emif_regs->AB1CR = acfg1; /* 0x08244128 */; + emif_regs->AB2CR = acfg2; + emif_regs->AB3CR = acfg3; + emif_regs->AB4CR = acfg4; + emif_regs->NANDFCR = 0x00000101; +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->IO_ADDR_R = (void __iomem *)NAND_CE0DATA; + nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA; + nand->chip_delay = 0; + nand->select_chip = nand_davinci_select_chip; +#ifdef CFG_NAND_USE_FLASH_BBT + nand->options = NAND_USE_FLASH_BBT; +#endif +#ifdef CFG_NAND_HW_ECC +#ifdef CFG_NAND_LARGEPAGE + nand->eccmode = NAND_ECC_HW12_2048; +#elif defined(CFG_NAND_SMALLPAGE) + nand->eccmode = NAND_ECC_HW3_512; +#else +#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!" +#endif + nand->autooob = &davinci_nand_oobinfo; + nand->calculate_ecc = nand_davinci_calculate_ecc; + nand->correct_data = nand_davinci_correct_data; + nand->enable_hwecc = nand_davinci_enable_hwecc; +#else + nand->eccmode = NAND_ECC_SOFT; +#endif + + /* Set address of hardware control function */ + nand->hwcontrol = nand_davinci_hwcontrol; + + nand->dev_ready = nand_davinci_dev_ready; + nand->waitfunc = nand_davinci_waitfunc; + + nand_flash_init(); + + return(0); +} + +#else +#error "U-Boot legacy NAND support not available for DaVinci chips" +#endif +#endif /* CFG_USE_NAND */ diff --git a/cpu/arm926ejs/davinci/reset.S b/cpu/arm926ejs/davinci/reset.S new file mode 100644 index 00000000000..a687d44035c --- /dev/null +++ b/cpu/arm926ejs/davinci/reset.S @@ -0,0 +1,77 @@ +/* + * Processor reset using WDT for TI TMS320DM644x SoC. + * + * Copyright (C) 2007 Sergey Kubushyn + * + * ----------------------------------------------------- + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.globl reset_cpu +reset_cpu: + ldr r0, WDT_TGCR + mov r1, $0x08 + str r1, [r0] + ldr r1, [r0] + orr r1, r1, $0x03 + str r1, [r0] + mov r1, $0 + ldr r0, WDT_TIM12 + str r1, [r0] + ldr r0, WDT_TIM34 + str r1, [r0] + ldr r0, WDT_PRD12 + str r1, [r0] + ldr r0, WDT_PRD34 + str r1, [r0] + ldr r0, WDT_TCR + ldr r1, [r0] + orr r1, r1, $0x40 + str r1, [r0] + ldr r0, WDT_WDTCR + ldr r1, [r0] + orr r1, r1, $0x4000 + str r1, [r0] + ldr r1, WDTCR_VAL1 + str r1, [r0] + ldr r1, WDTCR_VAL2 + str r1, [r0] + nop + nop + nop + nop +reset_cpu_loop: + b reset_cpu_loop + +WDT_TGCR: + .word 0x01c21c24 +WDT_TIM12: + .word 0x01c21c10 +WDT_TIM34: + .word 0x01c21c14 +WDT_PRD12: + .word 0x01c21c18 +WDT_PRD34: + .word 0x01c21c1c +WDT_TCR: + .word 0x01c21c20 +WDT_WDTCR: + .word 0x01c21c28 +WDTCR_VAL1: + .word 0xa5c64000 +WDTCR_VAL2: + .word 0xda7e4000 diff --git a/cpu/arm926ejs/davinci/timer.c b/cpu/arm926ejs/davinci/timer.c new file mode 100644 index 00000000000..c6b1dda51fc --- /dev/null +++ b/cpu/arm926ejs/davinci/timer.c @@ -0,0 +1,165 @@ +/* + * (C) Copyright 2003 + * Texas Instruments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. + * + * Copyright (C) 2007 Sergey Kubushyn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +typedef volatile struct { + u_int32_t pid12; + u_int32_t emumgt_clksped; + u_int32_t gpint_en; + u_int32_t gpdir_dat; + u_int32_t tim12; + u_int32_t tim34; + u_int32_t prd12; + u_int32_t prd34; + u_int32_t tcr; + u_int32_t tgcr; + u_int32_t wdtcr; + u_int32_t tlgc; + u_int32_t tlmr; +} davinci_timer; + +davinci_timer *timer = (davinci_timer *)CFG_TIMERBASE; + +#define TIMER_LOAD_VAL (CFG_HZ_CLOCK / CFG_HZ) +#define READ_TIMER timer->tim34 + +static ulong timestamp; +static ulong lastinc; + +int timer_init(void) +{ + /* We are using timer34 in unchained 32-bit mode, full speed */ + timer->tcr = 0x0; + timer->tgcr = 0x0; + timer->tgcr = 0x06; + timer->tim34 = 0x0; + timer->prd34 = TIMER_LOAD_VAL; + lastinc = 0; + timer->tcr = 0x80 << 16; + timestamp = 0; + + return(0); +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return(get_timer_masked() - base); +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +void udelay(unsigned long usec) +{ + udelay_masked(usec); +} + +void reset_timer_masked(void) +{ + lastinc = READ_TIMER; + timestamp = 0; +} + +ulong get_timer_raw(void) +{ + ulong now = READ_TIMER; + + if (now >= lastinc) { + /* normal mode */ + timestamp += now - lastinc; + } else { + /* overflow ... */ + timestamp += now + TIMER_LOAD_VAL - lastinc; + } + lastinc = now; + return timestamp; +} + +ulong get_timer_masked(void) +{ + return(get_timer_raw() / TIMER_LOAD_VAL); +} + +void udelay_masked(unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + tmo = CFG_HZ_CLOCK / 1000; + tmo *= usec; + tmo /= 1000; + + endtime = get_timer_raw() + tmo; + + do { + ulong now = get_timer_raw(); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return(get_timer(0)); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + ulong tbclk; + + tbclk = CFG_HZ; + return(tbclk); +} diff --git a/include/_exports.h b/include/_exports.h index da6e088163e..af43885c527 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -14,6 +14,9 @@ EXPORT_FUNC(vprintf) EXPORT_FUNC(do_reset) EXPORT_FUNC(getenv) EXPORT_FUNC(setenv) +#ifdef CONFIG_HAS_UID +EXPORT_FUNC(forceenv) +#endif EXPORT_FUNC(simple_strtoul) EXPORT_FUNC(simple_strtol) EXPORT_FUNC(strcmp) diff --git a/include/asm-arm/arch-davinci/emac_defs.h b/include/asm-arm/arch-davinci/emac_defs.h new file mode 100644 index 00000000000..0e10116d870 --- /dev/null +++ b/include/asm-arm/arch-davinci/emac_defs.h @@ -0,0 +1,311 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Based on: + * + * ---------------------------------------------------------------------------- + * + * dm644x_emac.h + * + * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM + * + * Copyright (C) 2005 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + + * Modifications: + * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot. + * + */ + +#ifndef _DM644X_EMAC_H_ +#define _DM644X_EMAC_H_ + +#include + +#define EMAC_BASE_ADDR (0x01c80000) +#define EMAC_WRAPPER_BASE_ADDR (0x01c81000) +#define EMAC_WRAPPER_RAM_ADDR (0x01c82000) +#define EMAC_MDIO_BASE_ADDR (0x01c84000) + +/* MDIO module input frequency */ +#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */ +/* MDIO clock output frequency */ +#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ + +/* Ethernet Min/Max packet size */ +#define EMAC_MIN_ETHERNET_PKT_SIZE 60 +#define EMAC_MAX_ETHERNET_PKT_SIZE 1518 +#define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */ + +/* Number of RX packet buffers + * NOTE: Only 1 buffer supported as of now + */ +#define EMAC_MAX_RX_BUFFERS 10 + + +/*********************************************** + ******** Internally used macros *************** + ***********************************************/ + +#define EMAC_CH_TX 1 +#define EMAC_CH_RX 0 + +/* Each descriptor occupies 4 words, lets start RX desc's at 0 and + * reserve space for 64 descriptors max + */ +#define EMAC_RX_DESC_BASE 0x0 +#define EMAC_TX_DESC_BASE 0x1000 + +/* EMAC Teardown value */ +#define EMAC_TEARDOWN_VALUE 0xfffffffc + +/* MII Status Register */ +#define MII_STATUS_REG 1 + +/* Number of statistics registers */ +#define EMAC_NUM_STATS 36 + + +/* EMAC Descriptor */ +typedef volatile struct _emac_desc +{ + u_int32_t next; /* Pointer to next descriptor in chain */ + u_int8_t *buffer; /* Pointer to data buffer */ + u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */ + u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */ +} emac_desc; + +/* CPPI bit positions */ +#define EMAC_CPPI_SOP_BIT (0x80000000) +#define EMAC_CPPI_EOP_BIT (0x40000000) +#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) +#define EMAC_CPPI_EOQ_BIT (0x10000000) +#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) +#define EMAC_CPPI_PASS_CRC_BIT (0x04000000) + +#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000) + +#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) +#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) + +#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) +#define EMAC_RXMBPENABLE_RXBROADEN (0x2000) + + +#define MDIO_CONTROL_IDLE (0x80000000) +#define MDIO_CONTROL_ENABLE (0x40000000) +#define MDIO_CONTROL_FAULT_ENABLE (0x40000) +#define MDIO_CONTROL_FAULT (0x80000) +#define MDIO_USERACCESS0_GO (0x80000000) +#define MDIO_USERACCESS0_WRITE_READ (0x0) +#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) +#define MDIO_USERACCESS0_ACK (0x20000000) + +/* Ethernet MAC Registers Structure */ +typedef struct { + dv_reg TXIDVER; + dv_reg TXCONTROL; + dv_reg TXTEARDOWN; + u_int8_t RSVD0[4]; + dv_reg RXIDVER; + dv_reg RXCONTROL; + dv_reg RXTEARDOWN; + u_int8_t RSVD1[100]; + dv_reg TXINTSTATRAW; + dv_reg TXINTSTATMASKED; + dv_reg TXINTMASKSET; + dv_reg TXINTMASKCLEAR; + dv_reg MACINVECTOR; + u_int8_t RSVD2[12]; + dv_reg RXINTSTATRAW; + dv_reg RXINTSTATMASKED; + dv_reg RXINTMASKSET; + dv_reg RXINTMASKCLEAR; + dv_reg MACINTSTATRAW; + dv_reg MACINTSTATMASKED; + dv_reg MACINTMASKSET; + dv_reg MACINTMASKCLEAR; + u_int8_t RSVD3[64]; + dv_reg RXMBPENABLE; + dv_reg RXUNICASTSET; + dv_reg RXUNICASTCLEAR; + dv_reg RXMAXLEN; + dv_reg RXBUFFEROFFSET; + dv_reg RXFILTERLOWTHRESH; + u_int8_t RSVD4[8]; + dv_reg RX0FLOWTHRESH; + dv_reg RX1FLOWTHRESH; + dv_reg RX2FLOWTHRESH; + dv_reg RX3FLOWTHRESH; + dv_reg RX4FLOWTHRESH; + dv_reg RX5FLOWTHRESH; + dv_reg RX6FLOWTHRESH; + dv_reg RX7FLOWTHRESH; + dv_reg RX0FREEBUFFER; + dv_reg RX1FREEBUFFER; + dv_reg RX2FREEBUFFER; + dv_reg RX3FREEBUFFER; + dv_reg RX4FREEBUFFER; + dv_reg RX5FREEBUFFER; + dv_reg RX6FREEBUFFER; + dv_reg RX7FREEBUFFER; + dv_reg MACCONTROL; + dv_reg MACSTATUS; + dv_reg EMCONTROL; + dv_reg FIFOCONTROL; + dv_reg MACCONFIG; + dv_reg SOFTRESET; + u_int8_t RSVD5[88]; + dv_reg MACSRCADDRLO; + dv_reg MACSRCADDRHI; + dv_reg MACHASH1; + dv_reg MACHASH2; + dv_reg BOFFTEST; + dv_reg TPACETEST; + dv_reg RXPAUSE; + dv_reg TXPAUSE; + u_int8_t RSVD6[16]; + dv_reg RXGOODFRAMES; + dv_reg RXBCASTFRAMES; + dv_reg RXMCASTFRAMES; + dv_reg RXPAUSEFRAMES; + dv_reg RXCRCERRORS; + dv_reg RXALIGNCODEERRORS; + dv_reg RXOVERSIZED; + dv_reg RXJABBER; + dv_reg RXUNDERSIZED; + dv_reg RXFRAGMENTS; + dv_reg RXFILTERED; + dv_reg RXQOSFILTERED; + dv_reg RXOCTETS; + dv_reg TXGOODFRAMES; + dv_reg TXBCASTFRAMES; + dv_reg TXMCASTFRAMES; + dv_reg TXPAUSEFRAMES; + dv_reg TXDEFERRED; + dv_reg TXCOLLISION; + dv_reg TXSINGLECOLL; + dv_reg TXMULTICOLL; + dv_reg TXEXCESSIVECOLL; + dv_reg TXLATECOLL; + dv_reg TXUNDERRUN; + dv_reg TXCARRIERSENSE; + dv_reg TXOCTETS; + dv_reg FRAME64; + dv_reg FRAME65T127; + dv_reg FRAME128T255; + dv_reg FRAME256T511; + dv_reg FRAME512T1023; + dv_reg FRAME1024TUP; + dv_reg NETOCTETS; + dv_reg RXSOFOVERRUNS; + dv_reg RXMOFOVERRUNS; + dv_reg RXDMAOVERRUNS; + u_int8_t RSVD7[624]; + dv_reg MACADDRLO; + dv_reg MACADDRHI; + dv_reg MACINDEX; + u_int8_t RSVD8[244]; + dv_reg TX0HDP; + dv_reg TX1HDP; + dv_reg TX2HDP; + dv_reg TX3HDP; + dv_reg TX4HDP; + dv_reg TX5HDP; + dv_reg TX6HDP; + dv_reg TX7HDP; + dv_reg RX0HDP; + dv_reg RX1HDP; + dv_reg RX2HDP; + dv_reg RX3HDP; + dv_reg RX4HDP; + dv_reg RX5HDP; + dv_reg RX6HDP; + dv_reg RX7HDP; + dv_reg TX0CP; + dv_reg TX1CP; + dv_reg TX2CP; + dv_reg TX3CP; + dv_reg TX4CP; + dv_reg TX5CP; + dv_reg TX6CP; + dv_reg TX7CP; + dv_reg RX0CP; + dv_reg RX1CP; + dv_reg RX2CP; + dv_reg RX3CP; + dv_reg RX4CP; + dv_reg RX5CP; + dv_reg RX6CP; + dv_reg RX7CP; +} emac_regs; + +/* EMAC Wrapper Registers Structure */ +typedef struct { + u_int8_t RSVD0[4100]; + dv_reg EWCTL; + dv_reg EWINTTCNT; +} ewrap_regs; + + +/* EMAC MDIO Registers Structure */ +typedef struct { + dv_reg VERSION; + dv_reg CONTROL; + dv_reg ALIVE; + dv_reg LINK; + dv_reg LINKINTRAW; + dv_reg LINKINTMASKED; + u_int8_t RSVD0[8]; + dv_reg USERINTRAW; + dv_reg USERINTMASKED; + dv_reg USERINTMASKSET; + dv_reg USERINTMASKCLEAR; + u_int8_t RSVD1[80]; + dv_reg USERACCESS0; + dv_reg USERPHYSEL0; + dv_reg USERACCESS1; + dv_reg USERPHYSEL1; +} mdio_regs; + +int dm644x_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data); +int dm644x_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data); + +typedef struct +{ + char name[64]; + int (*init)(int phy_addr); + int (*is_phy_connected)(int phy_addr); + int (*get_link_speed)(int phy_addr); + int (*auto_negotiate)(int phy_addr); +} phy_t; + +#define PHY_LXT972 (0x001378e2) +int lxt972_is_phy_connected(int phy_addr); +int lxt972_get_link_speed(int phy_addr); +int lxt972_init_phy(int phy_addr); +int lxt972_auto_negotiate(int phy_addr); + +#define PHY_DP83848 (0x20005c90) +int dp83848_is_phy_connected(int phy_addr); +int dp83848_get_link_speed(int phy_addr); +int dp83848_init_phy(int phy_addr); +int dp83848_auto_negotiate(int phy_addr); + +#endif /* _DM644X_EMAC_H_ */ diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h new file mode 100644 index 00000000000..646fc774694 --- /dev/null +++ b/include/asm-arm/arch-davinci/emif_defs.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _EMIF_DEFS_H_ +#define _EMIF_DEFS_H_ + +#include + +typedef struct { + dv_reg ERCSR; + dv_reg AWCCR; + dv_reg SDBCR; + dv_reg SDRCR; + dv_reg AB1CR; + dv_reg AB2CR; + dv_reg AB3CR; + dv_reg AB4CR; + dv_reg SDTIMR; + dv_reg DDRSR; + dv_reg DDRPHYCR; + dv_reg DDRPHYSR; + dv_reg TOTAR; + dv_reg TOTACTR; + dv_reg DDRPHYID_REV; + dv_reg SDSRETR; + dv_reg EIRR; + dv_reg EIMR; + dv_reg EIMSR; + dv_reg EIMCR; + dv_reg IOCTRLR; + dv_reg IOSTATR; + u_int8_t RSVD0[8]; + dv_reg NANDFCR; + dv_reg NANDFSR; + u_int8_t RSVD1[8]; + dv_reg NANDF1ECC; + dv_reg NANDF2ECC; + dv_reg NANDF3ECC; + dv_reg NANDF4ECC; +} emif_registers; + +typedef emif_registers *emifregs; +#endif diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h new file mode 100644 index 00000000000..ebcdcfea1e9 --- /dev/null +++ b/include/asm-arm/arch-davinci/hardware.h @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Based on: + * + * ------------------------------------------------------------------------- + * + * linux/include/asm-arm/arch-davinci/hardware.h + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include +#include + +#define REG(addr) (*(volatile unsigned int *)(addr)) +#define REG_P(addr) ((volatile unsigned int *)(addr)) + +typedef volatile unsigned int dv_reg; +typedef volatile unsigned int * dv_reg_p; + +/* + * Base register addresses + */ +#define DAVINCI_DMA_3PCC_BASE (0x01c00000) +#define DAVINCI_DMA_3PTC0_BASE (0x01c10000) +#define DAVINCI_DMA_3PTC1_BASE (0x01c10400) +#define DAVINCI_UART0_BASE (0x01c20000) +#define DAVINCI_UART1_BASE (0x01c20400) +#define DAVINCI_UART2_BASE (0x01c20800) +#define DAVINCI_I2C_BASE (0x01c21000) +#define DAVINCI_TIMER0_BASE (0x01c21400) +#define DAVINCI_TIMER1_BASE (0x01c21800) +#define DAVINCI_WDOG_BASE (0x01c21c00) +#define DAVINCI_PWM0_BASE (0x01c22000) +#define DAVINCI_PWM1_BASE (0x01c22400) +#define DAVINCI_PWM2_BASE (0x01c22800) +#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000) +#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800) +#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00) +#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000) +#define DAVINCI_SYSTEM_DFT_BASE (0x01c42000) +#define DAVINCI_ARM_INTC_BASE (0x01c48000) +#define DAVINCI_IEEE1394_BASE (0x01c60000) +#define DAVINCI_USB_OTG_BASE (0x01c64000) +#define DAVINCI_CFC_ATA_BASE (0x01c66000) +#define DAVINCI_SPI_BASE (0x01c66800) +#define DAVINCI_GPIO_BASE (0x01c67000) +#define DAVINCI_UHPI_BASE (0x01c67800) +#define DAVINCI_VPSS_REGS_BASE (0x01c70000) +#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01c80000) +#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01c81000) +#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01c82000) +#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01c84000) +#define DAVINCI_IMCOP_BASE (0x01cc0000) +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01e00000) +#define DAVINCI_VLYNQ_BASE (0x01e01000) +#define DAVINCI_MCBSP_BASE (0x01e02000) +#define DAVINCI_MMC_SD_BASE (0x01e10000) +#define DAVINCI_MS_BASE (0x01e20000) +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) +#define DAVINCI_VLYNQ_REMOTE_BASE (0x0c000000) + +/* Power and Sleep Controller (PSC) Domains */ +#define DAVINCI_GPSC_ARMDOMAIN 0 +#define DAVINCI_GPSC_DSPDOMAIN 1 + +#define DAVINCI_LPSC_VPSSMSTR 0 +#define DAVINCI_LPSC_VPSSSLV 1 +#define DAVINCI_LPSC_TPCC 2 +#define DAVINCI_LPSC_TPTC0 3 +#define DAVINCI_LPSC_TPTC1 4 +#define DAVINCI_LPSC_EMAC 5 +#define DAVINCI_LPSC_EMAC_WRAPPER 6 +#define DAVINCI_LPSC_MDIO 7 +#define DAVINCI_LPSC_IEEE1394 8 +#define DAVINCI_LPSC_USB 9 +#define DAVINCI_LPSC_ATA 10 +#define DAVINCI_LPSC_VLYNQ 11 +#define DAVINCI_LPSC_UHPI 12 +#define DAVINCI_LPSC_DDR_EMIF 13 +#define DAVINCI_LPSC_AEMIF 14 +#define DAVINCI_LPSC_MMC_SD 15 +#define DAVINCI_LPSC_MEMSTICK 16 +#define DAVINCI_LPSC_McBSP 17 +#define DAVINCI_LPSC_I2C 18 +#define DAVINCI_LPSC_UART0 19 +#define DAVINCI_LPSC_UART1 20 +#define DAVINCI_LPSC_UART2 21 +#define DAVINCI_LPSC_SPI 22 +#define DAVINCI_LPSC_PWM0 23 +#define DAVINCI_LPSC_PWM1 24 +#define DAVINCI_LPSC_PWM2 25 +#define DAVINCI_LPSC_GPIO 26 +#define DAVINCI_LPSC_TIMER0 27 +#define DAVINCI_LPSC_TIMER1 28 +#define DAVINCI_LPSC_TIMER2 29 +#define DAVINCI_LPSC_SYSTEM_SUBSYS 30 +#define DAVINCI_LPSC_ARM 31 +#define DAVINCI_LPSC_SCR2 32 +#define DAVINCI_LPSC_SCR3 33 +#define DAVINCI_LPSC_SCR4 34 +#define DAVINCI_LPSC_CROSSBAR 35 +#define DAVINCI_LPSC_CFG27 36 +#define DAVINCI_LPSC_CFG3 37 +#define DAVINCI_LPSC_CFG5 38 +#define DAVINCI_LPSC_GEM 39 +#define DAVINCI_LPSC_IMCOP 40 + +/* Some PSC defines */ +#define PSC_CHP_SHRTSW (0x01c40038) +#define PSC_GBLCTL (0x01c41010) +#define PSC_EPCPR (0x01c41070) +#define PSC_EPCCR (0x01c41078) +#define PSC_PTCMD (0x01c41120) +#define PSC_PTSTAT (0x01c41128) +#define PSC_PDSTAT (0x01c41200) +#define PSC_PDSTAT1 (0x01c41204) +#define PSC_PDCTL (0x01c41300) +#define PSC_PDCTL1 (0x01c41304) + +#define PSC_MDCTL_BASE (0x01c41a00) +#define PSC_MDSTAT_BASE (0x01c41800) + +#define VDD3P3V_PWDN (0x01c40048) +#define UART0_PWREMU_MGMT (0x01c20030) + +#define PSC_SILVER_BULLET (0x01c41a20) + +/* Some PLL defines */ +#define PLL1_PLLM (0x01c40910) +#define PLL2_PLLM (0x01c40d10) +#define PLL2_DIV2 (0x01c40d1c) + +/* Miscellania... */ +#define VBPR (0x20000020) +#define PINMUX0 (0x01c40000) +#define PINMUX1 (0x01c40004) + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-davinci/i2c_defs.h b/include/asm-arm/arch-davinci/i2c_defs.h new file mode 100644 index 00000000000..2e902e17f83 --- /dev/null +++ b/include/asm-arm/arch-davinci/i2c_defs.h @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * + * Some changes copyright (C) 2007 Sergey Kubushyn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _DAVINCI_I2C_H_ +#define _DAVINCI_I2C_H_ + +#define I2C_WRITE 0 +#define I2C_READ 1 + +#define I2C_BASE 0x01c21000 + +#define I2C_OA (I2C_BASE + 0x00) +#define I2C_IE (I2C_BASE + 0x04) +#define I2C_STAT (I2C_BASE + 0x08) +#define I2C_SCLL (I2C_BASE + 0x0c) +#define I2C_SCLH (I2C_BASE + 0x10) +#define I2C_CNT (I2C_BASE + 0x14) +#define I2C_DRR (I2C_BASE + 0x18) +#define I2C_SA (I2C_BASE + 0x1c) +#define I2C_DXR (I2C_BASE + 0x20) +#define I2C_CON (I2C_BASE + 0x24) +#define I2C_IV (I2C_BASE + 0x28) +#define I2C_PSC (I2C_BASE + 0x30) + +/* I2C masks */ + +/* I2C Interrupt Enable Register (I2C_IE): */ +#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */ +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Status Register (I2C_STAT): */ + +#define I2C_STAT_BB (1 << 12) /* Bus busy */ +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define I2C_STAT_AAS (1 << 9) /* Address as slave */ +#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */ +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ + + +/* I2C Interrupt Code Register (I2C_INTCODE): */ + +#define I2C_INTCODE_MASK 7 +#define I2C_INTCODE_NONE 0 +#define I2C_INTCODE_AL 1 /* Arbitration lost */ +#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ +#define I2C_INTCODE_ARDY 3 /* Register access ready */ +#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ +#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ +#define I2C_INTCODE_SCD 6 /* Stop condition detect */ + + +/* I2C Configuration Register (I2C_CON): */ + +#define I2C_CON_EN (1 << 5) /* I2C module enable */ +#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */ +#define I2C_CON_MST (1 << 10) /* Master/slave mode */ +#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ +#define I2C_CON_XA (1 << 8) /* Expand address */ +#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */ +#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */ + +#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */ + +#endif diff --git a/include/asm-arm/arch-davinci/nand_defs.h b/include/asm-arm/arch-davinci/nand_defs.h new file mode 100644 index 00000000000..619bd479736 --- /dev/null +++ b/include/asm-arm/arch-davinci/nand_defs.h @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Parts shamelesly stolen from Linux Kernel source tree. + * + * ------------------------------------------------------------ + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _NAND_DEFS_H_ +#define _NAND_DEFS_H_ + +#include + +#define MASK_CLE 0x10 +#define MASK_ALE 0x0a + +#define NAND_CE0CLE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x10)) +#define NAND_CE0ALE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x0a)) +#define NAND_CE0DATA ((volatile u_int8_t *)CFG_NAND_BASE) + +typedef struct { + u_int32_t NRCSR; + u_int32_t AWCCR; + u_int8_t RSVD0[8]; + u_int32_t AB1CR; + u_int32_t AB2CR; + u_int32_t AB3CR; + u_int32_t AB4CR; + u_int8_t RSVD1[32]; + u_int32_t NIRR; + u_int32_t NIMR; + u_int32_t NIMSR; + u_int32_t NIMCR; + u_int8_t RSVD2[16]; + u_int32_t NANDFCR; + u_int32_t NANDFSR; + u_int8_t RSVD3[8]; + u_int32_t NANDF1ECC; + u_int32_t NANDF2ECC; + u_int32_t NANDF3ECC; + u_int32_t NANDF4ECC; + u_int8_t RSVD4[4]; + u_int32_t IODFTECR; + u_int32_t IODFTGCR; + u_int8_t RSVD5[4]; + u_int32_t IODFTMRLR; + u_int32_t IODFTMRMR; + u_int32_t IODFTMRMSBR; + u_int8_t RSVD6[20]; + u_int32_t MODRNR; + u_int8_t RSVD7[76]; + u_int32_t CE0DATA; + u_int32_t CE0ALE; + u_int32_t CE0CLE; + u_int8_t RSVD8[4]; + u_int32_t CE1DATA; + u_int32_t CE1ALE; + u_int32_t CE1CLE; + u_int8_t RSVD9[4]; + u_int32_t CE2DATA; + u_int32_t CE2ALE; + u_int32_t CE2CLE; + u_int8_t RSVD10[4]; + u_int32_t CE3DATA; + u_int32_t CE3ALE; + u_int32_t CE3CLE; +} nand_registers; + +typedef volatile nand_registers *nandregs; + +#define NAND_READ_START 0x00 +#define NAND_READ_END 0x30 +#define NAND_STATUS 0x70 + +#ifdef CFG_NAND_HW_ECC +#define NAND_Ecc_P1e (1 << 0) +#define NAND_Ecc_P2e (1 << 1) +#define NAND_Ecc_P4e (1 << 2) +#define NAND_Ecc_P8e (1 << 3) +#define NAND_Ecc_P16e (1 << 4) +#define NAND_Ecc_P32e (1 << 5) +#define NAND_Ecc_P64e (1 << 6) +#define NAND_Ecc_P128e (1 << 7) +#define NAND_Ecc_P256e (1 << 8) +#define NAND_Ecc_P512e (1 << 9) +#define NAND_Ecc_P1024e (1 << 10) +#define NAND_Ecc_P2048e (1 << 11) + +#define NAND_Ecc_P1o (1 << 16) +#define NAND_Ecc_P2o (1 << 17) +#define NAND_Ecc_P4o (1 << 18) +#define NAND_Ecc_P8o (1 << 19) +#define NAND_Ecc_P16o (1 << 20) +#define NAND_Ecc_P32o (1 << 21) +#define NAND_Ecc_P64o (1 << 22) +#define NAND_Ecc_P128o (1 << 23) +#define NAND_Ecc_P256o (1 << 24) +#define NAND_Ecc_P512o (1 << 25) +#define NAND_Ecc_P1024o (1 << 26) +#define NAND_Ecc_P2048o (1 << 27) + +#define TF(v) (v ? 1 : 0) + +#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) +#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) +#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) +#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) +#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) +#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) +#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) +#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) + +#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) +#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) +#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) +#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) +#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) +#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) +#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) +#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) + +#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) +#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) +#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) +#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) +#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) +#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) +#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) +#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) + +#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) +#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) +#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) +#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) +#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) +#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) +#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) +#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) + +#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) +#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) +#endif + +#endif diff --git a/include/common.h b/include/common.h index ac29d3aac6c..229e64bd49d 100644 --- a/include/common.h +++ b/include/common.h @@ -241,6 +241,9 @@ int saveenv (void); void inline setenv (char *, char *); #else void setenv (char *, char *); +#ifdef CONFIG_HAS_UID +void forceenv (char *, char *); +#endif #endif /* CONFIG_PPC */ #ifdef CONFIG_ARM # include diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h new file mode 100644 index 00000000000..8ecd0595a20 --- /dev/null +++ b/include/configs/davinci_dvevm.h @@ -0,0 +1,214 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include + +/* + * Define this to make U-Boot skip low level initialization when loaded + * by initial bootloader. Not required by NAND U-Boot version but IS + * required for a NOR version used to burn the real NOR U-Boot into + * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive + * so it is NOT possible to build a U-Boot with both NAND and NOR routines. + * NOR U-Boot is loaded directly from Flash so it must perform all the + * low level initialization itself. NAND version is loaded by an initial + * bootloader (UBL in TI-ese) that performs such an initialization so it's + * skipped in NAND version. The third DaVinci boot mode loads a bootloader + * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever) + * performing low level init prior to loading. All that means we can NOT use + * NAND version to put U-Boot into NOR because it doesn't have NOR support and + * we can NOT use NOR version because it performs low level initialization + * effectively destroying itself in DDR memory. That's why a separate NOR + * version with this define is needed. It is loaded via UART, then one uses + * it to somehow download a proper NOR version built WITHOUT this define to + * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze + * NOR support into the initial bootloader so it won't be needed but DaVinci + * static RAM might be too small for this (I have something like 2Kbytes left + * as of now, without NOR support) so this might've not happened... + * +#define CONFIG_NOR_UART_BOOT + */ + +/*=======*/ +/* Board */ +/*=======*/ +#define DV_EVM +#define CFG_NAND_SMALLPAGE +#define CFG_USE_NOR +/*===================*/ +/* SoC Configuration */ +/*===================*/ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ +#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ +#define CFG_HZ 1000 +/*====================================================*/ +/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ +/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ +/*====================================================*/ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_EEPROM_PAGE_WRITE_BITS 6 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +/*=============*/ +/* Memory Info */ +/*=============*/ +#define CFG_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */ +#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ +#define CFG_MEMTEST_START 0x80000000 /* memtest start address */ +#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ +#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */ +#define DDR_8BANKS /* 8-bank DDR2 (256MB) */ +/*====================*/ +/* Serial Driver info */ +/*====================*/ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ +#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */ +#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */ +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/*===================*/ +/* I2C Configuration */ +/*===================*/ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +/*==================================*/ +/* Network & Ethernet Configuration */ +/*==================================*/ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ +#ifdef CFG_USE_NAND +#undef CFG_ENV_IS_IN_FLASH +#define CFG_NO_FLASH +#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#ifdef CFG_NAND_SMALLPAGE +#define CFG_ENV_SECT_SIZE 512 /* Env sector Size */ +#define CFG_ENV_SIZE SZ_16K +#else +#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */ +#define CFG_ENV_SIZE SZ_128K +#endif +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#define CFG_NAND_BASE 0x02000000 +#define CFG_NAND_HW_ECC +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 +#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +#define DEF_BOOTM "" +#elif defined(CFG_USE_NOR) +#ifdef CONFIG_NOR_UART_BOOT +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#else +#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_RELOCATE_UBOOT +#endif +#define CFG_ENV_IS_IN_FLASH +#undef CFG_NO_FLASH +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */ +#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */ +#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*3) +#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ +#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */ +#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ +#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ) +#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */ +#endif +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_MISC_INIT_R +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CFG_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +/*===================*/ +/* Linux Information */ +/*===================*/ +#define LINUX_BOOT_PARAM_ADDR 0x80000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS "mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" +#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2050000" +/*=================*/ +/* U-Boot commands */ +/*=================*/ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#ifdef CFG_USE_NAND +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_NAND +#elif defined(CFG_USE_NOR) +#define CONFIG_CMD_JFFS2 +#else +#error "Either CFG_USE_NAND or CFG_USE_NOR _MUST_ be defined !!!" +#endif +/*=======================*/ +/* KGDB support (if any) */ +/*=======================*/ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h new file mode 100644 index 00000000000..96c9a301478 --- /dev/null +++ b/include/configs/davinci_schmoogie.h @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include + +/*=======*/ +/* Board */ +/*=======*/ +#define SCHMOOGIE +#define CFG_NAND_LARGEPAGE +#define CFG_USE_NAND +/*===================*/ +/* SoC Configuration */ +/*===================*/ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ +#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ +#define CFG_HZ 1000 +/*=============*/ +/* Memory Info */ +/*=============*/ +#define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ +#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ +#define CFG_MEMTEST_START 0x80000000 /* memtest start address */ +#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ +#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ +#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ +/*====================*/ +/* Serial Driver info */ +/*====================*/ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ +#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */ +#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */ +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/*===================*/ +/* I2C Configuration */ +/*===================*/ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +/*==================================*/ +/* Network & Ethernet Configuration */ +/*==================================*/ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_OVERWRITE_ETHADDR_ONCE +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ +#undef CFG_ENV_IS_IN_FLASH +#define CFG_NO_FLASH +#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */ +#define CFG_ENV_SIZE SZ_128K +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#define CFG_NAND_BASE 0x02000000 +#define CFG_NAND_HW_ECC +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 +#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +/*=====================*/ +/* Board related stuff */ +/*=====================*/ +#define CONFIG_RTC_DS1307 /* RTC chip on SCHMOOGIE */ +#define CFG_I2C_RTC_ADDR 0x6f /* RTC chip I2C address */ +#define CONFIG_HAS_UID +#define CONFIG_UID_DS28CM00 /* Unique ID on SCHMOOGIE */ +#define CFG_UID_ADDR 0x50 /* UID chip I2C address */ +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_MISC_INIT_R +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CFG_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +/*===================*/ +/* Linux Information */ +/*===================*/ +#define LINUX_BOOT_PARAM_ADDR 0x80000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" +#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot" +/*=================*/ +/* U-Boot commands */ +/*=================*/ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_DATE +#define CONFIG_CMD_NAND +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +/*=======================*/ +/* KGDB support (if any) */ +/*=======================*/ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h new file mode 100644 index 00000000000..de8c4fac2b0 --- /dev/null +++ b/include/configs/davinci_sonata.h @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include + +/* + * Define this to make U-Boot skip low level initialization when loaded + * by initial bootloader. Not required by NAND U-Boot version but IS + * required for a NOR version used to burn the real NOR U-Boot into + * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive + * so it is NOT possible to build a U-Boot with both NAND and NOR routines. + * NOR U-Boot is loaded directly from Flash so it must perform all the + * low level initialization itself. NAND version is loaded by an initial + * bootloader (UBL in TI-ese) that performs such an initialization so it's + * skipped in NAND version. The third DaVinci boot mode loads a bootloader + * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever) + * performing low level init prior to loading. All that means we can NOT use + * NAND version to put U-Boot into NOR because it doesn't have NOR support and + * we can NOT use NOR version because it performs low level initialization + * effectively destroying itself in DDR memory. That's why a separate NOR + * version with this define is needed. It is loaded via UART, then one uses + * it to somehow download a proper NOR version built WITHOUT this define to + * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze + * NOR support into the initial bootloader so it won't be needed but DaVinci + * static RAM might be too small for this (I have something like 2Kbytes left + * as of now, without NOR support) so this might've not happened... + * +#define CONFIG_NOR_UART_BOOT + */ + +/*=======*/ +/* Board */ +/*=======*/ +#define SONATA_BOARD +#define CFG_NAND_SMALLPAGE +#define CFG_USE_NOR +/*===================*/ +/* SoC Configuration */ +/*===================*/ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ +#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ +#define CFG_HZ 1000 +/*====================================================*/ +/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ +/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ +/*====================================================*/ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_EEPROM_PAGE_WRITE_BITS 6 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +/*=============*/ +/* Memory Info */ +/*=============*/ +#define CFG_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */ +#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ +#define CFG_MEMTEST_START 0x80000000 /* memtest start address */ +#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ +#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ +#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ +/*====================*/ +/* Serial Driver info */ +/*====================*/ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ +#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */ +#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */ +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/*===================*/ +/* I2C Configuration */ +/*===================*/ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +/*==================================*/ +/* Network & Ethernet Configuration */ +/*==================================*/ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ +#ifdef CFG_USE_NAND +#undef CFG_ENV_IS_IN_FLASH +#define CFG_NO_FLASH +#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#define CFG_ENV_SECT_SIZE 512 /* Env sector Size */ +#define CFG_ENV_SIZE SZ_16K +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#define CFG_NAND_BASE 0x02000000 +#define CFG_NAND_HW_ECC +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 +#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +#define DEF_BOOTM "" +#elif defined(CFG_USE_NOR) +#ifdef CONFIG_NOR_UART_BOOT +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#else +#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_RELOCATE_UBOOT +#endif +#define CFG_ENV_IS_IN_FLASH +#undef CFG_NO_FLASH +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */ +#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */ +#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*2) +#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ +#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */ +#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ +#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ) +#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */ +#endif +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_MISC_INIT_R +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CFG_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +/*===================*/ +/* Linux Information */ +/*===================*/ +#define LINUX_BOOT_PARAM_ADDR 0x80000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" +#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2060000" +/*=================*/ +/* U-Boot commands */ +/*=================*/ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#ifdef CFG_USE_NAND +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_NAND +#elif defined(CFG_USE_NOR) +#define CONFIG_CMD_JFFS2 +#else +#error "Either CFG_USE_NAND or CFG_USE_NOR _MUST_ be defined !!!" +#endif +/*=======================*/ +/* KGDB support (if any) */ +/*=======================*/ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/dp83848.h b/include/dp83848.h new file mode 100644 index 00000000000..274bc4c969c --- /dev/null +++ b/include/dp83848.h @@ -0,0 +1,88 @@ +/* + * DP83848 ethernet Physical layer + * + * Copyright (C) 2007 Sergey Kubushyn + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + + +/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */ + +#define DP83848_CTL_REG 0x0 /* Basic Mode Control Reg */ +#define DP83848_STAT_REG 0x1 /* Basic Mode Status Reg */ +#define DP83848_PHYID1_REG 0x2 /* PHY Idendifier Reg 1 */ +#define DP83848_PHYID2_REG 0x3 /* PHY Idendifier Reg 2 */ +#define DP83848_ANA_REG 0x4 /* Auto_Neg Advt Reg */ +#define DP83848_ANLPA_REG 0x5 /* Auto_neg Link Partner Ability Reg */ +#define DP83848_ANE_REG 0x6 /* Auto-neg Expansion Reg */ +#define DP83848_PHY_STAT_REG 0x10 /* PHY Status Register */ +#define DP83848_PHY_INTR_CTRL_REG 0x11 /* PHY Interrupt Control Register */ +#define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */ + +/*--Bit definitions: DP83848_CTL_REG */ +#define DP83848_RESET (1 << 15) /* 1= S/W Reset */ +#define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */ +#define DP83848_SPEED_SELECT (1 << 13) +#define DP83848_AUTONEG (1 << 12) +#define DP83848_POWER_DOWN (1 << 11) +#define DP83848_ISOLATE (1 << 10) +#define DP83848_RESTART_AUTONEG (1 << 9) +#define DP83848_DUPLEX_MODE (1 << 8) +#define DP83848_COLLISION_TEST (1 << 7) + +/*--Bit definitions: DP83848_STAT_REG */ +#define DP83848_100BASE_T4 (1 << 15) +#define DP83848_100BASE_TX_FD (1 << 14) +#define DP83848_100BASE_TX_HD (1 << 13) +#define DP83848_10BASE_T_FD (1 << 12) +#define DP83848_10BASE_T_HD (1 << 11) +#define DP83848_MF_PREAMB_SUPPR (1 << 6) +#define DP83848_AUTONEG_COMP (1 << 5) +#define DP83848_RMT_FAULT (1 << 4) +#define DP83848_AUTONEG_ABILITY (1 << 3) +#define DP83848_LINK_STATUS (1 << 2) +#define DP83848_JABBER_DETECT (1 << 1) +#define DP83848_EXTEND_CAPAB (1 << 0) + +/*--definitions: DP83848_PHYID1 */ +#define DP83848_PHYID1_OUI 0x2000 +#define DP83848_PHYID2_OUI 0x5c90 + +/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */ +#define DP83848_NP (1 << 15) +#define DP83848_ACK (1 << 14) +#define DP83848_RF (1 << 13) +#define DP83848_PAUSE (1 << 10) +#define DP83848_T4 (1 << 9) +#define DP83848_TX_FDX (1 << 8) +#define DP83848_TX_HDX (1 << 7) +#define DP83848_10_FDX (1 << 6) +#define DP83848_10_HDX (1 << 5) +#define DP83848_AN_IEEE_802_3 0x0001 + +/*--Bit definitions: DP83848_ANER */ +#define DP83848_PDF (1 << 4) +#define DP83848_LP_NP_ABLE (1 << 3) +#define DP83848_NP_ABLE (1 << 2) +#define DP83848_PAGE_RX (1 << 1) +#define DP83848_LP_AN_ABLE (1 << 0) + +/*--Bit definitions: DP83848_PHY_STAT */ +#define DP83848_RX_ERR_LATCH (1 << 13) +#define DP83848_POLARITY_STAT (1 << 12) +#define DP83848_FALSE_CAR_SENSE (1 << 11) +#define DP83848_SIG_DETECT (1 << 10) +#define DP83848_DESCRAM_LOCK (1 << 9) +#define DP83848_PAGE_RCV (1 << 8) +#define DP83848_PHY_RMT_FAULT (1 << 6) +#define DP83848_JABBER (1 << 5) +#define DP83848_AUTONEG_COMPLETE (1 << 4) +#define DP83848_LOOPBACK_STAT (1 << 3) +#define DP83848_DUPLEX (1 << 2) +#define DP83848_SPEED (1 << 1) +#define DP83848_LINK (1 << 0) diff --git a/include/exports.h b/include/exports.h index 0516da93749..d6512cb3a45 100644 --- a/include/exports.h +++ b/include/exports.h @@ -25,6 +25,9 @@ char *getenv (char *name); void setenv (char *varname, char *varvalue); long simple_strtol(const char *cp,char **endp,unsigned int base); int strcmp(const char * cs,const char * ct); +#ifdef CONFIG_HAS_UID +void forceenv (char *varname, char *varvalue); +#endif #if defined(CONFIG_CMD_I2C) int i2c_write (uchar, uint, int , uchar* , int); int i2c_read (uchar, uint, int , uchar* , int); diff --git a/lib_arm/board.c b/lib_arm/board.c index 8f4e19bfcb5..d37e5dab352 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -364,6 +364,13 @@ void start_armboot (void) enable_interrupts (); /* Perform network card initialisation if necessary */ +#ifdef CONFIG_DRIVER_TI_EMAC +extern void dm644x_eth_set_mac_addr (const u_int8_t *addr); + if (getenv ("ethaddr")) { + dm644x_eth_set_mac_addr(gd->bd->bi_enetaddr); + } +#endif + #ifdef CONFIG_DRIVER_CS8900 cs8900_get_enetaddr (gd->bd->bi_enetaddr); #endif diff --git a/net/eth.c b/net/eth.c index 6576ee405bb..c8f92a52634 100644 --- a/net/eth.c +++ b/net/eth.c @@ -464,6 +464,8 @@ extern int at91rm9200_miiphy_initialize(bd_t *bis); extern int emac4xx_miiphy_initialize(bd_t *bis); extern int mcf52x2_miiphy_initialize(bd_t *bis); extern int ns7520_miiphy_initialize(bd_t *bis); +extern int dm644x_eth_miiphy_initialize(bd_t *bis); + int eth_initialize(bd_t *bis) { @@ -483,6 +485,9 @@ int eth_initialize(bd_t *bis) #endif #if defined(CONFIG_NETARM) ns7520_miiphy_initialize(bis); +#endif +#if defined(CONFIG_DRIVER_TI_EMAC) + dm644x_eth_miiphy_initialize(bis); #endif return 0; } -- cgit v1.3.1 From c2c0ab4aff86622b837a48a0e560351f9afafb95 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 10 Aug 2007 20:34:58 +0200 Subject: Conding style cleanup Signed-off-by: Stefan Roese --- cpu/arm926ejs/davinci/ether.c | 2 -- cpu/arm926ejs/davinci/lowlevel_init.S | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/arm926ejs/davinci/ether.c b/cpu/arm926ejs/davinci/ether.c index 9ec1ee70bf7..32e81d11d4e 100644 --- a/cpu/arm926ejs/davinci/ether.c +++ b/cpu/arm926ejs/davinci/ether.c @@ -252,7 +252,6 @@ static int gen_auto_negotiate(int phy_addr) { u_int16_t tmp; - if (!dm644x_eth_phy_read(phy_addr, PHY_BMCR, &tmp)) return(0); @@ -273,7 +272,6 @@ static int gen_auto_negotiate(int phy_addr) /* End of generic PHY functions */ - #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) static int dm644x_mii_phy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short *value) { diff --git a/cpu/arm926ejs/davinci/lowlevel_init.S b/cpu/arm926ejs/davinci/lowlevel_init.S index bbc48ec4725..a87c112eca4 100644 --- a/cpu/arm926ejs/davinci/lowlevel_init.S +++ b/cpu/arm926ejs/davinci/lowlevel_init.S @@ -545,7 +545,7 @@ VTP1Lock: mov r10, $0 str r10, [r6] - /* + /* * Call board-specific lowlevel init. * That MUST be present and THAT returns * back to arch calling code with "mov pc, lr." -- cgit v1.3.1 From 49bb59912d21aacb507eb81fd21fb7af650c706c Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Fri, 10 Aug 2007 15:48:59 +0800 Subject: mpc83xx: Suppress the warning 'burstlen' suppress the warning 'burstlen' of spd_sdram. Signed-off-by: Dave Liu --- cpu/mpc83xx/spd_sdram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 2c17cee31a5..54f0c83d454 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -576,7 +576,7 @@ long int spd_sdram() if (spd.dataw_lsb == 0x20) { if (spd.mem_type == SPD_MEMTYPE_DDR) burstlen = 0x03; /* 32 bit data bus, burst len is 8 */ - if (spd.mem_type == SPD_MEMTYPE_DDR2) + else burstlen = 0x02; /* 32 bit data bus, burst len is 4 */ printf("\n DDR DIMM: data bus width is 32 bit"); } else { -- cgit v1.3.1 From afaac86fe2948ac84cd9a12bbed883b3c683e7d9 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 12 Aug 2007 14:27:39 +0200 Subject: Clean up some remaining CFG_CMD_ -> CONFIG_CMD_ issues. Signed-off-by: Wolfgang Denk --- board/cm5200/cmd_cm5200.c | 4 ++-- board/pcs440ep/pcs440ep.c | 4 ++-- cpu/arm926ejs/davinci/ether.c | 2 +- cpu/mpc512x/fec.c | 6 +++--- cpu/mpc512x/traps.c | 14 +++++++------- include/configs/IceCube.h | 1 - include/configs/TQM5200.h | 5 ++--- include/configs/cm5200.h | 39 +++++++++++++++++---------------------- 8 files changed, 34 insertions(+), 41 deletions(-) (limited to 'cpu') diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c index 5119a99ca23..fd9b914ae3d 100644 --- a/board/cm5200/cmd_cm5200.c +++ b/board/cm5200/cmd_cm5200.c @@ -27,7 +27,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_BSP) +#ifdef CONFIG_CMD_BSB int do_i2c(char *argv[]) { @@ -445,4 +445,4 @@ U_BOOT_CMD( "fkt usb\n" " - Test USB communication\n" ); -#endif /* CFG_CMD_BSP */ +#endif /* CONFIG_CMD_BSP */ diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 696423eacbc..e247fee0c17 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -879,7 +879,7 @@ int ide_preinit (void) } #endif -#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) +#if defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) void ide_set_reset (int idereset) { debug ("ide_reset(%d)\n", idereset); @@ -890,4 +890,4 @@ void ide_set_reset (int idereset) } udelay (10000); } -#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ +#endif /* defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ diff --git a/cpu/arm926ejs/davinci/ether.c b/cpu/arm926ejs/davinci/ether.c index 32e81d11d4e..766bc7d66c5 100644 --- a/cpu/arm926ejs/davinci/ether.c +++ b/cpu/arm926ejs/davinci/ether.c @@ -272,7 +272,7 @@ static int gen_auto_negotiate(int phy_addr) /* End of generic PHY functions */ -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) static int dm644x_mii_phy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short *value) { return(dm644x_eth_phy_read(addr, reg, value) ? 0 : 1); diff --git a/cpu/mpc512x/fec.c b/cpu/mpc512x/fec.c index 1c87a53859d..3c142a9e58b 100644 --- a/cpu/mpc512x/fec.c +++ b/cpu/mpc512x/fec.c @@ -17,10 +17,10 @@ DECLARE_GLOBAL_DATA_PTR; #define DEBUG 0 -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ defined(CONFIG_MPC512x_FEC) -#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) +#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) #error "CONFIG_MII has to be defined!" #endif @@ -626,7 +626,7 @@ int mpc512x_fec_initialize (bd_t * bis) sprintf (dev->name, "FEC ETHERNET"); eth_register (dev); -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register (dev->name, fec512x_miiphy_read, fec512x_miiphy_write); #endif diff --git a/cpu/mpc512x/traps.c b/cpu/mpc512x/traps.c index 40281a2cbb4..8455c92761b 100644 --- a/cpu/mpc512x/traps.c +++ b/cpu/mpc512x/traps.c @@ -106,7 +106,7 @@ MachineCheckException (struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -144,7 +144,7 @@ MachineCheckException (struct pt_regs *regs) void AlignmentException (struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -156,7 +156,7 @@ AlignmentException (struct pt_regs *regs) void ProgramCheckException (struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -168,7 +168,7 @@ ProgramCheckException (struct pt_regs *regs) void SoftEmuException (struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -181,7 +181,7 @@ SoftEmuException (struct pt_regs *regs) void UnknownException (struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -190,7 +190,7 @@ UnknownException (struct pt_regs *regs) _exception (0, regs); } -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#ifdef CONFIG_CMD_BEDBUG extern void do_bedbug_breakpoint (struct pt_regs *); #endif @@ -199,7 +199,7 @@ DebugException (struct pt_regs *regs) { printf ("Debugger trap at @ %lx\n", regs->nip ); show_regs (regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#ifdef CONFIG_CMD_BEDBUG do_bedbug_breakpoint (regs); #endif } diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 1a7167b481c..532615485c5 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -85,7 +85,6 @@ /* USB */ #define CONFIG_USB_OHCI_NEW -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE #define CFG_OHCI_BE_CONTROLLER #undef CFG_USB_OHCI_BOARD_INIT diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 8360d8c0d7c..3d9850023dd 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -131,8 +131,9 @@ /* USB */ #if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) #define CONFIG_USB_OHCI_NEW -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_USB #undef CFG_USB_OHCI_BOARD_INIT #define CFG_USB_OHCI_CPU_INIT @@ -140,8 +141,6 @@ #define CFG_USB_OHCI_SLOT_NAME "mpc5200" #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 -#else -#define ADD_USB_CMD 0 #endif #ifndef CONFIG_CAM5200 diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index 76628560e5a..56c0ecb4d97 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -35,27 +35,22 @@ /* * Supported commands */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_I2C | \ - CFG_CMD_FLASH | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_DIAG | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP | \ - CFG_CMD_BSP | \ - CFG_CMD_USB | \ - CFG_CMD_FAT | \ - CFG_CMD_JFFS2) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_USB /* * Serial console configuration @@ -344,7 +339,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From 6b309f22a724fad8418e811751a0741b893419cf Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 12 Aug 2007 20:35:49 +0200 Subject: Minor alignment of output Signed-off-by: Wolfgang Denk --- cpu/mpc512x/cpu.c | 2 +- cpu/nios/cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c index 3be565ad034..3f2e3ad3c00 100644 --- a/cpu/mpc512x/cpu.c +++ b/cpu/mpc512x/cpu.c @@ -42,7 +42,7 @@ int checkcpu (void) u32 spridr = immr->sysconf.spridr; char buf[32]; - puts("CPU: "); + puts("CPU: "); switch (spridr & 0xffff0000) { case SPR_5121E: diff --git a/cpu/nios/cpu.c b/cpu/nios/cpu.c index d2bb2c09d1d..51f42461a3c 100644 --- a/cpu/nios/cpu.c +++ b/cpu/nios/cpu.c @@ -34,7 +34,7 @@ int checkcpu (void) /* Get cpu version info */ val = rdctl (CTL_CPU_ID); - printf ("CPU: "); + printf ("CPU: "); printf ("%s", (val & 0x00008000) ? "Nios-16 " : "Nios-32 "); rev_major = (val>>12) & 0x07; rev_minor = (val>>4) & 0x0ff; -- cgit v1.3.1 From 77d19a8bf3b0b1e401cb9f23c81e2ef419705c1a Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 12 Aug 2007 21:34:34 +0200 Subject: Minor alignment of output, 2nd try. Also update CHANGELOG Signed-off-by: Wolfgang Denk --- cpu/mpc512x/cpu.c | 2 +- cpu/nios/cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c index 3f2e3ad3c00..accae6e066e 100644 --- a/cpu/mpc512x/cpu.c +++ b/cpu/mpc512x/cpu.c @@ -42,7 +42,7 @@ int checkcpu (void) u32 spridr = immr->sysconf.spridr; char buf[32]; - puts("CPU: "); + puts ("CPU: "); switch (spridr & 0xffff0000) { case SPR_5121E: diff --git a/cpu/nios/cpu.c b/cpu/nios/cpu.c index 51f42461a3c..5519e827804 100644 --- a/cpu/nios/cpu.c +++ b/cpu/nios/cpu.c @@ -34,7 +34,7 @@ int checkcpu (void) /* Get cpu version info */ val = rdctl (CTL_CPU_ID); - printf ("CPU: "); + puts ("CPU: "); printf ("%s", (val & 0x00008000) ? "Nios-16 " : "Nios-32 "); rev_major = (val>>12) & 0x07; rev_minor = (val>>4) & 0x0ff; -- cgit v1.3.1 From f0d1246ed7cb5a88522244c596d7ae7e6f161283 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Wed, 27 Jun 2007 13:34:26 +0200 Subject: atmel_mci: Use 512 byte blocksize if possible Instead of always using the largest blocksize the card supports, check if it can support smaller block sizes and use 512 bytes if possible. Most cards do support this, and other parts of u-boot seem to have trouble with block sizes different from 512 bytes. Also enable underrun/overrun protection. Signed-off-by: Haavard Skinnemoen Acked-by: Hans-Christian Egtvedt --- cpu/at32ap/atmel_mci.c | 21 +++++++++++++++++---- cpu/at32ap/atmel_mci.h | 4 ++++ 2 files changed, 21 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/at32ap/atmel_mci.c b/cpu/at32ap/atmel_mci.c index 9f62c0f14b8..bdca1c19f41 100644 --- a/cpu/at32ap/atmel_mci.c +++ b/cpu/at32ap/atmel_mci.c @@ -82,7 +82,9 @@ static void mci_set_mode(unsigned long hz, unsigned long blklen) blklen &= 0xfffc; mmci_writel(MR, (MMCI_BF(CLKDIV, clkdiv) - | MMCI_BF(BLKLEN, blklen))); + | MMCI_BF(BLKLEN, blklen) + | MMCI_BIT(RDPROOF) + | MMCI_BIT(WRPROOF))); } #define RESP_NO_CRC 1 @@ -225,7 +227,7 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, *buffer++ = data; wordcount++; } - } while(wordcount < (512 / 4)); + } while(wordcount < (mmc_blkdev.blksz / 4)); pr_debug("mmc: read %u words, waiting for BLKE\n", wordcount); @@ -243,7 +245,7 @@ out: fail: mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); - printf("mmc: bread failed, card status = ", card_status); + printf("mmc: bread failed, card status = %08x\n", card_status); goto out; } @@ -409,6 +411,7 @@ int mmc_init(int verbose) { struct mmc_cid cid; struct mmc_csd csd; + unsigned int max_blksz; int ret; /* Initialize controller */ @@ -444,7 +447,17 @@ int mmc_init(int verbose) sizeof(mmc_blkdev.product)); sprintf((char *)mmc_blkdev.revision, "%x %x", cid.prv >> 4, cid.prv & 0x0f); - mmc_blkdev.blksz = 1 << csd.read_bl_len; + + /* + * If we can't use 512 byte blocks, refuse to deal with the + * card. Tons of code elsewhere seems to depend on this. + */ + max_blksz = 1 << csd.read_bl_len; + if (max_blksz < 512 || (max_blksz > 512 && !csd.read_bl_partial)) { + printf("Card does not support 512 byte reads, aborting.\n"); + return -ENODEV; + } + mmc_blkdev.blksz = 512; mmc_blkdev.lba = (csd.c_size + 1) * (1 << (csd.c_size_mult + 2)); mci_set_mode(CFG_MMC_CLK_PP, mmc_blkdev.blksz); diff --git a/cpu/at32ap/atmel_mci.h b/cpu/at32ap/atmel_mci.h index 0ffbc4fd097..5b4f5c99b6d 100644 --- a/cpu/at32ap/atmel_mci.h +++ b/cpu/at32ap/atmel_mci.h @@ -57,6 +57,10 @@ #define MMCI_CLKDIV_SIZE 8 #define MMCI_PWSDIV_OFFSET 8 #define MMCI_PWSDIV_SIZE 3 +#define MMCI_RDPROOF_OFFSET 11 +#define MMCI_RDPROOF_SIZE 1 +#define MMCI_WRPROOF_OFFSET 12 +#define MMCI_WRPROOF_SIZE 1 #define MMCI_PDCPADV_OFFSET 14 #define MMCI_PDCPADV_SIZE 1 #define MMCI_PDCMODE_OFFSET 15 -- cgit v1.3.1 From 0ba8eed28b575626b17e0a7882f923b83e0d7584 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Mon, 13 Aug 2007 17:22:31 +0200 Subject: AVR32: Include instead of include/asm-avr32/div64.h was recently moved to include/div64.h, but cpu/at32ap/interrupts.c wasn't properly updated (an earlier version of the patch was merged perhaps?) This patch updates cpu/at32ap/interrupts.c so that the avr32 port compiles again. Signed-off-by: Haavard Skinnemoen --- cpu/at32ap/interrupts.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/at32ap/interrupts.c b/cpu/at32ap/interrupts.c index c9e04993c77..bef1f30d79d 100644 --- a/cpu/at32ap/interrupts.c +++ b/cpu/at32ap/interrupts.c @@ -20,8 +20,8 @@ * MA 02111-1307 USA */ #include +#include -#include #include #include #include -- cgit v1.3.1 From a08458303e7f9db67f296980036d3292c35cb45c Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Fri, 29 Jun 2007 18:38:51 +0200 Subject: atmel_mci: Fix data timeout value Calculate the data timeout based on values from the CSD instead of just using a hardcoded DTOR value. This is a backport of a similar fix in BSP 2.0, with one additional fix: the DTOCYC value is rounded up instead of down. Signed-off-by: Haavard Skinnemoen --- cpu/at32ap/atmel_mci.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'cpu') diff --git a/cpu/at32ap/atmel_mci.c b/cpu/at32ap/atmel_mci.c index bdca1c19f41..cf48be10ba4 100644 --- a/cpu/at32ap/atmel_mci.c +++ b/cpu/at32ap/atmel_mci.c @@ -56,6 +56,7 @@ #define MMC_DEFAULT_RCA 1 static unsigned int mmc_rca; +static int mmc_card_is_sd; static block_dev_desc_t mmc_blkdev; block_dev_desc_t *mmc_get_dev(int dev) @@ -373,6 +374,7 @@ static int sd_init_card(struct mmc_cid *cid, int verbose) mmc_rca = resp[0] >> 16; if (verbose) printf("SD Card detected (RCA %u)\n", mmc_rca); + mmc_card_is_sd = 1; return 0; } @@ -407,6 +409,59 @@ static int mmc_init_card(struct mmc_cid *cid, int verbose) return ret; } +static void mci_set_data_timeout(struct mmc_csd *csd) +{ + static const unsigned int dtomul_to_shift[] = { + 0, 4, 7, 8, 10, 12, 16, 20, + }; + static const unsigned int taac_exp[] = { + 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, + }; + static const unsigned int taac_mant[] = { + 0, 10, 12, 13, 15, 60, 25, 30, + 35, 40, 45, 50, 55, 60, 70, 80, + }; + unsigned int timeout_ns, timeout_clks; + unsigned int e, m; + unsigned int dtocyc, dtomul; + unsigned int shift; + u32 dtor; + + e = csd->taac & 0x07; + m = (csd->taac >> 3) & 0x0f; + + timeout_ns = (taac_exp[e] * taac_mant[m] + 9) / 10; + timeout_clks = csd->nsac * 100; + + timeout_clks += (((timeout_ns + 9) / 10) + * ((CFG_MMC_CLK_PP + 99999) / 100000) + 9999) / 10000; + if (!mmc_card_is_sd) + timeout_clks *= 10; + else + timeout_clks *= 100; + + dtocyc = timeout_clks; + dtomul = 0; + while (dtocyc > 15 && dtomul < 8) { + dtomul++; + shift = dtomul_to_shift[dtomul]; + dtocyc = (timeout_clks + (1 << shift) - 1) >> shift; + } + + if (dtomul >= 8) { + dtomul = 7; + dtocyc = 15; + puts("Warning: Using maximum data timeout\n"); + } + + dtor = (MMCI_BF(DTOMUL, dtomul) + | MMCI_BF(DTOCYC, dtocyc)); + mmci_writel(DTOR, dtor); + + printf("mmc: Using %u cycles data timeout (DTOR=0x%x)\n", + dtocyc << shift, dtor); +} + int mmc_init(int verbose) { struct mmc_cid cid; @@ -421,6 +476,8 @@ int mmc_init(int verbose) mmci_writel(IDR, ~0UL); mci_set_mode(CFG_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); + mmc_card_is_sd = 0; + ret = sd_init_card(&cid, verbose); if (ret) { mmc_rca = MMC_DEFAULT_RCA; @@ -436,6 +493,8 @@ int mmc_init(int verbose) if (verbose) mmc_dump_csd(&csd); + mci_set_data_timeout(&csd); + /* Initialize the blockdev structure */ mmc_blkdev.if_type = IF_TYPE_MMC; mmc_blkdev.part_type = PART_TYPE_DOS; -- cgit v1.3.1 From 29372ff38c5baab7d0e3a8c14fe11fa194a38704 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Fri, 27 Jul 2007 01:50:47 -0500 Subject: mpc85xx L2 cache reporting and SRAM relocation option. Allow debugger to override flash cs0/cs1 settings to enable alternate boot regions Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- cpu/mpc85xx/cpu_init.c | 65 ++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 47 insertions(+), 18 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 9517146ed23..888417f864b 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -1,4 +1,6 @@ /* + * Copyright 2007 Freescale Semiconductor. + * * (C) Copyright 2003 Motorola Inc. * Modified by Xianghua Xiao, X.Xiao@motorola.com * @@ -133,15 +135,18 @@ void cpu_init_f (void) #endif /* now restrict to preliminary range */ + /* if cs1 is already set via debugger, leave cs0/cs1 alone */ + if (! memctl->br1 & 1) { #if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM) - memctl->br0 = CFG_BR0_PRELIM; - memctl->or0 = CFG_OR0_PRELIM; + memctl->br0 = CFG_BR0_PRELIM; + memctl->or0 = CFG_OR0_PRELIM; #endif #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) - memctl->or1 = CFG_OR1_PRELIM; - memctl->br1 = CFG_BR1_PRELIM; + memctl->or1 = CFG_OR1_PRELIM; + memctl->br1 = CFG_BR1_PRELIM; #endif + } #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) memctl->or2 = CFG_OR2_PRELIM; @@ -185,16 +190,23 @@ void cpu_init_f (void) * The newer 8548, etc, parts have twice as much cache, but * use the same bit-encoding as the older 8555, etc, parts. * - * FIXME: Use PVR_VER(pvr) == 1 test here instead of SVR_VER()? */ int cpu_init_r(void) { + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; + +#ifdef CONFIG_CLEAR_LAW0 + /* clear alternate boot location LAW (used for sdram, or ddr bank) */ + ecm->lawar0 = 0; +#endif + #if defined(CONFIG_L2_CACHE) - volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache; volatile uint cache_ctl; uint svr, ver; + uint l2srbar; svr = get_svr(); ver = SVR_VER(svr); @@ -204,30 +216,47 @@ int cpu_init_r(void) switch (cache_ctl & 0x30000000) { case 0x20000000: - if (ver == SVR_8548 || ver == SVR_8548_E) { + if (ver == SVR_8548 || ver == SVR_8548_E || + ver == SVR_8544) { printf ("L2 cache 512KB:"); + /* set L2E=1, L2I=1, & L2SRAM=0 */ + cache_ctl = 0xc0000000; } else { printf ("L2 cache 256KB:"); + /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ + cache_ctl = 0xc8000000; } break; - case 0x00000000: case 0x10000000: + printf ("L2 cache 256KB:"); + if (ver == SVR_8544 || ver == SVR_8544_E) { + cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ + } + break; case 0x30000000: + case 0x00000000: default: printf ("L2 cache unknown size (0x%08x)\n", cache_ctl); return -1; } - asm("msync;isync"); - l2cache->l2ctl = 0x68000000; /* invalidate */ - cache_ctl = l2cache->l2ctl; - asm("msync;isync"); - - l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */ - cache_ctl = l2cache->l2ctl; - asm("msync;isync"); - - printf(" enabled\n"); + if (l2cache->l2ctl & 0x80000000) { + printf(" already enabled."); + l2srbar = l2cache->l2srbar0; +#ifdef CFG_INIT_L2_ADDR + if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) { + l2srbar = CFG_INIT_L2_ADDR; + l2cache->l2srbar0 = l2srbar; + printf(" Moving to 0x%08x", CFG_INIT_L2_ADDR); + } +#endif /* CFG_INIT_L2_ADDR */ + puts("\n"); + } else { + asm("msync;isync"); + l2cache->l2ctl = cache_ctl; /* invalidate & enable */ + asm("msync;isync"); + printf(" enabled\n"); + } #else printf("L2 cache: disabled\n"); #endif -- cgit v1.3.1 From 40c7f9b0de4e300370adfc704128fa0f79a143b6 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Fri, 27 Jul 2007 01:50:48 -0500 Subject: 85xx allow debugger to configure ddr. Only check for mpc8548 rev 1 when compiled for 8548. Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- cpu/mpc85xx/spd_sdram.c | 48 +++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 45 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 3777f49adcc..d98455401a0 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor. * (C) Copyright 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) * @@ -173,7 +173,6 @@ spd_sdram(void) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_ddr_t *ddr = &immap->im_ddr; - volatile ccsr_gur_t *gur = &immap->im_gur; spd_eeprom_t spd; unsigned int n_ranks; unsigned int rank_density; @@ -189,7 +188,7 @@ spd_sdram(void) unsigned int max_data_rate, effective_data_rate; unsigned int busfreq; unsigned sdram_cfg; - unsigned int memsize; + unsigned int memsize = 0; unsigned char caslat, caslat_ctrl; unsigned int trfc, trfc_clk, trfc_low, trfc_high; unsigned int trcd_clk; @@ -204,6 +203,46 @@ spd_sdram(void) unsigned int mode_caslat; unsigned char sdram_type; unsigned char d_init; + unsigned int bnds; + + /* + * Skip configuration if already configured. + * memsize is determined from last configured chip select. + */ + if (ddr->cs0_config & 0x80000000) { + debug(" cs0 already configured, bnds=%x\n",ddr->cs0_bnds); + bnds = 0xfff & ddr->cs0_bnds; + if (bnds < 0xff) { /* do not add if at top of 4G */ + memsize = (bnds + 1) << 4; + } + } + if (ddr->cs1_config & 0x80000000) { + debug(" cs1 already configured, bnds=%x\n",ddr->cs1_bnds); + bnds = 0xfff & ddr->cs1_bnds; + if (bnds < 0xff) { /* do not add if at top of 4G */ + memsize = (bnds + 1) << 4; /* assume ordered bnds */ + } + } + if (ddr->cs2_config & 0x80000000) { + debug(" cs2 already configured, bnds=%x\n",ddr->cs2_bnds); + bnds = 0xfff & ddr->cs2_bnds; + if (bnds < 0xff) { /* do not add if at top of 4G */ + memsize = (bnds + 1) << 4; + } + } + if (ddr->cs3_config & 0x80000000) { + debug(" cs3 already configured, bnds=%x\n",ddr->cs3_bnds); + bnds = 0xfff & ddr->cs3_bnds; + if (bnds < 0xff) { /* do not add if at top of 4G */ + memsize = (bnds + 1) << 4; + } + } + + if (memsize) { + printf(" Reusing current %dMB configuration\n",memsize); + memsize = setup_laws_and_tlbs(memsize); + return memsize << 20; + } /* * Read SPD information. @@ -262,6 +301,7 @@ spd_sdram(void) return 0; } +#ifdef CONFIG_MPC8548 /* * Adjust DDR II IO voltage biasing. * Only 8548 rev 1 needs the fix @@ -269,9 +309,11 @@ spd_sdram(void) if ((SVR_VER(get_svr()) == SVR_8548_E) && (SVR_MJREV(get_svr()) == 1) && (spd.mem_type == SPD_MEMTYPE_DDR2)) { + volatile ccsr_gur_t *gur = &immap->im_gur; gur->ddrioovcr = (0x80000000 /* Enable */ | 0x10000000);/* VSEL to 1.8V */ } +#endif /* * Determine the size of each Rank in bytes. -- cgit v1.3.1 From 61a21e980a7b9188424d04f1c265fdc5c21c7e85 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 14 Aug 2007 01:34:21 -0500 Subject: 85xx start.S cleanup and exception support From: Ed Swarthout Support external interrupts from platform to eliminate system hangs. Define CONFIG_INTERRUPTS board configure option to enable. Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC. Remove extra cpu initialization redundant with hardware initialization. Whitespace cleanup. Define and use _START_OFFSET consistent with other processors using ppc_asm.tmpl Move additional code from .text to boot page to make room for exception vectors at start of image. Handle Machine Check, External and Critical exceptions. Fix e500 machine check error determination in traps.c TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half. Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- cpu/mpc85xx/interrupts.c | 33 +++ cpu/mpc85xx/start.S | 485 +++++++++++++++++++------------------------- cpu/mpc85xx/traps.c | 99 +++++++-- include/asm-ppc/processor.h | 3 + include/mpc85xx.h | 8 +- 5 files changed, 326 insertions(+), 302 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c index dc246dca028..bf737d62286 100644 --- a/cpu/mpc85xx/interrupts.c +++ b/cpu/mpc85xx/interrupts.c @@ -89,6 +89,39 @@ int interrupt_init (void) mtspr(SPRN_TCR, TCR_PIE); set_dec (decrementer_count); set_msr (get_msr () | MSR_EE); + +#ifdef CONFIG_INTERRUPTS + volatile ccsr_pic_t *pic = &immr->im_pic; + + pic->iivpr1 = 0x810002; /* 50220 enable ecm interrupts */ + debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1); + + pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ + debug("iivpr2@%x = %x\n",&pic->iivpr2, pic->iivpr2); + + pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */ + debug("iivpr3@%x = %x\n",&pic->iivpr3, pic->iivpr3); + +#ifdef CONFIG_PCI1 + pic->iivpr8 = 0x810008; /* enable pci1 interrupts */ + debug("iivpr8@%x = %x\n",&pic->iivpr8, pic->iivpr8); +#endif +#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2) + pic->iivpr9 = 0x810009; /* enable pci1 interrupts */ + debug("iivpr9@%x = %x\n",&pic->iivpr9, pic->iivpr9); +#endif +#ifdef CONFIG_PCIE1 + pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */ + debug("iivpr10@%x = %x\n",&pic->iivpr10, pic->iivpr10); +#endif +#ifdef CONFIG_PCIE3 + pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */ + debug("iivpr11@%x = %x\n",&pic->iivpr11, pic->iivpr11); +#endif + + pic->ctpr=0; /* 40080 clear current task priority register */ +#endif + return (0); } diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 77c155c5bdc..9dfd38d6a0d 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -1,7 +1,6 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor. * Copyright (C) 2003 Motorola,Inc. - * Xianghua Xiao * * See file CREDITS for list of people who contributed to this * project. @@ -46,7 +45,7 @@ #endif #undef MSR_KERNEL -#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ +#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ /* * Set up GOT: Global Offset Table @@ -80,110 +79,37 @@ * */ - .section .bootpg,"ax" - .globl _start_e500 + .section .bootpg,"ax" + .globl _start_e500 _start_e500: - mfspr r0, PVR - lis r1, PVR_85xx_REV1@h - ori r1, r1, PVR_85xx_REV1@l - cmpw r0, r1 - bne 1f - /* Semi-bogus errata fixup for Rev 1 */ - li r0,0x2000 - mtspr 977,r0 +/* clear registers/arrays not reset by hardware */ - /* - * Before invalidating MMU L1/L2, read TLB1 Entry 0 and then - * write it back immediately to fixup a Rev 1 bug (Errata CPU4) - * for this initial TLB1 entry 0, otherwise the TLB1 entry 0 - * will be invalidated (incorrectly). - */ - lis r2,0x1000 - mtspr MAS0,r2 - tlbre - tlbwe - isync - -1: - /* - * Clear and set up some registers. - * Note: Some registers need strict synchronization by - * sync/mbar/msync/isync when being "mtspr". - * BookE: isync before PID,tlbivax,tlbwe - * BookE: isync after MSR,PID; msync_isync after tlbivax & tlbwe - * E500: msync,isync before L1CSR0 - * E500: isync after BBEAR,BBTAR,BUCSR,DBCR0,DBCR1,HID0,HID1, - * L1CSR0, L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2], - * SPEFCSR - */ - - /* invalidate d-cache */ - mfspr r0,L1CSR0 - ori r0,r0,0x0002 - msync - isync - mtspr L1CSR0,r0 - isync - - /* disable d-cache */ - li r0,0x0 - mtspr L1CSR0,r0 - - /* invalidate i-cache */ - mfspr r0,L1CSR1 - ori r0,r0,0x0002 - mtspr L1CSR1,r0 - isync - - /* disable i-cache */ - li r0,0x0 - mtspr L1CSR1,r0 - isync - - /* clear registers */ - li r0,0 - mtspr SRR0,r0 - mtspr SRR1,r0 - mtspr CSRR0,r0 - mtspr CSRR1,r0 - mtspr MCSRR0,r0 - mtspr MCSRR1,r0 - - mtspr ESR,r0 - mtspr MCSR,r0 - mtspr DEAR,r0 - - /* not needed and conflicts with some debuggers */ - /* mtspr DBCR0,r0 */ - mtspr DBCR1,r0 - mtspr DBCR2,r0 - /* not needed and conflicts with some debuggers */ - /* mtspr IAC1,r0 */ - /* mtspr IAC2,r0 */ - mtspr DAC1,r0 - mtspr DAC2,r0 + /* L1 */ + li r0,2 + mtspr L1CSR0,r0 /* invalidate d-cache */ + mtspr L1CSR1,r0 /* invalidate i-cache */ mfspr r1,DBSR mtspr DBSR,r1 /* Clear all valid bits */ - mtspr PID0,r0 - mtspr PID1,r0 - mtspr PID2,r0 - mtspr TCR,r0 + /* + * Enable L1 Caches early + * + */ - mtspr BUCSR,r0 /* disable branch prediction */ - mtspr MAS4,r0 - mtspr MAS6,r0 -#if defined(CONFIG_ENABLE_36BIT_PHYS) - mtspr MAS7,r0 -#endif + lis r2,L1CSR0_CPE@H /* enable parity */ + ori r2,r2,L1CSR0_DCE + mtspr L1CSR0,r2 /* enable L1 Dcache */ + isync + mtspr L1CSR1,r2 /* enable L1 Icache */ isync + msync /* Setup interrupt vectors */ lis r1,TEXT_BASE@h - mtspr IVPR, r1 + mtspr IVPR,r1 li r1,0x0100 mtspr IVOR0,r1 /* 0: Critical input */ @@ -217,26 +143,6 @@ _start_e500: li r1,0x0f00 mtspr IVOR15,r1 /* 15: Debug */ - /* - * Invalidate MMU L1/L2 - * - * Note: There is a fixup earlier for Errata CPU4 on - * Rev 1 parts that must precede this MMU invalidation. - */ - li r2, 0x001e - mtspr MMUCSR0, r2 - isync - - /* - * Invalidate all TLB0 entries. - */ - li r3,4 - li r4,0 - tlbivax r4,r3 - /* - * To avoid REV1 Errata CPU6 issues, make sure - * the instruction following tlbivax is not a store. - */ /* * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e. @@ -254,14 +160,14 @@ _start_e500: lwzu r4,0(r5) /* how many TLB1 entries we actually use */ mtctr r4 -0: lwzu r0,4(r5) - lwzu r1,4(r5) - lwzu r2,4(r5) - lwzu r3,4(r5) - mtspr MAS0,r0 - mtspr MAS1,r1 - mtspr MAS2,r2 - mtspr MAS3,r3 +0: lwzu r6,4(r5) + lwzu r7,4(r5) + lwzu r8,4(r5) + lwzu r9,4(r5) + mtspr MAS0,r6 + mtspr MAS1,r7 + mtspr MAS2,r8 + mtspr MAS3,r9 isync msync tlbwe @@ -271,22 +177,22 @@ _start_e500: 1: #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) /* Special sequence needed to update CCSRBAR itself */ - lis r4, CFG_CCSRBAR_DEFAULT@h - ori r4, r4, CFG_CCSRBAR_DEFAULT@l + lis r4,CFG_CCSRBAR_DEFAULT@h + ori r4,r4,CFG_CCSRBAR_DEFAULT@l - lis r5, CFG_CCSRBAR@h - ori r5, r5, CFG_CCSRBAR@l + lis r5,CFG_CCSRBAR@h + ori r5,r5,CFG_CCSRBAR@l srwi r6,r5,12 - stw r6, 0(r4) + stw r6,0(r4) isync - lis r5, 0xffff + lis r5,0xffff ori r5,r5,0xf000 - lwz r5, 0(r5) + lwz r5,0(r5) isync - lis r3, CFG_CCSRBAR@h - lwz r5, CFG_CCSRBAR@l(r3) + lis r3,CFG_CCSRBAR@h + lwz r5,CFG_CCSRBAR@l(r3) isync #endif @@ -300,8 +206,8 @@ _start_e500: lwzu r5,0(r6) /* how many windows we actually use */ mtctr r5 - li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */ - li r1,0x0c30 + li r2,0x0c28 /* the first pair is reserved for */ + li r1,0x0c30 /* boot-over-rio-or-pci */ 0: lwzu r4,4(r6) lwzu r3,4(r6) @@ -311,31 +217,6 @@ _start_e500: addi r1,r1,0x0020 bdnz 0b - /* Jump out the last 4K page and continue to 'normal' start */ -1: bl 3f - b _start - -3: li r0,0 - mtspr SRR1,r0 /* Keep things disabled for now */ - mflr r1 - mtspr SRR0,r1 - rfi - -/* - * r3 - 1st arg to board_init(): IMMP pointer - * r4 - 2nd arg to board_init(): boot flag - */ - .text - .long 0x27051956 /* U-BOOT Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii CONFIG_IDENT_STRING, "\0" - - . = EXC_OFF_SYS_RESET - .globl _start -_start: /* Clear and set up some registers. */ li r0,0x0000 lis r1,0xffff @@ -354,17 +235,14 @@ _start: /* Enable Time Base and Select Time Base Clock */ lis r0,HID0_EMCP@h /* Enable machine check */ - ori r0,r0,0x4000 /* time base is processor clock */ #if defined(CONFIG_ENABLE_36BIT_PHYS) - ori r0,r0,0x0080 /* enable MAS7 updates */ + ori r0,r0,(HID0_TBEN|HID0_ENMAS7)@l /* Enable Timebase & MAS7 */ +#else + ori r0,r0,HID0_TBEN@l /* enable Timebase */ #endif mtspr HID0,r0 -#if defined(CONFIG_ADDR_STREAMING) - li r0,0x3000 -#else - li r0,0x1000 -#endif + li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ mtspr HID1,r0 /* Enable Branch Prediction */ @@ -382,35 +260,56 @@ _start: mtspr DBCR0,r0 #endif -/* L1 DCache is used for initial RAM */ - mfspr r2, L1CSR0 - ori r2, r2, 0x0003 - oris r2, r2, 0x0001 - mtspr L1CSR0, r2 /* enable/invalidate L1 Dcache */ + /* Jump out the last 4K page and continue to 'normal' start */ + bl 3f + b _start_cont + +3: li r0,0 + mtspr SRR1,r0 /* Keep things disabled for now */ + mflr r1 + mtspr SRR0,r1 + rfi isync + + .text + .globl _start +_start: + .long 0x27051956 /* U-BOOT Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" + + .align 4 + .globl _start_cont +_start_cont: + +/* L1 DCache is used for initial RAM */ + /* Allocate Initial RAM in data cache. */ - lis r3, CFG_INIT_RAM_ADDR@h - ori r3, r3, CFG_INIT_RAM_ADDR@l - li r2, 512 /* 512*32=16K */ + lis r3,CFG_INIT_RAM_ADDR@h + ori r3,r3,CFG_INIT_RAM_ADDR@l + li r2,512 /* 512*32=16K */ mtctr r2 - li r0, 0 + li r0,0 1: - dcbz r0, r3 - dcbtls 0,r0, r3 - addi r3, r3, 32 + dcbz r0,r3 + dcbtls 0,r0,r3 + addi r3,r3,32 bdnz 1b #ifndef CFG_RAMBOOT /* Calculate absolute address in FLASH and jump there */ /*--------------------------------------------------------------*/ - lis r3, CFG_MONITOR_BASE@h - ori r3, r3, CFG_MONITOR_BASE@l - addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET + lis r3,CFG_MONITOR_BASE@h + ori r3,r3,CFG_MONITOR_BASE@l + addi r3,r3,in_flash - _start + _START_OFFSET mtlr r3 blr - + .global in_flash in_flash: #endif /* CFG_RAMBOOT */ @@ -424,26 +323,24 @@ in_flash: stwu r1,-8(r1) /* Save back chain and move SP */ lis r0,RESET_VECTOR@h /* Address of reset vector */ - ori r0,r0, RESET_VECTOR@l + ori r0,r0,RESET_VECTOR@l stwu r1,-8(r1) /* Save back chain and move SP */ stw r0,+12(r1) /* Save return addr (underflow vect) */ GET_GOT bl cpu_init_f - bl icache_enable bl board_init_f isync -/* --FIXME-- machine check with MCSRRn and rfmci */ - + . = EXC_OFF_SYS_RESET .globl _start_of_vectors _start_of_vectors: -#if 0 + /* Critical input. */ - CRIT_EXCEPTION(0x0100, CritcalInput, CritcalInputException) -#endif -/* Machine check --FIXME-- Should be MACH_EXCEPTION */ - CRIT_EXCEPTION(0x0200, MachineCheck, MachineCheckException) + CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException) + +/* Machine check */ + MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) /* Data Storage exception. */ STD_EXCEPTION(0x0300, DataStorage, UnknownException) @@ -452,7 +349,7 @@ _start_of_vectors: STD_EXCEPTION(0x0400, InstStorage, UnknownException) /* External Interrupt exception. */ - STD_EXCEPTION(0x0500, ExtInterrupt, UnknownException) + STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException) /* Alignment exception. */ . = 0x0600 @@ -469,8 +366,8 @@ Alignment: mtlr r6 blrl .L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + .long AlignmentException - _start + _START_OFFSET + .long int_return - _start + _START_OFFSET /* Program check exception */ . = 0x0700 @@ -483,8 +380,8 @@ ProgramCheck: mtlr r6 blrl .L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET + .long ProgramCheckException - _start + _START_OFFSET + .long int_return - _start + _START_OFFSET /* No FPU on MPC85xx. This exception is not supposed to happen. */ @@ -496,23 +393,23 @@ ProgramCheck: * r3-... arguments */ SystemCall: - addis r11,r0,0 /* get functions table addr */ - ori r11,r11,0 /* Note: this code is patched in trap_init */ - addis r12,r0,0 /* get number of functions */ + addis r11,r0,0 /* get functions table addr */ + ori r11,r11,0 /* Note: this code is patched in trap_init */ + addis r12,r0,0 /* get number of functions */ ori r12,r12,0 - cmplw 0, r0, r12 + cmplw 0,r0,r12 bge 1f - rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ + rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ add r11,r11,r0 lwz r11,0(r11) - li r20,0xd00-4 /* Get stack pointer */ + li r20,0xd00-4 /* Get stack pointer */ lwz r12,0(r20) - subi r12,r12,12 /* Adjust stack pointer */ + subi r12,r12,12 /* Adjust stack pointer */ li r0,0xc00+_end_back-SystemCall - cmplw 0, r0, r12 /* Check stack overflow */ + cmplw 0,r0,r12 /* Check stack overflow */ bgt 1f stw r12,0(r20) @@ -570,7 +467,7 @@ _end_back: _end_of_vectors: - . = 0x2100 + . = . + (0x100 - ( . & 0xff )) /* align for debug */ /* * This code finishes saving the registers to the exception frame @@ -655,26 +552,58 @@ crit_return: REST_GPR(31, r1) lwz r2,_NIP(r1) /* Restore environment */ lwz r0,_MSR(r1) - mtspr 990,r2 /* SRR2 */ - mtspr 991,r0 /* SRR3 */ + mtspr SPRN_CSRR0,r2 + mtspr SPRN_CSRR1,r0 lwz r0,GPR0(r1) lwz r2,GPR2(r1) lwz r1,GPR1(r1) SYNC rfci +mck_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SPRN_MCSRR0,r2 + mtspr SPRN_MCSRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfmci + /* Cache functions. */ invalidate_icache: mfspr r0,L1CSR1 - ori r0,r0,0x0002 + ori r0,r0,L1CSR1_ICFI + msync + isync mtspr L1CSR1,r0 isync - blr /* entire I cache */ + blr /* entire I cache */ invalidate_dcache: mfspr r0,L1CSR0 - ori r0,r0,0x0002 + ori r0,r0,L1CSR0_DCFI msync isync mtspr L1CSR0,r0 @@ -697,9 +626,9 @@ icache_enable: .globl icache_disable icache_disable: mfspr r0,L1CSR1 - lis r1,0xfffffffe@h - ori r1,r1,0xfffffffe@l - and r0,r0,r1 + lis r3,0 + ori r3,r3,L1CSR1_ICE + andc r0,r0,r3 mtspr L1CSR1,r0 isync blr @@ -707,7 +636,7 @@ icache_disable: .globl icache_status icache_status: mfspr r3,L1CSR1 - andi. r3,r3,1 + andi. r3,r3,L1CSR1_ICE blr .globl dcache_enable @@ -727,12 +656,10 @@ dcache_enable: .globl dcache_disable dcache_disable: - mfspr r0,L1CSR0 - lis r1,0xfffffffe@h - ori r1,r1,0xfffffffe@l - and r0,r0,r1 - msync - isync + mfspr r3,L1CSR0 + lis r4,0 + ori r4,r4,L1CSR0_DCE + andc r3,r3,r4 mtspr L1CSR0,r0 isync blr @@ -740,27 +667,27 @@ dcache_disable: .globl dcache_status dcache_status: mfspr r3,L1CSR0 - andi. r3,r3,1 + andi. r3,r3,L1CSR0_DCE blr .globl get_pir get_pir: - mfspr r3, PIR + mfspr r3,PIR blr .globl get_pvr get_pvr: - mfspr r3, PVR + mfspr r3,PVR blr .globl get_svr get_svr: - mfspr r3, SVR + mfspr r3,SVR blr .globl wr_tcr wr_tcr: - mtspr TCR, r3 + mtspr TCR,r3 blr /*------------------------------------------------------------------------------- */ @@ -913,16 +840,16 @@ ppcSync: */ .globl relocate_code relocate_code: - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Init Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ + mr r1,r3 /* Set new stack pointer */ + mr r9,r4 /* Save copy of Init Data pointer */ + mr r10,r5 /* Save copy of Destination Address */ - mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l + mr r3,r5 /* Destination Address */ + lis r4,CFG_MONITOR_BASE@h /* Source Address */ + ori r4,r4,CFG_MONITOR_BASE@l lwz r5,GOT(__init_end) sub r5,r5,r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6,CFG_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: @@ -931,12 +858,12 @@ relocate_code: * * Offset: */ - sub r15, r10, r4 + sub r15,r10,r4 /* First our own GOT */ - add r14, r14, r15 + add r14,r14,r15 /* the the one used by the C code */ - add r30, r30, r15 + add r30,r30,r15 /* * Now relocate code @@ -997,10 +924,10 @@ relocate_code: * initialization, now running from RAM. */ - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + addi r0,r10,in_ram - _start + _START_OFFSET mtlr r0 blr /* NEVER RETURNS! */ - + .globl in_ram in_ram: /* @@ -1044,19 +971,19 @@ clear_bss: lwz r3,GOT(__bss_start) lwz r4,GOT(_end) - cmplw 0, r3, r4 + cmplw 0,r3,r4 beq 6f - li r0, 0 + li r0,0 5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 + stw r0,0(r3) + addi r3,r3,4 + cmplw 0,r3,r4 bne 5b 6: - mr r3, r9 /* Init Data pointer */ - mr r4, r10 /* Destination Address */ + mr r3,r9 /* Init Data pointer */ + mr r4,r10 /* Destination Address */ bl board_init_r /* @@ -1067,52 +994,54 @@ clear_bss: */ .globl trap_init trap_init: - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) + lwz r7,GOT(_start_of_vectors) + lwz r8,GOT(_end_of_vectors) - li r9, 0x100 /* reset vector always at 0x100 */ + li r9,0x100 /* reset vector always at 0x100 */ - cmplw 0, r7, r8 + cmplw 0,r7,r8 bgelr /* return if r7>=r8 - just in case */ mflr r4 /* save link register */ 1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 + lwz r0,0(r7) + stw r0,0(r9) + addi r7,r7,4 + addi r9,r9,4 + cmplw 0,r7,r8 bne 1b /* * relocate `hdlr' and `int_return' entries */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + li r7,.L_CriticalInput - _start + _START_OFFSET bl trap_reloc - li r7, .L_DataStorage - _start + EXC_OFF_SYS_RESET + li r7,.L_MachineCheck - _start + _START_OFFSET bl trap_reloc - li r7, .L_InstStorage - _start + EXC_OFF_SYS_RESET + li r7,.L_DataStorage - _start + _START_OFFSET bl trap_reloc - li r7, .L_ExtInterrupt - _start + EXC_OFF_SYS_RESET + li r7,.L_InstStorage - _start + _START_OFFSET bl trap_reloc - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + li r7,.L_ExtInterrupt - _start + _START_OFFSET bl trap_reloc - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + li r7,.L_Alignment - _start + _START_OFFSET bl trap_reloc - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + li r7,.L_ProgramCheck - _start + _START_OFFSET bl trap_reloc - li r7, .L_Decrementer - _start + EXC_OFF_SYS_RESET + li r7,.L_FPUnavailable - _start + _START_OFFSET bl trap_reloc - li r7, .L_IntervalTimer - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET + li r7,.L_Decrementer - _start + _START_OFFSET + bl trap_reloc + li r7,.L_IntervalTimer - _start + _START_OFFSET + li r8,_end_of_vectors - _start + _START_OFFSET 2: bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 + addi r7,r7,0x100 /* next exception vector */ + cmplw 0,r7,r8 blt 2b lis r7,0x0 - mtspr IVPR, r7 + mtspr IVPR,r7 mtlr r4 /* restore link register */ blr @@ -1121,13 +1050,13 @@ trap_init: * Function: relocate entries for one exception vector */ trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) + lwz r0,0(r7) /* hdlr ... */ + add r0,r0,r3 /* ... += dest_addr */ + stw r0,0(r7) - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) + lwz r0,4(r7) /* int_return ... */ + add r0,r0,r3 /* ... += dest_addr */ + stw r0,4(r7) blr @@ -1135,13 +1064,13 @@ trap_reloc: .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ - lis r3, (CFG_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l - li r2,512 - mtctr r2 -1: icbi r0, r3 - dcbi r0, r3 - addi r3, r3, 32 + lis r3,(CFG_INIT_RAM_ADDR & ~31)@h + ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l + li r4,512 + mtctr r4 +1: icbi r0,r3 + dcbi r0,r3 + addi r3,r3,32 bdnz 1b sync /* Wait for all icbi to complete on bus */ isync diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c index 9cd621c3ac4..efc80c7aee7 100644 --- a/cpu/mpc85xx/traps.c +++ b/cpu/mpc85xx/traps.c @@ -1,6 +1,7 @@ /* * linux/arch/ppc/kernel/traps.c * + * Copyright 2007 Freescale Semiconductor. * Copyright (C) 2003 Motorola * Modified by Xianghua Xiao(x.xiao@motorola.com) * @@ -145,10 +146,13 @@ CritcalInputException(struct pt_regs *regs) panic("Critical Input Exception"); } +int machinecheck_count = 0; +int machinecheck_error = 0; void MachineCheckException(struct pt_regs *regs) { unsigned long fixup; + unsigned int mcsr, mcsrr0, mcsrr1, mcar; /* Probing PCI using config cycles cause this exception * when a device is not present. Catch it and return to @@ -159,34 +163,62 @@ MachineCheckException(struct pt_regs *regs) return; } + mcsrr0 = mfspr(SPRN_MCSRR0); + mcsrr1 = mfspr(SPRN_MCSRR1); + mcsr = mfspr(SPRN_MCSR); + mcar = mfspr(SPRN_MCAR); + + machinecheck_count++; + machinecheck_error=1; + #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif printf("Machine check in kernel mode.\n"); - printf("Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - printf("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13): - printf("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - printf("Data parity signal\n"); - break; - case (0x80000000>>15): - printf("Address parity signal\n"); - break; - default: - printf("Unknown values in msr\n"); - } + printf("Caused by (from mcsr): "); + printf("mcsr = 0x%08x\n", mcsr); + if (mcsr & 0x80000000) + printf("Machine check input pin\n"); + if (mcsr & 0x40000000) + printf("Instruction cache parity error\n"); + if (mcsr & 0x20000000) + printf("Data cache push parity error\n"); + if (mcsr & 0x10000000) + printf("Data cache parity error\n"); + if (mcsr & 0x00000080) + printf("Bus instruction address error\n"); + if (mcsr & 0x00000040) + printf("Bus Read address error\n"); + if (mcsr & 0x00000020) + printf("Bus Write address error\n"); + if (mcsr & 0x00000010) + printf("Bus Instruction data bus error\n"); + if (mcsr & 0x00000008) + printf("Bus Read data bus error\n"); + if (mcsr & 0x00000004) + printf("Bus Write bus error\n"); + if (mcsr & 0x00000002) + printf("Bus Instruction parity error\n"); + if (mcsr & 0x00000001) + printf("Bus Read parity error\n"); + show_regs(regs); + printf("MCSR=0x%08x \tMCSRR0=0x%08x \nMCSRR1=0x%08x \tMCAR=0x%08x\n", + mcsr, mcsrr0, mcsrr1, mcar); print_backtrace((unsigned long *)regs->gpr[1]); - panic("machine check"); + if (machinecheck_count > 10) { + panic("machine check count too high\n"); + } + + if (machinecheck_count > 1) { + regs->nip += 4; /* skip offending instruction */ + printf("Skipping current instr, Returning to 0x%08x\n", + regs->nip); + } else { + printf("Returning back to 0x%08x\n",regs->nip); + } } void @@ -253,6 +285,33 @@ UnknownException(struct pt_regs *regs) regs->nip, regs->msr, regs->trap); _exception(0, regs); } +void +ExtIntException(struct pt_regs *regs) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_pic_t *pic = &immap->im_pic; + uint vect; + +#if defined(CONFIG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + printf("External Interrupt Exception at PC: %lx, SR: %lx, vector=%lx", + regs->nip, regs->msr, regs->trap); + vect = pic->iack0; + printf(" irq IACK0@%05x=%d\n",&pic->iack0,vect); + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + machinecheck_count++; +#ifdef EXTINT_NOSKIP + printf("Returning back to 0x%08x\n",regs->nip); +#else + regs->nip += 4; /* skip offending instruction */ + printf("Skipping current instr, Returning to 0x%08x\n",regs->nip); +#endif + +} void DebugException(struct pt_regs *regs) diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 9be5a279e26..0a160e2513a 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -217,12 +217,14 @@ #define HID0_DPM (1<<20) #define HID0_ICE (1< -- cgit v1.3.1 From 6c543597bb4b1ecf5d8589f7abb0f39929fb7fd1 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 13 Aug 2007 14:38:06 -0500 Subject: Fix minor 85xx warnings Some patches had inserted warnings into the build: * mpc8560ads declared data without using it * cpu_init declared ecm and immap without using it in all CONFIGs * MPC8548CDS.h had its default filenames changed so that they contained "\m" in the paths. Made the defaults not Windows-specific (or anything-specific) Signed-off-by: Andy Fleming --- board/mpc8560ads/mpc8560ads.c | 1 - cpu/mpc85xx/cpu_init.c | 4 +++- include/configs/MPC8548CDS.h | 6 ++++-- 3 files changed, 7 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c index 41acb97af7e..eef524b45ea 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/mpc8560ads/mpc8560ads.c @@ -554,7 +554,6 @@ ft_soc_setup(void *blob, bd_t *bd) { u32 *p; int len; - ulong data; p = ft_get_prop(blob, "/" OF_SOC "/cpm@e0000000/brg-frequency", &len); diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 888417f864b..c7fe130ee0e 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -194,10 +194,12 @@ void cpu_init_f (void) int cpu_init_r(void) { +#if defined(CONFIG_CLEAR_LAW0) || defined(CONFIG_L2_CACHE) volatile immap_t *immap = (immap_t *)CFG_IMMR; +#endif +#ifdef CONFIG_CLEAR_LAW0 volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; -#ifdef CONFIG_CLEAR_LAW0 /* clear alternate boot location LAW (used for sdram, or ddr bank) */ ecm->lawar0 = 0; #endif diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index d7afdbd606f..dfe4f5b7a1b 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -623,6 +623,7 @@ extern unsigned long get_clock_freq(void); #define ENET_ENV "" #endif +#if 0 #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ @@ -634,9 +635,9 @@ extern unsigned long get_clock_freq(void); "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ "consoledev=ttyS1\0" \ "ramdiskaddr=2000000\0" \ - "ramdiskfile=mpc8548cds\ramdisk.uboot\0" \ + "ramdiskfile=ramdisk.uboot\0" \ "dtbaddr=c00000\0" \ - "dtbfile=mpc8548cds\mpc8548cds.dtb\0" \ + "dtbfile=mpc8548cds.dtb\0" \ "eoi=mw e00400b0 0\0" \ "iack=md e00400a0 1\0" \ "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ @@ -658,6 +659,7 @@ extern unsigned long get_clock_freq(void); PCI_ENV1 \ PCI_ENV2 \ ENET_ENV +#endif #define CONFIG_NFSBOOTCOMMAND \ -- cgit v1.3.1 From 39980c610c9a4c381907c9e1d1b9c0e1c0dca57a Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 13 Aug 2007 14:49:59 -0500 Subject: MPC85xx BA bits not set for 3-bit bank address DIMM The current implementation does not set the number of bank address bits (BA) in the processor. The default assumes 2 logical bank bits. This works fine for a DIMM that uses devices with 4 internal banks (SPD byte17 = 0x4) but needs to be set appropriately for a DIMM that uses devices with 8 internal banks (SPD byte17 = 0x8). Signed-off-by: Greg Davis --- cpu/mpc85xx/spd_sdram.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index d98455401a0..679f3608f72 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -176,7 +176,7 @@ spd_sdram(void) spd_eeprom_t spd; unsigned int n_ranks; unsigned int rank_density; - unsigned int odt_rd_cfg, odt_wr_cfg; + unsigned int odt_rd_cfg, odt_wr_cfg, ba_bits; unsigned int odt_cfg, mode_odt_enable; unsigned int refresh_clk; #ifdef MPC85xx_DDR_SDRAM_CLK_CNTL @@ -341,9 +341,14 @@ spd_sdram(void) #endif } + ba_bits = 0; + if (spd.nbanks == 0x8) + ba_bits = 1; + ddr->cs0_config = ( 1 << 31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) + | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); debug("\n"); -- cgit v1.3.1 From 3db0bef59eab1155801618cef5c481e97553b597 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 7 Aug 2007 18:07:27 -0500 Subject: Use an absolute address when jumping out of 4k boot page On e500 when we leave the 4k boot page we should use an absolute address since we don't know where the board code may want us to be really running at. Signed-off-by: Kumar Gala --- cpu/mpc85xx/start.S | 53 ++++++++++++++++++++++++----------------------------- 1 file changed, 24 insertions(+), 29 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 9dfd38d6a0d..2c98c2ad8a0 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -260,9 +260,33 @@ _start_e500: mtspr DBCR0,r0 #endif +/* L1 DCache is used for initial RAM */ + + /* Allocate Initial RAM in data cache. + */ + lis r3,CFG_INIT_RAM_ADDR@h + ori r3,r3,CFG_INIT_RAM_ADDR@l + li r2,512 /* 512*32=16K */ + mtctr r2 + li r0,0 +1: + dcbz r0,r3 + dcbtls 0,r0,r3 + addi r3,r3,32 + bdnz 1b + /* Jump out the last 4K page and continue to 'normal' start */ +#ifdef CFG_RAMBOOT bl 3f b _start_cont +#else + /* Calculate absolute address in FLASH and jump there */ + /*--------------------------------------------------------------*/ + lis r3,CFG_MONITOR_BASE@h + ori r3,r3,CFG_MONITOR_BASE@l + addi r3,r3,_start_cont - _start + _START_OFFSET + mtlr r3 +#endif 3: li r0,0 mtspr SRR1,r0 /* Keep things disabled for now */ @@ -271,7 +295,6 @@ _start_e500: rfi isync - .text .globl _start _start: @@ -285,34 +308,6 @@ version_string: .align 4 .globl _start_cont _start_cont: - -/* L1 DCache is used for initial RAM */ - - /* Allocate Initial RAM in data cache. - */ - lis r3,CFG_INIT_RAM_ADDR@h - ori r3,r3,CFG_INIT_RAM_ADDR@l - li r2,512 /* 512*32=16K */ - mtctr r2 - li r0,0 -1: - dcbz r0,r3 - dcbtls 0,r0,r3 - addi r3,r3,32 - bdnz 1b - -#ifndef CFG_RAMBOOT - /* Calculate absolute address in FLASH and jump there */ - /*--------------------------------------------------------------*/ - lis r3,CFG_MONITOR_BASE@h - ori r3,r3,CFG_MONITOR_BASE@l - addi r3,r3,in_flash - _start + _START_OFFSET - mtlr r3 - blr - .global in_flash -in_flash: -#endif /* CFG_RAMBOOT */ - /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ lis r1,CFG_INIT_RAM_ADDR@h ori r1,r1,CFG_INIT_SP_OFFSET@l -- cgit v1.3.1 From d111d6382c99fdea08c2312eeeae8786945e189a Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Tue, 19 Jun 2007 14:18:32 -0400 Subject: Empirically set cpo and clk_adjust for mpc85xx DDR2 support This patch is against u-boot-mpc85xx.git of www.denx.com Setting cpo to 0x9 for frequencies higher than 333MHz is verified on both MPC8548CDS board and MPC8568MDS board, especially for supporting 533MHz DDR2. Setting clk_adjust to 0x6(3/4 late cycle) for MPC8568MDS board is for DDR2 on all current board versions especially ver 1.92 or later to bring up. Signed-off-by: Haiying Wang --- cpu/mpc85xx/spd_sdram.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 679f3608f72..5dc223a53e3 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -692,13 +692,10 @@ spd_sdram(void) */ cpo = 0; if (spd.mem_type == SPD_MEMTYPE_DDR2) { - if (effective_data_rate == 266 || effective_data_rate == 333) { + if (effective_data_rate <= 333) { cpo = 0x7; /* READ_LAT + 5/4 */ - } else if (effective_data_rate == 400) { - cpo = 0x9; /* READ_LAT + 7/4 */ } else { - /* Pure speculation */ - cpo = 0xb; + cpo = 0x9; /* READ_LAT + 7/4 */ } } @@ -905,7 +902,12 @@ spd_sdram(void) if (spd.mem_type == SPD_MEMTYPE_DDR) clk_adjust = 0x6; else +#ifdef CONFIG_MPC8568 + /* Empirally setting clk_adjust */ + clk_adjust = 0x6; +#else clk_adjust = 0x7; +#endif ddr->sdram_clk_cntl = (0 | 0x80000000 -- cgit v1.3.1 From da9d4610d76e52c4d20a8f3d8433439a7fcf5b71 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 14 Aug 2007 00:14:25 -0500 Subject: Add support for UEC to 8568 Signed-off-by: Haiying Wang Signed-off-by: Andy Fleming --- Makefile | 3 ++ board/mpc8568mds/bcsr.c | 7 ++++ board/mpc8568mds/bcsr.h | 1 + board/mpc8568mds/mpc8568mds.c | 61 ++++++++++++++++++++++++++++++- cpu/mpc85xx/Makefile | 2 +- cpu/mpc85xx/cpu.c | 24 +++++++++++- cpu/mpc85xx/cpu_init.c | 33 +++++++++++++++++ cpu/mpc85xx/qe_io.c | 85 +++++++++++++++++++++++++++++++++++++++++++ drivers/qe/uec.c | 27 +++++++++----- drivers/qe/uec.h | 1 + drivers/qe/uec_phy.c | 14 +++---- drivers/qe/uec_phy.h | 6 +-- include/asm-ppc/global_data.h | 8 ++-- include/asm-ppc/immap_qe.h | 20 +++++++++- include/configs/MPC8568MDS.h | 56 ++++++++++++++++++++++++---- 15 files changed, 313 insertions(+), 35 deletions(-) create mode 100644 cpu/mpc85xx/qe_io.c (limited to 'cpu') diff --git a/Makefile b/Makefile index f51688961b3..a5698cf7c95 100644 --- a/Makefile +++ b/Makefile @@ -212,6 +212,9 @@ LIBS += drivers/nand_legacy/libnand_legacy.a ifeq ($(CPU),mpc83xx) LIBS += drivers/qe/qe.a endif +ifeq ($(CPU),mpc85xx) +LIBS += drivers/qe/qe.a +endif LIBS += drivers/sk98lin/libsk98lin.a LIBS += post/libpost.a post/drivers/libpostdrivers.a LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \ diff --git a/board/mpc8568mds/bcsr.c b/board/mpc8568mds/bcsr.c index 2e2e8cd18fa..aae0f98e038 100644 --- a/board/mpc8568mds/bcsr.c +++ b/board/mpc8568mds/bcsr.c @@ -47,3 +47,10 @@ void disable_8568mds_flash_write() bcsr[9] &= ~(0x01); } + +void enable_8568mds_qe_mdio() +{ + u8 *bcsr = (u8 *)(CFG_BCSR); + + bcsr[7] |= 0x01; +} diff --git a/board/mpc8568mds/bcsr.h b/board/mpc8568mds/bcsr.h index 8d4cb2f1412..aefd9bf54d3 100644 --- a/board/mpc8568mds/bcsr.h +++ b/board/mpc8568mds/bcsr.h @@ -95,5 +95,6 @@ void enable_8568mds_duart(void); void enable_8568mds_flash_write(void); void disable_8568mds_flash_write(void); +void enable_8568mds_qe_mdio(void); #endif /* __BCSR_H_ */ diff --git a/board/mpc8568mds/mpc8568mds.c b/board/mpc8568mds/mpc8568mds.c index 23caaec72f2..818ff138a99 100644 --- a/board/mpc8568mds/mpc8568mds.c +++ b/board/mpc8568mds/mpc8568mds.c @@ -28,9 +28,65 @@ #include #include #include +#include #include "bcsr.h" +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* GETH1 */ + {4, 10, 1, 0, 2}, /* TxD0 */ + {4, 9, 1, 0, 2}, /* TxD1 */ + {4, 8, 1, 0, 2}, /* TxD2 */ + {4, 7, 1, 0, 2}, /* TxD3 */ + {4, 23, 1, 0, 2}, /* TxD4 */ + {4, 22, 1, 0, 2}, /* TxD5 */ + {4, 21, 1, 0, 2}, /* TxD6 */ + {4, 20, 1, 0, 2}, /* TxD7 */ + {4, 15, 2, 0, 2}, /* RxD0 */ + {4, 14, 2, 0, 2}, /* RxD1 */ + {4, 13, 2, 0, 2}, /* RxD2 */ + {4, 12, 2, 0, 2}, /* RxD3 */ + {4, 29, 2, 0, 2}, /* RxD4 */ + {4, 28, 2, 0, 2}, /* RxD5 */ + {4, 27, 2, 0, 2}, /* RxD6 */ + {4, 26, 2, 0, 2}, /* RxD7 */ + {4, 11, 1, 0, 2}, /* TX_EN */ + {4, 24, 1, 0, 2}, /* TX_ER */ + {4, 16, 2, 0, 2}, /* RX_DV */ + {4, 30, 2, 0, 2}, /* RX_ER */ + {4, 17, 2, 0, 2}, /* RX_CLK */ + {4, 19, 1, 0, 2}, /* GTX_CLK */ + {1, 31, 2, 0, 3}, /* GTX125 */ + + /* GETH2 */ + {5, 10, 1, 0, 2}, /* TxD0 */ + {5, 9, 1, 0, 2}, /* TxD1 */ + {5, 8, 1, 0, 2}, /* TxD2 */ + {5, 7, 1, 0, 2}, /* TxD3 */ + {5, 23, 1, 0, 2}, /* TxD4 */ + {5, 22, 1, 0, 2}, /* TxD5 */ + {5, 21, 1, 0, 2}, /* TxD6 */ + {5, 20, 1, 0, 2}, /* TxD7 */ + {5, 15, 2, 0, 2}, /* RxD0 */ + {5, 14, 2, 0, 2}, /* RxD1 */ + {5, 13, 2, 0, 2}, /* RxD2 */ + {5, 12, 2, 0, 2}, /* RxD3 */ + {5, 29, 2, 0, 2}, /* RxD4 */ + {5, 28, 2, 0, 2}, /* RxD5 */ + {5, 27, 2, 0, 3}, /* RxD6 */ + {5, 26, 2, 0, 2}, /* RxD7 */ + {5, 11, 1, 0, 2}, /* TX_EN */ + {5, 24, 1, 0, 2}, /* TX_ER */ + {5, 16, 2, 0, 2}, /* RX_DV */ + {5, 30, 2, 0, 2}, /* RX_ER */ + {5, 17, 2, 0, 2}, /* RX_CLK */ + {5, 19, 1, 0, 2}, /* GTX_CLK */ + {1, 31, 2, 0, 3}, /* GTX125 */ + {4, 6, 3, 0, 2}, /* MDIO */ + {4, 5, 1, 0, 2}, /* MDC */ + {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ +}; + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -50,6 +106,9 @@ int board_early_init_f (void) enable_8568mds_duart(); enable_8568mds_flash_write(); +#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) + enable_8568mds_qe_mdio(); +#endif #ifdef CFG_I2C2_OFFSET /* Enable I2C2_SCL and I2C2_SDA */ @@ -335,6 +394,6 @@ pci_init_board(void) { #ifdef CONFIG_PCI pib_init(); - pci_mpc85xx_init(&hose); + pci_mpc85xx_init(hose); #endif } diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index ff67dcdd353..32091fa4e1d 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -30,7 +30,7 @@ LIB = $(obj)lib$(CPU).a START = start.o resetvec.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o + pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 1d791c9b9b3..08e04685f59 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -280,7 +280,7 @@ ft_cpu_setup(void *blob, bd_t *bd) if (p != NULL) *p = cpu_to_be32(clock); -#if defined(CONFIG_TSEC1) +#if defined(CONFIG_HAS_ETH0) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); if (p) memcpy(p, bd->bi_enetaddr, 6); @@ -308,6 +308,17 @@ ft_cpu_setup(void *blob, bd_t *bd) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len); if (p) memcpy(p, bd->bi_enet2addr, 6); + +#ifdef CONFIG_UEC_ETH + p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len); + if (p) + memcpy(p, bd->bi_enet2addr, 6); + + p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len); + if (p) + memcpy(p, bd->bi_enet2addr, 6); + +#endif #endif #if defined(CONFIG_HAS_ETH3) @@ -318,6 +329,17 @@ ft_cpu_setup(void *blob, bd_t *bd) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len); if (p) memcpy(p, bd->bi_enet3addr, 6); + +#ifdef CONFIG_UEC_ETH + p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len); + if (p) + memcpy(p, bd->bi_enet3addr, 6); + + p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len); + if (p) + memcpy(p, bd->bi_enet3addr, 6); + +#endif #endif } diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index c7fe130ee0e..7b9961013c0 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -34,6 +34,29 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_QE +extern qe_iop_conf_t qe_iop_conf_tab[]; +extern void qe_config_iopin(u8 port, u8 pin, int dir, + int open_drain, int assign); +extern void qe_init(uint qe_base); +extern void qe_reset(void); + +static void config_qe_ioports(void) +{ + u8 port, pin; + int dir, open_drain, assign; + int i; + + for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { + port = qe_iop_conf_tab[i].port; + pin = qe_iop_conf_tab[i].pin; + dir = qe_iop_conf_tab[i].dir; + open_drain = qe_iop_conf_tab[i].open_drain; + assign = qe_iop_conf_tab[i].assign; + qe_config_iopin(port, pin, dir, open_drain, assign); + } +} +#endif #ifdef CONFIG_CPM2 static void config_8560_ioports (volatile immap_t * immr) @@ -181,6 +204,11 @@ void cpu_init_f (void) #if defined(CONFIG_CPM2) m8560_cpm_reset(); #endif +#ifdef CONFIG_QE + /* Config QE ioports */ + config_qe_ioports(); +#endif + } @@ -262,6 +290,11 @@ int cpu_init_r(void) #else printf("L2 cache: disabled\n"); #endif +#ifdef CONFIG_QE + uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */ + qe_init(qe_base); + qe_reset(); +#endif return 0; } diff --git a/cpu/mpc85xx/qe_io.c b/cpu/mpc85xx/qe_io.c new file mode 100644 index 00000000000..8878bc53193 --- /dev/null +++ b/cpu/mpc85xx/qe_io.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * Dave Liu + * based on source code of Shlomi Gridish + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "common.h" +#include "asm/errno.h" +#include "asm/io.h" +#include "asm/immap_85xx.h" + +#if defined(CONFIG_QE) +#define NUM_OF_PINS 32 +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) +{ + u32 pin_2bit_mask; + u32 pin_2bit_dir; + u32 pin_2bit_assign; + u32 pin_1bit_mask; + u32 tmp_val; + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile par_io_t *par_io = (volatile par_io_t *) + &(im->im_gur.qe_par_io); + + /* Caculate pin location and 2bit mask and dir */ + pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); + pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); + + /* Setup the direction */ + tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \ + in_be32(&par_io[port].cpdir2) : + in_be32(&par_io[port].cpdir1); + + if (pin > (NUM_OF_PINS/2) -1) { + out_be32(&par_io[port].cpdir2, ~pin_2bit_mask & tmp_val); + out_be32(&par_io[port].cpdir2, pin_2bit_dir | tmp_val); + } else { + out_be32(&par_io[port].cpdir1, ~pin_2bit_mask & tmp_val); + out_be32(&par_io[port].cpdir1, pin_2bit_dir | tmp_val); + } + + /* Calculate pin location for 1bit mask */ + pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); + + /* Setup the open drain */ + tmp_val = in_be32(&par_io[port].cpodr); + if (open_drain) + out_be32(&par_io[port].cpodr, pin_1bit_mask | tmp_val); + else + out_be32(&par_io[port].cpodr, ~pin_1bit_mask & tmp_val); + + /* Setup the assignment */ + tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? + in_be32(&par_io[port].cppar2): + in_be32(&par_io[port].cppar1); + pin_2bit_assign = (u32)(assign + << (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2)); + + /* Clear and set 2 bits mask */ + if (pin > (NUM_OF_PINS/2) - 1) { + out_be32(&par_io[port].cppar2, ~pin_2bit_mask & tmp_val); + out_be32(&par_io[port].cppar2, pin_2bit_assign | tmp_val); + } else { + out_be32(&par_io[port].cppar1, ~pin_2bit_mask & tmp_val); + out_be32(&par_io[port].cppar1, pin_2bit_assign | tmp_val); + } +} + +#endif /* CONFIG_QE */ diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index c416a67c832..89a72798232 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -391,17 +391,17 @@ static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode) return 0; } -static int init_mii_management_configuration(uec_t *uec_regs) +static int init_mii_management_configuration(uec_mii_t *uec_mii_regs) { uint timeout = 0x1000; u32 miimcfg = 0; - miimcfg = in_be32(&uec_regs->miimcfg); + miimcfg = in_be32(&uec_mii_regs->miimcfg); miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE; - out_be32(&uec_regs->miimcfg, miimcfg); + out_be32(&uec_mii_regs->miimcfg, miimcfg); /* Wait until the bus is free */ - while ((in_be32(&uec_regs->miimcfg) & MIIMIND_BUSY) && timeout--); + while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--); if (timeout <= 0) { printf("%s: The MII Bus is stuck!", __FUNCTION__); return -ETIMEDOUT; @@ -413,13 +413,13 @@ static int init_mii_management_configuration(uec_t *uec_regs) static int init_phy(struct eth_device *dev) { uec_private_t *uec; - uec_t *uec_regs; + uec_mii_t *umii_regs; struct uec_mii_info *mii_info; struct phy_info *curphy; int err; uec = (uec_private_t *)dev->priv; - uec_regs = uec->uec_regs; + umii_regs = uec->uec_mii_regs; uec->oldlink = 0; uec->oldspeed = 0; @@ -451,19 +451,19 @@ static int init_phy(struct eth_device *dev) mii_info->mii_id = uec->uec_info->phy_address; mii_info->dev = dev; - mii_info->mdio_read = &read_phy_reg; - mii_info->mdio_write = &write_phy_reg; + mii_info->mdio_read = &uec_read_phy_reg; + mii_info->mdio_write = &uec_write_phy_reg; uec->mii_info = mii_info; - if (init_mii_management_configuration(uec_regs)) { + if (init_mii_management_configuration(umii_regs)) { printf("%s: The MII Bus is stuck!", dev->name); err = -1; goto bus_fail; } /* get info for this PHY */ - curphy = get_phy_info(uec->mii_info); + curphy = uec_get_phy_info(uec->mii_info); if (!curphy) { printf("%s: No PHY found", dev->name); err = -1; @@ -989,6 +989,13 @@ static int uec_startup(uec_private_t *uec) /* Setup MAC interface mode */ uec_set_mac_if_mode(uec, uec_info->enet_interface); + /* Setup MII management base */ +#ifndef CONFIG_eTSEC_MDIO_BUS + uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg); +#else + uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS; +#endif + /* Setup MII master clock source */ qe_set_mii_clk_src(uec_info->uf_info.ucc_num); diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index 04950264b89..c384055cebf 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -675,6 +675,7 @@ typedef struct uec_private { ucc_fast_private_t *uccf; struct eth_device *dev; uec_t *uec_regs; + uec_mii_t *uec_mii_regs; /* enet init command parameter */ uec_init_cmd_pram_t *p_init_enet_param; u32 init_enet_param_offset; diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index 76fd38896a8..ca6faa6ef4e 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -60,14 +60,14 @@ void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val); /* Write value to the PHY for this device to the register at regnum, */ /* waiting until the write is done before it returns. All PHY */ /* configuration has to be done through the TSEC1 MIIM regs */ -void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value) +void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value) { uec_private_t *ugeth = (uec_private_t *) dev->priv; - uec_t *ug_regs; + uec_mii_t *ug_regs; enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; u32 tmp_reg; - ug_regs = ugeth->uec_regs; + ug_regs = ugeth->uec_mii_regs; /* Stop the MII management read cycle */ out_be32 (&ug_regs->miimcom, 0); @@ -87,15 +87,15 @@ void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value) /* Reads from register regnum in the PHY for device dev, */ /* returning the value. Clears miimcom first. All PHY */ /* configuration has to be done through the TSEC1 MIIM regs */ -int read_phy_reg (struct eth_device *dev, int mii_id, int regnum) +int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum) { uec_private_t *ugeth = (uec_private_t *) dev->priv; - uec_t *ug_regs; + uec_mii_t *ug_regs; enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; u32 tmp_reg; u16 value; - ug_regs = ugeth->uec_regs; + ug_regs = ugeth->uec_mii_regs; /* Setting up the MII Mangement Address Register */ tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; @@ -521,7 +521,7 @@ void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val) /* Use the PHY ID registers to determine what type of PHY is attached * to device dev. return a struct phy_info structure describing that PHY */ -struct phy_info *get_phy_info (struct uec_mii_info *mii_info) +struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info) { u16 phy_reg; u32 phy_ID; diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h index 9bd926ddd5a..e59a940e0dd 100644 --- a/drivers/qe/uec_phy.h +++ b/drivers/qe/uec_phy.h @@ -249,10 +249,10 @@ struct phy_info { void (*close) (struct uec_mii_info * mii_info); }; -struct phy_info *get_phy_info (struct uec_mii_info *mii_info); -void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, +struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info); +void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value); -int read_phy_reg (struct eth_device *dev, int mii_id, int regnum); +int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum); void mii_clear_phy_interrupt (struct uec_mii_info *mii_info); void mii_configure_phy_interrupt (struct uec_mii_info *mii_info, u32 interrupts); diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index bbaeb3f575f..1f1583a9231 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -71,16 +71,16 @@ typedef struct global_data { u32 lclk_clk; u32 ddr_clk; u32 pci_clk; +#if defined(CONFIG_MPC8360) + u32 ddr_sec_clk; +#endif /* CONFIG_MPC8360 */ +#endif #if defined(CONFIG_QE) u32 qe_clk; u32 brg_clk; uint mp_alloc_base; uint mp_alloc_top; #endif /* CONFIG_QE */ -#if defined (CONFIG_MPC8360) - u32 ddr_sec_clk; -#endif /* CONFIG_MPC8360 */ -#endif #if defined(CONFIG_MPC5xxx) unsigned long ipb_clk; unsigned long pci_clk; diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h index 950b9497f8a..a16a6d3fc5f 100644 --- a/include/asm-ppc/immap_qe.h +++ b/include/asm-ppc/immap_qe.h @@ -281,6 +281,17 @@ typedef struct ucc_slow { u8 res4[0x200 - 0x091]; } __attribute__ ((packed)) ucc_slow_t; +typedef struct ucc_mii_mng { + u32 miimcfg; /* MII management configuration reg */ + u32 miimcom; /* MII management command reg */ + u32 miimadd; /* MII management address reg */ + u32 miimcon; /* MII management control reg */ + u32 miimstat; /* MII management status reg */ + u32 miimind; /* MII management indication reg */ + u32 ifctl; /* interface control reg */ + u32 ifstat; /* interface statux reg */ +} __attribute__ ((packed))uec_mii_t; + typedef struct ucc_ethernet { u32 maccfg1; /* mac configuration reg. 1 */ u32 maccfg2; /* mac configuration reg. 2 */ @@ -540,14 +551,21 @@ typedef struct qe_immap { u8 res14[0x300]; u8 res15[0x3A00]; u8 res16[0x8000]; /* 0x108000 - 0x110000 */ +#if defined(CONFIG_MPC8568) + u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */ + u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */ +#else u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */ u8 res17[0x24000]; /* 0x11C000 - 0x140000 */ u8 res18[0xC0000]; /* 0x140000 - 0x200000 */ +#endif } __attribute__ ((packed)) qe_map_t; extern qe_map_t *qe_immr; -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_MPC8568) +#define QE_MURAM_SIZE 0x10000UL +#elif defined(CONFIG_MPC8360) #define QE_MURAM_SIZE 0xc000UL #elif defined(CONFIG_MPC832X) #define QE_MURAM_SIZE 0x4000UL diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 5bc953adc42..dc9cb1ff545 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -28,20 +28,21 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ #define CONFIG_MPC8568 1 /* MPC8568 specific */ #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ #define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ +#undef CONFIG_QE /* Enable QE */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ /*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */ /*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */ -/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */ +/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef @@ -297,6 +298,7 @@ extern unsigned long get_clock_freq(void); #define OF_CPU "PowerPC,8568@0" #define OF_SOC "soc8568@e0000000" +#define OF_QE "qe@e0080000" #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600" @@ -311,7 +313,7 @@ extern unsigned long get_clock_freq(void); #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x52 #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0,0x69} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 @@ -340,6 +342,44 @@ extern unsigned long get_clock_freq(void); #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#ifdef CONFIG_QE +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#ifndef CONFIG_TSEC_ENET +#define CONFIG_ETHPRIME "Freescale GETH" +#endif +#define CONFIG_PHY_MODE_NEED_CHANGE +#define CONFIG_eTSEC_MDIO_BUS + +#ifdef CONFIG_eTSEC_MDIO_BUS +#define CONFIG_MIIM_ADDRESS 0xE0024520 +#endif + +#define CONFIG_UEC_ETH1 /* GETH1 */ + +#ifdef CONFIG_UEC_ETH1 +#define CFG_UEC1_UCC_NUM 0 /* UCC1 */ +#define CFG_UEC1_RX_CLK QE_CLK_NONE +#define CFG_UEC1_TX_CLK QE_CLK16 +#define CFG_UEC1_ETH_TYPE GIGA_ETH +#define CFG_UEC1_PHY_ADDR 7 +#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII +#endif + +#define CONFIG_UEC_ETH2 /* GETH2 */ + +#ifdef CONFIG_UEC_ETH2 +#define CFG_UEC2_UCC_NUM 1 /* UCC2 */ +#define CFG_UEC2_RX_CLK QE_CLK_NONE +#define CFG_UEC2_TX_CLK QE_CLK16 +#define CFG_UEC2_ETH_TYPE GIGA_ETH +#define CFG_UEC2_PHY_ADDR 1 +#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII +#endif +#endif /* CONFIG_QE */ + #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -348,13 +388,12 @@ extern unsigned long get_clock_freq(void); #endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - #ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI 1 #endif +#if defined(CONFIG_TSEC_ENET) + #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "eTSEC0" @@ -460,12 +499,15 @@ extern unsigned long get_clock_freq(void); */ /* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD #define CONFIG_HAS_ETH2 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif #define CONFIG_IPADDR 192.168.1.253 -- cgit v1.3.1 From 7f3f2bd2dc08e0b05e185662ca2e2d283757104a Mon Sep 17 00:00:00 2001 From: Randy Vinson Date: Tue, 27 Feb 2007 19:42:22 -0700 Subject: 85xxCDS: Add make targets for legacy systems. The PCI ID select values on the Arcadia main board differ depending on the version of the hardware. The standard configuration supports Rev 3.1. The legacy target supports Rev 2.x. Signed-off-by Randy Vinson --- Makefile | 27 ++++++++++++++++++++++++--- board/cds/common/via.c | 2 +- board/cds/mpc8541cds/mpc8541cds.c | 15 +++++++++------ board/cds/mpc8548cds/mpc8548cds.c | 15 +++++++++------ board/cds/mpc8555cds/mpc8555cds.c | 15 +++++++++------ cpu/mpc85xx/pci.c | 2 +- include/configs/MPC8541CDS.h | 7 +++++++ include/configs/MPC8548CDS.h | 8 ++++++++ include/configs/MPC8555CDS.h | 7 +++++++ 9 files changed, 75 insertions(+), 23 deletions(-) (limited to 'cpu') diff --git a/Makefile b/Makefile index a5698cf7c95..95e9e369a5f 100644 --- a/Makefile +++ b/Makefile @@ -1786,17 +1786,38 @@ MPC8540EVAL_66_slave_config: unconfig MPC8560ADS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads +MPC8541CDS_legacy_config \ MPC8541CDS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8541cds cds + @mkdir -p $(obj)include + @echo "" >$(obj)include/config.h ; \ + if [ "$(findstring _legacy_,$@)" ] ; then \ + echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \ + echo "... legacy" ; \ + fi + @$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds cds MPC8544DS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale +MPC8548CDS_legacy_config \ MPC8548CDS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8548cds cds + @mkdir -p $(obj)include + @echo "" >$(obj)include/config.h ; \ + if [ "$(findstring _legacy_,$@)" ] ; then \ + echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \ + echo "... legacy" ; \ + fi + @$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds cds +MPC8555CDS_legacy_config \ MPC8555CDS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8555cds cds + @mkdir -p $(obj)include + @echo "" >$(obj)include/config.h ; \ + if [ "$(findstring _legacy_,$@)" ] ; then \ + echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \ + echo "... legacy" ; \ + fi + @$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds cds MPC8568MDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds diff --git a/board/cds/common/via.c b/board/cds/common/via.c index ded214f06f7..4a63d779440 100644 --- a/board/cds/common/via.c +++ b/board/cds/common/via.c @@ -45,7 +45,7 @@ void mpc85xx_config_via(struct pci_controller *hose, * This allows legacy I/O (i8259, etc) on the VIA * southbridge to be accessed. */ - bridge = PCI_BDF(0,17,0); + bridge = PCI_BDF(0,BRIDGE_ID,0); pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0); pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0); pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10); diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c index 41923248360..558ba9903ce 100644 --- a/board/cds/mpc8541cds/mpc8541cds.c +++ b/board/cds/mpc8541cds/mpc8541cds.c @@ -476,14 +476,17 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta static struct pci_config_table pci_mpc85xxcds_config_table[] = { {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, + {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, + {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, + mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, + mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, + mpc85xx_config_via_ac97, {0,0,0}}, {}, }; diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 242a68c391d..48753d7e241 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -299,14 +299,17 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta static struct pci_config_table pci_mpc85xxcds_config_table[] = { {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, + {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, + {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, + mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, + mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, + mpc85xx_config_via_ac97, {0,0,0}}, {}, }; diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c index 704bf03164a..8f1642187c1 100644 --- a/board/cds/mpc8555cds/mpc8555cds.c +++ b/board/cds/mpc8555cds/mpc8555cds.c @@ -473,14 +473,17 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta static struct pci_config_table pci_mpc85xxcds_config_table[] = { {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, + {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, + {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, + mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, + mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, + mpc85xx_config_via_ac97, {0,0,0}}, {}, }; diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index 3c1a323aad2..db09e45fbcc 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -142,7 +142,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose) u8 header_type; pci_hose_read_config_byte(hose, - PCI_BDF(0,17,0), + PCI_BDF(0,BRIDGE_ID,0), PCI_HEADER_TYPE, &header_type); } diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 50d3b6b8727..232f1716bcc 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -350,6 +350,13 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI2_IO_PHYS 0xe2100000 #define CFG_PCI2_IO_SIZE 0x100000 /* 1M */ +#ifdef CONFIG_LEGACY +#define BRIDGE_ID 17 +#define VIA_ID 2 +#else +#define BRIDGE_ID 28 +#define VIA_ID 4 +#endif #if defined(CONFIG_PCI) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index dfe4f5b7a1b..cda9fd5c1c7 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -395,6 +395,14 @@ extern unsigned long get_clock_freq(void); #define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ #endif +#ifdef CONFIG_LEGACY +#define BRIDGE_ID 17 +#define VIA_ID 2 +#else +#define BRIDGE_ID 28 +#define VIA_ID 4 +#endif + #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index a3025bd7157..e8fe99aaf13 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -350,6 +350,13 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI2_IO_PHYS 0xe2100000 #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ +#ifdef CONFIG_LEGACY +#define BRIDGE_ID 17 +#define VIA_ID 2 +#else +#define BRIDGE_ID 28 +#define VIA_ID 4 +#endif #if defined(CONFIG_PCI) -- cgit v1.3.1