From 6fbf261f8df294e589cfadebebe5468e3c0f29e9 Mon Sep 17 00:00:00 2001 From: Xie Xiaobo Date: Fri, 9 Mar 2007 19:08:25 +0800 Subject: Fix two bugs for MPC83xx DDR2 controller SPD Init There are a few bugs in the cpu/mpc83xx/spd_sdram.c the first bug is that the picos_to_clk routine introduces a huge rounding error in 83xx. the second bug is that the mode register write recovery field is tWR-1, not tWR >> 1. --- cpu/mpc83xx/spd_sdram.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index d9b8753ca09..41a1f1fc7b0 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -58,8 +58,8 @@ picos_to_clk(int picos) int clks; ddr_bus_clk = gd->ddr_clk >> 1; - clks = picos / ((1000000000 / ddr_bus_clk) * 1000); - if (picos % ((1000000000 / ddr_bus_clk) * 1000) != 0) + clks = picos / (1000000000 / (ddr_bus_clk / 1000)); + if (picos % (1000000000 / (ddr_bus_clk / 1000)) != 0) clks++; return clks; @@ -624,7 +624,7 @@ long int spd_sdram() | (1 << (16 + 10)) /* DQS Differential disable */ | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */ - | ((twr_clk >> 1) << 9) /* Write Recovery Autopre */ + | ((twr_clk - 1) << 9) /* Write Recovery Autopre */ | (caslat << 4) /* caslat */ | (burstlen << 0) /* Burst length */ ); -- cgit v1.2.3 From 7dbdf28b8bd855a8530dc3292e4982575a197060 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 20 Apr 2007 14:11:38 -0500 Subject: mpc86xx: protect memcpy to bad address if a mac-address is missing from dt Signed-off-by: Kim Phillips Signed-off-by: Jon Loeliger --- cpu/mpc86xx/cpu.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 84f5bef5087..73de8cb4af1 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -280,22 +280,26 @@ ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_MPC86XX_TSEC1) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); - memcpy(p, bd->bi_enetaddr, 6); + if (p != NULL) + memcpy(p, bd->bi_enetaddr, 6); #endif #if defined(CONFIG_MPC86XX_TSEC2) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); - memcpy(p, bd->bi_enet1addr, 6); + if (p != NULL) + memcpy(p, bd->bi_enet1addr, 6); #endif #if defined(CONFIG_MPC86XX_TSEC3) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len); - memcpy(p, bd->bi_enet2addr, 6); + if (p != NULL) + memcpy(p, bd->bi_enet2addr, 6); #endif #if defined(CONFIG_MPC86XX_TSEC4) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len); - memcpy(p, bd->bi_enet3addr, 6); + if (p != NULL) + memcpy(p, bd->bi_enet3addr, 6); #endif } -- cgit v1.2.3 From bd7851ce1e1f140665b520026abf1042968b1102 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 20 Apr 2007 14:12:26 -0500 Subject: mpc86xx; Write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. Signed-off-by: Timur Tabi Signed-off-by: Jon Loeliger --- cpu/mpc86xx/cpu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 73de8cb4af1..a33acfec4d3 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -282,24 +282,36 @@ ft_cpu_setup(void *blob, bd_t *bd) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enetaddr, 6); + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len); + if (p) + memcpy(p, bd->bi_enetaddr, 6); #endif #if defined(CONFIG_MPC86XX_TSEC2) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enet1addr, 6); + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len); + if (p != NULL) + memcpy(p, bd->bi_enet1addr, 6); #endif #if defined(CONFIG_MPC86XX_TSEC3) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enet2addr, 6); + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len); + if (p != NULL) + memcpy(p, bd->bi_enet2addr, 6); #endif #if defined(CONFIG_MPC86XX_TSEC4) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enet3addr, 6); + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len); + if (p != NULL) + memcpy(p, bd->bi_enet3addr, 6); #endif } -- cgit v1.2.3 From 0643631aa1036cd746bf5d15f5a34bc7bc01ea4f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Sat, 21 Apr 2007 21:02:40 +0200 Subject: 16bit read/write little endian --- cpu/microblaze/start.S | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'cpu') diff --git a/cpu/microblaze/start.S b/cpu/microblaze/start.S index 29481af9ae9..453815818d0 100644 --- a/cpu/microblaze/start.S +++ b/cpu/microblaze/start.S @@ -117,3 +117,36 @@ clear_bss: 3: /* jumping to board_init */ brai board_init 1: bri 1b + +/* + * Read 16bit little endian + */ + .text + .global in16 + .ent in16 + .align 2 +in16: lhu r3, r0, r5 + bslli r4, r3, 8 + bsrli r3, r3, 8 + andi r4, r4, 0xffff + or r3, r3, r4 + rtsd r15, 8 + sext16 r3, r3 + .end in16 + +/* + * Write 16bit little endian + * first parameter(r5) - address, second(r6) - short value + */ + .text + .global out16 + .ent out16 + .align 2 +out16: bslli r3, r6, 8 + bsrli r6, r6, 8 + andi r3, r3, 0xffff + or r3, r3, r6 + sh r3, r0, r5 + rtsd r15, 8 + or r0, r0, r0 + .end out16 -- cgit v1.2.3 From 323bfa8f436dc3bc57187c9b1488bc3146ff1522 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 23 Apr 2007 12:00:22 +0200 Subject: Remove BOARDLIBS usage completely Signed-off-by: Stefan Roese --- cpu/ixp/npe/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ixp/npe/Makefile b/cpu/ixp/npe/Makefile index 4de34fd5b9e..7f020b5d576 100644 --- a/cpu/ixp/npe/Makefile +++ b/cpu/ixp/npe/Makefile @@ -87,7 +87,7 @@ START := $(addprefix $(obj),$(START)) all: $(LIB) -$(LIB): $(obj).depend $(OBJS) +$(LIB): $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) ######################################################################### -- cgit v1.2.3 From a35b0c4950d84cf9e3a9e32b916135956d1ac636 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Mon, 16 Apr 2007 14:34:15 -0500 Subject: mpc83xx: Recognize SPR values for MPC8311 and MPC8313. Signed-off-by: Scott Wood --- cpu/mpc83xx/cpu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index e934ba638fe..d569c49727b 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -124,6 +124,18 @@ int checkcpu(void) case SPR_8321_REV11: puts("MPC8321, "); break; + case SPR_8311_REV10: + puts("MPC8311, "); + break; + case SPR_8311E_REV10: + puts("MPC8311E, "); + break; + case SPR_8313_REV10: + puts("MPC8313, "); + break; + case SPR_8313E_REV10: + puts("MPC8313E, "); + break; default: puts("Rev: Unknown revision number.\nWarning: Unsupported cpu revision!\n"); return 0; -- cgit v1.2.3 From 95e7ef897e54591e615fc1b458b74c286fe1fb06 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Mon, 16 Apr 2007 14:34:16 -0500 Subject: mpc83xx: Change PVR_83xx to PVR_E300C1-3, and update checkcpu(). Rather than misleadingly define PVR_83xx as the specific type of 83xx being built for, the PVR of each core revision is defined. checkcpu() now prints the core that it detects, rather than aborting if it doesn't find what it thinks it wants. Signed-off-by: Scott Wood --- cpu/mpc83xx/cpu.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index d569c49727b..332afaad9f5 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -52,13 +52,26 @@ int checkcpu(void) immr = (immap_t *)CFG_IMMR; - if ((pvr & 0xFFFF0000) != PVR_83xx) { - puts("Not MPC83xx Family!!!\n"); - return -1; + puts("CPU: "); + + switch (pvr & 0xffff0000) { + case PVR_E300C1: + printf("e300c1, "); + break; + + case PVR_E300C2: + printf("e300c2, "); + break; + + case PVR_E300C3: + printf("e300c3, "); + break; + + default: + printf("Unknown core, "); } spridr = immr->sysconf.spridr; - puts("CPU: "); switch(spridr) { case SPR_8349E_REV10: case SPR_8349E_REV11: -- cgit v1.2.3 From 7c98e5193e93df6b9b651851d54b638a61ebb0ea Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Mon, 16 Apr 2007 14:34:19 -0500 Subject: mpc83xx: Add 831x support to speed.c. Signed-off-by: Scott Wood --- cpu/mpc83xx/speed.c | 68 +++++++++++++++++++++++++++++++++-------------------- 1 file changed, 42 insertions(+), 26 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index c75993059e0..1a440310e5e 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -99,11 +99,13 @@ int get_clocks(void) u32 lcrr; u32 csb_clk; -#if defined(CONFIG_MPC834X) +#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) u32 tsec1_clk; u32 tsec2_clk; - u32 usbmph_clk; u32 usbdr_clk; +#endif +#ifdef CONFIG_MPC834X + u32 usbmph_clk; #endif u32 core_clk; u32 i2c1_clk; @@ -148,7 +150,7 @@ int get_clocks(void) sccr = im->clk.sccr; -#if defined(CONFIG_MPC834X) +#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: tsec1_clk = 0; @@ -167,6 +169,26 @@ int get_clocks(void) return -4; } + switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { + case 0: + usbdr_clk = 0; + break; + case 1: + usbdr_clk = csb_clk; + break; + case 2: + usbdr_clk = csb_clk / 2; + break; + case 3: + usbdr_clk = csb_clk / 3; + break; + default: + /* unkown SCCR_USBDRCM value */ + return -8; + } +#endif + +#if defined(CONFIG_MPC834X) switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { case 0: tsec2_clk = 0; @@ -205,24 +227,6 @@ int get_clocks(void) return -7; } - switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { - case 0: - usbdr_clk = 0; - break; - case 1: - usbdr_clk = csb_clk; - break; - case 2: - usbdr_clk = csb_clk / 2; - break; - case 3: - usbdr_clk = csb_clk / 3; - break; - default: - /* unkown SCCR_USBDRCM value */ - return -8; - } - if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) { /* if USB MPH clock is not disabled and * USB DR clock is not disabled then @@ -230,8 +234,16 @@ int get_clocks(void) */ return -9; } +#elif defined(CONFIG_MPC831X) + tsec2_clk = tsec1_clk; + + if (!(sccr & SCCR_TSEC1ON)) + tsec1_clk = 0; + if (!(sccr & SCCR_TSEC2ON)) + tsec2_clk = 0; #endif -#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) + +#if !defined(CONFIG_MPC834X) i2c1_clk = csb_clk; #endif #if !defined(CONFIG_MPC832X) @@ -314,11 +326,13 @@ int get_clocks(void) #endif gd->csb_clk = csb_clk; -#if defined(CONFIG_MPC834X) +#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) gd->tsec1_clk = tsec1_clk; gd->tsec2_clk = tsec2_clk; - gd->usbmph_clk = usbmph_clk; gd->usbdr_clk = usbdr_clk; +#endif +#if defined(CONFIG_MPC834X) + gd->usbmph_clk = usbmph_clk; #endif gd->core_clk = core_clk; gd->i2c1_clk = i2c1_clk; @@ -371,11 +385,13 @@ int print_clock_conf(void) #if !defined(CONFIG_MPC832X) printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000); #endif -#if defined(CONFIG_MPC834X) +#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000); printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000); - printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000); printf(" USB DR: %4d MHz\n", gd->usbdr_clk / 1000000); +#endif +#if defined(CONFIG_MPC834X) + printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000); #endif return 0; } -- cgit v1.2.3 From 49ea3b6eafe606285ae4d5c378026153dde53200 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Mon, 16 Apr 2007 14:34:21 -0500 Subject: mpc83xx: Add generic PCI setup code. Board code can now request the generic setup code rather than having to copy-and-paste it for themselves. Boards should be converted to use this once they're tested with it. Signed-off-by: Scott Wood --- cpu/mpc83xx/Makefile | 2 +- cpu/mpc83xx/pci.c | 191 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 192 insertions(+), 1 deletion(-) create mode 100644 cpu/mpc83xx/pci.c (limited to 'cpu') diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile index 4b9dcc8180f..bb96f774fe4 100644 --- a/cpu/mpc83xx/Makefile +++ b/cpu/mpc83xx/Makefile @@ -29,7 +29,7 @@ LIB = $(obj)lib$(CPU).a START = start.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - spd_sdram.o qe_io.o + spd_sdram.o qe_io.o pci.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c new file mode 100644 index 00000000000..2a2b0bd9028 --- /dev/null +++ b/cpu/mpc83xx/pci.c @@ -0,0 +1,191 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2007 + * + * Author: Scott Wood , + * with some bits from older board-specific PCI initialization. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_83XX_GENERIC_PCI +#define MAX_BUSES 2 + +DECLARE_GLOBAL_DATA_PTR; + +static struct pci_controller pci_hose[MAX_BUSES]; +static int pci_num_buses; + +static void pci_init_bus(int bus, struct pci_region *reg) +{ + volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile pot83xx_t *pot = immr->ios.pot; + volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus]; + struct pci_controller *hose = &pci_hose[bus]; + u32 dev; + u16 reg16; + int i; + + if (bus == 1) + pot += 3; + + /* Setup outbound translation windows */ + for (i = 0; i < 3; i++, reg++, pot++) { + if (reg->size == 0) + break; + + hose->regions[i] = *reg; + hose->region_count++; + + pot->potar = reg->bus_start >> 12; + pot->pobar = reg->phys_start >> 12; + pot->pocmr = ~(reg->size - 1) >> 12; + + if (reg->flags & PCI_REGION_IO) + pot->pocmr |= POCMR_IO; +#ifdef CONFIG_83XX_PCI_STREAMING + else if (reg->flags & PCI_REGION_PREFETCH) + pot->pocmr |= POCMR_SE; +#endif + + if (bus == 1) + pot->pocmr |= POCMR_DST; + + pot->pocmr |= POCMR_EN; + } + + /* Point inbound translation at RAM */ + pci_ctrl->pitar1 = 0; + pci_ctrl->pibar1 = 0; + pci_ctrl->piebar1 = 0; + pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | + PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); + + i = hose->region_count++; + hose->regions[i].bus_start = 0; + hose->regions[i].phys_start = 0; + hose->regions[i].size = gd->ram_size; + hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY; + + hose->first_busno = 0; + hose->last_busno = 0xff; + + pci_setup_indirect(hose, CFG_IMMR + 0x8300 + bus * 0x80, + CFG_IMMR + 0x8304 + bus * 0x80); + + pci_register_hose(hose); + + /* + * Write to Command register + */ + reg16 = 0xff; + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); +} + +/* + * The caller must have already set OCCR, and the PCI_LAW BARs + * must have been set to cover all of the requested regions. + * + * If fewer than three regions are requested, then the region + * list is terminated with a region of size 0. + */ +void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot) +{ + volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + int i; + + if (num_buses > MAX_BUSES) { + printf("%d PCI buses requsted, %d supported\n", + num_buses, MAX_BUSES); + + num_buses = MAX_BUSES; + } + + pci_num_buses = num_buses; + + /* + * Release PCI RST Output signal. + * Power on to RST high must be at least 100 ms as per PCI spec. + * On warm boots only 1 ms is required. + */ + udelay(warmboot ? 1000 : 100000); + + for (i = 0; i < num_buses; i++) + immr->pci_ctrl[i].gcr = 1; + + /* + * RST high to first config access must be at least 2^25 cycles + * as per PCI spec. This could be cut in half if we know we're + * running at 66MHz. This could be insufficiently long if we're + * running the PCI bus at significantly less than 33MHz. + */ + udelay(1020000); + + for (i = 0; i < num_buses; i++) + pci_init_bus(i, reg[i]); +} + +#ifdef CONFIG_OF_FLAT_TREE +void ft_pci_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + if (pci_num_buses < 1) + return; + + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); + if (p) { + p[0] = pci_hose[0].first_busno; + p[1] = pci_hose[0].last_busno; + } + + if (pci_num_buses < 2) + return; + + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); + if (p) { + p[0] = pci_hose[1].first_busno; + p[1] = pci_hose[1].last_busno; + } +} +#endif /* CONFIG_OF_FLAT_TREE */ + +#endif /* CONFIG_83XX_GENERIC_PCI */ -- cgit v1.2.3 From 63247a5acd58032e6cf33f525bc3923b467bac88 Mon Sep 17 00:00:00 2001 From: Zang Roy-r61911 Date: Wed, 20 Dec 2006 11:01:00 +0800 Subject: u-boot: v2: Remove the fixed TLB and LAW entrynubmer Remove the fixed TLB and LAW entry nubmer. Use actually TLB and LAW entry number to control the loop. This can reduce the potential risk for the 85xx processor increasing its TLB adn LAW entry number. Signed-off-by: Swarthout Edward Signed-off-by: Roy Zang --- cpu/mpc85xx/start.S | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index f96a4c3f8b0..20c7ebc7238 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -251,13 +251,10 @@ _start_e500: */ bl tlb1_entry mr r5,r0 - li r1,0x0020 /* max 16 TLB1 plus some TLB0 entries */ - mtctr r1 lwzu r4,0(r5) /* how many TLB1 entries we actually use */ + mtctr r4 -0: cmpwi r4,0 - beq 1f - lwzu r0,4(r5) +0: lwzu r0,4(r5) lwzu r1,4(r5) lwzu r2,4(r5) lwzu r3,4(r5) @@ -269,7 +266,6 @@ _start_e500: msync tlbwe isync - addi r4,r4,-1 bdnz 0b 1: @@ -301,20 +297,16 @@ _start_e500: bl law_entry mr r6,r0 - li r1,0x0007 /* 8 LAWs, but reserve one for boot-over-rio-or-pci */ - mtctr r1 lwzu r5,0(r6) /* how many windows we actually use */ + mtctr r5 li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */ li r1,0x0c30 -0: cmpwi r5,0 - beq 1f - lwzu r4,4(r6) +0: lwzu r4,4(r6) lwzu r3,4(r6) stwx r4,r7,r2 stwx r3,r7,r1 - addi r5,r5,-1 addi r2,r2,0x0020 addi r1,r1,0x0020 bdnz 0b -- cgit v1.2.3 From 96629cbabdb727d4a5e62542deefc01d498db6dc Mon Sep 17 00:00:00 2001 From: Zang Roy-r61911 Date: Tue, 5 Dec 2006 16:42:30 +0800 Subject: u-boot: Fix e500 v2 core reset bug The following patch fixes the e500 v2 core reset bug. For e500 v2 core, a new reset control register is added to reset the processor. Signed-off-by: Roy Zang --- cpu/mpc85xx/cpu.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 0507c47e6e7..2fe4f2abba5 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -140,16 +140,25 @@ int checkcpu (void) int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { + uint pvr; + uint ver; + pvr = get_pvr(); + ver = PVR_VER(pvr); + if (ver & 1){ + /* e500 v2 core has reset control register */ + volatile unsigned int * rstcr; + rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0); + *rstcr = 0x2; /* HRESET_REQ */ + }else{ /* * Initiate hard reset in debug control register DBCR0 * Make sure MSR[DE] = 1 */ - unsigned long val; - - val = mfspr(DBCR0); - val |= 0x70000000; - mtspr(DBCR0,val); - + unsigned long val; + val = mfspr(DBCR0); + val |= 0x70000000; + mtspr(DBCR0,val); + } return 1; } -- cgit v1.2.3 From 151d5d992eab8c497b24c816c73dc1ad8bffb4eb Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 23 Apr 2007 01:32:22 -0500 Subject: Add cpu support for the 8544 Recognize new SVR values, and add a few register definitions Signed-off-by: Ed Swarthout Signed-off-by: Jon Loeliger Acked-by: Andy Fleming --- cpu/mpc85xx/cpu.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 2fe4f2abba5..2fe6bdf4b94 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004,2007 Freescale Semiconductor, Inc. * (C) Copyright 2002, 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) * @@ -70,6 +70,12 @@ int checkcpu (void) case SVR_8548_E: puts("8548_E"); break; + case SVR_8544: + puts("8544"); + break; + case SVR_8544_E: + puts("8544_E"); + break; default: puts("Unknown"); break; @@ -112,7 +118,7 @@ int checkcpu (void) #endif clkdiv = lcrr & 0x0f; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { -#ifdef CONFIG_MPC8548 +#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) /* * Yes, the entire PQ38 family use the same * bit-representation for twice the clock divider values. -- cgit v1.2.3 From 03b81b48eec0ad249ec97a4ae16c36fa2e014ff4 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 23 Apr 2007 01:44:44 -0500 Subject: Some 85xx cpu cleanups * Cleaned up the TSR[WIS] clearing * Cleaned up DMA initialization Signed-off-by: Ed Swarthout Signed-off-by: Jon Loeliger Acked-by: Andy Fleming --- cpu/mpc85xx/cpu.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 2fe6bdf4b94..b701b477b16 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -198,9 +198,9 @@ reset_85xx_watchdog(void) * Clear TSR(WIS) bit by writing 1 */ unsigned long val; - val = mfspr(tsr); - val |= 0x40000000; - mtspr(tsr, val); + val = mfspr(SPRN_TSR); + val |= TSR_WIS; + mtspr(SPRN_TSR, val); } #endif /* CONFIG_WATCHDOG */ @@ -211,6 +211,7 @@ void dma_init(void) { dma->satr0 = 0x02c40000; dma->datr0 = 0x02c40000; + dma->sr0 = 0xfffffff; /* clear any errors */ asm("sync; isync; msync"); return; } @@ -225,6 +226,10 @@ uint dma_check(void) { status = dma->sr0; } + /* clear MR0[CS] channel start bit */ + dma->mr0 &= 0x00000001; + asm("sync;isync;msync"); + if (status != 0) { printf ("DMA Error: status = %x\n", status); } -- cgit v1.2.3 From 85e7c7a45e3dd9c7ce3e722352ba60f8df1a7a4b Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 12 Feb 2007 13:34:55 -0600 Subject: 85xx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. Signed-off-by: Timur Tabi --- cpu/mpc85xx/cpu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index b701b477b16..d5102dfddfd 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -275,21 +275,41 @@ ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_MPC85XX_TSEC1) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); + if (p) + memcpy(p, bd->bi_enetaddr, 6); + + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len); + if (p) memcpy(p, bd->bi_enetaddr, 6); #endif #if defined(CONFIG_HAS_ETH1) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); + if (p) + memcpy(p, bd->bi_enet1addr, 6); + + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len); + if (p) memcpy(p, bd->bi_enet1addr, 6); #endif #if defined(CONFIG_HAS_ETH2) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len); + if (p) + memcpy(p, bd->bi_enet2addr, 6); + + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len); + if (p) memcpy(p, bd->bi_enet2addr, 6); #endif #if defined(CONFIG_HAS_ETH3) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len); + if (p) + memcpy(p, bd->bi_enet3addr, 6); + + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len); + if (p) memcpy(p, bd->bi_enet3addr, 6); #endif -- cgit v1.2.3 From 9343dbf85bc03033f2102d8e8543567c2c1ad2d2 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Sat, 24 Feb 2007 01:16:45 -0600 Subject: Tweak DDR ECC error counter Enable single-bit error counter when memory was cleared by ddr controller. Signed-off-by: Ed Swarthout Signed-off-by: Andy Fleming --- cpu/mpc85xx/spd_sdram.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 6da5367a706..4b3c4eb7067 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -786,14 +786,17 @@ spd_sdram(void) * Is this an ECC DDR chip? * But don't mess with it if the DDR controller will init mem. */ -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +#ifdef CONFIG_DDR_ECC if (spd.config == 0x02) { +#ifndef CONFIG_ECC_INIT_VIA_DDRCONTROLLER ddr->err_disable = 0x0000000d; +#endif ddr->err_sbe = 0x00ff0000; } + debug("DDR: err_disable = 0x%08x\n", ddr->err_disable); debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe); -#endif +#endif /* CONFIG_DDR_ECC */ asm("sync;isync;msync"); udelay(500); -- cgit v1.2.3 From 1f9a318cea14272edd10d63739e2d326c90f430e Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Fri, 23 Feb 2007 16:28:46 -0600 Subject: Only set ddrioovcr for 8548 rev1. Signed-off-by: Ed Swarthout Signed-off-by: Andy Fleming --- cpu/mpc85xx/spd_sdram.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 4b3c4eb7067..16a697d40c1 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -263,13 +263,14 @@ spd_sdram(void) } /* - * Adjust DDR II IO voltage biasing. It just makes it work. + * Adjust DDR II IO voltage biasing. + * Only 8548 rev 1 needs the fix */ - if (spd.mem_type == SPD_MEMTYPE_DDR2) { - gur->ddrioovcr = (0 - | 0x80000000 /* Enable */ - | 0x10000000 /* VSEL to 1.8V */ - ); + if ((SVR_VER(get_svr()) == SVR_8548_E) && + (SVR_MJREV(get_svr()) == 1) && + (spd.mem_type == SPD_MEMTYPE_DDR2)) { + gur->ddrioovcr = (0x80000000 /* Enable */ + | 0x10000000);/* VSEL to 1.8V */ } /* -- cgit v1.2.3 From 0d8c3a2096eaff8d7de89d45e9af4d4b0d4868fe Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Fri, 23 Feb 2007 17:12:25 -0600 Subject: Support 1G size on 8548 e500v2 and newer cores support 1G page sizes. Signed-off-by: Ed Swarthout Signed-off-by: Andy Fleming --- cpu/mpc85xx/spd_sdram.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 16a697d40c1..3777f49adcc 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -995,17 +995,24 @@ setup_laws_and_tlbs(unsigned int memsize) break; case 256: case 512: + tlb_size = BOOKE_PAGESZ_256M; + break; case 1024: case 2048: - tlb_size = BOOKE_PAGESZ_256M; + if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx)) + tlb_size = BOOKE_PAGESZ_1G; + else + tlb_size = BOOKE_PAGESZ_256M; break; default: puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n"); /* * The memory was not able to be mapped. + * Default to a small size. */ - return 0; + tlb_size = BOOKE_PAGESZ_64M; + memsize=64; break; } -- cgit v1.2.3 From 66ed6cca3f340f7a8a06d9272ae2ef8e96f0273d Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 23 Apr 2007 02:37:47 -0500 Subject: Reworked 85xx speed detection code Changed the code to read the registers and calculate the clock rates, rather than using a "switch" statement. Idea from Andrew Klossner Signed-off-by: Andy Fleming --- cpu/mpc85xx/speed.c | 44 ++++++++------------------------------------ 1 file changed, 8 insertions(+), 36 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index ca81ee73521..12359a2d64b 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -37,49 +37,21 @@ void get_sys_info (sys_info_t * sysInfo) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; - uint plat_ratio,e500_ratio; + uint plat_ratio,e500_ratio,half_freqSystemBus; plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; - switch(plat_ratio) { - case 0x02: - case 0x03: - case 0x04: - case 0x05: - case 0x06: - case 0x08: - case 0x09: - case 0x0a: - case 0x0c: - case 0x10: - sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; - break; - default: - sysInfo->freqSystemBus = 0; - break; - } - + sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; e500_ratio = (gur->porpllsr) & 0x003f0000; e500_ratio >>= 16; - switch(e500_ratio) { - case 0x04: - sysInfo->freqProcessor = 2*sysInfo->freqSystemBus; - break; - case 0x05: - sysInfo->freqProcessor = 5*sysInfo->freqSystemBus/2; - break; - case 0x06: - sysInfo->freqProcessor = 3*sysInfo->freqSystemBus; - break; - case 0x07: - sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2; - break; - default: - sysInfo->freqProcessor = 0; - break; - } + + /* Divide before multiply to avoid integer + * overflow for processor speeds above 2GHz */ + half_freqSystemBus = sysInfo->freqSystemBus/2; + sysInfo->freqProcessor = e500_ratio*half_freqSystemBus; } + int get_clocks (void) { sys_info_t sys_info; -- cgit v1.2.3 From 37ed6cdd4159195bfad68d8a237f6adda8f482cb Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Tue, 24 Apr 2007 14:03:45 +0200 Subject: ppc4xx: setup 440EPx/GRx ZMII/RGMII bridge depending on PFC register content. Signed-off-by: Matthias Fuchs --- cpu/ppc4xx/4xx_enet.c | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index cf56581d845..be4e82405eb 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -339,29 +339,41 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) { unsigned long zmiifer=0x0; + unsigned long pfc1; - /* - * Right now only 2*RGMII is supported. Please extend when needed. - * sr - 2006-08-29 - */ - switch (1) { - case 0: + mfsdr(sdr_pfc1, pfc1); + pfc1 &= SDR0_PFC1_SELECT_MASK; + + switch (pfc1) { + case SDR0_PFC1_SELECT_CONFIG_2: /* 1 x GMII port */ out32 (ZMII_FER, 0x00); out32 (RGMII_FER, 0x00000037); bis->bi_phymode[0] = BI_PHYMODE_GMII; bis->bi_phymode[1] = BI_PHYMODE_NONE; break; - case 1: + case SDR0_PFC1_SELECT_CONFIG_4: /* 2 x RGMII ports */ out32 (ZMII_FER, 0x00); out32 (RGMII_FER, 0x00000055); bis->bi_phymode[0] = BI_PHYMODE_RGMII; bis->bi_phymode[1] = BI_PHYMODE_RGMII; break; - case 2: + case SDR0_PFC1_SELECT_CONFIG_6: /* 2 x SMII ports */ - + out32 (ZMII_FER, + ((ZMII_FER_SMII) << ZMII_FER_V(0)) | + ((ZMII_FER_SMII) << ZMII_FER_V(1))); + out32 (RGMII_FER, 0x00000000); + bis->bi_phymode[0] = BI_PHYMODE_SMII; + bis->bi_phymode[1] = BI_PHYMODE_SMII; + break; + case SDR0_PFC1_SELECT_CONFIG_1_2: + /* only 1 x MII supported */ + out32 (ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); + out32 (RGMII_FER, 0x00000000); + bis->bi_phymode[0] = BI_PHYMODE_MII; + bis->bi_phymode[1] = BI_PHYMODE_NONE; break; default: break; -- cgit v1.2.3 From 5c5d3242935cf3543af01142627494434834cf98 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 25 Apr 2007 12:34:38 -0500 Subject: mpc83xx: minor fixups for 8313rdb introduction --- cpu/mpc83xx/pci.c | 1 + 1 file changed, 1 insertion(+) (limited to 'cpu') diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c index 2a2b0bd9028..785d6129daf 100644 --- a/cpu/mpc83xx/pci.c +++ b/cpu/mpc83xx/pci.c @@ -25,6 +25,7 @@ #include #include +#include #include #ifdef CONFIG_83XX_GENERIC_PCI -- cgit v1.2.3 From c1ab82669d9525998c34e802a12cad662723f22a Mon Sep 17 00:00:00 2001 From: James Yang Date: Fri, 16 Mar 2007 13:02:53 -0500 Subject: Rewrote picos_to_clk() to avoid rounding errors. Clarified that conversion is to DRAM clocks rather than platform clocks. Made function static to spd_sdram.c. Signed-off-by: James Yang Signed-off-by: Jon Loeliger --- cpu/mpc86xx/spd_sdram.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index ac9ff81ce60..f37ab430b32 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -51,20 +51,32 @@ extern int dma_xfer(void *dest, uint count, void *src); #define CFG_SUPER_BANK_INTERLEAVING 0 /* - * Convert picoseconds into clock cycles (rounding up if needed). + * Convert picoseconds into DRAM clock cycles (rounding up if needed). */ -int -picos_to_clk(int picos) +static unsigned int +picos_to_clk(unsigned int picos) { - int clks; - - clks = picos / (2000000000 / (get_bus_freq(0) / 1000)); - if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) { + /* use unsigned long long to avoid rounding errors */ + const unsigned long long ULL_2e12 = 2000000000000ULL; + unsigned long long clks; + unsigned long long clks_temp; + + if (! picos) + return 0; + + clks = get_bus_freq(0) * (unsigned long long) picos; + clks_temp = clks; + clks = clks / ULL_2e12; + if (clks_temp % ULL_2e12) { clks++; } - return clks; + if (clks > 0xFFFFFFFFULL) { + clks = 0xFFFFFFFFULL; + } + + return (unsigned int) clks; } -- cgit v1.2.3 From 54b2d434ae9d01787936f34fe1759cf3d7624ae3 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 30 Apr 2007 15:26:21 -0500 Subject: mpc83xx: replace elaborate boottime verbosity with 'clocks' command and fix CPU: to align with Board: display text. Signed-off-by: Kim Phillips --- cpu/mpc83xx/cpu.c | 8 +++++--- cpu/mpc83xx/speed.c | 10 ++++++++-- 2 files changed, 13 insertions(+), 5 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 332afaad9f5..e078f27a23d 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -52,7 +52,7 @@ int checkcpu(void) immr = (immap_t *)CFG_IMMR; - puts("CPU: "); + puts("CPU: "); switch (pvr & 0xffff0000) { case PVR_E300C1: @@ -158,10 +158,12 @@ int checkcpu(void) /* Multiple revisons of 834x processors may have the same SPRIDR value. * So use PVR to identify the revision number. */ - printf("Rev: %02x at %s MHz\n", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock)); + printf("Rev: %02x at %s MHz", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock)); #else - printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock)); + printf("Rev: %02x at %s MHz", spridr & 0x0000FFFF, strmhz(buf, clock)); #endif + printf(", CSB: %4d MHz\n", gd->csb_clk / 1000000); + return 0; } diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index 1a440310e5e..bf30616548e 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -25,6 +25,7 @@ #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -365,11 +366,11 @@ ulong get_bus_freq(ulong dummy) return gd->csb_clk; } -int print_clock_conf(void) +int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { printf("Clock configuration:\n"); - printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000); printf(" Core: %4d MHz\n", gd->core_clk / 1000000); + printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000); #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) printf(" QE: %4d MHz\n", gd->qe_clk / 1000000); printf(" BRG: %4d MHz\n", gd->brg_clk / 1000000); @@ -395,3 +396,8 @@ int print_clock_conf(void) #endif return 0; } + +U_BOOT_CMD(clocks, 1, 0, do_clocks, + "clocks - print clock configuration\n", + " clocks\n" +); -- cgit v1.2.3 From f64702b7fc8f8df39d31add770df6e372f9e9ce3 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 30 Apr 2007 13:59:50 -0500 Subject: Fix memory initialization on MPC8349E-mITX Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP. This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary on some ITX boards, notably those with a revision 3.1 CPU. Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into ddr->sdram_clk_cntl if CFG_DDR_SDRAM_CLK_CNTL is not defined. Signed-off-by: Timur Tabi Acked-by: Michael Benedict Signed-off-by: Kim Phillips --- cpu/mpc83xx/spd_sdram.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 41a1f1fc7b0..647813f68d9 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -693,11 +693,6 @@ long int spd_sdram() #ifdef CFG_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; -#else - /* SS_EN = 0, source synchronous disable - * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd - */ - ddr->sdram_clk_cntl = 0x00000000; #endif debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl); -- cgit v1.2.3 From a75af9bfd8fff0499efdbb90601cec5a2afef117 Mon Sep 17 00:00:00 2001 From: James Yang Date: Wed, 7 Feb 2007 15:28:04 -0600 Subject: Conditionalize 8641 Rev1.0 MCM workarounds Signed-off-by: James Yang Signed-off-by: Jon Loeliger --- cpu/mpc86xx/start.S | 42 ++++++++++++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 14 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 7406fe2248b..67c56db1a37 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -241,26 +241,40 @@ in_flash: bl setup_ccsrbar #endif - /* Fix for SMP linux - Changing arbitration to round-robin */ - lis r3, CFG_CCSRBAR@h - ori r3, r3, 0x1000 - xor r4, r4, r4 - li r4, 0x1000 - stw r4, 0(r3) - /* setup the law entries */ - bl law_entry + /* -- MPC8641 Rev 1.0 MCM Errata fixups -- */ + + /* skip fixups if not Rev 1.0 */ + mfspr r4, SVR + rlwinm r4,r4,0,24,31 + cmpwi r4,0x10 + bne 1f + + lis r3,MCM_ABCR@ha + lwz r4,MCM_ABCR@l(r3) /* ABCR -> r4 */ + + /* set ABCR[A_STRM_CNT] = 0 */ + rlwinm r4,r4,0,0,29 + + /* set ABCR[ARB_POLICY] to 0x1 (round-robin) */ + addi r0,r0,1 + rlwimi r4,r0,12,18,19 + + stw r4,MCM_ABCR@l(r3) /* r4 -> ABCR */ sync - /* Don't use this feature due to bug in 8641D PD4 */ - /* Disable ERD_DIS */ - lis r3, CFG_CCSRBAR@h - ori r3, r3, 0x1008 - lwz r4, 0(r3) + /* Set DBCR[ERD_DIS] */ + lis r3,MCM_DBCR@ha + lwz r4,MCM_DBCR@l(r3) oris r4, r4, 0x4000 - stw r4, 0(r3) + stw r4,MCM_DBCR@l(r3) + sync +1: + /* setup the law entries */ + bl law_entry sync + #if (EMULATOR_RUN == 1) /* On the emulator we want to adjust these ASAP */ /* otherwise things are sloooow */ -- cgit v1.2.3 From 6743105988fc44d5b0d30388c790607835aae7a6 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 23 Apr 2007 02:54:25 -0500 Subject: Add support for the 8568 MDS board This included some changes to common files: * Add 8568 processor SVR to various places * Add support for setting the qe bus-frequency value in the dts * Add the 8568MDS target to the Makefile Signed-off-by: Andy Fleming --- cpu/mpc85xx/cpu.c | 7 +++++++ cpu/mpc85xx/cpu_init.c | 2 -- 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index d5102dfddfd..63176d2841d 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -76,6 +76,9 @@ int checkcpu (void) case SVR_8544_E: puts("8544_E"); break; + case SVR_8568_E: + puts("8568_E"); + break; default: puts("Unknown"); break; @@ -265,6 +268,10 @@ ft_cpu_setup(void *blob, bd_t *bd) if (p != NULL) *p = cpu_to_be32(clock); + p = ft_get_prop(blob, "/qe@e0080000/" OF_CPU "/bus-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len); if (p != NULL) *p = cpu_to_be32(clock); diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 9f4d36c1ab4..9517146ed23 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -143,12 +143,10 @@ void cpu_init_f (void) memctl->br1 = CFG_BR1_PRELIM; #endif -#if !defined(CONFIG_MPC85xx) #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) memctl->or2 = CFG_OR2_PRELIM; memctl->br2 = CFG_BR2_PRELIM; #endif -#endif #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) memctl->or3 = CFG_OR3_PRELIM; -- cgit v1.2.3 From ffa621a0d12a1ccd81c936c567f8917a213787a8 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Sat, 24 Feb 2007 01:08:13 -0600 Subject: Cleaned up some 85xx PCI bugs * Cleaned up the CDS PCI Config Tables and added NULL entries to the end * Fixed PCIe LAWBAR assignemt to use the cpu-relative address * Fixed 85xx PCI code to assign powar region sizes based on the config values (rather than hard-coding them) * Fixed the 8548 CDS PCI2 IO to once again have 0 as the base address Signed-off-by: Andy Fleming --- cpu/mpc85xx/pci.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index 84f839ae1e4..3c1a323aad2 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -90,14 +90,14 @@ pci_mpc85xx_init(struct pci_controller *board_hose) pcix->powbar1 = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff; pcix->powbear1 = 0x00000000; pcix->powar1 = (POWAR_EN | POWAR_MEM_READ | - POWAR_MEM_WRITE | POWAR_MEM_512M); + POWAR_MEM_WRITE | (__ilog2(CFG_PCI1_MEM_SIZE) - 1)); pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; pcix->potear2 = 0x00000000; pcix->powbar2 = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff; pcix->powbear2 = 0x00000000; pcix->powar2 = (POWAR_EN | POWAR_IO_READ | - POWAR_IO_WRITE | POWAR_IO_1M); + POWAR_IO_WRITE | (__ilog2(CFG_PCI1_IO_SIZE) - 1)); pcix->pitar1 = 0x00000000; pcix->piwbar1 = 0x00000000; @@ -175,14 +175,14 @@ pci_mpc85xx_init(struct pci_controller *board_hose) pcix2->powbar1 = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff; pcix2->powbear1 = 0x00000000; pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ | - POWAR_MEM_WRITE | POWAR_MEM_512M); + POWAR_MEM_WRITE | (__ilog2(CFG_PCI2_MEM_SIZE) - 1)); pcix2->potar2 = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff; pcix2->potear2 = 0x00000000; pcix2->powbar2 = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff; pcix2->powbear2 = 0x00000000; pcix2->powar2 = (POWAR_EN | POWAR_IO_READ | - POWAR_IO_WRITE | POWAR_IO_1M); + POWAR_IO_WRITE | (__ilog2(CFG_PCI2_IO_SIZE) - 1)); pcix2->pitar1 = 0x00000000; pcix2->piwbar1 = 0x00000000; -- cgit v1.2.3 From 2f15278c2eb911c668b4fe562130b78cf554d139 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 5 May 2007 18:23:11 +0200 Subject: Coding stylke cleanup; update CHANGELOG. Signed-off-by: Wolfgang Denk --- cpu/mpc85xx/cpu.c | 18 +++++++++--------- cpu/ppc4xx/4xx_enet.c | 4 ++-- 2 files changed, 11 insertions(+), 11 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 63176d2841d..7735a52ccf1 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -71,14 +71,14 @@ int checkcpu (void) puts("8548_E"); break; case SVR_8544: - puts("8544"); - break; - case SVR_8544_E: - puts("8544_E"); - break; - case SVR_8568_E: - puts("8568_E"); - break; + puts("8544"); + break; + case SVR_8544_E: + puts("8544_E"); + break; + case SVR_8568_E: + puts("8568_E"); + break; default: puts("Unknown"); break; @@ -157,7 +157,7 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) /* e500 v2 core has reset control register */ volatile unsigned int * rstcr; rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0); - *rstcr = 0x2; /* HRESET_REQ */ + *rstcr = 0x2; /* HRESET_REQ */ }else{ /* * Initiate hard reset in debug control register DBCR0 diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index be4e82405eb..1200d021af6 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -344,7 +344,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) mfsdr(sdr_pfc1, pfc1); pfc1 &= SDR0_PFC1_SELECT_MASK; - switch (pfc1) { + switch (pfc1) { case SDR0_PFC1_SELECT_CONFIG_2: /* 1 x GMII port */ out32 (ZMII_FER, 0x00); @@ -361,7 +361,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) break; case SDR0_PFC1_SELECT_CONFIG_6: /* 2 x SMII ports */ - out32 (ZMII_FER, + out32 (ZMII_FER, ((ZMII_FER_SMII) << ZMII_FER_V(0)) | ((ZMII_FER_SMII) << ZMII_FER_V(1))); out32 (RGMII_FER, 0x00000000); -- cgit v1.2.3 From a9d87e2707dcb249f6bb7f7ff7e00acd8cda9fd2 Mon Sep 17 00:00:00 2001 From: Grzegorz Wianecki Date: Sun, 29 Apr 2007 14:01:54 +0200 Subject: [PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot message MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up message. Use PVR to distinguish between the two variants, and print proper CPU information. Signed-off-by: Grzegorz Wianecki Signed-off-by: Bartlomiej Sieka Signed-off-by: Grant Likely --- cpu/mpc5xxx/cpu.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index 813aa7935d1..73b166d999e 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -53,12 +53,16 @@ int checkcpu (void) #else svr = get_svr(); pvr = get_pvr(); - switch (SVR_VER (svr)) { - case SVR_MPC5200: - printf ("MPC5200"); + + switch (pvr) { + case PVR_5200: + printf("MPC5200"); + break; + case PVR_5200B: + printf("MPC5200B"); break; default: - printf ("MPC52?? (SVR %08x)", svr); + printf("Unknown MPC5xxx"); break; } -- cgit v1.2.3 From ac4cd59d59c9bf3f89cb7a344abf8184d678f562 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Sat, 5 May 2007 08:12:30 +0200 Subject: 5xxx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. Signed-off-by: Timur Tabi Acked-by: Grant Likely --- cpu/mpc5xxx/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index 73b166d999e..1eac2bbfbe1 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -131,5 +131,9 @@ ft_cpu_setup(void *blob, bd_t *bd) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enetaddr, 6); + + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/local-mac-address", &len); + if (p != NULL) + memcpy(p, bd->bi_enetaddr, 6); } #endif -- cgit v1.2.3 From 42efed6130c8fcf7da881385b5427065d2801757 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 7 May 2007 17:22:25 +0200 Subject: fix: interrupt handler for multiple sources --- cpu/microblaze/interrupts.c | 19 ++++++++++++------- cpu/microblaze/timer.c | 4 +--- 2 files changed, 13 insertions(+), 10 deletions(-) (limited to 'cpu') diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c index 2db847cd02c..115e58d7f08 100644 --- a/cpu/microblaze/interrupts.c +++ b/cpu/microblaze/interrupts.c @@ -27,6 +27,7 @@ #include #include #include +#include #undef DEBUG_INT @@ -106,7 +107,6 @@ void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, void *arg) act->count = 0; enable_one_interrupt (irq); } else { /* disable */ - act->handler = (interrupt_handler_t *) def_hdlr; act->arg = (void *)irq; disable_one_interrupt (irq); @@ -147,12 +147,13 @@ int interrupts_init (void) void interrupt_handler (void) { - int irqs; - irqs = (intc->isr & intc->ier); /* find active interrupt */ - + int irqs = (intc->isr & intc->ier); /* find active interrupt */ + int i = 1; #ifdef DEBUG_INT + int value; printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, intc->iar, intc->mer); + R14(value); printf ("Interrupt handler on %x line, r14 %x\n", irqs, value); #endif struct irq_action *act = vecs; @@ -165,15 +166,19 @@ void interrupt_handler (void) #endif act->handler (act->arg); act->count++; + intc->iar = i; + return; } irqs >>= 1; act++; + i <<= 1; } - intc->iar = 0xFFFFFFFF; /* erase all events */ -#ifdef DEBUG + +#ifdef DEBUG_INT printf ("Dump INTC reg, isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, intc->iar, intc->mer); - printf ("Interrupt handler on %x line, r14\n", irqs); + R14(value); + printf ("Interrupt handler on %x line, r14 %x\n", irqs, value); #endif } #endif diff --git a/cpu/microblaze/timer.c b/cpu/microblaze/timer.c index be4fd57cc49..ab1cb127492 100644 --- a/cpu/microblaze/timer.c +++ b/cpu/microblaze/timer.c @@ -24,6 +24,7 @@ #include #include +#include volatile int timestamp = 0; @@ -44,9 +45,6 @@ void set_timer (ulong t) #ifdef CFG_INTC_0 #ifdef CFG_TIMER_0 -extern void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, - void *arg); - microblaze_timer_t *tmr = (microblaze_timer_t *) (CFG_TIMER_0_ADDR); void timer_isr (void *arg) -- cgit v1.2.3 From fb7c2dbef02c9f6f8d7b04ec4c2bfb91418b9c01 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 7 May 2007 19:12:43 +0200 Subject: fix: clean interrupt --- cpu/microblaze/Makefile | 3 ++- cpu/microblaze/interrupts.c | 13 +++++++++++-- 2 files changed, 13 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/microblaze/Makefile b/cpu/microblaze/Makefile index db1afa553dd..b7be5e146cb 100644 --- a/cpu/microblaze/Makefile +++ b/cpu/microblaze/Makefile @@ -26,7 +26,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -SOBJS = dcache.o icache.o irq.o disable_int.o enable_int.o +#SOBJS = dcache.o icache.o irq.o disable_int.o enable_int.o +SOBJS = dcache.o icache.o irq.o COBJS = cpu.o interrupts.o cache.o exception.o timer.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c index 115e58d7f08..c0c92ec5599 100644 --- a/cpu/microblaze/interrupts.c +++ b/cpu/microblaze/interrupts.c @@ -36,12 +36,14 @@ extern void microblaze_enable_interrupts (void); void enable_interrupts (void) { - microblaze_enable_interrupts (); + __asm__ __volatile__ ("msrset r0, 0x2"); + //microblaze_enable_interrupts (); } int disable_interrupts (void) { - microblaze_disable_interrupts (); + __asm__ __volatile__ ("msrclr r0, 0x2"); + //microblaze_disable_interrupts (); return 0; } @@ -49,6 +51,10 @@ int disable_interrupts (void) #ifdef CFG_TIMER_0 extern void timer_init (void); #endif +#ifdef CFG_FSL_2 +extern void fsl_init2 (void); +#endif + static struct irq_action vecs[CFG_INTC_0_NUM]; @@ -140,6 +146,9 @@ int interrupts_init (void) intc_init (); #ifdef CFG_TIMER_0 timer_init (); +#endif +#ifdef CFG_FSL_2 + fsl_init2 (); #endif enable_interrupts (); return 0; -- cgit v1.2.3 From f3f001a341ef185d0f13841be5b5dc3395aacc31 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 7 May 2007 19:25:08 +0200 Subject: fix: remove asm code --- cpu/microblaze/Makefile | 3 +- cpu/microblaze/cache.c | 16 ++++++++++ cpu/microblaze/dcache.S | 68 ------------------------------------------- cpu/microblaze/disable_int.S | 46 ----------------------------- cpu/microblaze/enable_int.S | 38 ------------------------ cpu/microblaze/icache.S | 69 -------------------------------------------- 6 files changed, 17 insertions(+), 223 deletions(-) delete mode 100644 cpu/microblaze/dcache.S delete mode 100644 cpu/microblaze/disable_int.S delete mode 100644 cpu/microblaze/enable_int.S delete mode 100644 cpu/microblaze/icache.S (limited to 'cpu') diff --git a/cpu/microblaze/Makefile b/cpu/microblaze/Makefile index b7be5e146cb..9d542013ccc 100644 --- a/cpu/microblaze/Makefile +++ b/cpu/microblaze/Makefile @@ -26,8 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -#SOBJS = dcache.o icache.o irq.o disable_int.o enable_int.o -SOBJS = dcache.o icache.o irq.o +SOBJS = irq.o COBJS = cpu.o interrupts.o cache.o exception.o timer.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c index fc388ebb562..683044caeaa 100644 --- a/cpu/microblaze/cache.c +++ b/cpu/microblaze/cache.c @@ -45,4 +45,20 @@ int icache_status (void) __asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory"); return i; } + +void icache_enable (void) { + __asm__ __volatile__ ("msrset r0, 0x80"); +} + +void icache_disable(void) { + __asm__ __volatile__ ("msrclr r0, 0x80"); +} + +void dcache_enable (void) { + __asm__ __volatile__ ("msrset r0, 0x20"); +} + +void dcache_disable(void) { + __asm__ __volatile__ ("msrclr r0, 0x20"); +} #endif diff --git a/cpu/microblaze/dcache.S b/cpu/microblaze/dcache.S deleted file mode 100644 index eaf96717ebb..00000000000 --- a/cpu/microblaze/dcache.S +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - .text - .globl dcache_enable - .ent dcache_enable - .align 2 -dcache_enable: - /* Make space on stack for a temporary */ - addi r1, r1, -4 - /* Save register r12 */ - swi r12, r1, 0 - /* Read the MSR register */ - mfs r12, rmsr - /* Set the instruction enable bit */ - ori r12, r12, 0x80 - /* Save the MSR register */ - mts rmsr, r12 - /* Load register r12 */ - lwi r12, r1, 0 - /* Return */ - rtsd r15, 8 - /* Update stack in the delay slot */ - addi r1, r1, 4 - .end dcache_enable - - .text - .globl dcache_disable - .ent dcache_disable - .align 2 -dcache_disable: - /* Make space on stack for a temporary */ - addi r1, r1, -4 - /* Save register r12 */ - swi r12, r1, 0 - /* Read the MSR register */ - mfs r12, rmsr - /* Clear the data cache enable bit */ - andi r12, r12, ~0x80 - /* Save the MSR register */ - mts rmsr, r12 - /* Load register r12 */ - lwi r12, r1, 0 - /* Return */ - rtsd r15, 8 - /* Update stack in the delay slot */ - addi r1, r1, 4 - .end dcache_disable diff --git a/cpu/microblaze/disable_int.S b/cpu/microblaze/disable_int.S deleted file mode 100644 index aecd79513ca..00000000000 --- a/cpu/microblaze/disable_int.S +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - .text - .globl microblaze_disable_interrupts - .ent microblaze_disable_interrupts - .align 2 -microblaze_disable_interrupts: - #Make space on stack for a temporary - addi r1, r1, -4 - #Save register r12 - swi r12, r1, 0 - #Read the MSR register - mfs r12, rmsr - #Clear the interrupt enable bit - andi r12, r12, ~2 - #Save the MSR register - mts rmsr, r12 - #Load register r12 - lwi r12, r1, 0 - #Return - rtsd r15, 8 - #Update stack in the delay slot - addi r1, r1, 4 - .end microblaze_disable_interrupts diff --git a/cpu/microblaze/enable_int.S b/cpu/microblaze/enable_int.S deleted file mode 100644 index c096c6c3c05..00000000000 --- a/cpu/microblaze/enable_int.S +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - .text - .globl microblaze_enable_interrupts - .ent microblaze_enable_interrupts - .align 2 -microblaze_enable_interrupts: - addi r1, r1, -4 - swi r12, r1, 0 - mfs r12, rmsr - ori r12, r12, 2 - mts rmsr, r12 - lwi r12, r1, 0 - rtsd r15, 8 - addi r1, r1, 4 - .end microblaze_enable_interrupts diff --git a/cpu/microblaze/icache.S b/cpu/microblaze/icache.S deleted file mode 100644 index 25940d106e3..00000000000 --- a/cpu/microblaze/icache.S +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - .text - .globl icache_enable - .ent icache_enable - .align 2 -icache_enable: - /* Make space on stack for a temporary */ - addi r1, r1, -4 - /* Save register r12 */ - swi r12, r1, 0 - /* Read the MSR register */ - mfs r12, rmsr - /* Set the instruction enable bit */ - ori r12, r12, 0x20 - /* Save the MSR register */ - mts rmsr, r12 - /* Load register r12 */ - lwi r12, r1, 0 - /* Return */ - rtsd r15, 8 - /* Update stack in the delay slot */ - addi r1, r1, 4 - .end icache_enable - - .text - .globl icache_disable - .ent icache_disable - .align 2 -icache_disable: - /* Make space on stack for a temporary */ - addi r1, r1, -4 - /* Save register r12 */ - swi r12, r1, 0 - /* Read the MSR register */ - mfs r12, rmsr - /* Clear the instruction enable bit */ - andi r12, r12, ~0x20 - /* Save the MSR register */ - mts rmsr, r12 - /* Load register r12 */ - lwi r12, r1, 0 - /* Return */ - rtsd r15, 8 - /* Update stack in the delay slot */ - addi r1, r1, 4 - .end icache_disable -- cgit v1.2.3 From 792032baa7d625e34c981ab6df521911bd8dc861 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 7 May 2007 19:30:12 +0200 Subject: fix: interrupt handler remove asm code --- cpu/microblaze/interrupts.c | 2 -- cpu/microblaze/irq.S | 9 +-------- 2 files changed, 1 insertion(+), 10 deletions(-) (limited to 'cpu') diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c index c0c92ec5599..dd6a0c7776a 100644 --- a/cpu/microblaze/interrupts.c +++ b/cpu/microblaze/interrupts.c @@ -37,13 +37,11 @@ extern void microblaze_enable_interrupts (void); void enable_interrupts (void) { __asm__ __volatile__ ("msrset r0, 0x2"); - //microblaze_enable_interrupts (); } int disable_interrupts (void) { __asm__ __volatile__ ("msrclr r0, 0x2"); - //microblaze_disable_interrupts (); return 0; } diff --git a/cpu/microblaze/irq.S b/cpu/microblaze/irq.S index a4e3fbfad67..393d6e8dd42 100644 --- a/cpu/microblaze/irq.S +++ b/cpu/microblaze/irq.S @@ -151,14 +151,7 @@ _interrupt_handler: addi r1, r1, 4 /* enable_interrupt */ - addi r1, r1, -4 - swi r12, r1, 0 - mfs r12, rmsr - ori r12, r12, 2 - mts rmsr, r12 - lwi r12, r1, 0 - addi r1, r1, 4 - nop + msrset r0, 2 bra r14 nop nop -- cgit v1.2.3 From 008861a2f3ef2c062744d733787c7e530a1b8761 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Mon, 7 May 2007 22:36:15 +0200 Subject: [MPC5xxx] There are networking problems on the Motion-PRO board with current PHY initalization code (tftp timeouts all the time). This commit temporarily disables PHY initalization sequence to make the networking operational, until a fix is found. --- cpu/mpc5xxx/fec.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c index e6392340a94..0b8f24d18a7 100644 --- a/cpu/mpc5xxx/fec.c +++ b/cpu/mpc5xxx/fec.c @@ -395,7 +395,9 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis) static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) { mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; +#ifndef CONFIG_MOTIONPRO const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */ +#endif /* !CONFIG_MOTIONPRO */ #if (DEBUG & 0x1) printf ("mpc5xxx_fec_init_phy... Begin\n"); @@ -428,6 +430,14 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) */ fec->eth->imask = 0x00000000; +/* + * In original Promess-provided code PHY initialization is disabled with the + * following comment: "Phy initialization is DISABLED for now. There was a + * problem with running 100 Mbps on PRO board". Thus we temporarily disable + * PHY initialization for the Motion-PRO board, until a proper fix is found. + */ + +#ifndef CONFIG_MOTIONPRO if (fec->xcv_type != SEVENWIRE) { /* * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock @@ -550,6 +560,7 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) } } +#endif /* !CONFIG_MOTIONPRO */ #if (DEBUG & 0x2) if (fec->xcv_type != SEVENWIRE) -- cgit v1.2.3 From fb05f6da35ea1c15c553abe6f23f656bf18dc5db Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 7 May 2007 23:58:31 +0200 Subject: new: USE_MSR_INTR support --- cpu/microblaze/cache.c | 9 +++++---- cpu/microblaze/interrupts.c | 4 ++-- cpu/microblaze/irq.S | 14 ++++++++++++++ 3 files changed, 21 insertions(+), 6 deletions(-) mode change 100644 => 100755 cpu/microblaze/cache.c mode change 100644 => 100755 cpu/microblaze/interrupts.c mode change 100644 => 100755 cpu/microblaze/irq.S (limited to 'cpu') diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c old mode 100644 new mode 100755 index 683044caeaa..4f36a84ec4b --- a/cpu/microblaze/cache.c +++ b/cpu/microblaze/cache.c @@ -23,6 +23,7 @@ */ #include +#include #if (CONFIG_COMMANDS & CFG_CMD_CACHE) @@ -47,18 +48,18 @@ int icache_status (void) } void icache_enable (void) { - __asm__ __volatile__ ("msrset r0, 0x80"); + MSRSET(0x20); } void icache_disable(void) { - __asm__ __volatile__ ("msrclr r0, 0x80"); + MSRCLR(0x20); } void dcache_enable (void) { - __asm__ __volatile__ ("msrset r0, 0x20"); + MSRSET(0x80); } void dcache_disable(void) { - __asm__ __volatile__ ("msrclr r0, 0x20"); + MSRCLR(0x80); } #endif diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c old mode 100644 new mode 100755 index dd6a0c7776a..b61153f8e6f --- a/cpu/microblaze/interrupts.c +++ b/cpu/microblaze/interrupts.c @@ -36,12 +36,12 @@ extern void microblaze_enable_interrupts (void); void enable_interrupts (void) { - __asm__ __volatile__ ("msrset r0, 0x2"); + MSRSET(0x2); } int disable_interrupts (void) { - __asm__ __volatile__ ("msrclr r0, 0x2"); + MSRCLR(0x2); return 0; } diff --git a/cpu/microblaze/irq.S b/cpu/microblaze/irq.S old mode 100644 new mode 100755 index 393d6e8dd42..e1fc19046c7 --- a/cpu/microblaze/irq.S +++ b/cpu/microblaze/irq.S @@ -23,6 +23,7 @@ */ #include +#include .text .global _interrupt_handler _interrupt_handler: @@ -151,7 +152,20 @@ _interrupt_handler: addi r1, r1, 4 /* enable_interrupt */ +#ifdef XILINX_USE_MSR_INSTR msrset r0, 2 +#else + /* FIXME unstable in stressed mode - two irqs */ + nop + addi r1, r1, -4 + swi r12, r1, 0 + mfs r12, rmsr + ori r12, r12, 2 + mts rmsr, r12 + lwi r12, r1, 0 + addi r1, r1, 4 + nop +#endif bra r14 nop nop -- cgit v1.2.3 From 1a50f164beb065f360fbddb76029607d6b099698 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 8 May 2007 14:52:52 +0200 Subject: add: Microblaze V5 exception handling --- cpu/microblaze/exception.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/microblaze/exception.c b/cpu/microblaze/exception.c index b135acbad9d..87ecbeaa49a 100644 --- a/cpu/microblaze/exception.c +++ b/cpu/microblaze/exception.c @@ -23,15 +23,16 @@ */ #include +#include void _hw_exception_handler (void) { int address = 0; int state = 0; /* loading address of exception EAR */ - __asm__ __volatile ("mfs %0,rear"::"r" (address):"memory"); + MFSEAR(address); /* loading excetpion state register ESR */ - __asm__ __volatile ("mfs %0,resr"::"r" (state):"memory"); + MFSESR(state); printf ("Hardware exception at 0x%x address\n", address); switch (state & 0x1f) { /* mask on exception cause */ case 0x1: @@ -49,6 +50,11 @@ void _hw_exception_handler (void) case 0x5: puts ("Divide by zero exception\n"); break; +#ifdef MICROBLAZE_V5 + case 0x1000: + puts ("Exception in delay slot\n"); + break; +#endif default: puts ("Undefined cause\n"); break; -- cgit v1.2.3 From e69f66c6ebe82bbbd1da766bc4eda40ec7ee5af1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 8 May 2007 15:57:43 +0200 Subject: add: reading special purpose registers --- cpu/microblaze/exception.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/microblaze/exception.c b/cpu/microblaze/exception.c index 87ecbeaa49a..d76b05a5262 100644 --- a/cpu/microblaze/exception.c +++ b/cpu/microblaze/exception.c @@ -30,9 +30,9 @@ void _hw_exception_handler (void) int address = 0; int state = 0; /* loading address of exception EAR */ - MFSEAR(address); + MFS (address, rear); /* loading excetpion state register ESR */ - MFSESR(state); + MFS (state, resr); printf ("Hardware exception at 0x%x address\n", address); switch (state & 0x1f) { /* mask on exception cause */ case 0x1: -- cgit v1.2.3 From 160131bf965785419626df6c388729fe0b597992 Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Wed, 9 May 2007 11:41:58 +0100 Subject: Add the files for the SMN42 board --- cpu/arm720t/lpc2292/Makefile | 50 ++++++++ cpu/arm720t/lpc2292/flash.c | 249 ++++++++++++++++++++++++++++++++++++++++ cpu/arm720t/lpc2292/iap_entry.S | 7 ++ cpu/arm720t/lpc2292/mmc.c | 157 +++++++++++++++++++++++++ cpu/arm720t/lpc2292/mmc_hw.c | 233 +++++++++++++++++++++++++++++++++++++ cpu/arm720t/lpc2292/mmc_hw.h | 29 +++++ cpu/arm720t/lpc2292/spi.c | 40 +++++++ 7 files changed, 765 insertions(+) create mode 100644 cpu/arm720t/lpc2292/Makefile create mode 100644 cpu/arm720t/lpc2292/flash.c create mode 100644 cpu/arm720t/lpc2292/iap_entry.S create mode 100644 cpu/arm720t/lpc2292/mmc.c create mode 100644 cpu/arm720t/lpc2292/mmc_hw.c create mode 100644 cpu/arm720t/lpc2292/mmc_hw.h create mode 100644 cpu/arm720t/lpc2292/spi.c (limited to 'cpu') diff --git a/cpu/arm720t/lpc2292/Makefile b/cpu/arm720t/lpc2292/Makefile new file mode 100644 index 00000000000..240f1e3b3b5 --- /dev/null +++ b/cpu/arm720t/lpc2292/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = flash.o mmc.o mmc_hw.o spi.o +SOBJS = $(obj)iap_entry.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +# this MUST be compiled as thumb code! +$(SOBJS): + $(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm720t/lpc2292/flash.c b/cpu/arm720t/lpc2292/flash.c new file mode 100644 index 00000000000..e5c869722dc --- /dev/null +++ b/cpu/arm720t/lpc2292/flash.c @@ -0,0 +1,249 @@ +/* + * (C) Copyright 2006 Embedded Artists AB + * + * Modified to remove all but the IAP-command related code by + * Gary Jennejohn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* IAP commands use 32 bytes at the top of CPU internal sram, we + use 512 bytes below that */ +#define COPY_BUFFER_LOCATION 0x40003de0 + +#define IAP_LOCATION 0x7ffffff1 +#define IAP_CMD_PREPARE 50 +#define IAP_CMD_COPY 51 +#define IAP_CMD_ERASE 52 +#define IAP_CMD_CHECK 53 +#define IAP_CMD_ID 54 +#define IAP_CMD_VERSION 55 +#define IAP_CMD_COMPARE 56 + +#define IAP_RET_CMD_SUCCESS 0 + +static unsigned long command[5]; +static unsigned long result[2]; + +extern void iap_entry(unsigned long * command, unsigned long * result); + +/*----------------------------------------------------------------------- + * + */ +static int get_flash_sector(flash_info_t * info, ulong flash_addr) +{ + int i; + + for(i = 1; i < (info->sector_count); i++) { + if (flash_addr < (info->start[i])) + break; + } + + return (i-1); +} + +/*----------------------------------------------------------------------- + * This function assumes that flash_addr is aligned on 512 bytes boundary + * in flash. This function also assumes that prepare have been called + * for the sector in question. + */ +int lpc2292_copy_buffer_to_flash(flash_info_t * info, ulong flash_addr) +{ + int first_sector; + int last_sector; + + first_sector = get_flash_sector(info, flash_addr); + last_sector = get_flash_sector(info, flash_addr + 512 - 1); + + /* prepare sectors for write */ + command[0] = IAP_CMD_PREPARE; + command[1] = first_sector; + command[2] = last_sector; + iap_entry(command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf("IAP prepare failed\n"); + return ERR_PROG_ERROR; + } + + command[0] = IAP_CMD_COPY; + command[1] = flash_addr; + command[2] = COPY_BUFFER_LOCATION; + command[3] = 512; + command[4] = CFG_SYS_CLK_FREQ >> 10; + iap_entry(command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf("IAP copy failed\n"); + return 1; + } + + return 0; +} + +/*----------------------------------------------------------------------- + */ + +int lpc2292_flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag; + int prot; + int sect; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + + flag = disable_interrupts(); + + printf ("Erasing %d sectors starting at sector %2d.\n" + "This make take some time ... ", + s_last - s_first + 1, s_first); + + command[0] = IAP_CMD_PREPARE; + command[1] = s_first; + command[2] = s_last; + iap_entry(command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf("IAP prepare failed\n"); + return ERR_PROTECTED; + } + + command[0] = IAP_CMD_ERASE; + command[1] = s_first; + command[2] = s_last; + command[3] = CFG_SYS_CLK_FREQ >> 10; + iap_entry(command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf("IAP erase failed\n"); + return ERR_PROTECTED; + } + + if (flag) + enable_interrupts(); + + return ERR_OK; +} + +int lpc2292_write_buff (flash_info_t * info, uchar * src, ulong addr, + ulong cnt) +{ + int first_copy_size; + int last_copy_size; + int first_block; + int last_block; + int nbr_mid_blocks; + uchar memmap_value; + ulong i; + uchar* src_org; + uchar* dst_org; + int ret = ERR_OK; + + src_org = src; + dst_org = (uchar*)addr; + + first_block = addr / 512; + last_block = (addr + cnt) / 512; + nbr_mid_blocks = last_block - first_block - 1; + + first_copy_size = 512 - (addr % 512); + last_copy_size = (addr + cnt) % 512; + + debug("\ncopy first block: (1) %lX -> %lX 0x200 bytes, " + "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n", + (ulong)(first_block * 512), + (ulong)COPY_BUFFER_LOCATION, + (ulong)src, + (ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size), + first_copy_size, + (ulong)COPY_BUFFER_LOCATION, + (ulong)(first_block * 512)); + + /* copy first block */ + memcpy((void*)COPY_BUFFER_LOCATION, + (void*)(first_block * 512), 512); + memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size), + src, first_copy_size); + lpc2292_copy_buffer_to_flash(info, first_block * 512); + src += first_copy_size; + addr += first_copy_size; + + /* copy middle blocks */ + for (i = 0; i < nbr_mid_blocks; i++) { + debug("copy middle block: %lX -> %lX 512 bytes, " + "%lX -> %lX 512 bytes\n", + (ulong)src, + (ulong)COPY_BUFFER_LOCATION, + (ulong)COPY_BUFFER_LOCATION, + (ulong)addr); + + memcpy((void*)COPY_BUFFER_LOCATION, src, 512); + lpc2292_copy_buffer_to_flash(info, addr); + src += 512; + addr += 512; + } + + + if (last_copy_size > 0) { + debug("copy last block: (1) %lX -> %lX 0x200 bytes, " + "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n", + (ulong)(last_block * 512), + (ulong)COPY_BUFFER_LOCATION, + (ulong)src, + (ulong)(COPY_BUFFER_LOCATION), + last_copy_size, + (ulong)COPY_BUFFER_LOCATION, + (ulong)addr); + + /* copy last block */ + memcpy((void*)COPY_BUFFER_LOCATION, + (void*)(last_block * 512), 512); + memcpy((void*)COPY_BUFFER_LOCATION, + src, last_copy_size); + lpc2292_copy_buffer_to_flash(info, addr); + } + + /* verify write */ + memmap_value = GET8(MEMMAP); + + disable_interrupts(); + + PUT8(MEMMAP, 01); /* we must make sure that initial 64 + bytes are taken from flash when we + do the compare */ + + for (i = 0; i < cnt; i++) { + if (*dst_org != *src_org){ + printf("Write failed. Byte %lX differs\n", i); + ret = ERR_PROG_ERROR; + break; + } + dst_org++; + src_org++; + } + + PUT8(MEMMAP, memmap_value); + enable_interrupts(); + + return ret; +} diff --git a/cpu/arm720t/lpc2292/iap_entry.S b/cpu/arm720t/lpc2292/iap_entry.S new file mode 100644 index 00000000000..c31d5190bd7 --- /dev/null +++ b/cpu/arm720t/lpc2292/iap_entry.S @@ -0,0 +1,7 @@ +IAP_ADDRESS: .word 0x7FFFFFF1 + +.globl iap_entry +iap_entry: + ldr r2, IAP_ADDRESS + bx r2 + mov pc, lr diff --git a/cpu/arm720t/lpc2292/mmc.c b/cpu/arm720t/lpc2292/mmc.c new file mode 100644 index 00000000000..fd7f149b66c --- /dev/null +++ b/cpu/arm720t/lpc2292/mmc.c @@ -0,0 +1,157 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "mmc_hw.h" +#include + +#ifdef CONFIG_MMC + +#undef MMC_DEBUG + +static block_dev_desc_t mmc_dev; + +/* these are filled out by a call to mmc_hw_get_parameters */ +static int hw_size; /* in kbytes */ +static int hw_nr_sects; +static int hw_sect_size; /* in bytes */ + +block_dev_desc_t * mmc_get_dev(int dev) +{ + return (block_dev_desc_t *)(&mmc_dev); +} + +unsigned long mmc_block_read(int dev, + unsigned long start, + lbaint_t blkcnt, + void *buffer) +{ + unsigned long rc = 0; + unsigned char *p = (unsigned char *)buffer; + unsigned long i; + unsigned long addr = start; + +#ifdef MMC_DEBUG + printf("mmc_block_read: start=%lu, blkcnt=%lu\n", start, + (unsigned long)blkcnt); +#endif + + for(i = 0; i < (unsigned long)blkcnt; i++) { +#ifdef MMC_DEBUG + printf("mmc_read_sector: addr=%lu, buffer=%p\n", addr, p); +#endif + (void)mmc_read_sector(addr, p); + rc++; + addr++; + p += hw_sect_size; + } + + return rc; +} + +/*----------------------------------------------------------------------------- + * Read hardware paramterers (sector size, size, number of sectors) + */ +static int mmc_hw_get_parameters(void) +{ + unsigned char csddata[16]; + unsigned int sizemult; + unsigned int size; + + mmc_read_csd(csddata); + hw_sect_size = 1<<(csddata[5] & 0x0f); + size = ((csddata[6]&0x03)<<10)+(csddata[7]<<2)+(csddata[8]&0xc0); + sizemult = ((csddata[10] & 0x80)>>7)+((csddata[9] & 0x03)<<1); + hw_nr_sects = (size+1)*(1<<(sizemult+2)); + hw_size = hw_nr_sects*hw_sect_size/1024; + +#ifdef MMC_DEBUG + printf("mmc_hw_get_parameters: hw_sect_size=%d, hw_nr_sects=%d, " + "hw_size=%d\n", hw_sect_size, hw_nr_sects, hw_size); +#endif + + return 0; +} + +int mmc_init(int verbose) +{ + int ret = -ENODEV; + + if (verbose) + printf("mmc_init\n"); + + spi_init(); + /* this meeds to be done twice */ + mmc_hw_init(); + udelay(1000); + mmc_hw_init(); + + mmc_hw_get_parameters(); + + mmc_dev.if_type = IF_TYPE_MMC; + mmc_dev.part_type = PART_TYPE_DOS; + mmc_dev.dev = 0; + mmc_dev.lun = 0; + mmc_dev.type = 0; + mmc_dev.blksz = hw_sect_size; + mmc_dev.lba = hw_nr_sects; + sprintf((char*)mmc_dev.vendor, "Unknown vendor"); + sprintf((char*)mmc_dev.product, "Unknown product"); + sprintf((char*)mmc_dev.revision, "N/A"); + mmc_dev.removable = 0; /* should be true??? */ + mmc_dev.block_read = mmc_block_read; + + fat_register_device(&mmc_dev, 1); + + ret = 0; + + return ret; +} + +int mmc_write(uchar * src, ulong dst, int size) +{ +#ifdef MMC_DEBUG + printf("mmc_write: src=%p, dst=%lu, size=%u\n", src, dst, size); +#endif + /* Since mmc2info always returns 0 this function will never be called */ + return 0; +} + +int mmc_read(ulong src, uchar * dst, int size) +{ +#ifdef MMC_DEBUG + printf("mmc_read: src=%lu, dst=%p, size=%u\n", src, dst, size); +#endif + /* Since mmc2info always returns 0 this function will never be called */ + return 0; +} + +int mmc2info(ulong addr) +{ + /* This function is used by cmd_cp to determine if source or destination + address resides on MMC-card or not. We do not support copy to and from + MMC-card so we always return 0. */ + return 0; +} + +#endif /* CONFIG_MMC */ diff --git a/cpu/arm720t/lpc2292/mmc_hw.c b/cpu/arm720t/lpc2292/mmc_hw.c new file mode 100644 index 00000000000..b4dc4a6e2f1 --- /dev/null +++ b/cpu/arm720t/lpc2292/mmc_hw.c @@ -0,0 +1,233 @@ +/* + This code was original written by Ulrich Radig and modified by + Embedded Artists AB (www.embeddedartists.com). + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include +#include +#include +#include + +#define MMC_Enable() PUT32(IO1CLR, 1l << 22) +#define MMC_Disable() PUT32(IO1SET, 1l << 22) +#define mmc_spi_cfg() spi_set_clock(8); spi_set_cfg(0, 1, 0); + +static unsigned char Write_Command_MMC (unsigned char *CMD); +static void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, + unsigned short int Bytes); + +/* initialize the hardware */ +int mmc_hw_init(void) +{ + unsigned long a; + unsigned short int Timeout = 0; + unsigned char b; + unsigned char CMD[] = {0x40, 0x00, 0x00, 0x00, 0x00, 0x95}; + + /* set-up GPIO and SPI */ + (*((volatile unsigned long *)PINSEL2)) &= ~(1l << 3); /* clear bit 3 */ + (*((volatile unsigned long *)IO1DIR)) |= (1l << 22); /* set bit 22 (output) */ + + MMC_Disable(); + + spi_lock(); + spi_set_clock(248); + spi_set_cfg(0, 1, 0); + MMC_Enable(); + + /* waste some time */ + for(a=0; a < 20000; a++) + asm("nop"); + + /* Put the MMC/SD-card into SPI-mode */ + for (b = 0; b < 10; b++) /* Sends min 74+ clocks to the MMC/SD-card */ + spi_write(0xff); + + /* Sends command CMD0 to MMC/SD-card */ + while (Write_Command_MMC(CMD) != 1) { + if (Timeout++ > 200) { + MMC_Disable(); + spi_unlock(); + return(1); /* Abort with command 1 (return 1) */ + } + } + /* Sends Command CMD1 an MMC/SD-card */ + Timeout = 0; + CMD[0] = 0x41;/* Command 1 */ + CMD[5] = 0xFF; + + while (Write_Command_MMC(CMD) != 0) { + if (Timeout++ > 200) { + MMC_Disable(); + spi_unlock(); + return (2); /* Abort with command 2 (return 2) */ + } + } + + MMC_Disable(); + spi_unlock(); + + return 0; +} + +/* ############################################################################ + Sends a command to the MMC/SD-card + ######################################################################### */ +static unsigned char Write_Command_MMC (unsigned char *CMD) +{ + unsigned char a, tmp = 0xff; + unsigned short int Timeout = 0; + + MMC_Disable(); + spi_write(0xFF); + MMC_Enable(); + + for (a = 0; a < 0x06; a++) + spi_write(*CMD++); + + while (tmp == 0xff) { + tmp = spi_read(); + if (Timeout++ > 5000) + break; + } + + return (tmp); +} + +/* ############################################################################ + Routine to read the CID register from the MMC/SD-card (16 bytes) + ######################################################################### */ +void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, unsigned short + int Bytes) +{ + unsigned short int a; + + spi_lock(); + mmc_spi_cfg(); + MMC_Enable(); + + if (Write_Command_MMC(CMD) != 0) { + MMC_Disable(); + spi_unlock(); + return; + } + + while (spi_read() != 0xfe) {}; + for (a = 0; a < Bytes; a++) + *Buffer++ = spi_read(); + + /* Read the CRC-byte */ + spi_read(); /* CRC - byte is discarded */ + spi_read(); /* CRC - byte is discarded */ + /* set MMC_Chip_Select to high (MMC/SD-card Inaktiv) */ + MMC_Disable(); + spi_unlock(); + + return; +} + +/* ############################################################################ + Routine to read a block (512 bytes) from the MMC/SD-card + ######################################################################### */ +unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer) +{ + /* Command 16 to read aBlocks from the MMC/SD - caed */ + unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF}; + + /* The addres on the MMC/SD-card is in bytes, + addr is transformed from blocks to bytes and the result is + placed into the command */ + + addr = addr << 9; /* addr = addr * 512 */ + + CMD[1] = ((addr & 0xFF000000) >> 24); + CMD[2] = ((addr & 0x00FF0000) >> 16); + CMD[3] = ((addr & 0x0000FF00) >> 8 ); + + MMC_Read_Block(CMD, Buffer, 512); + + return (0); +} + +/* ############################################################################ + Routine to write a block (512 byte) to the MMC/SD-card + ######################################################################### */ +unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer) +{ + unsigned char tmp, a; + unsigned short int b; + /* Command 24 to write a block to the MMC/SD - card */ + unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF}; + + /* The addres on the MMC/SD-card is in bytes, + addr is transformed from blocks to bytes and the result is + placed into the command */ + + addr = addr << 9; /* addr = addr * 512 */ + + CMD[1] = ((addr & 0xFF000000) >> 24); + CMD[2] = ((addr & 0x00FF0000) >> 16); + CMD[3] = ((addr & 0x0000FF00) >> 8 ); + + spi_lock(); + mmc_spi_cfg(); + MMC_Enable(); + + /* Send command CMD24 to the MMC/SD-card (Write 1 Block/512 Bytes) */ + tmp = Write_Command_MMC(CMD); + if (tmp != 0) { + MMC_Disable(); + spi_unlock(); + return(tmp); + } + + /* Do a short delay and send a clock-pulse to the MMC/SD-card */ + for (a = 0; a < 100; a++) + spi_read(); + + /* Send a start byte to the MMC/SD-card */ + spi_write(0xFE); + + /* Write the block (512 bytes) to the MMC/SD-card */ + for (b = 0; b < 512; b++) + spi_write(*Buffer++); + + /* write the CRC-Byte */ + spi_write(0xFF); /* write a dummy CRC */ + spi_write(0xFF); /* CRC code is not used */ + + /* Wait for MMC/SD-card busy */ + while (spi_read() != 0xff) {}; + + /* set MMC_Chip_Select to high (MMC/SD-card inactive) */ + MMC_Disable(); + spi_unlock(); + return (0); +} + +/* ######################################################################### + Routine to read the CSD register from the MMC/SD-card (16 bytes) + ######################################################################### */ +unsigned char mmc_read_csd (unsigned char *Buffer) +{ + /* Command to read the CSD register */ + unsigned char CMD[] = {0x49, 0x00, 0x00, 0x00, 0x00, 0xFF}; + + MMC_Read_Block(CMD, Buffer, 16); + + return (0); +} diff --git a/cpu/arm720t/lpc2292/mmc_hw.h b/cpu/arm720t/lpc2292/mmc_hw.h new file mode 100644 index 00000000000..3687dbf6969 --- /dev/null +++ b/cpu/arm720t/lpc2292/mmc_hw.h @@ -0,0 +1,29 @@ +/* + This module implements a linux character device driver for the 24c256 chip. + Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#ifndef _MMC_HW_ +#define _MMC_HW_ + +unsigned char mmc_read_csd(unsigned char *Buffer); +unsigned char mmc_read_sector (unsigned long addr, + unsigned char *Buffer); +unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer); +int mmc_hw_init(void); + +#endif /* _MMC_HW_ */ diff --git a/cpu/arm720t/lpc2292/spi.c b/cpu/arm720t/lpc2292/spi.c new file mode 100644 index 00000000000..d296bdac686 --- /dev/null +++ b/cpu/arm720t/lpc2292/spi.c @@ -0,0 +1,40 @@ +/* + This module implements an interface to the SPI on the lpc22xx. + Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include +#include +#include +#include +#include + +unsigned long spi_flags; +unsigned char spi_idle = 0x00; + +int spi_init(void) +{ + unsigned long pinsel0_value; + + /* activate spi pins */ + pinsel0_value = GET32(PINSEL0); + pinsel0_value &= ~(0xFFl << 8); + pinsel0_value |= (0x55l << 8); + PUT32(PINSEL0, pinsel0_value); + + return 0; +} -- cgit v1.2.3 From 10603d76767426be803dadd4fb688b97eb69481c Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 21 May 2007 07:41:22 +0200 Subject: ppc4xx: Fix problem in 405EZ OCM initialization As spotted by Bruce Adler this patch fixes an initialization problem for the 405EZ OCM. Signed-off-by: Stefan Roese --- cpu/ppc4xx/start.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index a96083caa58..85660b40dcd 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -783,7 +783,7 @@ _start: mtdcr ocmdscr2, r3 /* Set Data Side */ mtdcr ocmiscr2, r3 /* Set Instruction Side */ addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */ - mtdcr ocmdsisdpc,r4 + mtdcr ocmdsisdpc,r3 isync #else /* CONFIG_405EZ */ -- cgit v1.2.3 From 6f3dfc139a838b0841c151efe00ad47db2366e79 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 22 May 2007 12:46:10 +0200 Subject: ppc4xx: Add 405 support to 4xx NAND driver ndfc.c This patch adds support for 405 PPC's to the 4xx NAND driver ndfc.c. This is in preparation for the new AMCC 405EZ. Signed-off-by: Stefan Roese --- cpu/ppc4xx/ndfc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c index b198ff46ceb..08dfc329529 100644 --- a/cpu/ppc4xx/ndfc.c +++ b/cpu/ppc4xx/ndfc.c @@ -33,12 +33,13 @@ #if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \ (defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX)) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EZ)) #include #include #include -#include +#include static u8 hwctl = 0; @@ -176,8 +177,7 @@ int board_nand_init(struct nand_chip *nand) /* * Setup EBC (CS0 only right now) */ - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, 0xb8400000); + mtebc(EBC0_CFG, 0xb8400000); mtebc(pb0cr, CFG_EBC_PB0CR); mtebc(pb0ap, CFG_EBC_PB0AP); -- cgit v1.2.3 From c99512d6bd3973f01ca2fc4896d829b46e68f150 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Sun, 27 May 2007 16:53:43 +0200 Subject: MPC5xxx: Change names of defines related to IPB and PCI clocks. Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining them does not cause PCI or IPB clocks to run at the specified speed. Instead, they configure divisors used to calculate said clocks. This patch renames the defines according to their real function. Signed-off-by: Grzegorz Bernacki Acked-by: Bartlomiej Sieka --- cpu/mpc5xxx/cpu_init.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c index 7e658218525..d7440308a45 100644 --- a/cpu/mpc5xxx/cpu_init.c +++ b/cpu/mpc5xxx/cpu_init.c @@ -156,21 +156,21 @@ void cpu_init_f (void) *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15); *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CFG_SDRAM_BASE | 0x1d; -# if defined(CFG_IPBSPEED_133) +# if defined(CFG_IPBCLK_EQUALS_XLBCLK) /* Motorola reports IPB should better run at 133 MHz. */ *(vu_long *)MPC5XXX_ADDECR |= 1; /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */ addecr = *(vu_long *)MPC5XXX_CDM_CFG; addecr &= ~0x103; -# if defined(CFG_PCISPEED_66) +# if defined(CFG_PCICLK_EQUALS_IPBCLK_DIV2) /* pci_clk_sel = 0x01 -> IPB_CLK/2 */ addecr |= 0x01; # else /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */ addecr |= 0x02; -# endif /* CFG_PCISPEED_66 */ +# endif /* CFG_PCICLK_EQUALS_IPBCLK_DIV2 */ *(vu_long *)MPC5XXX_CDM_CFG = addecr; -# endif /* CFG_IPBSPEED_133 */ +# endif /* CFG_IPBCLK_EQUALS_XLBCLK */ /* Configure the XLB Arbiter */ *(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff; *(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111; -- cgit v1.2.3 From c00125e07c1ebc125bab40e1e18bceed8be0c162 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Sun, 27 May 2007 16:58:45 +0200 Subject: MPC5XXX, Motion-PRO: Fix PHY initialization problem. After being reset in mpc5xxx_fec_init_phy(), PHY goes into FX mode, in which networking does not function. This commit switches PHY to TX mode by clearing the FX_SEL bit of Mode Control Register. It also reverses commit 008861a2f3ef2c062744d733787c7e530a1b8761, i.e., a temporary workaround. Signed-off-by: Grzegorz Bernacki Acked-by: Bartlomiej Sieka --- cpu/mpc5xxx/fec.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c index 0b8f24d18a7..62b5f4efdca 100644 --- a/cpu/mpc5xxx/fec.c +++ b/cpu/mpc5xxx/fec.c @@ -395,9 +395,7 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis) static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) { mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; -#ifndef CONFIG_MOTIONPRO const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */ -#endif /* !CONFIG_MOTIONPRO */ #if (DEBUG & 0x1) printf ("mpc5xxx_fec_init_phy... Begin\n"); @@ -437,7 +435,6 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) * PHY initialization for the Motion-PRO board, until a proper fix is found. */ -#ifndef CONFIG_MOTIONPRO if (fec->xcv_type != SEVENWIRE) { /* * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock @@ -560,7 +557,6 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) } } -#endif /* !CONFIG_MOTIONPRO */ #if (DEBUG & 0x2) if (fec->xcv_type != SEVENWIRE) -- cgit v1.2.3 From 7187db73491c8de0fb56efb5e5134ba5ec443089 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 1 Jun 2007 13:45:00 +0200 Subject: ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe) Add config option for 180 degree advance clock control as needed for the AMCC Luan eval board. Signed-off-by: Stefan Roese --- cpu/ppc4xx/44x_spd_ddr2.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 2ecd3e4b610..48b9ee2f7e0 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -465,7 +465,11 @@ long int initdram(int board_type) * Set the SDRAM Clock Timing Register *-----------------------------------------------------------------*/ mfsdram(SDRAM_CLKTR, val); +#ifdef CFG_44x_DDR2_CKTR_180 + mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_180_DEG_ADV); +#else mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG); +#endif /*------------------------------------------------------------------ * Program the BxCF registers. @@ -1117,7 +1121,8 @@ static void program_codt(unsigned long *dimm_populated, modt3 = 0x00000000; } if (total_rank == 4) { - codt |= CALC_ODT_R(0) | CALC_ODT_R(1) | CALC_ODT_R(2) | CALC_ODT_R(3); + codt |= CALC_ODT_R(0) | CALC_ODT_R(1) | + CALC_ODT_R(2) | CALC_ODT_R(3); modt0 = CALC_ODT_RW(2); modt1 = 0x00000000; modt2 = CALC_ODT_RW(0); -- cgit v1.2.3 From d2d432760d2199d0e8558fdd9d1789b8131abcf7 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 1 Jun 2007 15:09:50 +0200 Subject: ppc4xx: 44x DDR driver code cleanup and small fix for Bamboo Signed-off-by: Stefan Roese --- cpu/ppc4xx/44x_spd_ddr.c | 341 +++++++++++++++++++++++------------------------ 1 file changed, 166 insertions(+), 175 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index 10b4c189789..c500d3f2421 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -20,7 +20,7 @@ * Jun Gu, Artesyn Technology, jung@artesyncp.com * Support for AMCC 440 based on OpenBIOS draminit.c from IBM. * - * (C) Copyright 2005 + * (C) Copyright 2005-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this @@ -42,6 +42,11 @@ * MA 02111-1307 USA */ +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + #include #include #include @@ -246,25 +251,6 @@ #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ #endif -const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = { - {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xFFFFFFFF, 0xFFFFFFFF}, - {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0x00000000, 0x00000000}, - {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0x55555555, 0x55555555}, - {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0xAAAAAAAA, 0xAAAAAAAA}, - {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0x5A5A5A5A, 0x5A5A5A5A}, - {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0xA5A5A5A5, 0xA5A5A5A5}, - {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, - 0x55AA55AA, 0x55AA55AA}, - {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0xAA55AA55, 0xAA55AA55} -}; - /* bank_parms is used to sort the bank sizes by descending order */ struct bank_param { unsigned long cr; @@ -278,46 +264,37 @@ extern unsigned char cfg_simulate_spd_eeprom[128]; #endif void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value); -unsigned char spd_read(uchar chip, uint addr); - -void get_spd_info(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks); - -void check_mem_type -(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks); - -void check_volt_type -(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks); - -void program_cfg0(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks); - -void program_cfg1(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks); - -void program_rtr (unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks); - -void program_tr0 (unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks); - -void program_tr1 (void); - -void program_ecc (unsigned long num_bytes); +static unsigned char spd_read(uchar chip, uint addr); +static void get_spd_info(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void check_mem_type(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void check_volt_type(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void program_cfg0(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void program_cfg1(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void program_rtr(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void program_tr0(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void program_tr1(void); + +#ifdef CONFIG_DDR_ECC +static void program_ecc(unsigned long num_bytes); +#endif -unsigned -long program_bxcr(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks); +static unsigned long program_bxcr(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); /* * This function is reading data from the DIMM module EEPROM over the SPD bus @@ -328,7 +305,6 @@ long program_bxcr(unsigned long* dimm_populated, * BUG: Don't handle ECC memory * BUG: A few values in the TR register is currently hardcoded */ - long int spd_sdram(void) { unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; unsigned long dimm_populated[sizeof(iic0_dimm_addr)]; @@ -421,9 +397,8 @@ long int spd_sdram(void) { */ while (1) { mfsdram(mem_mcsts, mcsts); - if ((mcsts & SDRAM_MCSTS_MRSC) != 0) { + if ((mcsts & SDRAM_MCSTS_MRSC) != 0) break; - } } /* @@ -431,14 +406,17 @@ long int spd_sdram(void) { */ program_tr1(); +#ifdef CONFIG_DDR_ECC /* - * if ECC is enabled, initialize parity bits + * If ecc is enabled, initialize the parity bits. */ + program_ecc(total_size); +#endif return total_size; } -unsigned char spd_read(uchar chip, uint addr) +static unsigned char spd_read(uchar chip, uint addr) { unsigned char data[2]; @@ -460,9 +438,9 @@ unsigned char spd_read(uchar chip, uint addr) return 0; } -void get_spd_info(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks) +static void get_spd_info(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) { unsigned long dimm_num; unsigned long dimm_found; @@ -480,14 +458,10 @@ void get_spd_info(unsigned long* dimm_populated, if ((num_of_bytes != 0) && (total_size != 0)) { dimm_populated[dimm_num] = TRUE; dimm_found = TRUE; -#if 0 - printf("DIMM slot %lu: populated\n", dimm_num); -#endif + debug("DIMM slot %lu: populated\n", dimm_num); } else { dimm_populated[dimm_num] = FALSE; -#if 0 - printf("DIMM slot %lu: Not populated\n", dimm_num); -#endif + debug("DIMM slot %lu: Not populated\n", dimm_num); } } @@ -497,9 +471,9 @@ void get_spd_info(unsigned long* dimm_populated, } } -void check_mem_type(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks) +static void check_mem_type(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) { unsigned long dimm_num; unsigned char dimm_type; @@ -509,9 +483,7 @@ void check_mem_type(unsigned long* dimm_populated, dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2); switch (dimm_type) { case 7: -#if 0 - printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num); -#endif + debug("DIMM slot %lu: DDR SDRAM detected\n", dimm_num); break; default: printf("ERROR: Unsupported DIMM detected in slot %lu.\n", @@ -525,10 +497,9 @@ void check_mem_type(unsigned long* dimm_populated, } } - -void check_volt_type(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks) +static void check_volt_type(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) { unsigned long dimm_num; unsigned long voltage_type; @@ -541,18 +512,16 @@ void check_volt_type(unsigned long* dimm_populated, dimm_num); hang(); } else { -#if 0 - printf("DIMM %lu voltage level supported.\n", dimm_num); -#endif + debug("DIMM %lu voltage level supported.\n", dimm_num); } break; } } } -void program_cfg0(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks) +static void program_cfg0(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) { unsigned long dimm_num; unsigned long cfg0; @@ -640,9 +609,9 @@ void program_cfg0(unsigned long* dimm_populated, mtsdram(mem_cfg0, cfg0); } -void program_cfg1(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks) +static void program_cfg1(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) { unsigned long cfg1; mfsdram(mem_cfg1, cfg1); @@ -658,9 +627,9 @@ void program_cfg1(unsigned long* dimm_populated, mtsdram(mem_cfg1, cfg1); } -void program_rtr (unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks) +static void program_rtr(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) { unsigned long dimm_num; unsigned long bus_period_x_10; @@ -676,7 +645,6 @@ void program_rtr (unsigned long* dimm_populated, get_sys_info(&sys_info); bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { if (dimm_populated[dimm_num] == TRUE) { refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12); @@ -719,9 +687,9 @@ void program_rtr (unsigned long* dimm_populated, mtsdram(mem_rtr, sdram_rtr); } -void program_tr0 (unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks) +static void program_tr0(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) { unsigned long dimm_num; unsigned long tr0; @@ -1001,13 +969,73 @@ void program_tr0 (unsigned long* dimm_populated, break; } -#if 0 - printf("tr0: %x\n", tr0); -#endif + debug("tr0: %x\n", tr0); mtsdram(mem_tr0, tr0); } -void program_tr1 (void) +static int short_mem_test(void) +{ + unsigned long i, j; + unsigned long bxcr_num; + unsigned long *membase; + const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = { + {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF}, + {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000}, + {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555}, + {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA}, + {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A}, + {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5}, + {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA}, + {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}}; + + for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) { + mtdcr(memcfga, mem_b0cr + (bxcr_num << 2)); + if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { + /* Bank is enabled */ + membase = (unsigned long*) + (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK); + + /* + * Run the short memory test + */ + for (i = 0; i < NUMMEMTESTS; i++) { + for (j = 0; j < NUMMEMWORDS; j++) { + membase[j] = test[i][j]; + ppcDcbf((unsigned long)&(membase[j])); + } + + for (j = 0; j < NUMMEMWORDS; j++) { + if (membase[j] != test[i][j]) { + ppcDcbf((unsigned long)&(membase[j])); + return 0; + } + ppcDcbf((unsigned long)&(membase[j])); + } + + if (j < NUMMEMWORDS) + return 0; + } + + /* + * see if the rdclt value passed + */ + if (i < NUMMEMTESTS) + return 0; + } + } + + return 1; +} + +static void program_tr1(void) { unsigned long tr0; unsigned long tr1; @@ -1015,8 +1043,7 @@ void program_tr1 (void) unsigned long ecc_temp; unsigned long dlycal; unsigned long dly_val; - unsigned long i, j, k; - unsigned long bxcr_num; + unsigned long k; unsigned long max_pass_length; unsigned long current_pass_length; unsigned long current_fail_length; @@ -1029,7 +1056,6 @@ void program_tr1 (void) unsigned char window_found; unsigned char fail_found; unsigned char pass_found; - unsigned long * membase; PPC440_SYS_INFO sys_info; /* @@ -1079,55 +1105,16 @@ void program_tr1 (void) window_found = FALSE; fail_found = FALSE; pass_found = FALSE; -#ifdef DEBUG - printf("Starting memory test "); -#endif + debug("Starting memory test "); + for (k = 0; k < NUMHALFCYCLES; k++) { - for (rdclt = 0; rdclt < dly_val; rdclt++) { + for (rdclt = 0; rdclt < dly_val; rdclt++) { /* * Set the timing reg for the test. */ mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt))); - for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) { - mtdcr(memcfga, mem_b0cr + (bxcr_num<<2)); - if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { - /* Bank is enabled */ - membase = (unsigned long*) - (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK); - - /* - * Run the short memory test - */ - for (i = 0; i < NUMMEMTESTS; i++) { - for (j = 0; j < NUMMEMWORDS; j++) { - membase[j] = test[i][j]; - ppcDcbf((unsigned long)&(membase[j])); - } - - for (j = 0; j < NUMMEMWORDS; j++) { - if (membase[j] != test[i][j]) { - ppcDcbf((unsigned long)&(membase[j])); - break; - } - ppcDcbf((unsigned long)&(membase[j])); - } - - if (j < NUMMEMWORDS) { - break; - } - } - - /* - * see if the rdclt value passed - */ - if (i < NUMMEMTESTS) { - break; - } - } - } - - if (bxcr_num == MAXBXCR) { + if (short_mem_test()) { if (fail_found == TRUE) { pass_found = TRUE; if (current_pass_length == 0) { @@ -1157,9 +1144,8 @@ void program_tr1 (void) } } } -#ifdef DEBUG - printf("."); -#endif + debug("."); + if (window_found == TRUE) { break; } @@ -1167,9 +1153,7 @@ void program_tr1 (void) tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK; rdclt_offset += dly_val; } -#ifdef DEBUG - printf("\n"); -#endif + debug("\n"); /* * make sure we find the window @@ -1218,18 +1202,17 @@ void program_tr1 (void) } tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average); -#if 0 - printf("tr1: %x\n", tr1); -#endif + debug("tr1: %x\n", tr1); + /* * program SDRAM Timing Register 1 TR1 */ mtsdram(mem_tr1, tr1); } -unsigned long program_bxcr(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks) +static unsigned long program_bxcr(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) { unsigned long dimm_num; unsigned long bank_base_addr; @@ -1262,8 +1245,8 @@ unsigned long program_bxcr(unsigned long* dimm_populated, #ifdef CONFIG_BAMBOO /* * This next section is hardware dependent and must be programmed - * to match the hardware. For bammboo, the following holds... - * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 + * to match the hardware. For bamboo, the following holds... + * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 (soldered onboard) * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1 * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1 * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3 @@ -1273,10 +1256,12 @@ unsigned long program_bxcr(unsigned long* dimm_populated, ctrl_bank_num[1] = 1; ctrl_bank_num[2] = 3; #else + /* + * Ocotea, Ebony and the other IBM/AMCC eval boards have + * 2 DIMM slots with each max 2 banks + */ ctrl_bank_num[0] = 0; - ctrl_bank_num[1] = 1; - ctrl_bank_num[2] = 2; - ctrl_bank_num[3] = 3; + ctrl_bank_num[1] = 2; #endif /* @@ -1290,6 +1275,8 @@ unsigned long program_bxcr(unsigned long* dimm_populated, num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4); num_banks = spd_read(iic0_dimm_addr[dimm_num], 5); bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31); + debug("DIMM%d: row=%d col=%d banks=%d\n", dimm_num, + num_row_addr, num_col_addr, num_banks); /* * Set the SDRAM0_BxCR regs @@ -1354,9 +1341,12 @@ unsigned long program_bxcr(unsigned long* dimm_populated, cr |= SDRAM_BXCR_SDBE; for (i = 0; i < num_banks; i++) { - bank_parms[ctrl_bank_num[dimm_num]+i+dimm_num].bank_size_bytes = - (4 * 1024 * 1024) * bank_size_id; - bank_parms[ctrl_bank_num[dimm_num]+i+dimm_num].cr = cr; + bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes = + (4 << 20) * bank_size_id; + bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr; + debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n", + dimm_num, i, ctrl_bank_num[dimm_num]+i, + bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes); } } } @@ -1400,13 +1390,15 @@ unsigned long program_bxcr(unsigned long* dimm_populated, bank_parms[sorted_bank_num[bx_cr_num]].cr; mtdcr(memcfgd, temp); bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes; + debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp); } } return(bank_base_addr); } -void program_ecc (unsigned long num_bytes) +#ifdef CONFIG_DDR_ECC +static void program_ecc(unsigned long num_bytes) { unsigned long bank_base_addr; unsigned long current_address; @@ -1425,14 +1417,12 @@ void program_ecc (unsigned long num_bytes) bank_base_addr = CFG_SDRAM_BASE; if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) { - mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | - SDRAM_CFG0_MCHK_GEN); + mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_GEN); - if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) { + if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) address_increment = 4; - } else { + else address_increment = 8; - } current_address = (unsigned long)(bank_base_addr); end_address = (unsigned long)(bank_base_addr) + num_bytes; @@ -1446,4 +1436,5 @@ void program_ecc (unsigned long num_bytes) SDRAM_CFG0_MCHK_CHK); } } +#endif /* CONFIG_DDR_ECC */ #endif /* CONFIG_SPD_EEPROM */ -- cgit v1.2.3 From 91da09cfbce0c1de05d6d84aa8363d666fa7ea3c Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 1 Jun 2007 15:15:12 +0200 Subject: NAND: Add hardware ECC support to the PPC4xx NAND driver ndfc.c This patch adds hardware ECC support to the NDFC driver. It also changes the register access from using the "simple" in32/out32 functions to the in_be32/out_be32 functions, which make sure that the access is correctly synced. This is the only recommended access to SoC registers in the current Linux kernel. Signed-off-by: Stefan Roese --- cpu/ppc4xx/ndfc.c | 74 ++++++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 54 insertions(+), 20 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c index b198ff46ceb..09aac38f488 100644 --- a/cpu/ppc4xx/ndfc.c +++ b/cpu/ppc4xx/ndfc.c @@ -3,7 +3,7 @@ * Platform independend driver for NDFC (NanD Flash Controller) * integrated into EP440 cores * - * (C) Copyright 2006 + * (C) Copyright 2006-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * Based on original work by @@ -37,7 +37,9 @@ #include #include +#include #include +#include #include static u8 hwctl = 0; @@ -69,11 +71,11 @@ static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte) ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; if (hwctl & 0x1) - out8(base + NDFC_CMD, byte); + out_8((u8 *)(base + NDFC_CMD), byte); else if (hwctl & 0x2) - out8(base + NDFC_ALE, byte); + out_8((u8 *)(base + NDFC_ALE), byte); else - out8(base + NDFC_DATA, byte); + out_8((u8 *)(base + NDFC_DATA), byte); } static u_char ndfc_read_byte(struct mtd_info *mtdinfo) @@ -81,7 +83,7 @@ static u_char ndfc_read_byte(struct mtd_info *mtdinfo) struct nand_chip *this = mtdinfo->priv; ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; - return (in8(base + NDFC_DATA)); + return (in_8((u8 *)(base + NDFC_DATA))); } static int ndfc_dev_ready(struct mtd_info *mtdinfo) @@ -89,17 +91,41 @@ static int ndfc_dev_ready(struct mtd_info *mtdinfo) struct nand_chip *this = mtdinfo->priv; ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; - while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY)) + while (!(in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY)) ; return 1; } -#ifndef CONFIG_NAND_SPL -/* - * Don't use these speedup functions in NAND boot image, since the image - * has to fit into 4kByte. - */ +static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode) +{ + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; + u32 ccr; + + ccr = in_be32((u32 *)(base + NDFC_CCR)); + ccr |= NDFC_CCR_RESET_ECC; + out_be32((u32 *)(base + NDFC_CCR), ccr); +} + +static int ndfc_calculate_ecc(struct mtd_info *mtdinfo, + const u_char *dat, u_char *ecc_code) +{ + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; + u32 ecc; + u8 *p = (u8 *)&ecc; + + ecc = in_be32((u32 *)(base + NDFC_ECC)); + + /* The NDFC uses Smart Media (SMC) bytes order + */ + ecc_code[0] = p[2]; + ecc_code[1] = p[1]; + ecc_code[2] = p[3]; + + return 0; +} /* * Speedups for buffer read/write/verify @@ -115,9 +141,14 @@ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) uint32_t *p = (uint32_t *) buf; for (;len > 0; len -= 4) - *p++ = in32(base + NDFC_DATA); + *p++ = in_be32((u32 *)(base + NDFC_DATA)); } +#ifndef CONFIG_NAND_SPL +/* + * Don't use these speedup functions in NAND boot image, since the image + * has to fit into 4kByte. + */ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) { struct nand_chip *this = mtdinfo->priv; @@ -125,7 +156,7 @@ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len uint32_t *p = (uint32_t *) buf; for (; len > 0; len -= 4) - out32(base + NDFC_DATA, *p++); + out_be32((u32 *)(base + NDFC_DATA), *p++); } static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) @@ -135,7 +166,7 @@ static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len uint32_t *p = (uint32_t *) buf; for (; len > 0; len -= 4) - if (*p++ != in32(base + NDFC_DATA)) + if (*p++ != in_be32((u32 *)(base + NDFC_DATA))) return -1; return 0; @@ -152,8 +183,8 @@ void board_nand_select_device(struct nand_chip *nand, int chip) ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc; /* Set NandFlash Core Configuration Register */ - /* 1col x 2 rows */ - out32(base + NDFC_CCR, 0x00000000 | (cs << 24)); + /* 1 col x 2 rows */ + out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24)); } int board_nand_init(struct nand_chip *nand) @@ -161,16 +192,19 @@ int board_nand_init(struct nand_chip *nand) int cs = (ulong)nand->IO_ADDR_W & 0x00000003; ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc; - nand->eccmode = NAND_ECC_SOFT; - nand->hwcontrol = ndfc_hwcontrol; nand->read_byte = ndfc_read_byte; + nand->read_buf = ndfc_read_buf; nand->write_byte = ndfc_write_byte; nand->dev_ready = ndfc_dev_ready; + nand->eccmode = NAND_ECC_HW3_256; + nand->enable_hwecc = ndfc_enable_hwecc; + nand->calculate_ecc = ndfc_calculate_ecc; + nand->correct_data = nand_correct_data; + #ifndef CONFIG_NAND_SPL nand->write_buf = ndfc_write_buf; - nand->read_buf = ndfc_read_buf; nand->verify_buf = ndfc_verify_buf; #else /* @@ -187,7 +221,7 @@ int board_nand_init(struct nand_chip *nand) * Select required NAND chip in NDFC */ board_nand_select_device(nand, cs); - out32(base + NDFC_BCFG0 + (cs << 2), 0x80002222); + out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), 0x80002222); return 0; } -- cgit v1.2.3 From cf959c7d6687567c308e366e9581e1a5aff5cc5b Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 1 Jun 2007 15:27:11 +0200 Subject: ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval board This patch adds NAND booting support for the AMCC Bamboo eval board. Since the NAND-SPL boot image is limited to 4kbytes, this version only supports the onboard 64MBytes of DDR. The DIMM modules can't be supported, since the setup code for I2C DIMM autodetection and configuration is too big for this NAND bootloader. Signed-off-by: Stefan Roese --- cpu/ppc4xx/start.S | 221 +++++++++++++++++++++++++++++++---------------------- 1 file changed, 129 insertions(+), 92 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 3b1586c0ae3..fe14ecd7bfe 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -110,6 +110,13 @@ # endif #endif /* CFG_INIT_DCACHE_CS */ +#define function_prolog(func_name) .text; \ + .align 2; \ + .globl func_name; \ + func_name: +#define function_epilog(func_name) .type func_name,@function; \ + .size func_name,.-func_name + /* We don't want the MMU yet. */ #undef MSR_KERNEL @@ -388,8 +395,9 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ 2: #if defined(CONFIG_NAND_SPL) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* - * Enable internal SRAM + * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM) */ lis r2,0x7fff ori r2,r2,0xffff @@ -399,6 +407,45 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ mfdcr r1,isram0_pmeg and r1,r1,r2 /* Disable pwr mgmt */ mtdcr isram0_pmeg,r1 +#endif +#if defined(CONFIG_440EP) + /* + * On 440EP with no internal SRAM, we setup SDRAM very early + * and copy the NAND_SPL to SDRAM and jump to it + */ + /* Clear Dcache to use as RAM */ + addis r3,r0,CFG_INIT_RAM_ADDR@h + ori r3,r3,CFG_INIT_RAM_ADDR@l + addis r4,r0,CFG_INIT_RAM_END@h + ori r4,r4,CFG_INIT_RAM_END@l + rlwinm. r5,r4,0,27,31 + rlwinm r5,r4,27,5,31 + beq ..d_ran3 + addi r5,r5,0x0001 +..d_ran3: + mtctr r5 +..d_ag3: + dcbz r0,r3 + addi r3,r3,32 + bdnz ..d_ag3 + /*----------------------------------------------------------------*/ + /* Setup the stack in internal SRAM */ + /*----------------------------------------------------------------*/ + lis r1,CFG_INIT_RAM_ADDR@h + ori r1,r1,CFG_INIT_SP_OFFSET@l + li r0,0 + stwu r0,-4(r1) + stwu r0,-4(r1) /* Terminate call chain */ + + stwu r1,-8(r1) /* Save back chain and move SP */ + lis r0,RESET_VECTOR@h /* Address of reset vector */ + ori r0,r0, RESET_VECTOR@l + stwu r1,-8(r1) /* Save back chain and move SP */ + stw r0,+12(r1) /* Save return addr (underflow vect) */ + sync + bl early_sdram_init + sync +#endif /* CONFIG_440EP */ /* * Copy SPL from cache into internal SRAM @@ -429,7 +476,7 @@ spl_loop: start_ram: sync isync -#endif +#endif /* CONFIG_NAND_SPL */ bl 3f b _start @@ -1137,7 +1184,6 @@ crit_return: lwz r1,GPR1(r1) SYNC rfci -#endif /* CONFIG_NAND_SPL */ /* Cache functions. */ @@ -1254,24 +1300,6 @@ wr_tcr: mtspr tcr, r3 blr -/*------------------------------------------------------------------------------- */ -/* Function: in8 */ -/* Description: Input 8 bits */ -/*------------------------------------------------------------------------------- */ - .globl in8 -in8: - lbz r3,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out8 */ -/* Description: Output 8 bits */ -/*------------------------------------------------------------------------------- */ - .globl out8 -out8: - stb r4,0x0000(r3) - blr - /*------------------------------------------------------------------------------- */ /* Function: out16 */ /* Description: Output 16 bits */ @@ -1290,15 +1318,6 @@ out16r: sthbrx r4,r0,r3 blr -/*------------------------------------------------------------------------------- */ -/* Function: out32 */ -/* Description: Output 32 bits */ -/*------------------------------------------------------------------------------- */ - .globl out32 -out32: - stw r4,0x0000(r3) - blr - /*------------------------------------------------------------------------------- */ /* Function: out32r */ /* Description: Byte reverse and output 32 bits */ @@ -1326,15 +1345,6 @@ in16r: lhbrx r3,r0,r3 blr -/*------------------------------------------------------------------------------- */ -/* Function: in32 */ -/* Description: Input 32 bits */ -/*------------------------------------------------------------------------------- */ - .globl in32 -in32: - lwz 3,0x0000(3) - blr - /*------------------------------------------------------------------------------- */ /* Function: in32r */ /* Description: Input 32 bits and byte reverse */ @@ -1377,9 +1387,6 @@ ppcSync: sync blr -/*------------------------------------------------------------------------------*/ - -#ifndef CONFIG_NAND_SPL /* * void relocate_code (addr_sp, gd, addr_moni) * @@ -1644,8 +1651,88 @@ trap_reloc: stw r0, 4(r7) blr + +#if defined(CONFIG_440) +/*----------------------------------------------------------------------------+ +| dcbz_area. ++----------------------------------------------------------------------------*/ + function_prolog(dcbz_area) + rlwinm. r5,r4,0,27,31 + rlwinm r5,r4,27,5,31 + beq ..d_ra2 + addi r5,r5,0x0001 +..d_ra2:mtctr r5 +..d_ag2:dcbz r0,r3 + addi r3,r3,32 + bdnz ..d_ag2 + sync + blr + function_epilog(dcbz_area) + +/*----------------------------------------------------------------------------+ +| dflush. Assume 32K at vector address is cachable. ++----------------------------------------------------------------------------*/ + function_prolog(dflush) + mfmsr r9 + rlwinm r8,r9,0,15,13 + rlwinm r8,r8,0,17,15 + mtmsr r8 + addi r3,r0,0x0000 + mtspr dvlim,r3 + mfspr r3,ivpr + addi r4,r0,1024 + mtctr r4 +..dflush_loop: + lwz r6,0x0(r3) + addi r3,r3,32 + bdnz ..dflush_loop + addi r3,r3,-32 + mtctr r4 +..ag: dcbf r0,r3 + addi r3,r3,-32 + bdnz ..ag + sync + mtmsr r9 + blr + function_epilog(dflush) +#endif /* CONFIG_440 */ #endif /* CONFIG_NAND_SPL */ +/*------------------------------------------------------------------------------- */ +/* Function: in8 */ +/* Description: Input 8 bits */ +/*------------------------------------------------------------------------------- */ + .globl in8 +in8: + lbz r3,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out8 */ +/* Description: Output 8 bits */ +/*------------------------------------------------------------------------------- */ + .globl out8 +out8: + stb r4,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out32 */ +/* Description: Output 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl out32 +out32: + stw r4,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in32 */ +/* Description: Input 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl in32 +in32: + lwz 3,0x0000(3) + blr /**************************************************************************/ /* PPC405EP specific stuff */ @@ -1892,13 +1979,6 @@ pll_wait: #endif /* CONFIG_405EP */ #if defined(CONFIG_440) -#define function_prolog(func_name) .text; \ - .align 2; \ - .globl func_name; \ - func_name: -#define function_epilog(func_name) .type func_name,@function; \ - .size func_name,.-func_name - /*----------------------------------------------------------------------------+ | mttlb3. +----------------------------------------------------------------------------*/ @@ -1946,47 +2026,4 @@ pll_wait: TLBRE(3,3,0) blr function_epilog(mftlb1) - -/*----------------------------------------------------------------------------+ -| dcbz_area. -+----------------------------------------------------------------------------*/ - function_prolog(dcbz_area) - rlwinm. r5,r4,0,27,31 - rlwinm r5,r4,27,5,31 - beq ..d_ra2 - addi r5,r5,0x0001 -..d_ra2:mtctr r5 -..d_ag2:dcbz r0,r3 - addi r3,r3,32 - bdnz ..d_ag2 - sync - blr - function_epilog(dcbz_area) - -/*----------------------------------------------------------------------------+ -| dflush. Assume 32K at vector address is cachable. -+----------------------------------------------------------------------------*/ - function_prolog(dflush) - mfmsr r9 - rlwinm r8,r9,0,15,13 - rlwinm r8,r8,0,17,15 - mtmsr r8 - addi r3,r0,0x0000 - mtspr dvlim,r3 - mfspr r3,ivpr - addi r4,r0,1024 - mtctr r4 -..dflush_loop: - lwz r6,0x0(r3) - addi r3,r3,32 - bdnz ..dflush_loop - addi r3,r3,-32 - mtctr r4 -..ag: dcbf r0,r3 - addi r3,r3,-32 - bdnz ..ag - sync - mtmsr r9 - blr - function_epilog(dflush) #endif /* CONFIG_440 */ -- cgit v1.2.3 From e3cbe1f93c5722f8ebbad468e30c069a2b511097 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Monin?= Date: Mon, 4 Jun 2007 08:36:05 +0200 Subject: [PATCH] Fix ppc4xx bootstrap letter displayed on startup The attached patch is mainly cosmetic, allowing u-boot to display the correct bootstrap option letter according to the datasheets. The original patch was extended with 405EZ support by Stefan Roese. Signed-off-by: Benoit Monin Signed-off-by: Stefan Roese --- cpu/ppc4xx/cpu.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 8e6bc84db03..c07bc0c325e 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -139,6 +139,7 @@ static char *bootstrap_str[] = { "Reserved", "I2C (Addr 0x50)", }; +static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' }; #endif #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) @@ -149,6 +150,7 @@ static char *bootstrap_str[] = { "I2C (Addr 0x54)", "I2C (Addr 0x50)", }; +static char bootstrap_char[] = { 'A', 'B', 'C', 'D'}; #endif #if defined(CONFIG_440EP) || defined(CONFIG_440GR) @@ -163,6 +165,7 @@ static char *bootstrap_str[] = { "PCI", "I2C (Addr 0x52)", }; +static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; #endif #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) @@ -177,6 +180,7 @@ static char *bootstrap_str[] = { "PCI", "I2C (Addr 0x52)", }; +static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; #endif #if defined(CONFIG_405EZ) @@ -199,6 +203,8 @@ static char *bootstrap_str[] = { "SPI (slow)", "I2C (Addr 0x50)", }; +static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \ + 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' }; #endif #if defined(SDR0_PINSTP_SHIFT) @@ -427,7 +433,7 @@ int checkcpu (void) printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis"); #endif /* I2C_BOOTROM */ #if defined(SDR0_PINSTP_SHIFT) - printf (" Bootstrap Option %c - ", (char)bootstrap_option() + 'A'); + printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]); printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]); #endif /* SDR0_PINSTP_SHIFT */ -- cgit v1.2.3 From 32922cdc470fdfd39bea0c1c4f582d3fb340421e Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Tue, 5 Jun 2007 12:30:52 -0500 Subject: mpc8641 image size cleanup e600 does not have a bootpg restriction. Move the version string to beginning of image at fff00000. Resetvec.S is not needed. Update flash copy instructions. Add tftpflash env variable Signed-off-by: Ed Swarthout Signed-off-by: Jon Loeliger --- cpu/mpc86xx/resetvec.S | 2 -- 1 file changed, 2 deletions(-) delete mode 100644 cpu/mpc86xx/resetvec.S (limited to 'cpu') diff --git a/cpu/mpc86xx/resetvec.S b/cpu/mpc86xx/resetvec.S deleted file mode 100644 index 9a552f6624e..00000000000 --- a/cpu/mpc86xx/resetvec.S +++ /dev/null @@ -1,2 +0,0 @@ - .section .resetvec,"ax" - b _start -- cgit v1.2.3 From c440bfe6d6d92d66478a7e84402b31f48413617b Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 6 Jun 2007 11:42:13 +0200 Subject: ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval board This patch adds NAND booting support for the AMCC Acadia eval board. Please make sure to configure jumper J7 to position 2-3 when booting from NOR, and to position 1-2 when booting for NAND. I also added a board command to configure the I2C bootstrap EEPROM values. Right now only 267MHz is support for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 267 nor ;to configure the board for 267MHz NOR booting => bootstrap 267 nand ;to configure the board for 267MHz NNAND booting Signed-off-by: Stefan Roese --- cpu/ppc4xx/start.S | 72 +++++++++++++++++++++++++++++++++++++++++------------- 1 file changed, 55 insertions(+), 17 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 78de30031d7..78d0042cc76 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -155,7 +155,9 @@ * NAND U-Boot image is started from offset 0 */ .text +#if defined(CONFIG_440) bl reconfig_tlb0 +#endif GET_GOT bl cpu_init_f /* run low-level CPU init code (from Flash) */ bl board_init_f @@ -857,6 +859,38 @@ _start: #endif /* CONFIG_405EZ */ #endif +#ifdef CONFIG_NAND_SPL + /* + * Copy SPL from cache into internal SRAM + */ + li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1 + mtctr r4 + lis r2,CFG_NAND_BOOT_SPL_SRC@h + ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l + lis r3,CFG_NAND_BOOT_SPL_DST@h + ori r3,r3,CFG_NAND_BOOT_SPL_DST@l +spl_loop: + lwzu r4,4(r2) + stwu r4,4(r3) + bdnz spl_loop + + /* + * Jump to code in RAM + */ + bl 00f +00: mflr r10 + lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h + ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l + sub r10,r10,r3 + addi r10,r10,28 + mtlr r10 + blr + +start_ram: + sync + isync +#endif /* CONFIG_NAND_SPL */ + /*----------------------------------------------------------------------- */ /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ /*----------------------------------------------------------------------- */ @@ -967,12 +1001,16 @@ _start: stw r0, +12(r1) /* Save return addr (underflow vect) */ #endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */ +#ifdef CONFIG_NAND_SPL + bl nand_boot /* will not return */ +#else GET_GOT /* initialize GOT access */ bl cpu_init_f /* run low-level CPU init code (from Flash) */ /* NEVER RETURNS! */ bl board_init_f /* run first part of init code (from Flash) */ +#endif /* CONFIG_NAND_SPL */ #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */ /*----------------------------------------------------------------------- */ @@ -1187,23 +1225,6 @@ crit_return: /* Cache functions. */ -invalidate_icache: - iccci r0,r0 /* for 405, iccci invalidates the */ - blr /* entire I cache */ - -invalidate_dcache: - addi r6,0,0x0000 /* clear GPR 6 */ - /* Do loop for # of dcache congruence classes. */ - lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */ - ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l - /* NOTE: dccci invalidates both */ - mtctr r7 /* ways in the D cache */ -..dcloop: - dccci 0,r6 /* invalidate line */ - addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */ - bdnz ..dcloop - blr - flush_dcache: addis r9,r0,0x0002 /* set mask for EE and CE msr bits */ ori r9,r9,0x8000 @@ -1734,6 +1755,23 @@ in32: lwz 3,0x0000(3) blr +invalidate_icache: + iccci r0,r0 /* for 405, iccci invalidates the */ + blr /* entire I cache */ + +invalidate_dcache: + addi r6,0,0x0000 /* clear GPR 6 */ + /* Do loop for # of dcache congruence classes. */ + lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */ + ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l + /* NOTE: dccci invalidates both */ + mtctr r7 /* ways in the D cache */ +..dcloop: + dccci 0,r6 /* invalidate line */ + addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */ + bdnz ..dcloop + blr + /**************************************************************************/ /* PPC405EP specific stuff */ /**************************************************************************/ -- cgit v1.2.3 From 9045f33c023f698660a2e45d1b2194c0711abebc Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 8 Jun 2007 10:24:58 +0200 Subject: Fix config problems on SC3 board; make ide_reset_timeout work. --- cpu/ppc4xx/405gp_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index 7134355635e..8bf03e1b2f1 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -380,7 +380,7 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); } -#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SOLIDCARD3)) +#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3)) /* *As is these functs get called out of flash Not a horrible -- cgit v1.2.3