From 7467599c896a57d5cd33aca8234442141c5e9f70 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Thu, 10 Sep 2009 15:27:57 -0400 Subject: OMAP3 Move cache routine to cache.S v7_flush_dcache_all, because it depends on omap ROM code is not generic. Rename the function to 'invalidate_dcache' and move it to the omap cpu directory. Collect the other omap cache routines l2_cache_enable and l2_cache_disable with invalide_dcache into cache.S. This means removing the old cache.c file that contained l2_cache_enable and l2_cache_disable. The conversion from cache.c to cache.S was done most through disassembling the uboot binary. The only significant change was to change the comparision for the return of get_cpu_rev from cmp r0, #0 beq earlier_than_label Which was lost information to cmp r0, #CPU_3XX_ES20 blt earlier_than_label The paths through the enable routine were verified by adding an infinite loop and seeing the hang. Then removing the infinite loop and seeing it continue. The disable routine is similar enough that it was not tested with this method. Run tested by cold booting from nand on beagle and zoom1. Compile tested on MAKEALL arm. Signed-off-by: Tom Rix --- cpu/arm_cortexa8/cpu.c | 2 +- cpu/arm_cortexa8/omap3/Makefile | 2 +- cpu/arm_cortexa8/omap3/board.c | 2 +- cpu/arm_cortexa8/omap3/cache.S | 191 ++++++++++++++++++++++++++++++++++++++++ cpu/arm_cortexa8/omap3/cache.c | 95 -------------------- cpu/arm_cortexa8/start.S | 85 ------------------ 6 files changed, 194 insertions(+), 183 deletions(-) create mode 100644 cpu/arm_cortexa8/omap3/cache.S delete mode 100644 cpu/arm_cortexa8/omap3/cache.c (limited to 'cpu') diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index 5a5981e4054..a01e0d605ff 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -64,7 +64,7 @@ int cleanup_before_linux(void) /* turn off L2 cache */ l2_cache_disable(); /* invalidate L2 cache also */ - v7_flush_dcache_all(get_device_type()); + invalidate_dcache(get_device_type()); #endif i = 0; /* mem barrier to sync up things */ diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile index eef165c3341..136b163ad75 100644 --- a/cpu/arm_cortexa8/omap3/Makefile +++ b/cpu/arm_cortexa8/omap3/Makefile @@ -26,10 +26,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a SOBJS := lowlevel_init.o +SOBJS += cache.o SOBJS += reset.o COBJS += board.o -COBJS += cache.o COBJS += clock.o COBJS += gpio.o COBJS += mem.o diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c index b8bd0524af9..dd2c94073b3 100644 --- a/cpu/arm_cortexa8/omap3/board.c +++ b/cpu/arm_cortexa8/omap3/board.c @@ -201,7 +201,7 @@ void s_init(void) * Right now flushing at low MPU speed. * Need to move after clock init */ - v7_flush_dcache_all(get_device_type()); + invalidate_dcache(get_device_type()); #ifndef CONFIG_ICACHE_OFF icache_enable(); #endif diff --git a/cpu/arm_cortexa8/omap3/cache.S b/cpu/arm_cortexa8/omap3/cache.S new file mode 100644 index 00000000000..0f63815359e --- /dev/null +++ b/cpu/arm_cortexa8/omap3/cache.S @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This file is based on and replaces the existing cache.c file + * The copyrights for the cache.c file are: + * + * (C) Copyright 2008 Texas Insturments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * omap3 cache code + */ + +.align 5 +.global invalidate_dcache +.global l2_cache_enable +.global l2_cache_disable + +/* + * invalidate_dcache() + * + * Invalidate the whole D-cache. + * + * Corrupted registers: r0-r5, r7, r9-r11 + * + * - mm - mm_struct describing address space + */ +invalidate_dcache: + stmfd r13!, {r0 - r5, r7, r9 - r12, r14} + + mov r7, r0 @ take a backup of device type + cmp r0, #0x3 @ check if the device type is + @ GP + moveq r12, #0x1 @ set up to invalide L2 +smi: .word 0x01600070 @ Call SMI monitor (smieq) + cmp r7, #0x3 @ compare again in case its + @ lost + beq finished_inval @ if GP device, inval done + @ above + + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished_inval @ if loc is 0, then no need to + @ clean + mov r10, #0 @ start clean at cache level 0 +inval_loop1: + add r2, r10, r10, lsr #1 @ work out 3x current cache + @ level + mov r1, r0, lsr r2 @ extract cache type bits from + @ clidr + and r1, r1, #7 @ mask of the bits for current + @ cache only + cmp r1, #2 @ see what cache we have at + @ this level + blt skip_inval @ skip if no cache, or just + @ i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr + mov r2, #0 @ operand for mcr SBZ + mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to + @ sych the new cssr&csidr, + @ with armv7 this is 'isb', + @ but we compile with armv5 + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the + @ cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the + @ way size + clz r5, r4 @ find bit position of way + @ size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the + @ index size +inval_loop2: + mov r9, r4 @ create working copy of max + @ way size +inval_loop3: + orr r11, r10, r9, lsl r5 @ factor way and cache number + @ into r11 + orr r11, r11, r7, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way + subs r9, r9, #1 @ decrement the way + bge inval_loop3 + subs r7, r7, #1 @ decrement the index + bge inval_loop2 +skip_inval: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt inval_loop1 +finished_inval: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr + mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, + @ with armv7 this is 'isb', + @ but we compile with armv5 + + ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} + + +l2_cache_enable: + push {r0, r1, r2, lr} + @ ES2 onwards we can disable/enable L2 ourselves + bl get_cpu_rev + cmp r0, #CPU_3XX_ES20 + blt l2_cache_disable_EARLIER_THAN_ES2 + mrc 15, 0, r3, cr1, cr0, 1 + orr r3, r3, #2 + mcr 15, 0, r3, cr1, cr0, 1 + b l2_cache_enable_END +l2_cache_enable_EARLIER_THAN_ES2: + @ Save r0, r12 and restore them after usage + mov r3, ip + str r3, [sp, #4] + mov r3, r0 + @ + @ GP Device ROM code API usage here + @ r12 = AUXCR Write function and r0 value + @ + mov ip, #3 + mrc 15, 0, r0, cr1, cr0, 1 + orr r0, r0, #2 + @ SMI instruction to call ROM Code API + .word 0xe1600070 + mov r0, r3 + mov ip, r3 + str r3, [sp, #4] +l2_cache_enable_END: + pop {r1, r2, r3, pc} + + +l2_cache_disable: + push {r0, r1, r2, lr} + @ ES2 onwards we can disable/enable L2 ourselves + bl get_cpu_rev + cmp r0, #CPU_3XX_ES20 + blt l2_cache_disable_EARLIER_THAN_ES2 + mrc 15, 0, r3, cr1, cr0, 1 + bic r3, r3, #2 + mcr 15, 0, r3, cr1, cr0, 1 + b l2_cache_disable_END +l2_cache_disable_EARLIER_THAN_ES2: + @ Save r0, r12 and restore them after usage + mov r3, ip + str r3, [sp, #4] + mov r3, r0 + @ + @ GP Device ROM code API usage here + @ r12 = AUXCR Write function and r0 value + @ + mov ip, #3 + mrc 15, 0, r0, cr1, cr0, 1 + bic r0, r0, #2 + @ SMI instruction to call ROM Code API + .word 0xe1600070 + mov r0, r3 + mov ip, r3 + str r3, [sp, #4] +l2_cache_disable_END: + pop {r1, r2, r3, pc} diff --git a/cpu/arm_cortexa8/omap3/cache.c b/cpu/arm_cortexa8/omap3/cache.c deleted file mode 100644 index 0d5b444be1d..00000000000 --- a/cpu/arm_cortexa8/omap3/cache.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * (C) Copyright 2008 Texas Insturments - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * omap3 L2 cache code - */ - -#include -#include -#include - -void l2_cache_enable(void) -{ - unsigned long i; - volatile unsigned int j; - - /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() >= CPU_3XX_ES20) { - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); - __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); - } else { - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - __asm__ __volatile__("orr r0, r0, #0x2"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); - } - -} - -void l2_cache_disable(void) -{ - unsigned long i; - volatile unsigned int j; - - /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() >= CPU_3XX_ES20) { - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); - __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); - } else { - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - __asm__ __volatile__("bic r0, r0, #0x2"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); - } -} diff --git a/cpu/arm_cortexa8/start.S b/cpu/arm_cortexa8/start.S index 6bd65521bdf..14a9bd3b039 100644 --- a/cpu/arm_cortexa8/start.S +++ b/cpu/arm_cortexa8/start.S @@ -415,88 +415,3 @@ fiq: #endif -/* - * v7_flush_dcache_all() - * - * Flush the whole D-cache. - * - * Corrupted registers: r0-r5, r7, r9-r11 - * - * - mm - mm_struct describing address space - */ - .align 5 -.global v7_flush_dcache_all -v7_flush_dcache_all: - stmfd r13!, {r0 - r5, r7, r9 - r12, r14} - - mov r7, r0 @ take a backup of device type - cmp r0, #0x3 @ check if the device type is - @ GP - moveq r12, #0x1 @ set up to invalide L2 -smi: .word 0x01600070 @ Call SMI monitor (smieq) - cmp r7, #0x3 @ compare again in case its - @ lost - beq finished_inval @ if GP device, inval done - @ above - - mrc p15, 1, r0, c0, c0, 1 @ read clidr - ands r3, r0, #0x7000000 @ extract loc from clidr - mov r3, r3, lsr #23 @ left align loc bit field - beq finished_inval @ if loc is 0, then no need to - @ clean - mov r10, #0 @ start clean at cache level 0 -inval_loop1: - add r2, r10, r10, lsr #1 @ work out 3x current cache - @ level - mov r1, r0, lsr r2 @ extract cache type bits from - @ clidr - and r1, r1, #7 @ mask of the bits for current - @ cache only - cmp r1, #2 @ see what cache we have at - @ this level - blt skip_inval @ skip if no cache, or just - @ i-cache - mcr p15, 2, r10, c0, c0, 0 @ select current cache level - @ in cssr - mov r2, #0 @ operand for mcr SBZ - mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to - @ sych the new cssr&csidr, - @ with armv7 this is 'isb', - @ but we compile with armv5 - mrc p15, 1, r1, c0, c0, 0 @ read the new csidr - and r2, r1, #7 @ extract the length of the - @ cache lines - add r2, r2, #4 @ add 4 (line length offset) - ldr r4, =0x3ff - ands r4, r4, r1, lsr #3 @ find maximum number on the - @ way size - clz r5, r4 @ find bit position of way - @ size increment - ldr r7, =0x7fff - ands r7, r7, r1, lsr #13 @ extract max number of the - @ index size -inval_loop2: - mov r9, r4 @ create working copy of max - @ way size -inval_loop3: - orr r11, r10, r9, lsl r5 @ factor way and cache number - @ into r11 - orr r11, r11, r7, lsl r2 @ factor index number into r11 - mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way - subs r9, r9, #1 @ decrement the way - bge inval_loop3 - subs r7, r7, #1 @ decrement the index - bge inval_loop2 -skip_inval: - add r10, r10, #2 @ increment cache number - cmp r3, r10 - bgt inval_loop1 -finished_inval: - mov r10, #0 @ swith back to cache level 0 - mcr p15, 2, r10, c0, c0, 0 @ select current cache level - @ in cssr - mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, - @ with armv7 this is 'isb', - @ but we compile with armv5 - - ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} -- cgit v1.2.3 From e08dbb4f203b7fd4311378c894c9924941666002 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Tue, 8 Sep 2009 11:37:39 -0400 Subject: TI DaVinci: DM646x: Initial Support for DM646x SOC DM646x is an SOC from TI which has both an ARM and a DSP. There are multiple variants of the SOC mainly dealing with different core speeds. This patch adds the initial framework for the DM646x SOC. Signed-off-by: Sandeep Paulraj --- cpu/arm926ejs/davinci/Makefile | 1 + cpu/arm926ejs/davinci/dm646x.c | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) create mode 100644 cpu/arm926ejs/davinci/dm646x.c (limited to 'cpu') diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile index 7501a852485..d7e9e2ca047 100644 --- a/cpu/arm926ejs/davinci/Makefile +++ b/cpu/arm926ejs/davinci/Makefile @@ -31,6 +31,7 @@ COBJS-y += cpu.o timer.o psc.o COBJS-$(CONFIG_SOC_DM355) += dm355.o COBJS-$(CONFIG_SOC_DM365) += dm365.o COBJS-$(CONFIG_SOC_DM644X) += dm644x.o +COBJS-$(CONFIG_SOC_DM646X) += dm646x.o COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o SOBJS = reset.o diff --git a/cpu/arm926ejs/davinci/dm646x.c b/cpu/arm926ejs/davinci/dm646x.c new file mode 100644 index 00000000000..329825f453b --- /dev/null +++ b/cpu/arm926ejs/davinci/dm646x.c @@ -0,0 +1,41 @@ +/* + * SoC-specific code for TMS320DM646x chips + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include + +void davinci_enable_uart0(void) +{ + lpsc_on(DAVINCI_DM646X_LPSC_UART0); +} + +#ifdef CONFIG_DRIVER_TI_EMAC +void davinci_enable_emac(void) +{ + lpsc_on(DAVINCI_DM646X_LPSC_EMAC); +} +#endif + +#ifdef CONFIG_DRIVER_DAVINCI_I2C +void davinci_enable_i2c(void) +{ + lpsc_on(DAVINCI_DM646X_LPSC_I2C); +} +#endif -- cgit v1.2.3 From 6c507885c766646a66d822feee351e1f2b58d586 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 24 Aug 2009 20:48:04 -0400 Subject: Blackfin: use scratch pad for exception stack If the memory layout pushes the stack out of the default DCPLB coverage, the exception handler may trigger a double fault by trying to push onto the uncovered stack. So handle the exception stack similar to the kernel by using the top of the scratch pad SRAM. Signed-off-by: Mike Frysinger --- cpu/blackfin/interrupt.S | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'cpu') diff --git a/cpu/blackfin/interrupt.S b/cpu/blackfin/interrupt.S index dd2cc5320c0..71e0fc67088 100644 --- a/cpu/blackfin/interrupt.S +++ b/cpu/blackfin/interrupt.S @@ -5,6 +5,7 @@ * Licensed under the GPL-2 or later. */ +#include #include #include @@ -12,12 +13,16 @@ /* default entry point for exceptions */ ENTRY(_trap) + CONFIG_BFIN_SCRATCH_REG = sp; + sp.l = LO(L1_SRAM_SCRATCH_END - 20); + sp.h = HI(L1_SRAM_SCRATCH_END - 20); SAVE_ALL_SYS r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ sp += -12; call _trap_c; sp += 12; RESTORE_ALL_SYS + sp = CONFIG_BFIN_SCRATCH_REG; rtx; ENDPROC(_trap) -- cgit v1.2.3 From ac28dcfe895e5fbfc51347e9e826c8f56796e551 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:46 +1000 Subject: i386: Change inline asm global symbols to local gcc 4.3.2 optimiser creates multiple copies of inline asm (who knows why) Remove use of global names for labels to prevent 'symbol already defined' errors Signed-off-by: Graeme Russ --- cpu/i386/sc520/sc520.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/i386/sc520/sc520.c b/cpu/i386/sc520/sc520.c index ae3b50007f2..1d79210a62f 100644 --- a/cpu/i386/sc520/sc520.c +++ b/cpu/i386/sc520/sc520.c @@ -109,9 +109,9 @@ void init_sc520(void) /* wait at least one millisecond */ asm("movl $0x2000,%%ecx\n" - "wait_loop: pushl %%ecx\n" + "0: pushl %%ecx\n" "popl %%ecx\n" - "loop wait_loop\n": : : "ecx"); + "loop 0b\n": : : "ecx"); /* turn on the SDRAM write buffer */ write_mmcr_byte(SC520_DBCTL, 0x11); -- cgit v1.2.3 From a219983dc16c90daed5e27133383edd7db95f4cd Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:49 +1000 Subject: Fix sc520 timer interrupt generation The current implementation has the timer being started before the interrupt handler is installed. It the interrupt occurs before the handler is installed, the timer interrupt is never reset and the timer stops Signed-off-by: Graeme Russ --- cpu/i386/sc520/sc520_timer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/i386/sc520/sc520_timer.c b/cpu/i386/sc520/sc520_timer.c index 2cb8656ebd5..2a3425b6167 100644 --- a/cpu/i386/sc520/sc520_timer.c +++ b/cpu/i386/sc520/sc520_timer.c @@ -54,9 +54,6 @@ int timer_init(void) write_mmcr_word (SC520_GPTMR1MAXCMPA, 100); write_mmcr_word (SC520_GPTMR1CTL, 0xe009); - /* Clear the GP Timers status register */ - write_mmcr_byte (SC520_GPTMRSTA, 0x07); - /* Register the SC520 specific timer interrupt handler */ register_timer_isr (sc520_timer_isr); @@ -64,6 +61,9 @@ int timer_init(void) irq_install_handler (0, timer_isr, NULL); unmask_irq (0); + /* Clear the GP Timer 1 status register to get the show rolling*/ + write_mmcr_byte (SC520_GPTMRSTA, 0x02); + return 0; } -- cgit v1.2.3 From ed3afafd487d1557e175d53270aa3f44427e5632 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:50 +1000 Subject: i386: Misc PCI fixups Change PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY (Originally done in commit ff4e66e93c1a, regressed by commit 6d7f610b09f8) Cast PCI_ROM_ADDRESS_MASK to u32 Wrap probe_pci_video() call inside #ifdef CONFIG_VIDEO Change call to pci_find_class() to pci_find_devices(). This is based on a patch submitted on 1st March 2007 (Patch that fixes the compilation errors for sc520_cdp board) by mushtaq_k This patch requires that PCI_VIDEO_VENDOR_ID and PCI_VIDEO_DEVICE_ID be specified in the board config file. Dummy values have been added for the SC520 CDP board to enable compilation, but since I do not have one of these, I do know what the values should be Signed-off-by: Graeme Russ --- cpu/i386/sc520/sc520_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/i386/sc520/sc520_pci.c b/cpu/i386/sc520/sc520_pci.c index 38b837e81ce..871ad0a7361 100644 --- a/cpu/i386/sc520/sc520_pci.c +++ b/cpu/i386/sc520/sc520_pci.c @@ -124,7 +124,7 @@ void pci_sc520_init(struct pci_controller *hose) SC520_PCI_MEMORY_BUS, SC520_PCI_MEMORY_PHYS, SC520_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); /* PCI memory space */ pci_set_region(hose->regions + 1, -- cgit v1.2.3 From 5aaeb2a3d4c968c54b8d9ddc97dabfd1a1e04cf8 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:56 +1000 Subject: i386: Replace [read, write]_mmcr_[byte, word, long] with memory mapped structure Signed-off-by: Graeme Russ --- cpu/i386/sc520/sc520.c | 71 ++++++++++---------------------------------- cpu/i386/sc520/sc520_pci.c | 66 ++++++++++++++++++++-------------------- cpu/i386/sc520/sc520_ssi.c | 28 +++++++++-------- cpu/i386/sc520/sc520_timer.c | 31 +++++++++---------- 4 files changed, 79 insertions(+), 117 deletions(-) (limited to 'cpu') diff --git a/cpu/i386/sc520/sc520.c b/cpu/i386/sc520/sc520.c index 1d79210a62f..4b566a75ccd 100644 --- a/cpu/i386/sc520/sc520.c +++ b/cpu/i386/sc520/sc520.c @@ -33,75 +33,35 @@ DECLARE_GLOBAL_DATA_PTR; /* * utility functions for boards based on the AMD sc520 * - * void write_mmcr_byte(u16 mmcr, u8 data) - * void write_mmcr_word(u16 mmcr, u16 data) - * void write_mmcr_long(u16 mmcr, u32 data) - * - * u8 read_mmcr_byte(u16 mmcr) - * u16 read_mmcr_word(u16 mmcr) - * u32 read_mmcr_long(u16 mmcr) - * * void init_sc520(void) * unsigned long init_sc520_dram(void) */ -static u32 mmcr_base= 0xfffef000; - -void write_mmcr_byte(u16 mmcr, u8 data) -{ - writeb(data, mmcr+mmcr_base); -} - -void write_mmcr_word(u16 mmcr, u16 data) -{ - writew(data, mmcr+mmcr_base); -} - -void write_mmcr_long(u16 mmcr, u32 data) -{ - writel(data, mmcr+mmcr_base); -} - -u8 read_mmcr_byte(u16 mmcr) -{ - return readb(mmcr+mmcr_base); -} - -u16 read_mmcr_word(u16 mmcr) -{ - return readw(mmcr+mmcr_base); -} - -u32 read_mmcr_long(u16 mmcr) -{ - return readl(mmcr+mmcr_base); -} - +volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000; void init_sc520(void) { /* Set the UARTxCTL register at it's slower, * baud clock giving us a 1.8432 MHz reference */ - write_mmcr_byte(SC520_UART1CTL, 7); - write_mmcr_byte(SC520_UART2CTL, 7); + sc520_mmcr->uart1ctl = 0x07; + sc520_mmcr->uart2ctl = 0x07; /* first set the timer pin mapping */ - write_mmcr_byte(SC520_CLKSEL, 0x72); /* no clock frequency selected, use 1.1892MHz */ + sc520_mmcr->clksel = 0x72; /* no clock frequency selected, use 1.1892MHz */ /* enable PCI bus arbitrer */ - write_mmcr_byte(SC520_SYSARBCTL,0x02); /* enable concurrent mode */ - - write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */ - write_mmcr_word(SC520_HBCTL,0x04); /* enable posted-writes */ + sc520_mmcr->sysarbctl = 0x02; /* enable concurrent mode */ + sc520_mmcr->sysarbmenb = 0x1f; /* enable external grants */ + sc520_mmcr->hbctl = 0x04; /* enable posted-writes */ if (CONFIG_SYS_SC520_HIGH_SPEED) { - write_mmcr_byte(SC520_CPUCTL, 0x2); /* set it to 133 MHz and write back */ + sc520_mmcr->cpuctl = 0x02; /* set it to 133 MHz and write back */ gd->cpu_clk = 133000000; printf("## CPU Speed set to 133MHz\n"); } else { - write_mmcr_byte(SC520_CPUCTL, 1); /* set CPU to 100 MHz and write back cache */ + sc520_mmcr->cpuctl = 0x01; /* set it to 100 MHz and write back */ printf("## CPU Speed set to 100MHz\n"); gd->cpu_clk = 100000000; } @@ -114,7 +74,7 @@ void init_sc520(void) "loop 0b\n": : : "ecx"); /* turn on the SDRAM write buffer */ - write_mmcr_byte(SC520_DBCTL, 0x11); + sc520_mmcr->dbctl = 0x11; /* turn on the cache and disable write through */ asm("movl %%cr0, %%eax\n" @@ -156,10 +116,9 @@ unsigned long init_sc520_dram(void) val = 3; /* 62.4us */ } - write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4)); + sc520_mmcr->drcctl = (sc520_mmcr->drcctl & 0xcf) | (val<<4); - val = read_mmcr_byte(SC520_DRCTMCTL); - val &= 0xf0; + val = sc520_mmcr->drctmctl & 0xf0; if (cas_precharge_delay==3) { val |= 0x04; /* 3T */ @@ -174,12 +133,12 @@ unsigned long init_sc520_dram(void) } else { val |= 1; } - write_mmcr_byte(SC520_DRCTMCTL, val); + sc520_mmcr->drctmctl = val; #endif /* We read-back the configuration of the dram * controller that the assembly code wrote */ - dram_ctrl = read_mmcr_long(SC520_DRCBENDADR); + dram_ctrl = sc520_mmcr->drcbendadr; bd->bi_dram[0].start = 0; if (dram_ctrl & 0x80) { @@ -232,7 +191,7 @@ void reset_cpu(ulong addr) { printf("Resetting using SC520 MMCR\n"); /* Write a '1' to the SYS_RST of the RESCFG MMCR */ - write_mmcr_word(SC520_RESCFG, 0x0001); + sc520_mmcr->rescfg = 0x01; /* NOTREACHED */ } diff --git a/cpu/i386/sc520/sc520_pci.c b/cpu/i386/sc520/sc520_pci.c index 871ad0a7361..f446c6d5927 100644 --- a/cpu/i386/sc520/sc520_pci.c +++ b/cpu/i386/sc520/sc520_pci.c @@ -33,23 +33,23 @@ static struct { u16 level_reg; u8 level_bit; } sc520_irq[] = { - { SC520_IRQ0, SC520_MPICMODE, 0x01 }, - { SC520_IRQ1, SC520_MPICMODE, 0x02 }, - { SC520_IRQ2, SC520_SL1PICMODE, 0x02 }, - { SC520_IRQ3, SC520_MPICMODE, 0x08 }, - { SC520_IRQ4, SC520_MPICMODE, 0x10 }, - { SC520_IRQ5, SC520_MPICMODE, 0x20 }, - { SC520_IRQ6, SC520_MPICMODE, 0x40 }, - { SC520_IRQ7, SC520_MPICMODE, 0x80 }, - - { SC520_IRQ8, SC520_SL1PICMODE, 0x01 }, - { SC520_IRQ9, SC520_SL1PICMODE, 0x02 }, - { SC520_IRQ10, SC520_SL1PICMODE, 0x04 }, - { SC520_IRQ11, SC520_SL1PICMODE, 0x08 }, - { SC520_IRQ12, SC520_SL1PICMODE, 0x10 }, - { SC520_IRQ13, SC520_SL1PICMODE, 0x20 }, - { SC520_IRQ14, SC520_SL1PICMODE, 0x40 }, - { SC520_IRQ15, SC520_SL1PICMODE, 0x80 } + { SC520_IRQ0, 0, 0x01 }, + { SC520_IRQ1, 0, 0x02 }, + { SC520_IRQ2, 1, 0x02 }, + { SC520_IRQ3, 0, 0x08 }, + { SC520_IRQ4, 0, 0x10 }, + { SC520_IRQ5, 0, 0x20 }, + { SC520_IRQ6, 0, 0x40 }, + { SC520_IRQ7, 0, 0x80 }, + + { SC520_IRQ8, 1, 0x01 }, + { SC520_IRQ9, 1, 0x02 }, + { SC520_IRQ10, 1, 0x04 }, + { SC520_IRQ11, 1, 0x08 }, + { SC520_IRQ12, 1, 0x10 }, + { SC520_IRQ13, 1, 0x20 }, + { SC520_IRQ14, 1, 0x40 }, + { SC520_IRQ15, 1, 0x80 } }; @@ -77,34 +77,34 @@ int pci_sc520_set_irq(int pci_pin, int irq) /* first disable any non-pci interrupt source that use * this level */ - for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) { - if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) { - continue; - } - if (read_mmcr_byte(i) == sc520_irq[irq].priority) { - write_mmcr_byte(i, SC520_IRQ_DISABLED); - } + + /* PCI interrupt mapping (A through D)*/ + for (i=0; i<=3 ;i++) { + if (sc520_mmcr->pci_int_map[i] == sc520_irq[irq].priority) + sc520_mmcr->pci_int_map[i] = SC520_IRQ_DISABLED; + } + + /* GP IRQ interrupt mapping */ + for (i=0; i<=10 ;i++) { + if (sc520_mmcr->gp_int_map[i] == sc520_irq[irq].priority) + sc520_mmcr->gp_int_map[i] = SC520_IRQ_DISABLED; } /* Set the trigger to level */ - write_mmcr_byte(sc520_irq[irq].level_reg, - read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit); + sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] = + sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] | sc520_irq[irq].level_bit; if (pci_pin < 4) { /* PCI INTA-INTD */ /* route the interrupt */ - write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority); - - + sc520_mmcr->pci_int_map[pci_pin] = sc520_irq[irq].priority; } else { /* GPIRQ0-GPIRQ10 used for additional PCI INTS */ - write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority); + sc520_mmcr->gp_int_map[pci_pin - 4] = sc520_irq[irq].priority; /* also set the polarity in this case */ - write_mmcr_word(SC520_INTPINPOL, - read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4))); - + sc520_mmcr->intpinpol = sc520_mmcr->intpinpol | (1 << (pci_pin-4)); } /* register the pin */ diff --git a/cpu/i386/sc520/sc520_ssi.c b/cpu/i386/sc520/sc520_ssi.c index dd667ca8cbb..8dbe17aa60e 100644 --- a/cpu/i386/sc520/sc520_ssi.c +++ b/cpu/i386/sc520/sc520_ssi.c @@ -61,32 +61,34 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase) temp |= PHS_INV_ENB; } - write_mmcr_byte(SC520_SSICTL, temp); + sc520_mmcr->ssictl = temp; return 0; } u8 ssi_txrx_byte(u8 data) { - write_mmcr_byte(SC520_SSIXMIT, data); - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV); - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - return read_mmcr_byte(SC520_SSIRCV); + sc520_mmcr->ssixmit = data; + while (sc520_mmcr->ssista & SSISTA_BSY); + sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMITRCV; + while (sc520_mmcr->ssista & SSISTA_BSY); + + return sc520_mmcr->ssircv; } void ssi_tx_byte(u8 data) { - write_mmcr_byte(SC520_SSIXMIT, data); - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT); + sc520_mmcr->ssixmit = data; + while (sc520_mmcr->ssista & SSISTA_BSY); + sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMIT; } u8 ssi_rx_byte(void) { - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV); - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - return read_mmcr_byte(SC520_SSIRCV); + while (sc520_mmcr->ssista & SSISTA_BSY); + sc520_mmcr->ssicmd = SSICMD_CMD_SEL_RCV; + while (sc520_mmcr->ssista & SSISTA_BSY); + + return sc520_mmcr->ssircv; } diff --git a/cpu/i386/sc520/sc520_timer.c b/cpu/i386/sc520/sc520_timer.c index 2a3425b6167..23de14bdd81 100644 --- a/cpu/i386/sc520/sc520_timer.c +++ b/cpu/i386/sc520/sc520_timer.c @@ -30,29 +30,29 @@ void sc520_timer_isr(void) { /* Ack the GP Timer Interrupt */ - write_mmcr_byte (SC520_GPTMRSTA, 0x02); + sc520_mmcr->gptmrsta = 0x02; } int timer_init(void) { /* Map GP Timer 1 to Master PIC IR0 */ - write_mmcr_byte (SC520_GPTMR1MAP, 0x01); + sc520_mmcr->gp_tmr_int_map[1] = 0x01; /* Disable GP Timers 1 & 2 - Allow configuration writes */ - write_mmcr_word (SC520_GPTMR1CTL, 0x4000); - write_mmcr_word (SC520_GPTMR2CTL, 0x4000); + sc520_mmcr->gptmr1ctl = 0x4000; + sc520_mmcr->gptmr2ctl = 0x4000; /* Reset GP Timers 1 & 2 */ - write_mmcr_word (SC520_GPTMR1CNT, 0x0000); - write_mmcr_word (SC520_GPTMR2CNT, 0x0000); + sc520_mmcr->gptmr1cnt = 0x0000; + sc520_mmcr->gptmr2cnt = 0x0000; /* Setup GP Timer 2 as a 100kHz (10us) prescaler */ - write_mmcr_word (SC520_GPTMR2MAXCMPA, 83); - write_mmcr_word (SC520_GPTMR2CTL, 0xc001); + sc520_mmcr->gptmr2maxcmpa = 83; + sc520_mmcr->gptmr2ctl = 0xc001; /* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */ - write_mmcr_word (SC520_GPTMR1MAXCMPA, 100); - write_mmcr_word (SC520_GPTMR1CTL, 0xe009); + sc520_mmcr->gptmr1maxcmpa = 100; + sc520_mmcr->gptmr1ctl = 0xe009; /* Register the SC520 specific timer interrupt handler */ register_timer_isr (sc520_timer_isr); @@ -62,7 +62,7 @@ int timer_init(void) unmask_irq (0); /* Clear the GP Timer 1 status register to get the show rolling*/ - write_mmcr_byte (SC520_GPTMRSTA, 0x02); + sc520_mmcr->gptmrsta = 0x02; return 0; } @@ -71,12 +71,13 @@ void udelay(unsigned long usec) { int m = 0; long u; + long temp; - read_mmcr_word (SC520_SWTMRMILLI); - read_mmcr_word (SC520_SWTMRMICRO); + temp = sc520_mmcr->swtmrmilli; + temp = sc520_mmcr->swtmrmicro; do { - m += read_mmcr_word (SC520_SWTMRMILLI); - u = read_mmcr_word (SC520_SWTMRMICRO) + (m * 1000); + m += sc520_mmcr->swtmrmilli; + u = sc520_mmcr->swtmrmicro + (m * 1000); } while (u < usec); } -- cgit v1.2.3 From 5ce1da9af35f13c231381d1152bd429d7801c3c2 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 1 Sep 2009 11:24:44 -0500 Subject: ppc: Remove -fno-strict-aliasing -fno-strict-aliasing is hidding warnings. Signed-off-by: Kumar Gala --- cpu/74xx_7xx/config.mk | 2 +- cpu/mpc824x/config.mk | 2 +- cpu/mpc8xx/config.mk | 2 +- cpu/ppc4xx/config.mk | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/74xx_7xx/config.mk b/cpu/74xx_7xx/config.mk index 324f62b836d..d58921079c7 100644 --- a/cpu/74xx_7xx/config.mk +++ b/cpu/74xx_7xx/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -mstring diff --git a/cpu/mpc824x/config.mk b/cpu/mpc824x/config.mk index 1bb0487bd3b..b607fee4fdd 100644 --- a/cpu/mpc824x/config.mk +++ b/cpu/mpc824x/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float diff --git a/cpu/mpc8xx/config.mk b/cpu/mpc8xx/config.mk index 6031e7f76af..2b3d545cc37 100644 --- a/cpu/mpc8xx/config.mk +++ b/cpu/mpc8xx/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -mstring -mcpu=860 -msoft-float diff --git a/cpu/ppc4xx/config.mk b/cpu/ppc4xx/config.mk index baa97a4122a..00ad39b6027 100644 --- a/cpu/ppc4xx/config.mk +++ b/cpu/ppc4xx/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -mstring -msoft-float cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') -- cgit v1.2.3 From d42914fbb8fc886f75da1bf74643fc3e7a00f3ce Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 1 Sep 2009 11:24:45 -0500 Subject: arm: Remove -fno-strict-aliasing -fno-strict-aliasing is hidding warnings. Signed-off-by: Kumar Gala --- cpu/arm1136/config.mk | 3 +-- cpu/arm1176/config.mk | 3 +-- cpu/arm1176/s3c64xx/config.mk | 3 +-- cpu/arm720t/config.mk | 3 +-- cpu/arm920t/config.mk | 3 +-- cpu/arm925t/config.mk | 3 +-- cpu/arm926ejs/config.mk | 3 +-- cpu/arm926ejs/davinci/config.mk | 3 +-- cpu/arm946es/config.mk | 3 +-- cpu/arm_cortexa8/config.mk | 3 +-- cpu/arm_intcm/config.mk | 3 +-- cpu/ixp/config.mk | 3 +-- cpu/lh7a40x/config.mk | 3 +-- cpu/pxa/config.mk | 3 +-- cpu/s3c44b0/config.mk | 3 +-- cpu/sa1100/config.mk | 3 +-- 16 files changed, 16 insertions(+), 32 deletions(-) (limited to 'cpu') diff --git a/cpu/arm1136/config.mk b/cpu/arm1136/config.mk index 61d5a382ed8..3e685354ab7 100644 --- a/cpu/arm1136/config.mk +++ b/cpu/arm1136/config.mk @@ -20,8 +20,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # Make ARMv5 to allow more compilers to work, even though its v6. PLATFORM_CPPFLAGS += -march=armv5 diff --git a/cpu/arm1176/config.mk b/cpu/arm1176/config.mk index a31c7b0f897..14346cfff3f 100644 --- a/cpu/arm1176/config.mk +++ b/cpu/arm1176/config.mk @@ -20,8 +20,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # Make ARMv5 to allow more compilers to work, even though its v6. PLATFORM_CPPFLAGS += -march=armv5t diff --git a/cpu/arm1176/s3c64xx/config.mk b/cpu/arm1176/s3c64xx/config.mk index a31c7b0f897..14346cfff3f 100644 --- a/cpu/arm1176/s3c64xx/config.mk +++ b/cpu/arm1176/s3c64xx/config.mk @@ -20,8 +20,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # Make ARMv5 to allow more compilers to work, even though its v6. PLATFORM_CPPFLAGS += -march=armv5t diff --git a/cpu/arm720t/config.mk b/cpu/arm720t/config.mk index 74d52831ede..3844c626af3 100644 --- a/cpu/arm720t/config.mk +++ b/cpu/arm720t/config.mk @@ -22,8 +22,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi # ========================================================================= diff --git a/cpu/arm920t/config.mk b/cpu/arm920t/config.mk index a43b1567110..8f6c1a354c5 100644 --- a/cpu/arm920t/config.mk +++ b/cpu/arm920t/config.mk @@ -21,8 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv4 # ========================================================================= diff --git a/cpu/arm925t/config.mk b/cpu/arm925t/config.mk index a43b1567110..8f6c1a354c5 100644 --- a/cpu/arm925t/config.mk +++ b/cpu/arm925t/config.mk @@ -21,8 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv4 # ========================================================================= diff --git a/cpu/arm926ejs/config.mk b/cpu/arm926ejs/config.mk index 90eb3c0edec..f8ef90f2d51 100644 --- a/cpu/arm926ejs/config.mk +++ b/cpu/arm926ejs/config.mk @@ -21,8 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv5te # ========================================================================= diff --git a/cpu/arm926ejs/davinci/config.mk b/cpu/arm926ejs/davinci/config.mk index 7757be398ae..565adda11d4 100644 --- a/cpu/arm926ejs/davinci/config.mk +++ b/cpu/arm926ejs/davinci/config.mk @@ -21,8 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv5te # ========================================================================= diff --git a/cpu/arm946es/config.mk b/cpu/arm946es/config.mk index a81321bd3cc..e783f697a10 100644 --- a/cpu/arm946es/config.mk +++ b/cpu/arm946es/config.mk @@ -21,8 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv4 # ========================================================================= diff --git a/cpu/arm_cortexa8/config.mk b/cpu/arm_cortexa8/config.mk index da5ee162c5f..49ac9c74aeb 100644 --- a/cpu/arm_cortexa8/config.mk +++ b/cpu/arm_cortexa8/config.mk @@ -20,8 +20,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # Make ARMv5 to allow more compilers to work, even though its v7a. PLATFORM_CPPFLAGS += -march=armv5 diff --git a/cpu/arm_intcm/config.mk b/cpu/arm_intcm/config.mk index a81321bd3cc..e783f697a10 100644 --- a/cpu/arm_intcm/config.mk +++ b/cpu/arm_intcm/config.mk @@ -21,8 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv4 # ========================================================================= diff --git a/cpu/ixp/config.mk b/cpu/ixp/config.mk index 2c33b40a2cb..deca3f4d550 100644 --- a/cpu/ixp/config.mk +++ b/cpu/ixp/config.mk @@ -24,8 +24,7 @@ BIG_ENDIAN = y -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float -mbig-endian +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float -mbig-endian PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100 # ========================================================================= diff --git a/cpu/lh7a40x/config.mk b/cpu/lh7a40x/config.mk index 27bc4812606..47b2b7b722d 100644 --- a/cpu/lh7a40x/config.mk +++ b/cpu/lh7a40x/config.mk @@ -21,8 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv4 # ========================================================================= diff --git a/cpu/pxa/config.mk b/cpu/pxa/config.mk index f360478d0c2..a05d69ca270 100644 --- a/cpu/pxa/config.mk +++ b/cpu/pxa/config.mk @@ -22,8 +22,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale # ========================================================================= diff --git a/cpu/s3c44b0/config.mk b/cpu/s3c44b0/config.mk index 3623f2503e2..7454d728a55 100644 --- a/cpu/s3c44b0/config.mk +++ b/cpu/s3c44b0/config.mk @@ -22,8 +22,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float # ========================================================================= diff --git a/cpu/sa1100/config.mk b/cpu/sa1100/config.mk index 553cd0c9cfc..6f21f410be3 100644 --- a/cpu/sa1100/config.mk +++ b/cpu/sa1100/config.mk @@ -22,8 +22,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100 # ========================================================================= -- cgit v1.2.3 From 13ba788a62c59ba85fb5849be74aec80bf34f0ba Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 2 Sep 2009 17:58:48 +0400 Subject: mpc83xx/serdes: License cleanup: remove "All Rights Reserved" notice "All Rights Reserved" conflicts with the GPL. Signed-off-by: Anton Vorontsov --- cpu/mpc83xx/serdes.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/serdes.c b/cpu/mpc83xx/serdes.c index 283cc3f4108..64033fe4c35 100644 --- a/cpu/mpc83xx/serdes.c +++ b/cpu/mpc83xx/serdes.c @@ -2,7 +2,7 @@ * Freescale SerDes initialization routine * * Copyright (C) 2007 Freescale Semicondutor, Inc. - * Copyright (C) 2008 MontaVista Software, Inc. All rights reserved. + * Copyright (C) 2008 MontaVista Software, Inc. * * Author: Li Yang * -- cgit v1.2.3 From 9179dd3bf5c257d1479fb4a154b57f33e3d839be Mon Sep 17 00:00:00 2001 From: Eric Millbrandt Date: Thu, 3 Sep 2009 08:09:44 -0500 Subject: Reset i2c slave devices during init on mpc5xxx cpus Reset any i2c devices that may have been interrupted during a system reset. Normally this would be accomplished by clocking the line until SCL and SDA are released and then sending a start condtiion (From an Atmel datasheet). There is no direct access to the i2c pins so instead create start commands through the i2c interface. Send a start command then delay for the SDA Hold time, repeat this by disabling/enabling the bus a total of 9 times. Signed-off-by: Eric Millbrandt --- cpu/mpc5xxx/i2c.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc5xxx/i2c.c b/cpu/mpc5xxx/i2c.c index 23419324ba5..4f7f7163287 100644 --- a/cpu/mpc5xxx/i2c.c +++ b/cpu/mpc5xxx/i2c.c @@ -207,6 +207,52 @@ static int receive_bytes(uchar chip, char *buf, int len) return 0; } +#if defined(CONFIG_SYS_I2C_INIT_MPC5XXX) + +#define FDR510(x) (u8) (((x & 0x20) >> 3) | (x & 0x3)) +#define FDR432(x) (u8) ((x & 0x1C) >> 2) +/* + * Reset any i2c devices that may have been interrupted during a system reset. + * Normally this would be accomplished by clocking the line until SCL and SDA + * are released and then sending a start condtiion (From an Atmel datasheet). + * There is no direct access to the i2c pins so instead create start commands + * through the i2c interface. Send a start command then delay for the SDA Hold + * time, repeat this by disabling/enabling the bus a total of 9 times. + */ +static void send_reset(void) +{ + struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; + int i; + u32 delay; + u8 fdr; + int SDA_Tap[] = { 3, 3, 4, 4, 1, 1, 2, 2}; + struct mpc5xxx_i2c_tap scltap[] = { + {4, 1}, + {4, 2}, + {6, 4}, + {6, 8}, + {14, 16}, + {30, 32}, + {62, 64}, + {126, 128} + }; + + fdr = (u8)mpc_reg_in(®s->mfdr); + + delay = scltap[FDR432(fdr)].scl2tap + ((SDA_Tap[FDR510(fdr)] - 1) * \ + scltap[FDR432(fdr)].tap2tap) + 3; + + for (i = 0; i < 9; i++) { + mpc_reg_out(®s->mcr, I2C_EN|I2C_STA|I2C_TX, I2C_INIT_MASK); + udelay(delay); + mpc_reg_out(®s->mcr, 0, I2C_INIT_MASK); + udelay(delay); + } + + mpc_reg_out(®s->mcr, I2C_EN, I2C_INIT_MASK); +} +#endif /* CONFIG_SYS_I2c_INIT_MPC5XXX */ + /**************** I2C API ****************/ void i2c_init(int speed, int saddr) @@ -225,6 +271,9 @@ void i2c_init(int speed, int saddr) mpc_reg_out(®s->mcr, I2C_EN, I2C_INIT_MASK); mpc_reg_out(®s->msr, 0, I2C_IF); +#if defined(CONFIG_SYS_I2C_INIT_MPC5XXX) + send_reset(); +#endif return; } -- cgit v1.2.3 From 20f02c3b760d33f67378a9bcff177a8012cd6a17 Mon Sep 17 00:00:00 2001 From: Dipen Dudhat Date: Tue, 1 Sep 2009 17:27:00 +0530 Subject: ppc/85xx: Use CONFIG_FSL_ESDHC to enable sdhc clk Enable eSDHC Clock based on generic CONFIG_FSL_ESDHC define instead of a platform define. This will enable all the 85xx platforms to use sdhc_clk based on CONFIG_FSL_ESDHC. Signed-off-by: Gao Guanhua Signed-off-by: Dipen Dudhat Signed-off-by: Kumar Gala --- cpu/mpc85xx/speed.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 3ef49b456fb..2fdcefb219c 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -153,7 +153,7 @@ int get_clocks (void) #endif gd->i2c2_clk = gd->i2c1_clk; -#if defined(CONFIG_MPC8536) +#if defined(CONFIG_FSL_ESDHC) gd->sdhc_clk = gd->bus_clk / 2; #endif -- cgit v1.2.3 From ed4b37e867714e264526d58edd5dce96e945024c Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 1 Sep 2009 22:01:54 -0500 Subject: ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist The ddr_pd_cntl isn't defined in any reference manual and thus we wil remove especially since we set it to 0, which would most likely be its POR value. Signed-off-by: Kumar Gala --- cpu/mpc85xx/ddr-gen3.c | 1 - cpu/mpc8xxx/ddr/ctrl_regs.c | 23 ----------------------- 2 files changed, 24 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c index 8ac3d5fbebf..0691ca455af 100644 --- a/cpu/mpc85xx/ddr-gen3.c +++ b/cpu/mpc85xx/ddr-gen3.c @@ -74,7 +74,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); - out_be32(&ddr->ddr_pd_cntl, regs->ddr_pd_cntl); out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 1689d680bdf..5e63c5df3ad 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1066,28 +1066,6 @@ static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; } -/* DDR Pre-Drive Conditioning Control (DDR_PD_CNTL) */ -static void set_ddr_pd_cntl(fsl_ddr_cfg_regs_t *ddr) -{ - /* Termination value during pre-drive conditioning */ - unsigned int tvpd = 0; - unsigned int pd_en = 0; /* Pre-Drive Conditioning Enable */ - unsigned int pdar = 0; /* Pre-Drive After Read */ - unsigned int pdaw = 0; /* Pre-Drive After Write */ - unsigned int pd_on = 0; /* Pre-Drive Conditioning On */ - unsigned int pd_off = 0; /* Pre-Drive Conditioning Off */ - - ddr->ddr_pd_cntl = (0 - | ((pd_en & 0x1) << 31) - | ((tvpd & 0x7) << 28) - | ((pdar & 0x7F) << 20) - | ((pdaw & 0x7F) << 12) - | ((pd_on & 0x1F) << 6) - | ((pd_off & 0x1F) << 0) - ); -} - - /* DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1) */ static void set_ddr_sdram_rcw_1(fsl_ddr_cfg_regs_t *ddr) { @@ -1355,7 +1333,6 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_zq_cntl(ddr, zq_en); set_ddr_wrlvl_cntl(ddr, wrlvl_en); - set_ddr_pd_cntl(ddr); set_ddr_sr_cntr(ddr, sr_it); set_ddr_sdram_rcw_1(ddr); -- cgit v1.2.3 From 4507c0a0a0e87aec662bedd54bdffdd81d26c643 Mon Sep 17 00:00:00 2001 From: Dipen Dudhat Date: Wed, 2 Sep 2009 11:25:08 +0530 Subject: ppc/85xx: Fix up eSDHC controller clock frequency in the device tree Signed-off-by: Dipen Dudhat Signed-off-by: Kumar Gala --- cpu/mpc85xx/fdt.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index a692529689d..8366379ab60 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -27,6 +27,9 @@ #include #include #include +#ifdef CONFIG_FSL_ESDHC +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -326,4 +329,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif ft_fixup_cache(blob); + +#if defined(CONFIG_FSL_ESDHC) + fdt_fixup_esdhc(blob, bd); +#endif } -- cgit v1.2.3 From e568fd99ab26a469646b9ad670443923174919c1 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 14 Aug 2009 13:37:54 -0500 Subject: 85xx: Add support for setting IVORs to fixed offset defaults In future Book-E implementations IVORs will most likely go away and be replaced with fixed offsets. The IVPR will continue to exist to allow for relocation of the interrupt vectors. This code adds support to setup the IVORs as their fixed offset values per the ISA 2.06 spec when we transition from u-boot to another OS either via 'bootm' or a cpu release. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu_init.c | 7 +++++ cpu/mpc85xx/fixed_ivor.S | 79 ++++++++++++++++++++++++++++++++++++++++++++++++ cpu/mpc85xx/release.S | 3 ++ cpu/mpc85xx/start.S | 6 ++++ 4 files changed, 95 insertions(+) create mode 100644 cpu/mpc85xx/fixed_ivor.S (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index c4d1a9dd9c7..a54cf5d1570 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -375,3 +375,10 @@ int cpu_init_r(void) #endif return 0; } + +extern void setup_ivors(void); + +void arch_preboot_os(void) +{ + setup_ivors(); +} diff --git a/cpu/mpc85xx/fixed_ivor.S b/cpu/mpc85xx/fixed_ivor.S new file mode 100644 index 00000000000..dc725c94813 --- /dev/null +++ b/cpu/mpc85xx/fixed_ivor.S @@ -0,0 +1,79 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * Kumar Gala + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This file is intended to be included by other asm code since + * we will want to execute this on both the primary core when + * it does a bootm and the secondary core's that get released + * out of the spin table */ + +#define SET_IVOR(vector_number, vector_offset) \ + li r3,vector_offset@l; \ + mtspr SPRN_IVOR##vector_number,r3; + +#define SET_GIVOR(vector_number, vector_offset) \ + li r3,vector_offset@l; \ + mtspr SPRN_GIVOR##vector_number,r3; + + SET_IVOR(0, 0x020) /* Critical Input */ + SET_IVOR(1, 0x000) /* Machine Check */ + SET_IVOR(2, 0x060) /* Data Storage */ + SET_IVOR(3, 0x080) /* Instruction Storage */ + SET_IVOR(4, 0x0a0) /* External Input */ + SET_IVOR(5, 0x0c0) /* Alignment */ + SET_IVOR(6, 0x0e0) /* Program */ + SET_IVOR(7, 0x100) /* FP Unavailable */ + SET_IVOR(8, 0x120) /* System Call */ + SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ + SET_IVOR(10, 0x160) /* Decrementer */ + SET_IVOR(11, 0x180) /* Fixed Interval Timer */ + SET_IVOR(12, 0x1a0) /* Watchdog Timer */ + SET_IVOR(13, 0x1c0) /* Data TLB Error */ + SET_IVOR(14, 0x1e0) /* Instruction TLB Error */ + SET_IVOR(15, 0x040) /* Debug */ + +/* e500v1 & e500v2 only */ +#ifndef CONFIG_E500MC + SET_IVOR(32, 0x200) /* SPE Unavailable */ + SET_IVOR(33, 0x220) /* Embedded FP Data */ + SET_IVOR(34, 0x240) /* Embedded FP Round */ +#endif + + SET_IVOR(35, 0x260) /* Performance monitor */ + +/* e500mc only */ +#ifdef CONFIG_E500MC + SET_IVOR(36, 0x280) /* Processor doorbell */ + SET_IVOR(37, 0x2a0) /* Processor doorbell critical */ + SET_IVOR(38, 0x2c0) /* Guest Processor doorbell */ + SET_IVOR(39, 0x2e0) /* Guest Processor critical & machine check */ + SET_IVOR(40, 0x300) /* Hypervisor system call */ + SET_IVOR(41, 0x320) /* Hypervisor Priviledge */ + + SET_GIVOR(2, 0x060) /* Guest Data Storage */ + SET_GIVOR(3, 0x080) /* Guest Instruction Storage */ + SET_GIVOR(4, 0x0a0) /* Guest External Input */ + SET_GIVOR(8, 0x120) /* Guest System Call */ + SET_GIVOR(13, 0x1c0) /* Guest Data TLB Error */ + SET_GIVOR(14, 0x1e0) /* Guest Instruction TLB Error */ +#endif diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 2d4f219a3b7..074b056b749 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -168,6 +168,9 @@ __secondary_start_page: bne 2b isync + /* setup IVORs to match fixed offsets */ +#include "fixed_ivor.S" + /* get the upper bits of the addr */ lwz r11,ENTRY_ADDR_UPPER(r10) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 4f7236fc35c..e21a4eb8767 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -1122,3 +1122,9 @@ flush_dcache: isync blr + +.globl setup_ivors +setup_ivors: + +#include "fixed_ivor.S" + blr -- cgit v1.2.3 From 176c84efc5760a78deb3f68bd23a987d26b6f099 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 3 Sep 2009 08:20:24 -0500 Subject: ppc/85xx: Add a simple function to search the TLB Allow us to search the TLB array based on an address. This is useful if we want to change an entry but dont know where it happens to be located. For example, the boot page mapping we use on MP or the flash TLB that we change the WIMGE settings for after we've relocated. Signed-off-by: Kumar Gala --- cpu/mpc85xx/tlb.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index f3d3080c44e..0497a29ba83 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -106,6 +106,33 @@ void init_tlbs(void) return ; } +static void tlbsx (const volatile unsigned *addr) +{ + __asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr)); +} + +/* return -1 if we didn't find anything */ +int find_tlb_idx(void *addr, u8 tlbsel) +{ + u32 _mas0, _mas1; + + /* zero out Search PID, AS */ + mtspr(MAS6, 0); + + tlbsx(addr); + + _mas0 = mfspr(MAS0); + _mas1 = mfspr(MAS1); + + /* we found something, and its in the TLB we expect */ + if ((MAS1_VALID & _mas1) && + (MAS0_TLBSEL(tlbsel) == (_mas0 & MAS0_TLBSEL_MSK))) { + return ((_mas0 & MAS0_ESEL_MSK) >> 16); + } + + return -1; +} + #ifdef CONFIG_ADDR_MAP void init_addr_map(void) { -- cgit v1.2.3 From eb0a2cc9e3486e0ca9d557abe5faa50f161331f2 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 3 Sep 2009 08:41:31 -0500 Subject: ppc/85xx: Fix bug in setup_mp code Its possible that we try and copy the boot page code out of flash into a DDR location that doesn't have a TLB cover it. For example, if we have 3G of DDR we typically only map the first 2G. In the cases of 4G+ this wasn't an issue since the reset page TLB mapping covered the last page of memory which we wanted to copy to. We now change the physical address of the reset page TLB to map to the true physical location of the boot page code, copy and than set the TLB back to its 1:1 mapping of the reset page. Signed-off-by: Kumar Gala --- cpu/mpc85xx/mp.c | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index 2df55c71d49..fa65bed083b 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "mp.h" DECLARE_GLOBAL_DATA_PTR; @@ -209,8 +210,33 @@ void setup_mp(void) ulong fixup = (ulong)&__secondary_start_page; u32 bootpg = determine_mp_bootpg(); - memcpy((void *)bootpg, (void *)fixup, 4096); - flush_cache(bootpg, 4096); + /* look for the tlb covering the reset page, there better be one */ + int i = find_tlb_idx((void *)0xfffff000, 1); - pq3_mp_up(bootpg); + /* we found a match */ + if (i != -1) { + /* map reset page to bootpg so we can copy code there */ + disable_tlb(i); + + set_tlb(1, 0xfffff000, bootpg, /* tlb, epn, rpn */ + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, /* perms, wimge */ + 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ + + memcpy((void *)0xfffff000, (void *)fixup, 4096); + flush_cache(0xfffff000, 4096); + + disable_tlb(i); + + /* setup reset page back to 1:1, we'll use HW boot translation + * to map this where we want + */ + set_tlb(1, 0xfffff000, 0xfffff000, /* tlb, epn, rpn */ + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */ + 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ + + pq3_mp_up(bootpg); + } else { + puts("WARNING: No reset page TLB. " + "Skipping secondary core setup\n"); + } } -- cgit v1.2.3 From 8b8376e81ca725772fa7a3e1b58ca55a761cdf1d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 2 Sep 2009 09:00:50 -0500 Subject: ppc/85xx: Cleanup makefile and related optional files Cleaned up cpu/mpc85xx/Makefile to use CONFIG_* for those obvious cases we have like PCI, CPM2, QE. Also reworked it to use one line per file for everything and sorted in alphabetical order. Signed-off-by: Kumar Gala --- cpu/mpc85xx/Makefile | 23 +++++++++++++++++------ cpu/mpc85xx/commproc.c | 3 --- cpu/mpc85xx/ether_fcc.c | 4 ---- cpu/mpc85xx/pci.c | 4 ++-- cpu/mpc85xx/serial_scc.c | 3 --- 5 files changed, 19 insertions(+), 18 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 1bd8f3057ae..a177f427efe 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -29,10 +29,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o resetvec.o -SOBJS-$(CONFIG_MP) += release.o +SOBJS-$(CONFIG_MP) += release.o SOBJS = $(SOBJS-y) -COBJS-$(CONFIG_MP) += mp.o -COBJS-$(CONFIG_OF_LIBFDT) += fdt.o + +COBJS-$(CONFIG_CPM2) += commproc.o # supports ddr1 COBJS-$(CONFIG_MPC8540) += ddr-gen1.o @@ -54,10 +54,21 @@ COBJS-$(CONFIG_P1020) += ddr-gen3.o COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o +COBJS-$(CONFIG_CPM2) += ether_fcc.o +COBJS-$(CONFIG_OF_LIBFDT) += fdt.o +COBJS-$(CONFIG_MP) += mp.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o -COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ - pci.o serial_scc.o commproc.o ether_fcc.o qe_io.o \ - $(COBJS-y) +COBJS-$(CONFIG_PCI) += pci.o +COBJS-$(CONFIG_QE) += qe_io.o +COBJS-$(CONFIG_CPM2) += serial_scc.o + +COBJS = $(COBJS-y) +COBJS += cpu.o +COBJS += cpu_init.o +COBJS += interrupts.o +COBJS += speed.o +COBJS += tlb.o +COBJS += traps.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc85xx/commproc.c b/cpu/mpc85xx/commproc.c index fff8dff5032..594aace4b12 100644 --- a/cpu/mpc85xx/commproc.c +++ b/cpu/mpc85xx/commproc.c @@ -26,7 +26,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_CPM2) /* * because we have stack and init data in dual port ram * we must reduce the size @@ -204,5 +203,3 @@ ulong post_word_load (void) } #endif /* CONFIG_POST */ - -#endif /* CONFIG_CPM2 */ diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c index 32ad46956ed..5f1414d7581 100644 --- a/cpu/mpc85xx/ether_fcc.c +++ b/cpu/mpc85xx/ether_fcc.c @@ -52,8 +52,6 @@ #include #endif -#if defined(CONFIG_CPM2) - #if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) && \ defined(CONFIG_NET_MULTI) @@ -469,5 +467,3 @@ int fec_initialize(bd_t *bis) } #endif - -#endif /* CONFIG_CPM2 */ diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index fedf1a54df6..75d2716ef40 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -29,7 +29,7 @@ #include #include -#if defined(CONFIG_PCI) && !defined(CONFIG_FSL_PCI_INIT) +#if !defined(CONFIG_FSL_PCI_INIT) #ifndef CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE @@ -227,4 +227,4 @@ pci_mpc85xx_init(struct pci_controller *board_hose) hose->last_busno = pci_hose_scan(hose); #endif } -#endif /* CONFIG_PCI */ +#endif /* !CONFIG_FSL_PCI_INIT */ diff --git a/cpu/mpc85xx/serial_scc.c b/cpu/mpc85xx/serial_scc.c index 05fb80875d8..2dab2124fcc 100644 --- a/cpu/mpc85xx/serial_scc.c +++ b/cpu/mpc85xx/serial_scc.c @@ -37,7 +37,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_CPM2) #if defined(CONFIG_CONS_ON_SCC) #if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */ @@ -267,5 +266,3 @@ serial_tstc() } #endif /* CONFIG_CONS_ON_SCC */ - -#endif /* CONFIG_CPM2 */ -- cgit v1.2.3 From 865f24dc92d03928c09b7f20a3133823e53c1ac3 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 2 Sep 2009 09:03:08 -0500 Subject: ppc/8xxx: Refactor code to determine if PCI is enabled & agent/host Refactor the code into a simple bitmask lookup table that determines if a given PCI controller is enabled and if its in host/root-complex or agent/end-point mode. Each processor in the PQ3/MPC86xx family specified different encodings for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals. Signed-off-by: Kumar Gala --- cpu/mpc8xxx/Makefile | 1 + cpu/mpc8xxx/pci_cfg.c | 225 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 226 insertions(+) create mode 100644 cpu/mpc8xxx/pci_cfg.c (limited to 'cpu') diff --git a/cpu/mpc8xxx/Makefile b/cpu/mpc8xxx/Makefile index 430a75f6f8c..5cb6814403d 100644 --- a/cpu/mpc8xxx/Makefile +++ b/cpu/mpc8xxx/Makefile @@ -11,6 +11,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib8xxx.a COBJS-y += cpu.o +COBJS-$(CONFIG_PCI) += pci_cfg.o SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/cpu/mpc8xxx/pci_cfg.c b/cpu/mpc8xxx/pci_cfg.c new file mode 100644 index 00000000000..9c7d92c4d93 --- /dev/null +++ b/cpu/mpc8xxx/pci_cfg.c @@ -0,0 +1,225 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +struct pci_info { + u16 agent; + u16 cfg; +}; + +/* The agent field is a bit mask in which each bit represents the value of + * cfg_host_agt[] signal and the bit is set of the given interface would be + * in agent/end-point mode for the given interface. + * + * The same idea is true of the cfg field. The bit will be set if the + * interface would be enabled based on the value of cfg_IO_ports[] signal + * + * On MPC86xx/PQ3 based systems: + * we extract cfg_host_agt from GUTS register PORBMSR + * we extract cfg_IO_ports from GUTS register PORDEVSR + * + * cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems + * without PCIe) + */ + +#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8560) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 0) | (1 << 2), + .cfg = 0, + }, +}; +#elif defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 0), + .cfg = 0, + }, +}; +#elif defined(CONFIG_MPC8536) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 5), + .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 3), + .cfg = (1 << 5) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_3] = { + .agent = (1 << 1), + .cfg = (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8544) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 5), + .cfg = (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | + (1 << 6) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 3), + .cfg = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_3] = { + .agent = (1 << 1), + .cfg = (1 << 6) | (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8548) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI_1] = { + .agent = (1 << 4) | (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCI_2] = { + .agent = (1 << 4) | (1 << 6), + .cfg = 0, + }, + /* PCI_2 is always host and we dont use iosel to determine enable/disable */ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 2), + .cfg = (1 << 3) | (1 << 4) | (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8568) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 0) | (1 << 4) | (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 2) | (1 << 4), + .cfg = (1 << 3) | (1 << 4) | (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8569) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 6), + .cfg = (1 << 0) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | + (1 << 8) | (1 << 0xc) | (1 << 0xf), + }, +}; +#elif defined(CONFIG_MPC8572) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5), + .cfg = (1 << 2) | (1 << 3) | (1 << 7) | + (1 << 0xb) | (1 << 0xc) | (1 << 0xf), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6), + .cfg = (1 << 3) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_3] = { + .agent = (1 << 0) | (1 << 3) | (1 << 5) | (1 << 6), + .cfg = (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8610) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI_1] = { + .agent = (1 << 4) | (1 << 5) | (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 2) | (1 << 5), + .cfg = (1 << 1) | (1 << 4), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 0) | (1 << 1) | (1 << 4), + .cfg = (1 << 0) | (1 << 4), + }, +}; +#elif defined(CONFIG_MPC8641) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = 0, /* we dont use agent on 8641 */ + .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) | + (1 << 7) | (1 << 0xe) | (1 << 0xf), + }, +}; +#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 1), + .cfg = (1 << 0) | (1 << 6) | (1 << 0xe) | (1 << 0xf), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 0) | (1 << 2), + .cfg = (1 << 0xe), + }, +}; +#elif defined(CONFIG_P2010) || defined(CONFIG_P2020) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5), + .cfg = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6) | + (1 << 0xd) | (1 << 0xe) | (1 << 0xf), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6), + .cfg = (1 << 2) | (1 << 0xe), + }, + [LAW_TRGT_IF_PCIE_3] = { + .agent = (1 << 0) | (1 << 3) | (1 << 5) | (1 << 6), + .cfg = (1 << 2) | (1 << 4), + }, +}; +#else +#error Need to define pci_config_info for processor +#endif + +int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent) +{ + return ((1 << host_agent) & pci_config_info[trgt].agent); +} + +int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel) +{ + return ((1 << io_sel) & pci_config_info[trgt].cfg); +} -- cgit v1.2.3 From ea8be4a65b18e8e6d41b7c7687280b1071cb9969 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Wed, 2 Sep 2009 13:35:21 +0530 Subject: ppc/85xx,86xx: Handling Unknown SOC version Incase the system is detected with Unknown SVR, let the system boot with a default value and a proper message. Now with dynamic detection of SOC properties from SVR, this is necessary to prevent a crash. Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 10 +++------- cpu/mpc86xx/cpu.c | 5 +---- cpu/mpc8xxx/cpu.c | 5 +++-- 3 files changed, 7 insertions(+), 13 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 6be98dc350c..63bdb6fde1d 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -69,13 +69,9 @@ int checkcpu (void) cpu = gd->cpu; - if (cpu->name) { - puts(cpu->name); - if (IS_E_PROCESSOR(svr)) - puts("E"); - } else { - puts("Unknown"); - } + puts(cpu->name); + if (IS_E_PROCESSOR(svr)) + puts("E"); printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 04409cec68f..e97ab6d8a5b 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -65,10 +65,7 @@ checkcpu(void) cpu = gd->cpu; - if (cpu->name) - puts(cpu->name); - else - puts("Unknown"); + puts(cpu->name); printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); puts("Core: "); diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c index 339f6d97c2b..c73ac3cc6d2 100644 --- a/cpu/mpc8xxx/cpu.c +++ b/cpu/mpc8xxx/cpu.c @@ -79,6 +79,8 @@ struct cpu_type cpu_type_list [] = { #endif }; +struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 1); + struct cpu_type *identify_cpu(u32 ver) { int i; @@ -86,8 +88,7 @@ struct cpu_type *identify_cpu(u32 ver) if (cpu_type_list[i].soc_ver == ver) return &cpu_type_list[i]; } - - return NULL; + return &cpu_type_unknown; } int cpu_numcores() { -- cgit v1.2.3 From ef4025cf61f0bd002d5e5be912b6606cbe48e66c Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Wed, 2 Sep 2009 19:40:36 +0530 Subject: ppc/85xx/86xx: Device tree fixup for number of cores Fixing the number of cores in the device tree based on the actual number of cores on the system. With this same device tree image can be used for dual core and single core members of otherwise exactly same SOC. For example: * P2020RDB and P2010RDB * P1020RDB and P1011RDB * MPC8641D and MPC8641 Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- cpu/mpc85xx/fdt.c | 2 ++ cpu/mpc86xx/fdt.c | 3 +++ cpu/mpc8xxx/Makefile | 1 + cpu/mpc8xxx/fdt.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 61 insertions(+) create mode 100644 cpu/mpc8xxx/fdt.c (limited to 'cpu') diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 8366379ab60..723f473dabf 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -34,6 +34,7 @@ DECLARE_GLOBAL_DATA_PTR; extern void ft_qe_setup(void *blob); +extern void ft_fixup_num_cores(void *blob); #ifdef CONFIG_MP #include "mp.h" @@ -327,6 +328,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_MP ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); #endif + ft_fixup_num_cores(blob); ft_fixup_cache(blob); diff --git a/cpu/mpc86xx/fdt.c b/cpu/mpc86xx/fdt.c index a36ee30c3f0..51f3f4c2203 100644 --- a/cpu/mpc86xx/fdt.c +++ b/cpu/mpc86xx/fdt.c @@ -13,6 +13,8 @@ DECLARE_GLOBAL_DATA_PTR; +extern void ft_fixup_num_cores(void *blob); + void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_MP @@ -54,4 +56,5 @@ void ft_cpu_setup(void *blob, bd_t *bd) if (off < 0) printf("%s: %s\n", __FUNCTION__, fdt_strerror(off)); #endif + ft_fixup_num_cores(blob); } diff --git a/cpu/mpc8xxx/Makefile b/cpu/mpc8xxx/Makefile index 5cb6814403d..481f9e541dc 100644 --- a/cpu/mpc8xxx/Makefile +++ b/cpu/mpc8xxx/Makefile @@ -11,6 +11,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib8xxx.a COBJS-y += cpu.o +COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_PCI) += pci_cfg.o SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) diff --git a/cpu/mpc8xxx/fdt.c b/cpu/mpc8xxx/fdt.c new file mode 100644 index 00000000000..3a9b5841b69 --- /dev/null +++ b/cpu/mpc8xxx/fdt.c @@ -0,0 +1,55 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This file is derived from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c. + * Basically this file contains cpu specific common code for 85xx/86xx + * processors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +void ft_fixup_num_cores(void *blob) { + int off, num_cores, del_cores; + + del_cores = 0; + num_cores = cpu_numcores(); + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + while (off != -FDT_ERR_NOTFOUND) { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + + /* if we find a cpu node outside of what we expect delete it + * and reset the offset back to the start since we can't + * trust the offsets anymore + */ + if (*reg > num_cores-1) { + fdt_del_node(blob, off); + del_cores++; + off = -1; + } + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } + debug ("%x core system found\n", num_cores); + debug ("deleted %d extra core entry entries from device tree\n", + del_cores); +} -- cgit v1.2.3 From 69460868594f2d593774fe82c3b0db19d4a178cb Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Thu, 3 Sep 2009 19:42:40 +0530 Subject: ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu(). While in probecpu() UART is still not initialized. Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 4 ++++ cpu/mpc86xx/cpu.c | 6 ++++++ cpu/mpc8xxx/cpu.c | 6 ------ 3 files changed, 10 insertions(+), 6 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 63bdb6fde1d..8b3810f5b00 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -61,6 +61,10 @@ int checkcpu (void) minor = SVR_MIN(svr); if (cpu_numcores() > 1) { +#ifndef CONFIG_MP + puts("Unicore software on multiprocessor system!!\n" + "To enable mutlticore build define CONFIG_MP\n"); +#endif volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index e97ab6d8a5b..f7e012db573 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -61,6 +61,12 @@ checkcpu(void) major = SVR_MAJ(svr); minor = SVR_MIN(svr); + if (cpu_numcores() > 1) { +#ifndef CONFIG_MP + puts("Unicore software on multiprocessor system!!\n" + "To enable mutlticore build define CONFIG_MP\n"); +#endif + } puts("CPU: "); cpu = gd->cpu; diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c index c73ac3cc6d2..00791e11bd5 100644 --- a/cpu/mpc8xxx/cpu.c +++ b/cpu/mpc8xxx/cpu.c @@ -107,12 +107,6 @@ int probecpu (void) gd->cpu = identify_cpu(ver); -#ifndef CONFIG_MP - if (cpu_numcores() > 1) { - puts("Unicore software on multiprocessor system!!\n" - "To enable mutlticore build define CONFIG_MP\n"); - } -#endif return 0; } -- cgit v1.2.3 From 5079ae4a203c8deb6fe58584ef151d5113ea1b54 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 8 Sep 2009 13:46:46 -0500 Subject: ppc/85xx: Clean up do_reset There is no reason to do a run time check for e500 v1 based cores to determine if we have the GUTs RSTCR facility. Only the first generation of PQ3 parts (MPC8540/41/55/60) do not have it. So checking to see if we are e500 v2 would miss future parts (like e500mc). Just change this to be ifdef'd based on CONFIG_MPC85{40,41,55,60}. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 8b3810f5b00..bdd9ee4c833 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -153,27 +153,15 @@ int checkcpu (void) int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { - uint pvr; - uint ver; +/* Everything after the first generation of PQ3 parts has RSTCR */ +#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) unsigned long val, msr; - pvr = get_pvr(); - ver = PVR_VER(pvr); - - if (ver & 1){ - /* e500 v2 core has reset control register */ - volatile unsigned int * rstcr; - rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0); - *rstcr = 0x2; /* HRESET_REQ */ - udelay(100); - } - /* - * Fallthrough if the code above failed * Initiate hard reset in debug control register DBCR0 - * Make sure MSR[DE] = 1 + * Make sure MSR[DE] = 1. This only resets the core. */ - msr = mfmsr (); msr |= MSR_DE; mtmsr (msr); @@ -181,6 +169,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) val = mfspr(DBCR0); val |= 0x70000000; mtspr(DBCR0,val); +#else + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ + udelay(100); +#endif return 1; } -- cgit v1.2.3 From bbff2d2861a1210cc6ab2a871cdd82f195905b2f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Sep 2009 11:40:41 -0500 Subject: ppc/85xx: Introduce RESET_VECTOR_ADDRESS to handle non-standard link address Some board ports place TEXT_BASE at a location that would cause the RESET_VECTOR_ADDRESS not to be at 0xfffffffc when we link. By default we assume RESET_VECTOR_ADDRESS will be 0xfffffffc if the board doesn't explicitly set it. Signed-off-by: Kumar Gala Acked-by: Wolfgang Denk --- cpu/mpc85xx/u-boot.lds | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/u-boot.lds b/cpu/mpc85xx/u-boot.lds index d6e22a7210e..ec4787157cc 100644 --- a/cpu/mpc85xx/u-boot.lds +++ b/cpu/mpc85xx/u-boot.lds @@ -20,6 +20,10 @@ * MA 02111-1307 USA */ +#ifndef RESET_VECTOR_ADDRESS +#define RESET_VECTOR_ADDRESS 0xfffffffc +#endif + OUTPUT_ARCH(powerpc) /* Do we need any of these for elf? __DYNAMIC = 0; */ @@ -116,17 +120,17 @@ SECTIONS . = ALIGN(256); __init_end = .; - .bootpg ADDR(.text) + 0x7f000 : + .bootpg RESET_VECTOR_ADDRESS - 0xffc : { cpu/mpc85xx/start.o (.bootpg) } :text = 0xffff - .resetvec ADDR(.text) + 0x7fffc : + .resetvec RESET_VECTOR_ADDRESS : { *(.resetvec) } :text = 0xffff - . = ADDR(.text) + 0x80000; + . = RESET_VECTOR_ADDRESS + 0x4; __bss_start = .; .bss (NOLOAD) : -- cgit v1.2.3 From 247eeb98a8b1582ea33dbb78d2cf48124299ddf8 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Mon, 7 Sep 2009 17:00:40 +0200 Subject: ppc4xx: Allow overwriting pci target registers for all 4xx boards This patch adds the CONFIG_PCI_4xx_PTM_OVERWRITE option and replaces the ugly 'if defined(BOARD1) || ... || defined(BOARDn)' construct in 4xx pci code. When CONFIG_PCI_4xx_PTM_OVERWRITE is defined the default ptm register setup can be overwritten through environment variables ptm1la, ptm1ms, ptm2la and ptm2ms to do application specific pci target BAR configuration. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c index 5d7d59c0ea0..184cef5d114 100644 --- a/cpu/ppc4xx/4xx_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -138,7 +138,7 @@ void pci_405gp_init(struct pci_controller *hose) unsigned short temp_short; unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI}; -#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405) +#if defined(CONFIG_PCI_4xx_PTM_OVERWRITE) char *ptmla_str, *ptmms_str; #endif unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA}; @@ -160,7 +160,7 @@ void pci_405gp_init(struct pci_controller *hose) #endif #endif -#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405) +#if defined(CONFIG_PCI_4xx_PTM_OVERWRITE) ptmla_str = getenv("ptm1la"); ptmms_str = getenv("ptm1ms"); if(NULL != ptmla_str && NULL != ptmms_str ) { -- cgit v1.2.3 From ed51257e2a1e0a6e37cfbd2b116a4d674d678db2 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 7 Sep 2009 10:52:24 +0200 Subject: ppc4xx: Fix compilation warning in 4xx miiphy.c This patch fixes the following compilation warning: miiphy.c: In function 'emac4xx_miiphy_read': miiphy.c:353: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Stefan Roese --- cpu/ppc4xx/miiphy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index 6a92bf83648..fa3bfc8d9f5 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -350,7 +350,7 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg, return -1; sta_reg = in_be32((void *)EMAC_STACR + emac_reg); - *value = *(u16 *)(&sta_reg); + *value = sta_reg >> 16; return 0; } -- cgit v1.2.3 From 297a65873d2cb2bd296253af51f59cc1391afbff Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 9 Sep 2009 16:25:29 +0200 Subject: ppc4xx: Big cleanup of PPC4xx defines This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese --- cpu/ppc4xx/40x_spd_sdram.c | 2 +- cpu/ppc4xx/44x_spd_ddr.c | 20 ++++---- cpu/ppc4xx/4xx_pci.c | 10 ++-- cpu/ppc4xx/4xx_uart.c | 28 ++++++------ cpu/ppc4xx/cpu.c | 38 +++++++-------- cpu/ppc4xx/cpu_init.c | 68 +++++++++++++-------------- cpu/ppc4xx/fdt.c | 4 +- cpu/ppc4xx/sdram.c | 4 +- cpu/ppc4xx/speed.c | 52 ++++++++++----------- cpu/ppc4xx/start.S | 112 ++++++++++++++++++++++----------------------- cpu/ppc4xx/usbdev.c | 4 +- 11 files changed, 171 insertions(+), 171 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c index 75bd70dc661..83fa709da2d 100644 --- a/cpu/ppc4xx/40x_spd_sdram.c +++ b/cpu/ppc4xx/40x_spd_sdram.c @@ -422,7 +422,7 @@ long int spd_sdram(int(read_spd)(uint addr)) * program all the registers. * -------------------------------------------------------------------*/ -#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) +#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data) /* disable memcontroller so updates work */ mtsdram0( mem_mcopt1, 0 ); diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index f26fcdaa1e9..c93f23a679f 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -192,8 +192,8 @@ long int spd_sdram(void) { /* * Soft-reset SDRAM controller. */ - mtsdr(sdr_srst, SDR0_SRST_DMC); - mtsdr(sdr_srst, 0x00000000); + mtsdr(SDR0_SRST, SDR0_SRST_DMC); + mtsdr(SDR0_SRST, 0x00000000); #endif /* @@ -848,11 +848,11 @@ static int short_mem_test(void) 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}}; for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) { - mtdcr(memcfga, mem_b0cr + (bxcr_num << 2)); - if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { + mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bxcr_num << 2)); + if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { /* Bank is enabled */ membase = (unsigned long*) - (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK); + (mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBA_MASK); /* * Run the short memory test @@ -1086,8 +1086,8 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, * Set the BxCR regs. First, wipe out the bank config registers. */ for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { - mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2)); - mtdcr(memcfgd, 0x00000000); + mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bx_cr_num << 2)); + mtdcr(SDRAM0_CFGDATA, 0x00000000); bank_parms[bx_cr_num].bank_size_bytes = 0; } @@ -1232,12 +1232,12 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, /* Set the SDRAM0_BxCR regs thanks to sort tables */ for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) { - mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2)); - temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | + mtdcr(SDRAM0_CFGADDR, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2)); + temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE); temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) | bank_parms[sorted_bank_num[bx_cr_num]].cr; - mtdcr(memcfgd, temp); + mtdcr(SDRAM0_CFGDATA, temp); bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes; debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp); } diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c index 184cef5d114..e97f32c7b07 100644 --- a/cpu/ppc4xx/4xx_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -100,7 +100,7 @@ int __pci_pre_init(struct pci_controller *hose) * The arbiter is enabled in this place because of * compatibility reasons. */ - mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_ARBIT_EN); + mtdcr(CPC0_PCI, mfdcr(CPC0_PCI) | CPC0_PCI_ARBIT_EN); #endif /* CONFIG_405EP */ return 1; @@ -118,10 +118,10 @@ ushort pmc405_pci_subsys_deviceid(void); int __is_pci_host(struct pci_controller *hose) { #if defined(CONFIG_405GP) - if (mfdcr(strap) & PSR_PCI_ARBIT_EN) + if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN) return 1; #elif defined (CONFIG_405EP) - if (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN) + if (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN) return 1; #endif return 0; @@ -491,7 +491,7 @@ int pci_440_init (struct pci_controller *hose) #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long strap; - mfsdr(sdr_sdstp1,strap); + mfsdr(SDR0_SDSTP1,strap); if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) { printf("PCI: SDR0_STRP1[PISE] not set.\n"); printf("PCI: Configuration aborted.\n"); @@ -500,7 +500,7 @@ int pci_440_init (struct pci_controller *hose) #elif defined(CONFIG_440GP) unsigned long strap; - strap = mfdcr(cpc0_strp1); + strap = mfdcr(CPC0_STRP1); if ((strap & CPC0_STRP1_PISE_MASK) == 0) { printf("PCI: CPC0_STRP1[PISE] not set.\n"); printf("PCI: Configuration aborted.\n"); diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c index 0780624e4a0..8de65425c97 100644 --- a/cpu/ppc4xx/4xx_uart.c +++ b/cpu/ppc4xx/4xx_uart.c @@ -90,7 +90,7 @@ DECLARE_GLOBAL_DATA_PTR; #define CR0_EXTCLK_ENA 0x00600000 #define CR0_UDIV_POS 16 #define UDIV_SUBTRACT 1 -#define UART0_SDR cntrl0 +#define UART0_SDR CPC0_CR0 #define MFREG(a, d) d = mfdcr(a) #define MTREG(a, d) mtdcr(a, d) #else /* #if defined(CONFIG_440GP) */ @@ -99,18 +99,18 @@ DECLARE_GLOBAL_DATA_PTR; #define CR0_EXTCLK_ENA 0x00800000 #define CR0_UDIV_POS 0 #define UDIV_SUBTRACT 0 -#define UART0_SDR sdr_uart0 -#define UART1_SDR sdr_uart1 +#define UART0_SDR SDR0_UART0 +#define UART1_SDR SDR0_UART1 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define UART2_SDR sdr_uart2 +#define UART2_SDR SDR0_UART2 #endif #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define UART3_SDR sdr_uart3 +#define UART3_SDR SDR0_UART3 #endif #define MFREG(a, d) mfsdr(a, d) #define MTREG(a, d) mtsdr(a, d) @@ -130,8 +130,8 @@ DECLARE_GLOBAL_DATA_PTR; #define CR0_EXTCLK_ENA 0x00800000 #define CR0_UDIV_POS 0 #define UDIV_SUBTRACT 0 -#define UART0_SDR sdr_uart0 -#define UART1_SDR sdr_uart1 +#define UART0_SDR SDR0_UART0 +#define UART1_SDR SDR0_UART1 #else /* CONFIG_405GP || CONFIG_405CR */ #define UART0_BASE 0xef600300 #define UART1_BASE 0xef600400 @@ -282,7 +282,7 @@ static void serial_divs (int baudrate, unsigned long *pudiv, u32 reg; /* check the pll feedback source */ - mfcpr(cprpllc, cpr_pllc); + mfcpr(CPR0_PLLC, cpr_pllc); get_sys_info(&sysinfo); @@ -312,10 +312,10 @@ static void serial_divs (int baudrate, unsigned long *pudiv, } *pudiv = udiv; - mfcpr(cprperd0, reg); + mfcpr(CPC0_PERD0, reg); reg &= ~0x0000ffff; reg |= ((udiv - 0) << 8) | (udiv - 0); - mtcpr(cprperd0, reg); + mtcpr(CPC0_PERD0, reg); *pbdiv = div / udiv; } #endif /* defined(CONFIG_440) && !defined(CONFIG_SYS_EXT_SERIAL_CLK) */ @@ -412,7 +412,7 @@ int serial_init_dev (unsigned long base) clk = tmp = reg = 0; #else #ifdef CONFIG_405EP - reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK); + reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK); clk = gd->cpu_clk; tmp = CONFIG_SYS_BASE_BAUD * 16; udiv = (clk + tmp / 2) / tmp; @@ -420,9 +420,9 @@ int serial_init_dev (unsigned long base) udiv = UDIV_MAX; reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */ reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */ - mtdcr (cpc0_ucr, reg); + mtdcr (CPC0_UCR, reg); #else /* CONFIG_405EP */ - reg = mfdcr(cntrl0) & ~CR0_MASK; + reg = mfdcr(CPC0_CR0) & ~CR0_MASK; #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK clk = CONFIG_SYS_EXT_SERIAL_CLOCK; udiv = 1; @@ -439,7 +439,7 @@ int serial_init_dev (unsigned long base) #endif #endif reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ - mtdcr (cntrl0, reg); + mtdcr (CPC0_CR0, reg); #endif /* CONFIG_405EP */ tmp = gd->baudrate * udiv * 16; bdiv = (clk + tmp / 2) / tmp; diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index e9861abe762..22879046694 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -64,7 +64,7 @@ int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num"))); static int pci_async_enabled(void) { #if defined(CONFIG_405GP) - return (mfdcr(strap) & PSR_PCI_ASYNC_EN); + return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN); #endif #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ @@ -72,7 +72,7 @@ static int pci_async_enabled(void) defined(CONFIG_460EX) || defined(CONFIG_460GT) unsigned long val; - mfsdr(sdr_sdstp1, val); + mfsdr(SDR0_SDSTP1, val); return (val & SDR0_SDSTP1_PAME_MASK); #endif } @@ -84,21 +84,21 @@ static int pci_async_enabled(void) static int pci_arbiter_enabled(void) { #if defined(CONFIG_405GP) - return (mfdcr(strap) & PSR_PCI_ARBIT_EN); + return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN); #endif #if defined(CONFIG_405EP) - return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN); + return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN); #endif #if defined(CONFIG_440GP) - return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK); + return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK); #endif #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long val; - mfsdr(sdr_xcr, val); + mfsdr(SDR0_XCR, val); return (val & 0x80000000); #endif #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ @@ -106,7 +106,7 @@ static int pci_arbiter_enabled(void) defined(CONFIG_460EX) || defined(CONFIG_460GT) unsigned long val; - mfsdr(sdr_pci0, val); + mfsdr(SDR0_PCI0, val); return (val & 0x80000000); #endif } @@ -118,11 +118,11 @@ static int pci_arbiter_enabled(void) static int i2c_bootrom_enabled(void) { #if defined(CONFIG_405EP) - return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP); + return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP); #else unsigned long val; - mfsdr(sdr_sdcs, val); + mfsdr(SDR0_SDCS0, val); return (val & SDR0_SDCS_SDD); #endif } @@ -256,7 +256,7 @@ static int bootstrap_option(void) { unsigned long val; - mfsdr(SDR_PINSTP, val); + mfsdr(SDR0_PINSTP, val); return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT); } #endif /* SDR0_PINSTP_SHIFT */ @@ -265,13 +265,13 @@ static int bootstrap_option(void) #if defined(CONFIG_440) static int do_chip_reset (unsigned long sys0, unsigned long sys1) { - /* Changes to cpc0_sys0 and cpc0_sys1 require chip + /* Changes to CPC0_SYS0 and CPC0_SYS1 require chip * reset. */ - mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */ - mtdcr (cpc0_sys0, sys0); - mtdcr (cpc0_sys1, sys1); - mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */ + mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */ + mtdcr (CPC0_SYS0, sys0); + mtdcr (CPC0_SYS1, sys1); + mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */ mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */ return 1; @@ -410,13 +410,13 @@ int checkcpu (void) case PVR_440GP_RB: puts("GP Rev. B"); /* See errata 1.12: CHIP_4 */ - if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) || - (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){ + if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) || + (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){ puts ( "\n\t CPC0_SYSx DCRs corrupted. " "Resetting chip ...\n"); udelay( 1000 * 1000 ); /* Give time for serial buf to clear */ - do_chip_reset ( mfdcr(cpc0_strp0), - mfdcr(cpc0_strp1) ); + do_chip_reset ( mfdcr(CPC0_STRP0), + mfdcr(CPC0_STRP1) ); } break; diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 65092fb8e47..bd06b9bc22c 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -58,17 +58,17 @@ void reconfigure_pll(u32 new_cpu_freq) target_perdv0 = 4; target_spcid0 = 4; - mfcpr(clk_primbd, reg); + mfcpr(CPR0_PRIMBD, reg); temp = (reg & PRBDV_MASK) >> 24; prbdv0 = temp ? temp : 8; if (prbdv0 != target_prbdv0) { reg &= ~PRBDV_MASK; reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24); - mtcpr(clk_primbd, reg); + mtcpr(CPR0_PRIMBD, reg); reset_needed = 1; } - mfcpr(clk_plld, reg); + mfcpr(CPR0_PLLD, reg); temp = (reg & PLLD_FWDVA_MASK) >> 16; fwdva = temp ? temp : 16; @@ -89,35 +89,35 @@ void reconfigure_pll(u32 new_cpu_freq) ((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) | ((target_fbdv == 32 ? 0 : target_fbdv) << 24) | (target_lfbdv == 64 ? 0 : target_lfbdv); - mtcpr(clk_plld, reg); + mtcpr(CPR0_PLLD, reg); reset_needed = 1; } - mfcpr(clk_perd, reg); + mfcpr(CPR0_PERD, reg); perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24; if (perdv0 != target_perdv0) { reg &= ~CPR0_PERD_PERDV0_MASK; reg |= (target_perdv0 << 24); - mtcpr(clk_perd, reg); + mtcpr(CPR0_PERD, reg); reset_needed = 1; } - mfcpr(clk_spcid, reg); + mfcpr(CPR0_SPCID, reg); temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24; spcid0 = temp ? temp : 4; if (spcid0 != target_spcid0) { reg &= ~CPR0_SPCID_SPCIDV0_MASK; reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24); - mtcpr(clk_spcid, reg); + mtcpr(CPR0_SPCID, reg); reset_needed = 1; } /* Set reload inhibit so configuration will persist across * processor resets */ - mfcpr(clk_icfg, reg); + mfcpr(CPR0_ICFG, reg); reg &= ~CPR0_ICFG_RLI_MASK; reg |= 1 << 31; - mtcpr(clk_icfg, reg); + mtcpr(CPR0_ICFG, reg); } /* Reset processor if configuration changed */ @@ -173,7 +173,7 @@ cpu_init_f (void) /* * Set EMAC noise filter bits */ - mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); + mtdcr(CPC0_EPCTL, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); #endif /* CONFIG_405EP */ #if defined(CONFIG_SYS_4xx_GPIO_TABLE) @@ -204,43 +204,43 @@ cpu_init_f (void) asm volatile("2: bdnz 2b" ::: "ctr", "cr0"); #endif - mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP); - mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR); + mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP); + mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR); #endif #if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1)) - mtebc(pb1ap, CONFIG_SYS_EBC_PB1AP); - mtebc(pb1cr, CONFIG_SYS_EBC_PB1CR); + mtebc(PB1AP, CONFIG_SYS_EBC_PB1AP); + mtebc(PB1CR, CONFIG_SYS_EBC_PB1CR); #endif #if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2)) - mtebc(pb2ap, CONFIG_SYS_EBC_PB2AP); - mtebc(pb2cr, CONFIG_SYS_EBC_PB2CR); + mtebc(PB2AP, CONFIG_SYS_EBC_PB2AP); + mtebc(PB2CR, CONFIG_SYS_EBC_PB2CR); #endif #if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3)) - mtebc(pb3ap, CONFIG_SYS_EBC_PB3AP); - mtebc(pb3cr, CONFIG_SYS_EBC_PB3CR); + mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); + mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR); #endif #if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4)) - mtebc(pb4ap, CONFIG_SYS_EBC_PB4AP); - mtebc(pb4cr, CONFIG_SYS_EBC_PB4CR); + mtebc(PB4AP, CONFIG_SYS_EBC_PB4AP); + mtebc(PB4CR, CONFIG_SYS_EBC_PB4CR); #endif #if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5)) - mtebc(pb5ap, CONFIG_SYS_EBC_PB5AP); - mtebc(pb5cr, CONFIG_SYS_EBC_PB5CR); + mtebc(PB5AP, CONFIG_SYS_EBC_PB5AP); + mtebc(PB5CR, CONFIG_SYS_EBC_PB5CR); #endif #if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6)) - mtebc(pb6ap, CONFIG_SYS_EBC_PB6AP); - mtebc(pb6cr, CONFIG_SYS_EBC_PB6CR); + mtebc(PB6AP, CONFIG_SYS_EBC_PB6AP); + mtebc(PB6CR, CONFIG_SYS_EBC_PB6CR); #endif #if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7)) - mtebc(pb7ap, CONFIG_SYS_EBC_PB7AP); - mtebc(pb7cr, CONFIG_SYS_EBC_PB7CR); + mtebc(PB7AP, CONFIG_SYS_EBC_PB7AP); + mtebc(PB7CR, CONFIG_SYS_EBC_PB7CR); #endif #if defined (CONFIG_SYS_EBC_CFG) @@ -276,9 +276,9 @@ cpu_init_f (void) * Compatibility mode and Ethernet Clock select are not * correct in the manual */ - mfsdr(sdr_mfr, val); + mfsdr(SDR0_MFR, val); val &= ~0x10000000; - mtsdr(sdr_mfr,val); + mtsdr(SDR0_MFR,val); #endif /* CONFIG_440GX */ #if defined(CONFIG_460EX) @@ -304,10 +304,10 @@ cpu_init_f (void) /* * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read */ - mtdcr(plb0_acr, (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) | - plb0_acr_rdp_4deep); - mtdcr(plb1_acr, (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) | - plb1_acr_rdp_4deep); + mtdcr(PLB0_ACR, (mfdcr(PLB0_ACR) & ~PLB0_ACR_RDP_MASK) | + PLB0_ACR_RDP_4DEEP); + mtdcr(PLB1_ACR, (mfdcr(PLB1_ACR) & ~PLB1_ACR_RDP_MASK) | + PLB1_ACR_RDP_4DEEP); #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */ } @@ -324,7 +324,7 @@ int cpu_init_r (void) * for compatibility to existing PPC405GP designs. */ if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) { - mtdcr(ecr, 0x60606000); + mtdcr(CPC0_ECR, 0x60606000); } #endif /* defined(CONFIG_405GP) */ diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c index ba5c120ad7f..496e0285b5b 100644 --- a/cpu/ppc4xx/fdt.c +++ b/cpu/ppc4xx/fdt.c @@ -51,8 +51,8 @@ void __ft_board_setup(void *blob, bd_t *bd) * peripheral banks into the OPB/PLB address space */ for (i = 0; i < EBC_NUM_BANKS; i++) { - mtdcr(ebccfga, EBC_BXCR(i)); - bxcr = mfdcr(ebccfgd); + mtdcr(EBC0_CFGADDR, EBC_BXCR(i)); + bxcr = mfdcr(EBC0_CFGDATA); if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) { *p++ = i; diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index 4365df9879d..5a3336e3c8a 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -375,8 +375,8 @@ phys_size_t initdram(int board_type) /* * Soft-reset SDRAM controller. */ - mtsdr(sdr_srst, SDR0_SRST_DMC); - mtsdr(sdr_srst, 0x00000000); + mtsdr(SDR0_SRST, SDR0_SRST_DMC); + mtsdr(SDR0_SRST, 0x00000000); #endif for (i=0; i> 4); sysInfo->pllFwdDivA = get_cpr0_fwdv(temp); @@ -342,7 +342,7 @@ void get_sys_info (sys_info_t *sysInfo) */ /* Decode CPR0_PLLD0 for divisors */ - mfcpr(clk_plld, reg); + mfcpr(CPR0_PLLD, reg); temp = (reg & PLLD_FWDVA_MASK) >> 16; sysInfo->pllFwdDivA = temp ? temp : 16; temp = (reg & PLLD_FWDVB_MASK) >> 8; @@ -351,28 +351,28 @@ void get_sys_info (sys_info_t *sysInfo) sysInfo->pllFbkDiv = temp ? temp : 32; lfdiv = reg & PLLD_LFBDV_MASK; - mfcpr(clk_opbd, reg); + mfcpr(CPR0_OPBD, reg); temp = (reg & OPBDDV_MASK) >> 24; sysInfo->pllOpbDiv = temp ? temp : 4; - mfcpr(clk_perd, reg); + mfcpr(CPR0_PERD, reg); temp = (reg & PERDV_MASK) >> 24; sysInfo->pllExtBusDiv = temp ? temp : 8; - mfcpr(clk_primbd, reg); + mfcpr(CPR0_PRIMBD, reg); temp = (reg & PRBDV_MASK) >> 24; prbdv0 = temp ? temp : 8; - mfcpr(clk_spcid, reg); + mfcpr(CPR0_SPCID, reg); temp = (reg & SPCID_MASK) >> 24; sysInfo->pllPciDiv = temp ? temp : 4; /* Calculate 'M' based on feedback source */ - mfsdr(sdr_sdstp0, reg); + mfsdr(SDR0_SDSTP0, reg); temp = (reg & PLLSYS0_SEL_MASK) >> 27; if (temp == 0) { /* PLL output */ /* Figure which pll to use */ - mfcpr(clk_pllc, reg); + mfcpr(CPR0_PLLC, reg); temp = (reg & PLLC_SRC_MASK) >> 29; if (!temp) /* PLLOUTA */ m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA; @@ -426,7 +426,7 @@ void get_sys_info (sys_info_t * sysInfo) unsigned long m; /* Extract configured divisors */ - strp0 = mfdcr( cpc0_strp0 ); + strp0 = mfdcr( CPC0_STRP0 ); sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15); sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12); temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18; @@ -484,8 +484,8 @@ void get_sys_info (sys_info_t * sysInfo) #endif /* Extract configured divisors */ - mfsdr( sdr_sdstp0,strp0 ); - mfsdr( sdr_sdstp1,strp1 ); + mfsdr( SDR0_SDSTP0,strp0 ); + mfsdr( SDR0_SDSTP1,strp1 ); temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8); sysInfo->pllFwdDivA = temp ? temp : 16 ; @@ -531,7 +531,7 @@ void get_sys_info (sys_info_t * sysInfo) /* Determine PCI Clock Period */ pci_clock_per = determine_pci_clock_per(); sysInfo->freqPCI = (ONE_BILLION/pci_clock_per) * 1000; - mfsdr(sdr_ddr0, sdr_ddrpll); + mfsdr(SDR0_DDR0, sdr_ddrpll); sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll)); #endif @@ -794,8 +794,8 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) /* * Read PLL Mode registers */ - pllmr0 = mfdcr (cpc0_pllmr0); - pllmr1 = mfdcr (cpc0_pllmr1); + pllmr0 = mfdcr (CPC0_PLLMR0); + pllmr1 = mfdcr (CPC0_PLLMR1); /* * Determine forward divider A @@ -918,8 +918,8 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) /* * Read PLL Mode registers */ - mfcpr(cprplld, cpr_plld); - mfcpr(cprpllc, cpr_pllc); + mfcpr(CPR0_PLLD, cpr_plld); + mfcpr(CPR0_PLLC, cpr_pllc); /* * Determine forward divider A @@ -943,7 +943,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) /* * Read CPR_PRIMAD register */ - mfcpr(cprprimad, cpr_primad); + mfcpr(CPC0_PRIMAD, cpr_primad); /* * Determine PLB_DIV. @@ -1074,7 +1074,7 @@ void get_sys_info (sys_info_t * sysInfo) }; unsigned char sel, cpudv0, plb2xDiv; - mfcpr(cpr0_plld, tmp); + mfcpr(CPR0_PLLD, tmp); /* * Determine forward divider A @@ -1094,29 +1094,29 @@ void get_sys_info (sys_info_t * sysInfo) /* * Determine PERDV0 */ - mfcpr(cpr0_perd, tmp); + mfcpr(CPR0_PERD, tmp); tmp = (tmp >> 24) & 0x03; sysInfo->pllExtBusDiv = (tmp == 0) ? 4 : tmp; /* * Determine OPBDV0 */ - mfcpr(cpr0_opbd, tmp); + mfcpr(CPR0_OPBD, tmp); tmp = (tmp >> 24) & 0x03; sysInfo->pllOpbDiv = (tmp == 0) ? 4 : tmp; /* Determine PLB2XDV0 */ - mfcpr(cpr0_plbd, tmp); + mfcpr(CPR0_PLBD, tmp); tmp = (tmp >> 16) & 0x07; plb2xDiv = (tmp == 0) ? 8 : tmp; /* Determine CPUDV0 */ - mfcpr(cpr0_cpud, tmp); + mfcpr(CPR0_CPUD, tmp); tmp = (tmp >> 24) & 0x07; cpudv0 = (tmp == 0) ? 8 : tmp; /* Determine SEL(5:7) in CPR0_PLLC */ - mfcpr(cpr0_pllc, tmp); + mfcpr(CPR0_PLLC, tmp); sel = (tmp >> 24) & 0x07; /* diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index f967d8464cf..287a912246a 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -83,64 +83,64 @@ #ifdef CONFIG_SYS_INIT_DCACHE_CS # if (CONFIG_SYS_INIT_DCACHE_CS == 0) -# define PBxAP pb0ap -# define PBxCR pb0cr +# define PBxAP PB1AP +# define PBxCR PB0CR # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 1) -# define PBxAP pb1ap -# define PBxCR pb1cr +# define PBxAP PB1AP +# define PBxCR PB1CR # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 2) -# define PBxAP pb2ap -# define PBxCR pb2cr +# define PBxAP PB2AP +# define PBxCR PB2CR # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 3) -# define PBxAP pb3ap -# define PBxCR pb3cr +# define PBxAP PB3AP +# define PBxCR PB3CR # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 4) -# define PBxAP pb4ap -# define PBxCR pb4cr +# define PBxAP PB4AP +# define PBxCR PB4CR # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 5) -# define PBxAP pb5ap -# define PBxCR pb5cr +# define PBxAP PB5AP +# define PBxCR PB5CR # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 6) -# define PBxAP pb6ap -# define PBxCR pb6cr +# define PBxAP PB6AP +# define PBxCR PB6CR # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 7) -# define PBxAP pb7ap -# define PBxCR pb7cr +# define PBxAP PB7AP +# define PBxCR PB7CR # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR @@ -998,7 +998,7 @@ _start: /*----------------------------------------------------------------------- */ addis r3,r0, 0xFFFF /* Clear all existing DMA status */ ori r3,r3, 0xFFFF - mtdcr dmasr, r3 + mtdcr DMASR, r3 bl ppc405ep_init /* do ppc405ep specific init */ #endif /* CONFIG_405EP */ @@ -1015,21 +1015,21 @@ _start: lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ - mtdcr ocmplb3cr1,r3 /* Set PLB Access */ + mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */ ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ - mtdcr ocmplb3cr2,r3 /* Set PLB Access */ + mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */ isync lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ - mtdcr ocmdscr1, r3 /* Set Data Side */ - mtdcr ocmiscr1, r3 /* Set Instruction Side */ + mtdcr OCM0_DSRC1, r3 /* Set Data Side */ + mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */ ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ - mtdcr ocmdscr2, r3 /* Set Data Side */ - mtdcr ocmiscr2, r3 /* Set Instruction Side */ + mtdcr OCM0_DSRC2, r3 /* Set Data Side */ + mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */ addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */ - mtdcr ocmdsisdpc,r3 + mtdcr OCM0_DISDPC,r3 isync #else /* CONFIG_405EZ */ @@ -1039,19 +1039,19 @@ _start: /* Setup OCM */ lis r0, 0x7FFF ori r0, r0, 0xFFFF - mfdcr r3, ocmiscntl /* get instr-side IRAM config */ - mfdcr r4, ocmdscntl /* get data-side IRAM config */ + mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */ + mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */ and r3, r3, r0 /* disable data-side IRAM */ and r4, r4, r0 /* disable data-side IRAM */ - mtdcr ocmiscntl, r3 /* set instr-side IRAM config */ - mtdcr ocmdscntl, r4 /* set data-side IRAM config */ + mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */ + mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */ isync lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l - mtdcr ocmdsarc, r3 + mtdcr OCM0_DSARC, r3 addis r4, 0, 0xC000 /* OCM data area enabled */ - mtdcr ocmdscntl, r4 + mtdcr OCM0_DSCNTL, r4 isync #endif /* CONFIG_405EZ */ #endif @@ -1061,16 +1061,16 @@ _start: /*----------------------------------------------------------------------- */ #ifdef CONFIG_SYS_INIT_DCACHE_CS li r4, PBxAP - mtdcr ebccfga, r4 + mtdcr EBC0_CFGADDR, r4 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l - mtdcr ebccfgd, r4 + mtdcr EBC0_CFGDATA, r4 addi r4, 0, PBxCR - mtdcr ebccfga, r4 + mtdcr EBC0_CFGADDR, r4 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l - mtdcr ebccfgd, r4 + mtdcr EBC0_CFGDATA, r4 /* * Enable the data cache for the 128MB storage access control region @@ -1428,16 +1428,16 @@ relocate_code: /* Restore the EBC parameters */ li r3, PBxAP - mtdcr ebccfga, r3 + mtdcr EBC0_CFGADDR, r3 lis r3, PBxAP_VAL@h ori r3, r3, PBxAP_VAL@l - mtdcr ebccfgd, r3 + mtdcr EBC0_CFGDATA, r3 li r3, PBxCR - mtdcr ebccfga, r3 + mtdcr EBC0_CFGADDR, r3 lis r3, PBxCR_VAL@h ori r3, r3, PBxCR_VAL@l - mtdcr ebccfgd, r3 + mtdcr EBC0_CFGDATA, r3 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ /* Restore registers */ @@ -1860,38 +1860,38 @@ ppc405ep_init: ori r4,r4,CONFIG_SYS_GPIO0_TCR@l stw r4,0(r3) - li r3,pb1ap /* program EBC bank 1 for RTC access */ - mtdcr ebccfga,r3 + li r3,PB1AP /* program EBC bank 1 for RTC access */ + mtdcr EBC0_CFGADDR,r3 lis r3,CONFIG_SYS_EBC_PB1AP@h ori r3,r3,CONFIG_SYS_EBC_PB1AP@l - mtdcr ebccfgd,r3 - li r3,pb1cr - mtdcr ebccfga,r3 + mtdcr EBC0_CFGDATA,r3 + li r3,PB1CR + mtdcr EBC0_CFGADDR,r3 lis r3,CONFIG_SYS_EBC_PB1CR@h ori r3,r3,CONFIG_SYS_EBC_PB1CR@l - mtdcr ebccfgd,r3 + mtdcr EBC0_CFGDATA,r3 - li r3,pb1ap /* program EBC bank 1 for RTC access */ - mtdcr ebccfga,r3 + li r3,PB1AP /* program EBC bank 1 for RTC access */ + mtdcr EBC0_CFGADDR,r3 lis r3,CONFIG_SYS_EBC_PB1AP@h ori r3,r3,CONFIG_SYS_EBC_PB1AP@l - mtdcr ebccfgd,r3 - li r3,pb1cr - mtdcr ebccfga,r3 + mtdcr EBC0_CFGDATA,r3 + li r3,PB1CR + mtdcr EBC0_CFGADDR,r3 lis r3,CONFIG_SYS_EBC_PB1CR@h ori r3,r3,CONFIG_SYS_EBC_PB1CR@l - mtdcr ebccfgd,r3 + mtdcr EBC0_CFGDATA,r3 - li r3,pb4ap /* program EBC bank 4 for FPGA access */ - mtdcr ebccfga,r3 + li r3,PB4AP /* program EBC bank 4 for FPGA access */ + mtdcr EBC0_CFGADDR,r3 lis r3,CONFIG_SYS_EBC_PB4AP@h ori r3,r3,CONFIG_SYS_EBC_PB4AP@l - mtdcr ebccfgd,r3 - li r3,pb4cr - mtdcr ebccfga,r3 + mtdcr EBC0_CFGDATA,r3 + li r3,PB4CR + mtdcr EBC0_CFGADDR,r3 lis r3,CONFIG_SYS_EBC_PB4CR@h ori r3,r3,CONFIG_SYS_EBC_PB4CR@l - mtdcr ebccfgd,r3 + mtdcr EBC0_CFGDATA,r3 #endif /* diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c index faf7f0878ff..5bb4f3ce632 100644 --- a/cpu/ppc4xx/usbdev.c +++ b/cpu/ppc4xx/usbdev.c @@ -206,14 +206,14 @@ void usb_dev_init() #ifdef USB_2_0_DEVICE printf("USB 2.0 Device init\n"); /*select 2.0 device */ - mtsdr(sdr_usb0, 0x0); /* 2.0 */ + mtsdr(SDR0_USB0, 0x0); /* 2.0 */ /*usb dev init */ *(unsigned char *)USB2D0_POWER_8 = 0xa1; /* 2.0 */ #else printf("USB 1.1 Device init\n"); /*select 1.1 device */ - mtsdr(sdr_usb0, 0x2); /* 1.1 */ + mtsdr(SDR0_USB0, 0x2); /* 1.1 */ /*usb dev init */ *(unsigned char *)USB2D0_POWER_8 = 0xc0; /* 1.1 */ -- cgit v1.2.3 From 3477bda1f5944a7e97918917c63d56dc144e1a51 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Thu, 20 Aug 2009 17:44:20 -0500 Subject: ppc/85xx: Don't enable interrupts before we're ready We cannot handle any exceptions while running in AS1, as the exceptions will transition back to AS0 without a valid mapping. Signed-off-by: Scott Wood --- cpu/mpc85xx/start.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index e21a4eb8767..eaed0e0be5f 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -278,8 +278,8 @@ _start_e500: msync tlbwe - lis r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@h - ori r6,r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@l + lis r6,MSR_IS|MSR_DS@h + ori r6,r6,MSR_IS|MSR_DS@l lis r7,switch_as@h ori r7,r7,switch_as@l -- cgit v1.2.3 From eea886da9a7f4fc2cb27952ce460e9daae98d2d0 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Thu, 20 Aug 2009 17:45:05 -0500 Subject: ppc/85xx: Ensure that MAS8 is zero when writing TLB entries. Its reset value is random, and we sometimes read uninitialized TLB arrays. Make sure that we don't retain MAS8 from reading such an entry if the VF bit in MAS8 is set, attempts to use the mapping will trap. Signed-off-by: Scott Wood --- cpu/mpc85xx/start.S | 4 ++++ cpu/mpc85xx/tlb.c | 3 +++ 2 files changed, 7 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index eaed0e0be5f..7a23b4f811d 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -156,6 +156,10 @@ _start_e500: mtspr MCSR,r0 /* machine check syndrome register */ mtxer r0 /* clear integer exception register */ +#ifdef CONFIG_SYS_BOOK3E_HV + mtspr MAS8,r0 /* make sure MAS8 is clear */ +#endif + /* Enable Time Base and Select Time Base Clock */ lis r0,HID0_EMCP@h /* Enable machine check */ #if defined(CONFIG_ENABLE_36BIT_PHYS) diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 0497a29ba83..03c2449b5c3 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -50,6 +50,9 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn, mtspr(MAS3, _mas3); #ifdef CONFIG_ENABLE_36BIT_PHYS mtspr(MAS7, _mas7); +#endif +#ifdef CONFIG_SYS_BOOK3E_HV + mtspr(MAS8, 0); #endif asm volatile("isync;msync;tlbwe;isync"); -- cgit v1.2.3 From f761439418f589e16804061edeb848c8ae497091 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Thu, 20 Aug 2009 17:45:00 -0500 Subject: ppc/85xx: Remove some bogus code from external interrupt handler. Skipping the interrupted instruction will accomplish nothing other than turning a spurious interrupt into a crash. External interrupts are not machine checks, so don't count them as such. Signed-off-by: Scott Wood --- cpu/mpc85xx/traps.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c index 1045cc1e7d0..9d16b9b55e7 100644 --- a/cpu/mpc85xx/traps.c +++ b/cpu/mpc85xx/traps.c @@ -287,6 +287,7 @@ UnknownException(struct pt_regs *regs) regs->nip, regs->msr, regs->trap); _exception(0, regs); } + void ExtIntException(struct pt_regs *regs) { @@ -305,14 +306,6 @@ ExtIntException(struct pt_regs *regs) printf(" irq IACK0@%05x=%d\n",(int)&pic->iack0,vect); show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); - machinecheck_count++; -#ifdef EXTINT_NOSKIP - printf("Returning back to 0x%08x\n",regs->nip); -#else - regs->nip += 4; /* skip offending instruction */ - printf("Skipping current instr, Returning to 0x%08lx\n",regs->nip); -#endif - } void -- cgit v1.2.3 From 6690dcc173f8de080f23a8db2d169f2ff2eec1a1 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 10 Sep 2009 14:54:55 -0500 Subject: ppc/8xxx: Misc DDR related fixes * Fix setting of ESDMODE (MR1) register - the bit shifting was wrong * Fix the format string to match size in a debug print Signed-off-by: Kumar Gala --- cpu/mpc8xxx/ddr/ctrl_regs.c | 10 +++++----- cpu/mpc8xxx/ddr/ddr3_dimm_params.c | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 5e63c5df3ad..25050414504 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -675,12 +675,12 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, esdmode = (0 | ((qoff & 0x1) << 12) | ((tdqs_en & 0x1) << 11) - | ((rtt & 0x4) << 9) /* rtt field is split */ + | ((rtt & 0x4) << 7) /* rtt field is split */ | ((wrlvl_en & 0x1) << 7) - | ((rtt & 0x2) << 6) /* rtt field is split */ - | ((dic & 0x2) << 5) /* DIC field is split */ + | ((rtt & 0x2) << 5) /* rtt field is split */ + | ((dic & 0x2) << 4) /* DIC field is split */ | ((al & 0x3) << 3) - | ((rtt & 0x1) << 2) /* rtt field is split */ + | ((rtt & 0x1) << 2) /* rtt field is split */ | ((dic & 0x1) << 1) /* DIC field is split */ | ((dll_en & 0x1) << 0) ); diff --git a/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/cpu/mpc8xxx/ddr/ddr3_dimm_params.c index 13d234e9331..d4199baa82c 100644 --- a/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/cpu/mpc8xxx/ddr/ddr3_dimm_params.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * Dave Liu * * calculate the organization and timing parameter @@ -71,7 +71,7 @@ compute_ranksize(const ddr3_spd_eeprom_t *spd) bsize = 1ULL << (nbit_sdram_cap_bsize - 3 + nbit_primary_bus_width - nbit_sdram_width); - debug("DDR: DDR III rank density = 0x%08x\n", bsize); + debug("DDR: DDR III rank density = 0x%16lx\n", bsize); return bsize; } -- cgit v1.2.3 From ccea800346cbf4f5217dbd37256bf7ae21162473 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 11 Sep 2009 11:27:00 -0500 Subject: ppc/85xx: Introduce low level write_tlb function Factor out the code we use to actually write a tlb entry. set_tlb is a logical view of the TLB while write_tlb is a low level matching the MAS registers. Signed-off-by: Kumar Gala --- cpu/mpc85xx/start.S | 24 +++++++++++++++++++++++- cpu/mpc85xx/tlb.c | 16 +++------------- 2 files changed, 26 insertions(+), 14 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 7a23b4f811d..eeee7a9764c 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007 Freescale Semiconductor. + * Copyright 2004, 2007-2009 Freescale Semiconductor. * Copyright (C) 2003 Motorola,Inc. * * See file CREDITS for list of people who contributed to this @@ -820,6 +820,28 @@ in32r: /*------------------------------------------------------------------------------*/ +/* + * void write_tlb(mas0, mas1, mas2, mas3, mas7) + */ + .globl write_tlb +write_tlb: + mtspr MAS0,r3 + mtspr MAS1,r4 + mtspr MAS2,r5 + mtspr MAS3,r6 +#ifdef CONFIG_ENABLE_36BIT_PHYS + mtspr MAS7,r7 +#endif + li r3,0 +#ifdef CONFIG_SYS_BOOK3E_HV + mtspr MAS8,r3 +#endif + isync + tlbwe + msync + isync + blr + /* * void relocate_code (addr_sp, gd, addr_moni) * diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 03c2449b5c3..d39712a5135 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -42,19 +42,9 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn, _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize); _mas2 = FSL_BOOKE_MAS2(epn, wimge); _mas3 = FSL_BOOKE_MAS3(rpn, 0, perms); - _mas7 = rpn >> 32; + _mas7 = FSL_BOOKE_MAS7(rpn); - mtspr(MAS0, _mas0); - mtspr(MAS1, _mas1); - mtspr(MAS2, _mas2); - mtspr(MAS3, _mas3); -#ifdef CONFIG_ENABLE_36BIT_PHYS - mtspr(MAS7, _mas7); -#endif -#ifdef CONFIG_SYS_BOOK3E_HV - mtspr(MAS8, 0); -#endif - asm volatile("isync;msync;tlbwe;isync"); + write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7); #ifdef CONFIG_ADDR_MAP if ((tlb == 1) && (gd->flags & GD_FLG_RELOC)) -- cgit v1.2.3 From b855dc47debf775c0bfd9fef4e9604ca7a5a6e9f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 11 Sep 2009 11:30:30 -0500 Subject: ppc/85xx: Repack tlb_table to save space We can pack the initial tlb_table in MAS register format and use write_tlb to set things up. This savings can be helpful for NAND style first stage boot loaders. Signed-off-by: Kumar Gala --- cpu/mpc85xx/tlb.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index d39712a5135..f87a10d4f40 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -90,10 +90,11 @@ void init_tlbs(void) int i; for (i = 0; i < num_tlb_entries; i++) { - set_tlb(tlb_table[i].tlb, tlb_table[i].epn, tlb_table[i].rpn, - tlb_table[i].perms, tlb_table[i].wimge, - tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize, - tlb_table[i].iprot); + write_tlb(tlb_table[i].mas0, + tlb_table[i].mas1, + tlb_table[i].mas2, + tlb_table[i].mas3, + tlb_table[i].mas7); } return ; -- cgit v1.2.3 From 8d82308305832441c12d1aebdb9a4a9bcc517724 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 11 Sep 2009 12:32:01 -0500 Subject: ppc/85xx: Move code around to prep for NAND_SPL If we move some of the functions in tlb.c around we need less ifdefs. The first stage loader just needs invalidate_tlb and init_tlbs. Signed-off-by: Kumar Gala --- cpu/mpc85xx/tlb.c | 46 +++++++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 23 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index f87a10d4f40..44e80b1b745 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -32,6 +32,29 @@ DECLARE_GLOBAL_DATA_PTR; +void invalidate_tlb(u8 tlb) +{ + if (tlb == 0) + mtspr(MMUCSR0, 0x4); + if (tlb == 1) + mtspr(MMUCSR0, 0x2); +} + +void init_tlbs(void) +{ + int i; + + for (i = 0; i < num_tlb_entries; i++) { + write_tlb(tlb_table[i].mas0, + tlb_table[i].mas1, + tlb_table[i].mas2, + tlb_table[i].mas3, + tlb_table[i].mas7); + } + + return ; +} + void set_tlb(u8 tlb, u32 epn, u64 rpn, u8 perms, u8 wimge, u8 ts, u8 esel, u8 tsize, u8 iprot) @@ -77,29 +100,6 @@ void disable_tlb(u8 esel) #endif } -void invalidate_tlb(u8 tlb) -{ - if (tlb == 0) - mtspr(MMUCSR0, 0x4); - if (tlb == 1) - mtspr(MMUCSR0, 0x2); -} - -void init_tlbs(void) -{ - int i; - - for (i = 0; i < num_tlb_entries; i++) { - write_tlb(tlb_table[i].mas0, - tlb_table[i].mas1, - tlb_table[i].mas2, - tlb_table[i].mas3, - tlb_table[i].mas7); - } - - return ; -} - static void tlbsx (const volatile unsigned *addr) { __asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr)); -- cgit v1.2.3 From 9f3243612ca29c40a55ab0c3927e072349690610 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Fri, 11 Sep 2009 14:19:10 +0800 Subject: ppc/85xx: add boot from NAND/eSDHC/eSPI support The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch implements these three bootup methods in a unified way - all of these use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM which lets us use the SPD to initialize the SDRAM. For all three bootup methods, the bootup process can be divided into two stages: the first stage will initialize the corresponding controller, configure the L2SRAM, then copy the second stage image to L2SRAM and jump to it. The second stage image is just like the general U-Boot image to configure all the hardware and boot up to U-Boot command line. When boot from NAND, the eLBC controller will first load the first stage image to internal 4K RAM buffer because it's also stored on the NAND flash. The first stage image, also call 4K NAND loader, will initialize the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K NAND loader's code comes from the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. When boot from eSDHC/eSPI, there's no such a first stage image because the CPU ROM code does the same work. It will initialize the L2SRAM according to the config addr/word pairs on the fixed address and initialize the eSDHC/eSPI controller, then load the second stage image to L2SRAM and jump to it. The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the second stage image for all different bootup methods. It's set in the board config file when one of the bootup methods above is selected. Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu_init.c | 19 ++++++ cpu/mpc85xx/start.S | 23 +++++++- cpu/mpc85xx/tlb.c | 2 + cpu/mpc85xx/u-boot-nand.lds | 138 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 181 insertions(+), 1 deletion(-) create mode 100644 cpu/mpc85xx/u-boot-nand.lds (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index a54cf5d1570..5f6651182b6 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -291,6 +291,25 @@ int cpu_init_r(void) asm("msync;isync"); cache_ctl = l2cache->l2ctl; + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + if (cache_ctl & MPC85xx_L2CTL_L2E) { + /* Clear L2 SRAM memory-mapped base address */ + out_be32(&l2cache->l2srbar0, 0x0); + out_be32(&l2cache->l2srbar1, 0x0); + + /* set MBECCDIS=0, SBECCDIS=0 */ + clrbits_be32(&l2cache->l2errdis, + (MPC85xx_L2ERRDIS_MBECC | + MPC85xx_L2ERRDIS_SBECC)); + + /* set L2E=0, L2SRAM=0 */ + clrbits_be32(&l2cache->l2ctl, + (MPC85xx_L2CTL_L2E | + MPC85xx_L2CTL_L2SRAM_ENTIRE)); + } +#endif + l2siz_field = (cache_ctl >> 28) & 0x3; switch (l2siz_field) { diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index eeee7a9764c..c9e91a90da6 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -57,10 +57,12 @@ GOT_ENTRY(_GOT2_TABLE_) GOT_ENTRY(_FIXUP_TABLE_) +#ifndef CONFIG_NAND_SPL GOT_ENTRY(_start) GOT_ENTRY(_start_of_vectors) GOT_ENTRY(_end_of_vectors) GOT_ENTRY(transfer_to_handler) +#endif GOT_ENTRY(__init_end) GOT_ENTRY(_end) @@ -239,10 +241,11 @@ _start_e500: #endif /* CONFIG_MPC8569 */ - /* create a temp mapping in AS=1 to the 4M boot window */ lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l +#ifndef CONFIG_SYS_RAMBOOT + /* create a temp mapping in AS=1 to the 4M boot window */ lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l @@ -252,6 +255,20 @@ _start_e500: /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l +#else + /* + * create a temp mapping in AS=1 to the 1M TEXT_BASE space, the main + * image has been relocated to TEXT_BASE on the second stage. + */ + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l + + lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l + + lis r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l +#endif mtspr MAS0,r6 mtspr MAS1,r7 @@ -363,6 +380,7 @@ _start_cont: bl board_init_f isync +#ifndef CONFIG_NAND_SPL . = EXC_OFF_SYS_RESET .globl _start_of_vectors _start_of_vectors: @@ -817,6 +835,7 @@ in32: in32r: lwbrx r3,r0,r3 blr +#endif /* !CONFIG_NAND_SPL */ /*------------------------------------------------------------------------------*/ @@ -1001,6 +1020,7 @@ clear_bss: mr r4,r10 /* Destination Address */ bl board_init_r +#ifndef CONFIG_NAND_SPL /* * Copy exception vector code to low memory * @@ -1154,3 +1174,4 @@ setup_ivors: #include "fixed_ivor.S" blr +#endif /* !CONFIG_NAND_SPL */ diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 44e80b1b745..6e94c237ad8 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -55,6 +55,7 @@ void init_tlbs(void) return ; } +#ifndef CONFIG_NAND_SPL void set_tlb(u8 tlb, u32 epn, u64 rpn, u8 perms, u8 wimge, u8 ts, u8 esel, u8 tsize, u8 iprot) @@ -209,3 +210,4 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) */ return memsize_in_meg; } +#endif /* !CONFIG_NAND_SPL */ diff --git a/cpu/mpc85xx/u-boot-nand.lds b/cpu/mpc85xx/u-boot-nand.lds new file mode 100644 index 00000000000..a0fc8f13887 --- /dev/null +++ b/cpu/mpc85xx/u-boot-nand.lds @@ -0,0 +1,138 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.fixup) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) - 0x1000 : + { + cpu/mpc85xx/start.o (.bootpg) + } :text = 0xffff + + . = ADDR(.text) + 0x80000; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} -- cgit v1.2.3 From 168f7cfe562001d5d7c2c724b8232a1dfb2d3463 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 11 Sep 2009 13:41:49 -0500 Subject: ppc/85xx: Change cpu_init_early_f so we can use with NAND SPL Use write_tlb and don't use memset so we can use the same code for cpu_init_early_f between NAND SPL and not. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu_init.c | 34 +++++++++++++++++++++++++--------- 1 file changed, 25 insertions(+), 9 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 5f6651182b6..07856c2a24c 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor. + * Copyright 2007-2009 Freescale Semiconductor, Inc. * * (C) Copyright 2003 Motorola Inc. * Modified by Xianghua Xiao, X.Xiao@motorola.com @@ -132,15 +132,26 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) /* We run cpu_init_early_f in AS = 1 */ void cpu_init_early_f(void) { + u32 mas0, mas1, mas2, mas3, mas7; + int i; + /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); + /* + * Clear initial global data + * we don't use memset so we can share this code with NAND_SPL + */ + for (i = 0; i < sizeof(gd_t); i++) + ((char *)gd)[i] = 0; - set_tlb(0, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 1, 0, BOOKE_PAGESZ_4K, 0); + mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0); + mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K); + mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); + + write_tlb(mas0, mas1, mas2, mas3, mas7); /* set up CCSR if we want it moved */ #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) @@ -149,9 +160,14 @@ void cpu_init_early_f(void) volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); - set_tlb(0, (u32)ccsr_virt, CONFIG_SYS_CCSRBAR_DEFAULT, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 1, 1, BOOKE_PAGESZ_4K, 0); + mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1); + /* mas1 is the same as above */ + mas2 = FSL_BOOKE_MAS2((u32)ccsr_virt, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, + MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT); + + write_tlb(mas0, mas1, mas2, mas3, mas7); temp = in_be32(ccsr_virt); out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12); -- cgit v1.2.3 From 002ebefddcf7589307aec95947f0133fd53958c6 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 11 Sep 2009 13:52:45 -0500 Subject: ppc/85xx: Split out cpu_init_early into its own file for NAND_SPL By pulling out cpu_init_early we can build just it and not all of cpu_init for NAND_SPL. Signed-off-by: Kumar Gala --- cpu/mpc85xx/Makefile | 1 + cpu/mpc85xx/cpu_init.c | 51 ----------------------------- cpu/mpc85xx/cpu_init_early.c | 76 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 77 insertions(+), 51 deletions(-) create mode 100644 cpu/mpc85xx/cpu_init_early.c (limited to 'cpu') diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index a177f427efe..3ef00e85069 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -65,6 +65,7 @@ COBJS-$(CONFIG_CPM2) += serial_scc.o COBJS = $(COBJS-y) COBJS += cpu.o COBJS += cpu_init.o +COBJS += cpu_init_early.o COBJS += interrupts.o COBJS += speed.o COBJS += tlb.o diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 07856c2a24c..48a82eda6d8 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -129,57 +129,6 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) } #endif -/* We run cpu_init_early_f in AS = 1 */ -void cpu_init_early_f(void) -{ - u32 mas0, mas1, mas2, mas3, mas7; - int i; - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - - /* - * Clear initial global data - * we don't use memset so we can share this code with NAND_SPL - */ - for (i = 0; i < sizeof(gd_t); i++) - ((char *)gd)[i] = 0; - - mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0); - mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K); - mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); - mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); - mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); - - write_tlb(mas0, mas1, mas2, mas3, mas7); - - /* set up CCSR if we want it moved */ -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) - { - u32 temp; - volatile u32 *ccsr_virt = - (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); - - mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1); - /* mas1 is the same as above */ - mas2 = FSL_BOOKE_MAS2((u32)ccsr_virt, MAS2_I|MAS2_G); - mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, - MAS3_SW|MAS3_SR); - mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT); - - write_tlb(mas0, mas1, mas2, mas3, mas7); - - temp = in_be32(ccsr_virt); - out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12); - temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR); - } -#endif - - init_laws(); - invalidate_tlb(0); - init_tlbs(); -} - /* * Breathe some life into the CPU... * diff --git a/cpu/mpc85xx/cpu_init_early.c b/cpu/mpc85xx/cpu_init_early.c new file mode 100644 index 00000000000..7886f868f2a --- /dev/null +++ b/cpu/mpc85xx/cpu_init_early.c @@ -0,0 +1,76 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* We run cpu_init_early_f in AS = 1 */ +void cpu_init_early_f(void) +{ + u32 mas0, mas1, mas2, mas3, mas7; + int i; + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + + /* + * Clear initial global data + * we don't use memset so we can share this code with NAND_SPL + */ + for (i = 0; i < sizeof(gd_t); i++) + ((char *)gd)[i] = 0; + + mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0); + mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K); + mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); + + write_tlb(mas0, mas1, mas2, mas3, mas7); + + /* set up CCSR if we want it moved */ +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) + { + u32 temp; + volatile u32 *ccsr_virt = + (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); + + mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1); + /* mas1 is the same as above */ + mas2 = FSL_BOOKE_MAS2((u32)ccsr_virt, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, + MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT); + + write_tlb(mas0, mas1, mas2, mas3, mas7); + + temp = in_be32(ccsr_virt); + out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12); + temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR); + } +#endif + + init_laws(); + invalidate_tlb(0); + init_tlbs(); +} -- cgit v1.2.3 From f8d7b56e003fe19f37d4e9e326df9e9024a052b0 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 11 Sep 2009 15:28:41 -0500 Subject: ppc/85xx: Disable all async interrupt sources when we boot We should make sure to clear MSR[ME, CE, DE] when we boot an OS image since we have changed the exception vectors and the OSes vectors might not be setup we should avoid async interrupts at all costs. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu_init.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 48a82eda6d8..a6d1e999b60 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -364,5 +364,16 @@ extern void setup_ivors(void); void arch_preboot_os(void) { + u32 msr; + + /* + * We are changing interrupt offsets and are about to boot the OS so + * we need to make sure we disable all async interrupts. EE is already + * disabled by the time we get called. + */ + msr = mfmsr(); + msr &= ~(MSR_ME|MSR_CE|MSR_DE); + mtmsr(msr); + setup_ivors(); } -- cgit v1.2.3 From bda4dece03675ad30c098a00f20332010ccb5c5d Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 11 Sep 2009 17:07:55 +0200 Subject: ppc4xx: Fix 405EZ uart base baud calculation With this fix, Linux correctly configures the baudrate when booting with FDT passed from U-Boot to Linux. Signed-off-by: Stefan Roese --- cpu/ppc4xx/speed.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 1f751372cad..9c4bc099044 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -914,6 +914,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ/1000); unsigned long primad_cpudv; unsigned long m; + unsigned long plloutb; /* * Read PLL Mode registers @@ -999,7 +1000,10 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) sysInfo->freqEBC = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / sysInfo->pllExtBusDiv; - sysInfo->freqUART = sysInfo->freqVCOHz; + plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ? + sysInfo->pllFwdDivB : sysInfo->pllFwdDiv) * sysInfo->pllFbkDiv) / + sysInfo->pllFwdDivB); + sysInfo->freqUART = plloutb; } /******************************************** -- cgit v1.2.3 From 012f51e7c1412b2e38b7e8f541889607154b6777 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 14 Sep 2009 11:13:34 +0200 Subject: ppc4xx: Consolidate get_OPB_freq() All 4xx variants had their own, mostly identical get_OPB_freq() function. Some variants even only had the OPB frequency calculated in this routine and not supplied the sys_info.freqOPB variable correctly (e.g. 405EZ). This resulted in incorrect OPB values passed via the FDT to Linux. This patch now removes all those copies and only uses one function for all 4xx variants (except for IOP480 which doesn't have an OPB). Signed-off-by: Stefan Roese --- cpu/ppc4xx/speed.c | 90 +++++++++--------------------------------------------- 1 file changed, 15 insertions(+), 75 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 9c4bc099044..988ba9742d2 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -165,29 +165,12 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) } } + sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv; sysInfo->freqEBC = sysInfo->freqPLB / sysInfo->pllExtBusDiv; - sysInfo->freqUART = sysInfo->freqProcessor; } -/******************************************** - * get_OPB_freq - * return OPB bus freq in Hz - *********************************************/ -ulong get_OPB_freq (void) -{ - ulong val = 0; - - PPC4xx_SYS_INFO sys_info; - - get_sys_info (&sys_info); - val = sys_info.freqPLB / sys_info.pllOpbDiv; - - return val; -} - - /******************************************** * get_PCI_freq * return PCI bus freq in Hz @@ -752,14 +735,6 @@ unsigned long determine_pci_clock_per(void) } #endif -ulong get_OPB_freq (void) -{ - - sys_info_t sys_info; - get_sys_info (&sys_info); - return sys_info.freqOPB; -} - #elif defined(CONFIG_XILINX_405) extern void get_sys_info (sys_info_t * sysInfo); extern ulong get_PCI_freq (void); @@ -874,23 +849,6 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) } -/******************************************** - * get_OPB_freq - * return OPB bus freq in Hz - *********************************************/ -ulong get_OPB_freq (void) -{ - ulong val = 0; - - PPC4xx_SYS_INFO sys_info; - - get_sys_info (&sys_info); - val = sys_info.freqPLB / sys_info.pllOpbDiv; - - return val; -} - - /******************************************** * get_PCI_freq * return PCI bus freq in Hz @@ -997,6 +955,9 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * m) / sysInfo->pllFwdDiv / sysInfo->pllPlbDiv; + sysInfo->freqOPB = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / + sysInfo->pllOpbDiv; + sysInfo->freqEBC = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / sysInfo->pllExtBusDiv; @@ -1006,22 +967,6 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) sysInfo->freqUART = plloutb; } -/******************************************** - * get_OPB_freq - * return OPB bus freq in Hz - *********************************************/ -ulong get_OPB_freq (void) -{ - ulong val = 0; - - PPC4xx_SYS_INFO sys_info; - - get_sys_info (&sys_info); - val = (CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / sys_info.pllOpbDiv; - - return val; -} - #elif defined(CONFIG_405EX) /* @@ -1168,22 +1113,6 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqUART = sysInfo->freqPLB; } -/******************************************** - * get_OPB_freq - * return OPB bus freq in Hz - *********************************************/ -ulong get_OPB_freq (void) -{ - ulong val = 0; - - PPC4xx_SYS_INFO sys_info; - - get_sys_info (&sys_info); - val = sys_info.freqPLB / sys_info.pllOpbDiv; - - return val; -} - #endif int get_clocks (void) @@ -1235,3 +1164,14 @@ ulong get_bus_freq (ulong dummy) return val; } + +#if !defined(CONFIG_IOP480) +ulong get_OPB_freq (void) +{ + PPC4xx_SYS_INFO sys_info; + + get_sys_info (&sys_info); + + return sys_info.freqOPB; +} +#endif -- cgit v1.2.3 From 9efeadc06f054a9486526d003aee127214155a3f Mon Sep 17 00:00:00 2001 From: Rupjyoti Sarmah Date: Mon, 21 Sep 2009 11:26:19 -0700 Subject: ppc4xx: Fix PCIE PLL lock on 440SPe Yucca board u-boot reports a PCIE PLL lock error at boot time on Yucca board, and left PCIe nonfunctional. This is fixed by making u-boot function ppc4xx_init_pcie() to wait 300 uS after negating reset before the first check of the PLL lock. Signed-off-by: Rupjyoti Sarmah Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_pcie.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index 07fbb0e643f..e880c288e1f 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -374,28 +374,35 @@ int ppc4xx_init_pcie(void) /* Set PLL clock receiver to LVPECL */ SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28); - if (check_error()) + if (check_error()) { + printf("ERROR: failed to set PCIe reference clock receiver --" + "PESDR0_PLLLCT1 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT1)); + return -1; + } + + /* Did resistance calibration work? */ + if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) { + printf("ERROR: PCIe resistance calibration failed --" + "PESDR0_PLLLCT2 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT2)); - if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) - { - printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n", - SDR_READ(PESDR0_PLLLCT2)); return -1; } /* De-assert reset of PCIe PLL, wait for lock */ SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24)); - udelay(3); + udelay(300); /* 300 uS is maximum time lock should take */ while (time_out) { if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) { time_out--; - udelay(1); + udelay(20); /* Wait 20 uS more if needed */ } else break; } if (!time_out) { - printf("PCIE: VCO output not locked\n"); + printf("ERROR: PCIe PLL VCO output not locked to ref clock --" + "PESDR0_PLLLCTS=0x%08x\n", SDR_READ(PESDR0_PLLLCT3)); + return -1; } return 0; -- cgit v1.2.3 From 98305c0764a6baf455bbfeb582e24e31e9587bf2 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Tue, 22 Sep 2009 14:53:10 +0800 Subject: ppc/85xx: add ld script file for boot from NAND The first stage 4K image uses a seperate ld script file to generate 4K image. This patch moves it to the cpu/mpc85xx/* to make it avaliable for 85xx platform. Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- cpu/mpc85xx/u-boot-nand_spl.lds | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 cpu/mpc85xx/u-boot-nand_spl.lds (limited to 'cpu') diff --git a/cpu/mpc85xx/u-boot-nand_spl.lds b/cpu/mpc85xx/u-boot-nand_spl.lds new file mode 100644 index 00000000000..fef3e42e09c --- /dev/null +++ b/cpu/mpc85xx/u-boot-nand_spl.lds @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de + * + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + . = 0xfff00000; + .text : { + *(.text) + } + _etext = .; + + .reloc : { + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + . = ALIGN(8); + .data : { + *(.rodata*) + *(.data*) + *(.sdata*) + } + _edata = .; + + . = ALIGN(8); + __init_begin = .; + __init_end = .; + + .resetvec ADDR(.text) + 0xffc : { + *(.resetvec) + } = 0xffff + + __bss_start = .; + .bss : { + *(.sbss) + *(.bss) + } + _end = .; +} +ASSERT(__init_end <= 0xfff00ffc, "NAND bootstrap too big"); -- cgit v1.2.3 From 2db3602fad9b0766997ae499c68533a66d87f189 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Tue, 22 Sep 2009 14:53:21 +0800 Subject: ppc/85xx: add cpu init config file for boot from NAND When boot from NAND, the NAND flash must be connected to br/or0. Also init RAM(L2 SRAM or DDR SDRAM) for load the second image to it. Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu_init_nand.c | 63 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 cpu/mpc85xx/cpu_init_nand.c (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu_init_nand.c b/cpu/mpc85xx/cpu_init_nand.c new file mode 100644 index 00000000000..184cca4c543 --- /dev/null +++ b/cpu/mpc85xx/cpu_init_nand.c @@ -0,0 +1,63 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +void cpu_init_f(void) +{ + ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + + /* + * LCRR - Clock Ratio Register - set up local bus timing + * when needed + */ + out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8); + +#if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM) + out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM); + out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM); +#else +#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined +#endif + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; + char *l2srbar; + int i; + + out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); + + /* set MBECCDIS=1, SBECCDIS=1 */ + out_be32(&l2cache->l2errdis, + (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); + + /* set L2E=1 & L2SRAM=001 */ + out_be32(&l2cache->l2ctl, + (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); + + /* Initialize L2 SRAM to zero */ + l2srbar = (char *)CONFIG_SYS_INIT_L2_ADDR; + for (i = 0; i < CONFIG_SYS_L2_SIZE; i++) + l2srbar[i] = 0; +#endif +} -- cgit v1.2.3 From b5190df365255ddc77a2f48ec14ed9c07c34129e Mon Sep 17 00:00:00 2001 From: Vivek Mahajan Date: Tue, 22 Sep 2009 12:48:27 +0530 Subject: 85xx-fdt: Fixed l2-ctlr's compatible prop for QorIQ The code assumed names where just numbers and always prefixed 'mpc'. However newer QorIQ don't follow the mpc naming scheme. Signed-off-by: Vivek Mahajan Signed-off-by: Kumar Gala --- cpu/mpc85xx/fdt.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 723f473dabf..61e0fb0636d 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor, Inc. + * Copyright 2007-2009 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -27,6 +27,7 @@ #include #include #include +#include #ifdef CONFIG_FSL_ESDHC #include #endif @@ -148,8 +149,14 @@ static inline void ft_fixup_l2cache(void *blob) } if (cpu) { - len = sprintf(compat_buf, "fsl,mpc%s-l2-cache-controller", - cpu->name); + if (isdigit(cpu->name[0])) + len = sprintf(compat_buf, + "fsl,mpc%s-l2-cache-controller", cpu->name); + else + len = sprintf(compat_buf, + "fsl,%c%s-l2-cache-controller", + tolower(cpu->name[0]), cpu->name + 1); + sprintf(&compat_buf[len + 1], "cache"); } fdt_setprop(blob, off, "cache-unified", NULL, 0); -- cgit v1.2.3 From fd8dfa17e9a0f360414523ab441e132fa65538d7 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 22 Sep 2009 15:45:44 -0500 Subject: ppc/85xx: Fix enabling of L2 cache We need to flash invalidate the locks in addition to the cache before we enable. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu_init.c | 4 ++-- cpu/mpc85xx/release.S | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index a6d1e999b60..a8d83b1c8a3 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -336,8 +336,8 @@ int cpu_init_r(void) u32 l2cfg0 = mfspr(SPRN_L2CFG0); /* invalidate the L2 cache */ - mtspr(SPRN_L2CSR0, L2CSR0_L2FI); - while (mfspr(SPRN_L2CSR0) & L2CSR0_L2FI) + mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); + while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) ; /* enable the cache */ diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 074b056b749..ecbd0d58577 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -102,7 +102,8 @@ __secondary_start_page: #ifdef CONFIG_BACKSIDE_L2_CACHE /* Enable/invalidate the L2 cache */ msync - lis r3,L2CSR0_L2FI@h + lis r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@h + ori r3,r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@l mtspr SPRN_L2CSR0,r3 1: mfspr r3,SPRN_L2CSR0 -- cgit v1.2.3 From 17e4eeb650ff3172c104457bea63101a8bb2cd7b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Sep 2009 01:44:00 -0500 Subject: ppc/p4080: CoreNet platfrom style CCSRBAR setting On CoreNet based platforms the CCSRBAR address is split between an high & low register and we no longer shift the address. Signed-off-by: Kumar Gala Signed-off-by: Scott Wood --- cpu/mpc85xx/cpu_init_early.c | 72 +++++++++++++++++++++++++++++++++----------- 1 file changed, 54 insertions(+), 18 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu_init_early.c b/cpu/mpc85xx/cpu_init_early.c index 7886f868f2a..32aa94b612c 100644 --- a/cpu/mpc85xx/cpu_init_early.c +++ b/cpu/mpc85xx/cpu_init_early.c @@ -24,6 +24,51 @@ DECLARE_GLOBAL_DATA_PTR; +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) +#ifdef CONFIG_FSL_CORENET +static void setup_ccsrbar(void) +{ + u32 temp; + volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); + volatile ccsr_local_t *ccm; + + /* + * We can't call set_law() because we haven't moved + * CCSR yet. + */ + ccm = (void *)ccsr_virt; + + out_be32(&ccm->law[0].lawbarh, + (u64)CONFIG_SYS_CCSRBAR_PHYS >> 32); + out_be32(&ccm->law[0].lawbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS); + out_be32(&ccm->law[0].lawar, + LAW_EN | (0x1e << 20) | LAW_SIZE_4K); + + in_be32((u32 *)(ccsr_virt + 0)); + in_be32((u32 *)(ccsr_virt + 1)); + isync(); + + ccm = (void *)CONFIG_SYS_CCSRBAR; + /* Now use the temporary LAW to move CCSR */ + out_be32(&ccm->ccsrbarh, (u64)CONFIG_SYS_CCSRBAR_PHYS >> 32); + out_be32(&ccm->ccsrbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS); + out_be32(&ccm->ccsrar, CCSRAR_C); + temp = in_be32(&ccm->ccsrar); + disable_law(0); +} +#else +static void setup_ccsrbar(void) +{ + u32 temp; + volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); + + temp = in_be32(ccsr_virt); + out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12); + temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR); +} +#endif +#endif + /* We run cpu_init_early_f in AS = 1 */ void cpu_init_early_f(void) { @@ -50,24 +95,15 @@ void cpu_init_early_f(void) /* set up CCSR if we want it moved */ #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) - { - u32 temp; - volatile u32 *ccsr_virt = - (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); - - mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1); - /* mas1 is the same as above */ - mas2 = FSL_BOOKE_MAS2((u32)ccsr_virt, MAS2_I|MAS2_G); - mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, - MAS3_SW|MAS3_SR); - mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT); - - write_tlb(mas0, mas1, mas2, mas3, mas7); - - temp = in_be32(ccsr_virt); - out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12); - temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR); - } + mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1); + /* mas1 is the same as above */ + mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT); + + write_tlb(mas0, mas1, mas2, mas3, mas7); + + setup_ccsrbar(); #endif init_laws(); -- cgit v1.2.3 From 2154836f4dcd2f4a5654802f9b6c829b3fef838e Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Sep 2009 01:44:39 -0500 Subject: ppc/p4080: CoreNet platfrom style secondary core release The CoreNet platform style of bringing secondary cores out of reset is a bit different that the PQ3 style. Mostly the registers that we use to setup boot translation, enable time bases, and boot release the cores have moved around. Signed-off-by: Kumar Gala --- cpu/mpc85xx/mp.c | 68 +++++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 65 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index fa65bed083b..b5c6020c7f1 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "mp.h" DECLARE_GLOBAL_DATA_PTR; @@ -135,7 +136,67 @@ ulong get_spin_addr(void) return addr; } -static void pq3_mp_up(unsigned long bootpg) +#ifdef CONFIG_FSL_CORENET +static void plat_mp_up(unsigned long bootpg) +{ + u32 up, cpu_up_mask, whoami; + u32 *table = (u32 *)get_spin_addr(); + volatile ccsr_gur_t *gur; + volatile ccsr_local_t *ccm; + volatile ccsr_rcpm_t *rcpm; + volatile ccsr_pic_t *pic; + int timeout = 10; + u32 nr_cpus; + struct law_entry e; + + gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); + rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + + nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1; + + whoami = in_be32(&pic->whoami); + cpu_up_mask = 1 << whoami; + out_be32(&ccm->bstrl, bootpg); + + e = find_law(bootpg); + out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K); + + /* disable time base at the platform */ + out_be32(&rcpm->ctbenrl, cpu_up_mask); + + /* release the hounds */ + up = ((1 << nr_cpus) - 1); + out_be32(&gur->brrl, up); + + /* wait for everyone */ + while (timeout) { + int i; + for (i = 0; i < nr_cpus; i++) { + if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) + cpu_up_mask |= (1 << i); + }; + + if ((cpu_up_mask & up) == up) + break; + + udelay(100); + timeout--; + } + + if (timeout == 0) + printf("CPU up timeout. CPU up mask is %x should be %x\n", + cpu_up_mask, up); + + /* enable time base at the platform */ + out_be32(&rcpm->ctbenrl, 0); + mtspr(SPRN_TBWU, 0); + mtspr(SPRN_TBWL, 0); + out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1); +} +#else +static void plat_mp_up(unsigned long bootpg) { u32 up, cpu_up_mask, whoami; u32 *table = (u32 *)get_spin_addr(); @@ -196,6 +257,7 @@ static void pq3_mp_up(unsigned long bootpg) devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); out_be32(&gur->devdisr, devdisr); } +#endif void cpu_mp_lmb_reserve(struct lmb *lmb) { @@ -217,7 +279,7 @@ void setup_mp(void) if (i != -1) { /* map reset page to bootpg so we can copy code there */ disable_tlb(i); - + set_tlb(1, 0xfffff000, bootpg, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, /* perms, wimge */ 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ @@ -234,7 +296,7 @@ void setup_mp(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */ 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ - pq3_mp_up(bootpg); + plat_mp_up(bootpg); } else { puts("WARNING: No reset page TLB. " "Skipping secondary core setup\n"); -- cgit v1.2.3 From 345fb36a2cf55c6ec912b84cdf2f04c4ce0c0aa1 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Mar 2009 02:39:17 -0500 Subject: ppc/p4080: Add various p4080 related defines (and p4040) There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p4080 & p4040 to cpu_type_list and SVR list * Added number of LAWs for p4080 * Set CONFIG_MAX_CPUS to 8 for p4080 Signed-off-by: Kumar Gala --- cpu/mpc85xx/Makefile | 1 + cpu/mpc8xxx/cpu.c | 4 ++++ 2 files changed, 5 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 3ef00e85069..56de7eb3818 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -53,6 +53,7 @@ COBJS-$(CONFIG_P1011) += ddr-gen3.o COBJS-$(CONFIG_P1020) += ddr-gen3.o COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o +COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c index 00791e11bd5..d191263f508 100644 --- a/cpu/mpc8xxx/cpu.c +++ b/cpu/mpc8xxx/cpu.c @@ -72,6 +72,10 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P2010, P2010_E, 1), CPU_TYPE_ENTRY(P2020, P2020, 2), CPU_TYPE_ENTRY(P2020, P2020_E, 2), + CPU_TYPE_ENTRY(P4040, P4040, 4), + CPU_TYPE_ENTRY(P4040, P4040_E, 4), + CPU_TYPE_ENTRY(P4080, P4080, 8), + CPU_TYPE_ENTRY(P4080, P4080_E, 8), #elif defined(CONFIG_MPC86xx) CPU_TYPE_ENTRY(8610, 8610, 1), CPU_TYPE_ENTRY(8641, 8641, 2), -- cgit v1.2.3 From 7f0b16fba4cdb511bf517bd56ed6834ff2c1da0f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Sep 2009 01:52:37 -0500 Subject: ppc/p4080: Handle timebase enabling and frequency reporting On CoreNet style platforms the timebase frequency is the bus frequency defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms the core not longer controls the enabling of the timebase. We now need to enable the boot core's timebase via CCSR register writes. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 4 ++++ cpu/mpc85xx/cpu_init.c | 17 +++++++++++++++++ cpu/mpc85xx/fdt.c | 2 +- 3 files changed, 22 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index bdd9ee4c833..25c04169fd9 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -184,7 +184,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) */ unsigned long get_tbclk (void) { +#ifdef CONFIG_FSL_CORENET + return (gd->bus_clk + 8) / 16; +#else return (gd->bus_clk + 4UL)/8UL; +#endif } diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index a8d83b1c8a3..53369349d13 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -136,6 +136,20 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) * initialize a bunch of registers */ +#ifdef CONFIG_FSL_CORENET +static void corenet_tb_init(void) +{ + volatile ccsr_rcpm_t *rcpm = + (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + volatile ccsr_pic_t *pic = + (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + u32 whoami = in_be32(&pic->whoami); + + /* Enable the timebase register for this core */ + out_be32(&rcpm->ctbenrl, (1 << whoami)); +} +#endif + void cpu_init_f (void) { volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); @@ -229,6 +243,9 @@ void cpu_init_f (void) #if defined(CONFIG_FSL_DMA) dma_init(); #endif +#ifdef CONFIG_FSL_CORENET + corenet_tb_init(); +#endif } diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 61e0fb0636d..efb65188226 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -294,7 +294,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_add_enet_stashing(blob); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "timebase-frequency", bd->bi_busfreq / 8, 1); + "timebase-frequency", get_tbclk(), 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); get_sys_info(&sysinfo); -- cgit v1.2.3 From 4dea2bbc7017514322383f202e1b720529dd5fbf Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Mar 2009 02:46:19 -0500 Subject: ppc/p4080: Determine various chip frequencies on CoreNet platforms The means to determine the core, bus, and DDR frequencies are completely new on CoreNet style platforms. Additionally on p4080 we can have different frequencies for FMAN and PME IP blocks. We need to keep track of the FMAN & PME frequencies since they are used for time stamping capabilities inside each block. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 45 +++++++++++++++++++++++++--- cpu/mpc85xx/speed.c | 86 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 127 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 25c04169fd9..0cc6e0323f2 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -46,11 +46,20 @@ int checkcpu (void) char buf1[32], buf2[32]; #ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_FSL_CORENET + u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) + >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; +#else u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; +#endif +#else +#ifdef CONFIG_FSL_CORENET + u32 ddr_sync = 0; #else u32 ddr_ratio = 0; #endif +#endif /* CONFIG_DDR_CLK_FREQ */ int i; svr = get_svr(); @@ -111,6 +120,19 @@ int checkcpu (void) } printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); +#ifdef CONFIG_FSL_CORENET + if (ddr_sync == 1) { + printf(" DDR:%-4s MHz (%s MT/s data rate) " + "(Synchronous), ", + strmhz(buf1, sysinfo.freqDDRBus/2), + strmhz(buf2, sysinfo.freqDDRBus)); + } else { + printf(" DDR:%-4s MHz (%s MT/s data rate) " + "(Asynchronous), ", + strmhz(buf1, sysinfo.freqDDRBus/2), + strmhz(buf2, sysinfo.freqDDRBus)); + } +#else switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", @@ -118,22 +140,26 @@ int checkcpu (void) strmhz(buf2, sysinfo.freqDDRBus)); break; case 0x7: - printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ", + printf(" DDR:%-4s MHz (%s MT/s data rate) " + "(Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; default: - printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ", + printf(" DDR:%-4s MHz (%s MT/s data rate) " + "(Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; } +#endif - if (sysinfo.freqLocalBus > LCRR_CLKDIV) + if (sysinfo.freqLocalBus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); - else + } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); + } #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); @@ -143,6 +169,17 @@ int checkcpu (void) printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); #endif +#ifdef CONFIG_SYS_DPAA_FMAN + for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { + printf(" FMAN%d: %s MHz\n", i, + strmhz(buf1, sysinfo.freqFMan[i])); + } +#endif + +#ifdef CONFIG_SYS_DPAA_PME + printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); +#endif + puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); return 0; diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 2fdcefb219c..0244b5c1b7e 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -1,5 +1,6 @@ /* * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc. + * * (C) Copyright 2003 Motorola Inc. * Xianghua Xiao, (X.Xiao@motorola.com) * @@ -37,6 +38,90 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info (sys_info_t * sysInfo) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_FSL_CORENET + volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); + + const u8 core_cplx_PLL[16] = { + [ 0] = 0, /* CC1 PPL / 1 */ + [ 1] = 0, /* CC1 PPL / 2 */ + [ 2] = 0, /* CC1 PPL / 4 */ + [ 4] = 1, /* CC2 PPL / 1 */ + [ 5] = 1, /* CC2 PPL / 2 */ + [ 6] = 1, /* CC2 PPL / 4 */ + [ 8] = 2, /* CC3 PPL / 1 */ + [ 9] = 2, /* CC3 PPL / 2 */ + [10] = 2, /* CC3 PPL / 4 */ + [12] = 3, /* CC4 PPL / 1 */ + [13] = 3, /* CC4 PPL / 2 */ + [14] = 3, /* CC4 PPL / 4 */ + }; + + const u8 core_cplx_PLL_div[16] = { + [ 0] = 1, /* CC1 PPL / 1 */ + [ 1] = 2, /* CC1 PPL / 2 */ + [ 2] = 4, /* CC1 PPL / 4 */ + [ 4] = 1, /* CC2 PPL / 1 */ + [ 5] = 2, /* CC2 PPL / 2 */ + [ 6] = 4, /* CC2 PPL / 4 */ + [ 8] = 1, /* CC3 PPL / 1 */ + [ 9] = 2, /* CC3 PPL / 2 */ + [10] = 4, /* CC3 PPL / 4 */ + [12] = 1, /* CC4 PPL / 1 */ + [13] = 2, /* CC4 PPL / 2 */ + [14] = 4, /* CC4 PPL / 4 */ + }; + uint lcrr_div, i, freqCC_PLL[4], rcw_tmp; + unsigned long sysclk = CONFIG_SYS_CLK_FREQ; + + sysInfo->freqSystemBus = sysclk; + sysInfo->freqDDRBus = sysclk; + freqCC_PLL[0] = sysclk; + freqCC_PLL[1] = sysclk; + freqCC_PLL[2] = sysclk; + freqCC_PLL[3] = sysclk; + + sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0xf; + sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0xf); + freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f; + freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f; + freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f; + freqCC_PLL[3] *= (in_be32(&clk->pllc4gsr) >> 1) & 0x3f; + + rcw_tmp = in_be32(&gur->rcwsr[3]); + for (i = 0; i < cpu_numcores(); i++) { + u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf; + u32 cplx_pll = core_cplx_PLL[c_pll_sel]; + + sysInfo->freqProcessor[i] = + freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel]; + } + +#define PME_CLK_SEL 0x80000000 +#define FM1_CLK_SEL 0x40000000 +#define FM2_CLK_SEL 0x20000000 + rcw_tmp = in_be32(&gur->rcwsr[7]); + +#ifdef CONFIG_SYS_DPAA_PME + if (rcw_tmp & PME_CLK_SEL) + sysInfo->freqPME = freqCC_PLL[2] / 2; + else + sysInfo->freqPME = sysInfo->freqSystemBus / 2; +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN + if (rcw_tmp & FM1_CLK_SEL) + sysInfo->freqFMan[0] = freqCC_PLL[2] / 2; + else + sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; +#if (CONFIG_SYS_NUM_FMAN) == 2 + if (rcw_tmp & FM2_CLK_SEL) + sysInfo->freqFMan[1] = freqCC_PLL[2] / 2; + else + sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; +#endif +#endif + +#else uint plat_ratio,e500_ratio,half_freqSystemBus; uint lcrr_div; int i; @@ -67,6 +152,7 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; } #endif +#endif #ifdef CONFIG_QE qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) -- cgit v1.2.3 From 5313e0959a7cd41e424b7d810beea9d9a063165a Mon Sep 17 00:00:00 2001 From: Martha M Stan Date: Mon, 21 Sep 2009 14:07:14 -0400 Subject: mpc512x: Streamlined fixed_sdram() init sequence. Signed-off-by: Martha M Stan Minor cleanup: Re-ordered default_mddrc_config[] to have matching indices. This allows to use the same index "N" for source and target fields; before, we had code like this out_be32(&im->mddrc.ddr_time_config2, mddrc_config[3]); which always looked like a copy & paste error because 2 != 3. Also, use NULL when meaning a null pointer. Signed-off-by: Wolfgang Denk --- cpu/mpc512x/fixed_sdram.c | 104 ++++++++++++++++++++++++++++++---------------- 1 file changed, 69 insertions(+), 35 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c index d906903d28d..673d61ee100 100644 --- a/cpu/mpc512x/fixed_sdram.c +++ b/cpu/mpc512x/fixed_sdram.c @@ -25,18 +25,70 @@ #include #include +/* + * MDDRC Config Runtime Settings in order of the 4 MDDRC cfg registers + */ +u32 default_mddrc_config[4] = { + CONFIG_SYS_MDDRC_TIME_CFG0, /* time_config0 */ + CONFIG_SYS_MDDRC_TIME_CFG1, /* time_config1 */ + CONFIG_SYS_MDDRC_TIME_CFG2, /* time_config2 */ + CONFIG_SYS_MDDRC_SYS_CFG, /* sys_config */ +}; + +u32 default_init_seq[] = { + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_PCHG_ALL, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_MICRON_INIT_DEV_OP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_EM2, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_PCHG_ALL, + CONFIG_SYS_DDRCMD_EM2, + CONFIG_SYS_DDRCMD_EM3, + CONFIG_SYS_DDRCMD_EN_DLL, + CONFIG_SYS_MICRON_INIT_DEV_OP, + CONFIG_SYS_DDRCMD_PCHG_ALL, + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_MICRON_INIT_DEV_OP, + CONFIG_SYS_DDRCMD_OCD_DEFAULT, + CONFIG_SYS_DDRCMD_PCHG_ALL, + CONFIG_SYS_DDRCMD_NOP +}; + /* * fixed sdram init: * The board doesn't use memory modules that have serial presence * detect or similar mechanism for discovery of the DRAM settings */ -long int fixed_sdram(void) +long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); u32 i; + /* take default settings and init sequence if necessary */ + if (mddrc_config == NULL) + mddrc_config = default_mddrc_config; + if (dram_init_seq == NULL) { + dram_init_seq = default_init_seq; + seq_sz = sizeof(default_init_seq)/sizeof(u32); + } + /* Initialize IO Control */ out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR); @@ -45,8 +97,8 @@ long int fixed_sdram(void) out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1); sync_law(&im->sysconf.ddrlaw.ar); - /* Enable DDR */ - out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN); + /* DDR Enable */ + out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_EN); /* Initialize DDR Priority Manager */ out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1); @@ -73,41 +125,23 @@ long int fixed_sdram(void) out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU); out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL); - /* Initialize MDDRC */ - out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG); - out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0); - out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1); - out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2); - - /* Initialize DDR */ - for (i = 0; i < 10; i++) - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + /* + * Initialize MDDRC + * put MDDRC in CMD mode and + * set the max time between refreshes to 0 during init process + */ + out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3] | MDDRC_SYS_CFG_CMD_MASK); + out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0] & MDDRC_REFRESH_ZERO_MASK); + out_be32(&im->mddrc.ddr_time_config1, mddrc_config[1]); + out_be32(&im->mddrc.ddr_time_config2, mddrc_config[2]); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + /* Initialize DDR with either default or supplied init sequence */ + for (i = 0; i < seq_sz; i++) + out_be32(&im->mddrc.ddr_command, dram_init_seq[i]); /* Start MDDRC */ - out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN); - out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN); + out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0]); + out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3]); return msize; } -- cgit v1.2.3 From b393a8951cd5c92fe20995aa9a61e8a54896b344 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 23 Sep 2009 07:56:08 +0200 Subject: mucmc52, uc101: delete ata@3a00 node, if no CF card is detected U-Boot can detect if an IDE device is present or not. If not, and this new config option is activated, U-Boot removes the ATA node from the DTS before booting Linux, so the Linux IDE driver does not probe the device and crash. This is needed for buggy hardware (uc101) where no pull down resistor is connected to the signal IDE5V_DD7. Signed-off-by: Heiko Schocher --- cpu/mpc5xxx/cpu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index f6258c7be60..efa64c74815 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -40,6 +40,10 @@ #include #endif +#if defined(CONFIG_OF_IDE_FIXUP) +#include +#endif + DECLARE_GLOBAL_DATA_PTR; int checkcpu (void) @@ -137,6 +141,22 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_path(blob, eth_path, "mac-address", enetaddr, 6, 0); do_fixup_by_path(blob, eth_path, "local-mac-address", enetaddr, 6, 0); #endif +#if defined(CONFIG_OF_IDE_FIXUP) + if (!ide_device_present(0)) { + /* NO CF card detected -> delete ata node in DTS */ + int nodeoffset = 0; + char nodename[] = "/soc5200@f0000000/ata@3a00"; + + nodeoffset = fdt_path_offset(blob, nodename); + if (nodeoffset >= 0) { + fdt_del_node(blob, nodeoffset); + } else { + printf("%s: cannot find %s node err:%s\n", + __func__, nodename, fdt_strerror(nodeoffset)); + } + } + +#endif } #endif -- cgit v1.2.3 From 6dceeaa679ca3326a8dd1ddbd535a0651ec231bb Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Sun, 27 Sep 2009 07:47:24 -0500 Subject: Add support for Eukrea CPUAT91 SBC CPUAT91 is built around Atmel's AT91RM9200 and has up to 16MB of NOR flash, up to 128MB of SDRAM, and includes a Micrel KS8721 PHY in RMII mode. Signed-off-by: Eric Benard Signed-off-by: Tom Rix --- cpu/arm920t/at91rm9200/Makefile | 5 +- cpu/arm920t/at91rm9200/ks8721.c | 249 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 252 insertions(+), 2 deletions(-) create mode 100644 cpu/arm920t/at91rm9200/ks8721.c (limited to 'cpu') diff --git a/cpu/arm920t/at91rm9200/Makefile b/cpu/arm920t/at91rm9200/Makefile index 73aeeac39de..114d8adeb2f 100644 --- a/cpu/arm920t/at91rm9200/Makefile +++ b/cpu/arm920t/at91rm9200/Makefile @@ -31,14 +31,15 @@ COBJS += bcm5221.o COBJS += dm9161.o COBJS += ether.o COBJS += i2c.o +COBJS-$(CONFIG_KS8721_PHY) += ks8721.o COBJS += lxt972.o COBJS += reset.o COBJS += spi.o COBJS += timer.o COBJS += usb.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS-y)) all: $(obj).depend $(LIB) diff --git a/cpu/arm920t/at91rm9200/ks8721.c b/cpu/arm920t/at91rm9200/ks8721.c new file mode 100644 index 00000000000..9fe379369a7 --- /dev/null +++ b/cpu/arm920t/at91rm9200/ks8721.c @@ -0,0 +1,249 @@ +/* + * (C) Copyright 2006 + * Author : Eric Benard (Eukrea Electromatique) + * based on dm9161.c which is : + * (C) Copyright 2003 + * Author : Hamid Ikdoumi (Atmel) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_DRIVER_ETHER + +#if defined(CONFIG_CMD_NET) + +/* + * Name: + * ks8721_isphyconnected + * Description: + * Reads the 2 PHY ID registers + * Arguments: + * p_mac - pointer to AT91S_EMAC struct + * Return value: + * 1 - if id read successfully + * 0 - if error + */ +unsigned int ks8721_isphyconnected(AT91PS_EMAC p_mac) +{ + unsigned short id1, id2; + + at91rm9200_EmacEnableMDIO(p_mac); + at91rm9200_EmacReadPhy(p_mac, + CONFIG_PHY_ADDRESS | KS8721_PHYID1, &id1); + at91rm9200_EmacReadPhy(p_mac, + CONFIG_PHY_ADDRESS | KS8721_PHYID2, &id2); + at91rm9200_EmacDisableMDIO(p_mac); + + if ((id1 == (KS8721_PHYID_OUI >> 6)) && + ((id2 >> 10) == (KS8721_PHYID_OUI & KS8721_LSB_MASK))) { + if ((id2 & KS8721_MODELMASK) == KS8721BL_MODEL) + printf("Micrel KS8721bL PHY detected : "); + else + printf("Unknown Micrel PHY detected : "); + return 1; + } + return 0; +} + +/* + * Name: + * ks8721_getlinkspeed + * Description: + * Link parallel detection status of MAC is checked and set in the + * MAC configuration registers + * Arguments: + * p_mac - pointer to MAC + * Return value: + * 1 - if link status set succesfully + * 0 - if link status not set + */ +unsigned char ks8721_getlinkspeed(AT91PS_EMAC p_mac) +{ + unsigned short stat1; + + if (!at91rm9200_EmacReadPhy(p_mac, KS8721_BMSR, &stat1)) + return 0; + + if (!(stat1 & KS8721_LINK_STATUS)) { + /* link status up? */ + printf("Link Down !\n"); + return 0; + } + + if (stat1 & KS8721_100BASE_TX_FD) { + /* set Emac for 100BaseTX and Full Duplex */ + printf("100BT FD\n"); + p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; + return 1; + } + + if (stat1 & KS8721_10BASE_T_FD) { + /* set MII for 10BaseT and Full Duplex */ + printf("10BT FD\n"); + p_mac->EMAC_CFG = (p_mac->EMAC_CFG & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_FD; + return 1; + } + + if (stat1 & KS8721_100BASE_T4_HD) { + /* set MII for 100BaseTX and Half Duplex */ + printf("100BT HD\n"); + p_mac->EMAC_CFG = (p_mac->EMAC_CFG & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_SPD; + return 1; + } + + if (stat1 & KS8721_10BASE_T_HD) { + /* set MII for 10BaseT and Half Duplex */ + printf("10BT HD\n"); + p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); + return 1; + } + return 0; +} + +/* + * Name: + * ks8721_initphy + * Description: + * MAC starts checking its link by using parallel detection and + * Autonegotiation and the same is set in the MAC configuration registers + * Arguments: + * p_mac - pointer to struct AT91S_EMAC + * Return value: + * 1 - if link status set succesfully + * 0 - if link status not set + */ +unsigned char ks8721_initphy(AT91PS_EMAC p_mac) +{ + unsigned char ret = 1; + unsigned short intvalue; + + at91rm9200_EmacEnableMDIO(p_mac); + + /* Try another time */ + if (!ks8721_getlinkspeed(p_mac)) + ret = ks8721_getlinkspeed(p_mac); + + /* Disable PHY Interrupts */ + intvalue = 0; + at91rm9200_EmacWritePhy(p_mac, + CONFIG_PHY_ADDRESS | KS8721_MDINTR, &intvalue); + at91rm9200_EmacDisableMDIO(p_mac); + + return ret; +} + +/* + * Name: + * ks8721_autonegotiate + * Description: + * MAC Autonegotiates with the partner status of same is set in the + * MAC configuration registers + * Arguments: + * dev - pointer to struct net_device + * Return value: + * 1 - if link status set successfully + * 0 - if link status not set + */ +unsigned char ks8721_autonegotiate(AT91PS_EMAC p_mac, int *status) +{ + unsigned short value; + unsigned short phyanar; + unsigned short phyanalpar; + + /* Set ks8721 control register */ + if (!at91rm9200_EmacReadPhy(p_mac, + CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) + return 0; + + /* remove autonegotiation enable */ + value &= ~KS8721_AUTONEG; + /* Electrically isolate PHY */ + value |= KS8721_ISOLATE; + if (!at91rm9200_EmacWritePhy(p_mac, + CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) { + return 0; + } + /* + * Set the Auto_negotiation Advertisement Register + * MII advertising for Next page, 100BaseTxFD and HD, + * 10BaseTFD and HD, IEEE 802.3 + */ + phyanar = KS8721_NP | KS8721_TX_FDX | KS8721_TX_HDX | + KS8721_10_FDX | KS8721_10_HDX | KS8721_AN_IEEE_802_3; + if (!at91rm9200_EmacWritePhy(p_mac, + CONFIG_PHY_ADDRESS | KS8721_ANAR, &phyanar)) { + return 0; + } + /* Read the Control Register */ + if (!at91rm9200_EmacReadPhy(p_mac, + CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) { + return 0; + } + value |= KS8721_SPEED_SELECT | KS8721_AUTONEG | KS8721_DUPLEX_MODE; + if (!at91rm9200_EmacWritePhy(p_mac, + CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) { + return 0; + } + /* Restart Auto_negotiation */ + value |= KS8721_RESTART_AUTONEG; + value &= ~KS8721_ISOLATE; + if (!at91rm9200_EmacWritePhy(p_mac, + CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) { + return 0; + } + /* Check AutoNegotiate complete */ + udelay(10000); + at91rm9200_EmacReadPhy(p_mac, + CONFIG_PHY_ADDRESS | KS8721_BMSR, &value); + if (!(value & KS8721_AUTONEG_COMP)) + return 0; + + /* Get the AutoNeg Link partner base page */ + if (!at91rm9200_EmacReadPhy(p_mac, + CONFIG_PHY_ADDRESS | KS8721_ANLPAR, &phyanalpar)) { + return 0; + } + + if ((phyanar & KS8721_TX_FDX) && (phyanalpar & KS8721_TX_FDX)) { + /* Set MII for 100BaseTX and Full Duplex */ + p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; + return 1; + } + + if ((phyanar & KS8721_10_FDX) && (phyanalpar & KS8721_10_FDX)) { + /* Set MII for 10BaseT and Full Duplex */ + p_mac->EMAC_CFG = (p_mac->EMAC_CFG & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_FD; + return 1; + } + return 0; +} + +#endif /* CONFIG_CMD_NET */ + +#endif /* CONFIG_DRIVER_ETHER */ -- cgit v1.2.3 From ef115a52b5d4eada120411a5aae9f0fb14023d1e Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Sun, 27 Sep 2009 11:10:09 -0500 Subject: Add support for Eukrea CPU9260/CPU9G20 SBC these boards are built around Atmel's AT91SAM9260/9G20 and have up to 64MB of NOR flash, up to 128MB of SDRAM, up to 2GB of NAND and include a 10/100 Ethernet PHY in RMII mode. Signed-off-by: Eric Benard Signed-off-by: Tom Rix --- cpu/arm926ejs/at91/lowlevel_init.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/arm926ejs/at91/lowlevel_init.S b/cpu/arm926ejs/at91/lowlevel_init.S index 9962ae9bedb..f11ebc67b37 100644 --- a/cpu/arm926ejs/at91/lowlevel_init.S +++ b/cpu/arm926ejs/at91/lowlevel_init.S @@ -194,7 +194,8 @@ SMRDATA: .word CONFIG_SYS_PIOD_PPUDR_VAL .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR) .word CONFIG_SYS_PIOD_PPUDR_VAL -#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) +#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \ + || defined(CONFIG_AT91SAM9G20) .word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR) .word CONFIG_SYS_PIOC_PDR_VAL1 .word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR) -- cgit v1.2.3 From dca0d1ee737918356a90f46bdc5505b107960031 Mon Sep 17 00:00:00 2001 From: Simon Kagstrom <[simon.kagstrom@netinsight.net]> Date: Thu, 1 Oct 2009 19:41:50 +0530 Subject: arm: Correct build with CONFIG_SYS_HUSH_PARSER set FLAG_PARSE_SEMICOLON is not defined without hush.h, so include that. Signed-off-by: Simon Kagstrom Signed-off-by: Prafulla Wadaskar --- cpu/arm926ejs/kirkwood/cpu.c | 1 + 1 file changed, 1 insertion(+) (limited to 'cpu') diff --git a/cpu/arm926ejs/kirkwood/cpu.c b/cpu/arm926ejs/kirkwood/cpu.c index bab5faf652e..6fc39025809 100644 --- a/cpu/arm926ejs/kirkwood/cpu.c +++ b/cpu/arm926ejs/kirkwood/cpu.c @@ -27,6 +27,7 @@ #include #include #include +#include #define BUFLEN 16 -- cgit v1.2.3