From 104992fc541302a6bac74448e01e7fdad20abca0 Mon Sep 17 00:00:00 2001
From: Becky Bruce <becky.bruce@freescale.com>
Date: Sun, 2 Nov 2008 18:19:32 -0600
Subject: powerpc 86xx: Handle CCSR relocation earlier

Currently, the CCSR gets relocated while translation is
enabled, meaning we need 2 BAT translations to get to both the
old location and the new location.  Also, the DEFAULT
CCSR location has a dependency on the BAT that maps the
FLASH region.  Moving the relocation removes this unnecessary
dependency. This makes it easier and more intutive to
modify the board's memory map.

Swap BATs 3 and 4 on 8610 so that all 86xx boards use the same
BAT for CCSR space.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
 cpu/mpc86xx/start.S | 29 ++++++++++++++++++++++++-----
 1 file changed, 24 insertions(+), 5 deletions(-)

(limited to 'cpu')

diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 75e431764b5..b1a23b42520 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -219,6 +219,11 @@ boot_warm:
 	sync
 #endif
 
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+	/* setup ccsrbar now while we're in real mode */
+	bl      setup_ccsrbar
+#endif
+
 	/*
 	 * Calculate absolute address in FLASH and jump there
 	 *------------------------------------------------------*/
@@ -281,10 +286,6 @@ in_flash:
 	bl      setup_bats
 	sync
 
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
-	/* setup ccsrbar */
-	bl      setup_ccsrbar
-#endif
 
 	/* run low-level CPU init code	   (from Flash) */
 	bl	cpu_init_f
@@ -365,10 +366,28 @@ invalidate_bats:
  * early_bats:
  *
  * Set up bats needed early on - this is usually the BAT for the
- * stack-in-cache and the Flash
+ * stack-in-cache, the Flash, and CCSR space
  */
 	.globl  early_bats
 early_bats:
+	/* IBAT 3 */
+	lis	r4, CONFIG_SYS_IBAT3L@h
+	ori     r4, r4, CONFIG_SYS_IBAT3L@l
+	lis	r3, CONFIG_SYS_IBAT3U@h
+	ori     r3, r3, CONFIG_SYS_IBAT3U@l
+	mtspr   IBAT3L, r4
+	mtspr   IBAT3U, r3
+	isync
+
+	/* DBAT 3 */
+	lis	r4, CONFIG_SYS_DBAT3L@h
+	ori     r4, r4, CONFIG_SYS_DBAT3L@l
+	lis	r3, CONFIG_SYS_DBAT3U@h
+	ori     r3, r3, CONFIG_SYS_DBAT3U@l
+	mtspr   DBAT3L, r4
+	mtspr   DBAT3U, r3
+	isync
+
 	/* IBAT 5 */
 	lis	r4, CONFIG_SYS_IBAT5L@h
 	ori     r4, r4, CONFIG_SYS_IBAT5L@l
-- 
cgit v1.3.1


From 1266df887781c779deaf6d05eea2ef90a470cb34 Mon Sep 17 00:00:00 2001
From: Becky Bruce <becky.bruce@freescale.com>
Date: Mon, 3 Nov 2008 15:44:01 -0600
Subject: powerpc: change 86xx SMP boot method

We put the bootpg for the secondary cpus into memory and use
BPTR to get to it.  This is a step towards converting to the
ePAPR boot methodology.  Also, the code is written to
deal properly with more than 4GB of RAM.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
 cpu/mpc86xx/Makefile          |   4 +
 cpu/mpc86xx/cpu_init.c        |   4 +
 cpu/mpc86xx/fdt.c             |  21 ++++++
 cpu/mpc86xx/mp.c              |  68 +++++++++++++++++
 cpu/mpc86xx/mp.h              |   7 ++
 cpu/mpc86xx/release.S         | 169 ++++++++++++++++++++++++++++++++++++++++++
 cpu/mpc86xx/start.S           |  77 +------------------
 include/configs/MPC8610HPCD.h |   7 ++
 include/configs/MPC8641HPCN.h |   7 ++
 include/configs/sbc8641d.h    |   7 ++
 10 files changed, 298 insertions(+), 73 deletions(-)
 create mode 100644 cpu/mpc86xx/mp.c
 create mode 100644 cpu/mpc86xx/mp.h
 create mode 100644 cpu/mpc86xx/release.S

(limited to 'cpu')

diff --git a/cpu/mpc86xx/Makefile b/cpu/mpc86xx/Makefile
index a9767adeb79..34a97555621 100644
--- a/cpu/mpc86xx/Makefile
+++ b/cpu/mpc86xx/Makefile
@@ -31,6 +31,10 @@ LIB	= $(obj)lib$(CPU).a
 START	= start.o
 SOBJS	= cache.o
 
+ifneq ($(CONFIG_NUM_CPUS),1)
+COBJS-y += mp.o
+SOBJS += release.o
+endif
 COBJS-y	+= traps.o
 COBJS-y	+= cpu.o
 COBJS-y	+= cpu_init.o
diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index 4ab88f0b0a8..06f179c0937 100644
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -31,6 +31,7 @@
 #include <mpc86xx.h>
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
+#include "mp.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -121,6 +122,9 @@ void cpu_init_f(void)
  */
 int cpu_init_r(void)
 {
+#if (CONFIG_NUM_CPUS > 1)
+	setup_mp();
+#endif
 	return 0;
 }
 
diff --git a/cpu/mpc86xx/fdt.c b/cpu/mpc86xx/fdt.c
index 1fef94f5db5..3adfad98c6b 100644
--- a/cpu/mpc86xx/fdt.c
+++ b/cpu/mpc86xx/fdt.c
@@ -9,9 +9,17 @@
 #include <common.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include "mp.h"
+
+DECLARE_GLOBAL_DATA_PTR;
 
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
+#if (CONFIG_NUM_CPUS > 1)
+	int off;
+	u32 bootpg;
+#endif
+
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 			     "timebase-frequency", bd->bi_busfreq / 4, 1);
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
@@ -32,4 +40,17 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	do_fixup_by_compat_u32(blob, "ns16550",
 			       "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 #endif
+
+#if (CONFIG_NUM_CPUS > 1)
+	/* if we have 4G or more of memory, put the boot page at 4Gb-1M */
+	if (gd->ram_size > 0xfffff000)
+		bootpg = 0xfff00000;
+	else
+		bootpg = gd->ram_size - (1024 * 1024);
+
+	/* Reserve the boot page so OSes dont use it */
+	off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
+	if (off < 0)
+		printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
+#endif
 }
diff --git a/cpu/mpc86xx/mp.c b/cpu/mpc86xx/mp.c
new file mode 100644
index 00000000000..5014401ddc2
--- /dev/null
+++ b/cpu/mpc86xx/mp.c
@@ -0,0 +1,68 @@
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <ioports.h>
+#include <lmb.h>
+#include <asm/io.h>
+#include "mp.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_NUM_CPUS > 1)
+void cpu_mp_lmb_reserve(struct lmb *lmb)
+{
+	u32 bootpg;
+
+	/* if we have 4G or more of memory, put the boot page at 4Gb-1M */
+	if ((u64)gd->ram_size > 0xfffff000)
+		bootpg = 0xfff00000;
+	else
+		bootpg = gd->ram_size - (1024 * 1024);
+
+	/* tell u-boot we stole a page */
+	lmb_reserve(lmb, bootpg, 4096);
+}
+
+/*
+ * Copy the code for other cpus to execute into an
+ * aligned location accessible via BPTR
+ */
+void setup_mp(void)
+{
+	extern ulong __secondary_start_page;
+	ulong fixup = (ulong)&__secondary_start_page;
+	u32 bootpg;
+	u32 bootpg_va;
+
+	/*
+	 * If we have 4G or more of memory, put the boot page at 4Gb-1M.
+	 * Otherwise, put it at the very end of RAM.
+	 */
+	if (gd->ram_size > 0xfffff000)
+		bootpg = 0xfff00000;
+	else
+		bootpg = gd->ram_size - (1024 * 1024);
+
+	if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
+		/* We're not covered by the DDR mapping, set up BAT  */
+		write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K |
+			  BATU_VS | BATU_VP,
+			  bootpg | BATL_PP_RW | BATL_MEMCOHERENCE);
+		bootpg_va = CONFIG_SYS_SCRATCH_VA;
+	} else {
+		bootpg_va = bootpg;
+	}
+
+	memcpy((void *)bootpg_va, (void *)fixup, 4096);
+	flush_cache(bootpg_va, 4096);
+
+	/* remove the temporary BAT mapping */
+	if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE)
+		write_bat(DBAT7, 0, 0);
+
+	/* If the physical location of bootpg is not at fff00000, set BPTR */
+	if (bootpg != 0xfff00000)
+		out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 |
+			 (bootpg >> 12));
+}
+#endif
diff --git a/cpu/mpc86xx/mp.h b/cpu/mpc86xx/mp.h
new file mode 100644
index 00000000000..886e0c839d8
--- /dev/null
+++ b/cpu/mpc86xx/mp.h
@@ -0,0 +1,7 @@
+#ifndef __MPC86XX_MP_H_
+#define __MPC86XX_MP_H_
+
+void setup_mp(void);
+void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+#endif
diff --git a/cpu/mpc86xx/release.S b/cpu/mpc86xx/release.S
new file mode 100644
index 00000000000..b524e5016e8
--- /dev/null
+++ b/cpu/mpc86xx/release.S
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2004, 2007, 2008 Freescale Semiconductor.
+ * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <mpc86xx.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+/* If this is a multi-cpu system then we need to handle the
+ * 2nd cpu.  The assumption is that the 2nd cpu is being
+ * held in boot holdoff mode until the 1st cpu unlocks it
+ * from Linux.	We'll do some basic cpu init and then pass
+ * it to the Linux Reset Vector.
+ * Sri:	 Much of this initialization is not required. Linux
+ * rewrites the bats, and the sprs and also enables the L1 cache.
+ *
+ * Core 0 must copy this to a 1M aligned region and set BPTR
+ * to point to it.
+ */
+#if (CONFIG_NUM_CPUS > 1)
+	.align 12
+.globl __secondary_start_page
+__secondary_start_page:
+	.space 0x100	/* space over to reset vector loc */
+	mfspr	r0, MSSCR0
+	andi.	r0, r0, 0x0020
+	rlwinm	r0,r0,27,31,31
+	mtspr	PIR, r0
+
+	/* Invalidate BATs */
+	li	r0, 0
+	mtspr	IBAT0U, r0
+	mtspr	IBAT1U, r0
+	mtspr	IBAT2U, r0
+	mtspr	IBAT3U, r0
+	mtspr	IBAT4U, r0
+	mtspr	IBAT5U, r0
+	mtspr	IBAT6U, r0
+	mtspr	IBAT7U, r0
+	isync
+	mtspr	DBAT0U, r0
+	mtspr	DBAT1U, r0
+	mtspr	DBAT2U, r0
+	mtspr	DBAT3U, r0
+	mtspr	DBAT4U, r0
+	mtspr	DBAT5U, r0
+	mtspr	DBAT6U, r0
+	mtspr	DBAT7U, r0
+	isync
+	sync
+
+	/* enable extended addressing */
+	mfspr	r0, HID0
+	lis	r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
+	ori	r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
+	mtspr	HID0, r0
+	sync
+	isync
+
+#ifdef CONFIG_SYS_L2
+	/* init the L2 cache */
+	addis	r3, r0, L2_INIT@h
+	ori	r3, r3, L2_INIT@l
+	sync
+	mtspr	l2cr, r3
+#ifdef CONFIG_ALTIVEC
+	dssall
+#endif
+	/* invalidate the L2 cache */
+	mfspr	r3, l2cr
+	rlwinm.	r3, r3, 0, 0, 0
+	beq	1f
+
+	mfspr	r3, l2cr
+	rlwinm	r3, r3, 0, 1, 31
+
+#ifdef	CONFIG_ALTIVEC
+	dssall
+#endif
+	sync
+	mtspr	l2cr, r3
+	sync
+1:	mfspr	r3, l2cr
+	oris	r3, r3, L2CR_L2I@h
+	mtspr	l2cr, r3
+
+invl2:
+	mfspr	r3, l2cr
+	andis.	r3, r3, L2CR_L2I@h
+	bne	invl2
+	sync
+#endif
+
+	/* enable and invalidate the data cache */
+	mfspr	r3, HID0
+	li	r5, HID0_DCFI|HID0_DLOCK
+	andc	r3, r3, r5
+	mtspr	HID0, r3		/* no invalidate, unlock */
+	ori	r3, r3, HID0_DCE
+	ori	r5, r3, HID0_DCFI
+	mtspr	HID0, r5		/* enable + invalidate */
+	mtspr	HID0, r3		/* enable */
+	sync
+#ifdef CFG_L2
+	sync
+	lis	r3, L2_ENABLE@h
+	ori	r3, r3, L2_ENABLE@l
+	mtspr	l2cr, r3
+	isync
+	sync
+#endif
+
+	/* enable and invalidate the instruction cache*/
+	mfspr	r3, HID0
+	li	r5, HID0_ICFI|HID0_ILOCK
+	andc	r3, r3, r5
+	ori	r3, r3, HID0_ICE
+	ori	r5, r3, HID0_ICFI
+	mtspr	HID0, r5
+	mtspr	HID0, r3
+	isync
+	sync
+
+	/* TBEN in HID0 */
+	mfspr	r4, HID0
+	oris	r4, r4, 0x0400
+	mtspr	HID0, r4
+	sync
+	isync
+
+	/* MCP|SYNCBE|ABE in HID1 */
+	mfspr	r4, HID1
+	oris	r4, r4, 0x8000
+	ori	r4, r4, 0x0C00
+	mtspr	HID1, r4
+	sync
+	isync
+
+	lis	r3, CONFIG_LINUX_RESET_VEC@h
+	ori	r3, r3, CONFIG_LINUX_RESET_VEC@l
+	mtlr	r3
+	blr
+
+	/* Never Returns, Running in Linux Now */
+#endif
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index b1a23b42520..48f8c5acf59 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -179,20 +179,10 @@ _end_of_vectors:
 
 boot_cold:
 boot_warm:
-
-	/* if this is a multi-core system we need to check which cpu
-	 * this is, if it is not cpu 0 send the cpu to the linux reset
-	 * vector */
-#if (CONFIG_NUM_CPUS > 1)
-	mfspr	r0, MSSCR0
-	andi.	r0, r0, 0x0020
-	rlwinm	r0,r0,27,31,31
-	mtspr	PIR, r0
-	beq	1f
-
-	bl	secondary_cpu_setup
-#endif
-
+	/*
+	 * NOTE: Only Cpu 0 will ever come here.  Other cores go to an
+	 * address specified by the BPTR
+	 */
 1:
 #ifdef CONFIG_SYS_RAMBOOT
 	/* disable everything */
@@ -978,63 +968,4 @@ unlock_ram_in_cache:
 #endif
 #endif
 
-/* If this is a multi-cpu system then we need to handle the
- * 2nd cpu.  The assumption is that the 2nd cpu is being
- * held in boot holdoff mode until the 1st cpu unlocks it
- * from Linux.	We'll do some basic cpu init and then pass
- * it to the Linux Reset Vector.
- * Sri:	 Much of this initialization is not required. Linux
- * rewrites the bats, and the sprs and also enables the L1 cache.
- */
-#if (CONFIG_NUM_CPUS > 1)
-.globl secondary_cpu_setup
-secondary_cpu_setup:
-	/* Do only core setup on all cores except cpu0 */
-	bl	invalidate_bats
-	sync
-	bl	enable_ext_addr
 
-#ifdef CONFIG_SYS_L2
-	/* init the L2 cache */
-	addis	r3, r0, L2_INIT@h
-	ori	r3, r3, L2_INIT@l
-	sync
-	mtspr	l2cr, r3
-#ifdef CONFIG_ALTIVEC
-	dssall
-#endif
-	/* invalidate the L2 cache */
-	bl	l2cache_invalidate
-	sync
-#endif
-
-	/* enable and invalidate the data cache */
-	bl	dcache_enable
-	sync
-
-	/* enable and invalidate the instruction cache*/
-	bl	icache_enable
-	sync
-
-	/* TBEN in HID0 */
-	mfspr	r4, HID0
-	oris	r4, r4, 0x0400
-	mtspr	HID0, r4
-	sync
-	isync
-
-	/* MCP|SYNCBE|ABE in HID1 */
-	mfspr	r4, HID1
-	oris	r4, r4, 0x8000
-	ori	r4, r4, 0x0C00
-	mtspr	HID1, r4
-	sync
-	isync
-
-	lis	r3, CONFIG_LINUX_RESET_VEC@h
-	ori	r3, r3, CONFIG_LINUX_RESET_VEC@l
-	mtlr	r3
-	blr
-
-	/* Never Returns, Running in Linux Now */
-#endif
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 6f041277a80..44867633667 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -36,6 +36,12 @@
 
 #define CONFIG_SYS_RESET_ADDRESS	0xfff00100
 
+/*
+ * virtual address to be used for temporary mappings.  There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA	0xc0000000
+
 #define CONFIG_PCI		1	/* Enable PCI/PCIE*/
 #define CONFIG_PCI1		1	/* PCI controler 1 */
 #define CONFIG_PCIE1		1	/* PCIe 1 connected to ULI bridge */
@@ -92,6 +98,7 @@
 
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
 #define CONFIG_VERY_BIG_RAM
 
 #define MPC86xx_DDR_SDRAM_CLK_CNTL
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index c33047f5406..1401e159a3d 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -45,6 +45,12 @@
 
 #define CONFIG_SYS_RESET_ADDRESS    0xfff00100
 
+/*
+ * virtual address to be used for temporary mappings.  There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA	0xe0000000
+
 /*
  * set this to enable Rapid IO.  PCI and RIO are mutually exclusive
  */
@@ -109,6 +115,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
 #define CONFIG_VERY_BIG_RAM
 
 #define MPC86xx_DDR_SDRAM_CLK_CNTL
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 09a990111b9..e8216ea358f 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -49,6 +49,12 @@
 
 #define CONFIG_SYS_RESET_ADDRESS    0xfff00100
 
+/*
+ * virtual address to be used for temporary mappings.  There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA	0xe8000000
+
 #define CONFIG_PCI		1	/* Enable PCIE */
 #define CONFIG_PCI1		1	/* PCIE controler 1 (slot 1) */
 #define CONFIG_PCI2		1	/* PCIE controler 2 (slot 2) */
@@ -108,6 +114,7 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE2	0x10000000	/* DDR bank 2 */
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_SYS_SDRAM_BASE2		CONFIG_SYS_DDR_SDRAM_BASE2
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
 #define CONFIG_VERY_BIG_RAM
 
 #define MPC86xx_DDR_SDRAM_CLK_CNTL
-- 
cgit v1.3.1


From 24bfb48c35fed6ad1f047e3e4a27df302482cd93 Mon Sep 17 00:00:00 2001
From: Becky Bruce <becky.bruce@freescale.com>
Date: Wed, 5 Nov 2008 14:55:30 -0600
Subject: mpc86xx: Move setup_bats into cpu_init_f

In order to later allow for a physical relocation of the
flash, setup_bats, which sets up the final BAT mapping
for the board, needs to happen *after* init_laws().
Otherwise, there will be no window programmed for the flash
at the new physical location at the point when we change
the mmu translation.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
 cpu/mpc86xx/cpu_init.c | 4 ++++
 cpu/mpc86xx/start.S    | 5 -----
 2 files changed, 4 insertions(+), 5 deletions(-)

(limited to 'cpu')

diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index 06f179c0937..a7e6036dbec 100644
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -33,6 +33,8 @@
 #include <asm/fsl_law.h>
 #include "mp.h"
 
+void setup_bats(void);
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -57,6 +59,8 @@ void cpu_init_f(void)
 	init_laws();
 #endif
 
+	setup_bats();
+
 	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 	 * addresses - these have to be modified later when FLASH size
 	 * has been determined
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 48f8c5acf59..0d30e91b61c 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -272,11 +272,6 @@ in_flash:
 
 	GET_GOT			/* initialize GOT access	*/
 
-	/* setup the rest of the bats */
-	bl      setup_bats
-	sync
-
-
 	/* run low-level CPU init code	   (from Flash) */
 	bl	cpu_init_f
 	sync
-- 
cgit v1.3.1


From c1e1cf69547b138173f87a7f81c42a5d8dbfde3d Mon Sep 17 00:00:00 2001
From: Becky Bruce <becky.bruce@freescale.com>
Date: Wed, 5 Nov 2008 14:55:34 -0600
Subject: mpc86xx: Use SRR0/1/rfi to enable address translation, not blr

Using a mtmsr/blr means that you have to be executing at the
same virtual address once you enable translation.  This is
unnecessarily restrictive, and is not really how this is
usually done.  Change it to use the more common mtspr SRR0/SRR1
and rfi method.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
 cpu/mpc86xx/start.S | 19 ++++++++-----------
 1 file changed, 8 insertions(+), 11 deletions(-)

(limited to 'cpu')

diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 0d30e91b61c..7e36801741c 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -244,9 +244,15 @@ in_flash:
 	 */
 
 	/* enable address translation */
-	bl	enable_addr_trans
-	sync
+	mfmsr	r5
+	ori	r5, r5, (MSR_IR | MSR_DR)
+	lis	r3,addr_trans_enabled@h
+	ori	r3, r3, addr_trans_enabled@l
+	mtspr	SPRN_SRR0,r3
+	mtspr	SPRN_SRR1,r5
+	rfi
 
+addr_trans_enabled:
 	/* enable and invalidate the data cache */
 /*	bl	l1dcache_enable */
 	bl	dcache_enable
@@ -423,15 +429,6 @@ tlblp:
 	blt tlblp
 	blr
 
-	.globl enable_addr_trans
-enable_addr_trans:
-	/* enable address translation */
-	mfmsr	r5
-	ori	r5, r5, (MSR_IR | MSR_DR)
-	mtmsr	r5
-	isync
-	blr
-
 	.globl disable_addr_trans
 disable_addr_trans:
 	/* disable address translation */
-- 
cgit v1.3.1


From bf9a8c34309ed9276258295db9e9212aabb2531a Mon Sep 17 00:00:00 2001
From: Becky Bruce <becky.bruce@freescale.com>
Date: Wed, 5 Nov 2008 14:55:35 -0600
Subject: mpc86xx: Change early FLASH mapping to 1M at
 CONFIG_MONITOR_BASE_EARLY

We define CONFIG_MONITOR_BASE_EARLY to define the initial location
of the bootpage in flash.   Use this to create an early mapping
definition for the FLASH, and change the early_bats code to use this.

This  change facilitates the relocation of the flash since the early
mappings are no longer tied to the final location of the flash.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
 cpu/mpc86xx/start.S           | 20 ++++++++++----------
 include/configs/MPC8610HPCD.h |  9 +++++++++
 include/configs/MPC8641HPCN.h | 12 +++++++++++-
 include/configs/sbc8641d.h    |  9 +++++++++
 4 files changed, 39 insertions(+), 11 deletions(-)

(limited to 'cpu')

diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 7e36801741c..60af3dd7128 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -217,8 +217,8 @@ boot_warm:
 	/*
 	 * Calculate absolute address in FLASH and jump there
 	 *------------------------------------------------------*/
-	lis	r3, CONFIG_SYS_MONITOR_BASE@h
-	ori	r3, r3, CONFIG_SYS_MONITOR_BASE@l
+	lis	r3, CONFIG_SYS_MONITOR_BASE_EARLY@h
+	ori	r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l
 	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
 	mtlr	r3
 	blr
@@ -398,19 +398,19 @@ early_bats:
 	isync
 
 	/* IBAT 6 */
-	lis	r4, CONFIG_SYS_IBAT6L@h
-	ori     r4, r4, CONFIG_SYS_IBAT6L@l
-	lis	r3, CONFIG_SYS_IBAT6U@h
-	ori     r3, r3, CONFIG_SYS_IBAT6U@l
+	lis	r4, CONFIG_SYS_IBAT6L_EARLY@h
+	ori     r4, r4, CONFIG_SYS_IBAT6L_EARLY@l
+	lis	r3, CONFIG_SYS_IBAT6U_EARLY@h
+	ori     r3, r3, CONFIG_SYS_IBAT6U_EARLY@l
 	mtspr   IBAT6L, r4
 	mtspr   IBAT6U, r3
 	isync
 
 	/* DBAT 6 */
-	lis	r4, CONFIG_SYS_DBAT6L@h
-	ori     r4, r4, CONFIG_SYS_DBAT6L@l
-	lis	r3, CONFIG_SYS_DBAT6U@h
-	ori     r3, r3, CONFIG_SYS_DBAT6U@l
+	lis	r4, CONFIG_SYS_DBAT6L_EARLY@h
+	ori     r4, r4, CONFIG_SYS_DBAT6L_EARLY@l
+	lis	r3, CONFIG_SYS_DBAT6U_EARLY@h
+	ori     r3, r3, CONFIG_SYS_DBAT6U_EARLY@l
 	mtspr   DBAT6L, r4
 	mtspr   DBAT6U, r3
 	isync
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 44867633667..f2fe4a6cf98 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -187,6 +187,7 @@
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
 
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
@@ -419,6 +420,14 @@
 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
 
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY	(TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
+
 /*
  * BAT7		4M	Cache-inhibited, guarded
  * 0xe800_0000	4M	PIXIS
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 0a6d5f9ef0c..4925057b2eb 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -206,7 +206,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #undef	CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
 
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
@@ -497,6 +498,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 				 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
 
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY	(TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
+
+/* Leave BAT7 free here - it is used for various things later */
 #define CONFIG_SYS_DBAT7L 0x00000000
 #define CONFIG_SYS_DBAT7U 0x00000000
 #define CONFIG_SYS_IBAT7L 0x00000000
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index e8216ea358f..45d81792e06 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -231,6 +231,7 @@
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
 
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
@@ -463,6 +464,14 @@
 #define CONFIG_SYS_IBAT6L	((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
 
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY	(TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
+
 #define CONFIG_SYS_DBAT7L	0x00000000
 #define CONFIG_SYS_DBAT7U	0x00000000
 #define CONFIG_SYS_IBAT7L	0x00000000
-- 
cgit v1.3.1


From c759a01a0022de9378a3a761f49786f87684c916 Mon Sep 17 00:00:00 2001
From: Becky Bruce <becky.bruce@freescale.com>
Date: Thu, 6 Nov 2008 17:36:04 -0600
Subject: mpc8641: Change 32-bit memory map

The memory map on the 8641hpcn is modified to look more like
the 85xx boards; this is a step towards a more standardized
layout going forward. As part of this change, we now relocate
the flash.

The regions for some of the mappings were far larger than they
needed to be.  I have reduced the mappings to match the
actual sizes supported by the hardware.

In addition I have removed the comments at the head
of the BAT blocks in the config file, rather than updating
them.  These get horribly out of date, and it's a simple
matter to look at the defines to see what they are set to
since everything is right here in the same file.

Documentation has been changed to reflect the new map, as this
change is user visible, and affects the OS which runs post-uboot.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
 board/freescale/mpc8641hpcn/config.mk |  2 +-
 board/freescale/mpc8641hpcn/law.c     | 23 ++++++-----
 cpu/mpc86xx/start.S                   |  2 +-
 doc/README.mpc8641hpcn                | 40 +++++++++---------
 include/configs/MPC8641HPCN.h         | 76 ++++++++++++++++++-----------------
 5 files changed, 75 insertions(+), 68 deletions(-)

(limited to 'cpu')

diff --git a/board/freescale/mpc8641hpcn/config.mk b/board/freescale/mpc8641hpcn/config.mk
index f778dcbe0c5..487a766998b 100644
--- a/board/freescale/mpc8641hpcn/config.mk
+++ b/board/freescale/mpc8641hpcn/config.mk
@@ -25,7 +25,7 @@
 # default CCSRBAR is at 0xff700000
 # assume U-Boot is less than 0.5MB
 #
-TEXT_BASE = 0xfff00000
+TEXT_BASE = 0xeff00000
 
 PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
 PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float
diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c
index 8ec52387579..669a091691c 100644
--- a/board/freescale/mpc8641hpcn/law.c
+++ b/board/freescale/mpc8641hpcn/law.c
@@ -31,17 +31,20 @@
  * LAW(Local Access Window) configuration:
  *
  * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * if PCI
  * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
  * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
- * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
- * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
- * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
- * 0xf800_0000     0xf80f_ffff     CCSRBAR                 1M
- * 0xf810_0000     0xf81f_ffff     PIXIS                   1M
- * 0xfe00_0000     0xffff_ffff     FLASH (boot bank)       32M
+ * else if RIO
+ * 0x8000_0000     0x9fff_ffff     RapidIO                 512M
+ * endif
+ * 0xffc0_0000     0xffc0_ffff     PCI1 IO                 64K
+ * 0xffc1_0000     0xffc1_ffff     PCI2 IO                 64K
+ * 0xffe0_0000     0xffef_ffff     CCSRBAR                 1M
+ * 0xffdf_0000     0xffe0_0000     PIXIS, CF               64K
+ * 0xef80_0000     0xefff_ffff     FLASH (boot bank)       8M
  *
  * Notes:
- *    CCSRBAR don't need a configured Local Access Window.
+ *    CCSRBAR doesn't need a configured Local Access Window.
  *    If flash is 8M at default position (last 8M), no LAW needed.
  */
 
@@ -52,12 +55,12 @@ struct law_entry law_table[] = {
 #ifdef CONFIG_PCI
 	SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
 	SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
 #elif defined(CONFIG_RIO)
 	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 #endif
-	SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
+	SET_LAW(PIXIS_BASE, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
 };
 
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 60af3dd7128..0aa8a4feaab 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -285,7 +285,7 @@ addr_trans_enabled:
 #ifdef	RUN_DIAG
 
 	/* Load PX_AUX register address in r4 */
-	lis	r4, 0xf810
+	lis	r4, PIXIS_BASE@h
 	ori	r4, r4, 0x6
 	/* Load contents of PX_AUX in r3 bits 24 to 31*/
 	lbz	r3, 0(r4)
diff --git a/doc/README.mpc8641hpcn b/doc/README.mpc8641hpcn
index 2c3c7034e2e..0a6e715bc28 100644
--- a/doc/README.mpc8641hpcn
+++ b/doc/README.mpc8641hpcn
@@ -79,51 +79,53 @@ Switches:
 
 3. Flash U-Boot
 ---------------
-The flash range 0xFF800000 to 0xFFFFFFFF can be divided into 2 halves.
+The flash range 0xEF800000 to 0xEFFFFFFF can be divided into 2 halves.
 It is possible to use either half to boot using u-boot.  Switch 5 bit 2
 is used for this purpose.
 
-0xFF800000 to 0xFFBFFFFF - 4MB
-0xFFC00000 to 0xFFFFFFFF - 4MB
-When this bit is 0, U-Boot is at 0xFFF00000.
-When this bit is 1, U-Boot is at 0xFFB00000.
+0xEF800000 to 0xEFBFFFFF - 4MB
+0xEFC00000 to 0xEFFFFFFF - 4MB
+When this bit is 0, U-Boot is at 0xEFF00000.
+When this bit is 1, U-Boot is at 0xEFB00000.
 
 Use the above mentioned flash commands to program the other half, and
 use switch 5, bit 2 to alternate between the halves.  Note: The booting
-version of U-Boot will always be at 0xFFF00000.
+version of U-Boot will always be at 0xEFF00000.
 
-To Flash U-Boot into the booting bank (0xFFC00000 - 0xFFFFFFFF):
+To Flash U-Boot into the booting bank (0xEFC00000 - 0xEFFFFFFF):
 
 	tftp 1000000 u-boot.bin
 	protect off all
-	erase fff00000 +$filesize
-	cp.b 1000000 fff00000 $filesize
+	erase eff00000 +$filesize
+	cp.b 1000000 eff00000 $filesize
 
 or use tftpflash command:
 	run tftpflash
 
-To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF):
+To Flash U-boot into the alternative bank (0xEF800000 - 0xEFBFFFFF):
 
 	tftp 1000000 u-boot.bin
-	erase ffb00000 +$filesize
-	cp.b 1000000 ffb00000 $filesize
+	erase efb00000 +$filesize
+	cp.b 1000000 efb00000 $filesize
 
 
 4. Memory Map
 -------------
+NOTE:  RIO and PCI are mutually exclusive, so they share an address
 
 	Memory Range			Device		Size
 	------------			------		----
 	0x0000_0000	0x7fff_ffff	DDR		2G
+	0x8000_0000	0x9fff_ffff	RIO MEM		512M
 	0x8000_0000	0x9fff_ffff	PCI1/PEX1 MEM	512M
-	0xa000_0000	0xafff_ffff	PCI2/PEX2 MEM	512M
-	0xf800_0000	0xf80f_ffff	CCSR		1M
-	0xf810_0000	0xf81f_ffff	PIXIS		1M
+	0xa000_0000	0xbfff_ffff	PCI2/PEX2 MEM	512M
+	0xffe0_0000	0xffef_ffff	CCSR		1M
+	0xffdf_0000	0xffdf_7fff	PIXIS		8K
+	0xffdf_8000	0xffdf_ffff	CF		8K
 	0xf840_0000	0xf840_3fff	Stack space	32K
-	0xe200_0000	0xe2ff_ffff	PCI1/PEX1 IO	16M
-	0xe300_0000	0xe3ff_ffff	PCI2/PEX2 IO	16M
-	0xfe00_0000	0xfeff_ffff	Flash(alternate)16M
-	0xff00_0000	0xffff_ffff	Flash(boot bank)16M
+	0xffc0_0000	0xffc0_ffff	PCI1/PEX1 IO	64K
+	0xffc1_0000	0xffc1_ffff	PCI2/PEX2 IO	64K
+	0xef80_0000	0xefff_ffff	Flash		8M
 
 5. pixis_reset command
 --------------------
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 4925057b2eb..ec3d112c2f9 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -96,7 +96,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * actual resources get mapped (not physical addresses)
  */
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
-#define CONFIG_SYS_CCSRBAR		0xf8000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
 #define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)
@@ -159,7 +159,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 
-#define CONFIG_SYS_FLASH_BASE		0xff800000     /* start of FLASH 8M */
+#define CONFIG_SYS_FLASH_BASE		0xef800000     /* start of FLASH 8M */
 
 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
 
@@ -172,15 +172,22 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_SYS_BR2_PRELIM		(BR_PHYS_ADDR(CF_BASE)		\
 					 | 0x00001001)	/* port size 16bit */
-#define CONFIG_SYS_OR2_PRELIM		0xfff06ff7	/* 1MB Compact Flash area*/
+#define CONFIG_SYS_OR2_PRELIM		0xffffeff7	/* 32k Compact Flash */
 
 #define CONFIG_SYS_BR3_PRELIM		(BR_PHYS_ADDR(PIXIS_BASE)	\
 					 | 0x00000801) /* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM		0xfff06ff7	/* 1MB PIXIS area*/
+#define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32k PIXIS area*/
 
+/*
+ * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
+ * The PIXIS and CF by themselves aren't large enough to take up the 128k
+ * required for the smallest BAT mapping, so there's a 64k hole.
+ */
+#define CONFIG_SYS_LBC_BASE		0xffde0000
 
 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
-#define PIXIS_BASE	(CONFIG_SYS_CCSRBAR + 0x00100000) /* PIXIS registers */
+#define PIXIS_BASE		(CONFIG_SYS_LBC_BASE + 0x00010000)
+#define PIXIS_SIZE		0x00008000	/* 32k */
 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
 #define PIXIS_VER		0x1	/* Board version at offset 1 */
 #define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
@@ -198,7 +205,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40	/* Reset altbank mask*/
 
 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
-#define CF_BASE			(PIXIS_BASE + 0x00100000)
+#define CF_BASE			(PIXIS_BASE + PIXIS_SIZE)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
@@ -287,7 +294,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * RapidIO MMU
  */
-#define CONFIG_SYS_RIO_MEM_BASE	0xc0000000	/* base address */
+#define CONFIG_SYS_RIO_MEM_BASE	0x80000000	/* base address */
 #define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BASE
 #define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
 
@@ -299,8 +306,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
-#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCI1_IO_PHYS	0xffc00000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64K */
 
 /* For RTL8139 */
 #define KSEG1ADDR(x)		({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
@@ -313,7 +320,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCI2_IO_BASE	0x00000000
 #define CONFIG_SYS_PCI2_IO_PHYS	(CONFIG_SYS_PCI1_IO_PHYS \
 				 + CONFIG_SYS_PCI1_IO_SIZE)
-#define CONFIG_SYS_PCI2_IO_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCI2_IO_SIZE	CONFIG_SYS_PCI1_IO_SIZE
 
 #if defined(CONFIG_PCI)
 
@@ -413,8 +420,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif	/* CONFIG_TSEC_ENET */
 
 /*
- * BAT0		2G     Cacheable, non-guarded
- * 0x0000_0000	2G     DDR
+ * BAT0		DDR
  */
 #define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_DBAT0U	(BATU_BL_2G | BATU_VS | BATU_VP)
@@ -422,22 +428,20 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_IBAT0U	CONFIG_SYS_DBAT0U
 
 /*
- * BAT1		unused
+ * BAT1		LBC (PIXIS/CF)
  */
-#define CONFIG_SYS_DBAT1L	0
-#define CONFIG_SYS_DBAT1U	0
-#define CONFIG_SYS_IBAT1L	0
-#define CONFIG_SYS_IBAT1U	0
+#define CONFIG_SYS_DBAT1L	(CONFIG_SYS_LBC_BASE | BATL_PP_RW \
+				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_LBC_BASE | BATU_BL_128K \
+				 | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_LBC_BASE | BATL_PP_RW \
+				 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
 
 /* if CONFIG_PCI:
- * BAT2		1G     Cache-inhibited, guarded
- * 0x8000_0000	512M   PCI-Express 1 Memory
- * 0xa000_0000	512M   PCI-Express 2 Memory
- *	Changed it for operating from 0xd0000000
- *
+ * BAT2		PCI1 and PCI1 MEM
  * if CONFIG_RIO
- * BAT2		512M   Cache-inhibited, guarded
- * 0xc000_0000	512M   RapidIO Memory
+ * BAT2		Rapidio Memory
  */
 #ifdef CONFIG_PCI
 #define CONFIG_SYS_DBAT2L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
@@ -456,30 +460,27 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
 
 /*
- * BAT3		4M     Cache-inhibited, guarded
- * 0xf800_0000	4M     CCSR
+ * BAT3		CCSR Space
  */
 #define CONFIG_SYS_DBAT3L	( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
+				 | BATU_VP)
 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
 
 /*
- * BAT4		32M    Cache-inhibited, guarded
- * 0xe200_0000	16M    PCI-Express 1 I/O
- * 0xe300_0000	16M    PCI-Express 2 I/0
- *    Note that this is at 0xe0000000
+ * BAT4		PCI1_IO and PCI2_IO
  */
 #define CONFIG_SYS_DBAT4L	( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_128K \
+				 | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
 
 /*
- * BAT5		128K   Cacheable, non-guarded
- * 0xe401_0000	128K   Init RAM for stack in the CPU DCache (no backing memory)
+ * BAT5		Init RAM for stack in the CPU DCache (no backing memory)
  */
 #define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
@@ -487,8 +488,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
 
 /*
- * BAT6		8M    Cache-inhibited, guarded
- * 0xff80_0000	8M    FLASH
+ * BAT6		FLASH
  */
 #define CONFIG_SYS_DBAT6L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW \
 				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
@@ -506,7 +506,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 				 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
 
-/* Leave BAT7 free here - it is used for various things later */
+/*
+ * BAT7		FREE - used later for tmp mappings
+ */
 #define CONFIG_SYS_DBAT7L 0x00000000
 #define CONFIG_SYS_DBAT7U 0x00000000
 #define CONFIG_SYS_IBAT7L 0x00000000
-- 
cgit v1.3.1


From 3111d32c494e8251b90917447796a7206b757e1e Mon Sep 17 00:00:00 2001
From: Becky Bruce <becky.bruce@freescale.com>
Date: Thu, 6 Nov 2008 17:37:35 -0600
Subject: mpc8641: Support 36-bit physical addressing

This patch creates a memory map with all the devices
in 36-bit physical space, in addition to the 32-bit map.
The CCSR relocation is moved (again, sorry) to
allow for the physical address to be 36 bits - this
requires translation to be enabled.  With 36-bit physical
addressing enabled, we are no longer running with VA=PA
translations.  This means we have to distinguish between
the two in the config file.  The existing region name is
used to indicate the virtual address, and a _PHYS variety
is created to represent the physical address.

Large physical addressing is not enabled by default.
Set CONFIG_PHYS_64BIT in the config file to turn this on.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
 board/freescale/mpc8641hpcn/law.c |  13 +--
 cpu/mpc86xx/start.S               |  44 +++++++---
 doc/README.mpc8641hpcn            |  24 ++++++
 include/configs/MPC8641HPCN.h     | 164 +++++++++++++++++++++++++++++---------
 4 files changed, 192 insertions(+), 53 deletions(-)

(limited to 'cpu')

diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c
index 669a091691c..bd357b86670 100644
--- a/board/freescale/mpc8641hpcn/law.c
+++ b/board/freescale/mpc8641hpcn/law.c
@@ -31,12 +31,13 @@
  * LAW(Local Access Window) configuration:
  *
  * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * if PCI
+ * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
  * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
  * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
- * else if RIO
+ * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
  * 0x8000_0000     0x9fff_ffff     RapidIO                 512M
  * endif
+ * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT)
  * 0xffc0_0000     0xffc0_ffff     PCI1 IO                 64K
  * 0xffc1_0000     0xffc1_ffff     PCI2 IO                 64K
  * 0xffe0_0000     0xffef_ffff     CCSRBAR                 1M
@@ -53,15 +54,15 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
 #endif
 #ifdef CONFIG_PCI
-	SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
 	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
 #elif defined(CONFIG_RIO)
 	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 #endif
-	SET_LAW(PIXIS_BASE, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
+	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 0aa8a4feaab..efd654ce76d 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -209,11 +209,6 @@ boot_warm:
 	sync
 #endif
 
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
-	/* setup ccsrbar now while we're in real mode */
-	bl      setup_ccsrbar
-#endif
-
 	/*
 	 * Calculate absolute address in FLASH and jump there
 	 *------------------------------------------------------*/
@@ -267,6 +262,10 @@ addr_trans_enabled:
 	sync
 #endif
 
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+	bl      setup_ccsrbar
+#endif
+
 	/* set up the stack pointer in our newly created
 	 * cache-ram (r1) */
 	lis	r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
@@ -414,6 +413,26 @@ early_bats:
 	mtspr   DBAT6L, r4
 	mtspr   DBAT6U, r3
 	isync
+
+#if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+	/* IBAT 7 */
+	lis	r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h
+	ori     r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l
+	lis	r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h
+	ori     r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l
+	mtspr   IBAT7L, r4
+	mtspr   IBAT7U, r3
+	isync
+
+	/* DBAT 7 */
+	lis	r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h
+	ori     r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l
+	lis	r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h
+	ori     r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l
+	mtspr   DBAT7L, r4
+	mtspr   DBAT7U, r3
+	isync
+#endif
 	blr
 
 	.globl clear_tlbs
@@ -860,17 +879,20 @@ setup_ccsrbar:
 	lis	r4, CONFIG_SYS_CCSRBAR_DEFAULT@h
 	ori	r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l
 
-	lis	r5, CONFIG_SYS_CCSRBAR@h
-	ori	r5, r5, CONFIG_SYS_CCSRBAR@l
-	srwi	r6,r5,12
-	stw	r6, 0(r4)
+	lis	r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
+	ori	r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
+	srwi	r5,r5,12
+	li	r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
+	rlwimi	r5,r6,20,8,11
+	stw	r5, 0(r4) /* Store physical value of CCSR */
 	isync
 
-	lis	r5, 0xffff
-	ori	r5,r5,0xf000
+	lis	r5, TEXT_BASE@h
+	ori	r5,r5,TEXT_BASE@l
 	lwz	r5, 0(r5)
 	isync
 
+	/* Use VA of CCSR to do read */
 	lis	r3, CONFIG_SYS_CCSRBAR@h
 	lwz	r5, CONFIG_SYS_CCSRBAR@l(r3)
 	isync
diff --git a/doc/README.mpc8641hpcn b/doc/README.mpc8641hpcn
index 0a6e715bc28..5ac39e67822 100644
--- a/doc/README.mpc8641hpcn
+++ b/doc/README.mpc8641hpcn
@@ -113,6 +113,9 @@ To Flash U-boot into the alternative bank (0xEF800000 - 0xEFBFFFFF):
 -------------
 NOTE:  RIO and PCI are mutually exclusive, so they share an address
 
+For 32-bit u-boot, devices are mapped so that the virtual address ==
+the physical address, and the map looks liks this:
+
 	Memory Range			Device		Size
 	------------			------		----
 	0x0000_0000	0x7fff_ffff	DDR		2G
@@ -127,6 +130,27 @@ NOTE:  RIO and PCI are mutually exclusive, so they share an address
 	0xffc1_0000	0xffc1_ffff	PCI2/PEX2 IO	64K
 	0xef80_0000	0xefff_ffff	Flash		8M
 
+For 36-bit-enabled u-boot, the virtual map is the same as for 32-bit.
+However, the physical map is altered to reside in 36-bit space, as follows.
+Addresses are no longer mapped with VA == PA.  All accesses from
+software use the VA; the PA is only used for setting up windows
+and mappings. Note that the low 32 bits are the same as the VA above;
+only the top 4 bits vary:
+
+	Memory Range			Device		Size
+	------------			------		----
+	0x0_0000_0000	0x0_7fff_ffff	DDR		2G
+	0xc_8000_0000	0xc_9fff_ffff	RIO MEM		512M
+	0xc_8000_0000	0xc_9fff_ffff	PCI1/PEX1 MEM	512M
+	0xc_a000_0000	0xc_bfff_ffff	PCI2/PEX2 MEM	512M
+	0xf_ffe0_0000	0xf_ffef_ffff	CCSR		1M
+	0xf_ffdf_0000	0xf_ffdf_7fff	PIXIS		8K
+	0xf_ffdf_8000	0xf_ffdf_ffff	CF		8K
+	0x0_f840_0000	0xf_f840_3fff	Stack space	32K
+	0xf_ffc0_0000	0xf_ffc0_ffff	PCI1/PEX1 IO	64K
+	0xf_ffc1_0000	0xf_ffc1_ffff	PCI2/PEX2 IO	64K
+	0xf_ef80_0000	0xf_efff_ffff	Flash		8M
+
 5. pixis_reset command
 --------------------
 A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index ec3d112c2f9..c84ae5e832b 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -38,6 +38,7 @@
 #define CONFIG_MPC8641HPCN	1	/* MPC8641HPCN board specific */
 #define CONFIG_NUM_CPUS		2	/* Number of CPUs in the system */
 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
+/*#define CONFIG_PHYS_64BIT	1*/	/* Place devices in 36-bit space */
 
 #ifdef RUN_DIAG
 #define CONFIG_SYS_DIAG_ADDR	     CONFIG_SYS_FLASH_BASE
@@ -91,6 +92,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 
+/*
+ * With the exception of PCI Memory and Rapid IO, most devices will simply
+ * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
+ * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
+ */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL
+#else
+#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0
+#endif
+
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
@@ -99,6 +111,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
+/* Physical addresses */
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0xf
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
+#endif
+
 #define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)
 #define CONFIG_SYS_PCI2_ADDR		(CONFIG_SYS_CCSRBAR+0x9000)
 
@@ -160,23 +180,31 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 
 #define CONFIG_SYS_FLASH_BASE		0xef800000     /* start of FLASH 8M */
+#define CONFIG_SYS_FLASH_BASE_PHYS	(CONFIG_SYS_FLASH_BASE \
+					 | CONFIG_SYS_PHYS_ADDR_HIGH)
+
 
 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
 
 /* Convert an address into the right format for the BR registers */
+#ifdef CONFIG_PHYS_64BIT
+#define BR_PHYS_ADDR(x)	((unsigned long)((x & 0x0ffff8000ULL) | \
+					 ((x & 0x300000000ULL) >> 19)))
+#else
 #define BR_PHYS_ADDR(x) (x & 0xffff8000)
+#endif
 
-#define CONFIG_SYS_BR0_PRELIM		(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) \
-					 | 0x00001001)	/* port size 16bit */
-#define CONFIG_SYS_OR0_PRELIM		0xff806ff7	/* 8MB Boot Flash area*/
+#define CONFIG_SYS_BR0_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+				 | 0x00001001)	/* port size 16bit */
+#define CONFIG_SYS_OR0_PRELIM	0xff806ff7	/* 8MB Boot Flash area*/
 
-#define CONFIG_SYS_BR2_PRELIM		(BR_PHYS_ADDR(CF_BASE)		\
-					 | 0x00001001)	/* port size 16bit */
-#define CONFIG_SYS_OR2_PRELIM		0xffffeff7	/* 32k Compact Flash */
+#define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(CF_BASE_PHYS)		\
+				 | 0x00001001)	/* port size 16bit */
+#define CONFIG_SYS_OR2_PRELIM	0xffffeff7	/* 32k Compact Flash */
 
-#define CONFIG_SYS_BR3_PRELIM		(BR_PHYS_ADDR(PIXIS_BASE)	\
-					 | 0x00000801) /* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32k PIXIS area*/
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS)	\
+				 | 0x00000801) /* port size 8bit */
+#define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32k PIXIS area*/
 
 /*
  * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
@@ -184,9 +212,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * required for the smallest BAT mapping, so there's a 64k hole.
  */
 #define CONFIG_SYS_LBC_BASE		0xffde0000
+#define CONFIG_SYS_LBC_BASE_PHYS	(CONFIG_SYS_LBC_BASE \
+					 | CONFIG_SYS_PHYS_ADDR_HIGH)
 
 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
 #define PIXIS_BASE		(CONFIG_SYS_LBC_BASE + 0x00010000)
+#define PIXIS_BASE_PHYS 	(CONFIG_SYS_LBC_BASE_PHYS + 0x00010000)
 #define PIXIS_SIZE		0x00008000	/* 32k */
 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
 #define PIXIS_VER		0x1	/* Board version at offset 1 */
@@ -206,6 +237,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
 #define CF_BASE			(PIXIS_BASE + PIXIS_SIZE)
+#define CF_BASE_PHYS		(PIXIS_BASE_PHYS + PIXIS_SIZE)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
@@ -295,7 +327,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * RapidIO MMU
  */
 #define CONFIG_SYS_RIO_MEM_BASE	0x80000000	/* base address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_RIO_MEM_PHYS  0x0000000c00000000ULL
+#else
 #define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BASE
+#endif
 #define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
 
 /*
@@ -303,10 +339,16 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * Addresses are mapped 1-1.
  */
 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x0000000c00000000ULL
+#else
 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#endif
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS	0xffc00000
+#define CONFIG_SYS_PCI1_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCI1_IO_PHYS	(CONFIG_SYS_PCI1_IO_VIRT \
+				 | CONFIG_SYS_PHYS_ADDR_HIGH)
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64K */
 
 /* For RTL8139 */
@@ -315,9 +357,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_SYS_PCI2_MEM_BASE 	(CONFIG_SYS_PCI1_MEM_BASE \
 					 + CONFIG_SYS_PCI1_MEM_SIZE)
-#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_PHYS	(CONFIG_SYS_PCI1_MEM_PHYS \
+					 + CONFIG_SYS_PCI1_MEM_SIZE)
 #define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCI2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \
+				 + CONFIG_SYS_PCI1_IO_SIZE)
 #define CONFIG_SYS_PCI2_IO_PHYS	(CONFIG_SYS_PCI1_IO_PHYS \
 				 + CONFIG_SYS_PCI1_IO_SIZE)
 #define CONFIG_SYS_PCI2_IO_SIZE	CONFIG_SYS_PCI1_IO_SIZE
@@ -349,10 +394,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
 
 /*PCIE video card used*/
-#define VIDEO_IO_OFFSET		CONFIG_SYS_PCI2_IO_PHYS
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCI2_IO_VIRT
 
 /*PCI video card used*/
-/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_PHYS*/
+/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_VIRT*/
 
 /* video */
 #define CONFIG_VIDEO
@@ -365,7 +410,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_ATI_RADEON_FB
 #define CONFIG_VIDEO_LOGO
 /*#define CONFIG_CONSOLE_CURSOR*/
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_PHYS
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
@@ -419,6 +464,21 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #endif	/* CONFIG_TSEC_ENET */
 
+/*  Contort an addr into the format needed for BATs */
+#ifdef CONFIG_PHYS_64BIT
+#define BAT_PHYS_ADDR(x)         ((unsigned long) \
+				  ((x & 0x00000000ffffffffULL) |	\
+				   ((x & 0x0000000e00000000ULL) >> 24) | \
+				   ((x & 0x0000000100000000ULL) >> 30)))
+#else
+#define BAT_PHYS_ADDR(x)        (x)
+#endif
+
+
+/* Put high physical address bits into the BAT format */
+#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
+#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
+
 /*
  * BAT0		DDR
  */
@@ -430,12 +490,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * BAT1		LBC (PIXIS/CF)
  */
-#define CONFIG_SYS_DBAT1L	(CONFIG_SYS_LBC_BASE | BATL_PP_RW \
-				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
+				 BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT1U	(CONFIG_SYS_LBC_BASE | BATU_BL_128K \
 				 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_LBC_BASE | BATL_PP_RW \
-				 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
+				 | BATL_PP_RW | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
 
 /* if CONFIG_PCI:
@@ -444,14 +505,23 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * BAT2		Rapidio Memory
  */
 #ifdef CONFIG_PCI
-#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
-				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G \
+#define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT \
+				 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_1G \
 				 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
-				 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
 #else /* CONFIG_RIO */
+#define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \
+				 | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT)
+
 #define CONFIG_SYS_DBAT2L	(CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT2U	(CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
@@ -461,22 +531,43 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 /*
  * BAT3		CCSR Space
+ * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs
+ * instead.  The assembler chokes on ULL.
  */
-#define CONFIG_SYS_DBAT3L	( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
-			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_CCSRBAR_PHYS_LOW \
+				 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+				 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT \
+				 | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
 				 | BATU_VP)
-#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR_PHYS_LOW \
+				 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+				 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
 
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT \
+				       | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
 /*
  * BAT4		PCI1_IO and PCI2_IO
  */
-#define CONFIG_SYS_DBAT4L	( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
-			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_128K \
+#define CONFIG_SYS_DBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT \
+				 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \
 				 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
 
 /*
@@ -490,12 +581,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * BAT6		FLASH
  */
-#define CONFIG_SYS_DBAT6L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW \
-				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT \
+				 | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
 				 | BATU_VP)
-#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW \
-				 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+				 | BATL_PP_RW | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
 
 /* Map the last 1M of flash where we're running from reset */
@@ -652,8 +744,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 	"ramdiskfile=your.ramdisk.u-boot\0"				\
 	"fdtaddr=c00000\0"						\
 	"fdtfile=mpc8641_hpcn.dtb\0"					\
-	"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
-	"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+	"en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"			\
+	"dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
 	"maxcpus=2"
 
 
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