From ab0df36fc7db9dda0b786b909f653e279dfeb9cf Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Fri, 29 Aug 2008 21:09:49 +0200 Subject: avr32: refactor the portmux/gpio code - Separate the portmux configuration functionality from the GPIO pin control API. - Separate the controller-specific code from the chip-specific code. - Allow "ganged" port configuration (multiple pins at once). - Add more flexibility to the "canned" peripheral select functions: - Allow using more than 23 address bits, more chip selects, as well as NAND- and CF-specific pins. - Make the MACB SPEED pin optional, and choose between MII/RMII using a parameter instead of an #ifdef. - Make it possible to use other MMC slots than slot 0, and support different MMC/SDCard data bus widths. - Use more reasonable pull-up defaults; floating pins may consume a lot of power. - Get rid of some custom portmux code from the mimc200 board code. The old gpio/portmux API couldn't really handle its requirements, but the new one can. - Add documentation. The end result is slightly smaller code for all boards. Which isn't really the point, but at least it isn't any larger. This has been verified on ATSTK1002 and ATNGW100. I'd appreciate if the board maintainers could help me test this on their boards. In particular, the mimc200 port has lost a lot of code, so I'm hoping Mark can help me out. Signed-off-by: Haavard Skinnemoen Cc: Hans-Christian Egtvedt Cc: Mark Jackson Cc: Alex Raimondi Cc: Julien May Changes since v1: * Enable pullup on NWAIT * Add missing include to portmux-pio.h * Rename CONFIG_PIO2 -> CONFIG_PORTMUX_PIO to match docs --- cpu/at32ap/Makefile | 2 +- cpu/at32ap/at32ap700x/Makefile | 2 +- cpu/at32ap/at32ap700x/gpio.c | 199 --------------------------------------- cpu/at32ap/at32ap700x/portmux.c | 204 ++++++++++++++++++++++++++++++++++++++++ cpu/at32ap/pio.c | 116 ----------------------- cpu/at32ap/portmux-pio.c | 92 ++++++++++++++++++ 6 files changed, 298 insertions(+), 317 deletions(-) delete mode 100644 cpu/at32ap/at32ap700x/gpio.c create mode 100644 cpu/at32ap/at32ap700x/portmux.c delete mode 100644 cpu/at32ap/pio.c create mode 100644 cpu/at32ap/portmux-pio.c (limited to 'cpu') diff --git a/cpu/at32ap/Makefile b/cpu/at32ap/Makefile index 33dc4276815..100cf3e74a4 100644 --- a/cpu/at32ap/Makefile +++ b/cpu/at32ap/Makefile @@ -34,7 +34,7 @@ COBJS-y += hsdramc.o COBJS-y += exception.o COBJS-y += cache.o COBJS-y += interrupts.o -COBJS-y += pio.o +COBJS-$(CONFIG_PORTMUX_PIO) += portmux-pio.o SRCS := $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/cpu/at32ap/at32ap700x/Makefile b/cpu/at32ap/at32ap700x/Makefile index 740423563ed..46e6ef661a4 100644 --- a/cpu/at32ap/at32ap700x/Makefile +++ b/cpu/at32ap/at32ap700x/Makefile @@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)lib$(SOC).a -COBJS := gpio.o clk.o +COBJS := portmux.o clk.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/at32ap/at32ap700x/gpio.c b/cpu/at32ap/at32ap700x/gpio.c deleted file mode 100644 index 56ba2f90c69..00000000000 --- a/cpu/at32ap/at32ap700x/gpio.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include - -#include - -#include -#include -#include - -/* - * Lots of small functions here. We depend on --gc-sections getting - * rid of the ones we don't need. - */ -void gpio_enable_ebi(void) -{ -#ifdef CFG_HSDRAMC -#ifndef CFG_SDRAM_16BIT - gpio_select_periph_A(GPIO_PIN_PE0, 0); - gpio_select_periph_A(GPIO_PIN_PE1, 0); - gpio_select_periph_A(GPIO_PIN_PE2, 0); - gpio_select_periph_A(GPIO_PIN_PE3, 0); - gpio_select_periph_A(GPIO_PIN_PE4, 0); - gpio_select_periph_A(GPIO_PIN_PE5, 0); - gpio_select_periph_A(GPIO_PIN_PE6, 0); - gpio_select_periph_A(GPIO_PIN_PE7, 0); - gpio_select_periph_A(GPIO_PIN_PE8, 0); - gpio_select_periph_A(GPIO_PIN_PE9, 0); - gpio_select_periph_A(GPIO_PIN_PE10, 0); - gpio_select_periph_A(GPIO_PIN_PE11, 0); - gpio_select_periph_A(GPIO_PIN_PE12, 0); - gpio_select_periph_A(GPIO_PIN_PE13, 0); - gpio_select_periph_A(GPIO_PIN_PE14, 0); - gpio_select_periph_A(GPIO_PIN_PE15, 0); -#endif - gpio_select_periph_A(GPIO_PIN_PE26, 0); -#endif -} - -#ifdef AT32AP700x_CHIP_HAS_USART -void gpio_enable_usart0(void) -{ - gpio_select_periph_B(GPIO_PIN_PA8, 0); - gpio_select_periph_B(GPIO_PIN_PA9, 0); -} - -void gpio_enable_usart1(void) -{ - gpio_select_periph_A(GPIO_PIN_PA17, 0); - gpio_select_periph_A(GPIO_PIN_PA18, 0); -} - -void gpio_enable_usart2(void) -{ - gpio_select_periph_B(GPIO_PIN_PB26, 0); - gpio_select_periph_B(GPIO_PIN_PB27, 0); -} - -void gpio_enable_usart3(void) -{ - gpio_select_periph_B(GPIO_PIN_PB17, 0); - gpio_select_periph_B(GPIO_PIN_PB18, 0); -} -#endif - -#ifdef AT32AP700x_CHIP_HAS_MACB -void gpio_enable_macb0(void) -{ - gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */ - gpio_select_periph_A(GPIO_PIN_PC4, 0); /* TXD1 */ - gpio_select_periph_A(GPIO_PIN_PC7, 0); /* TXEN */ - gpio_select_periph_A(GPIO_PIN_PC8, 0); /* TXCK */ - gpio_select_periph_A(GPIO_PIN_PC9, 0); /* RXD0 */ - gpio_select_periph_A(GPIO_PIN_PC10, 0); /* RXD1 */ - gpio_select_periph_A(GPIO_PIN_PC13, 0); /* RXER */ - gpio_select_periph_A(GPIO_PIN_PC15, 0); /* RXDV */ - gpio_select_periph_A(GPIO_PIN_PC16, 0); /* MDC */ - gpio_select_periph_A(GPIO_PIN_PC17, 0); /* MDIO */ -#if !defined(CONFIG_RMII) - gpio_select_periph_A(GPIO_PIN_PC0, 0); /* COL */ - gpio_select_periph_A(GPIO_PIN_PC1, 0); /* CRS */ - gpio_select_periph_A(GPIO_PIN_PC2, 0); /* TXER */ - gpio_select_periph_A(GPIO_PIN_PC5, 0); /* TXD2 */ - gpio_select_periph_A(GPIO_PIN_PC6, 0); /* TXD3 */ - gpio_select_periph_A(GPIO_PIN_PC11, 0); /* RXD2 */ - gpio_select_periph_A(GPIO_PIN_PC12, 0); /* RXD3 */ - gpio_select_periph_A(GPIO_PIN_PC14, 0); /* RXCK */ - gpio_select_periph_A(GPIO_PIN_PC18, 0); /* SPD */ -#endif -} - -void gpio_enable_macb1(void) -{ - gpio_select_periph_B(GPIO_PIN_PD13, 0); /* TXD0 */ - gpio_select_periph_B(GPIO_PIN_PD14, 0); /* TXD1 */ - gpio_select_periph_B(GPIO_PIN_PD11, 0); /* TXEN */ - gpio_select_periph_B(GPIO_PIN_PD12, 0); /* TXCK */ - gpio_select_periph_B(GPIO_PIN_PD10, 0); /* RXD0 */ - gpio_select_periph_B(GPIO_PIN_PD6, 0); /* RXD1 */ - gpio_select_periph_B(GPIO_PIN_PD5, 0); /* RXER */ - gpio_select_periph_B(GPIO_PIN_PD4, 0); /* RXDV */ - gpio_select_periph_B(GPIO_PIN_PD3, 0); /* MDC */ - gpio_select_periph_B(GPIO_PIN_PD2, 0); /* MDIO */ -#if !defined(CONFIG_RMII) - gpio_select_periph_B(GPIO_PIN_PC19, 0); /* COL */ - gpio_select_periph_B(GPIO_PIN_PC23, 0); /* CRS */ - gpio_select_periph_B(GPIO_PIN_PC26, 0); /* TXER */ - gpio_select_periph_B(GPIO_PIN_PC27, 0); /* TXD2 */ - gpio_select_periph_B(GPIO_PIN_PC28, 0); /* TXD3 */ - gpio_select_periph_B(GPIO_PIN_PC29, 0); /* RXD2 */ - gpio_select_periph_B(GPIO_PIN_PC30, 0); /* RXD3 */ - gpio_select_periph_B(GPIO_PIN_PC24, 0); /* RXCK */ - gpio_select_periph_B(GPIO_PIN_PD15, 0); /* SPD */ -#endif -} -#endif - -#ifdef AT32AP700x_CHIP_HAS_MMCI -void gpio_enable_mmci(void) -{ - gpio_select_periph_A(GPIO_PIN_PA10, 0); /* CLK */ - gpio_select_periph_A(GPIO_PIN_PA11, 0); /* CMD */ - gpio_select_periph_A(GPIO_PIN_PA12, 0); /* DATA0 */ - gpio_select_periph_A(GPIO_PIN_PA13, 0); /* DATA1 */ - gpio_select_periph_A(GPIO_PIN_PA14, 0); /* DATA2 */ - gpio_select_periph_A(GPIO_PIN_PA15, 0); /* DATA3 */ -} -#endif - -#ifdef AT32AP700x_CHIP_HAS_SPI -void gpio_enable_spi0(unsigned long cs_mask) -{ - gpio_select_periph_A(GPIO_PIN_PA0, 0); /* MISO */ - gpio_select_periph_A(GPIO_PIN_PA1, 0); /* MOSI */ - gpio_select_periph_A(GPIO_PIN_PA2, 0); /* SCK */ - - /* Set up NPCSx as GPIO outputs, initially high */ - if (cs_mask & (1 << 0)) { - gpio_set_value(GPIO_PIN_PA3, 1); - gpio_select_pio(GPIO_PIN_PA3, GPIOF_OUTPUT); - } - if (cs_mask & (1 << 1)) { - gpio_set_value(GPIO_PIN_PA4, 1); - gpio_select_pio(GPIO_PIN_PA4, GPIOF_OUTPUT); - } - if (cs_mask & (1 << 2)) { - gpio_set_value(GPIO_PIN_PA5, 1); - gpio_select_pio(GPIO_PIN_PA5, GPIOF_OUTPUT); - } - if (cs_mask & (1 << 3)) { - gpio_set_value(GPIO_PIN_PA20, 1); - gpio_select_pio(GPIO_PIN_PA20, GPIOF_OUTPUT); - } -} - -void gpio_enable_spi1(unsigned long cs_mask) -{ - gpio_select_periph_B(GPIO_PIN_PA0, 0); /* MISO */ - gpio_select_periph_B(GPIO_PIN_PB1, 0); /* MOSI */ - gpio_select_periph_B(GPIO_PIN_PB5, 0); /* SCK */ - - /* Set up NPCSx as GPIO outputs, initially high */ - if (cs_mask & (1 << 0)) { - gpio_set_value(GPIO_PIN_PB2, 1); - gpio_select_pio(GPIO_PIN_PB2, GPIOF_OUTPUT); - } - if (cs_mask & (1 << 1)) { - gpio_set_value(GPIO_PIN_PB3, 1); - gpio_select_pio(GPIO_PIN_PB3, GPIOF_OUTPUT); - } - if (cs_mask & (1 << 2)) { - gpio_set_value(GPIO_PIN_PB4, 1); - gpio_select_pio(GPIO_PIN_PB4, GPIOF_OUTPUT); - } - if (cs_mask & (1 << 3)) { - gpio_set_value(GPIO_PIN_PA27, 1); - gpio_select_pio(GPIO_PIN_PA27, GPIOF_OUTPUT); - } -} -#endif diff --git a/cpu/at32ap/at32ap700x/portmux.c b/cpu/at32ap/at32ap700x/portmux.c new file mode 100644 index 00000000000..2a3b004b049 --- /dev/null +++ b/cpu/at32ap/at32ap700x/portmux.c @@ -0,0 +1,204 @@ +/* + * Copyright (C) 2006, 2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include + +#include +#include +#include + +/* + * Lots of small functions here. We depend on --gc-sections getting + * rid of the ones we don't need. + */ +void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width, + unsigned long flags, unsigned long drive_strength) +{ + unsigned long porte_mask = 0; + + if (bus_width > 16) + portmux_select_peripheral(PORTMUX_PORT_E, 0xffff, + PORTMUX_FUNC_A, PORTMUX_BUSKEEPER); + if (addr_width > 23) + porte_mask |= (((1 << (addr_width - 23)) - 1) & 7) << 16; + if (flags & PORTMUX_EBI_CS(2)) + porte_mask |= 1 << 25; + if (flags & PORTMUX_EBI_CS(4)) + porte_mask |= 1 << 21; + if (flags & PORTMUX_EBI_CS(5)) + porte_mask |= 1 << 22; + if (flags & (PORTMUX_EBI_CF(0) | PORTMUX_EBI_CF(1))) + porte_mask |= (1 << 19) | (1 << 20) | (1 << 23); + + portmux_select_peripheral(PORTMUX_PORT_E, porte_mask, + PORTMUX_FUNC_A, 0); + + if (flags & PORTMUX_EBI_NWAIT) + portmux_select_peripheral(PORTMUX_PORT_E, 1 << 24, + PORTMUX_FUNC_A, PORTMUX_PULL_UP); +} + +#ifdef AT32AP700x_CHIP_HAS_MACB +void portmux_enable_macb0(unsigned long flags, unsigned long drive_strength) +{ + unsigned long portc_mask; + + portc_mask = (1 << 3) /* TXD0 */ + | (1 << 4) /* TXD1 */ + | (1 << 7) /* TXEN */ + | (1 << 8) /* TXCK */ + | (1 << 9) /* RXD0 */ + | (1 << 10) /* RXD1 */ + | (1 << 13) /* RXER */ + | (1 << 15) /* RXDV */ + | (1 << 16) /* MDC */ + | (1 << 17); /* MDIO */ + + if (flags & PORTMUX_MACB_MII) + portc_mask |= (1 << 0) /* COL */ + | (1 << 1) /* CRS */ + | (1 << 2) /* TXER */ + | (1 << 5) /* TXD2 */ + | (1 << 6) /* TXD3 */ + | (1 << 11) /* RXD2 */ + | (1 << 12) /* RXD3 */ + | (1 << 14); /* RXCK */ + + if (flags & PORTMUX_MACB_SPEED) + portc_mask |= (1 << 18);/* SPD */ + + /* REVISIT: Some pins are probably pure outputs */ + portmux_select_peripheral(PORTMUX_PORT_C, portc_mask, + PORTMUX_FUNC_A, PORTMUX_BUSKEEPER); +} + +void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength) +{ + unsigned long portc_mask = 0; + unsigned long portd_mask; + + portd_mask = (1 << 13) /* TXD0 */ + | (1 << 14) /* TXD1 */ + | (1 << 11) /* TXEN */ + | (1 << 12) /* TXCK */ + | (1 << 10) /* RXD0 */ + | (1 << 6) /* RXD1 */ + | (1 << 5) /* RXER */ + | (1 << 4) /* RXDV */ + | (1 << 3) /* MDC */ + | (1 << 2); /* MDIO */ + + if (flags & PORTMUX_MACB_MII) + portc_mask = (1 << 19) /* COL */ + | (1 << 23) /* CRS */ + | (1 << 26) /* TXER */ + | (1 << 27) /* TXD2 */ + | (1 << 28) /* TXD3 */ + | (1 << 29) /* RXD2 */ + | (1 << 30) /* RXD3 */ + | (1 << 24); /* RXCK */ + + if (flags & PORTMUX_MACB_SPEED) + portd_mask |= (1 << 15);/* SPD */ + + /* REVISIT: Some pins are probably pure outputs */ + portmux_select_peripheral(PORTMUX_PORT_D, portc_mask, + PORTMUX_FUNC_B, PORTMUX_BUSKEEPER); + portmux_select_peripheral(PORTMUX_PORT_C, portc_mask, + PORTMUX_FUNC_B, PORTMUX_BUSKEEPER); +} +#endif + +#ifdef AT32AP700x_CHIP_HAS_MMCI +void portmux_enable_mmci(unsigned int slot, unsigned long flags, + unsigned long drive_strength) +{ + unsigned long mask; + unsigned long portmux_flags = PORTMUX_PULL_UP; + + /* First, the common CLK signal. It doesn't need a pull-up */ + portmux_select_peripheral(PORTMUX_PORT_A, 1 << 10, + PORTMUX_FUNC_A, 0); + + if (flags & PORTMUX_MMCI_EXT_PULLUP) + portmux_flags = 0; + + /* Then, the per-slot signals */ + switch (slot) { + case 0: + mask = (1 << 11) | (1 << 12); /* CMD and DATA0 */ + if (flags & PORTMUX_MMCI_4BIT) + /* DATA1..DATA3 */ + mask |= (1 << 13) | (1 << 14) | (1 << 15); + portmux_select_peripheral(PORTMUX_PORT_A, mask, + PORTMUX_FUNC_A, portmux_flags); + break; + case 1: + mask = (1 << 6) | (1 << 7); /* CMD and DATA0 */ + if (flags & PORTMUX_MMCI_4BIT) + /* DATA1..DATA3 */ + mask |= (1 << 8) | (1 << 9) | (1 << 10); + portmux_select_peripheral(PORTMUX_PORT_B, mask, + PORTMUX_FUNC_B, portmux_flags); + break; + } +} +#endif + +#ifdef AT32AP700x_CHIP_HAS_SPI +void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength) +{ + unsigned long pin_mask; + + /* MOSI and SCK */ + portmux_select_peripheral(PORTMUX_PORT_A, (1 << 1) | (1 << 2), + PORTMUX_FUNC_A, 0); + /* MISO may float */ + portmux_select_peripheral(PORTMUX_PORT_A, 1 << 0, + PORTMUX_FUNC_A, PORTMUX_BUSKEEPER); + + /* Set up NPCSx as GPIO outputs, initially high */ + pin_mask = (cs_mask & 7) << 3; + if (cs_mask & (1 << 3)) + pin_mask |= 1 << 20; + + portmux_select_gpio(PORTMUX_PORT_A, pin_mask, + PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); +} + +void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength) +{ + /* MOSI and SCK */ + portmux_select_peripheral(PORTMUX_PORT_B, (1 << 1) | (1 << 5), + PORTMUX_FUNC_B, 0); + /* MISO may float */ + portmux_select_peripheral(PORTMUX_PORT_B, 1 << 0, + PORTMUX_FUNC_B, PORTMUX_BUSKEEPER); + + /* Set up NPCSx as GPIO outputs, initially high */ + portmux_select_gpio(PORTMUX_PORT_B, (cs_mask & 7) << 2, + PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); + portmux_select_gpio(PORTMUX_PORT_A, (cs_mask & 8) << (27 - 3), + PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); +} +#endif diff --git a/cpu/at32ap/pio.c b/cpu/at32ap/pio.c deleted file mode 100644 index f64004b6591..00000000000 --- a/cpu/at32ap/pio.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include - -#include -#include -#include - -#include "pio2.h" - -void gpio_select_periph_A(unsigned int pin, int use_pullup) -{ - void *base = gpio_pin_to_addr(pin); - uint32_t mask = 1 << (pin & 0x1f); - - if (!base) - panic("Invalid GPIO pin %u\n", pin); - - pio2_writel(base, ASR, mask); - pio2_writel(base, PDR, mask); - if (use_pullup) - pio2_writel(base, PUER, mask); - else - pio2_writel(base, PUDR, mask); -} - -void gpio_select_periph_B(unsigned int pin, int use_pullup) -{ - void *base = gpio_pin_to_addr(pin); - uint32_t mask = 1 << (pin & 0x1f); - - if (!base) - panic("Invalid GPIO pin %u\n", pin); - - pio2_writel(base, BSR, mask); - pio2_writel(base, PDR, mask); - if (use_pullup) - pio2_writel(base, PUER, mask); - else - pio2_writel(base, PUDR, mask); -} - -void gpio_select_pio(unsigned int pin, unsigned long gpiof_flags) -{ - void *base = gpio_pin_to_addr(pin); - uint32_t mask = 1 << (pin & 0x1f); - - if (!base) - panic("Invalid GPIO pin %u\n", pin); - - if (gpiof_flags & GPIOF_OUTPUT) { - if (gpiof_flags & GPIOF_MULTIDRV) - pio2_writel(base, MDER, mask); - else - pio2_writel(base, MDDR, mask); - pio2_writel(base, PUDR, mask); - pio2_writel(base, OER, mask); - } else { - if (gpiof_flags & GPIOF_PULLUP) - pio2_writel(base, PUER, mask); - else - pio2_writel(base, PUDR, mask); - if (gpiof_flags & GPIOF_DEGLITCH) - pio2_writel(base, IFER, mask); - else - pio2_writel(base, IFDR, mask); - pio2_writel(base, ODR, mask); - } - - pio2_writel(base, PER, mask); -} - -void gpio_set_value(unsigned int pin, int value) -{ - void *base = gpio_pin_to_addr(pin); - uint32_t mask = 1 << (pin & 0x1f); - - if (!base) - panic("Invalid GPIO pin %u\n", pin); - - if (value) - pio2_writel(base, SODR, mask); - else - pio2_writel(base, CODR, mask); -} - -int gpio_get_value(unsigned int pin) -{ - void *base = gpio_pin_to_addr(pin); - int value; - - if (!base) - panic("Invalid GPIO pin %u\n", pin); - - value = pio2_readl(base, PDSR); - return (value >> (pin & 0x1f)) & 1; -} diff --git a/cpu/at32ap/portmux-pio.c b/cpu/at32ap/portmux-pio.c new file mode 100644 index 00000000000..a29f94e3ba4 --- /dev/null +++ b/cpu/at32ap/portmux-pio.c @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2006, 2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include +#include + +void portmux_select_peripheral(void *port, unsigned long pin_mask, + enum portmux_function func, unsigned long flags) +{ + if (flags & PORTMUX_PULL_UP) + pio_writel(port, PUER, pin_mask); + else + pio_writel(port, PUDR, pin_mask); + + switch (func) { + case PORTMUX_FUNC_A: + pio_writel(port, ASR, pin_mask); + break; + case PORTMUX_FUNC_B: + pio_writel(port, BSR, pin_mask); + break; + } + + pio_writel(port, PDR, pin_mask); +} + +void portmux_select_gpio(void *port, unsigned long pin_mask, + unsigned long flags) +{ + if (flags & PORTMUX_PULL_UP) + pio_writel(port, PUER, pin_mask); + else + pio_writel(port, PUDR, pin_mask); + + if (flags & PORTMUX_OPEN_DRAIN) + pio_writel(port, MDER, pin_mask); + else + pio_writel(port, MDDR, pin_mask); + + if (flags & PORTMUX_DIR_OUTPUT) { + if (flags & PORTMUX_INIT_HIGH) + pio_writel(port, SODR, pin_mask); + else + pio_writel(port, CODR, pin_mask); + pio_writel(port, OER, pin_mask); + } else { + pio_writel(port, ODR, pin_mask); + } + + pio_writel(port, PER, pin_mask); +} + +void pio_set_output_value(unsigned int pin, int value) +{ + void *port = pio_pin_to_port(pin); + + if (!port) + panic("Invalid GPIO pin %u\n", pin); + + __pio_set_output_value(port, pin & 0x1f, value); +} + +int pio_get_input_value(unsigned int pin) +{ + void *port = pio_pin_to_port(pin); + + if (!port) + panic("Invalid GPIO pin %u\n", pin); + + return __pio_get_input_value(port, pin & 0x1f); +} -- cgit v1.3.1 From 98090cd75cdb40b2ab94c806c338540a5716748b Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Sun, 31 Aug 2008 18:05:32 +0200 Subject: avr32: Add gclk helper functions Add two helper functions for configuring and enabling generic clocks: - gclk_enable_output: Enables output on a GCLKx pin - gclk_set_rate: Configures a gclk to run at a specific rate This should eliminate any reason to go mucking about with PM registers from board code. Signed-off-by: Haavard Skinnemoen --- cpu/at32ap/at32ap700x/clk.c | 25 +++++++++ include/asm-avr32/arch-at32ap700x/clk.h | 99 ++++++++++++++++++++++++++++++++- 2 files changed, 122 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/at32ap/at32ap700x/clk.c b/cpu/at32ap/at32ap700x/clk.c index b3aa03495f5..a6a6c885e51 100644 --- a/cpu/at32ap/at32ap700x/clk.c +++ b/cpu/at32ap/at32ap700x/clk.c @@ -25,6 +25,7 @@ #include #include +#include #include "sm.h" @@ -66,3 +67,27 @@ void clk_init(void) sm_writel(PM_MCCTRL, SM_BIT(PLLSEL)); #endif } + +unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent, + unsigned long rate, unsigned long parent_rate) +{ + unsigned long divider; + + if (rate == 0 || parent_rate == 0) { + sm_writel(PM_GCCTRL(id), 0); + return 0; + } + + divider = (parent_rate + rate / 2) / rate; + if (divider <= 1) { + sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN)); + rate = parent_rate; + } else { + divider = min(255, divider / 2 - 1); + sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN) | SM_BIT(DIVEN) + | SM_BF(DIV, divider)); + rate = parent_rate / (2 * (divider + 1)); + } + + return rate; +} diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h index e9a4fe4d649..b2710a4ba85 100644 --- a/include/asm-avr32/arch-at32ap700x/clk.h +++ b/include/asm-avr32/arch-at32ap700x/clk.h @@ -23,11 +23,13 @@ #define __ASM_AVR32_ARCH_CLK_H__ #include +#include #ifdef CONFIG_PLL -#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) +#define PLL0_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) +#define MAIN_CLK_RATE PLL0_RATE #else -#define MAIN_CLK_RATE (CFG_OSC0_HZ) +#define MAIN_CLK_RATE (CFG_OSC0_HZ) #endif static inline unsigned long get_cpu_clk_rate(void) @@ -87,4 +89,97 @@ extern void gclk_init(void) __attribute__((weak)); /* Board code may need the SDRAM base clock as a compile-time constant */ #define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB) +/* Generic clock control */ +enum gclk_parent { + GCLK_PARENT_OSC0 = 0, + GCLK_PARENT_OSC1 = 1, + GCLK_PARENT_PLL0 = 2, + GCLK_PARENT_PLL1 = 3, +}; + +/* Some generic clocks have specific roles */ +#define GCLK_DAC_SAMPLE_CLK 6 +#define GCLK_LCDC_PIXCLK 7 + +extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent, + unsigned long rate, unsigned long parent_rate); + +/** + * gclk_set_rate - configure and enable a generic clock + * @id: Which GCLK[id] to enable + * @parent: Parent clock feeding the GCLK + * @rate: Target rate of the GCLK in Hz + * + * Returns the actual GCLK rate in Hz, after rounding to the nearest + * supported rate. + * + * All three parameters are usually constant, hence the inline. + */ +static inline unsigned long gclk_set_rate(unsigned int id, + enum gclk_parent parent, unsigned long rate) +{ + unsigned long parent_rate; + + if (id > 7) + return 0; + + switch (parent) { + case GCLK_PARENT_OSC0: + parent_rate = CFG_OSC0_HZ; + break; +#ifdef CFG_OSC1_HZ + case GCLK_PARENT_OSC1: + parent_rate = CFG_OSC1_HZ; + break; +#endif +#ifdef PLL0_RATE + case GCLK_PARENT_PLL0: + parent_rate = PLL0_RATE; + break; +#endif +#ifdef PLL1_RATE + case GCLK_PARENT_PLL1: + parent_rate = PLL1_RATE; + break; +#endif + default: + parent_rate = 0; + break; + } + + return __gclk_set_rate(id, parent, rate, parent_rate); +} + +/** + * gclk_enable_output - enable output on a GCLK pin + * @id: Which GCLK[id] pin to enable + * @drive_strength: Drive strength of external GCLK pin, if applicable + */ +static inline void gclk_enable_output(unsigned int id, + unsigned long drive_strength) +{ + switch (id) { + case 0: + portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30, + PORTMUX_FUNC_A, drive_strength); + break; + case 1: + portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31, + PORTMUX_FUNC_A, drive_strength); + break; + case 2: + portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19, + PORTMUX_FUNC_A, drive_strength); + break; + case 3: + portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29, + PORTMUX_FUNC_A, drive_strength); + break; + case 4: + portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30, + PORTMUX_FUNC_A, drive_strength); + break; + } +} + #endif /* __ASM_AVR32_ARCH_CLK_H__ */ -- cgit v1.3.1 From 36d375faf5cff98e8dca32aabbbb1ec6036437dd Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Sun, 31 Aug 2008 18:24:24 +0200 Subject: avr32: Use board_postclk_init instead of gclk_init Replace the avr32-specific gclk_init() board hook with the standard board_postclk_init() hook which is supposed to run at the same point during initialization. Provide a dummy weak alias for boards not implementing this hook. The cost of this is: - 2 bytes for the dummy function (retal 0) - 2 bytes for each unnecessary function call (short rcall) which is a pretty small price to pay for avoiding lots of #ifdef clutter. In this particular case, all boards probably end up slightly smaller because we avoid the conditional checking if the gclk_init symbol is NULL. Signed-off-by: Haavard Skinnemoen --- board/miromico/hammerhead/hammerhead.c | 3 ++- cpu/at32ap/cpu.c | 3 --- include/asm-avr32/arch-at32ap700x/clk.h | 1 - lib_avr32/board.c | 8 ++++++++ 4 files changed, 10 insertions(+), 5 deletions(-) (limited to 'cpu') diff --git a/board/miromico/hammerhead/hammerhead.c b/board/miromico/hammerhead/hammerhead.c index bf432cba85a..8670527891e 100644 --- a/board/miromico/hammerhead/hammerhead.c +++ b/board/miromico/hammerhead/hammerhead.c @@ -100,9 +100,10 @@ void board_init_info(void) gd->bd->bi_phy_id[0] = 0x01; } -void gclk_init(void) +int board_postclk_init(void) { /* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */ gclk_enable_output(3, PORTMUX_DRIVE_LOW); gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000); + return 0; } diff --git a/cpu/at32ap/cpu.c b/cpu/at32ap/cpu.c index 1a1370289d5..0ba836180e4 100644 --- a/cpu/at32ap/cpu.c +++ b/cpu/at32ap/cpu.c @@ -65,9 +65,6 @@ int cpu_init(void) sysreg_write(EVBA, (unsigned long)&_evba); asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET)); - if(gclk_init) - gclk_init(); - return 0; } diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h index b2710a4ba85..21545a3c185 100644 --- a/include/asm-avr32/arch-at32ap700x/clk.h +++ b/include/asm-avr32/arch-at32ap700x/clk.h @@ -84,7 +84,6 @@ static inline unsigned long get_spi_clk_rate(unsigned int dev_id) #endif extern void clk_init(void); -extern void gclk_init(void) __attribute__((weak)); /* Board code may need the SDRAM base clock as a compile-time constant */ #define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB) diff --git a/lib_avr32/board.c b/lib_avr32/board.c index d6423d4f3f9..19d76d2cacc 100644 --- a/lib_avr32/board.c +++ b/lib_avr32/board.c @@ -47,6 +47,13 @@ static unsigned long mem_malloc_start = 0; static unsigned long mem_malloc_end = 0; static unsigned long mem_malloc_brk = 0; +/* Weak aliases for optional board functions */ +static int __do_nothing(void) +{ + return 0; +} +int board_postclk_init(void) __attribute__((weak, alias("__do_nothing"))); + /* The malloc area is right below the monitor image in RAM */ static void mem_malloc_init(void) { @@ -187,6 +194,7 @@ void board_init_f(ulong board_type) /* Perform initialization sequence */ board_early_init_f(); cpu_init(); + board_postclk_init(); env_init(); init_baudrate(); serial_init(); -- cgit v1.3.1 From baf449fc5ff96f071bb0e3789fd3265f6d4fd9a0 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Mon, 1 Sep 2008 14:00:07 +0200 Subject: avr32: Add support for "GPIO" port mux The "GPIO" port mux is used on AVR32 UC3 parts as well as AT32AP7200 and all later AVR32 chips. This patch adds a driver for it, implementing the same API as the existing portmux-pio driver but with more functionality. Signed-off-by: Haavard Skinnemoen --- cpu/at32ap/Makefile | 1 + cpu/at32ap/portmux-gpio.c | 107 +++++++++++++++ include/asm-avr32/arch-common/portmux-gpio.h | 193 +++++++++++++++++++++++++++ 3 files changed, 301 insertions(+) create mode 100644 cpu/at32ap/portmux-gpio.c create mode 100644 include/asm-avr32/arch-common/portmux-gpio.h (limited to 'cpu') diff --git a/cpu/at32ap/Makefile b/cpu/at32ap/Makefile index 100cf3e74a4..e08f27383da 100644 --- a/cpu/at32ap/Makefile +++ b/cpu/at32ap/Makefile @@ -35,6 +35,7 @@ COBJS-y += exception.o COBJS-y += cache.o COBJS-y += interrupts.o COBJS-$(CONFIG_PORTMUX_PIO) += portmux-pio.o +COBJS-$(CONFIG_PORTMUX_GPIO) += portmux-gpio.o SRCS := $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/cpu/at32ap/portmux-gpio.c b/cpu/at32ap/portmux-gpio.c new file mode 100644 index 00000000000..9acd040d1be --- /dev/null +++ b/cpu/at32ap/portmux-gpio.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include +#include + +void portmux_select_peripheral(void *port, unsigned long pin_mask, + enum portmux_function func, unsigned long flags) +{ + /* Both pull-up and pull-down set means buskeeper */ + if (flags & PORTMUX_PULL_DOWN) + gpio_writel(port, PDERS, pin_mask); + else + gpio_writel(port, PDERC, pin_mask); + if (flags & PORTMUX_PULL_UP) + gpio_writel(port, PUERS, pin_mask); + else + gpio_writel(port, PUERC, pin_mask); + + /* Select drive strength */ + if (flags & PORTMUX_DRIVE_LOW) + gpio_writel(port, ODCR0S, pin_mask); + else + gpio_writel(port, ODCR0C, pin_mask); + if (flags & PORTMUX_DRIVE_HIGH) + gpio_writel(port, ODCR1S, pin_mask); + else + gpio_writel(port, ODCR1C, pin_mask); + + /* Select function */ + if (func & PORTMUX_FUNC_B) + gpio_writel(port, PMR0S, pin_mask); + else + gpio_writel(port, PMR0C, pin_mask); + if (func & PORTMUX_FUNC_C) + gpio_writel(port, PMR1S, pin_mask); + else + gpio_writel(port, PMR1C, pin_mask); + + /* Disable GPIO (i.e. enable peripheral) */ + gpio_writel(port, GPERC, pin_mask); +} + +void portmux_select_gpio(void *port, unsigned long pin_mask, + unsigned long flags) +{ + /* Both pull-up and pull-down set means buskeeper */ + if (flags & PORTMUX_PULL_DOWN) + gpio_writel(port, PDERS, pin_mask); + else + gpio_writel(port, PDERC, pin_mask); + if (flags & PORTMUX_PULL_UP) + gpio_writel(port, PUERS, pin_mask); + else + gpio_writel(port, PUERC, pin_mask); + + /* Enable open-drain mode if requested */ + if (flags & PORTMUX_OPEN_DRAIN) + gpio_writel(port, ODMERS, pin_mask); + else + gpio_writel(port, ODMERC, pin_mask); + + /* Select drive strength */ + if (flags & PORTMUX_DRIVE_LOW) + gpio_writel(port, ODCR0S, pin_mask); + else + gpio_writel(port, ODCR0C, pin_mask); + if (flags & PORTMUX_DRIVE_HIGH) + gpio_writel(port, ODCR1S, pin_mask); + else + gpio_writel(port, ODCR1C, pin_mask); + + /* Select direction and initial pin state */ + if (flags & PORTMUX_DIR_OUTPUT) { + if (flags & PORTMUX_INIT_HIGH) + gpio_writel(port, OVRS, pin_mask); + else + gpio_writel(port, OVRC, pin_mask); + gpio_writel(port, ODERS, pin_mask); + } else { + gpio_writel(port, ODERC, pin_mask); + } + + /* Enable GPIO */ + gpio_writel(port, GPERS, pin_mask); +} diff --git a/include/asm-avr32/arch-common/portmux-gpio.h b/include/asm-avr32/arch-common/portmux-gpio.h new file mode 100644 index 00000000000..24943ecdbd4 --- /dev/null +++ b/include/asm-avr32/arch-common/portmux-gpio.h @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __AVR32_PORTMUX_GPIO_H__ +#define __AVR32_PORTMUX_GPIO_H__ + +#include + +/* Register offsets */ +struct gpio_regs { + u32 GPER; + u32 GPERS; + u32 GPERC; + u32 GPERT; + u32 PMR0; + u32 PMR0S; + u32 PMR0C; + u32 PMR0T; + u32 PMR1; + u32 PMR1S; + u32 PMR1C; + u32 PMR1T; + u32 __reserved0[4]; + u32 ODER; + u32 ODERS; + u32 ODERC; + u32 ODERT; + u32 OVR; + u32 OVRS; + u32 OVRC; + u32 OVRT; + u32 PVR; + u32 __reserved_PVRS; + u32 __reserved_PVRC; + u32 __reserved_PVRT; + u32 PUER; + u32 PUERS; + u32 PUERC; + u32 PUERT; + u32 PDER; + u32 PDERS; + u32 PDERC; + u32 PDERT; + u32 IER; + u32 IERS; + u32 IERC; + u32 IERT; + u32 IMR0; + u32 IMR0S; + u32 IMR0C; + u32 IMR0T; + u32 IMR1; + u32 IMR1S; + u32 IMR1C; + u32 IMR1T; + u32 GFER; + u32 GFERS; + u32 GFERC; + u32 GFERT; + u32 IFR; + u32 __reserved_IFRS; + u32 IFRC; + u32 __reserved_IFRT; + u32 ODMER; + u32 ODMERS; + u32 ODMERC; + u32 ODMERT; + u32 __reserved1[4]; + u32 ODCR0; + u32 ODCR0S; + u32 ODCR0C; + u32 ODCR0T; + u32 ODCR1; + u32 ODCR1S; + u32 ODCR1C; + u32 ODCR1T; + u32 __reserved2[4]; + u32 OSRR0; + u32 OSRR0S; + u32 OSRR0C; + u32 OSRR0T; + u32 __reserved3[8]; + u32 STER; + u32 STERS; + u32 STERC; + u32 STERT; + u32 __reserved4[35]; + u32 VERSION; +}; + +/* Register access macros */ +#define gpio_readl(port, reg) \ + __raw_readl(&((struct gpio_regs *)port)->reg) +#define gpio_writel(gpio, reg, value) \ + __raw_writel(value, &((struct gpio_regs *)port)->reg) + +/* Portmux API starts here. See doc/README.AVR32-port-muxing */ + +enum portmux_function { + PORTMUX_FUNC_A, + PORTMUX_FUNC_B, + PORTMUX_FUNC_C, + PORTMUX_FUNC_D, +}; + +#define PORTMUX_DIR_INPUT (0 << 0) +#define PORTMUX_DIR_OUTPUT (1 << 0) +#define PORTMUX_INIT_LOW (0 << 1) +#define PORTMUX_INIT_HIGH (1 << 1) +#define PORTMUX_PULL_UP (1 << 2) +#define PORTMUX_PULL_DOWN (2 << 2) +#define PORTMUX_BUSKEEPER (3 << 2) +#define PORTMUX_DRIVE_MIN (0 << 4) +#define PORTMUX_DRIVE_LOW (1 << 4) +#define PORTMUX_DRIVE_HIGH (2 << 4) +#define PORTMUX_DRIVE_MAX (3 << 4) +#define PORTMUX_OPEN_DRAIN (1 << 6) + +void portmux_select_peripheral(void *port, unsigned long pin_mask, + enum portmux_function func, unsigned long flags); +void portmux_select_gpio(void *port, unsigned long pin_mask, + unsigned long flags); + +/* Internal helper functions */ + +static inline void *gpio_pin_to_port(unsigned int pin) +{ + return (void *)GPIO_BASE + (pin >> 5) * 0x200; +} + +static inline void __gpio_set_output_value(void *port, unsigned int pin, + int value) +{ + if (value) + gpio_writel(port, OVRS, 1 << pin); + else + gpio_writel(port, OVRC, 1 << pin); +} + +static inline int __gpio_get_input_value(void *port, unsigned int pin) +{ + return (gpio_readl(port, PVR) >> pin) & 1; +} + +void gpio_set_output_value(unsigned int pin, int value); +int gpio_get_input_value(unsigned int pin); + +/* GPIO API starts here */ + +/* + * GCC doesn't realize that the constant case is extremely trivial, + * so we need to help it make the right decision by using + * always_inline. + */ +__attribute__((always_inline)) +static inline void gpio_set_value(unsigned int pin, int value) +{ + if (__builtin_constant_p(pin)) + __gpio_set_output_value(gpio_pin_to_port(pin), + pin & 0x1f, value); + else + gpio_set_output_value(pin, value); +} + +__attribute__((always_inline)) +static inline int gpio_get_value(unsigned int pin) +{ + if (__builtin_constant_p(pin)) + return __gpio_get_input_value(gpio_pin_to_port(pin), + pin & 0x1f); + else + return gpio_get_input_value(pin); +} + +#endif /* __AVR32_PORTMUX_GPIO_H__ */ -- cgit v1.3.1