From f64702b7fc8f8df39d31add770df6e372f9e9ce3 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 30 Apr 2007 13:59:50 -0500 Subject: Fix memory initialization on MPC8349E-mITX Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP. This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary on some ITX boards, notably those with a revision 3.1 CPU. Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into ddr->sdram_clk_cntl if CFG_DDR_SDRAM_CLK_CNTL is not defined. Signed-off-by: Timur Tabi Acked-by: Michael Benedict Signed-off-by: Kim Phillips --- cpu/mpc83xx/spd_sdram.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 41a1f1fc7b0..647813f68d9 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -693,11 +693,6 @@ long int spd_sdram() #ifdef CFG_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; -#else - /* SS_EN = 0, source synchronous disable - * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd - */ - ddr->sdram_clk_cntl = 0x00000000; #endif debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl); -- cgit v1.3.1