From 656d8da9d2862afd293ae678d37a486d34b76ca2 Mon Sep 17 00:00:00 2001 From: Breno Matheus Lima Date: Wed, 5 Jun 2019 18:18:30 +0000 Subject: doc: Remove duplicated documentation directory Commit ad7061ed742e ("doc: Move device tree bindings documentation to doc/device-tree-bindings") moved all device tree binding documentation to doc/device-tree-bindings directory. The current U-Boot project still have two documentation directories: - doc/ - Documentation/ Move all documentation and sphinx files to doc directory so all content can be in a common place. Signed-off-by: Breno Lima --- doc/device-tree-bindings/cpu/fsl,mpc83xx.txt | 34 ++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 doc/device-tree-bindings/cpu/fsl,mpc83xx.txt (limited to 'doc/device-tree-bindings/cpu') diff --git a/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt b/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt new file mode 100644 index 00000000000..ac563d906ac --- /dev/null +++ b/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt @@ -0,0 +1,34 @@ +MPC83xx CPU devices + +MPC83xx SoCs contain a e300 core as their main processor. + +Required properties: +- compatible: must be one of "fsl,mpc83xx", + "fsl,mpc8308", + "fsl,mpc8309", + "fsl,mpc8313", + "fsl,mpc8315", + "fsl,mpc832x", + "fsl,mpc8349", + "fsl,mpc8360", + "fsl,mpc8379" +- clocks: has to have two entries, which must be the core clock at index 0 and + the CSB (Coherent System Bus) clock at index 1. Both are given by a suitable + "fsl,mpc83xx-clk" device + +Example: + +socclocks: clocks { + compatible = "fsl,mpc8315-clk"; + #clock-cells = <1>; +}; + +cpus { + compatible = "cpu_bus"; + + PowerPC,8315@0 { + compatible = "fsl,mpc8315"; + clocks = <&socclocks MPC83XX_CLK_CORE + &socclocks MPC83XX_CLK_CSB>; + }; +}; -- cgit v1.2.3