From 8d78a6b67467145f7e02295ca5d4944251dbc645 Mon Sep 17 00:00:00 2001 From: Peter Hoyes Date: Fri, 4 Mar 2022 16:30:18 +0000 Subject: vexpress64: Add ARMv8R-64 board variant The ARMv8-R64 architecture introduces optional VMSA (paging based MMU) support in the EL1/0 translation regime, which makes that part mostly compatible to ARMv8-A. Add a new board variant to describe the "BASE-R64" FVP model, which inherits a lot from the existing v8-A FVP support. One major difference is that the memory map in "inverted": DRAM starts at 0x0, MMIO is at 2GB [1]. * Create new TARGET_VEXPRESS64_BASER_FVP target, sharing most of the exising configuration. * Implement inverted memory map in vexpress_aemv8.h * Create vexpress_aemv8r defconfig * Provide an MMU memory map for the BASER_FVP * Update vexpress64 documentation At the moment the boot-wrapper is the only supported secure firmware. As there is no official DT for the board yet, we rely on it being supplied by the boot-wrapper into U-Boot, so use OF_HAS_PRIOR_STAGE, and go with a dummy DT for now. [1] https://developer.arm.com/documentation/100964/1114/Base-Platform/Base---memory/BaseR-Platform-memory-map Signed-off-by: Peter Hoyes [Andre: rebase and add Linux kernel header] Signed-off-by: Andre Przywara [trini: Add MAINTAINERS entry for Peter] --- doc/arch/arm64.rst | 3 ++- doc/board/armltd/vexpress64.rst | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'doc') diff --git a/doc/arch/arm64.rst b/doc/arch/arm64.rst index 80498f6f6b8..7c0713504c4 100644 --- a/doc/arch/arm64.rst +++ b/doc/arch/arm64.rst @@ -18,7 +18,8 @@ Notes classical firmware (like initial hardware setup, CPU errata workarounds or SMP bringup). U-Boot can be entered in EL2 when its main purpose is that of a boot loader. It can drop to lower exception levels before - entering the OS. + entering the OS. For ARMv8-R it is recommened to enter at S-EL1, as for this + architecture there is no S-EL3. 2. U-Boot for arm64 is compiled with AArch64-gcc. AArch64-gcc use rela relocation format, a tool(tools/relocate-rela) by Scott Wood diff --git a/doc/board/armltd/vexpress64.rst b/doc/board/armltd/vexpress64.rst index d87b1c38f5b..a7f771d2667 100644 --- a/doc/board/armltd/vexpress64.rst +++ b/doc/board/armltd/vexpress64.rst @@ -6,6 +6,7 @@ Arm Versatile Express The vexpress_* board configuration supports the following platforms: * FVP_Base_RevC-2xAEMvA + * FVP_BaseR_AEMv8R * Juno development board Fixed Virtual Platforms -- cgit v1.3.1 From d0ed9b10810f17c5b5cb2ee962c6d4df29a65a9c Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:09 -0400 Subject: doc: Convert semihosting readme to rST This converts the semihosting readme to rST. I have tried to make only cosmetic changes, but I did fix up the first link (which was broken). Signed-off-by: Sean Anderson --- doc/README.semihosting | 38 -------------------------------------- doc/usage/index.rst | 1 + doc/usage/semihosting.rst | 43 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 44 insertions(+), 38 deletions(-) delete mode 100644 doc/README.semihosting create mode 100644 doc/usage/semihosting.rst (limited to 'doc') diff --git a/doc/README.semihosting b/doc/README.semihosting deleted file mode 100644 index f382d0131eb..00000000000 --- a/doc/README.semihosting +++ /dev/null @@ -1,38 +0,0 @@ -SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Broadcom Corporation. - */ - -Semihosting is ARM's way of having a real or virtual target communicate -with a host or host debugger for basic operations such as file I/O, -console I/O, etc. Please see -http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/Bgbjjgij.html for more information. - -For developing on armv8 virtual fastmodel platforms, semihosting is a -valuable tool since it allows access to image/configuration files before -eMMC or other NV media are available. - -There are two main ARM virtual Fixed Virtual Platform (FVP) models, -Versatile Express (VE) FVP and BASE FVP (See -http://www.arm.com/products/tools/models/fast-models/foundation-model.php) -The initial vexpress64 u-boot board created here runs on the VE virtual -platform using the license-free Foundation_v8 simulator. Fortunately, -the Foundation_v8 simulator also supports the BASE_FVP model which -companies can purchase licenses for and contain much more functionality. -So we can, in u-boot, run either model by either using the VE FVP (default), -or turning on CONFIG_BASE_FVP for the more full featured model. - -Rather than create a new armv8 board similar to armltd/vexpress64, add -semihosting calls to the existing one, enabled with CONFIG_SEMIHOSTING -and CONFIG_BASE_FVP both set. Also reuse the existing board config file -vexpress_aemv8.h but differentiate the two models by the presence or -absence of CONFIG_BASE_FVP. This change is tested and works on both the -Foundation and Base fastmodel simulators. - -The semihosting code adds a command: - - smhload
[env var] - -That will load an image from the host filesystem into RAM at the specified -address and optionally store the load end address in the specified -environment variable. diff --git a/doc/usage/index.rst b/doc/usage/index.rst index 5b42579dfc6..3e520530c62 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -11,6 +11,7 @@ Use U-Boot netconsole partitions cmdline + semihosting Shell commands -------------- diff --git a/doc/usage/semihosting.rst b/doc/usage/semihosting.rst new file mode 100644 index 00000000000..ed16e4d582e --- /dev/null +++ b/doc/usage/semihosting.rst @@ -0,0 +1,43 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright 2014 Broadcom Corporation. + +Semihosting +=========== + +Semihosting is ARM's way of having a real or virtual target communicate +with a host or host debugger for basic operations such as file I/O, +console I/O, etc. Please see `Arm's semihosting documentation +`_ for more +information. + +For developing on armv8 virtual fastmodel platforms, semihosting is a +valuable tool since it allows access to image/configuration files before +eMMC or other NV media are available. + +There are two main ARM virtual Fixed Virtual Platform (FVP) models, +`Versatile Express (VE) FVP and BASE FVP +`_. +The initial vexpress64 u-boot board created here runs on the VE virtual +platform using the license-free Foundation_v8 simulator. Fortunately, +the Foundation_v8 simulator also supports the BASE_FVP model which +companies can purchase licenses for and contain much more functionality. +So we can, in U-Boot, run either model by either using the VE FVP (default), +or turning on ``CONFIG_BASE_FVP`` for the more full featured model. + +Rather than create a new armv8 board similar to ``armltd/vexpress64``, add +semihosting calls to the existing one, enabled with ``CONFIG_SEMIHOSTING`` +and ``CONFIG_BASE_FVP`` both set. Also reuse the existing board config file +vexpress_aemv8.h but differentiate the two models by the presence or +absence of ``CONFIG_BASE_FVP``. This change is tested and works on both the +Foundation and Base fastmodel simulators. + +Loading files +------------- + +The semihosting code adds a "hostfs":: + + smhload
[env var] + +That will load an image from the host filesystem into RAM at the specified +address and optionally store the load end address in the specified +environment variable. -- cgit v1.3.1 From 71230cdaa9597d410f1e8aca62ea5a0daeebc0ac Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:10 -0400 Subject: nxp: ls1046ardb: Convert README to rST This converts the readme for this board to rST. I have tried not to change any semantics from the original (though I did convert MB to M). Signed-off-by: Sean Anderson --- board/freescale/ls1046ardb/MAINTAINERS | 1 + board/freescale/ls1046ardb/README | 76 ------------------------- doc/board/nxp/index.rst | 1 + doc/board/nxp/ls1046ardb.rst | 100 +++++++++++++++++++++++++++++++++ 4 files changed, 102 insertions(+), 76 deletions(-) delete mode 100644 board/freescale/ls1046ardb/README create mode 100644 doc/board/nxp/ls1046ardb.rst (limited to 'doc') diff --git a/board/freescale/ls1046ardb/MAINTAINERS b/board/freescale/ls1046ardb/MAINTAINERS index efdea22bdeb..3c8cfe720dc 100644 --- a/board/freescale/ls1046ardb/MAINTAINERS +++ b/board/freescale/ls1046ardb/MAINTAINERS @@ -14,3 +14,4 @@ F: configs/ls1046ardb_tfa_SECURE_BOOT_defconfig F: configs/ls1046ardb_SECURE_BOOT_defconfig F: configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig F: configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +F: doc/board/nxp/ls1046ardb.rst diff --git a/board/freescale/ls1046ardb/README b/board/freescale/ls1046ardb/README deleted file mode 100644 index 90c44f4bce3..00000000000 --- a/board/freescale/ls1046ardb/README +++ /dev/null @@ -1,76 +0,0 @@ -Overview --------- -The LS1046A Reference Design Board (RDB) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS1046A -LayerScape Architecture processor. The LS1046ARDB provides SW development -platform for the Freescale LS1046A processor series, with a complete -debugging environment. The LS1046A RDB is lead-free and RoHS-compliant. - -LS1046A SoC Overview --------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A -SoC overview. - - LS1046ARDB board Overview - ----------------------- - - SERDES1 Connections, 4 lanes supporting: - - Lane0: 10GBase-R with x1 RJ45 connector - - Lane1: 10GBase-R Cage - - Lane2: SGMII.5 - - Lane3: SGMII.6 - - SERDES2 Connections, 4 lanes supporting: - - Lane0: PCIe1 with miniPCIe slot - - Lane1: PCIe2 with PCIe x2 slot - - Lane2: PCIe3 with PCIe x4 slot - - Lane3: SATA - - DDR Controller - - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s - -IFC/Local Bus - - One 512 MB NAND flash with ECC support - - CPLD connection - - USB 3.0 - - one Type A port, one Micro-AB port - - SDHC: connects directly to a full SD/MMC slot - - DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz) - - 4 I2C controllers - - UART - - Two 4-pin serial ports at up to 115.2 Kbit/s - - Two DB9 D-Type connectors supporting one Serial port each - - ARM JTAG support - -Memory map from core's view ----------------------------- -Start Address End Address Description Size -0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB -0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB -0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB -0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB -0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB -0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB -0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB -0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB -0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M -0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M -0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB -0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G -0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G -0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G - -QSPI flash map: -Start Address End Address Description Size -0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI 1MB -0x00_4010_0000 - 0x00_402F_FFFF U-Boot 2MB -0x00_4030_0000 - 0x00_403F_FFFF U-Boot Env 1MB -0x00_4040_0000 - 0x00_405F_FFFF PPA 2MB -0x00_4060_0000 - 0x00_408F_FFFF Secure boot header - + bootscript 3MB -0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB -0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB -0x00_4098_0000 - 0x00_40FF_FFFF Reserved 6MB -0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB - -Booting Options ---------------- -a) QSPI boot -b) SD boot -c) eMMC boot diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst index 63956287c5b..4514b8951ba 100644 --- a/doc/board/nxp/index.rst +++ b/doc/board/nxp/index.rst @@ -13,6 +13,7 @@ NXP Semiconductors imx8qxp_mek imxrt1020-evk imxrt1050-evk + ls1046ardb mx6sabreauto mx6sabresd mx6ul_14x14_evk diff --git a/doc/board/nxp/ls1046ardb.rst b/doc/board/nxp/ls1046ardb.rst new file mode 100644 index 00000000000..4bfeaa93ddb --- /dev/null +++ b/doc/board/nxp/ls1046ardb.rst @@ -0,0 +1,100 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +LS1046ARDB +========== + +The LS1046A Reference Design Board (RDB) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS1046A +LayerScape Architecture processor. The LS1046ARDB provides SW development +platform for the Freescale LS1046A processor series, with a complete +debugging environment. The LS1046A RDB is lead-free and RoHS-compliant. + +LS1046A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A +SoC overview. + +LS1046ARDB board Overview +------------------------- +- SERDES1 Connections, 4 lanes supporting: + + - Lane0: 10GBase-R with x1 RJ45 connector + - Lane1: 10GBase-R Cage + - Lane2: SGMII.5 + - Lane3: SGMII.6 + +- SERDES2 Connections, 4 lanes supporting: + + - Lane0: PCIe1 with miniPCIe slot + - Lane1: PCIe2 with PCIe x2 slot + - Lane2: PCIe3 with PCIe x4 slot + - Lane3: SATA + +- DDR Controller + + - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s + +- IFC/Local Bus + + - One 512 MB NAND flash with ECC support + - CPLD connection + +- USB 3.0 + + - one Type A port, one Micro-AB port + +- SDHC: connects directly to a full SD/MMC slot +- DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz) +- 4 I2C controllers +- UART + + - Two 4-pin serial ports at up to 115.2 Kbit/s + - Two DB9 D-Type connectors supporting one Serial port each + +- ARM JTAG support + +Memory map from core's view +---------------------------- + +================== ================== ================ ===== +Start Address End Address Description Size +================== ================== ================ ===== +``0x00_0000_0000`` ``0x00_000F_FFFF`` Secure Boot ROM 1M +``0x00_0100_0000`` ``0x00_0FFF_FFFF`` CCSRBAR 240M +``0x00_1000_0000`` ``0x00_1000_FFFF`` OCRAM0 64K +``0x00_1001_0000`` ``0x00_1001_FFFF`` OCRAM1 64K +``0x00_2000_0000`` ``0x00_20FF_FFFF`` DCSR 16M +``0x00_7E80_0000`` ``0x00_7E80_FFFF`` IFC - NAND Flash 64K +``0x00_7FB0_0000`` ``0x00_7FB0_0FFF`` IFC - CPLD 4K +``0x00_8000_0000`` ``0x00_FFFF_FFFF`` DRAM1 2G +``0x05_0000_0000`` ``0x05_07FF_FFFF`` QMAN S/W Portal 128M +``0x05_0800_0000`` ``0x05_0FFF_FFFF`` BMAN S/W Portal 128M +``0x08_8000_0000`` ``0x09_FFFF_FFFF`` DRAM2 6G +``0x40_0000_0000`` ``0x47_FFFF_FFFF`` PCI Express1 32G +``0x48_0000_0000`` ``0x4F_FFFF_FFFF`` PCI Express2 32G +``0x50_0000_0000`` ``0x57_FFFF_FFFF`` PCI Express3 32G +================== ================== ================ ===== + +QSPI flash map +-------------- + +================== ================== ================== ===== +Start Address End Address Description Size +================== ================== ================== ===== +``0x00_4000_0000`` ``0x00_400F_FFFF`` RCW + PBI 1M +``0x00_4010_0000`` ``0x00_402F_FFFF`` U-Boot 2M +``0x00_4030_0000`` ``0x00_403F_FFFF`` U-Boot Env 1M +``0x00_4040_0000`` ``0x00_405F_FFFF`` PPA 2M +``0x00_4060_0000`` ``0x00_408F_FFFF`` Secure boot header 3M + + bootscript +``0x00_4090_0000`` ``0x00_4093_FFFF`` FMan ucode 256K +``0x00_4094_0000`` ``0x00_4097_FFFF`` QE/uQE firmware 256K +``0x00_4098_0000`` ``0x00_40FF_FFFF`` Reserved 6M +``0x00_4100_0000`` ``0x00_43FF_FFFF`` FIT Image 48M +================== ================== ================== ===== + +Booting Options +--------------- +- QSPI boot +- SD boot +- eMMC boot -- cgit v1.3.1 From b5ec417b56bfbd6685247f58a26592052ab0f42e Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:11 -0400 Subject: doc: ls1046ardb: Expand boot mode section This adds some additional info about booting from different sources, including the correct switch positions. Signed-off-by: Sean Anderson --- doc/board/nxp/ls1046ardb.rst | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) (limited to 'doc') diff --git a/doc/board/nxp/ls1046ardb.rst b/doc/board/nxp/ls1046ardb.rst index 4bfeaa93ddb..c73516c0701 100644 --- a/doc/board/nxp/ls1046ardb.rst +++ b/doc/board/nxp/ls1046ardb.rst @@ -95,6 +95,17 @@ Start Address End Address Description Size Booting Options --------------- -- QSPI boot -- SD boot -- eMMC boot + +NB: The reference manual documents the RCW source with the *least-significant +bit first*. + +QSPI boot +^^^^^^^^^ + +This is the default. ``{ SW5[0:8], SW4[0] }`` should be ``0010_0010_0``. + +SD boot and eMMC boot +^^^^^^^^^^^^^^^^^^^^^ + +``{ SW5[0:8], SW4[0] }`` should be ``0010_0000_0``. eMMC is selected only if +there is no SD card in the slot. -- cgit v1.3.1 From e5e982c69bc6c90c62e5c080d1746bf6cdcc56c8 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:12 -0400 Subject: doc: ls1046ardb: Document debug uart This adds some instructions for enabling the debug uart, including the correct address and clock rate. Signed-off-by: Sean Anderson --- doc/board/nxp/ls1046ardb.rst | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'doc') diff --git a/doc/board/nxp/ls1046ardb.rst b/doc/board/nxp/ls1046ardb.rst index c73516c0701..e4499a13fb7 100644 --- a/doc/board/nxp/ls1046ardb.rst +++ b/doc/board/nxp/ls1046ardb.rst @@ -109,3 +109,12 @@ SD boot and eMMC boot ``{ SW5[0:8], SW4[0] }`` should be ``0010_0000_0``. eMMC is selected only if there is no SD card in the slot. + +Debug UART +---------- + +To enable the debug UART, enable the following config options:: + + CONFIG_DEBUG_UART_NS16550=y + CONFIG_DEBUG_UART_BASE=0x21c0500 + CONFIG_DEBUG_UART_CLOCK=300000000 -- cgit v1.3.1 From eeb54e81ca9226aa2a664af7d1e5bc2e44d790e3 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:25 -0400 Subject: doc: smh: Update semihosting documentation This documents how to use semihosting, the new semihosting features, and how to migrate from smhload. Signed-off-by: Sean Anderson --- doc/usage/semihosting.rst | 71 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 67 insertions(+), 4 deletions(-) (limited to 'doc') diff --git a/doc/usage/semihosting.rst b/doc/usage/semihosting.rst index ed16e4d582e..1d793983a7d 100644 --- a/doc/usage/semihosting.rst +++ b/doc/usage/semihosting.rst @@ -10,6 +10,12 @@ console I/O, etc. Please see `Arm's semihosting documentation `_ for more information. +Platform Support +---------------- + +Versatile Express +^^^^^^^^^^^^^^^^^ + For developing on armv8 virtual fastmodel platforms, semihosting is a valuable tool since it allows access to image/configuration files before eMMC or other NV media are available. @@ -31,13 +37,70 @@ vexpress_aemv8.h but differentiate the two models by the presence or absence of ``CONFIG_BASE_FVP``. This change is tested and works on both the Foundation and Base fastmodel simulators. +QEMU +^^^^ + +Another ARM emulator which supports semihosting is `QEMU +`_. To enable semihosting, enable +``CONFIG_SERIAL_PROBE_ALL`` when configuring U-Boot, and use +``-semihosting`` when invoking QEMU. Adding ``-nographic`` can also be +helpful. When using a semihosted serial console, QEMU will block waiting +for input. This will cause the GUI to become unresponsive. To mitigate +this, try adding ``-nographic``. For more information about building and +running QEMU, refer to the :doc:`board documentation +<../board/emulation/qemu-arm>`. + +OpenOCD +^^^^^^^ + +Any ARM platform can use semihosting with an attached debugger. One such +debugger with good support for a variety of boards and JTAG adapters is +`OpenOCD `_. Semihosting is not enabled by default, +so you will need to enable it:: + + $ openocd -f -c init -c halt -c \ + 'arm semihosting enable' -c resume + +Note that enabling semihosting can only be done after attaching to the +board with ``init``, and must be done while the CPU is halted. + Loading files ------------- -The semihosting code adds a "hostfs":: +The semihosting code adds a "semihosting filesystem":: - smhload
[env var] + load hostfs -
That will load an image from the host filesystem into RAM at the specified -address and optionally store the load end address in the specified -environment variable. +address. If you are using U-Boot SPL, you can also use ``BOOT_DEVICE_SMH`` +which will load ``CONFIG_SPL_FS_LOAD_PAYLOAD_NAME``. + +Host console +------------ + +U-Boot can use the host's console instead of a physical serial device by +enabling ``CONFIG_SERIAL_SEMIHOSTING``. If you don't have +``CONFIG_DM_SERIAL`` enabled, make sure you disable any other serial +drivers. + +Migrating from ``smhload`` +-------------------------- + +If you were using the ``smhload`` command, you can migrate commands like:: + + smhload
[] + +to a generic load command like:: + + load hostfs -
+ +The ``load`` command will set the ``filesize`` variable with the size of +the file. The ``fdt chosen`` command has been updated to take a size +instead of an end address. If you were adding the initramfs to your device +tree like:: + + fdt chosen
+ +you can now run:: + + fdt chosen
$filesize -- cgit v1.3.1 From 93c3d329707e0d8dc98e5f86938bbedbe15b5349 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 17:16:05 -0400 Subject: ls1046ardb: Add support for JTAG boot This adds support for booting entirely from JTAG while using a hard-coded RCW. With these steps, it is not necessary to program a "good" RCW using CodeWarrior. The method here can be performed with any JTAG adapter supported by OpenOCD, including the on-board CMSIS-DAP (albeit very slowly). These steps require LS1046A support in OpenOCD, which was added in [1]. [1] https://sourceforge.net/p/openocd/code/ci/5b70c1f679755677c925b4e6dd2c3d8be4715717/ Signed-off-by: Sean Anderson [trini: Add reference to doc/board/nxp/ls1046ardb.rst] --- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 2 + board/freescale/ls1046ardb/ls1046ardb.c | 10 +++++ doc/board/nxp/ls1046ardb.rst | 73 +++++++++++++++++++++++++++++++++ doc/usage/semihosting.rst | 3 +- include/configs/ls1046ardb.h | 2 + 5 files changed, 89 insertions(+), 1 deletion(-) (limited to 'doc') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 564cc27c8b2..1a7dde30a58 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -27,6 +27,8 @@ DECLARE_GLOBAL_DATA_PTR; u32 spl_boot_device(void) { + if (IS_ENABLED(CONFIG_SPL_SEMIHOSTING)) + return BOOT_DEVICE_SMH; #ifdef CONFIG_SPL_MMC return BOOT_DEVICE_MMC1; #endif diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c index d0abfe8869f..9af7cf763be 100644 --- a/board/freescale/ls1046ardb/ls1046ardb.c +++ b/board/freescale/ls1046ardb/ls1046ardb.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include #include #include @@ -27,6 +29,14 @@ DECLARE_GLOBAL_DATA_PTR; +struct serial_device *default_serial_console(void) +{ +#if IS_ENABLED(CONFIG_SEMIHOSTING_SERIAL) + return &serial_smh_device; +#endif + return &eserial1_device; +} + int board_early_init_f(void) { fsl_lsch2_early_init_f(); diff --git a/doc/board/nxp/ls1046ardb.rst b/doc/board/nxp/ls1046ardb.rst index e4499a13fb7..35465d00612 100644 --- a/doc/board/nxp/ls1046ardb.rst +++ b/doc/board/nxp/ls1046ardb.rst @@ -110,6 +110,79 @@ SD boot and eMMC boot ``{ SW5[0:8], SW4[0] }`` should be ``0010_0000_0``. eMMC is selected only if there is no SD card in the slot. +.. _ls1046ardb_jtag: + +JTAG boot +^^^^^^^^^ + +To recover a bricked board, or to perform initial programming, the ls1046 +supports using two hard-coded Reset Configuration Words (RCWs). Unfortunately, +this configuration disables most functionality, including the uarts and ethernet. +However, the SD/MMC and flash controllers are still functional. To get around +the lack of a serial console, we will use ARM semihosting instead. When +enabled, OpenOCD will interpret certain instructions as calls to the host +operating system. This allows U-Boot to use the console, read/write files, or +run arbitrary commands (!). + +When configuring U-Boot, ensure that ``CONFIG_SEMIHOSTING``, +``CONFIG_SPL_SEMIHOSTING``, and ``CONFIG_SEMIHOSTING_SERIAL`` are enabled. +``{ SW5[0:8], SW4[0] }`` should be ``0100_1111_0``. Additionally, ``SW4[7]`` +should be set to ``0``. Connect to the "console" USB connector on the front of +the enclosure. + +Create a new file called ``u-boot.tcl`` (or whatever you choose) with the +following contents:: + + # Load the configuration for the LS1046ARDB + source [find board/nxp_rdb-ls1046a.cfg] + # Initialize the scan chain + init + # Stop the processor + halt + # Enable semihosting + arm semihosting enable + # Load U-Boot SPL + load_image spl/u-boot-spl 0 elf + # Start executing SPL at the beginning of OCRAM + resume 0x10000000 + +Then, launch openocd like:: + + openocd -f u-boot.tcl + +You should see the U-boot SPL banner followed by the banner for U-Boot proper +in the output of openocd. The CMSIS-DAP adapter is slow, so this can take a +long time. If you don't see it, something has gone wrong. After a while, you +should see the prompt. You can load an image using semihosting by running:: + + => load hostfs - $loadaddr + +Note that openocd's terminal is "cooked," so commands will only be sent to +U-Boot when you press enter, and all commands will be echoed twice. +Additionally, openocd will block when waiting for input, ignoring gdb, JTAG +events, and Ctrl-Cs. To make openocd process these events, just hit enter. + +Using an external JTAG adapter +"""""""""""""""""""""""""""""" + +The CMSIS-DAP adapter can be rather slow. To speed up booting, use an external +JTAG adapter. The following examples assume you are using a J-Link, though any +adapter supported by OpenOCD will do. Ensure that ``SW4[7]`` is ``1``. Attach +your jtag adapter to J22. Modify ``u-boot.tcl`` and replace the first two lines +with the following:: + + # Load the J-Link configuration (or whatever your adapter is) + source [find interface/jlink.cfg] + # Use JTAG, since the J-Link also supports SWD + transport select jtag + # The reset pin resets the whole CPU + reset_config srst_only + # Load the LS1046A config + source [find target/ls1046a.cfg] + +You can proceed as normal through the rest of the steps above. I got a speedup +of around 100x by using a J-Link. + Debug UART ---------- diff --git a/doc/usage/semihosting.rst b/doc/usage/semihosting.rst index 1d793983a7d..6a280b455e0 100644 --- a/doc/usage/semihosting.rst +++ b/doc/usage/semihosting.rst @@ -62,7 +62,8 @@ so you will need to enable it:: 'arm semihosting enable' -c resume Note that enabling semihosting can only be done after attaching to the -board with ``init``, and must be done while the CPU is halted. +board with ``init``, and must be done while the CPU is halted. For a more +extended example, refer to the :ref:`LS1046ARDB docs `. Loading files ------------- diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 04c3ad02c8f..df699bca34a 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -140,6 +140,8 @@ #endif #endif +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + #include #endif /* __LS1046ARDB_H__ */ -- cgit v1.3.1