From eca61ae70c80ce42272ab8b999750d925f0ad85c Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Mon, 28 Jan 2019 11:43:26 -0600 Subject: doc: ti-secure: Add ULO info for AM57xx/DRA7xx secure devices from TI Booting from UART and USB on HS devices is now supported for this platform. Update documentation for the same. Signed-off-by: Andrew F. Davis Reviewed-by: Tom Rini --- doc/README.ti-secure | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'doc') diff --git a/doc/README.ti-secure b/doc/README.ti-secure index 4b5380c0f3d..76950253ac4 100644 --- a/doc/README.ti-secure +++ b/doc/README.ti-secure @@ -108,7 +108,8 @@ Booting of U-Boot SPL Invoking the script for DRA7xx/AM57xx Secure Devices ==================================================== - create-boot-image.sh + create-boot-image.sh \ + is a value that specifies the type of the image to generate OR the action the image generation tool will take. Valid @@ -116,7 +117,6 @@ Booting of U-Boot SPL X-LOADER - Generates an image for NOR or QSPI boot modes MLO - Generates an image for SD/MMC/eMMC boot modes ULO - Generates an image for USB/UART peripheral boot modes - Note: ULO is not yet used by the u-boot build process is the full path and filename of the public world boot loader binary file (for this platform, this is always u-boot-spl.bin). @@ -130,9 +130,13 @@ Booting of U-Boot SPL the device ROM bootloader requires for loading from the FAT partition of an SD card (same as on non-secure devices) + u-boot-spl_HS_ULO - boot image for USB/UART peripheral boot modes u-boot-spl_HS_X-LOADER - boot image for all other flash memories including QSPI and NOR flash + is the address at which SOC ROM should load the + + Invoking the script for Keystone2 Secure Devices ============================================= -- cgit v1.3.1 From bbd108a08225b1239b1ec1c10e8131fba6a3a95a Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 30 Jan 2019 13:07:06 +0100 Subject: clk: stm32mp1: correctly handle Clock Spreading Generator To activate the csg option, the driver need to set the bit2 of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator of PLLn enable. Signed-off-by: Patrick Delaunay --- doc/device-tree-bindings/clock/st,stm32mp1.txt | 10 +++++----- drivers/clk/clk_stm32mp1.c | 8 +++++++- 2 files changed, 12 insertions(+), 6 deletions(-) (limited to 'doc') diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt b/doc/device-tree-bindings/clock/st,stm32mp1.txt index 6a9397e1054..ffcf8cd31dc 100644 --- a/doc/device-tree-bindings/clock/st,stm32mp1.txt +++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt @@ -132,15 +132,15 @@ Optional Properties: frac = < 0x810 >; }; st,pll@1 { - cfg = < 1 43 1 0 0 PQR(0,1,1)>; - csg = <10 20 1>; + cfg = < 1 43 1 0 0 PQR(0,1,1) >; + csg = < 10 20 1 >; }; st,pll@2 { - cfg = < 2 85 3 13 3 0>; - csg = <10 20 SSCG_MODE_CENTER_SPREAD>; + cfg = < 2 85 3 13 3 0 >; + csg = < 10 20 SSCG_MODE_CENTER_SPREAD >; }; st,pll@3 { - cfg = < 2 78 4 7 9 3>; + cfg = < 2 78 4 7 9 3 >; }; st,pkcs = < CLK_STGEN_HSE diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 09227cf8db5..aebc6f0a34c 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -165,6 +165,7 @@ /* used for ALL PLLNCR registers */ #define RCC_PLLNCR_PLLON BIT(0) #define RCC_PLLNCR_PLLRDY BIT(1) +#define RCC_PLLNCR_SSCG_CTRL BIT(2) #define RCC_PLLNCR_DIVPEN BIT(4) #define RCC_PLLNCR_DIVQEN BIT(5) #define RCC_PLLNCR_DIVREN BIT(6) @@ -1319,7 +1320,10 @@ static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id) { const struct stm32mp1_clk_pll *pll = priv->data->pll; - writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr); + clrsetbits_le32(priv->base + pll[pll_id].pllxcr, + RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | + RCC_PLLNCR_DIVREN, + RCC_PLLNCR_PLLON); } static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output) @@ -1438,6 +1442,8 @@ static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg) RCC_PLLNCSGR_SSCG_MODE_MASK); writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr); + + setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL); } static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc) -- cgit v1.3.1