From 92d5ecba47feb9961c3b7525e947866c5f0d2de5 Mon Sep 17 00:00:00 2001 From: Albert Aribaud Date: Mon, 11 Oct 2010 13:13:28 +0200 Subject: arm: implement ELF relocations ELF relocation tables generated with linker option -pie can be used to fixup code and data in a single loop at relocation, removing the need for manual fixups anywhere else in the code. Signed-off-by: Albert Aribaud --- doc/README.arm-relocation | 222 +++++++++------------------------------------- 1 file changed, 40 insertions(+), 182 deletions(-) (limited to 'doc') diff --git a/doc/README.arm-relocation b/doc/README.arm-relocation index e3ed60ecdcf..b46347bb5b1 100644 --- a/doc/README.arm-relocation +++ b/doc/README.arm-relocation @@ -1,49 +1,54 @@ To make relocation on arm working, the following changes are done: -Add new compilerflag: +At arch level: add linker flag -pie --fPIC + This causes the linker to generate fixup tables .rel.dyn and .dynsym, + which must be applied to the relocated image before transferring + control to it. - -> compiler generates position independent code + These fixups are described in the ARM ELF documentation as type 23 + (program-base-relative) and 2 (symbol-relative) -changes in board code: +At cpu level: modify linker file and add a relocation and fixup loop -- dram_init: - - bd pointer is now at this point not accessible, so only - detect the real dramsize, and store it in gd->ram_size. - best detected with get_ram_size(); - ToDo: move there also the dram initialization on boards where - it is possible. - - setup the bd_t dram bank info in the new function - dram_init_banksize(). + the linker file must be modified to include the .rel.dyn and .dynsym + tables in the binary image, and to provide symbols for the relocation + code to access these tables -- board.c code is adapted from ppc code + The relocation and fixup loop must be executed after executing + board_init_f at initial location and before executing board_init_r + at final location. -- undef CONFIG_RELOC_FIXUP_WORKS +At board level: - -> cmdtabl, and subcommand table must be handled from "hand" - collected in section "__datarellocal_start". + dram_init(): bd pointer is now at this point not accessible, so only + detect the real dramsize, and store it in gd->ram_size. Bst detected + with get_ram_size(). - - How To fixup the sections: +TODO: move also dram initialization there on boards where it is possible. - __datarel_start, __datarelrolocal_start, __datarellocal_start and - __datarelro_start + Setup of the the bd_t dram bank info is done in the new function + dram_init_banksize() called after bd is accessible. - automatically? Then it should be possible to define again - CONFIG_RELOC_FIXUP_WORKS +At lib level: -- irq stack setup is now not longer on a fix position, instead it is - calculated in board_init_f, and stored in gd->irq_sp + Board.c code is adapted from ppc code -------------------------------------------------------------------------------------- +At config level: -To compile a board without relocation, define CONFIG_SYS_ARM_WITHOUT_RELOC -This possibility will removed!! So please fix your board to compile without -CONFIG_SYS_ARM_WITHOUT_RELOC defined!!! + Define CONFIG_RELOC_FIXUP_WORKS. + Undefine CONFIG_SYS_ARM_WITHOUT_RELOC -------------------------------------------------------------------------------------- +* WARNING ** WARNING ** WARNING ** WARNING ** WARNING ** WARNING ** WARNING * + +Boards which are not fixed to support relocation will be REMOVED! + +Eventually, CONFIG_SYS_ARM_WITHOUT_RELOC and CONFIG_RELOC_FIXUP_WORKS will +disappear and boards which have to migrated to relocation will disappear too. + +----------------------------------------------------------------------------- -For boards which boot from nand_spl, it is possible to save a copy +For boards which boot from nand_spl, it is possible to save one copy if TEXT_BASE == relocation address! This prevents that uboot code is copied again in relocate_code(). @@ -64,9 +69,9 @@ f) u-boot code steps through board_init_f() and calculates If TEXT_BASE == relocation address, the copying of u-boot in f) could be saved. -------------------------------------------------------------------------------------- +----------------------------------------------------------------------------- -ToDo: +TODO - fill in bd_t infos (check) - adapt all boards @@ -80,7 +85,7 @@ ToDo: - new function dram_init_banksize() is actual board specific. Maybe we make a weak default function in arch/arm/lib/board.c ? -------------------------------------------------------------------------------------- +----------------------------------------------------------------------------- Relocation with NAND_SPL (example for the tx25): @@ -98,158 +103,11 @@ Relocation with NAND_SPL (example for the tx25): from the nand_spl code), no need to copy, just go on with bss clear and jump to board_init_r. -------------------------------------------------------------------------------------- - -Relocation: -How to translate flash addresses in GOT to ram addresses. -This is automagically done from code, but this example -shows, how this magic code works ;-) -(example on the qong board) - -Find a variable: - -a) search it in System.map -(for example flash_info) - -a005b4c0 B BootpID -a005b4c4 B BootpTry -a005b4c8 b slave -a005b4cc B flash_info -^^^^^^^^ -a005c908 b saved_sector.4002 -a005c910 b cfi_mtd_info -a005c9c0 b cfi_mtd_names -a005c9d0 B mtd_table - ---------------------------------------- - -b) create hexdump from u-boot code: - -hexdump -C u-boot > gnlmpfhex - ---------------------------------------- - -c) search the variables address in the hexdump - - -* -0005fc80 00 00 00 00 00 00 00 00 2c 06 01 a0 18 cd 05 a0 |........,.......| -0005fc90 9c d4 05 a0 bc b4 05 a0 1c 7f 05 a0 f0 05 01 a0 |................| -0005fca0 08 5a 04 a0 1c ab 05 a0 ec a4 05 a0 98 c3 01 a0 |.Z..............| -0005fcb0 a0 d6 05 a0 04 71 05 a0 c0 f9 00 a0 3c cd 05 a0 |.....q......<...| -0005fcc0 cc b4 05 a0 f0 fa 00 a0 f0 d6 05 a0 10 86 05 a0 |................| - ^^^^^^^^^^^ -0005fcd0 a4 16 06 a0 dc 64 05 a0 18 86 05 a0 52 48 05 a0 |.....d......RH..| -0005fce0 c0 86 05 a0 24 6e 02 a0 b4 6c 05 a0 b0 94 01 a0 |....$n...l......| -0005fcf0 1c 86 05 a0 50 85 05 a0 d4 0c 06 a0 bc 0b 06 a0 |....P...........| - - --> 0005fcc0 - ----------------------------------------- - -d) know we calculate this address in RAM - - - 8ff08000 (new address of code in RAM *1) - -+ 0005fcc0 - -- 00008000 (offset of text *2) - ----------- - - 8ff5fcc0 -> Addr GOT in RAM - -*1: -activate debug and look for the line: -Now running in RAM - U-Boot at: 8ff08000 - ^^^^^^^^ - new address of u-boot code in RAM - -*2: -Section Headers: - [Nr] Name Type Addr Off Size ES Flg Lk Inf Al - [ 0] NULL 00000000 000000 000000 00 0 0 0 - [ 1] .text PROGBITS a0000000 008000 04599c 00 AX 0 0 32 - ^^^^^^ - Offset of text +----------------------------------------------------------------------------- ----------------------------------------- +How ELF relocations 23 and 2 work. -e) now we look in 8ff5fcc0 (RAM) - - -QongEVB>md 0x8ff5fcc0 -8ff5fcc0 : a005b4cc a000faf0 a005d6f0 a0058610 ................ - ^^^^^^^^ - Bingo, here we have the old flash address (when relocation - is working, here is the fixed ram address. see @ f, how - it gets calculated) - - ----------------------------------------- - -f) now translate it in the new RAM address - - a005b4cc - -- a0000000 TextBase - -+ 8ff08000 new address of u-boot in ram ----------- - 8ff634cc - -QongEVB>mm 0x8ff5fcc0 0x8ff634cc 1 -QongEVB>md 0x8ff5fcc0 -8ff5fcc0 : 8ff634cc a000faf0 a005d6f0 a0058610 .4.............. -8ff5fcd0 : a00616a4 a00564dc a0058618 a0054852 .....d......RH.. - -As this must be done for all address in the GOT, the u-boot -code did this automagically ... :-) - ----------------------------------------------- - -g) check if the new address is really in the bss section: - -bss start: -8ff6054c (8ff08000 + 0005854C monitorlen) - -bss end: -8ff698ac (8ff08000 + 618AC) - -8ff634cc is in bss :-) - ----------------------------------------------- - -h) u-boot prints: - -important addresses: - -U-Boot code: A0000000 -> A005854C BSS: -> A00618AC TextBase 0xa0000000 -Now running in RAM - U-Boot at: 8ff08000 relocBase 0x8ff08000 - - ---------- - -U-Boot 2010.06-rc2-00002-gf8fbb25-dirty (Jun 18 2010 - 17:07:19) - -U-Boot code: A0000000 -> A005854C BSS: -> A00618AC -CPU: Freescale i.MX31 at 398 MHz -Board: DAVE/DENX Qong -mon: FFFFFFFF gd->monLen: 000618AC -Top of RAM usable for U-Boot at: 90000000 -LCD panel info: 640 x 480, 16 bit/pix -Reserving 600k for LCD Framebuffer at: 8ff6a000 -Reserving 390k for U-Boot at: 8ff08000 -Reserving 1280k for malloc() at: 8fdc8000 -Reserving 28 Bytes for Board Info at: 8fdc7fe4 -Reserving 48 Bytes for Global Data at: 8fdc7fb4 -New Stack Pointer is: 8fdc7fb0 -RAM Configuration: -Bank #0: 80000000 256 MiB -mon: 0005854C gd->monLen: 000618AC -Now running in RAM - U-Boot at: 8ff08000 +TBC ------------------------------------------------------------------------------------- -- cgit v1.3.1 From c8d76eaf606096eddbe62b8a86545f5116f5189c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 18 Oct 2010 23:43:37 +0200 Subject: Rename TEXT_BASE: fix merge conflicts Commit 14d0a02a "Rename TEXT_BASE into CONFIG_SYS_TEXT_BASE" missed a few places, especially for boards that were added inbetween. Fix the remaining issues. Signed-off-by: Wolfgang Denk --- board/a4m072/config.mk | 39 --------------------------------------- board/eNET/u-boot.lds | 8 ++++---- doc/README.arm-relocation | 10 +++++----- include/configs/a4m072.h | 6 ++++-- nand_spl/nand_boot.c | 3 ++- nand_spl/nand_boot_fsl_nfc.c | 3 ++- 6 files changed, 17 insertions(+), 52 deletions(-) delete mode 100644 board/a4m072/config.mk (limited to 'doc') diff --git a/board/a4m072/config.mk b/board/a4m072/config.mk deleted file mode 100644 index c6ba51d960f..00000000000 --- a/board/a4m072/config.mk +++ /dev/null @@ -1,39 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# a4m072 board: -# -# Valid values for TEXT_BASE is: -# -# 0xFE000000 boot low -# - -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -ifndef TEXT_BASE -## Standard: boot low -TEXT_BASE = 0xFE000000 -endif - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds index b414079bc14..3eeb2a201b4 100644 --- a/board/eNET/u-boot.lds +++ b/board/eNET/u-boot.lds @@ -27,7 +27,7 @@ ENTRY(_start) SECTIONS { - . = TEXT_BASE; /* Location of bootcode in flash */ + . = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */ __text_start = .; .text : { *(.text*); } @@ -94,11 +94,11 @@ SECTIONS * The fff0 offset of resetvec is important, however. */ . = 0xfffffe00; - .start32 : AT (TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); } + .start32 : AT (CONFIG_SYS_TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); } . = 0xf800; - .start16 : AT (TEXT_BASE + 0x3f800) { KEEP(*(.start16)); } + .start16 : AT (CONFIG_SYS_TEXT_BASE + 0x3f800) { KEEP(*(.start16)); } . = 0xfff0; - .resetvec : AT (TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); } + .resetvec : AT (CONFIG_SYS_TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); } } diff --git a/doc/README.arm-relocation b/doc/README.arm-relocation index 4ab3c7c0bd6..e9fe9993d95 100644 --- a/doc/README.arm-relocation +++ b/doc/README.arm-relocation @@ -92,11 +92,11 @@ Relocation with NAND_SPL (example for the tx25): the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution @CONFIG_SYS_NAND_U_BOOT_START -- This u-boot does no ram int, nor cpu register setup. Just looks - where it have to relocate and relocate itself to this address. - If relocate address = CONFIG_SYS_TEXT_BASE(not the same, as the TEXT_BASE - from the nand_spl code), no need to copy, just go on with bss clear - and jump to board_init_r. +- This u-boot does no RAM init, nor CPU register setup. Just look + where it has to copy and relocate itself to this address. If + relocate address = CONFIG_SYS_TEXT_BASE (not the same, as the + CONFIG_SYS_TEXT_BASE from the nand_spl code), then there is no need + to copy, just go on with bss clear and jump to board_init_r. ------------------------------------------------------------------------------------- diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h index 6dcebe6f44c..24a04ebefb5 100644 --- a/include/configs/a4m072.h +++ b/include/configs/a4m072.h @@ -37,6 +37,8 @@ #define CONFIG_A4M072 1 /* ... on A4M072 board */ #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ +#define CONFIG_SYS_TEXT_BASE 0xFE000000 + #define CONFIG_MISC_INIT_R #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ @@ -125,7 +127,7 @@ #define CONFIG_CMD_PCI #endif -#if (TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */ +#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */ #define CONFIG_SYS_LOWBOOT 1 #define CONFIG_SYS_LOWBOOT32 1 #endif @@ -238,7 +240,7 @@ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) # define CONFIG_SYS_RAMBOOT 1 #endif diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c index 4d6db14abe5..ccd0af25548 100644 --- a/nand_spl/nand_boot.c +++ b/nand_spl/nand_boot.c @@ -224,7 +224,8 @@ static int nand_load(struct mtd_info *mtd, unsigned int offs, #if defined(CONFIG_ARM) && !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) void board_init_f (ulong bootflag) { - relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL, TEXT_BASE); + relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL, + CONFIG_SYS_TEXT_BASE); } #endif diff --git a/nand_spl/nand_boot_fsl_nfc.c b/nand_spl/nand_boot_fsl_nfc.c index 959f162324d..21ed3fcff4b 100644 --- a/nand_spl/nand_boot_fsl_nfc.c +++ b/nand_spl/nand_boot_fsl_nfc.c @@ -266,7 +266,8 @@ static int nand_load(unsigned int from, unsigned int size, unsigned char *buf) #if defined(CONFIG_ARM) && !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) void board_init_f (ulong bootflag) { - relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL, TEXT_BASE); + relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL, + CONFIG_SYS_TEXT_BASE); } #endif -- cgit v1.3.1 From 923527aacefc04d78003829c1e38f3985a334024 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 19 Oct 2010 21:46:25 +0200 Subject: doc/README.scrapyard: add documentation for abandoned boards Add a document to maintain a list of boards removed from the current source tree, so archeologists can check more easily if here is something they might want to dig for... Signed-off-by: Wolfgang Denk --- doc/README.scrapyard | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 doc/README.scrapyard (limited to 'doc') diff --git a/doc/README.scrapyard b/doc/README.scrapyard new file mode 100644 index 00000000000..a707c6fa937 --- /dev/null +++ b/doc/README.scrapyard @@ -0,0 +1,29 @@ +Over time, support for more and more boards gets added to U-Boot - +while other board support code dies a silent death caused by +negligence in combination with ordinary bitrot. Sometimes this goes +by unnoticed, but often build errors will result. If nobody cares any +more to resolve such problems, then the code is really dead and will +be removed from the U-Boot source tree. The remainders rest in piece +in the imperishable depths of the git history. This document tries to +maintain a list of such former fellows, so archeologists can check +easily if here is something they might want to dig for... + + +Board Arch CPU removed Commit last known maintainer/contact +============================================================================= +NC650 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk +CP850 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk +logodl ARM PXA2xx 059e778 2010-10-18 August Hoeraendl +CCM powerpc MPC860 dff07e1 2010-10-06 Wolfgang Grandegger +PCU_E powerpc MPC860T 544d97e 2010-10-06 Wolfgang Denk +spieval powerpc MPC5200 69434e4 2010-09-19 +smmaco4 powerpc MPC5200 9ddc3af 2010-09-19 +HMI10 powerpc MPC823 77efe35 2010-09-19 Wolfgang Denk +GTH powerpc MPC860 0fe247b 2010-07-17 Thomas Lange +AmigaOneG3SE 953b7e6 2010-06-23 +suzaku microblaze 4f18060 2009-10-03 Yasushi Shoji +XUPV2P microblaze 8fab49e 2008-12-10 Michal Simek +MVS1 powerpc MPC823 306620b 2008-08-26 Andre Schwarz +adsvix ARM PXA27x 7610db1 2008-07-30 Adrian Filipi +R5200 ColdFire 48ead7a 2008-03-31 Zachary P. Landau +CPCI440 powerpc 440GP b568fd2 2007-12-27 Matthias Fuchs -- cgit v1.3.1 From ae8082c7e0be9e31a70959a60d3f2ea70d4ecc70 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 19 Oct 2010 14:58:02 +0200 Subject: Add UBI README This patch adds a small README to describe the usage of the U-Boot UBI commands. Signed-off-by: Stefan Roese --- doc/README.ubi | 144 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 144 insertions(+) create mode 100644 doc/README.ubi (limited to 'doc') diff --git a/doc/README.ubi b/doc/README.ubi new file mode 100644 index 00000000000..da2dfac50ce --- /dev/null +++ b/doc/README.ubi @@ -0,0 +1,144 @@ +------------------- +UBI usage in U-Boot +------------------- + +Here the list of the currently implemented UBI commands: + +=> help ubi +ubi - ubi commands + +Usage: +ubi part [part] [offset] + - Show or set current partition (with optional VID header offset) +ubi info [l[ayout]] - Display volume and ubi layout information +ubi create[vol] volume [size] [type] - create volume name with size +ubi write[vol] address volume size - Write volume from address with size +ubi read[vol] address volume [size] - Read volume to address with size +ubi remove[vol] volume - Remove volume +[Legends] + volume: character name + size: specified in bytes + type: s[tatic] or d[ynamic] (default=dynamic) + + +The first command that is needed to be issues is "ubi part" to connect +one mtd partition to the UBI subsystem. This command will either create +a new UBI device on the requested MTD partition. Or it will attach a +previously created UBI device. The other UBI commands will only work +when such a UBI device is attached (via "ubi part"). Here an example: + +=> mtdparts + +device nor0 <1fc000000.nor_flash>, # parts = 6 + #: name size offset mask_flags + 0: kernel 0x00200000 0x00000000 0 + 1: dtb 0x00040000 0x00200000 0 + 2: root 0x00200000 0x00240000 0 + 3: user 0x01ac0000 0x00440000 0 + 4: env 0x00080000 0x01f00000 0 + 5: u-boot 0x00080000 0x01f80000 0 + +active partition: nor0,0 - (kernel) 0x00200000 @ 0x00000000 + +defaults: +mtdids : nor0=1fc000000.nor_flash +mtdparts: mtdparts=1fc000000.nor_flash:2m(kernel),256k(dtb),2m(root),27392k(user),512k(env),512k(u-boot) + +=> ubi part root +Creating 1 MTD partitions on "nor0": +0x000000240000-0x000000440000 : "mtd=2" +UBI: attaching mtd1 to ubi0 +UBI: physical eraseblock size: 262144 bytes (256 KiB) +UBI: logical eraseblock size: 262016 bytes +UBI: smallest flash I/O unit: 1 +UBI: VID header offset: 64 (aligned 64) +UBI: data offset: 128 +UBI: attached mtd1 to ubi0 +UBI: MTD device name: "mtd=2" +UBI: MTD device size: 2 MiB +UBI: number of good PEBs: 8 +UBI: number of bad PEBs: 0 +UBI: max. allowed volumes: 128 +UBI: wear-leveling threshold: 4096 +UBI: number of internal volumes: 1 +UBI: number of user volumes: 1 +UBI: available PEBs: 0 +UBI: total number of reserved PEBs: 8 +UBI: number of PEBs reserved for bad PEB handling: 0 +UBI: max/mean erase counter: 2/1 + + +Now that the UBI device is attached, this device can be modified +using the following commands: + +ubi info Display volume and ubi layout information +ubi createvol Create UBI volume on UBI device +ubi removevol Remove UBI volume from UBI device +ubi read Read data from UBI volume to memory +ubi write Write data from memory to UBI volume + + +Here a few examples on the usage: + +=> ubi create testvol +Creating dynamic volume testvol of size 1048064 + +=> ubi info l +UBI: volume information dump: +UBI: vol_id 0 +UBI: reserved_pebs 4 +UBI: alignment 1 +UBI: data_pad 0 +UBI: vol_type 3 +UBI: name_len 7 +UBI: usable_leb_size 262016 +UBI: used_ebs 4 +UBI: used_bytes 1048064 +UBI: last_eb_bytes 262016 +UBI: corrupted 0 +UBI: upd_marker 0 +UBI: name testvol + +UBI: volume information dump: +UBI: vol_id 2147479551 +UBI: reserved_pebs 2 +UBI: alignment 1 +UBI: data_pad 0 +UBI: vol_type 3 +UBI: name_len 13 +UBI: usable_leb_size 262016 +UBI: used_ebs 2 +UBI: used_bytes 524032 +UBI: last_eb_bytes 2 +UBI: corrupted 0 +UBI: upd_marker 0 +UBI: name layout volume + +=> ubi info +UBI: MTD device name: "mtd=2" +UBI: MTD device size: 2 MiB +UBI: physical eraseblock size: 262144 bytes (256 KiB) +UBI: logical eraseblock size: 262016 bytes +UBI: number of good PEBs: 8 +UBI: number of bad PEBs: 0 +UBI: smallest flash I/O unit: 1 +UBI: VID header offset: 64 (aligned 64) +UBI: data offset: 128 +UBI: max. allowed volumes: 128 +UBI: wear-leveling threshold: 4096 +UBI: number of internal volumes: 1 +UBI: number of user volumes: 1 +UBI: available PEBs: 0 +UBI: total number of reserved PEBs: 8 +UBI: number of PEBs reserved for bad PEB handling: 0 +UBI: max/mean erase counter: 4/1 + +=> ubi write 800000 testvol 80000 +Volume "testvol" found at volume id 0 + +=> ubi read 900000 testvol 80000 +Volume testvol found at volume id 0 +read 524288 bytes from volume 0 to 900000(buf address) + +=> cmp.b 800000 900000 80000 +Total of 524288 bytes were the same -- cgit v1.3.1 From ebbe11dd365b16573e25b1b361287f9539daa33c Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 28 Sep 2010 15:20:33 -0700 Subject: Add memory test feature for mpc85xx POST. The memory test is performed after DDR initialization when U-boot stills runs in flash and cache. On recent mpc85xx platforms, the total memory can be more than 2GB. To cover whole memory, it needs be mapped 2GB at a time using a sliding TLB window. After the testing, DDR is remapped with up to 2GB memory from the lowest address as normal. If memory test fails, DDR DIMM SPD and DDR controller registers are dumped for further debugging. Signed-off-by: York Sun Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cpu.c | 219 +++++++++++++++++++++++++++++++++++++++++ doc/README.fsl-ddr | 14 +++ 2 files changed, 233 insertions(+) (limited to 'doc') diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 3f80700711d..fc5d951e9aa 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -34,6 +34,9 @@ #include #include #include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -282,3 +285,219 @@ void mpc85xx_reginfo(void) print_laws(); print_lbc_regs(); } + +#if CONFIG_POST & CONFIG_SYS_POST_MEMORY + +/* Board-specific functions defined in each board's ddr.c */ +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num); +void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, + phys_addr_t *rpn); +unsigned int + setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); + +static void dump_spd_ddr_reg(void) +{ + int i, j, k, m; + u8 *p_8; + u32 *p_32; + ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; + generic_spd_eeprom_t + spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; + + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + fsl_ddr_get_spd(spd[i], i); + + puts("SPD data of all dimms (zero vaule is omitted)...\n"); + puts("Byte (hex) "); + k = 1; + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) + printf("Dimm%d ", k++); + } + puts("\n"); + for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { + m = 0; + printf("%3d (0x%02x) ", k, k); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + p_8 = (u8 *) &spd[i][j]; + if (p_8[k]) { + printf("0x%02x ", p_8[k]); + m++; + } else + puts(" "); + } + } + if (m) + puts("\n"); + else + puts("\r"); + } + + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + switch (i) { + case 0: + ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; + break; +#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR + case 1: + ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; + break; +#endif + default: + printf("%s unexpected controller number = %u\n", + __func__, i); + return; + } + } + printf("DDR registers dump for all controllers " + "(zero vaule is omitted)...\n"); + puts("Offset (hex) "); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); + puts("\n"); + for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { + m = 0; + printf("%6d (0x%04x)", k * 4, k * 4); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + p_32 = (u32 *) ddr[i]; + if (p_32[k]) { + printf(" 0x%08x", p_32[k]); + m++; + } else + puts(" "); + } + if (m) + puts("\n"); + else + puts("\r"); + } + puts("\n"); +} + +/* invalid the TLBs for DDR and setup new ones to cover p_addr */ +static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) +{ + u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; + unsigned long epn; + u32 tsize, valid, ptr; + phys_addr_t rpn = 0; + int ddr_esel; + + ptr = vstart; + + while (ptr < (vstart + size)) { + ddr_esel = find_tlb_idx((void *)ptr, 1); + if (ddr_esel != -1) { + read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); + disable_tlb(ddr_esel); + } + ptr += TSIZE_TO_BYTES(tsize); + } + + /* Setup new tlb to cover the physical address */ + setup_ddr_tlbs_phys(p_addr, size>>20); + + ptr = vstart; + ddr_esel = find_tlb_idx((void *)ptr, 1); + if (ddr_esel != -1) { + read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); + } else { + printf("TLB error in function %s\n", __func__); + return -1; + } + + return 0; +} + +/* + * slide the testing window up to test another area + * for 32_bit system, the maximum testable memory is limited to + * CONFIG_MAX_MEM_MAPPED + */ +int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) +{ + phys_addr_t test_cap, p_addr; + phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); + +#if !defined(CONFIG_PHYS_64BIT) || \ + !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ + (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) + test_cap = p_size; +#else + test_cap = gd->ram_size; +#endif + p_addr = (*vstart) + (*size) + (*phys_offset); + if (p_addr < test_cap - 1) { + p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); + if (reset_tlb(p_addr, p_size, phys_offset) == -1) + return -1; + *vstart = CONFIG_SYS_DDR_SDRAM_BASE; + *size = (u32) p_size; + printf("Testing 0x%08llx - 0x%08llx\n", + (u64)(*vstart) + (*phys_offset), + (u64)(*vstart) + (*phys_offset) + (*size) - 1); + } else + return 1; + + return 0; +} + +/* initialization for testing area */ +int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) +{ + phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); + + *vstart = CONFIG_SYS_DDR_SDRAM_BASE; + *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ + *phys_offset = 0; + +#if !defined(CONFIG_PHYS_64BIT) || \ + !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ + (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) + if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { + puts("Cannot test more than "); + print_size(CONFIG_MAX_MEM_MAPPED, + " without proper 36BIT support.\n"); + } +#endif + printf("Testing 0x%08llx - 0x%08llx\n", + (u64)(*vstart) + (*phys_offset), + (u64)(*vstart) + (*phys_offset) + (*size) - 1); + + return 0; +} + +/* invalid TLBs for DDR and remap as normal after testing */ +int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) +{ + unsigned long epn; + u32 tsize, valid, ptr; + phys_addr_t rpn = 0; + int ddr_esel; + + /* disable the TLBs for this testing */ + ptr = *vstart; + + while (ptr < (*vstart) + (*size)) { + ddr_esel = find_tlb_idx((void *)ptr, 1); + if (ddr_esel != -1) { + read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); + disable_tlb(ddr_esel); + } + ptr += TSIZE_TO_BYTES(tsize); + } + + puts("Remap DDR "); + setup_ddr_tlbs(gd->ram_size>>20); + puts("\n"); + + return 0; +} + +void arch_memory_failure_handle(void) +{ + dump_spd_ddr_reg(); +} +#endif diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index e108a0d50c9..1657ef61702 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -78,6 +78,20 @@ If the DDR controller supports address hashing, it can be enabled by hwconfig. Syntax is: hwconfig=fsl_ddr:addr_hash=true + +Memory testing options for mpc85xx +================================== +1. Memory test can be done once U-boot prompt comes up using mtest, or +2. Memory test can be done with Power-On-Self-Test function, activated at + compile time. + + In order to enable the POST memory test, CONFIG_POST needs to be + defined in board configuraiton header file. By default, POST memory test + performs a fast test. A slow test can be enabled by changing the flag at + compiling time. To test memory bigger than 2GB, 36BIT support is needed. + Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB + window to physical address so that all physical memory can be tested. + Combination of hwconfig ======================= Hwconfig can be combined with multiple parameters, for example, on a supported -- cgit v1.3.1