From 414e10b96c775a1d145eb4dc9524e02328531a1b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 15 Mar 2021 18:00:02 +1300 Subject: x86: coral: Add information about building / running Add detailed information on how to build the coral image, since it needs binary blobs. Provide a way to avoid the memory-training delay. Also show the console output from a sample run. Signed-off-by: Simon Glass --- doc/board/google/chromebook_coral.rst | 234 +++++++++++++++++++++++++++++++--- 1 file changed, 217 insertions(+), 17 deletions(-) (limited to 'doc') diff --git a/doc/board/google/chromebook_coral.rst b/doc/board/google/chromebook_coral.rst index c39f1e310c7..4b585678dcf 100644 --- a/doc/board/google/chromebook_coral.rst +++ b/doc/board/google/chromebook_coral.rst @@ -16,6 +16,169 @@ Note that booting U-Boot on APL is already supported by coreboot and Slim Bootloader. This documentation refers to a 'bare metal' port. +Building +-------- + +First, you need the following binary blobs: + + * descriptor.bin - Intel flash descriptor + * fitimage.bin - Base flash image structure + * fsp_m.bin - FSP-M, for setting up SDRAM + * fsp_s.bin - FSP-S, for setting up Silicon + * vbt.bin - for setting up display + +These binaries do not seem to be available publicly. If you have a ROM image, +such as santa.bin then you can do this:: + + cbfstool santa.bin extract -n fspm.bin -f fsp-m.bin + cbfstool santa.bin extract -n fsps.bin -f fsp-s.bin + cbfstool santa.bin extract -n vbt-santa.bin -f vbt.bin + mkdir tmp + cd tmp + dump_fmap -x ../santa.bin + mv SI_DESC ../descriptor.bin + mv IFWI ../fitimage.bin + +Put all of these files in `board/google/chromebook_coral` so they can be found +by the build. + +To build:: + + make O=/tmp/b/chromebook_coral chromebook_coral_defconfig + make O=/tmp/b/chromebook_coral -s -j30 all + +That should produce `/tmp/b/chrombook_coral/u-boot.rom` which you can use with +a Dediprog em100:: + + em100 -s -c w25q128fw -d /tmp/b/chromebook_coral/u-boot.rom -r + +or you can use flashrom to write it to the board. If you do that, make sure you +have a way to restore the old ROM without booting the board. Otherwise you may +brick it. Having said that, you may find these instructions useful if you want +to unbrick your device: + + https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging.md + +You can buy Suzy-Q from Sparkfun: + + https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/main/docs/ccd.md#suzyq-suzyqable + +Note that it will hang at the SPL prompt for 21 seconds. When booting into +Chrome OS it will always select developer mode, so will wipe anything you have +on the device if you let it proceed. You have two seconds in U-Boot to stop the +auto-boot prompt and several seconds at the 'developer wipe' screen to stop it +wiping the disk. + +Here is the console output:: + + U-Boot TPL 2021.04-rc1-00128-g344eefcdfec-dirty (Feb 11 2021 - 20:13:08 -0700) + Trying to boot from Mapped SPI + + U-Boot SPL 2021.04-rc1-00128-g344eefcdfec-dirty (Feb 11 2021 - 20:13:08 -0700) + Trying to boot from Mapped SPI + + + U-Boot 2021.04-rc1-00128-g344eefcdfec-dirty (Feb 11 2021 - 20:13:08 -0700) + + CPU: Intel(R) Celeron(R) CPU N3450 @ 1.10GHz + DRAM: 3.9 GiB + MMC: sdmmc@1b,0: 1, emmc@1c,0: 2 + Video: 1024x768x32 @ b0000000 + Model: Google Coral + Net: No ethernet found. + SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB + Hit any key to stop autoboot: 0 + cmdline=console= loglevel=7 init=/sbin/init cros_secure oops=panic panic=-1 root=PARTUUID=${uuid}/PARTNROFF=1 rootwait rw dm_verity.error_behavior=3 dm_verity.max_bios=-1 dm_verity.dev_wait=0 dm="1 vroot none rw 1,0 3788800 verity payload=ROOT_DEV hashtree=HASH_DEV hashstart=3788800 alg=sha1 root_hexdigest=55052b629d3ac889f25a9583ea12cdcd3ea15ff8 salt=a2d4d9e574069f4fed5e3961b99054b7a4905414b60a25d89974a7334021165c" noinitrd vt.global_cursor_default=0 kern_guid=${uuid} add_efi_memmap boot=local noresume noswap i915.modeset=1 Kernel command line: "console= loglevel=7 init=/sbin/init cros_secure oops=panic panic=-1 root=PARTUUID=35c775e7-3735-d745-93e5-d9e0238f7ed0/PARTNROFF=1 rootwait rw dm_verity.error_behavior=3 dm_verity.max_bios=-1 dm_verity.dev_wait=0 dm="1 vroot none rw 1,0 3788800 verity payload=ROOT_DEV hashtree=HASH_DEV hashstart=3788800 alg=sha1 root_hexdigest=55052b629d3ac889f25a9583ea12cdcd3ea15ff8 salt=a2d4d9e574069f4fed5e3961b99054b7a4905414b60a25d89974a7334021165c" noinitrd vt.global_cursor_default=0 kern_guid=35c775e7-3735-d745-93e5-d9e0238f7ed0 add_efi_memmap boot=local noresume noswap i915.modeset=1 tpm_tis.force=1 tpm_tis.interrupts=0 nmi_watchdog=panic,lapic disablevmx=off " + Setup located at 00090000: + + ACPI RSDP addr : 7991f000 + E820: 14 entries + Addr Size Type + d0000000 1000000 + 0 a0000 RAM + a0000 60000 Reserved + 7b000000 800000 Reserved + 7b800000 4800000 Reserved + 7ac00000 400000 Reserved + 100000 ff00000 RAM + 10000000 2151000 Reserved + 12151000 68aaf000 RAM + 100000000 80000000 RAM + e0000000 10000000 Reserved + 7991bfd0 12e4030 Reserved + d0000000 10000000 Reserved + fed10000 8000 Reserved + Setup sectors : 1e + Root flags : 1 + Sys size : 63420 + RAM size : 0 + Video mode : ffff + Root dev : 0 + Boot flag : 0 + Jump : 66eb + Header : 53726448 + Kernel V2 + Version : 20d + Real mode switch : 0 + Start sys : 1000 + Kernel version : 38cc + @00003acc: + Type of loader : 80 + U-Boot, version 0 + Load flags : 81 + : loaded-high can-use-heap + Setup move size : 8000 + Code32 start : 100000 + Ramdisk image : 0 + Ramdisk size : 0 + Bootsect kludge : 0 + Heap end ptr : 8e00 + Ext loader ver : 0 + Ext loader type : 0 + Command line ptr : 99000 + console= loglevel=7 init=/sbin/init cros_secure oops=panic panic=-1 root=PARTUUID=35c775e7-3735-d745-93e5-d9e0238f7ed0/PARTNROFF=1 rootwait rw dm_verity.error_behavior=3 dm_verity.max_bios=-1 dm_verity.dev_wait=0 dm="1 vroot none rw 1,0 3788800 verity payload=ROOT_DEV hashtree=HASH_DEV hashstart=3788800 alg=sha1 root_hexdigest=55052b629d3ac889f25a9583ea12cdcd3ea15ff8 salt=a2d4d9e574069f4fed5e3961b99054b7a4905414b60a25d89974a7334021165c" noinitrd vt.global_cursor_default=0 kern_guid=35c775e7-3735-d745-93e5-d9e0238f7ed0 add_efi_memmap boot=local noresume noswap i915.modeset=1 tpm_tis.force=1 tpm_tis.interrupts=0 nmi_watchdog=panic,lapic disablevmx=off + Initrd addr max : 7fffffff + Kernel alignment : 200000 + Relocatable kernel : 1 + Min alignment : 15 + : 200000 + Xload flags : 3 + : 64-bit-entry can-load-above-4gb + Cmdline size : 7ff + Hardware subarch : 0 + HW subarch data : 0 + Payload offset : 26e + Payload length : 612045 + Setup data : 0 + Pref address : 1000000 + Init size : 1383000 + Handover offset : 0 + + Starting kernel ... + + Timer summary in microseconds (17 records): + Mark Elapsed Stage + 0 0 reset + 155,279 155,279 TPL + 237,088 81,809 end phase + 237,533 445 SPL + 816,456 578,923 end phase + 817,357 901 board_init_f + 1,061,751 244,394 board_init_r + 1,402,435 340,684 id=64 + 1,430,071 27,636 main_loop + 5,532,057 4,101,986 start_kernel + + Accumulated time: + 685 dm_r + 2,817 fast_spi + 33,095 dm_spl + 52,468 dm_f + 208,242 fsp-m + 242,221 fsp-s + 332,710 mmap_spi + + Boot flow - TPL --------------- @@ -181,7 +344,7 @@ Partial memory map ff000000 Bottom of ROM fefc0000 Top of CAR region fef96000 Stack for FSP-M - fef40000 59000 FSP-M + fef40000 59000 FSP-M (also VPL loads here) fef11000 SPL loaded here fef10000 CONFIG_BLOBLIST_ADDR fef10000 Stack top in TPL, SPL and U-Boot before relocation @@ -195,35 +358,72 @@ Partial memory map 1110000 CONFIG_SYS_TEXT_BASE +Speeding up SPL for development +------------------------------- + +The 21-second wait for memory training is annoying during development, since +every new image incurs this cost when booting. There is no cache to fall back on +since that area of the image is empty on start-up. + +You can add suitable cache contents to the image to fix this, for development +purposes only, like this:: + + # Read the image back after booting through SPL + em100 -s -c w25q128fw -u image.bin + + # Extract the two cache regions + binman extract -i image.bin extra *cache + + # Move them into the source directory + mv *cache board/google/chromebook_coral + +Then add something like this to the devicetree:: + + #if IS_ENABLED(CONFIG_HAVE_MRC) || IS_ENABLED(CONFIG_FSP_VERSION2) + /* Provide initial contents of the MRC data for faster development */ + rw-mrc-cache { + type = "blob"; + /* Mirror the offset in spi-flash@0 */ + offset = <0xff8e0000>; + size = <0x10000>; + filename = "board/google/chromebook_coral/rw-mrc-cache"; + }; + rw-var-mrc-cache { + type = "blob"; + size = <0x1000>; + filename = "board/google/chromebook_coral/rw-var-mrc-cache"; + }; + #endif + +This tells binman to put the cache contents in the same place as the +`rw-mrc-cache` and `rw-var-mrc-cache` regions defined by the SPI-flash driver. + + Supported peripherals --------------------- -- UART -- SPI flash -- Video -- MMC (dev 0) and micro-SD (dev 1) -- Chrome OS EC -- Keyboard -- USB +The following have U-Boot drivers: + + - UART + - SPI flash + - Video + - MMC (dev 0) and micro-SD (dev 1) + - Chrome OS EC + - Cr50 (security chip) + - Keyboard + - USB To do ----- - Finish peripherals - - left-side USB - - USB-C - - Cr50 (security chip: a basic driver is running but not included here) - Sound (Intel I2S support exists, but need da7219 driver) - - Various minor features supported by LPC, etc. -- Booting Chrome OS, e.g. with verified boot -- Integrate with Chrome OS vboot -- Improvements to booting from coreboot (i.e. as a coreboot target) - Use FSP-T binary instead of our own CAR implementation - Use the official FSP package instead of the coreboot one -- Enable all CPU cores - Suspend / resume -- ACPI +- Fix MMC which seems to try to read even though the card is empty +- Fix USB3 crash "WARN halted endpoint, queueing URB anyway." Credits -- cgit v1.3.1 From 71cebf0b5947cc0e393bec0841744d9eda0a038d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 15 Mar 2021 18:00:24 +1300 Subject: x86: Add a command to display coreboot sysinfo This information is interesting to look at and can be important for debugging and inspection. Add a command to display it in a helpful format. Signed-off-by: Simon Glass --- cmd/Kconfig | 9 + cmd/x86/Makefile | 1 + cmd/x86/cbsysinfo.c | 394 ++++++++++++++++++++++++++++++++++++++++++++ doc/usage/index.rst | 1 + doc/usage/x86/cbsysinfo.rst | 25 +++ 5 files changed, 430 insertions(+) create mode 100644 cmd/x86/cbsysinfo.c create mode 100644 doc/usage/x86/cbsysinfo.rst (limited to 'doc') diff --git a/cmd/Kconfig b/cmd/Kconfig index e4bb1d4c4a7..8ab34f3798d 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -2251,6 +2251,15 @@ config CMD_BEDBUG for some PowerPC processors. For details please see the documentation in doc/README.bedbug. +config CMD_CBSYSINFO + bool "cbsysinfo" + depends on X86 + default y if SYS_COREBOOT + help + This provides information about the coreboot sysinfo table stored in + memory by coreboot before jumping to U-Boot. It can be useful for + debugging the beaaviour of coreboot or U-Boot. + config CMD_DIAG bool "diag - Board diagnostics" help diff --git a/cmd/x86/Makefile b/cmd/x86/Makefile index 144b1cf5abe..5f82204c87e 100644 --- a/cmd/x86/Makefile +++ b/cmd/x86/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ +obj-$(CONFIG_CMD_CBSYSINFO) += cbsysinfo.o obj-y += mtrr.o obj-$(CONFIG_CMD_EXCEPTION) += exception.o obj-$(CONFIG_USE_HOB) += hob.o diff --git a/cmd/x86/cbsysinfo.c b/cmd/x86/cbsysinfo.c new file mode 100644 index 00000000000..a0db0ad364e --- /dev/null +++ b/cmd/x86/cbsysinfo.c @@ -0,0 +1,394 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Google LLC + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void cbprompt(const char *name) +{ + for (; *name == '>'; name++) + puts(" "); + printf("%-12s: ", name); +} + +static void print_dec(const char *name, int value) +{ + cbprompt(name); + printf(value > 9 ? "0d%d\n" : "%d\n", value); +} + +static void print_hex(const char *name, int value) +{ + cbprompt(name); + printf("%x\n", value); +} + +static void print_addr(const char *name, ulong value) +{ + cbprompt(name); + printf("%08lx\n", value); +} + +static void print_addr64(const char *name, u64 value) +{ + cbprompt(name); + printf("%16llx\n", value); +} + +static void print_ptr(const char *name, const void *value) +{ + cbprompt(name); + printf("%p\n", value); +} + +static void print_str(const char *name, const char *value) +{ + if (value) { + cbprompt(name); + printf("%s\n", value); + } +} + +static void print_idx(const char *name, uint idx, const u8 *strings) +{ + const char *ptr; + + cbprompt(name); + ptr = (char *)strings + idx; + printf("%d: %s\n", idx, ptr ? ptr : "(unknown)"); +} + +static const char *const cb_mem_name[] = { + NULL, + "ram", + "reserved", + "acpi", + "nvs", + "unusable", + "vendor", +}; + +static const char *get_mem_name(int tag) +{ + if (tag >= CB_MEM_RAM && tag <= CB_MEM_VENDOR_RSVD) + return cb_mem_name[tag]; + + if (tag == CB_MEM_TABLE) + return "table"; + + return "(unknown)"; +} + +static const struct timestamp_id_to_name { + uint id; + const char *name; +} timestamp_ids[] = { + /* Marker to report base_time */ + { 0, "1st timestamp" }, + { TS_START_ROMSTAGE, "start of romstage" }, + { TS_BEFORE_INITRAM, "before ram initialization" }, + { TS_AFTER_INITRAM, "after ram initialization" }, + { TS_END_ROMSTAGE, "end of romstage" }, + { TS_START_VBOOT, "start of verified boot" }, + { TS_END_VBOOT, "end of verified boot" }, + { TS_START_COPYRAM, "starting to load ramstage" }, + { TS_END_COPYRAM, "finished loading ramstage" }, + { TS_START_RAMSTAGE, "start of ramstage" }, + { TS_START_BOOTBLOCK, "start of bootblock" }, + { TS_END_BOOTBLOCK, "end of bootblock" }, + { TS_START_COPYROM, "starting to load romstage" }, + { TS_END_COPYROM, "finished loading romstage" }, + { TS_START_ULZMA, "starting LZMA decompress (ignore for x86)" }, + { TS_END_ULZMA, "finished LZMA decompress (ignore for x86)" }, + { TS_START_ULZ4F, "starting LZ4 decompress (ignore for x86)" }, + { TS_END_ULZ4F, "finished LZ4 decompress (ignore for x86)" }, + { TS_DEVICE_ENUMERATE, "device enumeration" }, + { TS_DEVICE_CONFIGURE, "device configuration" }, + { TS_DEVICE_ENABLE, "device enable" }, + { TS_DEVICE_INITIALIZE, "device initialization" }, + { TS_DEVICE_DONE, "device setup done" }, + { TS_CBMEM_POST, "cbmem post" }, + { TS_WRITE_TABLES, "write tables" }, + { TS_FINALIZE_CHIPS, "finalize chips" }, + { TS_LOAD_PAYLOAD, "load payload" }, + { TS_ACPI_WAKE_JUMP, "ACPI wake jump" }, + { TS_SELFBOOT_JUMP, "selfboot jump" }, + + { TS_START_COPYVER, "starting to load verstage" }, + { TS_END_COPYVER, "finished loading verstage" }, + { TS_START_TPMINIT, "starting to initialize TPM" }, + { TS_END_TPMINIT, "finished TPM initialization" }, + { TS_START_VERIFY_SLOT, "starting to verify keyblock/preamble (RSA)" }, + { TS_END_VERIFY_SLOT, "finished verifying keyblock/preamble (RSA)" }, + { TS_START_HASH_BODY, "starting to verify body (load+SHA2+RSA) " }, + { TS_DONE_LOADING, "finished loading body (ignore for x86)" }, + { TS_DONE_HASHING, "finished calculating body hash (SHA2)" }, + { TS_END_HASH_BODY, "finished verifying body signature (RSA)" }, + + { TS_START_COPYVPD, "starting to load Chrome OS VPD" }, + { TS_END_COPYVPD_RO, "finished loading Chrome OS VPD (RO)" }, + { TS_END_COPYVPD_RW, "finished loading Chrome OS VPD (RW)" }, + + { TS_U_BOOT_INITTED, "U-Boot start" }, + { TS_RO_PARAMS_INIT, "RO parameter init" }, + { TS_RO_VB_INIT, "RO vboot init" }, + { TS_RO_VB_SELECT_FIRMWARE, "RO vboot select firmware" }, + { TS_RO_VB_SELECT_AND_LOAD_KERNEL, "RO vboot select&load kernel" }, + { TS_RW_VB_SELECT_AND_LOAD_KERNEL, "RW vboot select&load kernel" }, + { TS_VB_SELECT_AND_LOAD_KERNEL, "vboot select&load kernel" }, + { TS_VB_EC_VBOOT_DONE, "finished EC verification" }, + { TS_VB_STORAGE_INIT_DONE, "finished storage device initialization" }, + { TS_VB_READ_KERNEL_DONE, "finished reading kernel from disk" }, + { TS_VB_VBOOT_DONE, "finished vboot kernel verification" }, + { TS_KERNEL_DECOMPRESSION, "starting kernel decompression/relocation" }, + { TS_START_KERNEL, "jumping to kernel" }, + { TS_U_BOOT_START_KERNEL, "just before jump to kernel" }, + + /* Intel ME-related timestamps */ + { TS_ME_INFORM_DRAM_WAIT, "waiting for ME acknowledgment of raminit"}, + { TS_ME_INFORM_DRAM_DONE, "finished waiting for ME response"}, + + /* FSP-related timestamps */ + { TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit" }, + { TS_FSP_MEMORY_INIT_END, "returning from FspMemoryInit" }, + { TS_FSP_TEMP_RAM_EXIT_START, "calling FspTempRamExit" }, + { TS_FSP_TEMP_RAM_EXIT_END, "returning from FspTempRamExit" }, + { TS_FSP_SILICON_INIT_START, "calling FspSiliconInit" }, + { TS_FSP_SILICON_INIT_END, "returning from FspSiliconInit" }, + { TS_FSP_BEFORE_ENUMERATE, "calling FspNotify(AfterPciEnumeration)" }, + { TS_FSP_AFTER_ENUMERATE, + "returning from FspNotify(AfterPciEnumeration)" }, + { TS_FSP_BEFORE_FINALIZE, "calling FspNotify(ReadyToBoot)" }, + { TS_FSP_AFTER_FINALIZE, "returning from FspNotify(ReadyToBoot)" }, + { TS_FSP_BEFORE_END_OF_FIRMWARE, "calling FspNotify(EndOfFirmware)" }, + { TS_FSP_AFTER_END_OF_FIRMWARE, + "returning from FspNotify(EndOfFirmware)" }, +}; + +static const char *timestamp_name(uint32_t id) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(timestamp_ids); i++) { + if (timestamp_ids[i].id == id) + return timestamp_ids[i].name; + } + + return ""; +} + +static void show_table(struct sysinfo_t *info, bool verbose) +{ + struct cb_serial *ser = info->serial; + int i; + + printf("Coreboot table at %lx, decoded to %p", + gd->arch.coreboot_table, info); + if (info->header) + printf(", forwarded to %p\n", info->header); + printf("\n"); + + print_dec("CPU KHz", info->cpu_khz); + + print_addr("Serial I/O port", info->ser_ioport); + print_addr(">base", info->ser_base); + print_ptr(">pointer", ser); + if (ser) { + print_hex(">type", ser->type); + print_addr(">base", ser->baseaddr); + print_dec(">baud", ser->baud); + print_hex(">baud", ser->regwidth); + print_dec(">input_hz", ser->input_hertz); + print_addr(">PCI addr", ser->uart_pci_addr); + } + + print_dec("Mem ranges", info->n_memranges); + printf("%12s: %-11s || base || size\n", "id", "type"); + for (i = 0; i < info->n_memranges; i++) { + const struct memrange *mr = &info->memrange[i]; + + printf("%12d: %02x:%-8s %016llx %016llx\n", i, mr->type, + get_mem_name(mr->type), mr->base, mr->size); + } + print_ptr("option_table", info->option_table); + + print_hex("CMOS start", info->cmos_range_start); + if (info->cmos_range_start) { + print_hex(">CMOS end", info->cmos_range_end); + print_hex(">CMOS csum loc", info->cmos_checksum_location); + } + + print_hex("VBNV start", info->vbnv_start); + print_hex("VBNV size", info->vbnv_size); + + print_str("CB version", info->cb_version); + print_str(">Extra", info->extra_version); + print_str(">Build", info->build); + print_str(">Time", info->compile_time); + print_str(">By", info->compile_by); + print_str(">Host", info->compile_host); + print_str(">Domain", info->compile_domain); + print_str(">Compiler", info->compiler); + print_str(">Linker", info->linker); + print_str(">Assembler", info->assembler); + + print_ptr("Framebuffer", info->framebuffer); + if (info->framebuffer) { + struct cb_framebuffer *fb = info->framebuffer; + + print_addr64(">Phys addr", fb->physical_address); + print_dec(">X res", fb->x_resolution); + print_dec(">X res", fb->y_resolution); + print_hex(">Bytes / line", fb->bytes_per_line); + print_dec(">Bpp", fb->bits_per_pixel); + printf(" %-12s red %d/%d, green %d/%d, blue %d/%d, reserved %d/%d\n", + "pos/size", fb->red_mask_pos, fb->red_mask_size, + fb->green_mask_pos, fb->green_mask_size, + fb->blue_mask_pos, fb->blue_mask_size, + fb->reserved_mask_pos, fb->reserved_mask_size); + } + + print_dec("GPIOs", info->num_gpios); + printf("%12s: %4s %12s %3s %s\n", "id", "port", "polarity", "val", + "name"); + for (i = 0; i < info->num_gpios; i++) { + const struct cb_gpio *gpio = &info->gpios[i]; + char portstr[4]; + + if (gpio->port == 0xffffffff) + strcpy(portstr, "-"); + else + sprintf(portstr, "%x", gpio->port); + printf("%12d: %4s %12s %3d %s\n", i, portstr, + gpio->polarity == CB_GPIO_ACTIVE_LOW ? "active-low" : + "active-high", gpio->value, gpio->name); + } + print_dec("MACs", info->num_macs); + for (i = 0; i < info->num_macs; i++) { + const struct mac_address *mac = &info->macs[i]; + int j; + + printf("%12d: ", i); + for (j = 0; j < sizeof(mac->mac_addr); j++) + printf("%s%02x", j ? ":" : "", mac->mac_addr[j]); + printf("\n"); + } + print_str(">Serial #", info->serialno); + print_ptr("Multiboot tab", info->mbtable); + print_ptr("CB header", info->header); + print_ptr("CB mainboard", info->mainboard); + if (info->mainboard) { + struct cb_mainboard *mb = info->mainboard; + + print_idx(">vendor", mb->vendor_idx, mb->strings); + print_idx(">part_number", mb->part_number_idx, mb->strings); + } + print_ptr("vboot handoff", info->vboot_handoff); + print_hex(">size", info->vboot_handoff_size); + print_ptr(">vdat addr", info->vdat_addr); + print_hex(">size", info->vdat_size); + + print_addr64("SMBIOS", info->smbios_start); + print_hex(">size", info->smbios_size); + print_hex("ROM MTRR", info->x86_rom_var_mtrr_index); + + print_ptr("Tstamp table", info->tstamp_table); + if (verbose && info->tstamp_table) { + struct timestamp_table *ts = info->tstamp_table; + + printf("%-12s", "Base_time"); + print_grouped_ull(ts->base_time, 12); + printf("\n"); + print_dec("Tick MHz", ts->tick_freq_mhz); + for (i = 0; i < ts->num_entries; i++) { + const struct timestamp_entry *tse; + + tse = &ts->entries[i]; + printf(" "); + print_grouped_ull(tse->entry_stamp, 12); + printf(" %s\n", timestamp_name(tse->entry_id)); + } + } + + print_ptr("CBmem cons", info->cbmem_cons); + if (info->cbmem_cons) { + struct cbmem_console *cons = info->cbmem_cons; + int i; + + print_hex("Size", cons->size); + print_hex("Cursor", cons->cursor); + if (verbose) { + for (i = 0; i < cons->cursor; i++) { + int ch = cons->body[i]; + + putc(ch); + + if (ch == '\n') { + /* check for ctrl-c to abort... */ + if (ctrlc()) { + puts("Abort\n"); + return; + } + printf(" "); + } + } + printf("\n"); + } + } + + print_ptr("MRC cache", info->mrc_cache); + print_ptr("ACPI GNVS", info->acpi_gnvs); + print_hex("Board ID", info->board_id); + print_hex("RAM code", info->ram_code); + print_ptr("WiFi calib", info->wifi_calibration); + print_addr64("Ramoops buff", info->ramoops_buffer); + print_hex(">size", info->ramoops_buffer_size); + print_hex("SF size", info->spi_flash.size); + print_hex("SF sector", info->spi_flash.sector_size); + print_hex("SF erase cmd", info->spi_flash.erase_cmd); + + print_addr64("FMAP offset", info->fmap_offset); + print_addr64("CBFS offset", info->cbfs_offset); + print_addr64("CBFS size", info->cbfs_size); + print_addr64("Boot media size", info->boot_media_size); + print_addr64("MTC start", info->mtc_start); + print_hex("MTC size", info->mtc_size); + + print_ptr("Chrome OS VPD", info->chromeos_vpd); +} + +static int do_cbsysinfo(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + bool verbose = false; + + if (argc > 1) { + if (!strcmp("-v", argv[1])) + verbose = true; + else + return CMD_RET_USAGE; + } + + if (!gd->arch.coreboot_table) { + printf("No coreboot sysinfo table found\n"); + return CMD_RET_FAILURE; + } + show_table(&lib_sysinfo, verbose); + + return 0; +} + +U_BOOT_CMD( + cbsysinfo, 2, 1, do_cbsysinfo, + "Show coreboot sysinfo table", + "[-v] Dumps out the contents of the sysinfo table. This only\n" + "works if U-Boot is booted from coreboot" +); diff --git a/doc/usage/index.rst b/doc/usage/index.rst index 35c515f8b59..fb834349ca3 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -21,6 +21,7 @@ Shell commands booti bootmenu button + x86/cbsysinfo conitrace echo exception diff --git a/doc/usage/x86/cbsysinfo.rst b/doc/usage/x86/cbsysinfo.rst new file mode 100644 index 00000000000..8c03a85169d --- /dev/null +++ b/doc/usage/x86/cbsysinfo.rst @@ -0,0 +1,25 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +cbsysinfo +========= + +Synopis +------- + +:: + + cbsysinfo + + +Description +----------- + +This displays information obtained from the coreboot sysinfo table. It is only +useful when booting U-Boot from coreboot. + +Example +------- + +:: + + => cbsysinfo -- cgit v1.3.1 From 1758551ec9526d56303a2b5cf1f58147e66945ed Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 15 Mar 2021 18:11:11 +1300 Subject: sandbox: Provide a way to bind fixed/removeable devices At present when a file is bound to a host device it is always marked as removeable. Arguably the device is removeable, since it can be unbound at will. However while it is bound, it is not considered removable by the user. Also it is useful to be able to model both fixed and removeable devices for code that distinguishes them. Add a -r flag to the 'host bind' command and plumb it through to provide this feature. Signed-off-by: Simon Glass --- cmd/host.c | 19 +++++++++++++++---- doc/arch/sandbox.rst | 2 ++ drivers/block/sandbox.c | 8 ++++---- include/sandboxblockdev.h | 9 ++++++++- 4 files changed, 29 insertions(+), 9 deletions(-) (limited to 'doc') diff --git a/cmd/host.c b/cmd/host.c index 847bb1d3b5f..6aa3d9167a4 100644 --- a/cmd/host.c +++ b/cmd/host.c @@ -41,6 +41,7 @@ static int do_host_save(struct cmd_tbl *cmdtp, int flag, int argc, static int do_host_bind(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + bool removable = false; const char *dev_str; char *file; char *ep; @@ -49,7 +50,16 @@ static int do_host_bind(struct cmd_tbl *cmdtp, int flag, int argc, /* Skip 'bind' */ argc--; argv++; - if (argc < 1 || argv > 2) + if (argc < 2) + return CMD_RET_USAGE; + + if (!strcmp(argv[0], "-r")) { + removable = true; + argc--; + argv++; + } + + if (argc > 2) return CMD_RET_USAGE; dev_str = argv[0]; dev = simple_strtoul(dev_str, &ep, 16); @@ -59,7 +69,7 @@ static int do_host_bind(struct cmd_tbl *cmdtp, int flag, int argc, } file = argc > 1 ? argv[1] : NULL; - return !!host_dev_bind(dev, file); + return !!host_dev_bind(dev, file, removable); } static int do_host_info(struct cmd_tbl *cmdtp, int flag, int argc, @@ -154,7 +164,7 @@ static struct cmd_tbl cmd_host_sub[] = { U_BOOT_CMD_MKENT(ls, 3, 0, do_host_ls, "", ""), U_BOOT_CMD_MKENT(save, 6, 0, do_host_save, "", ""), U_BOOT_CMD_MKENT(size, 3, 0, do_host_size, "", ""), - U_BOOT_CMD_MKENT(bind, 3, 0, do_host_bind, "", ""), + U_BOOT_CMD_MKENT(bind, 4, 0, do_host_bind, "", ""), U_BOOT_CMD_MKENT(info, 3, 0, do_host_info, "", ""), U_BOOT_CMD_MKENT(dev, 0, 1, do_host_dev, "", ""), }; @@ -186,7 +196,8 @@ U_BOOT_CMD( "host save hostfs - [] - " "save a file to host\n" "host size hostfs - - determine size of file on host\n" - "host bind [] - bind \"host\" device to file\n" + "host bind [-r] [] - bind \"host\" device to file\n" + " -r = mark as removable\n" "host info [] - show device binding & info\n" "host dev [] - Set or retrieve the current host device\n" "host commands use the \"hostfs\" device. The \"host\" device is used\n" diff --git a/doc/arch/sandbox.rst b/doc/arch/sandbox.rst index 8b18a221172..e052b6bdb09 100644 --- a/doc/arch/sandbox.rst +++ b/doc/arch/sandbox.rst @@ -389,6 +389,8 @@ the contents of the root directory on the second partion of the image =>host bind 0 ./disk.raw =>ls host 0:2 +The device can be marked removeable with 'host bind -r'. + A disk image can be created using the following commands:: $> truncate -s 1200M ./disk.raw diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c index e2f229b15db..1c2c3b4f886 100644 --- a/drivers/block/sandbox.c +++ b/drivers/block/sandbox.c @@ -89,7 +89,7 @@ static unsigned long host_block_write(struct blk_desc *block_dev, } #ifdef CONFIG_BLK -int host_dev_bind(int devnum, char *filename) +int host_dev_bind(int devnum, char *filename, bool removable) { struct host_block_dev *host_dev; struct udevice *dev; @@ -146,7 +146,7 @@ int host_dev_bind(int devnum, char *filename) } desc = blk_get_devnum_by_type(IF_TYPE_HOST, devnum); - desc->removable = 1; + desc->removable = removable; snprintf(desc->vendor, BLK_VEN_SIZE, "U-Boot"); snprintf(desc->product, BLK_PRD_SIZE, "hostfile"); snprintf(desc->revision, BLK_REV_SIZE, "1.0"); @@ -160,7 +160,7 @@ err: return ret; } #else -int host_dev_bind(int dev, char *filename) +int host_dev_bind(int dev, char *filename, bool removable) { struct host_block_dev *host_dev = find_host_device(dev); @@ -195,7 +195,7 @@ int host_dev_bind(int dev, char *filename) blk_dev->block_write = host_block_write; blk_dev->devnum = dev; blk_dev->part_type = PART_TYPE_UNKNOWN; - blk_dev->removable = 1; + blk_dev->removable = removable; snprintf(blk_dev->vendor, BLK_VEN_SIZE, "U-Boot"); snprintf(blk_dev->product, BLK_PRD_SIZE, "hostfile"); snprintf(blk_dev->revision, BLK_REV_SIZE, "1.0"); diff --git a/include/sandboxblockdev.h b/include/sandboxblockdev.h index c1f0afb337d..4006e942a02 100644 --- a/include/sandboxblockdev.h +++ b/include/sandboxblockdev.h @@ -14,6 +14,13 @@ struct host_block_dev { int fd; }; -int host_dev_bind(int dev, char *filename); +/** + * host_dev_bind() - Bind or unbind a device + * + * @dev: Device number (0=first slot) + * @filename: Host filename to use, or NULL to unbind + * @removable: true if the block device should mark itself as removable + */ +int host_dev_bind(int dev, char *filename, bool removable); #endif -- cgit v1.3.1 From 2d0423aff9fd9adc0933f94df6726e29ee2c89be Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 15 Mar 2021 18:11:20 +1300 Subject: doc: Convert Chromium OS docs to rst Move this documentation over to reST. Move the example files into a files/ directory so they are still separate. Do a few minor updates while we are here: - Tidy up sandbox build instructions - Update my github account name - Add some talks and links Signed-off-by: Simon Glass --- doc/README.chromium | 218 ----------------- doc/README.chromium-chainload | 239 ------------------- doc/chromium/chainload.rst | 257 +++++++++++++++++++++ doc/chromium/chromebook_jerry.its | 42 ---- doc/chromium/devkeys/kernel.keyblock | Bin 1208 -> 0 bytes doc/chromium/devkeys/kernel_data_key.vbprivk | Bin 1199 -> 0 bytes doc/chromium/files/chromebook_jerry.its | 42 ++++ doc/chromium/files/devkeys/kernel.keyblock | Bin 0 -> 1208 bytes doc/chromium/files/devkeys/kernel_data_key.vbprivk | Bin 0 -> 1199 bytes doc/chromium/files/nyan-big.its | 42 ++++ doc/chromium/index.rst | 14 ++ doc/chromium/nyan-big.its | 42 ---- doc/chromium/overview.rst | 74 ++++++ doc/chromium/run_vboot.rst | 204 ++++++++++++++++ doc/index.rst | 8 + 15 files changed, 641 insertions(+), 541 deletions(-) delete mode 100644 doc/README.chromium delete mode 100644 doc/README.chromium-chainload create mode 100644 doc/chromium/chainload.rst delete mode 100644 doc/chromium/chromebook_jerry.its delete mode 100644 doc/chromium/devkeys/kernel.keyblock delete mode 100644 doc/chromium/devkeys/kernel_data_key.vbprivk create mode 100644 doc/chromium/files/chromebook_jerry.its create mode 100644 doc/chromium/files/devkeys/kernel.keyblock create mode 100644 doc/chromium/files/devkeys/kernel_data_key.vbprivk create mode 100644 doc/chromium/files/nyan-big.its create mode 100644 doc/chromium/index.rst delete mode 100644 doc/chromium/nyan-big.its create mode 100644 doc/chromium/overview.rst create mode 100644 doc/chromium/run_vboot.rst (limited to 'doc') diff --git a/doc/README.chromium b/doc/README.chromium deleted file mode 100644 index 75f2f24042c..00000000000 --- a/doc/README.chromium +++ /dev/null @@ -1,218 +0,0 @@ -Chromium OS Support in U-Boot -============================= - -Introduction ------------- - -This describes how to use U-Boot with Chromium OS. Several options are -available: - - - Running U-Boot from the 'altfw' feature, which is available on selected - Chromebooks from 2019 onwards (initially Grunt). Press '1' from the - developer-mode screen to get into U-Boot. See here for details: - https://sites.google.com/a/chromium.org/dev/chromium-os/poking-around-your-chrome-os-device?pli=1 - - - Running U-Boot from the disk partition. This involves signing U-Boot and - placing it on the disk, for booting as a 'kernel'. See - README.chromium-chainload for information on this. This is the only - option on non-U-Boot Chromebooks from 2013 to 2018 and is somewhat - more involved. - - - Running U-Boot with Chromium OS verified boot. This allows U-Boot to be - used instead of either or both of depthcharge (a bootloader which forked - from U-Boot in 2013) and coreboot. See below for more information on - this. - - - Running U-Boot from coreboot. This allows U-Boot to run on more devices - since many of them only support coreboot as the bootloader and have - no bare-metal support in U-Boot. For this, use the 'coreboot' target. - - - Running U-Boot and booting into a Chrome OS image, but without verified - boot. This can be useful for testing. - - -U-Boot with Chromium OS verified boot -------------------------------------- - -To obtain: - - git clone https://github.com/sglass68/u-boot.git - cd u-boot - git checkout cros-master - - cd .. - git clone https://chromium.googlesource.com/chromiumos/platform/vboot_reference - cd vboot_reference - git checkout 45964294 - # futility: updater: Correct output version for Snow - -To build for sandbox: - - UB=/tmp/b/chromeos_sandbox # U-Boot build directory - cd u-boot - make O=$UB chromeos_sandbox_defconfig - make O=$UB -j20 -s VBOOT_SOURCE=/path/to/vboot_reference \ - MAKEFLAGS_VBOOT=DEBUG=1 QUIET=1 - -Replace sandbox with another supported target. - -This produces $UB/image.bin which contains the firmware binaries in a SPI -flash image. - -To run on sandbox: - - $UB/tpl/u-boot-tpl -d $UB/u-boot.dtb.out \ - -L6 -c "host bind 0 $CROS/src/build/images/cheza/latest/chromiumos_image.bin; vboot go auto" \ - -l -w -s state.dtb -r - -To run on other boards: - Install image.bin in the SPI flash of your device - Boot your system - - -Sandbox -------- - -Most Chromium OS development with U-Boot is undertaken using sandbox. There is -a sandbox target available (chromeos_sandbox) which allows running U-Boot on -a Linux machine completion with emulations of the display, TPM, disk, etc. - -Running sandbox starts TPL, which contains the first phase of vboot, providing -a device tree and binding a Chromium OS disk image for use to find kernels -(any Chromium OS image will do). It also saves driver state between U-Boot -phases into state.dtb and will automatically ensure that memory is shared -between all phases. TPL will jump to SPL and then on to U-Boot proper. - -It is possible to run with debugging on, e.g. - - gdb --args $UB/tpl/u-boot-tpl -d .... - -Breakpoints can be set in any U-Boot phase. Overall this is a good debugging -environment for new verified-boot features. - - -Samus ------ - -Basic support is available for samus, using the chromeos_samus target. If you -have an em100, use: - - sudo em100 -s -c W25Q128FW -d $UB/image.bin -t -r - -to write the image and then boot samus (Power-Refresh). - - -Boot flow ---------- - -Verified boot starts in TPL, which selects the A or B SPL, which in turn selects -the A or B U-Boot. Then this jumps to the selected kernel. If anything goes -wrong, the device reboots and the recovery SPL and U-Boot are used instead. - -More details are available here: - - https://www.chromium.org/chromium-os/chromiumos-design-docs/firmware-boot-and-recovery - - -New uclasses ------------- - -Several uclasses are provided in cros/: - - UCLASS_CROS_AUX_FW Chrome OS auxiliary firmware - UCLASS_CROS_FWSTORE Chrome OS firmware storage - UCLASS_CROS_NVDATA Chrome OS non-volatile data device - UCLASS_CROS_VBOOT_EC Chrome OS vboot EC operations - UCLASS_CROS_VBOOT_FLAG Chrome OS verified boot flag - -The existing UCLASS_CROS_EC is also used. - - -Commands --------- - -A new 'vboot' command is provided to run particular vboot stages. The most -useful command is 'vboot go auto', which continues where the last stage left -off. - -Note that TPL and SPL do not supports commands as yet, so the vboot code is -called directly from the SPL boot devices (BOOT_DEVICE_CROS_VBOOT). See -cros_load_image_tpl() and cros_load_image_spl() which both call -vboot_run_auto(). - - -Config options --------------- - -The main option is CONFIG_CHROMEOS, which enables a wide array of other options -so that the required features are present. - - -Device-tree config ------------------- - -Various options are available which control the operation of verified boot. -See cros/dts/bindings/config.txt for details. Most config is handled at run- -time, although build-time config (with Kconfig) could also be added fairly -easily. - - -Porting to other hardware -------------------------- - -A basic port to samus (Chromebook Pixel 2015) is in a basic working state, -using the chromeos_samus target. Patches will likely be forthcoming in early -2019. Ports to an ARM board and coreboot (for x86 Chromebooks) are in the -dreaming state. - - -Tests ------ - -Chromium OS firmware has a very limited set of tests. The tests that originally -existed in U-Boot were not brought over to coreboot or depthcharge. - -The U-Boot tests ('make check') do operate, but at present there are no -Chromium OS tests available. These will hopefully come together over time. Of -course the above sandbox feature provides a sort of functional test and can -detect problems that affect the flow or particular vboot features. - - -U-Boot without Chromium OS verified boot ----------------------------------------- - -The following script can be used to boot a Chrome OS image on coral: - - # Read the image header and obtain the address of the kernel - # The offset 4f0 is defined by verified boot and may change for other - # Chromebooks - read mmc 2:2 100000 0 80; setexpr loader *001004f0; - - # Get the kernel size and calculate the number of blocks (0x200 bytes each) - setexpr size *00100518; setexpr blocks $size / 200; - - # Read the full kernel and calculate the address of the setup block - read mmc 2:2 100000 80 $blocks; setexpr setup $loader - 1000; - - # Locate the command line - setexpr cmdline $loader - 2000; - - # Start the zboot process with the loaded kernel, setup block and cmdline - zboot start 100000 0 0 0 $setup $cmdline; - - # Load the kernel, fix up the 'setup' block, dump information - zboot load; zboot setup; zboot dump - - # Boot into Chrome OS - zboot go - - -TO DO ------ - -Get the full ACPI tables working with Coral - - -Simon Glass -sjg@chromium.org -7 October 2018 diff --git a/doc/README.chromium-chainload b/doc/README.chromium-chainload deleted file mode 100644 index 45eaeced2da..00000000000 --- a/doc/README.chromium-chainload +++ /dev/null @@ -1,239 +0,0 @@ -Running U-Boot from coreboot on Chromebooks -=========================================== - -U-Boot can be used as a secondary boot loader in a few situations such as from -UEFI and coreboot (see README.x86). Recent Chromebooks use coreboot even on -ARM platforms to start up the machine. - -This document aims to provide a guide to booting U-Boot on a Chromebook. It -is only a starting point, and there are many guides on the interwebs. But -placing this information in the U-Boot tree should make it easier to find for -those who use U-Boot habitually. - -Most of these platforms are supported by U-Boot natively, but it is risky to -replace the ROM unless you have a servo board and cable to restore it with. - - -For all of these the standard U-Boot build instructions apply. For example on -ARM: - - sudo apt install gcc-arm-linux-gnueabi - mkdir b - make O=b/nyan_big CROSS_COMPILE=arm-linux-gnueabi- nyan-big_defconfig all - -You can obtain the vbutil_kernel utility here: - - https://drive.google.com/open?id=0B7WYZbZ9zd-3dHlVVXo4VXE2T0U - - -Snow (Samsung ARM Chromebook) ------------------------------ - -See here: - -https://www.chromium.org/chromium-os/firmware-porting-guide/using-nv-u-boot-on-the-samsung-arm-chromebook - - -Nyan-big --------- - -Compiled based on information here: -https://lists.denx.de/pipermail/u-boot/2015-March/209530.html -https://git.collabora.com/cgit/user/tomeu/u-boot.git/commit/?h=nyan-big -https://lists.denx.de/pipermail/u-boot/2017-May/289491.html -https://github.com/chromeos-nvidia-androidtv/gnu-linux-on-acer-chromebook-13#copy-data-to-the-sd-card - -1. Build U-Boot - - mkdir b - make -j8 O=b/nyan-big CROSS_COMPILE=arm-linux-gnueabi- nyan-big_defconfig all - - -2. Select a .its file - -Select something from doc/chromium which matches your board, or create your -own. - -Note that the device tree node is required, even though it is not actually -used by U-Boot. This is because the Chromebook expects to pass it to the -kernel, and crashes if it is not present. - - -3. Build and sign an image - - ./b/nyan-big/tools/mkimage -f doc/chromium/nyan-big.its u-boot-chromium.fit - echo test >dummy.txt - vbutil_kernel --arch arm --keyblock doc/chromium/devkeys/kernel.keyblock \ - --signprivate doc/chromium/devkeys/kernel_data_key.vbprivk \ - --version 1 --config dummy.txt --vmlinuz u-boot-chromium.fit \ - --bootloader dummy.txt --pack u-boot.kpart - - -4. Prepare an SD card - - DISK=/dev/sdc # Replace with your actual SD card device - sudo cgpt create $DISK - sudo cgpt add -b 34 -s 32768 -P 1 -S 1 -t kernel $DISK - sudo cgpt add -b 32802 -s 2000000 -t rootfs $DISK - sudo gdisk $DISK # Enter command 'w' to write a protective MBR to the disk - - -5. Write U-Boot to the SD card - - sudo dd if=u-boot.kpart of=/dev/sdc1; sync - - -6. Start it up - -Reboot the device in dev mode. Make sure that you have USB booting enabled. To -do this, login as root (via Ctrl-Alt-forward_arrow) and type -'enable_dev_usb_boot'. You only need to do this once. - -Reboot the device with the SD card inserted. Press Clrl-U at the developer -mode screen. It should show something like the following on the display: - - U-Boot 2017.07-00637-g242eb42-dirty (May 22 2017 - 06:14:21 -0600) - - Model: Acer Chromebook 13 CB5-311 - Board: Google/NVIDIA Nyan-big, ID: 1 - - Net: No ethernet found. - Hit any key to stop autoboot: 0 - Tegra124 (Nyan-big) # - - -7. Known problems - -On the serial console the word MMC is chopped at the start of the line: - -C: sdhci@700b0000: 2, sdhci@700b0400: 1, sdhci@700b0600: 0 - -This is likely due to some problem with change-over of the serial driver -during relocation (or perhaps updating the clock setup in board_init()). - - -9. Notes - -To check that you copied the u-boot.its file correctly, use these commands. -You should see that the data at 0x100 in u-boot-chromium.fit is the first few -bytes of U-Boot: - - hd u-boot-chromium.fit |head -20 - ... - 00000100 b8 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................| - - hd b/nyan-big/u-boot.bin |head - 00000000 b8 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................| - - -The 'data' property of the FIT is set up to start at offset 0x100 bytes into -the file. The change to CONFIG_SYS_TEXT_BASE is also an offset of 0x100 bytes -from the load address. If this changes, you either need to modify U-Boot to be -fully relocatable, or expect it to hang. - - -chromebook_jerry ----------------- - -The instruction are similar to those for Nyan with changes as noted below: - -1. Patch U-Boot - -Open include/configs/rk3288_common.h - -Change: - -#define CONFIG_SYS_TEXT_BASE 0x00100000 - -to: - -#define CONFIG_SYS_TEXT_BASE 0x02000100 - - - -2. Build U-Boot - - mkdir b - make -j8 O=b/chromebook_jerry CROSS_COMPILE=arm-linux-gnueabi- \ - chromebook_jerry_defconfig all - - -3. See above - -4. Build and sign an image - - ./b/chromebook_jerry/tools/mkimage -f doc/chromium/chromebook_jerry.its \ - u-boot-chromium.fit - echo test >dummy.txt - vbutil_kernel --arch arm --keyblock doc/chromium/devkeys/kernel.keyblock \ - --signprivate doc/chromium/devkeys/kernel_data_key.vbprivk \ - --version 1 --config dummy.txt --vmlinuz u-boot-chromium.fit \ - --bootloader dummy.txt --pack u-boot.kpart - - -5. See above - -6. See above - -7. Start it up - -Reboot the device in dev mode. Make sure that you have USB booting enabled. To -do this, login as root (via Ctrl-Alt-forward_arrow) and type -'enable_dev_usb_boot'. You only need to do this once. - -Reboot the device with the SD card inserted. Press Clrl-U at the developer -mode screen. It should show something like the following on the display: - - U-Boot 2017.05-00649-g72acdbf-dirty (May 29 2017 - 14:57:05 -0600) - - Model: Google Jerry - Net: Net Initialization Skipped - No ethernet found. - Hit any key to stop autoboot: 0 - - -8. Known problems - -None as yet. - - -9. Notes - -None as yet. - - -Other notes -=========== - -flashrom --------- - - Used to make a backup of your firmware, or to replace it. - - See: https://www.chromium.org/chromium-os/packages/cros-flashrom - - -coreboot --------- - -Coreboot itself is not designed to actually boot an OS. Instead, a program -called Depthcharge is used. This originally came out of U-Boot and was then -heavily hacked and modified such that is is almost unrecognisable. It does -include a very small part of the U-Boot command-line interface but is not -usable as a general-purpose boot loader. - -In addition, it has a very unusual design in that it does not do device init -itself, but instead relies on coreboot. This is similar to (in U-Boot) having -a SPI driver with an empty probe() method, relying on whatever was set up -beforehand. It can be quite hard to figure out between these two code bases -what settings are actually used. When chain-loading into U-Boot we must be -careful to reinit anything that U-Boot expects. If not, some peripherals (or -the whole machine) may not work. This makes the process of chainloading more -complicated than it could be on some platforms. - -Finally, it supports only a subset of the U-Boot's FIT format. In particular -it uses a fixed address to load the FIT and does not support load/exec -addresses. This means that U-Boot must be able to boot from whatever -address Depthcharge happens to use (it is the CONFIG_KERNEL_START setting -in Depthcharge). In practice this means that the data in the kernel@1 FIT node -(see above) must start at the same address as U-Boot's CONFIG_SYS_TEXT_BASE. diff --git a/doc/chromium/chainload.rst b/doc/chromium/chainload.rst new file mode 100644 index 00000000000..7b6bb10d36d --- /dev/null +++ b/doc/chromium/chainload.rst @@ -0,0 +1,257 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright 2020 Google LLC + +Running U-Boot from coreboot on Chromebooks +=========================================== + +U-Boot can be used as a secondary boot loader in a few situations such as from +UEFI and coreboot (see README.x86). Recent Chromebooks use coreboot even on +ARM platforms to start up the machine. + +This document aims to provide a guide to booting U-Boot on a Chromebook. It +is only a starting point, and there are many guides on the interwebs. But +placing this information in the U-Boot tree should make it easier to find for +those who use U-Boot habitually. + +Most of these platforms are supported by U-Boot natively, but it is risky to +replace the ROM unless you have a servo board and cable to restore it with. + + +For all of these the standard U-Boot build instructions apply. For example on +ARM:: + + sudo apt install gcc-arm-linux-gnueabi + mkdir b + make O=b/nyan_big CROSS_COMPILE=arm-linux-gnueabi- nyan-big_defconfig all + +You can obtain the vbutil_kernel utility here: + + https://drive.google.com/open?id=0B7WYZbZ9zd-3dHlVVXo4VXE2T0U + + +Snow (Samsung ARM Chromebook) +----------------------------- + +See here: + +https://www.chromium.org/chromium-os/firmware-porting-guide/using-nv-u-boot-on-the-samsung-arm-chromebook + + +Nyan-big +-------- + +Compiled based on information here:: + + https://lists.denx.de/pipermail/u-boot/2015-March/209530.html + https://git.collabora.com/cgit/user/tomeu/u-boot.git/commit/?h=nyan-big + https://lists.denx.de/pipermail/u-boot/2017-May/289491.html + https://github.com/chromeos-nvidia-androidtv/gnu-linux-on-acer-chromebook-13#copy-data-to-the-sd-card + +1. Build U-Boot + +Steps:: + + mkdir b + make -j8 O=b/nyan-big CROSS_COMPILE=arm-linux-gnueabi- nyan-big_defconfig all + + +2. Select a .its file + +Select something from doc/chromium which matches your board, or create your +own. + +Note that the device tree node is required, even though it is not actually +used by U-Boot. This is because the Chromebook expects to pass it to the +kernel, and crashes if it is not present. + + +3. Build and sign an image + +Steps:: + + ./b/nyan-big/tools/mkimage -f doc/chromium/files/nyan-big.its u-boot-chromium.fit + echo test >dummy.txt + vbutil_kernel --arch arm \ + --keyblock doc/chromium/files/devkeys/kernel.keyblock \ + --signprivate doc/chromium/files/devkeys/kernel_data_key.vbprivk \ + --version 1 --config dummy.txt --vmlinuz u-boot-chromium.fit \ + --bootloader dummy.txt --pack u-boot.kpart + + +4. Prepare an SD card + +Steps:: + + DISK=/dev/sdc # Replace with your actual SD card device + sudo cgpt create $DISK + sudo cgpt add -b 34 -s 32768 -P 1 -S 1 -t kernel $DISK + sudo cgpt add -b 32802 -s 2000000 -t rootfs $DISK + sudo gdisk $DISK # Enter command 'w' to write a protective MBR to the disk + + +5. Write U-Boot to the SD card + +Steps:: + + sudo dd if=u-boot.kpart of=/dev/sdc1; sync + + +6. Start it up + +Reboot the device in dev mode. Make sure that you have USB booting enabled. To +do this, login as root (via Ctrl-Alt-forward_arrow) and type +'enable_dev_usb_boot'. You only need to do this once. + +Reboot the device with the SD card inserted. Press Clrl-U at the developer +mode screen. It should show something like the following on the display:: + + U-Boot 2017.07-00637-g242eb42-dirty (May 22 2017 - 06:14:21 -0600) + + Model: Acer Chromebook 13 CB5-311 + Board: Google/NVIDIA Nyan-big, ID: 1 + + Net: No ethernet found. + Hit any key to stop autoboot: 0 + Tegra124 (Nyan-big) # + + +7. Known problems + +On the serial console the word MMC is chopped at the start of the line:: + + C: sdhci@700b0000: 2, sdhci@700b0400: 1, sdhci@700b0600: 0 + +This is likely due to some problem with change-over of the serial driver +during relocation (or perhaps updating the clock setup in board_init()). + + +9. Notes + +To check that you copied the u-boot.its file correctly, use these commands. +You should see that the data at 0x100 in u-boot-chromium.fit is the first few +bytes of U-Boot:: + + hd u-boot-chromium.fit |head -20 + ... + 00000100 b8 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................| + + hd b/nyan-big/u-boot.bin |head + 00000000 b8 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................| + + +The 'data' property of the FIT is set up to start at offset 0x100 bytes into +the file. The change to CONFIG_SYS_TEXT_BASE is also an offset of 0x100 bytes +from the load address. If this changes, you either need to modify U-Boot to be +fully relocatable, or expect it to hang. + + +chromebook_jerry +---------------- + +The instruction are similar to those for Nyan with changes as noted below: + +1. Patch U-Boot + +Open include/configs/rk3288_common.h + +Change:: + + #define CONFIG_SYS_TEXT_BASE 0x00100000 + +to:: + + #define CONFIG_SYS_TEXT_BASE 0x02000100 + + + +2. Build U-Boot + +Steps:: + + mkdir b + make -j8 O=b/chromebook_jerry CROSS_COMPILE=arm-linux-gnueabi- \ + chromebook_jerry_defconfig all + + +3. See above + +4. Build and sign an image + +Steps:: + + ./b/chromebook_jerry/tools/mkimage -f doc/chromium/chromebook_jerry.its \ + u-boot-chromium.fit + echo test >dummy.txt + vbutil_kernel --arch arm \ + --keyblock doc/chromium/files/devkeys/kernel.keyblock \ + --signprivate doc/chromium/files/devkeys/kernel_data_key.vbprivk \ + --version 1 --config dummy.txt --vmlinuz u-boot-chromium.fit \ + --bootloader dummy.txt --pack u-boot.kpart + + +5. See above + +6. See above + +7. Start it up + +Reboot the device in dev mode. Make sure that you have USB booting enabled. To +do this, login as root (via Ctrl-Alt-forward_arrow) and type +'enable_dev_usb_boot'. You only need to do this once. + +Reboot the device with the SD card inserted. Press Clrl-U at the developer +mode screen. It should show something like the following on the display:: + + U-Boot 2017.05-00649-g72acdbf-dirty (May 29 2017 - 14:57:05 -0600) + + Model: Google Jerry + Net: Net Initialization Skipped + No ethernet found. + Hit any key to stop autoboot: 0 + + +8. Known problems + +None as yet. + + +9. Notes + +None as yet. + + +Other notes +----------- + +flashrom +~~~~~~~~ + +Used to make a backup of your firmware, or to replace it. + +See: https://www.chromium.org/chromium-os/packages/cros-flashrom + + +coreboot +~~~~~~~~ + +Coreboot itself is not designed to actually boot an OS. Instead, a program +called Depthcharge is used. This originally came out of U-Boot and was then +heavily hacked and modified such that is is almost unrecognisable. It does +include a very small part of the U-Boot command-line interface but is not +usable as a general-purpose boot loader. + +In addition, it has a very unusual design in that it does not do device init +itself, but instead relies on coreboot. This is similar to (in U-Boot) having +a SPI driver with an empty probe() method, relying on whatever was set up +beforehand. It can be quite hard to figure out between these two code bases +what settings are actually used. When chain-loading into U-Boot we must be +careful to reinit anything that U-Boot expects. If not, some peripherals (or +the whole machine) may not work. This makes the process of chainloading more +complicated than it could be on some platforms. + +Finally, it supports only a subset of the U-Boot's FIT format. In particular +it uses a fixed address to load the FIT and does not support load/exec +addresses. This means that U-Boot must be able to boot from whatever +address Depthcharge happens to use (it is the CONFIG_KERNEL_START setting +in Depthcharge). In practice this means that the data in the kernel@1 FIT node +(see above) must start at the same address as U-Boot's CONFIG_SYS_TEXT_BASE. diff --git a/doc/chromium/chromebook_jerry.its b/doc/chromium/chromebook_jerry.its deleted file mode 100644 index 7505a20535b..00000000000 --- a/doc/chromium/chromebook_jerry.its +++ /dev/null @@ -1,42 +0,0 @@ -/dts-v1/; - -/ { - description = "U-Boot mainline"; - #address-cells = <1>; - - images { - kernel { - description = "U-Boot mainline"; - type = "kernel_noload"; - arch = "arm"; - os = "linux"; - data = /incbin/("../../b/chromebook_jerry/u-boot.bin"); - compression = "none"; - load = <0>; - entry = <0>; - hash-2 { - algo = "sha1"; - }; - }; - - fdt-1{ - description = "rk3288-veryron-jerry.dtb"; - data = /incbin/("../../b/chromebook_jerry/u-boot.dtb"); - type = "flat_dt"; - arch = "arm"; - compression = "none"; - hash-1{ - algo = "sha1"; - }; - }; - }; - - configurations { - default = "config-1"; - config-1 { - description = "Boot U-Boot"; - kernel = "kernel"; - fdt = "fdt-1"; - }; - }; -}; diff --git a/doc/chromium/devkeys/kernel.keyblock b/doc/chromium/devkeys/kernel.keyblock deleted file mode 100644 index 9740be4e600..00000000000 Binary files a/doc/chromium/devkeys/kernel.keyblock and /dev/null differ diff --git a/doc/chromium/devkeys/kernel_data_key.vbprivk b/doc/chromium/devkeys/kernel_data_key.vbprivk deleted file mode 100644 index 8d392fb294c..00000000000 Binary files a/doc/chromium/devkeys/kernel_data_key.vbprivk and /dev/null differ diff --git a/doc/chromium/files/chromebook_jerry.its b/doc/chromium/files/chromebook_jerry.its new file mode 100644 index 00000000000..7505a20535b --- /dev/null +++ b/doc/chromium/files/chromebook_jerry.its @@ -0,0 +1,42 @@ +/dts-v1/; + +/ { + description = "U-Boot mainline"; + #address-cells = <1>; + + images { + kernel { + description = "U-Boot mainline"; + type = "kernel_noload"; + arch = "arm"; + os = "linux"; + data = /incbin/("../../b/chromebook_jerry/u-boot.bin"); + compression = "none"; + load = <0>; + entry = <0>; + hash-2 { + algo = "sha1"; + }; + }; + + fdt-1{ + description = "rk3288-veryron-jerry.dtb"; + data = /incbin/("../../b/chromebook_jerry/u-boot.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + hash-1{ + algo = "sha1"; + }; + }; + }; + + configurations { + default = "config-1"; + config-1 { + description = "Boot U-Boot"; + kernel = "kernel"; + fdt = "fdt-1"; + }; + }; +}; diff --git a/doc/chromium/files/devkeys/kernel.keyblock b/doc/chromium/files/devkeys/kernel.keyblock new file mode 100644 index 00000000000..9740be4e600 Binary files /dev/null and b/doc/chromium/files/devkeys/kernel.keyblock differ diff --git a/doc/chromium/files/devkeys/kernel_data_key.vbprivk b/doc/chromium/files/devkeys/kernel_data_key.vbprivk new file mode 100644 index 00000000000..8d392fb294c Binary files /dev/null and b/doc/chromium/files/devkeys/kernel_data_key.vbprivk differ diff --git a/doc/chromium/files/nyan-big.its b/doc/chromium/files/nyan-big.its new file mode 100644 index 00000000000..bd412915e95 --- /dev/null +++ b/doc/chromium/files/nyan-big.its @@ -0,0 +1,42 @@ +/dts-v1/; + +/ { + description = "U-Boot mainline"; + #address-cells = <1>; + + images { + kernel { + description = "U-Boot mainline "; + type = "kernel_noload"; + arch = "arm"; + os = "linux"; + data = /incbin/("../.././b/nyan-big/u-boot.bin"); + compression = "none"; + load = <0>; + entry = <0>; + hash-2 { + algo = "sha1"; + }; + }; + + fdt-1{ + description = "tegra124-nyan-big.dtb"; + data = /incbin/("../.././b/nyan-big/u-boot.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + hash-1{ + algo = "sha1"; + }; + }; + }; + + configurations { + default = "config-1"; + config-1 { + description = "Boot U-Boot"; + kernel = "kernel"; + fdt = "fdt-1"; + }; + }; +}; diff --git a/doc/chromium/index.rst b/doc/chromium/index.rst new file mode 100644 index 00000000000..0722c250033 --- /dev/null +++ b/doc/chromium/index.rst @@ -0,0 +1,14 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright 2020 Google LLC + +Chromium OS-specific doc +======================== + +This provides some information about Chromium OS and U-Boot. + +.. toctree:: + :maxdepth: 2 + + overview + run_vboot + chainload diff --git a/doc/chromium/nyan-big.its b/doc/chromium/nyan-big.its deleted file mode 100644 index bd412915e95..00000000000 --- a/doc/chromium/nyan-big.its +++ /dev/null @@ -1,42 +0,0 @@ -/dts-v1/; - -/ { - description = "U-Boot mainline"; - #address-cells = <1>; - - images { - kernel { - description = "U-Boot mainline "; - type = "kernel_noload"; - arch = "arm"; - os = "linux"; - data = /incbin/("../.././b/nyan-big/u-boot.bin"); - compression = "none"; - load = <0>; - entry = <0>; - hash-2 { - algo = "sha1"; - }; - }; - - fdt-1{ - description = "tegra124-nyan-big.dtb"; - data = /incbin/("../.././b/nyan-big/u-boot.dtb"); - type = "flat_dt"; - arch = "arm"; - compression = "none"; - hash-1{ - algo = "sha1"; - }; - }; - }; - - configurations { - default = "config-1"; - config-1 { - description = "Boot U-Boot"; - kernel = "kernel"; - fdt = "fdt-1"; - }; - }; -}; diff --git a/doc/chromium/overview.rst b/doc/chromium/overview.rst new file mode 100644 index 00000000000..5498ed9c16c --- /dev/null +++ b/doc/chromium/overview.rst @@ -0,0 +1,74 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright 2020 Google LLC + +Chromium OS Support in U-Boot +============================= + +Introduction +------------ + +This describes how to use U-Boot with Chromium OS. Several options are +available: + + - Running U-Boot from the 'altfw' feature, which is available on selected + Chromebooks from 2019 onwards (initially Grunt). Press '1' from the + developer-mode screen to get into U-Boot. See here for details: + https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_mode.md + + - Running U-Boot from the disk partition. This involves signing U-Boot and + placing it on the disk, for booting as a 'kernel'. See + :doc:`chainload` for information on this. This is the only + option on non-U-Boot Chromebooks from 2013 to 2018 and is somewhat + more involved. + + - Running U-Boot with Chromium OS verified boot. This allows U-Boot to be + used instead of either or both of depthcharge (a bootloader which forked + from U-Boot in 2013) and coreboot. See :doc:`run_vboot` for more + information on this. + + - Running U-Boot from coreboot. This allows U-Boot to run on more devices + since many of them only support coreboot as the bootloader and have + no bare-metal support in U-Boot. For this, use the 'coreboot' target. + + - Running U-Boot and booting into a Chrome OS image, but without verified + boot. This can be useful for testing. + + +Talks and documents +------------------- + +Here is some material relevant to Chromium OS verified boot with U-Boot: + + - "U-Boot with Chrome OS and firmware packaging" + + - Author: Simon Glass + - Presented at Open Source Firmware Conference 2018, Erlangen + - Describes the work in progress as at the end of 2018 + - Slides at `OSFC `_ + - Video on `Youtube `_ + + - "Verified Boot in Chrome OS and how to make it work for you" + + - Author: Simon Glass + - Presented at ELCE 2013, Edinburgh + - Describes the original 2013 implementation as shipped on snow (first + `ARM Chromebook was a Samsung Chromebook `_ + with Samsung Exynos5250 `review `_), + spring (`HP Chromebook 11 `_) + and pit/pi (`Samsung Chromebook 2 `_ + with Exynos 5 Octa 5420 in 2014). + - Slides at `Google research `_ + - Video at `Youtube `_ + + - "Chrome University 2018: Chrome OS Firmware and Verified Boot 201" + + - Author: Duncan Laurie + - Describes Chrome OS firmware as of 2018 and includes a wide range of + topics. This has no U-Boot information, but does cover coreboot and also + talks about the Chrome OS EC and Security chip. This is probably the + best introduction talk. + - Video at `YouTube `_ + + - `Chromium OS U-Boot `_ + + - `Firmware porting Guide `_ diff --git a/doc/chromium/run_vboot.rst b/doc/chromium/run_vboot.rst new file mode 100644 index 00000000000..41b4f631835 --- /dev/null +++ b/doc/chromium/run_vboot.rst @@ -0,0 +1,204 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright 2020 Google LLC +.. sectionauthor:: Simon Glass + + +Running U-Boot with Chromium OS verified boot +============================================= + +To obtain:: + + git clone https://github.com/sjg20/u-boot.git + cd u-boot + git checkout cros-master + + cd .. + git clone https://chromium.googlesource.com/chromiumos/platform/vboot_reference + cd vboot_reference + git checkout 45964294 + # futility: updater: Correct output version for Snow + +To build for sandbox:: + + UB=/tmp/b/chromeos_sandbox # U-Boot build directory + cd u-boot + make O=$UB chromeos_sandbox_defconfig + make O=$UB -j20 -s VBOOT_SOURCE=/path/to/vboot_reference \ + MAKEFLAGS_VBOOT=DEBUG=1 QUIET=1 + +Replace sandbox with another supported target. + +This produces $UB/image.bin which contains the firmware binaries in a SPI +flash image. + +To run on sandbox:: + + CROS=~/cosarm + IMG=$CROS/src/build/images/coral/latest/chromiumos_image.bin + $UB/tpl/u-boot-tpl -d $UB/u-boot.dtb.out \ + -L6 -c "host bind 0 $IMG; vboot go auto" \ + -l -w -s state.dtb -r -n -m $UB/ram + + $UB/tpl/u-boot-tpl -d $UB/u-boot.dtb.out -L6 -l \ + -c "host bind 0 $IMG; vboot go auto" -w -s $UB/state.dtb -r -n -m $UB/mem + + +To run on other boards: + + - Install image.bin in the SPI flash of your device + - Boot your system + + +Sandbox +------- + +Most Chromium OS development with U-Boot is undertaken using sandbox. There is +a sandbox target available (chromeos_sandbox) which allows running U-Boot on +a Linux machine completion with emulations of the display, TPM, disk, etc. + +Running sandbox starts TPL, which contains the first phase of vboot, providing +a device tree and binding a Chromium OS disk image for use to find kernels +(any Chromium OS image will do). It also saves driver state between U-Boot +phases into state.dtb and will automatically ensure that memory is shared +between all phases. TPL will jump to SPL and then on to U-Boot proper. + +It is possible to run with debugging on, e.g.:: + + gdb --args $UB/tpl/u-boot-tpl -d .... + +Breakpoints can be set in any U-Boot phase. Overall this is a good debugging +environment for new verified-boot features. + + +Samus +----- + +Basic support is available for samus, using the chromeos_samus target. If you +have an em100, use:: + + sudo em100 -s -c W25Q128FW -d $UB/image.bin -t -r + +to write the image and then boot samus (Power-Refresh). + + +Boot flow +--------- + +Verified boot starts in TPL, which selects the A or B SPL, which in turn selects +the A or B U-Boot. Then this jumps to the selected kernel. If anything goes +wrong, the device reboots and the recovery SPL and U-Boot are used instead. + +More details are available here: + + https://www.chromium.org/chromium-os/chromiumos-design-docs/firmware-boot-and-recovery + + +New uclasses +------------ + +Several uclasses are provided in cros/: + +UCLASS_CROS_AUX_FW + Chrome OS auxiliary firmware + +UCLASS_CROS_FWSTORE + Chrome OS firmware storage + +UCLASS_CROS_NVDATA + Chrome OS non-volatile data device + +UCLASS_CROS_VBOOT_EC + Chrome OS vboot EC operations + +UCLASS_CROS_VBOOT_FLAG + Chrome OS verified boot flag + +The existing UCLASS_CROS_EC is also used. + + +Commands +-------- + +A new 'vboot' command is provided to run particular vboot stages. The most +useful command is 'vboot go auto', which continues where the last stage left +off. + +Note that TPL and SPL do not supports commands as yet, so the vboot code is +called directly from the SPL boot devices (BOOT_DEVICE_CROS_VBOOT). See +cros_load_image_tpl() and cros_load_image_spl() which both call +vboot_run_auto(). + + +Config options +-------------- + +The main option is CONFIG_CHROMEOS, which enables a wide array of other options +so that the required features are present. + + +Device-tree config +------------------ + +Various options are available which control the operation of verified boot. +See cros/dts/bindings/config.txt for details. Most config is handled at run- +time, although build-time config (with Kconfig) could also be added fairly +easily. + + +Porting to other hardware +------------------------- + +A basic port to samus (Chromebook Pixel 2015) is in a basic working state, +using the chromeos_samus target. Patches will likely be forthcoming in early +2019. Ports to an ARM board and coreboot (for x86 Chromebooks) are in the +dreaming state. + + +Tests +----- + +Chromium OS firmware has a very limited set of tests. The tests that originally +existed in U-Boot were not brought over to coreboot or depthcharge. + +The U-Boot tests ('make check') do operate, but at present there are no +Chromium OS tests available. These will hopefully come together over time. Of +course the above sandbox feature provides a sort of functional test and can +detect problems that affect the flow or particular vboot features. + + +U-Boot without Chromium OS verified boot +---------------------------------------- + +The following script can be used to boot a Chrome OS image on coral:: + + # Read the image header and obtain the address of the kernel + # The offset 4f0 is defined by verified boot and may change for other + # Chromebooks + read mmc 2:2 100000 0 80; setexpr loader *001004f0; + + # Get the kernel size and calculate the number of blocks (0x200 bytes each) + setexpr size *00100518; setexpr blocks $size / 200; + + # Read the full kernel and calculate the address of the setup block + read mmc 2:2 100000 80 $blocks; setexpr setup $loader - 1000; + + # Locate the command line + setexpr cmdline $loader - 2000; + + # Start the zboot process with the loaded kernel, setup block and cmdline + zboot start 100000 0 0 0 $setup $cmdline; + + # Load the kernel, fix up the 'setup' block, dump information + zboot load; zboot setup; zboot dump + + # Boot into Chrome OS + zboot go + + +TO DO +----- + +Get the full ACPI tables working with Coral + + +7 October 2018 diff --git a/doc/index.rst b/doc/index.rst index f7aada966b0..02de1d46842 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -87,6 +87,14 @@ Android-specific features available in U-Boot. android/index +Chromium OS-specific doc +------------------------ + +.. toctree:: + :maxdepth: 2 + + chromium/index + Indices and tables ================== -- cgit v1.3.1 From 80a4570c99233cf9c7b30bf77b9c9ab47b41fb15 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 21 Mar 2021 16:50:07 +1300 Subject: x86: coral: Show memory config and SKU ID on startup Provide the model information through sysinfo so that it shows up on boot. For memconfig 4 pins are provided, for 16 combinations. For SKU ID there are two options: - two pins provided in a ternary arrangement, for 9 combinations. - reading from the EC Add a binding doc and drop the unused #defines as well. Example: U-Boot 2021.01-rc5 CPU: Intel(R) Celeron(R) CPU N3450 @ 1.10GHz DRAM: 3.9 GiB MMC: sdmmc@1b,0: 1, emmc@1c,0: 2 Video: 1024x768x32 @ b0000000 Model: Google Coral (memconfig 5, SKU 3) This depends on the GPIO series: http://patchwork.ozlabs.org/project/uboot/list/?series=228126 Signed-off-by: Simon Glass Acked-by: Bin Meng --- arch/x86/dts/chromebook_coral.dts | 11 ++ board/google/chromebook_coral/coral.c | 139 ++++++++++++++++++++-- board/google/chromebook_coral/variant_gpio.h | 6 - doc/device-tree-bindings/sysinfo/google,coral.txt | 37 ++++++ 4 files changed, 179 insertions(+), 14 deletions(-) create mode 100644 doc/device-tree-bindings/sysinfo/google,coral.txt (limited to 'doc') diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 527c0adbd57..c8cb4e21c6d 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -56,6 +56,17 @@ recovery-gpios = <&gpio_nw (-1) GPIO_ACTIVE_LOW>; write-protect-gpios = <&gpio_nw GPIO_75 GPIO_ACTIVE_HIGH>; phase-enforce-gpios = <&gpio_n GPIO_10 GPIO_ACTIVE_HIGH>; + memconfig-gpios = <&gpio_nw GPIO_101 GPIO_ACTIVE_HIGH + &gpio_nw GPIO_102 GPIO_ACTIVE_HIGH + &gpio_n GPIO_38 GPIO_ACTIVE_HIGH + &gpio_n GPIO_45 GPIO_ACTIVE_HIGH>; + + /* + * This is used for reef only: + * + * skuconfig-gpios = <&gpio_nw GPIO_16 GPIO_ACTIVE_HIGH + * &gpio_nw GPIO_17 GPIO_ACTIVE_HIGH>; + */ smbios { /* Type 1 table */ system { diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c index b255bf6187e..3f9235c903b 100644 --- a/board/google/chromebook_coral/coral.c +++ b/board/google/chromebook_coral/coral.c @@ -3,9 +3,12 @@ * Copyright 2019 Google LLC */ +#define LOG_CATEGORY UCLASS_SYSINFO + #include #include #include +#include #include #include #include @@ -15,6 +18,7 @@ #include #include #include +#include #include "variant_gpio.h" struct cros_gpio_info { @@ -29,10 +33,125 @@ int arch_misc_init(void) return 0; } -/* This function is needed if CONFIG_CMDLINE is not enabled */ -int board_run_command(const char *cmdline) +static int get_memconfig(struct udevice *dev) { - printf("No command line\n"); + struct gpio_desc gpios[4]; + int cfg; + int ret; + + ret = gpio_request_list_by_name(dev, "memconfig-gpios", gpios, + ARRAY_SIZE(gpios), + GPIOD_IS_IN | GPIOD_PULL_UP); + if (ret < 0) { + log_debug("Cannot get GPIO list '%s' (%d)\n", dev->name, ret); + return ret; + } + + /* Give the lines time to settle */ + udelay(10); + + ret = dm_gpio_get_values_as_int(gpios, ARRAY_SIZE(gpios)); + if (ret < 0) + return log_msg_ret("get", ret); + cfg = ret; + + ret = gpio_free_list(dev, gpios, ARRAY_SIZE(gpios)); + if (ret) + return log_msg_ret("free", ret); + + return cfg; +} + +/** + * get_skuconfig() - Get the SKU number either from pins or the EC + * + * Two options are supported: + * skuconfig-gpios - two pins in the device tree (tried first) + * EC - reading from the EC (backup) + * + * @dev: sysinfo device to use + * @return SKU ID, or -ve error if not found + */ +static int get_skuconfig(struct udevice *dev) +{ + struct gpio_desc gpios[2]; + int cfg; + int ret; + + ret = gpio_request_list_by_name(dev, "skuconfig-gpios", gpios, + ARRAY_SIZE(gpios), + GPIOD_IS_IN); + if (ret != ARRAY_SIZE(gpios)) { + struct udevice *cros_ec; + + log_debug("Cannot get GPIO list '%s' (%d)\n", dev->name, ret); + + /* Try the EC */ + ret = uclass_first_device_err(UCLASS_CROS_EC, &cros_ec); + if (ret < 0) { + log_err("Cannot find EC for SKU details\n"); + return log_msg_ret("sku", ret); + } + ret = cros_ec_get_sku_id(cros_ec); + if (ret < 0) { + log_err("Cannot read SKU details\n"); + return log_msg_ret("sku", ret); + } + + return ret; + } + + ret = dm_gpio_get_values_as_int_base3(gpios, ARRAY_SIZE(gpios)); + if (ret < 0) + return log_msg_ret("get", ret); + cfg = ret; + + ret = gpio_free_list(dev, gpios, ARRAY_SIZE(gpios)); + if (ret) + return log_msg_ret("free", ret); + + return cfg; +} + +static int coral_get_str(struct udevice *dev, int id, size_t size, char *val) +{ + int ret; + + if (IS_ENABLED(CONFIG_SPL_BUILD)) + return -ENOSYS; + + switch (id) { + case SYSINFO_ID_SMBIOS_SYSTEM_VERSION: + case SYSINFO_ID_SMBIOS_BASEBOARD_VERSION: { + ret = get_skuconfig(dev); + + if (ret < 0) + return ret; + if (size < 15) + return -ENOSPC; + sprintf(val, "rev%d", ret); + break; + } + case SYSINFO_ID_BOARD_MODEL: { + int mem_config, sku_config; + const char *model; + + ret = get_memconfig(dev); + if (ret < 0) + log_warning("Unable to read memconfig (err=%d)\n", ret); + mem_config = ret; + ret = get_skuconfig(dev); + if (ret < 0) + log_warning("Unable to read skuconfig (err=%d)\n", ret); + sku_config = ret; + model = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + snprintf(val, size, "%s (memconfig %d, SKU %d)", model, + mem_config, sku_config); + break; + } + default: + return -ENOENT; + } return 0; } @@ -45,12 +164,15 @@ int chromeos_get_gpio(const struct udevice *dev, const char *prop, int ret; ret = gpio_request_by_name((struct udevice *)dev, prop, 0, &desc, 0); - if (ret == -ENOTBLK) + if (ret == -ENOTBLK) { info->gpio_num = CROS_GPIO_VIRTUAL; - else if (ret) + log_debug("GPIO '%s' is virtual\n", prop); + } else if (ret) { return log_msg_ret("gpio", ret); - else + } else { info->gpio_num = desc.offset; + dm_gpio_free((struct udevice *)dev, &desc); + } info->linux_name = dev_read_string(desc.dev, "linux-name"); if (!info->linux_name) return log_msg_ret("linux-name", -ENOENT); @@ -83,11 +205,11 @@ static int chromeos_acpi_gpio_generate(const struct udevice *dev, ret = chromeos_get_gpio(dev, "write-protect-gpios", CROS_GPIO_WP, &info[1]); if (ret) - return log_msg_ret("rec", ret); + return log_msg_ret("wp", ret); ret = chromeos_get_gpio(dev, "phase-enforce-gpios", CROS_GPIO_PE, &info[2]); if (ret) - return log_msg_ret("rec", ret); + return log_msg_ret("phase", ret); acpigen_write_scope(ctx, "\\"); acpigen_write_name(ctx, "OIPG"); acpigen_write_package(ctx, count); @@ -147,6 +269,7 @@ struct acpi_ops coral_acpi_ops = { }; struct sysinfo_ops coral_sysinfo_ops = { + .get_str = coral_get_str, }; #if !CONFIG_IS_ENABLED(OF_PLATDATA) diff --git a/board/google/chromebook_coral/variant_gpio.h b/board/google/chromebook_coral/variant_gpio.h index f516d88be5c..403e2419a71 100644 --- a/board/google/chromebook_coral/variant_gpio.h +++ b/board/google/chromebook_coral/variant_gpio.h @@ -34,12 +34,6 @@ /* Determine if board is in final shipping mode. */ #define GPIO_SHIP_MODE GPIO_10 -/* Memory SKU GPIOs. */ -#define MEM_CONFIG3 GPIO_45 -#define MEM_CONFIG2 GPIO_38 -#define MEM_CONFIG1 GPIO_102 -#define MEM_CONFIG0 GPIO_101 - /* DMIC_CONFIG_PIN: High for 1-DMIC and low for 4-DMIC's */ #define DMIC_CONFIG_PIN GPIO_17 diff --git a/doc/device-tree-bindings/sysinfo/google,coral.txt b/doc/device-tree-bindings/sysinfo/google,coral.txt new file mode 100644 index 00000000000..d8a1a79687e --- /dev/null +++ b/doc/device-tree-bindings/sysinfo/google,coral.txt @@ -0,0 +1,37 @@ +Google Coral sysinfo information +================================ + +This binding allows information about the board to be described. It includes +the SMBIOS binding as well. + +Required properties: + + - compatible: "google,coral" + - recovery-gpios: GPIO to use for recovery button (-1 if none) + - wite-protect-gpios: GPIO to use for write-protect screw + - phase-enforce-gpios: GPIO to indicate the board is in final ship mode + - memconfig-gpios: 4 GPIOs to use to read memory config (as base2 int) + +Optional properties: + - skuconfig-gpios: 2 GPIOs to use to read SKU ID. If not present, the + Chromium OS EC SKU_ID is used instead + +Example: + +board: board { + compatible = "google,coral"; + recovery-gpios = <&gpio_nw (-1) GPIO_ACTIVE_LOW>; + write-protect-gpios = <&gpio_nw GPIO_75 GPIO_ACTIVE_HIGH>; + phase-enforce-gpios = <&gpio_n GPIO_10 GPIO_ACTIVE_HIGH>; + memconfig-gpios = <&gpio_nw GPIO_101 GPIO_ACTIVE_HIGH + &gpio_nw GPIO_102 GPIO_ACTIVE_HIGH + &gpio_n GPIO_38 GPIO_ACTIVE_HIGH + &gpio_n GPIO_45 GPIO_ACTIVE_HIGH>; + + /* + * This is used for reef only: + * + * skuconfig-gpios = <&gpio_nw GPIO_16 GPIO_ACTIVE_HIGH + * &gpio_nw GPIO_17 GPIO_ACTIVE_HIGH>; + */ + }; -- cgit v1.3.1