From 82450b9a62f381ed3ef40ef3753dd4bda61db90e Mon Sep 17 00:00:00 2001 From: Miao Yan Date: Thu, 28 Nov 2013 17:51:40 +0800 Subject: README.vxworks: add a document describing the new VxWorks boot interface Signed-off-by: Miao Yan --- doc/README.vxworks | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 doc/README.vxworks (limited to 'doc') diff --git a/doc/README.vxworks b/doc/README.vxworks new file mode 100644 index 00000000000..4cb302e7f4f --- /dev/null +++ b/doc/README.vxworks @@ -0,0 +1,19 @@ +From VxWorks 6.9+ (not include 6.9), VxWorks starts adopting device tree as its hardware +decription mechansim (for PowerPC and ARM), thus requiring boot interface changes. +This section will describe the new interface. + +For PowerPC, the calling convention of the new VxWorks entry point conforms to the ePAPR standard, +which is shown below (see ePAPR for more details): + + void (*kernel_entry)(fdt_addr, + 0, 0, EPAPR_MAGIC, boot_IMA, 0, 0) + +For ARM, the calling convention is show below: + + void (*kernel_entry)(void *fdt_addr) + +When booting new VxWorks kernel (uImage format), the parameters passed to bootm is like below: + + bootm - + +The do_bootvx command still works as it was for older VxWorks kernels. -- cgit v1.2.3 From 320cf350801f30875fe5749eee74aed242573031 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 18 Dec 2013 16:03:44 +0900 Subject: sh: add support for sh7753evb board The SH7753 EVB board has SH7753, 512MB DDR3-SDRAM, SPI ROM, Gigabit Ethernet, and eMMC. This patch support the following functions: - 512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMC Signed-off-by: Yoshihiro Shimoda Signed-off-by: Nobuhiro Iwamatsu --- doc/README.sh7753evb | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 doc/README.sh7753evb (limited to 'doc') diff --git a/doc/README.sh7753evb b/doc/README.sh7753evb new file mode 100644 index 00000000000..5fe178c53f0 --- /dev/null +++ b/doc/README.sh7753evb @@ -0,0 +1,67 @@ +======================================== +Renesas SH7753 EVB board +======================================== + +This board specification: +========================= + +The SH7753 EVB (board config name:sh7753evb) has the following device: + + - SH7753 (SH-4A) + - DDR3-SDRAM 512MB + - SPI ROM 8MB + - Gigabit Ethernet controllers + - eMMC 4GB + + +Configuration for This board: +============================= + +You can select the configuration as follows: + + - make sh7753evb_config + + +This board specific command: +============================ + +This board has the following its specific command: + + - write_mac + + +1. write_mac + +You can write MAC address to SPI ROM. + + Usage 1) Write MAC address + + write_mac [GETHERC ch0] [GETHERC ch1] + + For example) + => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f + *) We have to input the command as a single line + (without carriage return) + *) We have to reset after input the command. + + Usage 2) Show current data + + write_mac + + For example) + => write_mac + GETHERC ch0 = 74:90:50:00:33:9e + GETHERC ch1 = 74:90:50:00:33:9f + + +Update SPI ROM: +============================ + +1. Copy u-boot image to RAM area. +2. Probe SPI device. + => sf probe 0 + SF: Detected MX25L6405D with page size 64KiB, total 8 MiB +3. Erase SPI ROM. + => sf erase 0 80000 +4. Write u-boot image to SPI ROM. + => sf write 0x48000000 0 80000 -- cgit v1.2.3 From 16f47c9c510a61ee91d6b9d02dd723522beff80f Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Wed, 18 Dec 2013 15:31:55 +0900 Subject: spi: Add support SH Quad SPI driver This patch adds a driver for Renesas SoC's Quad SPI bus. This supports with 8 bits per transfer to use with SPI flash. Signed-off-by: Kouei Abe Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Jagannadha Sutradharudu Teki --- doc/SPI/README.sh_qspi_test | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 doc/SPI/README.sh_qspi_test (limited to 'doc') diff --git a/doc/SPI/README.sh_qspi_test b/doc/SPI/README.sh_qspi_test new file mode 100644 index 00000000000..8a33fec32fd --- /dev/null +++ b/doc/SPI/README.sh_qspi_test @@ -0,0 +1,38 @@ +------------------------------------------------- + Simple steps used to test the SH-QSPI at U-Boot +------------------------------------------------- + +#0, Currently, SH-QSPI is used by lager board (Renesas ARM SoC R8A7790) + and koelsch board (Renesas ARM SoC R8A7791). These boot from SPI ROM + basically. Thus, U-Boot start, SH-QSPI will is operating normally. + +#1, build U-Boot and load u-boot.bin + + => tftpboot 40000000 u-boot.bin + sh_eth Waiting for PHY auto negotiation to complete.. done + sh_eth: 100Base/Half + Using sh_eth device + TFTP from server 192.168.169.1; our IP address is 192.168.169.79 + Filename 'u-boot.bin'. + Load address: 0x40000000 + Loading: ############ + 2.5 MiB/s + done + Bytes transferred = 175364 (2ad04 hex) + +#2, Commands to erase/write u-boot to flash device + + Note: This method is description of the lager board. If you want to use the + other boards, please change the value according to each environment. + + => sf probe 0 + SF: Detected S25FL512S_256K with page size 512 Bytes, erase size 64 KiB, total 64 MiB + => sf erase 80000 40000 + SF: 262144 bytes @ 0x80000 Erased: OK + => sf write 40000000 80000 175364 + SF: 1528676 bytes @ 0x80000 Written: OK + => + +#3, Push reset button. + + If you're written correctly and driver works properly, U-Boot starts. -- cgit v1.2.3 From c5c1af21764d9423b45c1d03e835c4547a8bc5cb Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Mon, 30 Dec 2013 18:26:14 -0600 Subject: socfpga/dwmmc: Adding DesignWare MMC driver support for SOCFPGA To add the DesignWare MMC driver support for Altera SOCFPGA. It required information such as clocks and bus width from platform specific files (SOCFPGA handoff files) Signed-off-by: Chin Liang See Cc: Rajeshwari Shinde Cc: Jaehoon Chung Cc: Pantelis Antoniou Cc: Wolfgang Denk Acked-by: Pantelis Antoniou --- doc/README.socfpga | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 doc/README.socfpga (limited to 'doc') diff --git a/doc/README.socfpga b/doc/README.socfpga new file mode 100644 index 00000000000..cfcbbfe3798 --- /dev/null +++ b/doc/README.socfpga @@ -0,0 +1,53 @@ + +-------------------------------------------- +SOCFPGA Documentation for U-Boot and SPL +-------------------------------------------- + +This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore +based SOCFPGA. To know more about the hardware itself, please refer to +www.altera.com. + + +-------------------------------------------- +socfpga_dw_mmc +-------------------------------------------- +Here are macro and detailed configuration required to enable DesignWare SDMMC +controller support within SOCFPGA + +#define CONFIG_MMC +-> To enable the SD MMC framework support + +#define CONFIG_SDMMC_BASE (SOCFPGA_SDMMC_ADDRESS) +-> The base address of CSR register for DesignWare SDMMC controller + +#define CONFIG_GENERIC_MMC +-> Enable the generic MMC driver + +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 +-> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM + +#define CONFIG_DWMMC +-> Enable the common DesignWare SDMMC controller framework + +#define CONFIG_SOCFPGA_DWMMC +-> Enable the SOCFPGA specific driver for DesignWare SDMMC controller + +#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 +-> The FIFO depth for SOCFPGA DesignWare SDMMC controller + +#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 +-> Phase-shifted clock of sdmmc_clk for controller to drive command and data to +the card to meet hold time requirements. SD clock is running at 50MHz and +drvsel is set to shift 135 degrees (3 * 45 degrees). With that, the hold time +is 135 / 360 * 20ns = 7.5ns. + +#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 +-> Phase-shifted clock of sdmmc_clk used to sample the command and data from +the card + +#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH 4 +-> Bus width of data line which either 1, 4 or 8 and based on board routing. + +#define CONFIG_SOCFPGA_DWMMC_BUS_HZ 50000000 +-> The clock rate to controller. Do note the controller have a wrapper which +divide the clock from PLL by 4. -- cgit v1.2.3 From 0ae7653128c80a4f2920cbe9b124792c2fd9d9e0 Mon Sep 17 00:00:00 2001 From: David Feng Date: Sat, 14 Dec 2013 11:47:35 +0800 Subject: arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood Signed-off-by: David Feng --- doc/README.arm64 | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 doc/README.arm64 (limited to 'doc') diff --git a/doc/README.arm64 b/doc/README.arm64 new file mode 100644 index 00000000000..75586dbaa70 --- /dev/null +++ b/doc/README.arm64 @@ -0,0 +1,46 @@ +U-boot for arm64 + +Summary +======= +No hardware platform of arm64 is available now. The u-boot is +simulated on Foundation Model and Fast Model for ARMv8. + +Notes +===== + +1. Currenly, u-boot run at the highest exception level processor + supported and jump to EL2 or optionally EL1 before enter OS. + +2. U-boot for arm64 is compiled with AArch64-gcc. AArch64-gcc + use rela relocation format, a tool(tools/relocate-rela) by Scott Wood + is used to encode the initial addend of rela to u-boot.bin. After running, + the u-boot will be relocated to destination again. + +3. Fdt should be placed at a 2-megabyte boundary and within the first 512 + megabytes from the start of the kernel image. So, fdt_high should be + defined specially. + Please reference linux/Documentation/arm64/booting.txt for detail. + +4. Spin-table is used to wake up secondary processors. One location + (or per processor location) is defined to hold the kernel entry point + for secondary processors. It must be ensured that the location is + accessible and zero immediately after secondary processor + enter slave_cpu branch execution in start.S. The location address + is encoded in cpu node of DTS. Linux kernel store the entry point + of secondary processors to it and send event to wakeup secondary + processors. + Please reference linux/Documentation/arm64/booting.txt for detail. + +5. Generic board is supported. + +6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and + aarch32 specific codes. + +Contributor +=========== + Tom Rini + Scott Wood + York Sun + Simon Glass + Sharma Bhupesh + Rob Herring -- cgit v1.2.3 From ba45a072bf9a186d99aae35af56699eeb7704b1c Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:11 +0530 Subject: doc: zynq: Add information on zynq u-boot Information on zynq u-boot about - zynq boards - mainline status - TODO Signed-off-by: Jagannadha Sutradharudu Teki --- doc/README.zynq | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 doc/README.zynq (limited to 'doc') diff --git a/doc/README.zynq b/doc/README.zynq new file mode 100644 index 00000000000..56a74b4f1f0 --- /dev/null +++ b/doc/README.zynq @@ -0,0 +1,60 @@ +# +# Xilinx ZYNQ U-Boot +# +# (C) Copyright 2013 Xilinx, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +1. About this + +This document describes the information about Xilinx Zynq U-Boot - +like supported boards, ML status and TODO list. + +2. Zynq boards + +Xilinx Zynq-7000 All Programmable SoCs enable extensive system level +differentiation, integration, and flexibility through hardware, software, +and I/O programmability. + +* zc70x + - zc702 (single qspi, gem0, mmc) [1] + - zc706 (dual parallel qspi, gem0, mmc) [2] +* zed (single qspi, gem0, mmc) [3] +* microzed (single qspi, gem0, mmc) [4] +* zc770 + - zc770-xm010 (single qspi, gem0, mmc) + - zc770-xm011 (8 or 16 bit nand) + - zc770-xm012 (nor) + - zc770-xm013 (dual parallel qspi, gem1) + +3. Mainline status + +- Added basic board configurations support. +- Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq +- Added zynq boards named - zynq, zynq_dcc +- Added zynq drivers: + serial - drivers/serial/serial_zynq.c + net - drivers/net/zynq_gem.c + mmc - drivers/mmc/zynq_sdhci.c + mmc - drivers/mmc/zynq_sdhci.c + spi- drivers/spi/zynq_spi.c + i2c - drivers/i2c/zynq_i2c.c + +4. TODO + +- Add zynq boards support - zc70x, zed, microzed, zc770 +- Add zynq qspi controller driver +- Add zynq nand controller driver +- d-cache support for zynq_gem.c +- FDT support for zynq boards +- Need proper cleanups on board configurations + +[1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm +[2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm +[3] http://zedboard.org/product/zedboard +[4] http://zedboard.org/product/microzed + +-- +Jagannadha Sutradharudu Teki +Sun Dec 15 14:52:41 IST 2013 -- cgit v1.2.3 From b3de92495f23db58a2643fb9328edacbf9a17f1c Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:21 +0530 Subject: zynq: Add support to find bootmode Added support to find the bootmodes by reading slcr bootmode register. this can be helpful to autoboot the configurations w.r.t a specified bootmode. Added this functionality on board_late_init as it's not needed for normal initializtion part. Signed-off-by: Jagannadha Sutradharudu Teki --- doc/README.zynq | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) (limited to 'doc') diff --git a/doc/README.zynq b/doc/README.zynq index 56a74b4f1f0..ea1c8c14124 100644 --- a/doc/README.zynq +++ b/doc/README.zynq @@ -28,7 +28,27 @@ and I/O programmability. - zc770-xm012 (nor) - zc770-xm013 (dual parallel qspi, gem1) -3. Mainline status +3. Bootmode + +Zynq has a facility to read the bootmode from the slcr bootmode register +once user is setting through jumpers on the board - see page no:1546 on [5] + +All possible bootmode values are defined in Table 6-2:Boot_Mode MIO Pins +on [5]. + +board_late_init() will read the bootmode values using slcr bootmode register +at runtime and assign the modeboot variable to specific bootmode string which +is intern used in autoboot. + +SLCR bootmode register Bit[3:0] values +#define ZYNQ_BM_NOR 0x02 +#define ZYNQ_BM_SD 0x05 +#define ZYNQ_BM_JTAG 0x0 + +"modeboot" variable can assign any of "norboot", "sdboot" or "jtagboot" +bootmode strings at runtime. + +4. Mainline status - Added basic board configurations support. - Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq @@ -41,7 +61,7 @@ and I/O programmability. spi- drivers/spi/zynq_spi.c i2c - drivers/i2c/zynq_i2c.c -4. TODO +5. TODO - Add zynq boards support - zc70x, zed, microzed, zc770 - Add zynq qspi controller driver @@ -54,6 +74,7 @@ and I/O programmability. [2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm [3] http://zedboard.org/product/zedboard [4] http://zedboard.org/product/microzed +[5] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf -- Jagannadha Sutradharudu Teki -- cgit v1.2.3 From 10a147bc665367111920be657409a5d56d3c0590 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:31 +0530 Subject: doc: Update the zynq u-boot status Updated doc/README.zynq to current status Signed-off-by: Jagannadha Sutradharudu Teki --- doc/README.zynq | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) (limited to 'doc') diff --git a/doc/README.zynq b/doc/README.zynq index ea1c8c14124..043c9701409 100644 --- a/doc/README.zynq +++ b/doc/README.zynq @@ -28,7 +28,19 @@ and I/O programmability. - zc770-xm012 (nor) - zc770-xm013 (dual parallel qspi, gem1) -3. Bootmode +3. Building + + # Configure for zc70x board + $ make zynq_zc70x_config + Configuring for zynq_zc70x board... + + # Building default dts for zc702 board + $ make + + # Building specified dts for zc706 board + $ make DEVICE_TREE=zynq-zc706 + +4. Bootmode Zynq has a facility to read the bootmode from the slcr bootmode register once user is setting through jumpers on the board - see page no:1546 on [5] @@ -48,11 +60,11 @@ SLCR bootmode register Bit[3:0] values "modeboot" variable can assign any of "norboot", "sdboot" or "jtagboot" bootmode strings at runtime. -4. Mainline status +5. Mainline status - Added basic board configurations support. - Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq -- Added zynq boards named - zynq, zynq_dcc +- Added zynq boards named - zc70x, zed, microzed, zc770_xm010, zc770_xm012, zc770_xm013 - Added zynq drivers: serial - drivers/serial/serial_zynq.c net - drivers/net/zynq_gem.c @@ -60,15 +72,16 @@ bootmode strings at runtime. mmc - drivers/mmc/zynq_sdhci.c spi- drivers/spi/zynq_spi.c i2c - drivers/i2c/zynq_i2c.c +- Done proper cleanups on board configurations +- Added basic FDT support for zynq boards +- d-cache support for zynq_gem.c -5. TODO +6. TODO -- Add zynq boards support - zc70x, zed, microzed, zc770 +- Add zynq boards support - zc770_xm011 - Add zynq qspi controller driver - Add zynq nand controller driver -- d-cache support for zynq_gem.c -- FDT support for zynq boards -- Need proper cleanups on board configurations +- Add FDT support on individual drivers [1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm [2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm -- cgit v1.2.3 From af5b9b1f789d600cf0d996f1a5e80eb8b38f4264 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Mon, 13 Jan 2014 21:06:16 +0100 Subject: mini2440: remove board support Signed-off-by: Albert ARIBAUD Acked-by: Minkyu Kang --- doc/README.mini2440 | 28 ---------------------------- doc/README.scrapyard | 5 +++-- 2 files changed, 3 insertions(+), 30 deletions(-) delete mode 100644 doc/README.mini2440 (limited to 'doc') diff --git a/doc/README.mini2440 b/doc/README.mini2440 deleted file mode 100644 index 311ca52862a..00000000000 --- a/doc/README.mini2440 +++ /dev/null @@ -1,28 +0,0 @@ -U-Boot for FriendlyARM Mini2440 (s3c2440) - -This file contains information for the port of U-Boot to FriendlyARM -mini2440 - -All information about the board can be found on : -http://www.friendlyarm.net/products/mini2440 - -To build u-boot : ./MAKEALL mini2440 - -Overview : --------- -FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440 -ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9 -systems. It's a low cost board. - -Boot Methods : ------------- -Mini2440 can boot from NOR or NAND. - -Build : ------ -./MAKEALL mini2440 - -or - -make mini2440_config -make diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 604de0c8a78..be3e97eebde 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,8 +11,9 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -omap730p2 arm arm926ejs - 2013-11-11 -pn62 powerpc mpc824x - 2013-11-11 Wolfgang Grandegger +mini2440 arm arm920t - 2014-01-13 Gabriel Huau +omap730p2 arm arm926ejs 79c5c08d 2013-11-11 +pn62 powerpc mpc824x 649acfe1 2013-11-11 Wolfgang Grandegger pdnb3 arm ixp 304db0b 2013-09-24 Stefan Roese scpu arm ixp 304db0b 2013-09-24 Stefan Roese omap1510inn arm arm925t 0610a16 2013-09-23 Kshitij Gupta -- cgit v1.2.3 From e570aca9474bb707cd2cab0c5c9b8aba957ae51e Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Mon, 13 Jan 2014 21:06:17 +0100 Subject: mx1ads: remove board support Signed-off-by: Albert ARIBAUD Acked-by: Stefano Babic --- doc/README.scrapyard | 1 + 1 file changed, 1 insertion(+) (limited to 'doc') diff --git a/doc/README.scrapyard b/doc/README.scrapyard index be3e97eebde..2aed8559939 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +mx1ads arm arm920t - 2014-01-13 mini2440 arm arm920t - 2014-01-13 Gabriel Huau omap730p2 arm arm926ejs 79c5c08d 2013-11-11 pn62 powerpc mpc824x 649acfe1 2013-11-11 Wolfgang Grandegger -- cgit v1.2.3