From 7ae22d72781de76b3c23b018a3fccc172e9875de Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 12 Feb 2020 19:37:38 +0100 Subject: arm: stm32mp: bsec: add permanent lock support in bsec driver Add BSEC lock access (read / write) at 0xC0000000 offset of misc driver. The write access only available for Trusted boot mode, based on new SMC STM32_SMC_WRLOCK_OTP. With the fuse command, the permanent lock status is accessed with 0x10000000 offset (0xC0000000 - 0x8000000 for OTP sense/program divided by u32 size), for example: Read lock status of fuse 57 (0x39) STM32MP> fuse sense 0 0x10000039 1 Sensing bank 0: Word 0x10000039: 00000000 Set permanent lock of fuse 57 (0x39) STM32MP> fuse prog 0 0x10000039 1 Sensing bank 0: Word 0x10000039: 00000000 WARNING: the OTP lock is updated only after reboot WARING: Programming lock or fuses is an irreversible operation! This may brick your system. Signed-off-by: Patrick Delaunay Acked-by: Patrice Chotard --- doc/board/st/stm32mp1.rst | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) (limited to 'doc') diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst index 1640bf910ec..ee42af6579d 100644 --- a/doc/board/st/stm32mp1.rst +++ b/doc/board/st/stm32mp1.rst @@ -416,20 +416,26 @@ For STMicroelectonics board, it is retrieved in STM32MP15x OTP : - OTP_58[15:0] = MAC_ADDR[47:32] To program a MAC address on virgin OTP words above, you can use the fuse command -on bank 0 to access to internal OTP: +on bank 0 to access to internal OTP and lock them: Prerequisite: check if a MAC address isn't yet programmed in OTP -1) check OTP: their value must be equal to 0 +1) check OTP: their value must be equal to 0:: - STM32MP> fuse sense 0 57 2 - Sensing bank 0: - Word 0x00000039: 00000000 00000000 + STM32MP> fuse sense 0 57 2 + Sensing bank 0: + Word 0x00000039: 00000000 00000000 + +2) check environment variable:: + + STM32MP> env print ethaddr + ## Error: "ethaddr" not defined -2) check environment variable +3) check lock status of fuse 57 & 58 (at 0x39, 0=unlocked, 1=locked):: - STM32MP> env print ethaddr - ## Error: "ethaddr" not defined + STM32MP> fuse sense 0 0x10000039 2 + Sensing bank 0: + Word 0x10000039: 00000000 00000000 Example to set mac address "12:34:56:78:9a:bc" @@ -443,11 +449,19 @@ Example to set mac address "12:34:56:78:9a:bc" Sensing bank 0: Word 0x00000039: 78563412 0000bc9a -3) next REBOOT, in the trace:: +3) Lock OTP:: + + STM32MP> fuse prog 0 0x10000039 1 1 + + STM32MP> fuse sense 0 0x10000039 2 + Sensing bank 0: + Word 0x10000039: 00000001 00000001 + +4) next REBOOT, in the trace:: ### Setting environment from OTP MAC address = "12:34:56:78:9a:bc" -4) check env update:: +5) check env update:: STM32MP> env print ethaddr ethaddr=12:34:56:78:9a:bc -- cgit v1.3.1 From 050fed8a974790f553b580f8e2cdb26181f875c1 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 26 Feb 2020 11:26:43 +0100 Subject: stm32mp1: add 800 MHz profile support The STM32MP1 series is available in 3 different lines which are pin-to-pin compatible: - STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD - STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD - STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz Each line comes with a security option (cryptography & secure boot) & a Cortex-A frequency option : - A : Cortex-A7 @ 650 MHz - C : Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz - D : Cortex-A7 @ 800 MHz - F : Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz This patch adds the support of STM32MP15xD and STM32MP15xF in U-Boot. Signed-off-by: Patrick Delaunay Acked-by: Patrice Chotard --- arch/arm/mach-stm32mp/cpu.c | 18 ++++++++++++++++++ arch/arm/mach-stm32mp/fdt.c | 7 +++++++ arch/arm/mach-stm32mp/include/mach/sys_proto.h | 8 +++++++- doc/board/st/stm32mp1.rst | 8 ++++++++ 4 files changed, 40 insertions(+), 1 deletion(-) (limited to 'doc') diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 9c5e0448ce5..9aa57943345 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -285,18 +285,36 @@ void get_soc_name(char name[SOC_NAME_SIZE]) /* MPUs Part Numbers */ switch (get_cpu_type()) { + case CPU_STM32MP157Fxx: + cpu_s = "157F"; + break; + case CPU_STM32MP157Dxx: + cpu_s = "157D"; + break; case CPU_STM32MP157Cxx: cpu_s = "157C"; break; case CPU_STM32MP157Axx: cpu_s = "157A"; break; + case CPU_STM32MP153Fxx: + cpu_s = "153F"; + break; + case CPU_STM32MP153Dxx: + cpu_s = "153D"; + break; case CPU_STM32MP153Cxx: cpu_s = "153C"; break; case CPU_STM32MP153Axx: cpu_s = "153A"; break; + case CPU_STM32MP151Fxx: + cpu_s = "151F"; + break; + case CPU_STM32MP151Dxx: + cpu_s = "151D"; + break; case CPU_STM32MP151Cxx: cpu_s = "151C"; break; diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c index a3db86dc465..3ee7d6a8337 100644 --- a/arch/arm/mach-stm32mp/fdt.c +++ b/arch/arm/mach-stm32mp/fdt.c @@ -244,6 +244,8 @@ int ft_system_setup(void *blob, bd_t *bd) get_soc_name(name); switch (cpu) { + case CPU_STM32MP151Fxx: + case CPU_STM32MP151Dxx: case CPU_STM32MP151Cxx: case CPU_STM32MP151Axx: stm32_fdt_fixup_cpu(blob, name); @@ -251,6 +253,8 @@ int ft_system_setup(void *blob, bd_t *bd) soc = fdt_path_offset(blob, "/soc"); stm32_fdt_disable(blob, soc, STM32_FDCAN_BASE, "can", name); /* fall through */ + case CPU_STM32MP153Fxx: + case CPU_STM32MP153Dxx: case CPU_STM32MP153Cxx: case CPU_STM32MP153Axx: stm32_fdt_disable(blob, soc, STM32_GPU_BASE, "gpu", name); @@ -261,8 +265,11 @@ int ft_system_setup(void *blob, bd_t *bd) } switch (cpu) { + case CPU_STM32MP157Dxx: case CPU_STM32MP157Axx: + case CPU_STM32MP153Dxx: case CPU_STM32MP153Axx: + case CPU_STM32MP151Dxx: case CPU_STM32MP151Axx: stm32_fdt_disable(blob, soc, STM32_CRYP1_BASE, "cryp", name); stm32_fdt_disable(blob, soc, STM32_CRYP2_BASE, "cryp", name); diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index 065b7b28561..1617126beac 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -3,13 +3,19 @@ * Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved */ -/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0)*/ +/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit7:0) */ #define CPU_STM32MP157Cxx 0x05000000 #define CPU_STM32MP157Axx 0x05000001 #define CPU_STM32MP153Cxx 0x05000024 #define CPU_STM32MP153Axx 0x05000025 #define CPU_STM32MP151Cxx 0x0500002E #define CPU_STM32MP151Axx 0x0500002F +#define CPU_STM32MP157Fxx 0x05000080 +#define CPU_STM32MP157Dxx 0x05000081 +#define CPU_STM32MP153Fxx 0x050000A4 +#define CPU_STM32MP153Dxx 0x050000A5 +#define CPU_STM32MP151Fxx 0x050000AE +#define CPU_STM32MP151Dxx 0x050000AF /* return CPU_STMP32MP...Xxx constants */ u32 get_cpu_type(void); diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst index ee42af6579d..b7a0fbfd035 100644 --- a/doc/board/st/stm32mp1.rst +++ b/doc/board/st/stm32mp1.rst @@ -25,6 +25,14 @@ It features: - Standard connectivity, widely inherited from the STM32 MCU family - Comprehensive security support +Each line comes with a security option (cryptography & secure boot) and +a Cortex-A frequency option: + + - A : Cortex-A7 @ 650 MHz + - C : Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz + - D : Cortex-A7 @ 800 MHz + - F : Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz + Everything is supported in Linux but U-Boot is limited to: 1. UART -- cgit v1.3.1 From 9368bdfebde16368cdb642adbb12f9c871c94d63 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 6 Mar 2020 11:14:11 +0100 Subject: ram: stm32mp1: the property st, phy-cal becomes optional This parameter "st,phy-cal" becomes optional and when it is absent the built-in PHY calibration is done. It is the case in the helper dtsi file "stm32mp15-ddr.dtsi" except if DDR_PHY_CAL_SKIP is defined. This patch also impact the ddr interactive mode - the registers of the param 'phy.cal' are initialized to 0 when "st,phy-cal" is not present in device tree (default behavior when DDR_PHY_CAL_SKIP is not activated) - the info 'cal' field can be use to change the calibration behavior - cal=1 => use param phy.cal to initialize the PHY, built-in training is skipped - cal=0 => param phy.cal is absent, built-in training is used (default) Signed-off-by: Patrick Delaunay Acked-by: Patrice Chotard --- arch/arm/dts/stm32mp15-ddr.dtsi | 3 ++ .../memory-controllers/st,stm32mp1-ddr.txt | 2 ++ drivers/ram/stm32mp1/stm32mp1_ddr.c | 19 +++++++----- drivers/ram/stm32mp1/stm32mp1_ddr.h | 1 + drivers/ram/stm32mp1/stm32mp1_interactive.c | 13 ++++++++- drivers/ram/stm32mp1/stm32mp1_ram.c | 34 +++++++++++++++++----- 6 files changed, 56 insertions(+), 16 deletions(-) (limited to 'doc') diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi index 38f29bb789e..8b20b5e1735 100644 --- a/arch/arm/dts/stm32mp15-ddr.dtsi +++ b/arch/arm/dts/stm32mp15-ddr.dtsi @@ -133,6 +133,7 @@ DDR_MR3 >; +#ifdef DDR_PHY_CAL_SKIP st,phy-cal = < DDR_DX0DLLCR DDR_DX0DQTR @@ -148,6 +149,8 @@ DDR_DX3DQSTR >; +#endif + status = "okay"; }; }; diff --git a/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt b/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt index ee708ce92c7..ac6a7df4327 100644 --- a/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt +++ b/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt @@ -129,6 +129,8 @@ phyc attributes: MR3 - st,phy-cal : phy cal depending of calibration or tuning of DDR + This parameter is optional; when it is absent the built-in PHY + calibration is done. for STM32MP15x: 12 values are requested in this order DX0DLLCR DX0DQTR diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c index b9300dd6d16..11b14ae6520 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr.c +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c @@ -769,7 +769,8 @@ start: */ set_reg(priv, REGPHY_REG, &config->p_reg); set_reg(priv, REGPHY_TIMING, &config->p_timing); - set_reg(priv, REGPHY_CAL, &config->p_cal); + if (config->p_cal_present) + set_reg(priv, REGPHY_CAL, &config->p_cal); if (INTERACTIVE(STEP_PHY_INIT)) goto start; @@ -804,13 +805,16 @@ start: wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL); - debug("DDR DQS training : "); + if (config->p_cal_present) { + debug("DDR DQS training skipped.\n"); + } else { + debug("DDR DQS training : "); /* 8. Disable Auto refresh and power down by setting * - RFSHCTL3.dis_au_refresh = 1 * - PWRCTL.powerdown_en = 0 * - DFIMISC.dfiinit_complete_en = 0 */ - stm32mp1_refresh_disable(priv->ctl); + stm32mp1_refresh_disable(priv->ctl); /* 9. Program PUBL PGCR to enable refresh during training and rank to train * not done => keep the programed value in PGCR @@ -818,14 +822,15 @@ start: /* 10. configure PUBL PIR register to specify which training step to run */ /* warning : RVTRN is not supported by this PUBL */ - stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN); + stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN); /* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */ - ddrphy_idone_wait(priv->phy); + ddrphy_idone_wait(priv->phy); /* 12. set back registers in step 8 to the orginal values if desidered */ - stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3, - config->c_reg.pwrctl); + stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3, + config->c_reg.pwrctl); + } /* if (config->p_cal_present) */ /* enable uMCTL2 AXI port 0 and 1 */ setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN); diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.h b/drivers/ram/stm32mp1/stm32mp1_ddr.h index 52b748f3ca2..4998f044394 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr.h +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.h @@ -170,6 +170,7 @@ struct stm32mp1_ddr_config { struct stm32mp1_ddrphy_reg p_reg; struct stm32mp1_ddrphy_timing p_timing; struct stm32mp1_ddrphy_cal p_cal; + bool p_cal_present; }; int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u32 mem_speed); diff --git a/drivers/ram/stm32mp1/stm32mp1_interactive.c b/drivers/ram/stm32mp1/stm32mp1_interactive.c index cedf92cb5f1..805c9ddaadc 100644 --- a/drivers/ram/stm32mp1/stm32mp1_interactive.c +++ b/drivers/ram/stm32mp1/stm32mp1_interactive.c @@ -106,7 +106,7 @@ static void stm32mp1_do_usage(void) "help displays help\n" "info displays DDR information\n" "info changes DDR information\n" - " with = step, name, size or speed\n" + " with = step, name, size, speed or cal\n" "freq displays the DDR PHY frequency in kHz\n" "freq changes the DDR PHY frequency\n" "param [type|reg] prints input parameters\n" @@ -160,6 +160,7 @@ static void stm32mp1_do_info(struct ddr_info *priv, printf("name = %s\n", config->info.name); printf("size = 0x%x\n", config->info.size); printf("speed = %d kHz\n", config->info.speed); + printf("cal = %d\n", config->p_cal_present); return; } @@ -208,6 +209,16 @@ static void stm32mp1_do_info(struct ddr_info *priv, } return; } + if (!strcmp(argv[1], "cal")) { + if (strict_strtoul(argv[2], 10, &value) < 0 || + (value != 0 && value != 1)) { + printf("invalid value %s\n", argv[2]); + } else { + config->p_cal_present = value; + printf("cal = %d\n", config->p_cal_present); + } + return; + } printf("argument %s invalid\n", argv[1]); } diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c index eb78f1198d7..b1e593f86bd 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ram.c +++ b/drivers/ram/stm32mp1/stm32mp1_ram.c @@ -65,18 +65,22 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) struct clk axidcg; struct stm32mp1_ddr_config config; -#define PARAM(x, y) \ - { x,\ - offsetof(struct stm32mp1_ddr_config, y),\ - sizeof(config.y) / sizeof(u32)} +#define PARAM(x, y, z) \ + { .name = x, \ + .offset = offsetof(struct stm32mp1_ddr_config, y), \ + .size = sizeof(config.y) / sizeof(u32), \ + .present = z, \ + } -#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x) -#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x) +#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x, NULL) +#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x, NULL) +#define PHY_PARAM_OPT(x) PARAM("st,phy-"#x, p_##x, &config.p_##x##_present) const struct { const char *name; /* name in DT */ const u32 offset; /* offset in config struct */ const u32 size; /* size of parameters */ + bool * const present; /* presence indication for opt */ } param[] = { CTL_PARAM(reg), CTL_PARAM(timing), @@ -84,7 +88,7 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) CTL_PARAM(perf), PHY_PARAM(reg), PHY_PARAM(timing), - PHY_PARAM(cal) + PHY_PARAM_OPT(cal) }; config.info.speed = dev_read_u32_default(dev, "st,mem-speed", 0); @@ -103,11 +107,25 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) param[idx].size); debug("%s: %s[0x%x] = %d\n", __func__, param[idx].name, param[idx].size, ret); - if (ret) { + if (ret && + (ret != -FDT_ERR_NOTFOUND || !param[idx].present)) { pr_err("%s: Cannot read %s, error=%d\n", __func__, param[idx].name, ret); return -EINVAL; } + if (param[idx].present) { + /* save presence of optional parameters */ + *param[idx].present = true; + if (ret == -FDT_ERR_NOTFOUND) { + *param[idx].present = false; +#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE + /* reset values if used later */ + memset((void *)((u32)&config + + param[idx].offset), + 0, param[idx].size * sizeof(u32)); +#endif + } + } } ret = clk_get_by_name(dev, "axidcg", &axidcg); -- cgit v1.3.1