From f5cbb5c7cd24b5e674933bb381d854c02512d2d9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 27 Jun 2021 17:50:57 -0600 Subject: x86: pci: Allow binding of some devices before relocation At present only bridge devices are bound before relocation, to save space in pre-relocation memory. In some cases we do actually want to bind a device, e.g. because it provides the console UART. Add a devicetree binding to support this. Use the PCI_VENDEV() macro to encode the cell value. This is present in U-Boot but not used, so move it to the binding header-file. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- doc/device-tree-bindings/pci/x86-pci.txt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'doc') diff --git a/doc/device-tree-bindings/pci/x86-pci.txt b/doc/device-tree-bindings/pci/x86-pci.txt index 95e370b3e72..cf4e5ed595a 100644 --- a/doc/device-tree-bindings/pci/x86-pci.txt +++ b/doc/device-tree-bindings/pci/x86-pci.txt @@ -20,6 +20,10 @@ For PCI devices the following optional property is available: output to be lost. This should not generally be used in production code, although it is often harmless. +- u-boot,pci-pre-reloc : List of vendor/device IDs to bind before relocation, even + if they are not bridges. This is useful if the device is needed (e.g. a + UART). The format is 0xvvvvdddd where d is the device ID and v is the + vendor ID. Example: @@ -32,7 +36,8 @@ pci { 0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000 0x01000000 0x0 0x1000 0x1000 0 0xefff>; u-boot,skip-auto-config-until-reloc; - + u-boot,pci-pre-reloc = < + PCI_VENDEV(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_UART2)>; serial: serial@18,2 { reg = <0x0200c210 0 0 0 0>; -- cgit v1.2.3 From e74d0ec80bfd4a8326008836dfc81099382a41b5 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 27 Jun 2021 17:51:08 -0600 Subject: x86: coreboot: Document the memory map Add information about memory usage when U-Boot is started from coreboot. This is useful when debugging. Also, since coreboot takes a chunk of memory in the middle of SDRAM for use by PCI devices, it can help avoid overwriting this with a loaded kernel by accident. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- doc/board/coreboot/coreboot.rst | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'doc') diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst index 9c44c025a48..3792f9e1c8d 100644 --- a/doc/board/coreboot/coreboot.rst +++ b/doc/board/coreboot/coreboot.rst @@ -50,3 +50,24 @@ works by using a 32-bit SPL binary to switch to 64-bit for running U-Boot. It can be useful for running UEFI applications, for example. This has only been lightly tested. + + +Memory map +---------- + + ========== ================================================================== + Address Region at that address + ========== ================================================================== + ffffffff Top of ROM (and last byte of 32-bit address space) + 7a9fd000 Typical top of memory available to U-Boot + (use cbsysinfo to see where memory range 'table' starts) + 10000000 Memory reserved by coreboot for mapping PCI devices + (typical size 2151000, includes framebuffer) + 1920000 CONFIG_SYS_CAR_ADDR, fake Cache-as-RAM memory, used during startup + 1110000 CONFIG_SYS_TEXT_BASE (start address of U-Boot code, before reloc) + 110000 CONFIG_BLOBLIST_ADDR (before being relocated) + 100000 CONFIG_PRE_CON_BUF_ADDR + f0000 ACPI tables set up by U-Boot + (typically redirects to 7ab10030 or similar) + 500 Location of coreboot sysinfo table, used during startup + ========== ================================================================== -- cgit v1.2.3 From 4db474aea09ab75644e0c5a63c57d74226be921d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 27 Jun 2021 17:51:11 -0600 Subject: doc: Update documentation for cros-2021.04 release With the new 2021.04 we have a new version of Chromium OS boot, which supports sandbox, coral and coral-on-coreboot. Add documentation for this. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- doc/chromium/run_vboot.rst | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'doc') diff --git a/doc/chromium/run_vboot.rst b/doc/chromium/run_vboot.rst index 41b4f631835..a9e4408d55f 100644 --- a/doc/chromium/run_vboot.rst +++ b/doc/chromium/run_vboot.rst @@ -6,11 +6,15 @@ Running U-Boot with Chromium OS verified boot ============================================= +Note: Once you use the source below you can obtain extra documentation with +'make htmldocs'. See the 'Internal Documentation' link, under +'Chromium OS-specific doc'. + To obtain:: git clone https://github.com/sjg20/u-boot.git cd u-boot - git checkout cros-master + git checkout cros-2021.04 cd .. git clone https://chromium.googlesource.com/chromiumos/platform/vboot_reference @@ -169,7 +173,8 @@ detect problems that affect the flow or particular vboot features. U-Boot without Chromium OS verified boot ---------------------------------------- -The following script can be used to boot a Chrome OS image on coral:: +The following script can be used to boot a Chrome OS image on coral. It is +defined as the boot command in mainline:: # Read the image header and obtain the address of the kernel # The offset 4f0 is defined by verified boot and may change for other @@ -195,10 +200,4 @@ The following script can be used to boot a Chrome OS image on coral:: zboot go -TO DO ------ - -Get the full ACPI tables working with Coral - - 7 October 2018 -- cgit v1.2.3