From 0dc8cbda52a11addd0abe7bea77927fc2ba88d77 Mon Sep 17 00:00:00 2001 From: Thomas Weißschuh Date: Sun, 11 Feb 2024 21:18:41 +0100 Subject: doc: fix mistyped "env flags" command MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Thomas Weißschuh Reviewed-by: Heinrich Schuchardt --- doc/usage/cmd/env.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'doc') diff --git a/doc/usage/cmd/env.rst b/doc/usage/cmd/env.rst index a859e32798c..a7e21693a67 100644 --- a/doc/usage/cmd/env.rst +++ b/doc/usage/cmd/env.rst @@ -350,7 +350,7 @@ edit exists CONFIG_CMD_ENV_EXISTS -flsgs +flags CONFIG_CMD_ENV_FLAGS erase -- cgit v1.3.1 From 27987b86a0a45849c1f6110252ec15b413caf34c Mon Sep 17 00:00:00 2001 From: Alexander Dahl Date: Mon, 26 Feb 2024 16:46:43 +0100 Subject: doc: develop: commands: Fix function prototype When using the previous prototype you got a compiler warning like this: warning: initialization of 'int (*)(struct cmd_tbl *, int, int, char * const*)' from incompatible pointer type 'int (*)(struct cmd_tbl *, int, int, const char **)' [-Wincompatible-pointer-types] Fixes: 3d9640f55cb2 ("doc: expand README.commands") Signed-off-by: Alexander Dahl --- doc/develop/commands.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'doc') diff --git a/doc/develop/commands.rst b/doc/develop/commands.rst index ede880d248c..5ad4e59c838 100644 --- a/doc/develop/commands.rst +++ b/doc/develop/commands.rst @@ -88,7 +88,7 @@ The command function pointer has to be of type .. code-block:: c - int (*cmd)(struct cmd_tbl *cmdtp, int flag, int argc, const char *argv[]); + int (*cmd)(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); cmdtp Table entry describing the command (see above). -- cgit v1.3.1 From f99a1e241ffe9ad979b93a2c7d58edadf083505d Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 28 Feb 2024 09:58:48 +0100 Subject: doc: board: phytec: phycore-am62x: Update artifact names Use proper binary artifact names for HSFS devices. Do not use the *_unsigned binaries. Signed-off-by: Wadim Egorov Reviewed-by: Dhruva Gole --- doc/board/phytec/phycore-am62x.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'doc') diff --git a/doc/board/phytec/phycore-am62x.rst b/doc/board/phytec/phycore-am62x.rst index 1d641a78cf8..bc6d5246694 100644 --- a/doc/board/phytec/phycore-am62x.rst +++ b/doc/board/phytec/phycore-am62x.rst @@ -92,9 +92,9 @@ Assuming the uSD card is `/dev/mmcblk0`: To boot from a micro SD card on a HSFS device simply copy the following artifacts to the FAT partition: -* tiboot3.bin from R5 build as tiboot3.bin -* tispl.bin_unsigned from Cortex-A build as tispl.bin -* u-boot.img_unsigned from Cortex-A build as u-boot.img +* tiboot3.bin from R5 build +* tispl.bin from Cortex-A build +* u-boot.img from Cortex-A build Boot ---- -- cgit v1.3.1 From b13297cc45baee6ee75292ee6aa39dfd0e048443 Mon Sep 17 00:00:00 2001 From: Benjamin Gray Date: Tue, 5 Mar 2024 19:52:03 +0100 Subject: doc/sphinx: fix Python string escapes Python 3.6 introduced a DeprecationWarning for invalid escape sequences. This is upgraded to a SyntaxWarning in Python 3.12, and will eventually be a syntax error. Fix these now to get ahead of it before it's an error. Signed-off-by: Benjamin Gray Message-ID: <20230912060801.95533-3-bgray@linux.ibm.com> Signed-off-by: Jonathan Corbet Adapted for U-Boot Signed-off-by: Heinrich Schuchardt --- doc/sphinx/cdomain.py | 2 +- doc/sphinx/kernel_abi.py | 2 +- doc/sphinx/kerneldoc.py | 2 +- doc/sphinx/maintainers_include.py | 8 ++++---- 4 files changed, 7 insertions(+), 7 deletions(-) (limited to 'doc') diff --git a/doc/sphinx/cdomain.py b/doc/sphinx/cdomain.py index 014a5229e57..491a7ed5f47 100644 --- a/doc/sphinx/cdomain.py +++ b/doc/sphinx/cdomain.py @@ -93,7 +93,7 @@ def markup_ctype_refs(match): # RE_expr = re.compile(r':c:(expr|texpr):`([^\`]+)`') def markup_c_expr(match): - return '\ ``' + match.group(2) + '``\ ' + return '\\ ``' + match.group(2) + '``\\ ' # # Parse Sphinx 3.x C markups, replacing them by backward-compatible ones diff --git a/doc/sphinx/kernel_abi.py b/doc/sphinx/kernel_abi.py index f3da859c987..32c50e496b5 100644 --- a/doc/sphinx/kernel_abi.py +++ b/doc/sphinx/kernel_abi.py @@ -147,7 +147,7 @@ class KernelCmd(Directive): code_block += "\n " + l lines = code_block + "\n\n" - line_regex = re.compile("^#define LINENO (\S+)\#([0-9]+)$") + line_regex = re.compile(r"^#define LINENO (\S+)\#([0-9]+)$") ln = 0 n = 0 f = fname diff --git a/doc/sphinx/kerneldoc.py b/doc/sphinx/kerneldoc.py index 01a55429c57..bc8bb9e5125 100644 --- a/doc/sphinx/kerneldoc.py +++ b/doc/sphinx/kerneldoc.py @@ -130,7 +130,7 @@ class KernelDocDirective(Directive): result = ViewList() lineoffset = 0; - line_regex = re.compile("^#define LINENO ([0-9]+)$") + line_regex = re.compile(r"^#define LINENO ([0-9]+)$") for line in lines: match = line_regex.search(line) if match: diff --git a/doc/sphinx/maintainers_include.py b/doc/sphinx/maintainers_include.py index dc8fed48d3c..6cee52cbb39 100755 --- a/doc/sphinx/maintainers_include.py +++ b/doc/sphinx/maintainers_include.py @@ -79,7 +79,7 @@ class MaintainersInclude(Include): line = line.rstrip() # Linkify all non-wildcard refs to ReST files in Documentation/. - pat = '(Documentation/([^\s\?\*]*)\.rst)' + pat = r'(Documentation/([^\s\?\*]*)\.rst)' m = re.search(pat, line) if m: # maintainers.rst is in a subdirectory, so include "../". @@ -92,11 +92,11 @@ class MaintainersInclude(Include): output = "| %s" % (line.replace("\\", "\\\\")) # Look for and record field letter to field name mappings: # R: Designated *reviewer*: FullName - m = re.search("\s(\S):\s", line) + m = re.search(r"\s(\S):\s", line) if m: field_letter = m.group(1) if field_letter and not field_letter in fields: - m = re.search("\*([^\*]+)\*", line) + m = re.search(r"\*([^\*]+)\*", line) if m: fields[field_letter] = m.group(1) elif subsystems: @@ -114,7 +114,7 @@ class MaintainersInclude(Include): field_content = "" # Collapse whitespace in subsystem name. - heading = re.sub("\s+", " ", line) + heading = re.sub(r"\s+", " ", line) output = output + "%s\n%s" % (heading, "~" * len(heading)) field_prev = "" else: -- cgit v1.3.1 From c8a2567475508156f4f43ea2caf3532790d47f8e Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 5 Mar 2024 19:52:04 +0100 Subject: doc: fix incorrect path Documentation When copying the build system for Linux we missed to replace some instances of 'Documentation' by 'doc'. Signed-off-by: Heinrich Schuchardt --- doc/sphinx/maintainers_include.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'doc') diff --git a/doc/sphinx/maintainers_include.py b/doc/sphinx/maintainers_include.py index 6cee52cbb39..13557d3d3c2 100755 --- a/doc/sphinx/maintainers_include.py +++ b/doc/sphinx/maintainers_include.py @@ -78,8 +78,8 @@ class MaintainersInclude(Include): # Drop needless input whitespace. line = line.rstrip() - # Linkify all non-wildcard refs to ReST files in Documentation/. - pat = r'(Documentation/([^\s\?\*]*)\.rst)' + # Linkify all non-wildcard refs to ReST files in doc/. + pat = r'(doc/([^\s\?\*]*)\.rst)' m = re.search(pat, line) if m: # maintainers.rst is in a subdirectory, so include "../". @@ -177,11 +177,11 @@ class MaintainersInclude(Include): if not self.state.document.settings.file_insertion_enabled: raise self.warning('"%s" directive disabled.' % self.name) - # Walk up source path directories to find Documentation/../ + # Walk up source path directories to find doc/../ path = self.state_machine.document.attributes['source'] path = os.path.realpath(path) tail = path - while tail != "Documentation" and tail != "": + while tail != "doc" and tail != "": (path, tail) = os.path.split(path) # Append "MAINTAINERS" -- cgit v1.3.1 From 3f190c55a4211215914126b74357344342329943 Mon Sep 17 00:00:00 2001 From: Wan Yee Lau Date: Mon, 5 Feb 2024 11:47:16 +0800 Subject: drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA Add socfpga_dtreg driver enablement for Intel SoCFPGA. Signed-off-by: Wan Yee Lau Reviewed-by: Tien Fong Chee --- arch/arm/Kconfig | 2 + doc/device-tree-bindings/misc/socfpga_dtreg.txt | 80 +++++++++++++++++ drivers/misc/Kconfig | 7 ++ drivers/misc/Makefile | 1 + drivers/misc/socfpga_dtreg.c | 115 ++++++++++++++++++++++++ 5 files changed, 205 insertions(+) create mode 100644 doc/device-tree-bindings/misc/socfpga_dtreg.txt create mode 100644 drivers/misc/socfpga_dtreg.c (limited to 'doc') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 01d6556c42b..16864f8afac 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1116,6 +1116,8 @@ config ARCH_SOCFPGA select SPL_LIBGENERIC_SUPPORT select SPL_OF_CONTROL select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 + select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64 + select SPL_SOCFPGA_DT_REG if TARGET_SOCFPGA_SOC64 select SPL_SERIAL select SPL_SYSRESET select SPL_WATCHDOG diff --git a/doc/device-tree-bindings/misc/socfpga_dtreg.txt b/doc/device-tree-bindings/misc/socfpga_dtreg.txt new file mode 100644 index 00000000000..cf40fdd2da8 --- /dev/null +++ b/doc/device-tree-bindings/misc/socfpga_dtreg.txt @@ -0,0 +1,80 @@ +* Firewall and privilege register settings in device tree + +Required properties: +-------------------- + +- compatible: should contain "intel,socfpga-dtreg" +- reg: Physical base address and size of block register. +- intel,offset-settings: 32-bit offset address of block register, + followed by 32-bit value settings and + the masking bits, only masking bit + set to 1 allows modification. + +The device tree node which describes secure and privilege register access +configuration in compile time. + +Most of these registers are expected to work except for the case which some +registers configuration are required for granting access to some other +registers, for example CCU registers have to be properly configured before +allowing register configuration access to fpga2sdram firewall as shown in +below example. + +Some registers depend on runtime data for proper configuration are expected +to be part of driver that generating these data for example configuration for +soc_noc_fw_ddr_mpu_inst_0_ddr_scr block register depend on DDR size parsed from +memory device tree node. + +Please refer details of tested examples below for both fpga2sdram and QoS +configuration with default reset value and the comments. + +Example: +-------- + +Configuration for multiple dtreg node support in device tree: + + socfpga_dtreg0: socfpga-dtreg0 { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 { + reg = <0xf7100200 0x00000014>; + intel,offset-settings = + /* + * Disable ocram security at CCU for + * non secure access + */ + <0x0000004 0x8000ffff 0xe007ffff>, + <0x0000008 0x8000ffff 0xe007ffff>, + <0x000000c 0x8000ffff 0xe007ffff>, + <0x0000010 0x8000ffff 0xe007ffff>; + bootph-all; + }; + }; + + socfpga_dtreg1: socfpga-dtreg1 { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 { + reg = <0xf8020000 0x0000001c>; + intel,offset-settings = + /* Disable MPFE firewall for SMMU */ + <0x00000000 0x00010101 0x00010101>, + /* + * Disable MPFE firewall for HMC + * adapter + */ + <0x00000004 0x00000001 0x00010101>; + bootph-all; + }; + }; + +To call the nodes use: + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-dtreg0", &dev); + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-dtreg1", &dev); + diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index f11ce72525f..98043fc2ff3 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -689,4 +689,11 @@ config SL28CPLD the base driver which provides common access methods for the sub-drivers. +config SPL_SOCFPGA_DT_REG + bool "Enable register setting from device tree in SPL" + depends on SPL + help + Enable register setting from device tree. This also + provides user a clean interface and all register settings are + centralized in one place, device tree. endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 0432db6ed12..1522f6c3b7d 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -90,3 +90,4 @@ obj-$(CONFIG_K3_AVS0) += k3_avs.o obj-$(CONFIG_ESM_K3) += k3_esm.o obj-$(CONFIG_ESM_PMIC) += esm_pmic.o obj-$(CONFIG_SL28CPLD) += sl28cpld.o +obj-$(CONFIG_SPL_SOCFPGA_SEC_REG) += socfpga_dtreg.o diff --git a/drivers/misc/socfpga_dtreg.c b/drivers/misc/socfpga_dtreg.c new file mode 100644 index 00000000000..ea5d0bcdf51 --- /dev/null +++ b/drivers/misc/socfpga_dtreg.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation + */ + +#include +#include +#include +#include + +#define NUMBER_OF_ELEMENTS 3 + +static int socfpga_dtreg_probe(struct udevice *dev) +{ + const fdt32_t *list; + fdt_addr_t offset, base; + fdt_val_t val, read_val, mask, set_mask; + int size, i; + u32 blk_sz, reg; + ofnode node; + const char *name = NULL; + + debug("%s(dev=%p)\n", __func__, dev); + + if (!dev_has_ofnode(dev)) + return 0; + + dev_for_each_subnode(node, dev) { + name = ofnode_get_name(node); + if (!name) + return -EINVAL; + + if (ofnode_read_u32_index(node, "reg", 1, &blk_sz)) + return -EINVAL; + + base = ofnode_get_addr(node); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + debug("%s(node_offset 0x%lx node_name %s ", __func__, + node.of_offset, name); + debug("node addr 0x%llx blk sz 0x%x)\n", base, blk_sz); + + list = ofnode_read_prop(node, "intel,offset-settings", &size); + if (!list) + return -EINVAL; + + debug("%s(intel,offset-settings property size=%x)\n", __func__, + size); + size /= sizeof(*list) * NUMBER_OF_ELEMENTS; + + /* + * First element: offset + * Second element: val + * Third element: mask + */ + for (i = 0; i < size; i++) { + offset = fdt32_to_cpu(*list++); + val = fdt32_to_cpu(*list++); + + /* Reads the masking bit value from the list */ + mask = fdt32_to_cpu(*list++); + + /* + * Reads out the offsets, value and masking bits + * Ex: <0x00000000 0x00000230 0xffffffff> + */ + debug("%s(intel,offset-settings 0x%llx : 0x%llx : 0x%llx)\n", + __func__, offset, val, mask); + + if (blk_sz < offset + SZ_4) { + printf("%s: Overflow as offset 0x%llx or reg", + __func__, offset); + printf(" write is more than block size 0x%x\n", + blk_sz); + return -EINVAL; + } + + if (mask != 0) { + if (mask == 0xffffffff) { + reg = base + offset; + writel(val, (uintptr_t)reg); + } else { + /* Mask the value with the masking bits */ + set_mask = val & mask; + + reg = base + offset; + + /* Clears and sets specific bits in the register */ + clrsetbits_le32((uintptr_t)reg, mask, set_mask); + } + } + + read_val = readl((uintptr_t)reg); + + /* Reads out the register, masked value and the read value */ + debug("%s(reg 0x%x = wr : 0x%llx rd : 0x%llx)\n", + __func__, reg, set_mask, read_val); + } + } + + return 0; +}; + +static const struct udevice_id socfpga_dtreg_ids[] = { + {.compatible = "intel,socfpga-dtreg"}, + { } +}; + +U_BOOT_DRIVER(socfpga_dtreg) = { + .name = "socfpga-dtreg", + .id = UCLASS_NOP, + .of_match = socfpga_dtreg_ids, + .probe = socfpga_dtreg_probe, +}; -- cgit v1.3.1