From f1d87db49bdc1cc97e0ee5636b20f1a99c4fcaf2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 14 Mar 2023 17:59:51 -0600 Subject: x86: minnowmax: Fix up adjustment of CONFIG_TEXT_BASE With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings. Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too. Add documentation on how to make this change safely. Fixes: 66e2c665f3b6 ("x86: minnowmax: Adjust CONFIG_TEXT_BASE") Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- doc/board/intel/minnowmax.rst | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'doc') diff --git a/doc/board/intel/minnowmax.rst b/doc/board/intel/minnowmax.rst index 1ba25b50d21..d0286bd9937 100644 --- a/doc/board/intel/minnowmax.rst +++ b/doc/board/intel/minnowmax.rst @@ -54,9 +54,9 @@ Offset Description Controlling config 000000 descriptor.bin Hard-coded to 0 in ifdtool 001000 me.bin Set by the descriptor 500000 +5f0000 MRC cache CONFIG_ENABLE_MRC_CACHE +600000 u-boot-dtb.bin CONFIG_TEXT_BASE 6ef000 Environment CONFIG_ENV_OFFSET -6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE -700000 u-boot-dtb.bin CONFIG_TEXT_BASE 7b0000 vga.bin CONFIG_VGA_BIOS_ADDR 7c0000 fsp.bin CONFIG_FSP_ADDR 7f8000 (depends on size of fsp.bin) @@ -68,3 +68,14 @@ Overall ROM image size is controlled by CONFIG_ROM_SIZE. Note that the debug version of the FSP is bigger in size. If this version is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of the default value 0xfffc0000. + +If you want to change CONFIG_TEXT_BASE from the current value of ffe00000 +you need to check a few other things. CONFIG_SYS_MONITOR_BASE should +automatically update to be the same as CONFIG_TEXT_BASE but +CONFIG_SYS_MONITOR_LEN may need to be adjusted too. It must cover the space +from the start of U-Boot to the end of the RAM, since the 16-bit boot needs to +be able to jump to U-Boot. See the end of arch/x86/lib/fsp1/fsp_car.S which +has these values. + +Also check the MRC cache address in the devicetree ("rw-mrc-cache"). It must +not overlap with U-Boot. -- cgit v1.3.1