From a67e219d0ca1b4b45ddb0cfb0afa2d1781262f62 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Tue, 14 Mar 2023 00:38:26 +0000 Subject: clk: rockchip: rk3568: Fix reset handler The reset handler for rk3568 is missing its private data. This leads to an abort when a reset is triggered. => reset resetting ... "Synchronous Abort" handler, esr 0x96000045 elr: 0000000000a2bc04 lr : 0000000000a2bbd4 (reloc) elr: 00000000eff9bc04 lr : 00000000eff9bbd4 x0 : 00000000fdd20000 x1 : 0000000014000001 x2 : 000000000000fdb9 x3 : 00000000edf77e88 x4 : 00000000edf50e78 x5 : 00000000edf77530 x6 : 000000000000001d x7 : 00000000edf8a1d0 x8 : 00000000ffffffd8 x9 : 0000000000000008 x10: 000000000000000d x11: 0000000000000006 x12: 000000000001869f x13: 0000000086c290c5 x14: 000000009118e878 x15: 0000000000000000 x16: 00000000eff9bbb8 x17: 0000000012f8c119 x18: 00000000edf50dc0 x19: 0000000000000000 x20: 0000000000000001 x21: 0000000000000000 x22: 00000000edf85900 x23: 0000000000000001 x24: 00000000effe8bbc x25: 0000000000000000 x26: 00000000edf85940 x27: 0000000000000000 x28: 0000000000000000 x29: 00000000edf3c8e0 Code: d65f03c0 d5033fbf b9400661 529d9502 (b8216802) Resetting CPU ... Add the missing dev_set_priv to the rk3568 clk driver to fix this. Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") Signed-off-by: Peter Geis Reviewed-by: Kever Yang Reviewed-by: Jagan Teki Tested-by: Jagan Teki # radxa-cm3 Signed-off-by: Jonas Karlman --- drivers/clk/rockchip/clk_rk3568.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 99c195b3afe..253b69504f9 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -2937,6 +2938,7 @@ static int rk3568_clk_bind(struct udevice *dev) glb_srst_fst); priv->glb_srst_snd_value = offsetof(struct rk3568_cru, glb_srsr_snd); + dev_set_priv(sys_child, priv); } #if CONFIG_IS_ENABLED(RESET_ROCKCHIP) -- cgit v1.3.1 From 67a1d773e7ed1bbfe05ff02d13e56558e7203af5 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 14 Mar 2023 00:38:27 +0000 Subject: clk: rockchip: rk3588: Fix clk_aux16m in clock driver The rate and error value is not returned for aux16m clocks, fix this. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3588.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index 5271d943483..a7df553e875 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -1558,7 +1558,7 @@ static ulong rk3588_clk_get_rate(struct clk *clk) #ifndef CONFIG_SPL_BUILD case CLK_AUX16M_0: case CLK_AUX16M_1: - rk3588_aux16m_get_clk(priv, clk->id); + rate = rk3588_aux16m_get_clk(priv, clk->id); break; case ACLK_VOP_ROOT: case ACLK_VOP: @@ -1707,7 +1707,7 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate) #ifndef CONFIG_SPL_BUILD case CLK_AUX16M_0: case CLK_AUX16M_1: - rk3588_aux16m_set_clk(priv, clk->id, rate); + ret = rk3588_aux16m_set_clk(priv, clk->id, rate); break; case ACLK_VOP_ROOT: case ACLK_VOP: -- cgit v1.3.1 From 4340771323fc8cc9eee5508ffabbd48d0d83c27a Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Tue, 7 Mar 2023 21:16:10 -0800 Subject: clk: rockchip: rk3568: add stubs for CLK_PCIEPHY_REF clocks Device tree contains assigned-clock-rates property for these, but default value will work just fine Reviewed-by: Kever Yang Signed-off-by: Vasily Khoruzhick --- drivers/clk/rockchip/clk_rk3568.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 253b69504f9..1c6adc56f91 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -425,6 +425,9 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate) case PCLK_PMU: ret = rk3568_pmu_set_pmuclk(priv, rate); break; + case CLK_PCIEPHY0_REF: + case CLK_PCIEPHY1_REF: + return 0; default: return -ENOENT; } -- cgit v1.3.1 From afafaa2a8f3f0ef38fc55c5d830890adb508549f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 18 Mar 2023 12:30:53 +0100 Subject: clk: renesas: Pack reset identifier before look up The reset identifier must be processed via MOD_CLK_PACK() before it is used to look up register and bit within reset_regs or reset_clear_regs arrays, otherwise completely bogus register and bit is picked from the arrays, one which may even be out of range. Fixes: 326e05c5e21 ("clk: renesas: Add and enable CPG reset driver") Signed-off-by: Marek Vasut --- drivers/clk/renesas/clk-rcar-gen3.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index d778db6569d..c121d82de7e 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -479,8 +479,9 @@ static int gen3_reset_assert(struct reset_ctl *reset_ctl) { struct udevice *cdev = (struct udevice *)dev_get_driver_data(reset_ctl->dev); struct gen3_clk_priv *priv = dev_get_priv(cdev); - unsigned int reg = reset_ctl->id / 32; - unsigned int bit = reset_ctl->id % 32; + unsigned int packed_id = MOD_CLK_PACK(reset_ctl->id); + unsigned int reg = packed_id / 32; + unsigned int bit = packed_id % 32; u32 bitmask = BIT(bit); writel(bitmask, priv->base + priv->info->reset_regs[reg]); @@ -492,8 +493,9 @@ static int gen3_reset_deassert(struct reset_ctl *reset_ctl) { struct udevice *cdev = (struct udevice *)dev_get_driver_data(reset_ctl->dev); struct gen3_clk_priv *priv = dev_get_priv(cdev); - unsigned int reg = reset_ctl->id / 32; - unsigned int bit = reset_ctl->id % 32; + unsigned int packed_id = MOD_CLK_PACK(reset_ctl->id); + unsigned int reg = packed_id / 32; + unsigned int bit = packed_id % 32; u32 bitmask = BIT(bit); writel(bitmask, priv->base + priv->info->reset_clear_regs[reg]); -- cgit v1.3.1