From 0131c902148432c10ef762afb92acbdf7242cc78 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Wed, 2 Aug 2023 13:47:25 +0530 Subject: net: ti: am65-cpsw-nuss: Add support for SGMII mode Add support for configuring the CPSW Ethernet Switch in SGMII mode. Signed-off-by: Siddharth Vadapalli --- drivers/net/ti/am65-cpsw-nuss.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'drivers/net') diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 51a8167d14a..456c3eb5b24 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -57,6 +57,12 @@ #define AM65_CPSW_PN_REG_SA_L 0x308 #define AM65_CPSW_PN_REG_SA_H 0x30c +#define AM65_CPSW_SGMII_CONTROL_REG 0x010 +#define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG 0x018 +#define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0) + +#define ADVERTISE_SGMII 0x1 + #define AM65_CPSW_ALE_CTL_REG 0x8 #define AM65_CPSW_ALE_CTL_REG_ENABLE BIT(31) #define AM65_CPSW_ALE_CTL_REG_RESET_TBL BIT(30) @@ -92,6 +98,7 @@ struct am65_cpsw_port { fdt_addr_t port_base; + fdt_addr_t port_sgmii_base; fdt_addr_t macsl_base; bool disabled; u32 mac_control; @@ -204,6 +211,8 @@ static int am65_cpsw_update_link(struct am65_cpsw_priv *priv) mac_control |= AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX; if (phy->speed == 100) mac_control |= AM65_CPSW_MACSL_CTL_REG_IFCTL_A; + if (phy->interface == PHY_INTERFACE_MODE_SGMII) + mac_control |= AM65_CPSW_MACSL_CTL_EXT_EN; } if (mac_control == port->mac_control) @@ -229,6 +238,7 @@ out: #define AM65_GMII_SEL_MODE_MII 0 #define AM65_GMII_SEL_MODE_RMII 1 #define AM65_GMII_SEL_MODE_RGMII 2 +#define AM65_GMII_SEL_MODE_SGMII 3 #define AM65_GMII_SEL_RGMII_IDMODE BIT(4) @@ -280,6 +290,10 @@ static int am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv, rgmii_id = true; break; + case PHY_INTERFACE_MODE_SGMII: + mode = AM65_GMII_SEL_MODE_SGMII; + break; + default: dev_warn(dev, "Unsupported PHY mode: %u. Defaulting to MII.\n", @@ -420,6 +434,13 @@ static int am65_cpsw_start(struct udevice *dev) goto err_dis_rx; } + if (priv->phydev->interface == PHY_INTERFACE_MODE_SGMII) { + writel(ADVERTISE_SGMII, + port->port_sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG); + writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE, + port->port_sgmii_base + AM65_CPSW_SGMII_CONTROL_REG); + } + ret = phy_startup(priv->phydev); if (ret) { dev_err(dev, "phy_startup failed\n"); @@ -872,6 +893,8 @@ static int am65_cpsw_probe_nuss(struct udevice *dev) port->port_base = cpsw_common->cpsw_base + AM65_CPSW_CPSW_NU_PORTS_OFFSET + (i * AM65_CPSW_CPSW_NU_PORTS_OFFSET); + port->port_sgmii_base = cpsw_common->ss_base + + (i * AM65_CPSW_SGMII_BASE); port->macsl_base = port->port_base + AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET; } -- cgit v1.2.3 From 8a5fe044958af879d7364d56ee7210aa2fc1c2b1 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 2 Aug 2023 13:47:26 +0530 Subject: net: ti: am65-cpsw-nuss: Add logic to support MDIO reset Enhance the AM65 CPSW NUSS driver to perform a MDIO reset using a GPIO line. Logic is also added to perform a pre and post delay around reset using the optional 'reset-delay-us' and 'reset-post-delay-us' properties. This is similar to the reset being performed in the Linux kernel. The reset is done once when the CPSW MDIO bus is being initialized. Signed-off-by: Suman Anna Signed-off-by: Siddharth Vadapalli --- drivers/net/ti/am65-cpsw-nuss.c | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) (limited to 'drivers/net') diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 456c3eb5b24..f4e58093805 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,7 @@ #include #include #include +#include #include #include "cpsw_mdio.h" @@ -96,6 +98,8 @@ #define AM65_CPSW_CPPI_PKT_TYPE 0x7 +#define DEFAULT_GPIO_RESET_DELAY 10 + struct am65_cpsw_port { fdt_addr_t port_base; fdt_addr_t port_sgmii_base; @@ -120,6 +124,10 @@ struct am65_cpsw_common { struct mii_dev *bus; u32 bus_freq; + struct gpio_desc mdio_gpio_reset; + u32 reset_delay_us; + u32 reset_post_delay_us; + struct dma dma_tx; struct dma dma_rx; u32 rx_next; @@ -679,6 +687,16 @@ static int am65_cpsw_mdio_init(struct udevice *dev) if (!priv->has_phy || cpsw_common->bus) return 0; + if (IS_ENABLED(CONFIG_DM_GPIO)) { + if (dm_gpio_is_valid(&cpsw_common->mdio_gpio_reset)) { + dm_gpio_set_value(&cpsw_common->mdio_gpio_reset, 1); + udelay(cpsw_common->reset_delay_us); + dm_gpio_set_value(&cpsw_common->mdio_gpio_reset, 0); + if (cpsw_common->reset_post_delay_us > 0) + udelay(cpsw_common->reset_post_delay_us); + } + } + ret = am65_cpsw_mdio_setup(dev); if (ret) return ret; @@ -818,7 +836,7 @@ out: static int am65_cpsw_probe_nuss(struct udevice *dev) { struct am65_cpsw_common *cpsw_common = dev_get_priv(dev); - ofnode ports_np, node; + ofnode ports_np, node, mdio_np; int ret, i; struct udevice *port_dev; @@ -845,6 +863,24 @@ static int am65_cpsw_probe_nuss(struct udevice *dev) AM65_CPSW_CPSW_NU_ALE_BASE; cpsw_common->mdio_base = cpsw_common->ss_base + AM65_CPSW_MDIO_BASE; + if (IS_ENABLED(CONFIG_DM_GPIO)) { + /* get bus level PHY reset GPIO details */ + mdio_np = dev_read_subnode(dev, "mdio"); + if (!ofnode_valid(mdio_np)) { + ret = -ENOENT; + goto out; + } + + cpsw_common->reset_delay_us = ofnode_read_u32_default(mdio_np, "reset-delay-us", + DEFAULT_GPIO_RESET_DELAY); + cpsw_common->reset_post_delay_us = ofnode_read_u32_default(mdio_np, + "reset-post-delay-us", + 0); + ret = gpio_request_by_name_nodev(mdio_np, "reset-gpios", 0, + &cpsw_common->mdio_gpio_reset, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + } + ports_np = dev_read_subnode(dev, "ethernet-ports"); if (!ofnode_valid(ports_np)) { ret = -ENOENT; -- cgit v1.2.3 From fb89b69a3fa9c3521ece586bdbd01cc5b947d549 Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Sat, 5 Aug 2023 12:35:01 +0200 Subject: net: phy: motorcomm: Add support for YT8511 PHY The YT8511 ethernet PHYs can be found on e.g. the SOQuartz or the Quartz64. Add rudimentary support for them. Signed-off-by: Nicolas Frattaroli --- drivers/net/phy/Kconfig | 2 +- drivers/net/phy/motorcomm.c | 88 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+), 1 deletion(-) (limited to 'drivers/net') diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 0c3c39a5504..3d96938eaba 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -224,7 +224,7 @@ config PHY_MOTORCOMM tristate "Motorcomm PHYs" help Enables support for Motorcomm network PHYs. - Currently supports the YT8531 Gigabit Ethernet PHYs. + Currently supports the YT8511 and YT8531 Gigabit Ethernet PHYs. config PHY_MSCC bool "Microsemi Corp Ethernet PHYs support" diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index e822fd76f27..8635a960d6e 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -11,6 +11,7 @@ #include #include +#define PHY_ID_YT8511 0x0000010a #define PHY_ID_YT8531 0x4f51e91b #define PHY_ID_MASK GENMASK(31, 0) @@ -26,6 +27,31 @@ #define YTPHY_DTS_OUTPUT_CLK_25M 25000000 #define YTPHY_DTS_OUTPUT_CLK_125M 125000000 +#define YT8511_EXT_CLK_GATE 0x0c +#define YT8511_EXT_DELAY_DRIVE 0x0d +#define YT8511_EXT_SLEEP_CTRL 0x27 + +/* 2b00 25m from pll + * 2b01 25m from xtl *default* + * 2b10 62.m from pll + * 2b11 125m from pll + */ +#define YT8511_CLK_125M (BIT(2) | BIT(1)) +#define YT8511_PLLON_SLP BIT(14) + +/* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */ +#define YT8511_DELAY_RX BIT(0) + +/* TX Gig-E Delay is bits 7:4, default 0x5 + * TX Fast-E Delay is bits 15:12, default 0xf + * Delay = 150ps * N - 250ps + * On = 2000ps, off = 50ps + */ +#define YT8511_DELAY_GE_TX_EN (0xf << 4) +#define YT8511_DELAY_GE_TX_DIS (0x2 << 4) +#define YT8511_DELAY_FE_TX_EN (0xf << 12) +#define YT8511_DELAY_FE_TX_DIS (0x2 << 12) + #define YT8531_SCR_SYNCE_ENABLE BIT(6) /* 1b0 output 25m clock *default* * 1b1 output 125m clock @@ -347,6 +373,58 @@ static void ytphy_dt_parse(struct phy_device *phydev) priv->flag |= TX_CLK_1000_INVERTED; } +static int yt8511_config(struct phy_device *phydev) +{ + u32 ge, fe; + int ret; + + ret = genphy_config_aneg(phydev); + if (ret < 0) + return ret; + + switch (phydev->interface) { + case PHY_INTERFACE_MODE_RGMII: + ge = YT8511_DELAY_GE_TX_DIS; + fe = YT8511_DELAY_FE_TX_DIS; + break; + case PHY_INTERFACE_MODE_RGMII_RXID: + ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_DIS; + fe = YT8511_DELAY_FE_TX_DIS; + break; + case PHY_INTERFACE_MODE_RGMII_TXID: + ge = YT8511_DELAY_GE_TX_EN; + fe = YT8511_DELAY_FE_TX_EN; + break; + case PHY_INTERFACE_MODE_RGMII_ID: + ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN; + fe = YT8511_DELAY_FE_TX_EN; + break; + default: /* do not support other modes */ + return -EOPNOTSUPP; + } + + ret = ytphy_modify_ext(phydev, YT8511_EXT_CLK_GATE, + (YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN), ge); + if (ret < 0) + return ret; + /* set clock mode to 125m */ + ret = ytphy_modify_ext(phydev, YT8511_EXT_CLK_GATE, + YT8511_CLK_125M, YT8511_CLK_125M); + if (ret < 0) + return ret; + ret = ytphy_modify_ext(phydev, YT8511_EXT_DELAY_DRIVE, + YT8511_DELAY_FE_TX_EN, fe); + if (ret < 0) + return ret; + /* sleep control, disable PLL in sleep for now */ + ret = ytphy_modify_ext(phydev, YT8511_EXT_SLEEP_CTRL, YT8511_PLLON_SLP, + 0); + if (ret < 0) + return ret; + + return 0; +} + static int yt8531_config(struct phy_device *phydev) { struct ytphy_plat_priv *priv = phydev->priv; @@ -425,6 +503,16 @@ static int yt8531_probe(struct phy_device *phydev) return 0; } +U_BOOT_PHY_DRIVER(motorcomm8511) = { + .name = "YT8511 Gigabit Ethernet", + .uid = PHY_ID_YT8511, + .mask = PHY_ID_MASK, + .features = PHY_GBIT_FEATURES, + .config = &yt8511_config, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + U_BOOT_PHY_DRIVER(motorcomm8531) = { .name = "YT8531 Gigabit Ethernet", .uid = PHY_ID_YT8531, -- cgit v1.2.3 From cba79a1b2e1155eb69802cc9a8e7d1d856237f67 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Aug 2023 16:10:08 +0200 Subject: net: phy: broadcom: add support for BCM54210E MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's Broadcom PHY simply described as single-port RGMII 10/100/1000BASE-T PHY. It requires disabling delay skew and GTXCLK bits. BCM54210E support ported from Linux kernel commit 0fc9ae1076697 ("net: phy: broadcom: add support for BCM54210E") AUX/SHD/bcm54xx_config_clock_delay update ported from Linux 6.5-rc4 commit 28e219aea0b9e ("net: phy: broadcom: drop brcm_phy_setbits() and use phy_set_bits() instead") Signed-off-by: Marek Vasut Reviewed-by: Rafał Miłecki --- drivers/net/phy/broadcom.c | 101 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 100 insertions(+), 1 deletion(-) (limited to 'drivers/net') diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c index 36c70da181a..82e3bbef7dd 100644 --- a/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c @@ -30,10 +30,87 @@ #define MIIM_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */ #define MIIM_BCM_AUXCNTL_SHDWSEL_MISC 0x0007 -#define MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN 0x0800 +#define MIIM_BCM_AUXCNTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010 +#define MIIM_BCM_AUXCNTL_SHDWSEL_MISC_RGMII_EN 0x0080 +#define MIIM_BCM_AUXCNTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100 +#define MIIM_BCM_AUXCNTL_MISC_FORCE_AMDIX 0x0200 +#define MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN 0x0800 +#define MIIM_BCM_AUXCNTL_MISC_WREN 0x8000 #define MIIM_BCM_CHANNEL_WIDTH 0x2000 +#define BCM54810_SHD_CLK_CTL 0x3 +#define BCM54810_SHD_CLK_CTL_GTXCLK_EN BIT(9) + +static int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum) +{ + /* The register must be written to both the Shadow Register Select and + * the Shadow Read Register Selector + */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, + MIIM_BCM54xx_AUXCNTL_ENCODE(regnum)); + return phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL); +} + +static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val) +{ + return phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, regnum | val); +} + +static int bcm_phy_read_shadow(struct phy_device *phydev, u16 shadow) +{ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, + MIIM_BCM54XX_SHD_VAL(shadow)); + return MIIM_BCM54XX_SHD_DATA(phy_read(phydev, MDIO_DEVAD_NONE, + MIIM_BCM54XX_SHD)); +} + +static int bcm_phy_write_shadow(struct phy_device *phydev, u16 shadow, u16 val) +{ + return phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, + MIIM_BCM54XX_SHD_WR_ENCODE(shadow, val)); +} + +static int bcm54xx_config_clock_delay(struct phy_device *phydev) +{ + int rc, val; + + /* handling PHY's internal RX clock delay */ + val = bcm54xx_auxctl_read(phydev, MIIM_BCM_AUXCNTL_SHDWSEL_MISC); + val |= MIIM_BCM_AUXCNTL_MISC_WREN; + if (phydev->interface == PHY_INTERFACE_MODE_RGMII || + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { + /* Disable RGMII RXC-RXD skew */ + val &= ~MIIM_BCM_AUXCNTL_SHDWSEL_MISC_RGMII_SKEW_EN; + } + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { + /* Enable RGMII RXC-RXD skew */ + val |= MIIM_BCM_AUXCNTL_SHDWSEL_MISC_RGMII_SKEW_EN; + } + rc = bcm54xx_auxctl_write(phydev, MIIM_BCM_AUXCNTL_SHDWSEL_MISC, val); + if (rc < 0) + return rc; + + /* handling PHY's internal TX clock delay */ + val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL); + if (phydev->interface == PHY_INTERFACE_MODE_RGMII || + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { + /* Disable internal TX clock delay */ + val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN; + } + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { + /* Enable internal TX clock delay */ + val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN; + } + rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val); + if (rc < 0) + return rc; + + return 0; +} + static void bcm_phy_write_misc(struct phy_device *phydev, u16 reg, u16 chl, u16 value) { @@ -62,6 +139,18 @@ static int bcm5461_config(struct phy_device *phydev) return 0; } +/* Broadcom BCM54210E */ +static int bcm54210e_config(struct phy_device *phydev) +{ + int ret; + + ret = bcm54xx_config_clock_delay(phydev); + if (ret < 0) + return ret; + + return bcm5461_config(phydev); +} + static int bcm54xx_parse_status(struct phy_device *phydev) { unsigned int mii_reg; @@ -311,6 +400,16 @@ static int bcm5482_startup(struct phy_device *phydev) return bcm54xx_parse_status(phydev); } +U_BOOT_PHY_DRIVER(bcm54210e) = { + .name = "Broadcom BCM54210E", + .uid = 0x600d84a0, + .mask = 0xfffffff0, + .features = PHY_GBIT_FEATURES, + .config = &bcm54210e_config, + .startup = &bcm54xx_startup, + .shutdown = &genphy_shutdown, +}; + U_BOOT_PHY_DRIVER(bcm5461s) = { .name = "Broadcom BCM5461S", .uid = 0x2060c0, -- cgit v1.2.3 From 8ec228b62b4546376757492bf6fbd9607e97b98e Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 31 Aug 2023 22:16:38 +0000 Subject: net: zynq: Use generic_phy_valid() helper The documentation for struct phy state that "The content of the structure is managed solely by the PHY API and PHY drivers". Change to use the generic_phy_valid() helper to check if phy is valid. Fixes: 10c50b1facbf ("net: zynq: Add support for PHY configuration in SGMII mode") Signed-off-by: Jonas Karlman --- drivers/net/zynq_gem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/net') diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index f3cdfb0275d..3377e669f2f 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -890,7 +890,8 @@ static int zynq_gem_probe(struct udevice *dev) if (ret) goto err3; - if (priv->interface == PHY_INTERFACE_MODE_SGMII && phy.dev) { + if (priv->interface == PHY_INTERFACE_MODE_SGMII && + generic_phy_valid(&phy)) { if (IS_ENABLED(CONFIG_DM_ETH_PHY)) { if (device_is_compatible(dev, "cdns,zynqmp-gem") || device_is_compatible(dev, "xlnx,zynqmp-gem")) { -- cgit v1.2.3 From 3903d695b482e8958ec78c9acb87b85a6ba69e2b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 6 Sep 2023 23:30:08 +0200 Subject: net: miiphybb: Remove unused NEEDS_MANUAL_RELOC code bits The last user of the NEEDS_MANUAL_RELOC has been removed in commit 26af162ac8f8 ("arch: m68k: Implement relocation") Remove now unused NEEDS_MANUAL_RELOC code. Signed-off-by: Marek Vasut --- drivers/net/phy/miiphybb.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c index 24d617553e7..cf71f7d4e7e 100644 --- a/drivers/net/phy/miiphybb.c +++ b/drivers/net/phy/miiphybb.c @@ -18,10 +18,6 @@ #include #include -#define BB_MII_RELOCATE(v,off) (v += (v?off:0)) - -DECLARE_GLOBAL_DATA_PTR; - #ifndef CONFIG_BITBANGMII_MULTI /* @@ -110,21 +106,9 @@ int bb_miiphy_init(void) { int i; - for (i = 0; i < bb_miiphy_buses_num; i++) { -#if defined(CONFIG_NEEDS_MANUAL_RELOC) - /* Relocate the hook pointers*/ - BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off); - BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off); - BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_tristate, gd->reloc_off); - BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdio, gd->reloc_off); - BB_MII_RELOCATE(bb_miiphy_buses[i].get_mdio, gd->reloc_off); - BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdc, gd->reloc_off); - BB_MII_RELOCATE(bb_miiphy_buses[i].delay, gd->reloc_off); -#endif - if (bb_miiphy_buses[i].init != NULL) { + for (i = 0; i < bb_miiphy_buses_num; i++) + if (bb_miiphy_buses[i].init != NULL) bb_miiphy_buses[i].init(&bb_miiphy_buses[i]); - } - } return 0; } -- cgit v1.2.3 From 09c8b8de021781103bad3e90c0bffc47d84af99e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 6 Sep 2023 23:30:09 +0200 Subject: net: phy: Remove unused NEEDS_MANUAL_RELOC code bits The last user of the NEEDS_MANUAL_RELOC has been removed in commit 26af162ac8f8 ("arch: m68k: Implement relocation") Remove now unused NEEDS_MANUAL_RELOC code. Signed-off-by: Marek Vasut --- drivers/net/phy/phy.c | 31 ------------------------------- 1 file changed, 31 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index ae21acb059b..d50fd505e51 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -463,37 +463,6 @@ U_BOOT_PHY_DRIVER(genphy) = { .shutdown = genphy_shutdown, }; -#ifdef CONFIG_NEEDS_MANUAL_RELOC -int phy_init(void) -{ - const int ll_n_ents = ll_entry_count(struct phy_driver, phy_driver); - struct phy_driver *drv, *ll_entry; - - /* Perform manual relocation on linker list based PHY drivers */ - ll_entry = ll_entry_start(struct phy_driver, phy_driver); - for (drv = ll_entry; drv != ll_entry + ll_n_ents; drv++) { - if (drv->probe) - drv->probe += gd->reloc_off; - if (drv->config) - drv->config += gd->reloc_off; - if (drv->startup) - drv->startup += gd->reloc_off; - if (drv->shutdown) - drv->shutdown += gd->reloc_off; - if (drv->readext) - drv->readext += gd->reloc_off; - if (drv->writeext) - drv->writeext += gd->reloc_off; - if (drv->read_mmd) - drv->read_mmd += gd->reloc_off; - if (drv->write_mmd) - drv->write_mmd += gd->reloc_off; - } - - return 0; -} -#endif - int phy_set_supported(struct phy_device *phydev, u32 max_speed) { /* The default values for phydev->supported are provided by the PHY -- cgit v1.2.3 From a77c2bd90254df10d196e105593d1ed46bb5bceb Mon Sep 17 00:00:00 2001 From: Maxim Kochetkov Date: Fri, 11 Aug 2023 10:43:51 +0300 Subject: net: axi_emac: Convert to ofnode functions FDT functions is not working when OF_LIVE is enabled. Convert fdt parsing functions to ofnode parsing functions. Signed-off-by: Maxim Kochetkov Link: https://lore.kernel.org/r/20230811074351.26916-1-fido_max@inbox.ru --- drivers/net/xilinx_axi_emac.c | 50 +++++++++++++++++++++---------------------- 1 file changed, 24 insertions(+), 26 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 39cb3cc260b..54f22327684 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -112,7 +112,7 @@ struct axidma_plat { int pcsaddr; int phyaddr; u8 eth_hasnobuf; - int phy_of_handle; + ofnode phynode; enum emac_variant mactype; }; @@ -127,7 +127,7 @@ struct axidma_priv { struct phy_device *phydev; struct mii_dev *bus; u8 eth_hasnobuf; - int phy_of_handle; + ofnode phynode; enum emac_variant mactype; }; @@ -335,8 +335,8 @@ static int axiemac_phy_init(struct udevice *dev) phydev->supported &= supported; phydev->advertising = phydev->supported; priv->phydev = phydev; - if (priv->phy_of_handle) - priv->phydev->node = offset_to_ofnode(priv->phy_of_handle); + if (ofnode_valid(priv->phynode)) + priv->phydev->node = priv->phynode; phy_config(phydev); return 0; @@ -839,7 +839,7 @@ static int axi_emac_probe(struct udevice *dev) priv->eth_hasnobuf = plat->eth_hasnobuf; priv->pcsaddr = plat->pcsaddr; priv->phyaddr = plat->phyaddr; - priv->phy_of_handle = plat->phy_of_handle; + priv->phynode = plat->phynode; priv->interface = pdata->phy_interface; if (IS_ENABLED(CONFIG_DM_ETH_PHY)) @@ -894,20 +894,21 @@ static int axi_emac_of_to_plat(struct udevice *dev) { struct axidma_plat *plat = dev_get_plat(dev); struct eth_pdata *pdata = &plat->eth_pdata; - int node = dev_of_offset(dev); - int offset = 0; + struct ofnode_phandle_args pcs_node, axistream_node; + ofnode phynode; + int ret; pdata->iobase = dev_read_addr(dev); plat->mactype = dev_get_driver_data(dev); - offset = fdtdec_lookup_phandle(gd->fdt_blob, node, - "axistream-connected"); - if (offset <= 0) { + ret = dev_read_phandle_with_args(dev, "axistream-connected", NULL, 0, 0, + &axistream_node); + if (ret) { printf("%s: axistream is not found\n", __func__); return -EINVAL; } - plat->dmatx = (struct axidma_reg *)fdtdec_get_addr_size_auto_parent - (gd->fdt_blob, 0, offset, "reg", 0, NULL, false); + + plat->dmatx = (struct axidma_reg *)ofnode_get_addr(axistream_node.node); if (!plat->dmatx) { printf("%s: axi_dma register space not found\n", __func__); return -EINVAL; @@ -918,30 +919,27 @@ static int axi_emac_of_to_plat(struct udevice *dev) /* PHYAD 0 always redirects to the PCS/PMA PHY */ plat->pcsaddr = 0; - offset = fdtdec_lookup_phandle(gd->fdt_blob, node, - "phy-handle"); - if (offset > 0) { + phynode = dev_get_phy_node(dev); + if (ofnode_valid(phynode)) { if (!(IS_ENABLED(CONFIG_DM_ETH_PHY))) - plat->phyaddr = fdtdec_get_int(gd->fdt_blob, - offset, - "reg", -1); - plat->phy_of_handle = offset; + plat->phyaddr = ofnode_read_u32_default(phynode, + "reg", -1); + plat->phynode = phynode; } pdata->phy_interface = dev_read_phy_mode(dev); if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) return -EINVAL; - plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node, - "xlnx,eth-hasnobuf"); + plat->eth_hasnobuf = dev_read_bool(dev, "xlnx,eth-hasnobuf"); if (pdata->phy_interface == PHY_INTERFACE_MODE_SGMII || pdata->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { - offset = fdtdec_lookup_phandle(gd->fdt_blob, node, - "pcs-handle"); - if (offset > 0) { - plat->pcsaddr = fdtdec_get_int(gd->fdt_blob, - offset, "reg", -1); + ret = dev_read_phandle_with_args(dev, "pcs-handle", NULL, 0, 0, + &pcs_node); + if (!ret) { + plat->pcsaddr = ofnode_read_u32_default(pcs_node.node, + "reg", -1); } } } -- cgit v1.2.3 From e31d707d8b591973560cb656d152a154993b1d74 Mon Sep 17 00:00:00 2001 From: Tejas Bhumkar Date: Fri, 15 Sep 2023 10:20:43 +0530 Subject: net: phy: xilinx-gmii2rgmii: Removed hardcoded phy address 0 for bridge Current code expects bridge phy address at 0 which is not correct expectation because bridge phy address is configurable. That's why update the code to read reg property to figure it out where bridge is and use it in phy creation code. Signed-off-by: Tejas Bhumkar Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20230915045043.4167628-1-tejas.arvind.bhumkar@amd.com --- drivers/net/phy/phy.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/net') diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index d50fd505e51..63b3e46f101 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -807,7 +807,10 @@ static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus, ofnode_for_each_subnode(node, dev_ofnode(dev)) { node = ofnode_by_compatible(node, "xlnx,gmii-to-rgmii-1.0"); if (ofnode_valid(node)) { - phydev = phy_device_create(bus, 0, + int gmiirgmii_phyaddr; + + gmiirgmii_phyaddr = ofnode_read_u32_default(node, "reg", 0); + phydev = phy_device_create(bus, gmiirgmii_phyaddr, PHY_GMII2RGMII_ID, false); if (phydev) phydev->node = node; -- cgit v1.2.3 From 1e94b46f73cedcebbff73799203f3266c5b28d90 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 14 Sep 2023 18:21:46 -0600 Subject: common: Drop linux/printk.h from common header This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass --- drivers/net/bcm-sf2-eth-gmac.c | 1 + drivers/net/bcm-sf2-eth.c | 1 + drivers/net/bcm6348-eth.c | 1 + drivers/net/bcm6368-eth.c | 1 + drivers/net/designware.c | 1 + drivers/net/dwc_eth_qos.c | 1 + drivers/net/fsl-mc/dpio/qbman_sys.h | 1 + drivers/net/ftgmac100.c | 1 + drivers/net/mscc_eswitch/jr2_switch.c | 1 + drivers/net/mscc_eswitch/ocelot_switch.c | 1 + drivers/net/mscc_eswitch/serval_switch.c | 1 + drivers/net/mscc_eswitch/servalt_switch.c | 1 + drivers/net/mt7628-eth.c | 1 + drivers/net/mtk_eth.c | 1 + drivers/net/mvmdio.c | 1 + drivers/net/phy/dp83867.c | 1 + drivers/net/phy/mscc.c | 1 + drivers/net/rtl8169.c | 1 + drivers/net/sni_ave.c | 1 + drivers/net/ti/am65-cpsw-nuss.c | 1 + drivers/net/ti/cpsw-common.c | 1 + drivers/net/ti/cpsw.c | 1 + drivers/net/ti/keystone_net.c | 1 + 23 files changed, 23 insertions(+) (limited to 'drivers/net') diff --git a/drivers/net/bcm-sf2-eth-gmac.c b/drivers/net/bcm-sf2-eth-gmac.c index 3caf0f33109..cbe1e85222f 100644 --- a/drivers/net/bcm-sf2-eth-gmac.c +++ b/drivers/net/bcm-sf2-eth-gmac.c @@ -6,6 +6,7 @@ #ifdef BCM_GMAC_DEBUG #ifndef DEBUG #define DEBUG +#include #endif #endif diff --git a/drivers/net/bcm-sf2-eth.c b/drivers/net/bcm-sf2-eth.c index 88dc3ab3846..1524f5c9989 100644 --- a/drivers/net/bcm-sf2-eth.c +++ b/drivers/net/bcm-sf2-eth.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include diff --git a/drivers/net/bcm6348-eth.c b/drivers/net/bcm6348-eth.c index 53171736117..72dcd07d30d 100644 --- a/drivers/net/bcm6348-eth.c +++ b/drivers/net/bcm6348-eth.c @@ -18,6 +18,7 @@ #include #include #include +#include #define ETH_RX_DESC PKTBUFSRX #define ETH_MAX_MTU_SIZE 1518 diff --git a/drivers/net/bcm6368-eth.c b/drivers/net/bcm6368-eth.c index c2a8b9f0576..fdd938ce0dd 100644 --- a/drivers/net/bcm6368-eth.c +++ b/drivers/net/bcm6368-eth.c @@ -19,6 +19,7 @@ #include #include #include +#include #define ETH_PORT_STR "brcm,enetsw-port" diff --git a/drivers/net/designware.c b/drivers/net/designware.c index e09ca3313dd..20b86e74cec 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include "designware.h" diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 1e92bd9ca9c..9b1a9e69bf8 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -52,6 +52,7 @@ #include #endif #include +#include #include "dwc_eth_qos.h" diff --git a/drivers/net/fsl-mc/dpio/qbman_sys.h b/drivers/net/fsl-mc/dpio/qbman_sys.h index ff998d49dc4..1c6e4891302 100644 --- a/drivers/net/fsl-mc/dpio/qbman_sys.h +++ b/drivers/net/fsl-mc/dpio/qbman_sys.h @@ -21,6 +21,7 @@ /* Trace the 3 different classes of read/write access to QBMan. #undef as * required. */ #include +#include #undef QBMAN_CCSR_TRACE #undef QBMAN_CINH_TRACE #undef QBMAN_CENA_TRACE diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index a50cde338a2..587d3658fa9 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "ftgmac100.h" diff --git a/drivers/net/mscc_eswitch/jr2_switch.c b/drivers/net/mscc_eswitch/jr2_switch.c index 1462b8f3bc8..7157428a685 100644 --- a/drivers/net/mscc_eswitch/jr2_switch.c +++ b/drivers/net/mscc_eswitch/jr2_switch.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include "mscc_xfer.h" diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c b/drivers/net/mscc_eswitch/ocelot_switch.c index 1bf6c42c0fc..7ea1f551a11 100644 --- a/drivers/net/mscc_eswitch/ocelot_switch.c +++ b/drivers/net/mscc_eswitch/ocelot_switch.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "mscc_xfer.h" #include "mscc_mac_table.h" diff --git a/drivers/net/mscc_eswitch/serval_switch.c b/drivers/net/mscc_eswitch/serval_switch.c index 38ddba12b66..be06e483373 100644 --- a/drivers/net/mscc_eswitch/serval_switch.c +++ b/drivers/net/mscc_eswitch/serval_switch.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "mscc_xfer.h" #include "mscc_mac_table.h" diff --git a/drivers/net/mscc_eswitch/servalt_switch.c b/drivers/net/mscc_eswitch/servalt_switch.c index db863c2a9ff..2d2329c204a 100644 --- a/drivers/net/mscc_eswitch/servalt_switch.c +++ b/drivers/net/mscc_eswitch/servalt_switch.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "mscc_xfer.h" #include "mscc_miim.h" diff --git a/drivers/net/mt7628-eth.c b/drivers/net/mt7628-eth.c index 0a9bdb3ddbd..b95de474fb0 100644 --- a/drivers/net/mt7628-eth.c +++ b/drivers/net/mt7628-eth.c @@ -28,6 +28,7 @@ #include #include #include +#include /* Ethernet frame engine register */ #define PDMA_RELATED 0x0800 diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index d4111e73df1..3cfce058451 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "mtk_eth.h" diff --git a/drivers/net/mvmdio.c b/drivers/net/mvmdio.c index c0ebcdb1f68..5ebcfe14b7f 100644 --- a/drivers/net/mvmdio.c +++ b/drivers/net/mvmdio.c @@ -13,6 +13,7 @@ #include #include #include +#include #define MVMDIO_SMI_DATA_SHIFT 0 #define MVMDIO_SMI_PHY_ADDR_SHIFT 16 diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 7111e36aa0d..b6726031ebb 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c index ef1761a8bda..bd9cd952975 100644 --- a/drivers/net/phy/mscc.c +++ b/drivers/net/phy/mscc.c @@ -15,6 +15,7 @@ #include #include #include +#include /* Microsemi PHY ID's */ #define PHY_ID_VSC8530 0x00070560 diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 963702777c2..93e83661cec 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -51,6 +51,7 @@ #include #include #include +#include #undef DEBUG_RTL8169 #undef DEBUG_RTL8169_TX diff --git a/drivers/net/sni_ave.c b/drivers/net/sni_ave.c index f5a0d80af7a..8eeecbc4cf3 100644 --- a/drivers/net/sni_ave.c +++ b/drivers/net/sni_ave.c @@ -23,6 +23,7 @@ #include #include #include +#include #define AVE_GRST_DELAY_MSEC 40 #define AVE_MIN_XMITSIZE 60 diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index f4e58093805..18a33c4c0e3 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include "cpsw_mdio.h" diff --git a/drivers/net/ti/cpsw-common.c b/drivers/net/ti/cpsw-common.c index 3140f2515fb..d5428274d19 100644 --- a/drivers/net/ti/cpsw-common.c +++ b/drivers/net/ti/cpsw-common.c @@ -12,6 +12,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c index 3a8cc9c52a5..877be7fca52 100644 --- a/drivers/net/ti/cpsw.c +++ b/drivers/net/ti/cpsw.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "cpsw_mdio.h" diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c index 89b04b6fbda..43dbf3f1067 100644 --- a/drivers/net/ti/keystone_net.c +++ b/drivers/net/ti/keystone_net.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include -- cgit v1.2.3