From aa6e94deabb45154cea07ad44c4a5c047bca078b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:37 -0500 Subject: global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- drivers/pci/Kconfig | 2 +- drivers/pci/pci-rcar-gen2.c | 4 ++-- drivers/pci/pci_sh7751.c | 6 +++--- drivers/pci/pcie_dw_mvebu.c | 4 ++-- drivers/pci/pcie_layerscape.h | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) (limited to 'drivers/pci') diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 22f4995453e..a3b662fb13d 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -60,7 +60,7 @@ config PCI_MAP_SYSTEM_MEMORY instead of a physical address (e.g. on MIPS). The PCI core will then remap the virtual memory base address to a physical address when adding the PCI region of type PCI_REGION_SYS_MEMORY. - This should only be required on MIPS where CONFIG_SYS_SDRAM_BASE is still + This should only be required on MIPS where CFG_SYS_SDRAM_BASE is still being used as virtual address. config PCI_SRIOV diff --git a/drivers/pci/pci-rcar-gen2.c b/drivers/pci/pci-rcar-gen2.c index dc114027814..b81eb353689 100644 --- a/drivers/pci/pci-rcar-gen2.c +++ b/drivers/pci/pci-rcar-gen2.c @@ -191,7 +191,7 @@ static int rcar_gen2_pci_probe(struct udevice *dev) /* AHB-PCI Bridge Communication Registers */ writel(RCAR_AHB_BUS_MODE, priv->cfg_base + RCAR_AHB_BUS_CTR_REG); - writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16, + writel((CFG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16, priv->cfg_base + RCAR_PCIAHB_WIN1_CTR_REG); writel(0xf0000000 | RCAR_PCIAHB_PREFETCH16, priv->cfg_base + RCAR_PCIAHB_WIN2_CTR_REG); @@ -204,7 +204,7 @@ static int rcar_gen2_pci_probe(struct udevice *dev) /* PCI Configuration Registers for AHBPCI */ devad = setup_bus_address(dev, PCI_BDF(0, 0, 0), 0); writel(priv->cfg_base + 0x800, devad + PCI_BASE_ADDRESS_0); - writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1); + writel(CFG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1); writel(0xf0000000, devad + PCI_BASE_ADDRESS_2); writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_PARITY | PCI_COMMAND_SERR, diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c index d514c040344..c1be56ce7a0 100644 --- a/drivers/pci/pci_sh7751.c +++ b/drivers/pci/pci_sh7751.c @@ -158,9 +158,9 @@ static int sh7751_pci_probe(struct udevice *dev) /* Set up target memory mappings (for external DMA access) */ /* Map both P0 and P2 range to Area 3 RAM for ease of use */ - p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0); - p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0); - p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5); + p4_out(CFG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0); + p4_out(CFG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0); + p4_out(CFG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5); p4_out(0, SH7751_PCILSR1); p4_out(0, SH7751_PCILAR1); diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index 99891dce61d..a0b82c78321 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -459,9 +459,9 @@ static void pcie_dw_set_host_bars(const void *regs_base) } /* Set the BAR base and size towards DDR */ - bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf; + bar0 = CFG_SYS_SDRAM_BASE & ~0xf; bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32; - writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0); + writel(CFG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0); reg = ((size >> 20) - 1) << 12; writel(size, regs_base + RESIZABLE_BAR_CTL0); diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index a52774179e2..b7f692f6450 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -14,11 +14,11 @@ #include #ifndef CFG_SYS_PCI_MEMORY_BUS -#define CFG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_PCI_MEMORY_BUS CFG_SYS_SDRAM_BASE #endif #ifndef CFG_SYS_PCI_MEMORY_PHYS -#define CFG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_PCI_MEMORY_PHYS CFG_SYS_SDRAM_BASE #endif #ifndef CFG_SYS_PCI_MEMORY_SIZE -- cgit v1.2.3