From 9675d9202780fd996c00ad34f0360c89376205b3 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 21 Jun 2023 23:11:46 +0800 Subject: riscv: Rename SiFive CLINT to RISC-V ALINT As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng Reviewed-by: Rick Chen --- drivers/timer/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/timer/Makefile') diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index cdc20f5e946..1ca74805fd9 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -25,7 +25,7 @@ obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o obj-$(CONFIG_SP804_TIMER) += sp804_timer.o -obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o +obj-$(CONFIG_$(SPL_)RISCV_ACLINT) += riscv_aclint_timer.o obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o obj-$(CONFIG_STM32_TIMER) += stm32_timer.o obj-$(CONFIG_TEGRA_TIMER) += tegra-timer.o -- cgit v1.3.1