From 77dd7c6854f3bd8ddc422f0cb1953071fe00dc6c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 6 Dec 2019 21:41:49 -0700 Subject: x86: timer: use a timer base of 0 On x86 platforms the timer is reset to 0 when the SoC is reset. Having this as the timer base is useful since it provides an indication of how long it takes before U-Boot is running. When U-Boot sets the timer base to something else, time is lost and we no-longer have an accurate account of the time since reset. This particularly affects bootstage. Change the default to not read the timer base, leaving it at 0. Add an option for when U-Boot is the secondary bootloader. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/timer/Kconfig | 14 ++++++++++++++ drivers/timer/tsc_timer.c | 3 ++- 2 files changed, 16 insertions(+), 1 deletion(-) (limited to 'drivers/timer') diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 5f4bc6edb67..41f97551337 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -174,6 +174,20 @@ config X86_TSC_TIMER help Select this to enable Time-Stamp Counter (TSC) timer for x86. +config X86_TSC_READ_BASE + bool "Read the TSC timer base on start-up" + depends on X86_TSC_TIMER + help + On x86 platforms the TSC timer tick starts at the value 0 on reset. + This it makes no sense to read the timer on boot and use that as the + base, since we will miss some time taken to load U-Boot, etc. This + delay is controlled by the SoC and we cannot reduce it, but for + bootstage we want to record the time since reset as accurately as + possible. + + The only exception is when U-Boot is used as a secondary bootloader, + where this option should be enabled. + config MTK_TIMER bool "MediaTek timer support" depends on TIMER diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index 0df551f94cc..813817f4672 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -397,7 +397,8 @@ static void tsc_timer_ensure_setup(bool early) { if (gd->arch.tsc_inited) return; - gd->arch.tsc_base = rdtsc(); + if (IS_ENABLED(CONFIG_X86_TSC_READ_BASE)) + gd->arch.tsc_base = rdtsc(); if (!gd->arch.clock_rate) { unsigned long fast_calibrate; -- cgit v1.3.1 From 642e8487ec629b43b1c5caf846098bfc952be5c0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 6 Dec 2019 21:41:50 -0700 Subject: x86: timer: Reduce timer code size in TPL on Intel CPUs Most of the timer-calibration methods are not needed on recent Intel CPUs and just increase code size. Add an option to use the known-good way to get the clock frequency in TPL. Size reduction is about 700 bytes. Note that version 1 of this commit caused bootstage to crash since the CPU was not identified. This is corrected by changes previously applied to make sure that the CPU is identified before spl_init() is called, such as 39146a2e0b x86: Move CPU init to before spl_init() Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/timer/Kconfig | 9 +++++++++ drivers/timer/tsc_timer.c | 7 +++++-- 2 files changed, 14 insertions(+), 2 deletions(-) (limited to 'drivers/timer') diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 41f97551337..96cc49273f4 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -188,6 +188,15 @@ config X86_TSC_READ_BASE The only exception is when U-Boot is used as a secondary bootloader, where this option should be enabled. +config TPL_X86_TSC_TIMER_NATIVE + bool "x86 TSC timer uses native calibration" + depends on TPL && X86_TSC_TIMER + help + Selects native timer calibration for TPL and don't include the other + methods in the code. This helps to reduce code size in TPL and works + on fairly modern Intel chips. Code-size reductions is about 700 + bytes. + config MTK_TIMER bool "MediaTek timer support" depends on TIMER diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index 813817f4672..43cb2d820e8 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -50,8 +50,7 @@ static unsigned long native_calibrate_tsc(void) return 0; crystal_freq = tsc_info.ecx / 1000; - - if (!crystal_freq) { + if (!CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE) && !crystal_freq) { switch (gd->arch.x86_model) { case INTEL_FAM6_SKYLAKE_MOBILE: case INTEL_FAM6_SKYLAKE_DESKTOP: @@ -407,6 +406,10 @@ static void tsc_timer_ensure_setup(bool early) if (fast_calibrate) goto done; + /* Reduce code size by dropping other methods */ + if (CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE)) + panic("no timer"); + fast_calibrate = cpu_mhz_from_cpuid(); if (fast_calibrate) goto done; -- cgit v1.3.1