From 5764acb2617658af76c25285685e791ce6d0b051 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 21 Jun 2023 23:11:44 +0800 Subject: riscv: timer: Update the sifive clint timer driver to support aclint This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform. The RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, however the device tree binding is a new one. This change updates the sifive clint timer driver to support ACLINT mtimer device, using a per-driver data field to hold the mtimer offset to the base address encoded in the mtimer node. [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc Signed-off-by: Bin Meng Reviewed-by: Rick Chen --- drivers/timer/sifive_clint_timer.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) (limited to 'drivers/timer') diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/sifive_clint_timer.c index 939b99d937d..be45f17ddfb 100644 --- a/drivers/timer/sifive_clint_timer.c +++ b/drivers/timer/sifive_clint_timer.c @@ -12,12 +12,16 @@ #include #include +#define CLINT_MTIME_OFFSET 0xbff8 +#define ACLINT_MTIME_OFFSET 0 + /* mtime register */ -#define MTIME_REG(base) ((ulong)(base) + 0xbff8) +#define MTIME_REG(base, offset) ((ulong)(base) + (offset)) static u64 notrace sifive_clint_get_count(struct udevice *dev) { - return readq((void __iomem *)MTIME_REG(dev_get_priv(dev))); + return readq((void __iomem *)MTIME_REG(dev_get_priv(dev), + dev_get_driver_data(dev))); } #if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY) @@ -35,7 +39,8 @@ unsigned long notrace timer_early_get_rate(void) */ u64 notrace timer_early_get_count(void) { - return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE)); + return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE, + RISCV_MMODE_TIMEROFF)); } #endif @@ -53,8 +58,9 @@ static int sifive_clint_probe(struct udevice *dev) } static const struct udevice_id sifive_clint_ids[] = { - { .compatible = "riscv,clint0" }, - { .compatible = "sifive,clint0" }, + { .compatible = "riscv,clint0", .data = CLINT_MTIME_OFFSET }, + { .compatible = "sifive,clint0", .data = CLINT_MTIME_OFFSET }, + { .compatible = "riscv,aclint-mtimer", .data = ACLINT_MTIME_OFFSET }, { } }; -- cgit v1.2.3 From 9675d9202780fd996c00ad34f0360c89376205b3 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 21 Jun 2023 23:11:46 +0800 Subject: riscv: Rename SiFive CLINT to RISC-V ALINT As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng Reviewed-by: Rick Chen --- drivers/timer/Makefile | 2 +- drivers/timer/riscv_aclint_timer.c | 74 ++++++++++++++++++++++++++++++++++++++ drivers/timer/sifive_clint_timer.c | 74 -------------------------------------- 3 files changed, 75 insertions(+), 75 deletions(-) create mode 100644 drivers/timer/riscv_aclint_timer.c delete mode 100644 drivers/timer/sifive_clint_timer.c (limited to 'drivers/timer') diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index cdc20f5e946..1ca74805fd9 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -25,7 +25,7 @@ obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o obj-$(CONFIG_SP804_TIMER) += sp804_timer.o -obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o +obj-$(CONFIG_$(SPL_)RISCV_ACLINT) += riscv_aclint_timer.o obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o obj-$(CONFIG_STM32_TIMER) += stm32_timer.o obj-$(CONFIG_TEGRA_TIMER) += tegra-timer.o diff --git a/drivers/timer/riscv_aclint_timer.c b/drivers/timer/riscv_aclint_timer.c new file mode 100644 index 00000000000..e29d527c8d7 --- /dev/null +++ b/drivers/timer/riscv_aclint_timer.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020, Sean Anderson + * Copyright (C) 2018, Bin Meng + */ + +#include +#include +#include +#include +#include +#include +#include + +#define CLINT_MTIME_OFFSET 0xbff8 +#define ACLINT_MTIME_OFFSET 0 + +/* mtime register */ +#define MTIME_REG(base, offset) ((ulong)(base) + (offset)) + +static u64 notrace riscv_aclint_timer_get_count(struct udevice *dev) +{ + return readq((void __iomem *)MTIME_REG(dev_get_priv(dev), + dev_get_driver_data(dev))); +} + +#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY) +/** + * timer_early_get_rate() - Get the timer rate before driver model + */ +unsigned long notrace timer_early_get_rate(void) +{ + return RISCV_MMODE_TIMER_FREQ; +} + +/** + * timer_early_get_count() - Get the timer count before driver model + * + */ +u64 notrace timer_early_get_count(void) +{ + return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE, + RISCV_MMODE_TIMEROFF)); +} +#endif + +static const struct timer_ops riscv_aclint_timer_ops = { + .get_count = riscv_aclint_timer_get_count, +}; + +static int riscv_aclint_timer_probe(struct udevice *dev) +{ + dev_set_priv(dev, dev_read_addr_ptr(dev)); + if (!dev_get_priv(dev)) + return -EINVAL; + + return timer_timebase_fallback(dev); +} + +static const struct udevice_id riscv_aclint_timer_ids[] = { + { .compatible = "riscv,clint0", .data = CLINT_MTIME_OFFSET }, + { .compatible = "sifive,clint0", .data = CLINT_MTIME_OFFSET }, + { .compatible = "riscv,aclint-mtimer", .data = ACLINT_MTIME_OFFSET }, + { } +}; + +U_BOOT_DRIVER(riscv_aclint_timer) = { + .name = "riscv_aclint_timer", + .id = UCLASS_TIMER, + .of_match = riscv_aclint_timer_ids, + .probe = riscv_aclint_timer_probe, + .ops = &riscv_aclint_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/sifive_clint_timer.c deleted file mode 100644 index be45f17ddfb..00000000000 --- a/drivers/timer/sifive_clint_timer.c +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020, Sean Anderson - * Copyright (C) 2018, Bin Meng - */ - -#include -#include -#include -#include -#include -#include -#include - -#define CLINT_MTIME_OFFSET 0xbff8 -#define ACLINT_MTIME_OFFSET 0 - -/* mtime register */ -#define MTIME_REG(base, offset) ((ulong)(base) + (offset)) - -static u64 notrace sifive_clint_get_count(struct udevice *dev) -{ - return readq((void __iomem *)MTIME_REG(dev_get_priv(dev), - dev_get_driver_data(dev))); -} - -#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY) -/** - * timer_early_get_rate() - Get the timer rate before driver model - */ -unsigned long notrace timer_early_get_rate(void) -{ - return RISCV_MMODE_TIMER_FREQ; -} - -/** - * timer_early_get_count() - Get the timer count before driver model - * - */ -u64 notrace timer_early_get_count(void) -{ - return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE, - RISCV_MMODE_TIMEROFF)); -} -#endif - -static const struct timer_ops sifive_clint_ops = { - .get_count = sifive_clint_get_count, -}; - -static int sifive_clint_probe(struct udevice *dev) -{ - dev_set_priv(dev, dev_read_addr_ptr(dev)); - if (!dev_get_priv(dev)) - return -EINVAL; - - return timer_timebase_fallback(dev); -} - -static const struct udevice_id sifive_clint_ids[] = { - { .compatible = "riscv,clint0", .data = CLINT_MTIME_OFFSET }, - { .compatible = "sifive,clint0", .data = CLINT_MTIME_OFFSET }, - { .compatible = "riscv,aclint-mtimer", .data = ACLINT_MTIME_OFFSET }, - { } -}; - -U_BOOT_DRIVER(sifive_clint) = { - .name = "sifive_clint", - .id = UCLASS_TIMER, - .of_match = sifive_clint_ids, - .probe = sifive_clint_probe, - .ops = &sifive_clint_ops, - .flags = DM_FLAG_PRE_RELOC, -}; -- cgit v1.2.3