From 41d62e2f275c44fd47bcd6d856608528006b082b Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Mon, 21 Feb 2022 09:22:39 +0100 Subject: sandbox: scmi: test against a single scmi agent As per DT bindings since Linux kernel v5.14, the device tree can define only 1 SCMI agent node that is named scmi [1]. As a consequence, change implementation of the SCMI driver test through sandbox architecture to reflect that. This change updates sandbox test DT and sandbox SCMI driver accordingly since all these are impacted. Cc: Simon Glass Reviewed-by: Patrick Delaunay Signed-off-by: Etienne Carriere --- drivers/firmware/scmi/sandbox-scmi_agent.c | 169 +++++++++------------------ drivers/firmware/scmi/sandbox-scmi_devices.c | 4 +- 2 files changed, 54 insertions(+), 119 deletions(-) (limited to 'drivers') diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c b/drivers/firmware/scmi/sandbox-scmi_agent.c index 4b968205c2f..51474b57608 100644 --- a/drivers/firmware/scmi/sandbox-scmi_agent.c +++ b/drivers/firmware/scmi/sandbox-scmi_agent.c @@ -19,51 +19,35 @@ * The sandbox SCMI agent driver simulates to some extend a SCMI message * processing. It simulates few of the SCMI services for some of the * SCMI protocols embedded in U-Boot. Currently: - * - SCMI clock protocol: emulate 2 agents each exposing few clocks - * - SCMI reset protocol: emulate 1 agent exposing a reset controller - * - SCMI voltage domain protocol: emulate 1 agent exposing 2 regulators + * - SCMI clock protocol emulates an agent exposing 2 clocks + * - SCMI reset protocol emulates an agent exposing a reset controller + * - SCMI voltage domain protocol emulates an agent exposing 2 regulators * - * Agent #0 simulates 2 clocks, 1 reset domain and 1 voltage domain. - * See IDs in scmi0_clk[]/scmi0_reset[] and "sandbox-scmi-agent@0" in test.dts. - * - * Agent #1 simulates 1 clock. - * See IDs in scmi1_clk[] and "sandbox-scmi-agent@1" in test.dts. + * As per DT bindings, the device node name shall be scmi. * * All clocks and regulators are default disabled and reset controller down. * - * This Driver exports sandbox_scmi_service_ctx() for the test sequence to + * This driver exports sandbox_scmi_service_ctx() for the test sequence to * get the state of the simulated services (clock state, rate, ...) and * check back-end device state reflects the request send through the * various uclass devices, as clocks and reset controllers. */ -#define SANDBOX_SCMI_AGENT_COUNT 2 - -static struct sandbox_scmi_clk scmi0_clk[] = { +static struct sandbox_scmi_clk scmi_clk[] = { { .id = 7, .rate = 1000 }, { .id = 3, .rate = 333 }, }; -static struct sandbox_scmi_reset scmi0_reset[] = { +static struct sandbox_scmi_reset scmi_reset[] = { { .id = 3 }, }; -static struct sandbox_scmi_voltd scmi0_voltd[] = { +static struct sandbox_scmi_voltd scmi_voltd[] = { { .id = 0, .voltage_uv = 3300000 }, { .id = 1, .voltage_uv = 1800000 }, }; -static struct sandbox_scmi_clk scmi1_clk[] = { - { .id = 1, .rate = 44 }, -}; - -/* The list saves to simulted end devices references for test purpose */ -struct sandbox_scmi_agent *sandbox_scmi_agent_list[SANDBOX_SCMI_AGENT_COUNT]; - -static struct sandbox_scmi_service sandbox_scmi_service_state = { - .agent = sandbox_scmi_agent_list, - .agent_count = SANDBOX_SCMI_AGENT_COUNT, -}; +static struct sandbox_scmi_service sandbox_scmi_service_state; struct sandbox_scmi_service *sandbox_scmi_service_ctx(void) { @@ -74,9 +58,8 @@ static void debug_print_agent_state(struct udevice *dev, char *str) { struct sandbox_scmi_agent *agent = dev_get_priv(dev); - dev_dbg(dev, "Dump sandbox_scmi_agent %u: %s\n", agent->idx, str); - dev_dbg(dev, " scmi%u_clk (%zu): %d/%ld, %d/%ld, %d/%ld, ...\n", - agent->idx, + dev_dbg(dev, "Dump sandbox_scmi_agent: %s\n", str); + dev_dbg(dev, " scmi_clk (%zu): %d/%ld, %d/%ld, %d/%ld, ...\n", agent->clk_count, agent->clk_count ? agent->clk[0].enabled : -1, agent->clk_count ? agent->clk[0].rate : -1, @@ -84,13 +67,11 @@ static void debug_print_agent_state(struct udevice *dev, char *str) agent->clk_count > 1 ? agent->clk[1].rate : -1, agent->clk_count > 2 ? agent->clk[2].enabled : -1, agent->clk_count > 2 ? agent->clk[2].rate : -1); - dev_dbg(dev, " scmi%u_reset (%zu): %d, %d, ...\n", - agent->idx, + dev_dbg(dev, " scmi_reset (%zu): %d, %d, ...\n", agent->reset_count, agent->reset_count ? agent->reset[0].asserted : -1, agent->reset_count > 1 ? agent->reset[1].asserted : -1); - dev_dbg(dev, " scmi%u_voltd (%zu): %u/%d, %u/%d, ...\n", - agent->idx, + dev_dbg(dev, " scmi_voltd (%zu): %u/%d, %u/%d, ...\n", agent->voltd_count, agent->voltd_count ? agent->voltd[0].enabled : -1, agent->voltd_count ? agent->voltd[0].voltage_uv : -1, @@ -98,56 +79,35 @@ static void debug_print_agent_state(struct udevice *dev, char *str) agent->voltd_count ? agent->voltd[1].voltage_uv : -1); }; -static struct sandbox_scmi_clk *get_scmi_clk_state(uint agent_id, uint clock_id) +static struct sandbox_scmi_clk *get_scmi_clk_state(uint clock_id) { - struct sandbox_scmi_clk *target = NULL; - size_t target_count = 0; size_t n; - switch (agent_id) { - case 0: - target = scmi0_clk; - target_count = ARRAY_SIZE(scmi0_clk); - break; - case 1: - target = scmi1_clk; - target_count = ARRAY_SIZE(scmi1_clk); - break; - default: - return NULL; - } - - for (n = 0; n < target_count; n++) - if (target[n].id == clock_id) - return target + n; + for (n = 0; n < ARRAY_SIZE(scmi_clk); n++) + if (scmi_clk[n].id == clock_id) + return scmi_clk + n; return NULL; } -static struct sandbox_scmi_reset *get_scmi_reset_state(uint agent_id, - uint reset_id) +static struct sandbox_scmi_reset *get_scmi_reset_state(uint reset_id) { size_t n; - if (agent_id == 0) { - for (n = 0; n < ARRAY_SIZE(scmi0_reset); n++) - if (scmi0_reset[n].id == reset_id) - return scmi0_reset + n; - } + for (n = 0; n < ARRAY_SIZE(scmi_reset); n++) + if (scmi_reset[n].id == reset_id) + return scmi_reset + n; return NULL; } -static struct sandbox_scmi_voltd *get_scmi_voltd_state(uint agent_id, - uint domain_id) +static struct sandbox_scmi_voltd *get_scmi_voltd_state(uint domain_id) { size_t n; - if (agent_id == 0) { - for (n = 0; n < ARRAY_SIZE(scmi0_voltd); n++) - if (scmi0_voltd[n].id == domain_id) - return scmi0_voltd + n; - } + for (n = 0; n < ARRAY_SIZE(scmi_voltd); n++) + if (scmi_voltd[n].id == domain_id) + return scmi_voltd + n; return NULL; } @@ -159,7 +119,6 @@ static struct sandbox_scmi_voltd *get_scmi_voltd_state(uint agent_id, static int sandbox_scmi_clock_rate_set(struct udevice *dev, struct scmi_msg *msg) { - struct sandbox_scmi_agent *agent = dev_get_priv(dev); struct scmi_clk_rate_set_in *in = NULL; struct scmi_clk_rate_set_out *out = NULL; struct sandbox_scmi_clk *clk_state = NULL; @@ -171,7 +130,7 @@ static int sandbox_scmi_clock_rate_set(struct udevice *dev, in = (struct scmi_clk_rate_set_in *)msg->in_msg; out = (struct scmi_clk_rate_set_out *)msg->out_msg; - clk_state = get_scmi_clk_state(agent->idx, in->clock_id); + clk_state = get_scmi_clk_state(in->clock_id); if (!clk_state) { dev_err(dev, "Unexpected clock ID %u\n", in->clock_id); @@ -190,7 +149,6 @@ static int sandbox_scmi_clock_rate_set(struct udevice *dev, static int sandbox_scmi_clock_rate_get(struct udevice *dev, struct scmi_msg *msg) { - struct sandbox_scmi_agent *agent = dev_get_priv(dev); struct scmi_clk_rate_get_in *in = NULL; struct scmi_clk_rate_get_out *out = NULL; struct sandbox_scmi_clk *clk_state = NULL; @@ -202,7 +160,7 @@ static int sandbox_scmi_clock_rate_get(struct udevice *dev, in = (struct scmi_clk_rate_get_in *)msg->in_msg; out = (struct scmi_clk_rate_get_out *)msg->out_msg; - clk_state = get_scmi_clk_state(agent->idx, in->clock_id); + clk_state = get_scmi_clk_state(in->clock_id); if (!clk_state) { dev_err(dev, "Unexpected clock ID %u\n", in->clock_id); @@ -219,7 +177,6 @@ static int sandbox_scmi_clock_rate_get(struct udevice *dev, static int sandbox_scmi_clock_gate(struct udevice *dev, struct scmi_msg *msg) { - struct sandbox_scmi_agent *agent = dev_get_priv(dev); struct scmi_clk_state_in *in = NULL; struct scmi_clk_state_out *out = NULL; struct sandbox_scmi_clk *clk_state = NULL; @@ -231,7 +188,7 @@ static int sandbox_scmi_clock_gate(struct udevice *dev, struct scmi_msg *msg) in = (struct scmi_clk_state_in *)msg->in_msg; out = (struct scmi_clk_state_out *)msg->out_msg; - clk_state = get_scmi_clk_state(agent->idx, in->clock_id); + clk_state = get_scmi_clk_state(in->clock_id); if (!clk_state) { dev_err(dev, "Unexpected clock ID %u\n", in->clock_id); @@ -249,7 +206,6 @@ static int sandbox_scmi_clock_gate(struct udevice *dev, struct scmi_msg *msg) static int sandbox_scmi_rd_attribs(struct udevice *dev, struct scmi_msg *msg) { - struct sandbox_scmi_agent *agent = dev_get_priv(dev); struct scmi_rd_attr_in *in = NULL; struct scmi_rd_attr_out *out = NULL; struct sandbox_scmi_reset *reset_state = NULL; @@ -261,7 +217,7 @@ static int sandbox_scmi_rd_attribs(struct udevice *dev, struct scmi_msg *msg) in = (struct scmi_rd_attr_in *)msg->in_msg; out = (struct scmi_rd_attr_out *)msg->out_msg; - reset_state = get_scmi_reset_state(agent->idx, in->domain_id); + reset_state = get_scmi_reset_state(in->domain_id); if (!reset_state) { dev_err(dev, "Unexpected reset domain ID %u\n", in->domain_id); @@ -278,7 +234,6 @@ static int sandbox_scmi_rd_attribs(struct udevice *dev, struct scmi_msg *msg) static int sandbox_scmi_rd_reset(struct udevice *dev, struct scmi_msg *msg) { - struct sandbox_scmi_agent *agent = dev_get_priv(dev); struct scmi_rd_reset_in *in = NULL; struct scmi_rd_reset_out *out = NULL; struct sandbox_scmi_reset *reset_state = NULL; @@ -290,7 +245,7 @@ static int sandbox_scmi_rd_reset(struct udevice *dev, struct scmi_msg *msg) in = (struct scmi_rd_reset_in *)msg->in_msg; out = (struct scmi_rd_reset_out *)msg->out_msg; - reset_state = get_scmi_reset_state(agent->idx, in->domain_id); + reset_state = get_scmi_reset_state(in->domain_id); if (!reset_state) { dev_err(dev, "Unexpected reset domain ID %u\n", in->domain_id); @@ -321,7 +276,6 @@ static int sandbox_scmi_rd_reset(struct udevice *dev, struct scmi_msg *msg) static int sandbox_scmi_voltd_attribs(struct udevice *dev, struct scmi_msg *msg) { - struct sandbox_scmi_agent *agent = dev_get_priv(dev); struct scmi_voltd_attr_in *in = NULL; struct scmi_voltd_attr_out *out = NULL; struct sandbox_scmi_voltd *voltd_state = NULL; @@ -333,7 +287,7 @@ static int sandbox_scmi_voltd_attribs(struct udevice *dev, struct scmi_msg *msg) in = (struct scmi_voltd_attr_in *)msg->in_msg; out = (struct scmi_voltd_attr_out *)msg->out_msg; - voltd_state = get_scmi_voltd_state(agent->idx, in->domain_id); + voltd_state = get_scmi_voltd_state(in->domain_id); if (!voltd_state) { dev_err(dev, "Unexpected domain ID %u\n", in->domain_id); @@ -351,7 +305,6 @@ static int sandbox_scmi_voltd_attribs(struct udevice *dev, struct scmi_msg *msg) static int sandbox_scmi_voltd_config_set(struct udevice *dev, struct scmi_msg *msg) { - struct sandbox_scmi_agent *agent = dev_get_priv(dev); struct scmi_voltd_config_set_in *in = NULL; struct scmi_voltd_config_set_out *out = NULL; struct sandbox_scmi_voltd *voltd_state = NULL; @@ -363,7 +316,7 @@ static int sandbox_scmi_voltd_config_set(struct udevice *dev, in = (struct scmi_voltd_config_set_in *)msg->in_msg; out = (struct scmi_voltd_config_set_out *)msg->out_msg; - voltd_state = get_scmi_voltd_state(agent->idx, in->domain_id); + voltd_state = get_scmi_voltd_state(in->domain_id); if (!voltd_state) { dev_err(dev, "Unexpected domain ID %u\n", in->domain_id); @@ -388,7 +341,6 @@ static int sandbox_scmi_voltd_config_set(struct udevice *dev, static int sandbox_scmi_voltd_config_get(struct udevice *dev, struct scmi_msg *msg) { - struct sandbox_scmi_agent *agent = dev_get_priv(dev); struct scmi_voltd_config_get_in *in = NULL; struct scmi_voltd_config_get_out *out = NULL; struct sandbox_scmi_voltd *voltd_state = NULL; @@ -400,7 +352,7 @@ static int sandbox_scmi_voltd_config_get(struct udevice *dev, in = (struct scmi_voltd_config_get_in *)msg->in_msg; out = (struct scmi_voltd_config_get_out *)msg->out_msg; - voltd_state = get_scmi_voltd_state(agent->idx, in->domain_id); + voltd_state = get_scmi_voltd_state(in->domain_id); if (!voltd_state) { dev_err(dev, "Unexpected domain ID %u\n", in->domain_id); @@ -420,7 +372,6 @@ static int sandbox_scmi_voltd_config_get(struct udevice *dev, static int sandbox_scmi_voltd_level_set(struct udevice *dev, struct scmi_msg *msg) { - struct sandbox_scmi_agent *agent = dev_get_priv(dev); struct scmi_voltd_level_set_in *in = NULL; struct scmi_voltd_level_set_out *out = NULL; struct sandbox_scmi_voltd *voltd_state = NULL; @@ -432,7 +383,7 @@ static int sandbox_scmi_voltd_level_set(struct udevice *dev, in = (struct scmi_voltd_level_set_in *)msg->in_msg; out = (struct scmi_voltd_level_set_out *)msg->out_msg; - voltd_state = get_scmi_voltd_state(agent->idx, in->domain_id); + voltd_state = get_scmi_voltd_state(in->domain_id); if (!voltd_state) { dev_err(dev, "Unexpected domain ID %u\n", in->domain_id); @@ -448,7 +399,6 @@ static int sandbox_scmi_voltd_level_set(struct udevice *dev, static int sandbox_scmi_voltd_level_get(struct udevice *dev, struct scmi_msg *msg) { - struct sandbox_scmi_agent *agent = dev_get_priv(dev); struct scmi_voltd_level_get_in *in = NULL; struct scmi_voltd_level_get_out *out = NULL; struct sandbox_scmi_voltd *voltd_state = NULL; @@ -460,7 +410,7 @@ static int sandbox_scmi_voltd_level_get(struct udevice *dev, in = (struct scmi_voltd_level_get_in *)msg->in_msg; out = (struct scmi_voltd_level_get_out *)msg->out_msg; - voltd_state = get_scmi_voltd_state(agent->idx, in->domain_id); + voltd_state = get_scmi_voltd_state(in->domain_id); if (!voltd_state) { dev_err(dev, "Unexpected domain ID %u\n", in->domain_id); @@ -541,52 +491,37 @@ static int sandbox_scmi_test_remove(struct udevice *dev) { struct sandbox_scmi_agent *agent = dev_get_priv(dev); + if (agent != sandbox_scmi_service_ctx()->agent) + return -EINVAL; + debug_print_agent_state(dev, "removed"); /* We only need to dereference the agent in the context */ - sandbox_scmi_service_ctx()->agent[agent->idx] = NULL; + sandbox_scmi_service_ctx()->agent = NULL; return 0; } static int sandbox_scmi_test_probe(struct udevice *dev) { - static const char basename[] = "sandbox-scmi-agent@"; struct sandbox_scmi_agent *agent = dev_get_priv(dev); - const size_t basename_size = sizeof(basename) - 1; - - if (strncmp(basename, dev->name, basename_size)) - return -ENOENT; - - switch (dev->name[basename_size]) { - case '0': - *agent = (struct sandbox_scmi_agent){ - .idx = 0, - .clk = scmi0_clk, - .clk_count = ARRAY_SIZE(scmi0_clk), - .reset = scmi0_reset, - .reset_count = ARRAY_SIZE(scmi0_reset), - .voltd = scmi0_voltd, - .voltd_count = ARRAY_SIZE(scmi0_voltd), - }; - break; - case '1': - *agent = (struct sandbox_scmi_agent){ - .idx = 1, - .clk = scmi1_clk, - .clk_count = ARRAY_SIZE(scmi1_clk), - }; - break; - default: - dev_err(dev, "%s(): Unexpected agent ID %s\n", - __func__, dev->name + basename_size); - return -ENOENT; - } + + if (sandbox_scmi_service_ctx()->agent) + return -EINVAL; + + *agent = (struct sandbox_scmi_agent){ + .clk = scmi_clk, + .clk_count = ARRAY_SIZE(scmi_clk), + .reset = scmi_reset, + .reset_count = ARRAY_SIZE(scmi_reset), + .voltd = scmi_voltd, + .voltd_count = ARRAY_SIZE(scmi_voltd), + }; debug_print_agent_state(dev, "probed"); /* Save reference for tests purpose */ - sandbox_scmi_service_ctx()->agent[agent->idx] = agent; + sandbox_scmi_service_ctx()->agent = agent; return 0; }; diff --git a/drivers/firmware/scmi/sandbox-scmi_devices.c b/drivers/firmware/scmi/sandbox-scmi_devices.c index 66a67928817..9baeb469ec0 100644 --- a/drivers/firmware/scmi/sandbox-scmi_devices.c +++ b/drivers/firmware/scmi/sandbox-scmi_devices.c @@ -23,7 +23,7 @@ * and reset controllers. */ -#define SCMI_TEST_DEVICES_CLK_COUNT 3 +#define SCMI_TEST_DEVICES_CLK_COUNT 2 #define SCMI_TEST_DEVICES_RD_COUNT 1 #define SCMI_TEST_DEVICES_VOLTD_COUNT 2 @@ -135,7 +135,7 @@ U_BOOT_DRIVER(sandbox_scmi_devices) = { .name = "sandbox-scmi_devices", .id = UCLASS_MISC, .of_match = sandbox_scmi_devices_ids, - .priv_auto = sizeof(struct sandbox_scmi_device_priv), + .priv_auto = sizeof(struct sandbox_scmi_device_priv), .remove = sandbox_scmi_devices_remove, .probe = sandbox_scmi_devices_probe, }; -- cgit v1.3.1 From 6983710a31a0d6fb782eb0ea18b9325e4075f4c3 Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Mon, 21 Feb 2022 09:22:40 +0100 Subject: scmi: change parameter dev in devm_scmi_process_msg Changes devm_scmi_process_msg() first argument from target parent device to current SCMI device and lookup the SCMI agent device among SCMI device parents for find the SCMI agent operator needed for communication with the firmware. This change is needed in order to support CCF in clk_scmi driver unless what CCF will fail to find the right udevice related to exposed SCMI clocks. This patch allows to simplify the caller sequence, using SCMI device reference as parameter instead of knowing SCMI uclass topology. This change also adds some protection in case devm_scmi_process_msg() API function is called for an invalid device type. Cc: Lukasz Majewski Cc: Sean Anderson Cc: Jaehoon Chung Cc: Patrick Delaunay Reviewed-by: Patrick Delaunay Signed-off-by: Etienne Carriere --- drivers/clk/clk_scmi.c | 6 +++--- drivers/firmware/scmi/scmi_agent-uclass.c | 17 +++++++++++++++-- drivers/power/regulator/scmi_regulator.c | 10 +++++----- drivers/reset/reset-scmi.c | 4 ++-- include/scmi_agent.h | 2 +- 5 files changed, 26 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c index 9a0a6f66434..42fbab0d21b 100644 --- a/drivers/clk/clk_scmi.c +++ b/drivers/clk/clk_scmi.c @@ -24,7 +24,7 @@ static int scmi_clk_gate(struct clk *clk, int enable) in, out); int ret; - ret = devm_scmi_process_msg(clk->dev->parent, &msg); + ret = devm_scmi_process_msg(clk->dev, &msg); if (ret) return ret; @@ -52,7 +52,7 @@ static ulong scmi_clk_get_rate(struct clk *clk) in, out); int ret; - ret = devm_scmi_process_msg(clk->dev->parent, &msg); + ret = devm_scmi_process_msg(clk->dev, &msg); if (ret < 0) return ret; @@ -77,7 +77,7 @@ static ulong scmi_clk_set_rate(struct clk *clk, ulong rate) in, out); int ret; - ret = devm_scmi_process_msg(clk->dev->parent, &msg); + ret = devm_scmi_process_msg(clk->dev, &msg); if (ret < 0) return ret; diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c index 4f5870b4838..3819f2fa993 100644 --- a/drivers/firmware/scmi/scmi_agent-uclass.c +++ b/drivers/firmware/scmi/scmi_agent-uclass.c @@ -116,10 +116,23 @@ static const struct scmi_agent_ops *transport_dev_ops(struct udevice *dev) int devm_scmi_process_msg(struct udevice *dev, struct scmi_msg *msg) { - const struct scmi_agent_ops *ops = transport_dev_ops(dev); + const struct scmi_agent_ops *ops; + struct udevice *parent = dev; + + /* Find related SCMI agent device */ + do { + parent = dev_get_parent(parent); + } while (parent && device_get_uclass_id(parent) != UCLASS_SCMI_AGENT); + + if (!parent) { + dev_err(dev, "Invalid SCMI device, agent not found\n"); + return -ENODEV; + } + + ops = transport_dev_ops(parent); if (ops->process_msg) - return ops->process_msg(dev, msg); + return ops->process_msg(parent, msg); return -EPROTONOSUPPORT; } diff --git a/drivers/power/regulator/scmi_regulator.c b/drivers/power/regulator/scmi_regulator.c index 3ddeaf4adcb..2966bdcf830 100644 --- a/drivers/power/regulator/scmi_regulator.c +++ b/drivers/power/regulator/scmi_regulator.c @@ -38,7 +38,7 @@ static int scmi_voltd_set_enable(struct udevice *dev, bool enable) in, out); int ret; - ret = devm_scmi_process_msg(dev->parent->parent, &msg); + ret = devm_scmi_process_msg(dev, &msg); if (ret) return ret; @@ -61,7 +61,7 @@ static int scmi_voltd_get_enable(struct udevice *dev) in, out); int ret; - ret = devm_scmi_process_msg(dev->parent->parent, &msg); + ret = devm_scmi_process_msg(dev, &msg); if (ret < 0) return ret; @@ -85,7 +85,7 @@ static int scmi_voltd_set_voltage_level(struct udevice *dev, int uV) in, out); int ret; - ret = devm_scmi_process_msg(dev->parent->parent, &msg); + ret = devm_scmi_process_msg(dev, &msg); if (ret < 0) return ret; @@ -104,7 +104,7 @@ static int scmi_voltd_get_voltage_level(struct udevice *dev) in, out); int ret; - ret = devm_scmi_process_msg(dev->parent->parent, &msg); + ret = devm_scmi_process_msg(dev, &msg); if (ret < 0) return ret; @@ -147,7 +147,7 @@ static int scmi_regulator_probe(struct udevice *dev) /* Check voltage domain is known from SCMI server */ in.domain_id = pdata->domain_id; - ret = devm_scmi_process_msg(dev->parent->parent, &scmi_msg); + ret = devm_scmi_process_msg(dev, &scmi_msg); if (ret) { dev_err(dev, "Failed to query voltage domain %u: %d\n", pdata->domain_id, ret); diff --git a/drivers/reset/reset-scmi.c b/drivers/reset/reset-scmi.c index ca0135a4203..850cb188868 100644 --- a/drivers/reset/reset-scmi.c +++ b/drivers/reset/reset-scmi.c @@ -26,7 +26,7 @@ static int scmi_reset_set_level(struct reset_ctl *rst, bool assert_not_deassert) in, out); int ret; - ret = devm_scmi_process_msg(rst->dev->parent, &msg); + ret = devm_scmi_process_msg(rst->dev, &msg); if (ret) return ret; @@ -58,7 +58,7 @@ static int scmi_reset_request(struct reset_ctl *rst) * We don't really care about the attribute, just check * the reset domain exists. */ - ret = devm_scmi_process_msg(rst->dev->parent, &msg); + ret = devm_scmi_process_msg(rst->dev, &msg); if (ret) return ret; diff --git a/include/scmi_agent.h b/include/scmi_agent.h index 5015c06be99..18bcd48a9d4 100644 --- a/include/scmi_agent.h +++ b/include/scmi_agent.h @@ -51,7 +51,7 @@ struct scmi_msg { * Caller sets scmi_msg::out_msg_sz to the output message buffer size. * On return, scmi_msg::out_msg_sz stores the response payload size. * - * @dev: SCMI agent device + * @dev: SCMI device * @msg: Message structure reference * Return: 0 on success and a negative errno on failure */ -- cgit v1.3.1 From 10d3e5d20b284025cb6a734fcc7e1c8231ff56b6 Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Mon, 21 Feb 2022 09:22:41 +0100 Subject: firmware: scmi: fix sandbox and related tests for clock discovery Updates sandbox SCMI clock driver and tests since enabling CCF will mandate clock discovery that is all exposed SCMI clocks shall be discovered at initialization. For this reason, sandbox SCMI clock driver must emulate all clocks exposed by SCMI server, not only those effectively consumed by some other U-Boot devices. Therefore the sandbox SCMI test driver exposes 3 clocks (IDs 0, 1 and 2) and sandbox SCMI clock consumer driver gets 2 of them. Cc: Simon Glass Reviewed-by: Patrick Delaunay Signed-off-by: Etienne Carriere --- arch/sandbox/dts/test.dts | 2 +- arch/sandbox/include/asm/scmi_test.h | 1 - drivers/firmware/scmi/sandbox-scmi_agent.c | 12 +++++------- test/dm/scmi.c | 15 ++++++++++----- 4 files changed, 16 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 30874b038bb..3d206fdb3cf 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -1392,7 +1392,7 @@ sandbox_scmi { compatible = "sandbox,scmi-devices"; - clocks = <&clk_scmi 7>, <&clk_scmi 3>; + clocks = <&clk_scmi 2>, <&clk_scmi 0>; resets = <&reset_scmi 3>; regul0-supply = <®ul0_scmi>; regul1-supply = <®ul1_scmi>; diff --git a/arch/sandbox/include/asm/scmi_test.h b/arch/sandbox/include/asm/scmi_test.h index 054be5f14ef..c72ec1e1cb2 100644 --- a/arch/sandbox/include/asm/scmi_test.h +++ b/arch/sandbox/include/asm/scmi_test.h @@ -17,7 +17,6 @@ struct sandbox_scmi_service; * @rate: Clock rate in Hertz */ struct sandbox_scmi_clk { - uint id; bool enabled; ulong rate; }; diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c b/drivers/firmware/scmi/sandbox-scmi_agent.c index 51474b57608..fc717a8aeab 100644 --- a/drivers/firmware/scmi/sandbox-scmi_agent.c +++ b/drivers/firmware/scmi/sandbox-scmi_agent.c @@ -34,8 +34,9 @@ */ static struct sandbox_scmi_clk scmi_clk[] = { - { .id = 7, .rate = 1000 }, - { .id = 3, .rate = 333 }, + { .rate = 333 }, + { .rate = 200 }, + { .rate = 1000 }, }; static struct sandbox_scmi_reset scmi_reset[] = { @@ -81,11 +82,8 @@ static void debug_print_agent_state(struct udevice *dev, char *str) static struct sandbox_scmi_clk *get_scmi_clk_state(uint clock_id) { - size_t n; - - for (n = 0; n < ARRAY_SIZE(scmi_clk); n++) - if (scmi_clk[n].id == clock_id) - return scmi_clk + n; + if (clock_id < ARRAY_SIZE(scmi_clk)) + return scmi_clk + clock_id; return NULL; } diff --git a/test/dm/scmi.c b/test/dm/scmi.c index d576b5fd89d..795f207304a 100644 --- a/test/dm/scmi.c +++ b/test/dm/scmi.c @@ -52,7 +52,7 @@ static int ut_assert_scmi_state_postprobe(struct unit_test_state *uts, ut_assertnonnull(scmi_ctx); agent = scmi_ctx->agent; ut_assertnonnull(agent); - ut_asserteq(2, agent->clk_count); + ut_asserteq(3, agent->clk_count); ut_assertnonnull(agent->clk); ut_asserteq(1, agent->reset_count); ut_assertnonnull(agent->reset); @@ -125,14 +125,19 @@ static int dm_test_scmi_clocks(struct unit_test_state *uts) ut_assertnonnull(agent); /* Test SCMI clocks rate manipulation */ + ut_asserteq(333, agent->clk[0].rate); + ut_asserteq(200, agent->clk[1].rate); + ut_asserteq(1000, agent->clk[2].rate); + ut_asserteq(1000, clk_get_rate(&scmi_devices->clk[0])); ut_asserteq(333, clk_get_rate(&scmi_devices->clk[1])); ret_dev = clk_set_rate(&scmi_devices->clk[1], 1088); ut_assert(!ret_dev || ret_dev == 1088); - ut_asserteq(1000, agent->clk[0].rate); - ut_asserteq(1088, agent->clk[1].rate); + ut_asserteq(1088, agent->clk[0].rate); + ut_asserteq(200, agent->clk[1].rate); + ut_asserteq(1000, agent->clk[2].rate); ut_asserteq(1000, clk_get_rate(&scmi_devices->clk[0])); ut_asserteq(1088, clk_get_rate(&scmi_devices->clk[1])); @@ -148,8 +153,8 @@ static int dm_test_scmi_clocks(struct unit_test_state *uts) ut_asserteq(0, clk_enable(&scmi_devices->clk[1])); - ut_assert(!agent->clk[0].enabled); - ut_assert(agent->clk[1].enabled); + ut_assert(agent->clk[0].enabled); + ut_assert(!agent->clk[1].enabled); ut_assert(!agent->clk[2].enabled); ut_assertok(clk_disable(&scmi_devices->clk[1])); -- cgit v1.3.1 From 7c33f78983c344c46d46d857fd1d5e2b5b95ad40 Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Mon, 21 Feb 2022 09:22:42 +0100 Subject: clk: scmi: register scmi clocks with CCF Implements SCMI APIs to retrieve the number exposed SCMI clocks using SCMI_PROTOCOL_ATTRIBUTES messages and the names of the clocks using SCMI_CLOCK_ATTRIBUTES messages. This change updates sandbox SCMI clock test driver to manage these 2 new message IDs. Cc: Lukasz Majewski Cc: Sean Anderson Cc: Clement Leger Cc: Patrick Delaunay Reviewed-by: Patrick Delaunay Signed-off-by: Gabriel Fernandez Signed-off-by: Etienne Carriere --- drivers/clk/clk_scmi.c | 90 ++++++++++++++++++++++++++++++ drivers/firmware/scmi/sandbox-scmi_agent.c | 53 ++++++++++++++++++ include/scmi_protocols.h | 43 ++++++++++++++ 3 files changed, 186 insertions(+) (limited to 'drivers') diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c index 42fbab0d21b..57022685e23 100644 --- a/drivers/clk/clk_scmi.c +++ b/drivers/clk/clk_scmi.c @@ -11,6 +11,52 @@ #include #include #include +#include + +static int scmi_clk_get_num_clock(struct udevice *dev, size_t *num_clocks) +{ + struct scmi_clk_protocol_attr_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_CLOCK, + .message_id = SCMI_PROTOCOL_ATTRIBUTES, + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + + *num_clocks = out.attributes & SCMI_CLK_PROTO_ATTR_COUNT_MASK; + + return 0; +} + +static int scmi_clk_get_attibute(struct udevice *dev, int clkid, char **name) +{ + struct scmi_clk_attribute_in in = { + .clock_id = clkid, + }; + struct scmi_clk_attribute_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_CLOCK, + .message_id = SCMI_CLOCK_ATTRIBUTES, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + + *name = out.clock_name; + + return 0; +} static int scmi_clk_gate(struct clk *clk, int enable) { @@ -88,6 +134,49 @@ static ulong scmi_clk_set_rate(struct clk *clk, ulong rate) return scmi_clk_get_rate(clk); } +static int scmi_clk_probe(struct udevice *dev) +{ + struct clk *clk; + size_t num_clocks, i; + int ret; + + if (!CONFIG_IS_ENABLED(CLK_CCF)) + return 0; + + /* register CCF children: CLK UCLASS, no probed again */ + if (device_get_uclass_id(dev->parent) == UCLASS_CLK) + return 0; + + ret = scmi_clk_get_num_clock(dev, &num_clocks); + if (ret) + return ret; + + for (i = 0; i < num_clocks; i++) { + char *name; + + if (!scmi_clk_get_attibute(dev, i, &name)) { + char *clock_name = strdup(name); + + clk = kzalloc(sizeof(*clk), GFP_KERNEL); + if (!clk || !clock_name) + ret = -ENOMEM; + else + ret = clk_register(clk, dev->driver->name, + clock_name, dev->name); + + if (ret) { + free(clk); + free(clock_name); + return ret; + } + + clk_dm(i, clk); + } + } + + return 0; +} + static const struct clk_ops scmi_clk_ops = { .enable = scmi_clk_enable, .disable = scmi_clk_disable, @@ -99,4 +188,5 @@ U_BOOT_DRIVER(scmi_clock) = { .name = "scmi_clk", .id = UCLASS_CLK, .ops = &scmi_clk_ops, + .probe = &scmi_clk_probe, }; diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c b/drivers/firmware/scmi/sandbox-scmi_agent.c index fc717a8aeab..c555164d196 100644 --- a/drivers/firmware/scmi/sandbox-scmi_agent.c +++ b/drivers/firmware/scmi/sandbox-scmi_agent.c @@ -114,6 +114,55 @@ static struct sandbox_scmi_voltd *get_scmi_voltd_state(uint domain_id) * Sandbox SCMI agent ops */ +static int sandbox_scmi_clock_protocol_attribs(struct udevice *dev, + struct scmi_msg *msg) +{ + struct scmi_clk_protocol_attr_out *out = NULL; + + if (!msg->out_msg || msg->out_msg_sz < sizeof(*out)) + return -EINVAL; + + out = (struct scmi_clk_protocol_attr_out *)msg->out_msg; + out->attributes = ARRAY_SIZE(scmi_clk); + out->status = SCMI_SUCCESS; + + return 0; +} + +static int sandbox_scmi_clock_attribs(struct udevice *dev, struct scmi_msg *msg) +{ + struct scmi_clk_attribute_in *in = NULL; + struct scmi_clk_attribute_out *out = NULL; + struct sandbox_scmi_clk *clk_state = NULL; + int ret; + + if (!msg->in_msg || msg->in_msg_sz < sizeof(*in) || + !msg->out_msg || msg->out_msg_sz < sizeof(*out)) + return -EINVAL; + + in = (struct scmi_clk_attribute_in *)msg->in_msg; + out = (struct scmi_clk_attribute_out *)msg->out_msg; + + clk_state = get_scmi_clk_state(in->clock_id); + if (!clk_state) { + dev_err(dev, "Unexpected clock ID %u\n", in->clock_id); + + out->status = SCMI_NOT_FOUND; + } else { + memset(out, 0, sizeof(*out)); + + if (clk_state->enabled) + out->attributes = 1; + + ret = snprintf(out->clock_name, sizeof(out->clock_name), + "clk%u", in->clock_id); + assert(ret > 0 && ret < sizeof(out->clock_name)); + + out->status = SCMI_SUCCESS; + } + + return 0; +} static int sandbox_scmi_clock_rate_set(struct udevice *dev, struct scmi_msg *msg) { @@ -427,6 +476,10 @@ static int sandbox_scmi_test_process_msg(struct udevice *dev, switch (msg->protocol_id) { case SCMI_PROTOCOL_ID_CLOCK: switch (msg->message_id) { + case SCMI_PROTOCOL_ATTRIBUTES: + return sandbox_scmi_clock_protocol_attribs(dev, msg); + case SCMI_CLOCK_ATTRIBUTES: + return sandbox_scmi_clock_attribs(dev, msg); case SCMI_CLOCK_RATE_SET: return sandbox_scmi_clock_rate_set(dev, msg); case SCMI_CLOCK_RATE_GET: diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index ef26e721762..a220cb2a91a 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -40,22 +40,65 @@ enum scmi_status_code { SCMI_PROTOCOL_ERROR = -10, }; +/* + * Generic message IDs + */ +enum scmi_discovery_id { + SCMI_PROTOCOL_VERSION = 0x0, + SCMI_PROTOCOL_ATTRIBUTES = 0x1, + SCMI_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2, +}; + /* * SCMI Clock Protocol */ enum scmi_clock_message_id { + SCMI_CLOCK_ATTRIBUTES = 0x3, SCMI_CLOCK_RATE_SET = 0x5, SCMI_CLOCK_RATE_GET = 0x6, SCMI_CLOCK_CONFIG_SET = 0x7, }; +#define SCMI_CLK_PROTO_ATTR_COUNT_MASK GENMASK(15, 0) #define SCMI_CLK_RATE_ASYNC_NOTIFY BIT(0) #define SCMI_CLK_RATE_ASYNC_NORESP (BIT(0) | BIT(1)) #define SCMI_CLK_RATE_ROUND_DOWN 0 #define SCMI_CLK_RATE_ROUND_UP BIT(2) #define SCMI_CLK_RATE_ROUND_CLOSEST BIT(3) +#define SCMI_CLOCK_NAME_LENGTH_MAX 16 + +/** + * struct scmi_clk_get_nb_out - Response for SCMI_PROTOCOL_ATTRIBUTES command + * @status: SCMI command status + * @attributes: Attributes of the clock protocol, mainly number of clocks exposed + */ +struct scmi_clk_protocol_attr_out { + s32 status; + u32 attributes; +}; + +/** + * struct scmi_clk_attribute_in - Message payload for SCMI_CLOCK_ATTRIBUTES command + * @clock_id: SCMI clock ID + */ +struct scmi_clk_attribute_in { + u32 clock_id; +}; + +/** + * struct scmi_clk_get_nb_out - Response payload for SCMI_CLOCK_ATTRIBUTES command + * @status: SCMI command status + * @attributes: clock attributes + * @clock_name: name of the clock + */ +struct scmi_clk_attribute_out { + s32 status; + u32 attributes; + char clock_name[SCMI_CLOCK_NAME_LENGTH_MAX]; +}; + /** * struct scmi_clk_state_in - Message payload for CLOCK_CONFIG_SET command * @clock_id: SCMI clock ID -- cgit v1.3.1 From 3db7b2bb4c23939336c0fb9aaa8bc6795410f5af Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 23 Feb 2022 12:28:14 -0500 Subject: powerpc: Remove unused MPC8540/60ADS code Remove some code, primarily CPM2 related, that is now unused since the removal of MPC8540/60ADS. Fixes 3913191c8a6b ("powerpc: mpc8540ads: mpc8560ads: Drop support for MPC8540/60ADS") Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/powerpc/cpu/mpc85xx/Makefile | 2 - arch/powerpc/cpu/mpc85xx/commproc.c | 188 -------- arch/powerpc/cpu/mpc85xx/cpu.c | 4 - arch/powerpc/cpu/mpc85xx/cpu_init.c | 72 --- arch/powerpc/cpu/mpc85xx/fdt.c | 8 - arch/powerpc/cpu/mpc85xx/serial_scc.c | 262 ----------- arch/powerpc/cpu/mpc85xx/speed.c | 16 - arch/powerpc/include/asm/cpm_85xx.h | 824 --------------------------------- arch/powerpc/include/asm/global_data.h | 11 - arch/powerpc/include/asm/immap_85xx.h | 327 ------------- arch/powerpc/lib/bdinfo.c | 13 - arch/powerpc/lib/bootm.c | 6 - drivers/pci/pci_mpc85xx.c | 1 - include/asm-generic/u-boot.h | 6 - include/configs/MPC8540ADS.h | 303 ------------ include/configs/MPC8560ADS.h | 292 ------------ 16 files changed, 2335 deletions(-) delete mode 100644 arch/powerpc/cpu/mpc85xx/commproc.c delete mode 100644 arch/powerpc/cpu/mpc85xx/serial_scc.c delete mode 100644 arch/powerpc/include/asm/cpm_85xx.h delete mode 100644 include/configs/MPC8540ADS.h delete mode 100644 include/configs/MPC8560ADS.h (limited to 'drivers') diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 6f4ad1f9b76..c32cde04e16 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -27,7 +27,6 @@ obj-$(CONFIG_MP) += release.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o endif -obj-$(CONFIG_CPM2) += commproc.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_FSL_CORENET) += liodn.o @@ -49,7 +48,6 @@ obj-$(CONFIG_ARCH_T2080) += t2080_ids.o obj-$(CONFIG_QE) += qe_io.o -obj-$(CONFIG_CPM2) += serial_scc.o obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/commproc.c b/arch/powerpc/cpu/mpc85xx/commproc.c deleted file mode 100644 index 8e8427a08bb..00000000000 --- a/arch/powerpc/cpu/mpc85xx/commproc.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Adapted for Motorola MPC8560 chips - * Xianghua Xiao - * - * This file is based on "arch/powerpc/8260_io/commproc.c" - here is it's - * copyright notice: - * - * General Purpose functions for the global management of the - * 8220 Communication Processor Module. - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) - * 2.3.99 Updates - * Copyright (c) 2003 Motorola,Inc. - * - * In addition to the individual control of the communication - * channels, there are a few functions that globally affect the - * communication processor. - * - * Buffer descriptors must be allocated from the dual ported memory - * space. The allocator for that is here. When the communication - * process is reset, we reclaim the memory available. There is - * currently no deallocator for this memory. - */ -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * because we have stack and init data in dual port ram - * we must reduce the size - */ -#undef CPM_DATAONLY_SIZE -#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) - -void -m8560_cpm_reset(void) -{ - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; - volatile ulong count; - - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - - /* Reclaim the DP memory for our use. - */ - gd->arch.dp_alloc_base = CPM_DATAONLY_BASE; - gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE; - - /* - * Reset CPM - */ - cpm->im_cpm_cp.cpcr = CPM_CR_RST; - count = 0; - do { /* Spin until command processed */ - __asm__ __volatile__ ("eieio"); - } while ((cpm->im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000); -} - -/* Allocate some memory from the dual ported ram. - * To help protocols with object alignment restrictions, we do that - * if they ask. - */ -uint -m8560_cpm_dpalloc(uint size, uint align) -{ - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; - uint retloc; - uint align_mask, off; - uint savebase; - - align_mask = align - 1; - savebase = gd->arch.dp_alloc_base; - - off = gd->arch.dp_alloc_base & align_mask; - if (off != 0) - gd->arch.dp_alloc_base += (align - off); - - if ((off = size & align_mask) != 0) - size += align - off; - - if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) { - gd->arch.dp_alloc_base = savebase; - panic("m8560_cpm_dpalloc: ran out of dual port ram!"); - } - - retloc = gd->arch.dp_alloc_base; - gd->arch.dp_alloc_base += size; - - memset((void *)&(cpm->im_dprambase[retloc]), 0, size); - - return(retloc); -} - -/* We also own one page of host buffer space for the allocation of - * UART "fifos" and the like. - */ -uint -m8560_cpm_hostalloc(uint size, uint align) -{ - /* the host might not even have RAM yet - just use dual port RAM */ - return (m8560_cpm_dpalloc(size, align)); -} - -/* Set a baud rate generator. This needs lots of work. There are - * eight BRGs, which can be connected to the CPM channels or output - * as clocks. The BRGs are in two different block of internal - * memory mapped space. - * The baud rate clock is the system clock divided by something. - * It was set up long ago during the initial boot phase and is - * is given to us. - * Baud rate clocks are zero-based in the driver code (as that maps - * to port numbers). Documentation uses 1-based numbering. - */ -#define BRG_INT_CLK gd->arch.brg_clk -#define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16) - -/* This function is used by UARTS, or anything else that uses a 16x - * oversampled clock. - */ -void -m8560_cpm_setbrg(uint brg, uint rate) -{ - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; - volatile uint *bp; - - /* This is good enough to get SMCs running..... - */ - if (brg < 4) { - bp = (uint *)&(cpm->im_cpm_brg1.brgc1); - } - else { - bp = (uint *)&(cpm->im_cpm_brg2.brgc5); - brg -= 4; - } - bp += brg; - *bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; -} - -/* This function is used to set high speed synchronous baud rate - * clocks. - */ -void -m8560_cpm_fastbrg(uint brg, uint rate, int div16) -{ - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; - volatile uint *bp; - - /* This is good enough to get SMCs running..... - */ - if (brg < 4) { - bp = (uint *)&(cpm->im_cpm_brg1.brgc1); - } - else { - bp = (uint *)&(cpm->im_cpm_brg2.brgc5); - brg -= 4; - } - bp += brg; - *bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; - if (div16) - *bp |= CPM_BRG_DIV16; -} - -/* This function is used to set baud rate generators using an external - * clock source and 16x oversampling. - */ - -void -m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) -{ - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; - volatile uint *bp; - - if (brg < 4) { - bp = (uint *)&(cpm->im_cpm_brg1.brgc1); - } - else { - bp = (uint *)&(cpm->im_cpm_brg2.brgc5); - brg -= 4; - } - bp += brg; - *bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; - if (pinsel == 0) - *bp |= CPM_BRG_EXTC_CLK3_9; - else - *bp |= CPM_BRG_EXTC_CLK5_15; -} diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index cd32290410f..cc1d02df811 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -241,10 +241,6 @@ int checkcpu (void) printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); #endif -#ifdef CONFIG_CPM2 - printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus)); -#endif - #ifdef CONFIG_QE printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe)); #endif diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index e920e01b254..e9e133baf07 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -152,70 +152,6 @@ static void config_qe_ioports(void) } #endif -#ifdef CONFIG_CPM2 -void config_8560_ioports (volatile ccsr_cpm_t * cpm) -{ - int portnum; - - for (portnum = 0; portnum < 4; portnum++) { - uint pmsk = 0, - ppar = 0, - psor = 0, - pdir = 0, - podr = 0, - pdat = 0; - iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; - iop_conf_t *eiopc = iopc + 32; - uint msk = 1; - - /* - * NOTE: - * index 0 refers to pin 31, - * index 31 refers to pin 0 - */ - while (iopc < eiopc) { - if (iopc->conf) { - pmsk |= msk; - if (iopc->ppar) - ppar |= msk; - if (iopc->psor) - psor |= msk; - if (iopc->pdir) - pdir |= msk; - if (iopc->podr) - podr |= msk; - if (iopc->pdat) - pdat |= msk; - } - - msk <<= 1; - iopc++; - } - - if (pmsk != 0) { - volatile ioport_t *iop = ioport_addr (cpm, portnum); - uint tpmsk = ~pmsk; - - /* - * the (somewhat confused) paragraph at the - * bottom of page 35-5 warns that there might - * be "unknown behaviour" when programming - * PSORx and PDIRx, if PPARx = 1, so I - * decided this meant I had to disable the - * dedicated function first, and enable it - * last. - */ - iop->ppar &= tpmsk; - iop->psor = (iop->psor & tpmsk) | psor; - iop->podr = (iop->podr & tpmsk) | podr; - iop->pdat = (iop->pdat & tpmsk) | pdat; - iop->pdir = (iop->pdir & tpmsk) | pdir; - iop->ppar |= ppar; - } - } -} -#endif - #ifdef CONFIG_SYS_FSL_CPC #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F) void disable_cpc_sram(void) @@ -474,16 +410,8 @@ ulong cpu_init_f(void) #endif #endif -#ifdef CONFIG_CPM2 - config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); -#endif - init_early_memctl_regs(); -#if defined(CONFIG_CPM2) - m8560_cpm_reset(); -#endif - #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) /* Config QE ioports */ config_qe_ioports(); diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index d4b828e3824..c8ad6a1b01c 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -652,14 +652,6 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif -#ifdef CONFIG_CPM2 - do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", - "current-speed", gd->baudrate, 1); - - do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", - "clock-frequency", bd->bi_brgfreq, 1); -#endif - #ifdef CONFIG_FSL_CORENET do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0", "clock-frequency", get_board_sys_clk(), 1); diff --git a/arch/powerpc/cpu/mpc85xx/serial_scc.c b/arch/powerpc/cpu/mpc85xx/serial_scc.c deleted file mode 100644 index a2505d1ffc1..00000000000 --- a/arch/powerpc/cpu/mpc85xx/serial_scc.c +++ /dev/null @@ -1,262 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2003 Motorola Inc. - * Xianghua Xiao (X.Xiao@motorola.com) - * Modified based on 8260 for 8560. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00. - */ - -/* - * Minimal serial functions needed to use one of the SCC ports - * as serial console interface. - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CONS_ON_SCC) - -#if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */ - -#define SCC_INDEX 0 -#define PROFF_SCC PROFF_SCC1 -#define CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\ - CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1) -#define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK - -#elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */ - -#define SCC_INDEX 1 -#define PROFF_SCC PROFF_SCC2 -#define CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\ - CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2) -#define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK - -#elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */ - -#define SCC_INDEX 2 -#define PROFF_SCC PROFF_SCC3 -#define CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\ - CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3) -#define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK - -#elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */ - -#define SCC_INDEX 3 -#define PROFF_SCC PROFF_SCC4 -#define CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\ - CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4) -#define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK - -#else - -#error "console not correctly defined" - -#endif - -static int mpc85xx_serial_init(void) -{ - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; - volatile ccsr_cpm_scc_t *sp; - volatile scc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp); - uint dpaddr; - - /* initialize pointers to SCC */ - - sp = (ccsr_cpm_scc_t *) &(cpm->im_cpm_scc[SCC_INDEX]); - up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); - - /* Disable transmitter/receiver. - */ - sp->gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - /* put the SCC channel into NMSI (non multiplexd serial interface) - * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15). - */ - cpm->im_cpm_mux.cmxscr = \ - (cpm->im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE; - - /* Set up the baud rate generator. - */ - serial_setbrg (); - - /* Allocate space for two buffer descriptors in the DP ram. - * damm: allocating space after the two buffers for rx/tx data - */ - - dpaddr = m8560_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - rbdf = (cbd_t *)&(cpm->im_dprambase[dpaddr]); - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = BD_SC_WRAP; - - /* Set up the uart parameters in the parameter ram. - */ - up->scc_genscc.scc_rbase = dpaddr; - up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); - up->scc_genscc.scc_rfcr = CPMFCR_EB; - up->scc_genscc.scc_tfcr = CPMFCR_EB; - up->scc_genscc.scc_mrblr = 1; - up->scc_maxidl = 0; - up->scc_brkcr = 1; - up->scc_parec = 0; - up->scc_frmec = 0; - up->scc_nosec = 0; - up->scc_brkec = 0; - up->scc_uaddr1 = 0; - up->scc_uaddr2 = 0; - up->scc_toseq = 0; - up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000; - up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000; - up->scc_rccm = 0xc0ff; - - /* Mask all interrupts and remove anything pending. - */ - sp->sccm = 0; - sp->scce = 0xffff; - - /* Set 8 bit FIFO, 16 bit oversampling and UART mode. - */ - sp->gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */ - sp->gsmrl = \ - SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART; - - /* Set CTS no flow control, 1 stop bit, 8 bit character length, - * normal async UART mode, no parity - */ - sp->psmr = SCU_PSMR_CL; - - /* execute the "Init Rx and Tx params" CP command. - */ - - while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK, - 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. - */ - sp->gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT; - - return (0); -} - -static void mpc85xx_serial_setbrg(void) -{ -#if defined(CONFIG_CONS_USE_EXTC) - m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate, - CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL); -#else - m8560_cpm_setbrg(SCC_INDEX, gd->baudrate); -#endif -} - -static void mpc85xx_serial_putc(const char c) -{ - volatile scc_uart_t *up; - volatile cbd_t *tbdf; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; - - if (c == '\n') - serial_putc ('\r'); - - up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); - tbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_tbase]); - - /* Wait for last character to go. - */ - while (tbdf->cbd_sc & BD_SC_READY) - ; - - /* Load the character into the transmit buffer. - */ - *(volatile char *)tbdf->cbd_bufaddr = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; -} - -static int mpc85xx_serial_getc(void) -{ - volatile cbd_t *rbdf; - volatile scc_uart_t *up; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; - unsigned char c; - - up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); - rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]); - - /* Wait for character to show up. - */ - while (rbdf->cbd_sc & BD_SC_EMPTY) - ; - - /* Grab the char and clear the buffer again. - */ - c = *(volatile unsigned char *)rbdf->cbd_bufaddr; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return (c); -} - -static int mpc85xx_serial_tstc(void) -{ - volatile cbd_t *rbdf; - volatile scc_uart_t *up; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; - - up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); - rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]); - - return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0); -} - -static struct serial_device mpc85xx_serial_drv = { - .name = "mpc85xx_serial", - .start = mpc85xx_serial_init, - .stop = NULL, - .setbrg = mpc85xx_serial_setbrg, - .putc = mpc85xx_serial_putc, - .puts = default_serial_puts, - .getc = mpc85xx_serial_getc, - .tstc = mpc85xx_serial_tstc, -}; - -void mpc85xx_serial_initialize(void) -{ - serial_register(&mpc85xx_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &mpc85xx_serial_drv; -} -#endif /* CONFIG_CONS_ON_SCC */ diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 5a9cd281617..4b6f3d28baa 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -580,15 +580,6 @@ int get_clocks(void) sys_info_t sys_info; #ifdef CONFIG_ARCH_MPC8544 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; -#endif -#if defined(CONFIG_CPM2) - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; - uint sccr, dfbrg; - - /* set VCO = 4 * BRG */ - cpm->im_cpm_intctl.sccr &= 0xfffffffc; - sccr = cpm->im_cpm_intctl.sccr; - dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; #endif get_sys_info (&sys_info); gd->cpu_clk = sys_info.freq_processor[0]; @@ -635,13 +626,6 @@ int get_clocks(void) #endif #endif /* defined(CONFIG_FSL_ESDHC) */ -#if defined(CONFIG_CPM2) - gd->arch.vco_out = 2*sys_info.freq_systembus; - gd->arch.cpm_clk = gd->arch.vco_out / 2; - gd->arch.scc_clk = gd->arch.vco_out / 4; - gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1))); -#endif - if(gd->cpu_clk != 0) return (0); else return (1); } diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h deleted file mode 100644 index d42469c6e05..00000000000 --- a/arch/powerpc/include/asm/cpm_85xx.h +++ /dev/null @@ -1,824 +0,0 @@ -/* - * MPC85xx Communication Processor Module - * Copyright (c) 2003,Motorola Inc. - * Xianghua Xiao (X.Xiao@motorola.com) - * - * MPC8260 Communication Processor Module. - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * - * This file contains structures and information for the communication - * processor channels found in the dual port RAM or parameter RAM. - * All CPM control and status is available through the MPC8260 internal - * memory map. See immap.h for details. - */ -#ifndef __CPM_85XX__ -#define __CPM_85XX__ - -#include - -/* CPM Command register. -*/ -#define CPM_CR_RST ((uint)0x80000000) -#define CPM_CR_PAGE ((uint)0x7c000000) -#define CPM_CR_SBLOCK ((uint)0x03e00000) -#define CPM_CR_FLG ((uint)0x00010000) -#define CPM_CR_MCN ((uint)0x00003fc0) -#define CPM_CR_OPCODE ((uint)0x0000000f) - -/* Device sub-block and page codes. -*/ -#define CPM_CR_SCC1_SBLOCK (0x04) -#define CPM_CR_SCC2_SBLOCK (0x05) -#define CPM_CR_SCC3_SBLOCK (0x06) -#define CPM_CR_SCC4_SBLOCK (0x07) -#define CPM_CR_SMC1_SBLOCK (0x08) -#define CPM_CR_SMC2_SBLOCK (0x09) -#define CPM_CR_SPI_SBLOCK (0x0a) -#define CPM_CR_I2C_SBLOCK (0x0b) -#define CPM_CR_TIMER_SBLOCK (0x0f) -#define CPM_CR_RAND_SBLOCK (0x0e) -#define CPM_CR_FCC1_SBLOCK (0x10) -#define CPM_CR_FCC2_SBLOCK (0x11) -#define CPM_CR_FCC3_SBLOCK (0x12) -#define CPM_CR_MCC1_SBLOCK (0x1c) - -#define CPM_CR_SCC1_PAGE (0x00) -#define CPM_CR_SCC2_PAGE (0x01) -#define CPM_CR_SCC3_PAGE (0x02) -#define CPM_CR_SCC4_PAGE (0x03) -#define CPM_CR_SPI_PAGE (0x09) -#define CPM_CR_I2C_PAGE (0x0a) -#define CPM_CR_TIMER_PAGE (0x0a) -#define CPM_CR_RAND_PAGE (0x0a) -#define CPM_CR_FCC1_PAGE (0x04) -#define CPM_CR_FCC2_PAGE (0x05) -#define CPM_CR_FCC3_PAGE (0x06) -#define CPM_CR_MCC1_PAGE (0x07) -#define CPM_CR_MCC2_PAGE (0x08) - -/* Some opcodes (there are more...later) -*/ -#define CPM_CR_INIT_TRX ((ushort)0x0000) -#define CPM_CR_INIT_RX ((ushort)0x0001) -#define CPM_CR_INIT_TX ((ushort)0x0002) -#define CPM_CR_HUNT_MODE ((ushort)0x0003) -#define CPM_CR_STOP_TX ((ushort)0x0004) -#define CPM_CR_RESTART_TX ((ushort)0x0006) -#define CPM_CR_SET_GADDR ((ushort)0x0008) - -#define mk_cr_cmd(PG, SBC, MCN, OP) \ - ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) - -/* Dual Port RAM addresses. The first 16K is available for almost - * any CPM use, so we put the BDs there. The first 128 bytes are - * used for SMC1 and SMC2 parameter RAM, so we start allocating - * BDs above that. All of this must change when we start - * downloading RAM microcode. - */ -#define CPM_DATAONLY_BASE ((uint)128) -#define CPM_DP_NOSPACE ((uint)0x7FFFFFFF) -#define CPM_FCC_SPECIAL_BASE ((uint)0x0000B000) -#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE) - -/* The number of pages of host memory we allocate for CPM. This is - * done early in kernel initialization to get physically contiguous - * pages. - */ -#define NUM_CPM_HOST_PAGES 2 - -/* Export the base address of the communication processor registers - * and dual port ram. - */ -/*extern cpm8560_t *cpmp; Pointer to comm processor */ -uint m8560_cpm_dpalloc(uint size, uint align); -uint m8560_cpm_hostalloc(uint size, uint align); -void m8560_cpm_setbrg(uint brg, uint rate); -void m8560_cpm_fastbrg(uint brg, uint rate, int div16); -void m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel); - -/* Buffer descriptors used by many of the CPM protocols. -*/ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_CD ((ushort)0x0001) /* ?? */ - -/* Function code bits, usually generic to devices. -*/ -#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ -#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ -#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ -#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ -#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ - -/* Parameter RAM offsets from the base. -*/ -#define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */ -#define PROFF_SCC1 ((uint)0x8000) -#define PROFF_SCC2 ((uint)0x8100) -#define PROFF_SCC3 ((uint)0x8200) -#define PROFF_SCC4 ((uint)0x8300) -#define PROFF_FCC1 ((uint)0x8400) -#define PROFF_FCC2 ((uint)0x8500) -#define PROFF_FCC3 ((uint)0x8600) -#define PROFF_MCC1 ((uint)0x8700) -#define PROFF_MCC2 ((uint)0x8800) -#define PROFF_SPI_BASE ((uint)0x89fc) -#define PROFF_TIMERS ((uint)0x8ae0) -#define PROFF_REVNUM ((uint)0x8af0) -#define PROFF_RAND ((uint)0x8af8) -#define PROFF_I2C_BASE ((uint)0x8afc) - -/* Baud rate generators. -*/ -#define CPM_BRG_RST ((uint)0x00020000) -#define CPM_BRG_EN ((uint)0x00010000) -#define CPM_BRG_EXTC_INT ((uint)0x00000000) -#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000) -#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000) -#define CPM_BRG_ATB ((uint)0x00002000) -#define CPM_BRG_CD_MASK ((uint)0x00001ffe) -#define CPM_BRG_DIV16 ((uint)0x00000001) - -/* SCCs. -*/ -#define SCC_GSMRH_IRP ((uint)0x00040000) -#define SCC_GSMRH_GDE ((uint)0x00010000) -#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) -#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) -#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) -#define SCC_GSMRH_REVD ((uint)0x00002000) -#define SCC_GSMRH_TRX ((uint)0x00001000) -#define SCC_GSMRH_TTX ((uint)0x00000800) -#define SCC_GSMRH_CDP ((uint)0x00000400) -#define SCC_GSMRH_CTSP ((uint)0x00000200) -#define SCC_GSMRH_CDS ((uint)0x00000100) -#define SCC_GSMRH_CTSS ((uint)0x00000080) -#define SCC_GSMRH_TFL ((uint)0x00000040) -#define SCC_GSMRH_RFW ((uint)0x00000020) -#define SCC_GSMRH_TXSY ((uint)0x00000010) -#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) -#define SCC_GSMRH_SYNL8 ((uint)0x00000008) -#define SCC_GSMRH_SYNL4 ((uint)0x00000004) -#define SCC_GSMRH_RTSM ((uint)0x00000002) -#define SCC_GSMRH_RSYN ((uint)0x00000001) - -#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ -#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) -#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) -#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) -#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) -#define SCC_GSMRL_TCI ((uint)0x10000000) -#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) -#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) -#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) -#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) -#define SCC_GSMRL_RINV ((uint)0x02000000) -#define SCC_GSMRL_TINV ((uint)0x01000000) -#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) -#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) -#define SCC_GSMRL_TPL_48 ((uint)0x00800000) -#define SCC_GSMRL_TPL_32 ((uint)0x00600000) -#define SCC_GSMRL_TPL_16 ((uint)0x00400000) -#define SCC_GSMRL_TPL_8 ((uint)0x00200000) -#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) -#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) -#define SCC_GSMRL_TPP_01 ((uint)0x00100000) -#define SCC_GSMRL_TPP_10 ((uint)0x00080000) -#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) -#define SCC_GSMRL_TEND ((uint)0x00040000) -#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) -#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) -#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) -#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) -#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) -#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) -#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) -#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) -#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) -#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) -#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) -#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) -#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) -#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) -#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ -#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) -#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) -#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) -#define SCC_GSMRL_ENR ((uint)0x00000020) -#define SCC_GSMRL_ENT ((uint)0x00000010) -#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) -#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) -#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) -#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) -#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) -#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) -#define SCC_GSMRL_MODE_UART ((uint)0x00000004) -#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) -#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) -#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) - -#define SCC_TODR_TOD ((ushort)0x8000) - -/* SCC Event and Mask register. -*/ -#define SCCM_TXE ((unsigned char)0x10) -#define SCCM_BSY ((unsigned char)0x04) -#define SCCM_TX ((unsigned char)0x02) -#define SCCM_RX ((unsigned char)0x01) - -typedef struct scc_param { - ushort scc_rbase; /* Rx Buffer descriptor base address */ - ushort scc_tbase; /* Tx Buffer descriptor base address */ - u_char scc_rfcr; /* Rx function code */ - u_char scc_tfcr; /* Tx function code */ - ushort scc_mrblr; /* Max receive buffer length */ - uint scc_rstate; /* Internal */ - uint scc_idp; /* Internal */ - ushort scc_rbptr; /* Internal */ - ushort scc_ibc; /* Internal */ - uint scc_rxtmp; /* Internal */ - uint scc_tstate; /* Internal */ - uint scc_tdp; /* Internal */ - ushort scc_tbptr; /* Internal */ - ushort scc_tbc; /* Internal */ - uint scc_txtmp; /* Internal */ - uint scc_rcrc; /* Internal */ - uint scc_tcrc; /* Internal */ -} sccp_t; - -/* CPM Ethernet through SCC1. - */ -typedef struct scc_enet { - sccp_t sen_genscc; - uint sen_cpres; /* Preset CRC */ - uint sen_cmask; /* Constant mask for CRC */ - uint sen_crcec; /* CRC Error counter */ - uint sen_alec; /* alignment error counter */ - uint sen_disfc; /* discard frame counter */ - ushort sen_pads; /* Tx short frame pad character */ - ushort sen_retlim; /* Retry limit threshold */ - ushort sen_retcnt; /* Retry limit counter */ - ushort sen_maxflr; /* maximum frame length register */ - ushort sen_minflr; /* minimum frame length register */ - ushort sen_maxd1; /* maximum DMA1 length */ - ushort sen_maxd2; /* maximum DMA2 length */ - ushort sen_maxd; /* Rx max DMA */ - ushort sen_dmacnt; /* Rx DMA counter */ - ushort sen_maxb; /* Max BD byte count */ - ushort sen_gaddr1; /* Group address filter */ - ushort sen_gaddr2; - ushort sen_gaddr3; - ushort sen_gaddr4; - uint sen_tbuf0data0; /* Save area 0 - current frame */ - uint sen_tbuf0data1; /* Save area 1 - current frame */ - uint sen_tbuf0rba; /* Internal */ - uint sen_tbuf0crc; /* Internal */ - ushort sen_tbuf0bcnt; /* Internal */ - ushort sen_paddrh; /* physical address (MSB) */ - ushort sen_paddrm; - ushort sen_paddrl; /* physical address (LSB) */ - ushort sen_pper; /* persistence */ - ushort sen_rfbdptr; /* Rx first BD pointer */ - ushort sen_tfbdptr; /* Tx first BD pointer */ - ushort sen_tlbdptr; /* Tx last BD pointer */ - uint sen_tbuf1data0; /* Save area 0 - current frame */ - uint sen_tbuf1data1; /* Save area 1 - current frame */ - uint sen_tbuf1rba; /* Internal */ - uint sen_tbuf1crc; /* Internal */ - ushort sen_tbuf1bcnt; /* Internal */ - ushort sen_txlen; /* Tx Frame length counter */ - ushort sen_iaddr1; /* Individual address filter */ - ushort sen_iaddr2; - ushort sen_iaddr3; - ushort sen_iaddr4; - ushort sen_boffcnt; /* Backoff counter */ - - /* NOTE: Some versions of the manual have the following items - * incorrectly documented. Below is the proper order. - */ - ushort sen_taddrh; /* temp address (MSB) */ - ushort sen_taddrm; - ushort sen_taddrl; /* temp address (LSB) */ -} scc_enet_t; - - -/* SCC Event register as used by Ethernet. -*/ -#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ -#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* SCC Mode Register (PSMR) as used by Ethernet. -*/ -#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ -#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ -#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ -#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ -#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ -#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ -#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ -#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ -#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ -#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ -#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ -#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ -#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ - -/* Buffer descriptor control/status used by Ethernet receive. - * Common to SCC and FCC. - */ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ -#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. - * Common to SCC and FCC. - */ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - -/* SCC as UART -*/ -typedef struct scc_uart { - sccp_t scc_genscc; - uint scc_res1; /* Reserved */ - uint scc_res2; /* Reserved */ - ushort scc_maxidl; /* Maximum idle chars */ - ushort scc_idlc; /* temp idle counter */ - ushort scc_brkcr; /* Break count register */ - ushort scc_parec; /* receive parity error counter */ - ushort scc_frmec; /* receive framing error counter */ - ushort scc_nosec; /* receive noise counter */ - ushort scc_brkec; /* receive break condition counter */ - ushort scc_brkln; /* last received break length */ - ushort scc_uaddr1; /* UART address character 1 */ - ushort scc_uaddr2; /* UART address character 2 */ - ushort scc_rtemp; /* Temp storage */ - ushort scc_toseq; /* Transmit out of sequence char */ - ushort scc_char1; /* control character 1 */ - ushort scc_char2; /* control character 2 */ - ushort scc_char3; /* control character 3 */ - ushort scc_char4; /* control character 4 */ - ushort scc_char5; /* control character 5 */ - ushort scc_char6; /* control character 6 */ - ushort scc_char7; /* control character 7 */ - ushort scc_char8; /* control character 8 */ - ushort scc_rccm; /* receive control character mask */ - ushort scc_rccr; /* receive control character register */ - ushort scc_rlbc; /* receive last break character */ -} scc_uart_t; - -/* SCC Event and Mask registers when it is used as a UART. -*/ -#define UART_SCCM_GLR ((ushort)0x1000) -#define UART_SCCM_GLT ((ushort)0x0800) -#define UART_SCCM_AB ((ushort)0x0200) -#define UART_SCCM_IDL ((ushort)0x0100) -#define UART_SCCM_GRA ((ushort)0x0080) -#define UART_SCCM_BRKE ((ushort)0x0040) -#define UART_SCCM_BRKS ((ushort)0x0020) -#define UART_SCCM_CCR ((ushort)0x0008) -#define UART_SCCM_BSY ((ushort)0x0004) -#define UART_SCCM_TX ((ushort)0x0002) -#define UART_SCCM_RX ((ushort)0x0001) - -/* The SCC PSMR when used as a UART. -*/ -#define SCU_PSMR_FLC ((ushort)0x8000) -#define SCU_PSMR_SL ((ushort)0x4000) -#define SCU_PSMR_CL ((ushort)0x3000) -#define SCU_PSMR_UM ((ushort)0x0c00) -#define SCU_PSMR_FRZ ((ushort)0x0200) -#define SCU_PSMR_RZS ((ushort)0x0100) -#define SCU_PSMR_SYN ((ushort)0x0080) -#define SCU_PSMR_DRT ((ushort)0x0040) -#define SCU_PSMR_PEN ((ushort)0x0010) -#define SCU_PSMR_RPM ((ushort)0x000c) -#define SCU_PSMR_REVP ((ushort)0x0008) -#define SCU_PSMR_TPM ((ushort)0x0003) -#define SCU_PSMR_TEVP ((ushort)0x0003) - -/* CPM Transparent mode SCC. - */ -typedef struct scc_trans { - sccp_t st_genscc; - uint st_cpres; /* Preset CRC */ - uint st_cmask; /* Constant mask for CRC */ -} scc_trans_t; - -#define BD_SCC_TX_LAST ((ushort)0x0800) - -/* How about some FCCs..... -*/ -#define FCC_GFMR_DIAG_NORM ((uint)0x00000000) -#define FCC_GFMR_DIAG_LE ((uint)0x40000000) -#define FCC_GFMR_DIAG_AE ((uint)0x80000000) -#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) -#define FCC_GFMR_TCI ((uint)0x20000000) -#define FCC_GFMR_TRX ((uint)0x10000000) -#define FCC_GFMR_TTX ((uint)0x08000000) -#define FCC_GFMR_TTX ((uint)0x08000000) -#define FCC_GFMR_CDP ((uint)0x04000000) -#define FCC_GFMR_CTSP ((uint)0x02000000) -#define FCC_GFMR_CDS ((uint)0x01000000) -#define FCC_GFMR_CTSS ((uint)0x00800000) -#define FCC_GFMR_SYNL_NONE ((uint)0x00000000) -#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) -#define FCC_GFMR_SYNL_8 ((uint)0x00008000) -#define FCC_GFMR_SYNL_16 ((uint)0x0000c000) -#define FCC_GFMR_RTSM ((uint)0x00002000) -#define FCC_GFMR_RENC_NRZ ((uint)0x00000000) -#define FCC_GFMR_RENC_NRZI ((uint)0x00000800) -#define FCC_GFMR_REVD ((uint)0x00000400) -#define FCC_GFMR_TENC_NRZ ((uint)0x00000000) -#define FCC_GFMR_TENC_NRZI ((uint)0x00000100) -#define FCC_GFMR_TCRC_16 ((uint)0x00000000) -#define FCC_GFMR_TCRC_32 ((uint)0x00000080) -#define FCC_GFMR_ENR ((uint)0x00000020) -#define FCC_GFMR_ENT ((uint)0x00000010) -#define FCC_GFMR_MODE_ENET ((uint)0x0000000c) -#define FCC_GFMR_MODE_ATM ((uint)0x0000000a) -#define FCC_GFMR_MODE_HDLC ((uint)0x00000000) - -/* Generic FCC parameter ram. -*/ -typedef struct fcc_param { - ushort fcc_riptr; /* Rx Internal temp pointer */ - ushort fcc_tiptr; /* Tx Internal temp pointer */ - ushort fcc_res1; - ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ - uint fcc_rstate; /* Upper byte is Func code, must be set */ - uint fcc_rbase; /* Receive BD base */ - ushort fcc_rbdstat; /* RxBD status */ - ushort fcc_rbdlen; /* RxBD down counter */ - uint fcc_rdptr; /* RxBD internal data pointer */ - uint fcc_tstate; /* Upper byte is Func code, must be set */ - uint fcc_tbase; /* Transmit BD base */ - ushort fcc_tbdstat; /* TxBD status */ - ushort fcc_tbdlen; /* TxBD down counter */ - uint fcc_tdptr; /* TxBD internal data pointer */ - uint fcc_rbptr; /* Rx BD Internal buf pointer */ - uint fcc_tbptr; /* Tx BD Internal buf pointer */ - uint fcc_rcrc; /* Rx temp CRC */ - uint fcc_res2; - uint fcc_tcrc; /* Tx temp CRC */ -} fccp_t; - - -/* Ethernet controller through FCC. -*/ -typedef struct fcc_enet { - fccp_t fen_genfcc; - uint fen_statbuf; /* Internal status buffer */ - uint fen_camptr; /* CAM address */ - uint fen_cmask; /* Constant mask for CRC */ - uint fen_cpres; /* Preset CRC */ - uint fen_crcec; /* CRC Error counter */ - uint fen_alec; /* alignment error counter */ - uint fen_disfc; /* discard frame counter */ - ushort fen_retlim; /* Retry limit */ - ushort fen_retcnt; /* Retry counter */ - ushort fen_pper; /* Persistence */ - ushort fen_boffcnt; /* backoff counter */ - uint fen_gaddrh; /* Group address filter, high 32-bits */ - uint fen_gaddrl; /* Group address filter, low 32-bits */ - ushort fen_tfcstat; /* out of sequence TxBD */ - ushort fen_tfclen; - uint fen_tfcptr; - ushort fen_mflr; /* Maximum frame length (1518) */ - ushort fen_paddrh; /* MAC address */ - ushort fen_paddrm; - ushort fen_paddrl; - ushort fen_ibdcount; /* Internal BD counter */ - ushort fen_ibdstart; /* Internal BD start pointer */ - ushort fen_ibdend; /* Internal BD end pointer */ - ushort fen_txlen; /* Internal Tx frame length counter */ - uint fen_ibdbase[8]; /* Internal use */ - uint fen_iaddrh; /* Individual address filter */ - uint fen_iaddrl; - ushort fen_minflr; /* Minimum frame length (64) */ - ushort fen_taddrh; /* Filter transfer MAC address */ - ushort fen_taddrm; - ushort fen_taddrl; - ushort fen_padptr; /* Pointer to pad byte buffer */ - ushort fen_cftype; /* control frame type */ - ushort fen_cfrange; /* control frame range */ - ushort fen_maxb; /* maximum BD count */ - ushort fen_maxd1; /* Max DMA1 length (1520) */ - ushort fen_maxd2; /* Max DMA2 length (1520) */ - ushort fen_maxd; /* internal max DMA count */ - ushort fen_dmacnt; /* internal DMA counter */ - uint fen_octc; /* Total octect counter */ - uint fen_colc; /* Total collision counter */ - uint fen_broc; /* Total broadcast packet counter */ - uint fen_mulc; /* Total multicast packet count */ - uint fen_uspc; /* Total packets < 64 bytes */ - uint fen_frgc; /* Total packets < 64 bytes with errors */ - uint fen_ospc; /* Total packets > 1518 */ - uint fen_jbrc; /* Total packets > 1518 with errors */ - uint fen_p64c; /* Total packets == 64 bytes */ - uint fen_p65c; /* Total packets 64 < bytes <= 127 */ - uint fen_p128c; /* Total packets 127 < bytes <= 255 */ - uint fen_p256c; /* Total packets 256 < bytes <= 511 */ - uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ - uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ - uint fen_cambuf; /* Internal CAM buffer poiner */ - ushort fen_rfthr; /* Received frames threshold */ - ushort fen_rfcnt; /* Received frames count */ -} fcc_enet_t; - -/* FCC Event/Mask register as used by Ethernet. -*/ -#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ -#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ -#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ -#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* FCC Mode Register (FPSMR) as used by Ethernet. -*/ -#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ -#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ -#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ -#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ -#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ -#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ -#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ -#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ -#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ -#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ -#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ -#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ -#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ - -/* IIC parameter RAM. -*/ -typedef struct iic { - ushort iic_rbase; /* Rx Buffer descriptor base address */ - ushort iic_tbase; /* Tx Buffer descriptor base address */ - u_char iic_rfcr; /* Rx function code */ - u_char iic_tfcr; /* Tx function code */ - ushort iic_mrblr; /* Max receive buffer length */ - uint iic_rstate; /* Internal */ - uint iic_rdp; /* Internal */ - ushort iic_rbptr; /* Internal */ - ushort iic_rbc; /* Internal */ - uint iic_rxtmp; /* Internal */ - uint iic_tstate; /* Internal */ - uint iic_tdp; /* Internal */ - ushort iic_tbptr; /* Internal */ - ushort iic_tbc; /* Internal */ - uint iic_txtmp; /* Internal */ -} iic_t; - -/* SPI parameter RAM. -*/ -typedef struct spi { - ushort spi_rbase; /* Rx Buffer descriptor base address */ - ushort spi_tbase; /* Tx Buffer descriptor base address */ - u_char spi_rfcr; /* Rx function code */ - u_char spi_tfcr; /* Tx function code */ - ushort spi_mrblr; /* Max receive buffer length */ - uint spi_rstate; /* Internal */ - uint spi_rdp; /* Internal */ - ushort spi_rbptr; /* Internal */ - ushort spi_rbc; /* Internal */ - uint spi_rxtmp; /* Internal */ - uint spi_tstate; /* Internal */ - uint spi_tdp; /* Internal */ - ushort spi_tbptr; /* Internal */ - ushort spi_tbc; /* Internal */ - uint spi_txtmp; /* Internal */ - uint spi_res; /* Tx temp. */ - uint spi_res1[4]; /* SDMA temp. */ -} spi_t; - -/* SPI Mode register. -*/ -#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ -#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ -#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ -#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ -#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ -#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ -#define SPMODE_EN ((ushort)0x0100) /* Enable */ -#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ -#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ - -#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) -#define SPMODE_PM(x) ((x) &0xF) - -#define SPI_EB ((u_char)0x10) /* big endian byte order */ - -#define BD_IIC_START ((ushort)0x0400) - -/*----------------------------------------------------------------------- - * CMXFCR - CMX FCC Clock Route Register 15-12 - */ -#define CMXFCR_FC1 0x40000000 /* FCC1 connection */ -#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */ -#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */ -#define CMXFCR_FC2 0x00400000 /* FCC2 connection */ -#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */ -#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */ -#define CMXFCR_FC3 0x00004000 /* FCC3 connection */ -#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */ -#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */ - -#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */ -#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */ -#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */ -#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */ -#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */ -#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */ -#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */ -#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */ - -#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */ -#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */ -#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */ -#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */ -#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */ -#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */ -#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */ -#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */ - -#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */ -#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */ -#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */ -#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */ -#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */ -#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */ -#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */ -#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */ - -#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */ -#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */ -#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */ -#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */ -#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */ -#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */ -#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */ -#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */ - -#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */ -#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */ -#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */ -#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */ -#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */ -#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */ -#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */ -#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */ - -#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */ -#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */ -#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */ -#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */ -#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */ -#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */ -#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */ -#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */ - -/*----------------------------------------------------------------------- - * CMXSCR - CMX SCC Clock Route Register 15-14 - */ -#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */ -#define CMXSCR_SC1 0x40000000 /* SCC1 connection */ -#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */ -#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */ -#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */ -#define CMXSCR_SC2 0x00400000 /* SCC2 connection */ -#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */ -#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */ -#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */ -#define CMXSCR_SC3 0x00004000 /* SCC3 connection */ -#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */ -#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */ -#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */ -#define CMXSCR_SC4 0x00000040 /* SCC4 connection */ -#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */ -#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */ - -#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */ -#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */ -#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */ -#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */ -#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */ -#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */ -#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */ -#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */ - -#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */ -#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */ -#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */ -#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */ -#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */ -#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */ -#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */ -#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */ - -#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */ -#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */ -#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */ -#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */ -#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */ -#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */ -#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */ -#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */ - -#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */ -#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */ -#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */ -#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */ -#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */ -#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */ -#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */ -#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */ - -#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */ -#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */ -#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */ -#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */ -#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */ -#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */ -#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */ -#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */ - -#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */ -#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */ -#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */ -#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */ -#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */ -#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */ -#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */ -#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */ - -#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */ -#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */ -#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */ -#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */ -#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */ -#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */ -#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */ -#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */ - -#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */ -#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */ -#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */ -#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */ -#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */ -#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */ -#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ -#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ - -#endif /* __CPM_85XX__ */ diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 2975255bfe2..770adcd30f2 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -19,13 +19,6 @@ struct arch_global_data { #endif #if defined(CONFIG_MPC8xx) unsigned long brg_clk; -#endif -#if defined(CONFIG_CPM2) - /* There are many clocks on the MPC8260 - see page 9-5 */ - unsigned long vco_out; - unsigned long cpm_clk; - unsigned long scc_clk; - unsigned long brg_clk; #endif /* TODO: sjg@chromium.org: Should these be unslgned long? */ #if defined(CONFIG_MPC83xx) @@ -88,10 +81,6 @@ struct arch_global_data { unsigned long arbiter_event_attributes; unsigned long arbiter_event_address; #endif -#if defined(CONFIG_CPM2) - unsigned int dp_alloc_base; - unsigned int dp_alloc_top; -#endif #ifdef CONFIG_SYS_FPGA_COUNT unsigned fpga_state[CONFIG_SYS_FPGA_COUNT]; #endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 770705a8794..b8bc5844821 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -921,330 +921,6 @@ typedef struct ccsr_pic { u8 res150[130892]; } ccsr_pic_t; -/* CPM Block */ -#ifndef CONFIG_CPM2 -typedef struct ccsr_cpm { - u8 res[262144]; -} ccsr_cpm_t; -#else -/* - * DPARM - * General SIU - */ -typedef struct ccsr_cpm_siu { - u8 res1[80]; - u32 smaer; - u32 smser; - u32 smevr; - u8 res2[4]; - u32 lmaer; - u32 lmser; - u32 lmevr; - u8 res3[2964]; -} ccsr_cpm_siu_t; - -/* IRQ Controller */ -typedef struct ccsr_cpm_intctl { - u16 sicr; - u8 res1[2]; - u32 sivec; - u32 sipnrh; - u32 sipnrl; - u32 siprr; - u32 scprrh; - u32 scprrl; - u32 simrh; - u32 simrl; - u32 siexr; - u8 res2[88]; - u32 sccr; - u8 res3[124]; -} ccsr_cpm_intctl_t; - -/* input/output port */ -typedef struct ccsr_cpm_iop { - u32 pdira; - u32 ppara; - u32 psora; - u32 podra; - u32 pdata; - u8 res1[12]; - u32 pdirb; - u32 pparb; - u32 psorb; - u32 podrb; - u32 pdatb; - u8 res2[12]; - u32 pdirc; - u32 pparc; - u32 psorc; - u32 podrc; - u32 pdatc; - u8 res3[12]; - u32 pdird; - u32 ppard; - u32 psord; - u32 podrd; - u32 pdatd; - u8 res4[12]; -} ccsr_cpm_iop_t; - -/* CPM timers */ -typedef struct ccsr_cpm_timer { - u8 tgcr1; - u8 res1[3]; - u8 tgcr2; - u8 res2[11]; - u16 tmr1; - u16 tmr2; - u16 trr1; - u16 trr2; - u16 tcr1; - u16 tcr2; - u16 tcn1; - u16 tcn2; - u16 tmr3; - u16 tmr4; - u16 trr3; - u16 trr4; - u16 tcr3; - u16 tcr4; - u16 tcn3; - u16 tcn4; - u16 ter1; - u16 ter2; - u16 ter3; - u16 ter4; - u8 res3[608]; -} ccsr_cpm_timer_t; - -/* SDMA */ -typedef struct ccsr_cpm_sdma { - u8 sdsr; - u8 res1[3]; - u8 sdmr; - u8 res2[739]; -} ccsr_cpm_sdma_t; - -/* FCC1 */ -typedef struct ccsr_cpm_fcc1 { - u32 gfmr; - u32 fpsmr; - u16 ftodr; - u8 res1[2]; - u16 fdsr; - u8 res2[2]; - u16 fcce; - u8 res3[2]; - u16 fccm; - u8 res4[2]; - u8 fccs; - u8 res5[3]; - u8 ftirr_phy[4]; -} ccsr_cpm_fcc1_t; - -/* FCC2 */ -typedef struct ccsr_cpm_fcc2 { - u32 gfmr; - u32 fpsmr; - u16 ftodr; - u8 res1[2]; - u16 fdsr; - u8 res2[2]; - u16 fcce; - u8 res3[2]; - u16 fccm; - u8 res4[2]; - u8 fccs; - u8 res5[3]; - u8 ftirr_phy[4]; -} ccsr_cpm_fcc2_t; - -/* FCC3 */ -typedef struct ccsr_cpm_fcc3 { - u32 gfmr; - u32 fpsmr; - u16 ftodr; - u8 res1[2]; - u16 fdsr; - u8 res2[2]; - u16 fcce; - u8 res3[2]; - u16 fccm; - u8 res4[2]; - u8 fccs; - u8 res5[3]; - u8 res[36]; -} ccsr_cpm_fcc3_t; - -/* FCC1 extended */ -typedef struct ccsr_cpm_fcc1_ext { - u32 firper; - u32 firer; - u32 firsr_h; - u32 firsr_l; - u8 gfemr; - u8 res[15]; - -} ccsr_cpm_fcc1_ext_t; - -/* FCC2 extended */ -typedef struct ccsr_cpm_fcc2_ext { - u32 firper; - u32 firer; - u32 firsr_h; - u32 firsr_l; - u8 gfemr; - u8 res[31]; -} ccsr_cpm_fcc2_ext_t; - -/* FCC3 extended */ -typedef struct ccsr_cpm_fcc3_ext { - u8 gfemr; - u8 res[47]; -} ccsr_cpm_fcc3_ext_t; - -/* TC layers */ -typedef struct ccsr_cpm_tmp1 { - u8 res[496]; -} ccsr_cpm_tmp1_t; - -/* BRGs:5,6,7,8 */ -typedef struct ccsr_cpm_brg2 { - u32 brgc5; - u32 brgc6; - u32 brgc7; - u32 brgc8; - u8 res[608]; -} ccsr_cpm_brg2_t; - -/* I2C */ -typedef struct ccsr_cpm_i2c { - u8 i2mod; - u8 res1[3]; - u8 i2add; - u8 res2[3]; - u8 i2brg; - u8 res3[3]; - u8 i2com; - u8 res4[3]; - u8 i2cer; - u8 res5[3]; - u8 i2cmr; - u8 res6[331]; -} ccsr_cpm_i2c_t; - -/* CPM core */ -typedef struct ccsr_cpm_cp { - u32 cpcr; - u32 rccr; - u8 res1[14]; - u16 rter; - u8 res2[2]; - u16 rtmr; - u16 rtscr; - u8 res3[2]; - u32 rtsr; - u8 res4[12]; -} ccsr_cpm_cp_t; - -/* BRGs:1,2,3,4 */ -typedef struct ccsr_cpm_brg1 { - u32 brgc1; - u32 brgc2; - u32 brgc3; - u32 brgc4; -} ccsr_cpm_brg1_t; - -/* SCC1-SCC4 */ -typedef struct ccsr_cpm_scc { - u32 gsmrl; - u32 gsmrh; - u16 psmr; - u8 res1[2]; - u16 todr; - u16 dsr; - u16 scce; - u8 res2[2]; - u16 sccm; - u8 res3; - u8 sccs; - u8 res4[8]; -} ccsr_cpm_scc_t; - -typedef struct ccsr_cpm_tmp2 { - u8 res[32]; -} ccsr_cpm_tmp2_t; - -/* SPI */ -typedef struct ccsr_cpm_spi { - u16 spmode; - u8 res1[4]; - u8 spie; - u8 res2[3]; - u8 spim; - u8 res3[2]; - u8 spcom; - u8 res4[82]; -} ccsr_cpm_spi_t; - -/* CPM MUX */ -typedef struct ccsr_cpm_mux { - u8 cmxsi1cr; - u8 res1; - u8 cmxsi2cr; - u8 res2; - u32 cmxfcr; - u32 cmxscr; - u8 res3[2]; - u16 cmxuar; - u8 res4[16]; -} ccsr_cpm_mux_t; - -/* SI,MCC,etc */ -typedef struct ccsr_cpm_tmp3 { - u8 res[58592]; -} ccsr_cpm_tmp3_t; - -typedef struct ccsr_cpm_iram { - u32 iram[8192]; - u8 res[98304]; -} ccsr_cpm_iram_t; - -typedef struct ccsr_cpm { - /* Some references are into the unique & known dpram spaces, - * others are from the generic base. - */ -#define im_dprambase im_dpram1 - u8 im_dpram1[16*1024]; - u8 res1[16*1024]; - u8 im_dpram2[16*1024]; - u8 res2[16*1024]; - ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ - ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */ - ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ - ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ - ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ - ccsr_cpm_fcc1_t im_cpm_fcc1; - ccsr_cpm_fcc2_t im_cpm_fcc2; - ccsr_cpm_fcc3_t im_cpm_fcc3; - ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext; - ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext; - ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext; - ccsr_cpm_tmp1_t im_cpm_tmp1; - ccsr_cpm_brg2_t im_cpm_brg2; - ccsr_cpm_i2c_t im_cpm_i2c; - ccsr_cpm_cp_t im_cpm_cp; - ccsr_cpm_brg1_t im_cpm_brg1; - ccsr_cpm_scc_t im_cpm_scc[4]; - ccsr_cpm_tmp2_t im_cpm_tmp2; - ccsr_cpm_spi_t im_cpm_spi; - ccsr_cpm_mux_t im_cpm_mux; - ccsr_cpm_tmp3_t im_cpm_tmp3; - ccsr_cpm_iram_t im_cpm_iram; -} ccsr_cpm_t; -#endif - #ifdef CONFIG_SYS_SRIO /* Architectural regsiters */ struct rio_arch { @@ -2888,7 +2564,6 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 #define CONFIG_SYS_SEC_MON_OFFSET 0xE6000 #define CONFIG_SYS_SFP_OFFSET 0xE7000 -#define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000 #define CONFIG_SYS_FSL_FM1_OFFSET 0x100000 @@ -2965,8 +2640,6 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) #define CONFIG_SYS_MPC8xxx_PIC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) -#define CONFIG_SYS_MPC85xx_CPM_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET) #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \ diff --git a/arch/powerpc/lib/bdinfo.c b/arch/powerpc/lib/bdinfo.c index d2e5e6057b3..55dcad5df8e 100644 --- a/arch/powerpc/lib/bdinfo.c +++ b/arch/powerpc/lib/bdinfo.c @@ -27,13 +27,6 @@ int arch_setup_bdinfo(void) bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ -#if defined(CONFIG_CPM2) - bd->bi_cpmfreq = gd->arch.cpm_clk; - bd->bi_brgfreq = gd->arch.brg_clk; - bd->bi_sccfreq = gd->arch.scc_clk; - bd->bi_vco = gd->arch.vco_out; -#endif /* CONFIG_CPM2 */ - return 0; } @@ -59,10 +52,4 @@ void arch_print_bdinfo(void) puts("addressing = 32-bit\n"); #endif board_detail(); -#if defined(CONFIG_CPM2) - bdinfo_print_mhz("cpmfreq", bd->bi_cpmfreq); - bdinfo_print_mhz("vco", bd->bi_vco); - bdinfo_print_mhz("sccfreq", bd->bi_sccfreq); - bdinfo_print_mhz("brgfreq", bd->bi_brgfreq); -#endif } diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 8d65047aa4d..3b43066bb4f 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -266,12 +266,6 @@ static void set_clocks_in_mhz (struct bd_info *kbd) /* convert all clock information to MHz */ kbd->bi_intfreq /= 1000000L; kbd->bi_busfreq /= 1000000L; -#if defined(CONFIG_CPM2) - kbd->bi_cpmfreq /= 1000000L; - kbd->bi_brgfreq /= 1000000L; - kbd->bi_sccfreq /= 1000000L; - kbd->bi_vco /= 1000000L; -#endif } } diff --git a/drivers/pci/pci_mpc85xx.c b/drivers/pci/pci_mpc85xx.c index 1e180ee289b..8a81a74067e 100644 --- a/drivers/pci/pci_mpc85xx.c +++ b/drivers/pci/pci_mpc85xx.c @@ -6,7 +6,6 @@ */ #include #include -#include #include #include #include diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 637de0c4558..1becc669aee 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -52,12 +52,6 @@ struct bd_info { unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ unsigned long bi_intfreq; /* Internal Freq, in MHz */ unsigned long bi_busfreq; /* Bus Freq, in MHz */ -#if defined(CONFIG_CPM2) - unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */ - unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */ - unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ - unsigned long bi_vco; /* VCO Out from PLL, in MHz */ -#endif #if defined(CONFIG_M68K) unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ #endif diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h deleted file mode 100644 index 57097b17eb1..00000000000 --- a/include/configs/MPC8540ADS.h +++ /dev/null @@ -1,303 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2004, 2011 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - */ - -/* - * mpc8540ads board configuration file - * - * Please refer to doc/README.mpc85xx for more info. - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_SERVERIP, etc in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * default CCARBAR is at 0xff700000 - * assume U-Boot is less than 0.5MB - */ - -#ifndef CONFIG_HAS_FEC -#define CONFIG_HAS_FEC 1 /* 8540 has FEC */ -#endif - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - * - * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to - * 33MHz to accommodate, based on a PCI pin. - * Note that PCI-X won't work at 33MHz. - */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 -#define CONFIG_SYS_DDR_TIMING_1 0x37344321 -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ -#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ -#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ - -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* - * Local Bus Definitions - */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ - -#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ - | LSDMR_RFCR5 \ - | LSDMR_PRETOACT3 \ - | LSDMR_ACTTORW3 \ - | LSDMR_BL8 \ - | LSDMR_WRC2 \ - | LSDMR_CL3 \ - | LSDMR_RFEN \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) -#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) -#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) - -/* - * 32KB, 8-bit wide for ADS config reg - */ -#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* - * I2C - */ -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ - -#if defined(CONFIG_PCI) - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -#if CONFIG_HAS_FEC -#define CONFIG_MPC85XX_FEC 1 -#define CONFIG_MPC85XX_FEC_NAME "FEC" -#define FEC_PHY_ADDR 3 -#define FEC_PHYIDX 0 -#define FEC_FLAGS 0 -#endif - -/* Options are: TSEC[0-1], FEC */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Miscellaneous configurable options - */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/nfsroot" -#define CONFIG_BOOTFILE "your.uImage" - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h deleted file mode 100644 index d23cf0e41aa..00000000000 --- a/include/configs/MPC8560ADS.h +++ /dev/null @@ -1,292 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2004, 2011 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - */ - -/* - * mpc8560ads board configuration file - * - * Please refer to doc/README.mpc85xx for more info. - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_SERVERIP, etc. in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* High Level Configuration Options */ -#define CONFIG_CPM2 1 /* has CPM2 */ - -/* - * default CCARBAR is at 0xff700000 - * assume U-Boot is less than 0.5MB - */ - -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 -#define CONFIG_SYS_DDR_TIMING_1 0x37344321 -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ -#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ -#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ - -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* - * Local Bus Definitions - */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ - -#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ - | LSDMR_RFCR5 \ - | LSDMR_PRETOACT3 \ - | LSDMR_ACTTORW3 \ - | LSDMR_BL8 \ - | LSDMR_WRC2 \ - | LSDMR_CL3 \ - | LSDMR_RFEN \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) -#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) -#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) - -/* - * 32KB, 8-bit wide for ADS config reg - */ -#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ - -/* Serial Port */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -/* - * I2C - */ -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ - -#if defined(CONFIG_PCI) - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#endif /* CONFIG_PCI */ - -#ifdef CONFIG_TSEC_ENET - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* - * Environment Configuration - */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/nfsroot" -#define CONFIG_BOOTFILE "your.uImage" - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyCPM\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=mpc8560ads.dtb\0" - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 819b4778d6f9136676c5484ca504bd3363b89fd5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 25 Feb 2022 11:19:52 -0500 Subject: Convert CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS to Kconfig This converts the following to Kconfig: CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS Signed-off-by: Tom Rini --- configs/blanche_defconfig | 1 + configs/ls1021aqds_ddr4_nor_defconfig | 1 + configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021aqds_nor_defconfig | 1 + configs/ls1021aqds_nor_lpuart_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_nor_defconfig | 1 + configs/ls1021atwr_nor_lpuart_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1043aqds_defconfig | 1 + configs/ls1043aqds_lpuart_defconfig | 1 + configs/ls1043aqds_nand_defconfig | 1 + configs/ls1043aqds_nor_ddr3_defconfig | 1 + configs/ls1043aqds_sdcard_ifc_defconfig | 1 + configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1043aqds_tfa_defconfig | 1 + configs/ls1043ardb_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_defconfig | 1 + configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_nand_defconfig | 1 + configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_sdcard_defconfig | 1 + configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_tfa_defconfig | 1 + configs/ls1046aqds_SECURE_BOOT_defconfig | 1 + configs/ls1046aqds_defconfig | 1 + configs/ls1046aqds_lpuart_defconfig | 1 + configs/ls1046aqds_nand_defconfig | 1 + configs/ls1046aqds_sdcard_ifc_defconfig | 1 + configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1046aqds_tfa_defconfig | 1 + configs/pg_wcom_expu1_defconfig | 1 + configs/pg_wcom_expu1_update_defconfig | 1 + configs/pg_wcom_seli8_defconfig | 1 + configs/pg_wcom_seli8_update_defconfig | 1 + configs/qemu_arm64_defconfig | 1 + configs/qemu_arm_defconfig | 1 + configs/r8a77990_ebisu_defconfig | 1 + configs/r8a77995_draak_defconfig | 1 + configs/rcar3_salvator-x_defconfig | 1 + configs/rcar3_ulcb_defconfig | 1 + drivers/mtd/Kconfig | 7 +++++++ include/configs/T102xRDB.h | 1 - include/configs/blanche.h | 1 - include/configs/draak.h | 1 - include/configs/ebisu.h | 1 - include/configs/km/pg-wcom-ls102xa.h | 1 - include/configs/ls1021aqds.h | 1 - include/configs/ls1021atwr.h | 1 - include/configs/ls1043aqds.h | 1 - include/configs/ls1043ardb.h | 1 - include/configs/ls1046aqds.h | 1 - include/configs/qemu-arm.h | 1 - include/configs/salvator-x.h | 1 - include/configs/ulcb.h | 1 - 59 files changed, 52 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig index 1e117c9e8f4..82d54debb3d 100644 --- a/configs/blanche_defconfig +++ b/configs/blanche_defconfig @@ -53,6 +53,7 @@ CONFIG_RENESAS_SDHI=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 925d68db8e1..1bc73dbc710 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -65,6 +65,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index c71c8649d92..2a3348f7ef0 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -66,6 +66,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 58629beb0c7..c31047f7446 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -87,6 +87,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index d252ed49e95..7ad5c164520 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -64,6 +64,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index fb9f457b74d..3e8b34b58b5 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -66,6 +66,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 1d6d88ff372..fdfcf9d84f2 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -67,6 +67,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 38b17048c4f..29045bf3acf 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -84,6 +84,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 2f66d833a31..834a2d3308c 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -54,6 +54,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index c1adc6e23fa..a31560a1286 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -56,6 +56,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index 150179d6334..427fa1b6a3b 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -57,6 +57,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index a8288e9fb6a..0139f03ed42 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -74,6 +74,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 695505a9752..aec9e5c7947 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -74,6 +74,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_ATHEROS=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index ef1a591ec09..ad59689c6ce 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -65,6 +65,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 8dd6ce41d6c..d583573f179 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -66,6 +66,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 3e548031071..8027b019568 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -85,6 +85,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_NAND_FSL_IFC=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 97fe2ce8bd6..5be7e4c8e59 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -66,6 +66,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index be40f49f6e1..dd36d811b3a 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -84,6 +84,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index e196c4428f4..7fadadb5694 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -65,6 +65,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 6a897948850..5510d50a3c8 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -74,6 +74,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index e7c277d6c62..c0ffae9380f 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -47,6 +47,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 94daa1f10ba..173109eda49 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -50,6 +50,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index a86138f1798..37687fc5859 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -61,6 +61,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_NAND_FSL_IFC=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 19a54d1ea2e..a8dc3484d5c 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -69,6 +69,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_NAND_FSL_IFC=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index 61e348291e8..bd1c4559ec4 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -63,6 +63,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index ef82842b649..0976b9650bd 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -68,6 +68,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index 6ff5614cb53..4b0ef668e78 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -48,6 +48,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index 551807e879d..ea5d0040084 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -54,6 +54,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index c15302c753c..bbeea5a9403 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -62,6 +62,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index bc326114cd1..f1f82d7a900 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -65,6 +65,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index 52855d12e51..282cb435007 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -66,6 +66,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index ab780c16221..9f158aa94a9 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -84,6 +84,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index b5b501c9a95..f906202cbff 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -85,6 +85,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 740838baa10..5d71bbe860a 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -65,6 +65,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 11de0d40afa..b817907d83f 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -74,6 +74,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig index 7b9e292ebed..706aacfea00 100644 --- a/configs/pg_wcom_expu1_defconfig +++ b/configs/pg_wcom_expu1_defconfig @@ -67,6 +67,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig index b37755f2e26..9cd479877ec 100644 --- a/configs/pg_wcom_expu1_update_defconfig +++ b/configs/pg_wcom_expu1_update_defconfig @@ -65,6 +65,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig index 56db37b7aa5..8ca1a60e111 100644 --- a/configs/pg_wcom_seli8_defconfig +++ b/configs/pg_wcom_seli8_defconfig @@ -67,6 +67,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig index b340b1fb1d2..5575ee8115f 100644 --- a/configs/pg_wcom_seli8_update_defconfig +++ b/configs/pg_wcom_seli8_update_defconfig @@ -65,6 +65,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 606a7fdee03..62aa341d6a1 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -41,6 +41,7 @@ CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index febf8f28065..791a26c0e10 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -43,6 +43,7 @@ CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index 9470beed32a..0d8c9d54577 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -68,6 +68,7 @@ CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index ea94d5c6ee9..de9cfd9bab1 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -62,6 +62,7 @@ CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_RENESAS_RPC_HF=y diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index d4dc8ecc51f..5fb27d257af 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -69,6 +69,7 @@ CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig index 3a5e43390ee..ade9286e25d 100644 --- a/configs/rcar3_ulcb_defconfig +++ b/configs/rcar3_ulcb_defconfig @@ -70,6 +70,7 @@ CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y +CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index bde3004171a..588ebe9119b 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -52,6 +52,13 @@ config CFI_FLASH option. Visit for more information on CFI. +config CFI_FLASH_USE_WEAK_ACCESSORS + bool "Allow read/write functions to be overridden" + depends on FLASH_CFI_DRIVER + help + Enable this option to allow for the flash_{read,write}{8,16,32,64} + functions to be overridden by the platform. + config SYS_FLASH_USE_BUFFER_WRITE bool "Enable buffered writes to flash" depends on FLASH_CFI_DRIVER diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index baab7c0f479..a7c47c79b35 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -372,7 +372,6 @@ #ifdef CONFIG_FSL_DIU_FB #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) #define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS /* * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so * disable empty flash sector detection, which is I/O-intensive. diff --git a/include/configs/blanche.h b/include/configs/blanche.h index 2135ba700e9..4f8da594043 100644 --- a/include/configs/blanche.h +++ b/include/configs/blanche.h @@ -29,7 +29,6 @@ #define CONFIG_SH_QSPI_BASE 0xE6B10000 #else #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_FLASH_BASE 0x00000000 #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ diff --git a/include/configs/draak.h b/include/configs/draak.h index e3e2b6a0bdd..c66a481dadb 100644 --- a/include/configs/draak.h +++ b/include/configs/draak.h @@ -19,7 +19,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h index 178b050a12f..cbd1445636f 100644 --- a/include/configs/ebisu.h +++ b/include/configs/ebisu.h @@ -21,7 +21,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 8453be84959..7b3e1d7188c 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -75,7 +75,6 @@ #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS #define CONFIG_SYS_WRITE_SWAPPED_DATA #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 8c4cb7b7205..864584bbbe9 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -99,7 +99,6 @@ #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS #define CONFIG_SYS_WRITE_SWAPPED_DATA #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index dcee79de884..38bcb5cae31 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -121,7 +121,6 @@ #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS #define CONFIG_SYS_WRITE_SWAPPED_DATA #endif diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index ea6831bb827..eb95f53a776 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -92,7 +92,6 @@ #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS #define CONFIG_SYS_WRITE_SWAPPED_DATA /* diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 31b578ae33b..dbeafe33579 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -62,7 +62,6 @@ #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS #define CONFIG_SYS_WRITE_SWAPPED_DATA /* diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 3d72c67a54f..d77119a7b22 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -105,7 +105,6 @@ #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS #define CONFIG_SYS_WRITE_SWAPPED_DATA /* diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index d45f6068607..f5811076072 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -67,6 +67,5 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MAX_FLASH_SECT 256 /* Sector: 256K, Bank: 64M */ -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS #endif /* __CONFIG_H */ diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 9542b0d1b59..1b3aa304d69 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -19,7 +19,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index ca79b0352ad..57e6863cc43 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -19,7 +19,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -- cgit v1.3.1 From f9147d636ce26eec8719ce8167887736c321ef94 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 25 Feb 2022 11:19:53 -0500 Subject: Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang Cc: Pramod Kumar Cc: Priyanka Jain Cc: Rajesh Bhagat Cc: Vladimir Oltean Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/ls102xa/Kconfig | 2 +- arch/arm/cpu/armv7/ls102xa/soc.c | 2 ++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 +++- configs/MPC8548CDS_36BIT_defconfig | 1 + configs/MPC8548CDS_defconfig | 1 + configs/MPC8548CDS_legacy_defconfig | 1 + configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PA_NAND_defconfig | 1 + configs/P1010RDB-PA_NOR_defconfig | 1 + configs/P1010RDB-PA_SDCARD_defconfig | 1 + configs/P1010RDB-PA_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_NAND_defconfig | 1 + configs/P1010RDB-PB_NOR_defconfig | 1 + configs/P1010RDB-PB_SDCARD_defconfig | 1 + configs/P1010RDB-PB_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_defconfig | 1 + configs/P1020RDB-PC_NAND_defconfig | 1 + configs/P1020RDB-PC_SDCARD_defconfig | 1 + configs/P1020RDB-PC_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_defconfig | 1 + configs/P1020RDB-PD_NAND_defconfig | 1 + configs/P1020RDB-PD_SDCARD_defconfig | 1 + configs/P1020RDB-PD_SPIFLASH_defconfig | 1 + configs/P1020RDB-PD_defconfig | 1 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_36BIT_defconfig | 1 + configs/P2020RDB-PC_NAND_defconfig | 1 + configs/P2020RDB-PC_SDCARD_defconfig | 1 + configs/P2020RDB-PC_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_defconfig | 1 + configs/T1042D4RDB_NAND_defconfig | 1 + configs/T1042D4RDB_SDCARD_defconfig | 1 + configs/T1042D4RDB_SPIFLASH_defconfig | 1 + configs/T1042D4RDB_defconfig | 1 + configs/kmcent2_defconfig | 1 + configs/qemu-ppce500_defconfig | 1 + configs/socrates_defconfig | 1 + drivers/ddr/fsl/Kconfig | 4 ++++ include/configs/MPC8548CDS.h | 1 - include/configs/P1010RDB.h | 1 - include/configs/P2041RDB.h | 1 - include/configs/T102xRDB.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/corenet_ds.h | 1 - include/configs/km/pg-wcom-ls102xa.h | 1 - include/configs/kmcent2.h | 1 - include/configs/kontron_sl28.h | 1 - include/configs/ls1012a2g5rdb.h | 1 - include/configs/ls1012afrdm.h | 2 -- include/configs/ls1012afrwy.h | 2 -- include/configs/ls1012aqds.h | 1 - include/configs/ls1012ardb.h | 1 - include/configs/ls1021aiot.h | 2 -- include/configs/ls1021aqds.h | 1 - include/configs/ls1021atsn.h | 2 -- include/configs/ls1021atwr.h | 2 -- include/configs/ls1028a_common.h | 1 - include/configs/ls1043aqds.h | 1 - include/configs/ls1043ardb.h | 1 - include/configs/ls1046afrwy.h | 1 - include/configs/ls1046aqds.h | 1 - include/configs/ls1046ardb.h | 1 - include/configs/ls1088a_common.h | 1 - include/configs/ls2080a_common.h | 1 - include/configs/ls2080aqds.h | 1 - include/configs/ls2080ardb.h | 1 - include/configs/lx2160a_common.h | 1 - include/configs/p1_p2_rdb_pc.h | 2 -- include/configs/qemu-ppce500.h | 2 -- include/configs/socrates.h | 1 - 85 files changed, 56 insertions(+), 44 deletions(-) (limited to 'drivers') diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 6a948d7ba7f..ef1f45650f3 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -5,7 +5,7 @@ config ARCH_LS1021A select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008407 - select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A008850 if SYS_FSL_DDR select SYS_FSL_ERRATUM_A008997 if USB select SYS_FSL_ERRATUM_A009007 if USB select SYS_FSL_ERRATUM_A009008 if USB diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 8a95ee86a9b..c131d92b993 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -12,7 +12,9 @@ #include #include #include +#ifdef CONFIG_SYS_FSL_ERRATUM_A008850 #include +#endif struct liodn_id_table sec_liodn_tbl[] = { SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 2ded3e4efc9..177f568f26e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -36,6 +35,7 @@ #endif #include #ifdef CONFIG_SYS_FSL_DDR +#include #include #endif #include @@ -1632,11 +1632,13 @@ void update_early_mmu_table(void) __weak int dram_init(void) { +#ifdef CONFIG_SYS_FSL_DDR fsl_initdram(); #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); +#endif #endif return 0; diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index e040e5dc09e..76d2b551a7a 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -33,6 +33,7 @@ CONFIG_ENV_ADDR=0xFFF60000 CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="8548cds/uImage.uboot" CONFIG_DM=y +CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index c508d61055f..6a550874689 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -32,6 +32,7 @@ CONFIG_ENV_ADDR=0xFFF60000 CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="8548cds/uImage.uboot" CONFIG_DM=y +CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index d6addc7ed16..ae262bf66d0 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -32,6 +32,7 @@ CONFIG_ENV_ADDR=0xFFF60000 CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="8548cds/uImage.uboot" CONFIG_DM=y +CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index b1bb2c552d1..0782dce8ecc 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -59,6 +59,7 @@ CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_TPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index 02af639e3bb..9c0df849985 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -41,6 +41,7 @@ CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index a9ecce9af4b..5804ba7d3a4 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -53,6 +53,7 @@ CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index d7248b1976d..bcf82ebba4e 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -55,6 +55,7 @@ CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index 132ed6982a2..a1cd44b1628 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -58,6 +58,7 @@ CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_TPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 31bcb475cd5..3ce8e3f646b 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -40,6 +40,7 @@ CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index c3b10b58148..7a6b19cccbc 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -52,6 +52,7 @@ CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index 2e50fc8e4f5..22798d8ec80 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -54,6 +54,7 @@ CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 0dc8322159f..f861734e2ff 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -60,6 +60,7 @@ CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_TPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 95366b24c60..80a8f4e48f0 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -42,6 +42,7 @@ CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 5a6b8550ceb..4082cef228f 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -54,6 +54,7 @@ CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 656029df8c6..4b581682e26 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -56,6 +56,7 @@ CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 77619350987..d8e588249e6 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -59,6 +59,7 @@ CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_TPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 19e54a8de89..bec233f645a 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -41,6 +41,7 @@ CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 598bacc5d40..f8a795df3f7 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -53,6 +53,7 @@ CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index cbe6df6a186..510ff5e6dcb 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -55,6 +55,7 @@ CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index e1e320dbef4..b499ec3a643 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -57,6 +57,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8396 diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 00661d91be2..530693b5b60 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -52,6 +52,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 6467032bd48..75e58512cd6 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -54,6 +54,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 3009e2954e1..79afdab0a81 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -41,6 +41,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 965eb7d2a11..44a4ec99e51 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -56,6 +56,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8396 diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 6130ba7842f..7e06a9aff73 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -51,6 +51,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 9c0547cb620..da35cddf7dd 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -53,6 +53,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 353d9236ca5..c8919b77999 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -40,6 +40,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 919c0d0ff6e..cfc73c44043 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -59,6 +59,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8796 diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 9d5d3faf83f..2d3577309fd 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -54,6 +54,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEC001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index e5b32daf350..bce232e99d3 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -56,6 +56,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEC001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index 632a3ed9b87..5b1031796b1 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -43,6 +43,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEC001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index ad57ba07242..1731d4fc73e 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -61,6 +61,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8396 diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 4dc11436f28..6662fe96169 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -56,6 +56,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 2078af27f76..d9d1f8b7908 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -58,6 +58,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 95202dc12b8..6111d3b76ff 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -45,6 +45,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index f736336cf7c..9e0de443fa1 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -60,6 +60,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8396 diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 0e50bb26ca0..cbe30d3062a 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -55,6 +55,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 4dbce7e36cb..7f735008147 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -57,6 +57,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 77b16b738ad..728336e065a 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -44,6 +44,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=1 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index a6480e95fe0..76747d40e55 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -57,6 +57,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 418addce48d..a8d1fbe0242 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -56,6 +56,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 922c3bb97cb..97345114d33 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -58,6 +58,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 470fa85bfa3..a73bbb0e729 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -41,6 +41,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_DM_I2C=y diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index 32c9f49cb0d..40f471ec22c 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -48,6 +48,7 @@ CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_SYS_FSL_DDR3=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_FSL=y diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index e6c998d8f87..3b3632f39d7 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -37,6 +37,7 @@ CONFIG_DM=y CONFIG_SIMPLE_BUS_CORRECT_RANGE=y CONFIG_BLK=y CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_CHIP_SELECTS_PER_CTRL=0 CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_FSL=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index 034d299d872..e24be7a853f 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -46,6 +46,7 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR=0xFFF40000 CONFIG_ENV_ADDR_REDUND=0xFFF20000 CONFIG_DM=y +CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFE001001 CONFIG_SYS_OR0_PRELIM=0xFE000030 diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index b0e6df8be41..27716706043 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -49,6 +49,10 @@ config SYS_NUM_DDR_CTLRS ARCH_LX2162A default 1 +config CHIP_SELECTS_PER_CTRL + int "Number of chip selects per controller" + default 4 + config SYS_FSL_DDR_VER int default 50 if SYS_FSL_DDR_VER_50 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 08ab80026f4..093061b52ff 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -48,7 +48,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) /* I2C addresses of SPD EEPROMs */ #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index a9c4930d770..5f36951932d 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -170,7 +170,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 /* DDR3 Controller Settings */ #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 38341984a02..045d9114933 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -93,7 +93,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x52 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index a7c47c79b35..f803b51f458 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -152,7 +152,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #if defined(CONFIG_TARGET_T1024RDB) #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 7365ee4a2ac..8a71807679e 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -132,7 +132,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index fec70fe739e..76e00cc095d 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -117,7 +117,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 2 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 0c47b2ddf11..35064fec7e4 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -112,7 +112,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 15a088ff225..8c9e5806e0b 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -93,7 +93,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 /* * IFC Definitions diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index a67a89a1148..c5a8567e1f6 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -96,7 +96,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 7b3e1d7188c..97f64530456 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -23,7 +23,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x54 diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 52a5ff9382e..707926f324c 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -175,7 +175,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x54 diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 448749a7f81..9eeb7ef9bfc 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -19,7 +19,6 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define CONFIG_VERY_BIG_RAM -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index 0263bb82893..8191c856a93 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -10,7 +10,6 @@ /* DDR */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 /* SATA */ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index ef57cf6aaa3..7735a005e20 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -10,9 +10,7 @@ /* DDR */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 #ifndef CONFIG_SPL_BUILD #undef BOOT_TARGET_DEVICES diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index c61865ccd4e..7d8d6ee085f 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -14,10 +14,8 @@ #define BOARD_REV_MASK 0x001A0000 /* DDR */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define SYS_SDRAM_SIZE_512 0x20000000 #define SYS_SDRAM_SIZE_1024 0x40000000 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 /* ENV */ #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index cbcb3f72a56..d57f28e4967 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -11,7 +11,6 @@ /* DDR */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 /* diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index c9a152e08a2..c51c4f2d3ea 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -11,7 +11,6 @@ /* DDR */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 /* diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 2e5b804a4cb..4e5228aa219 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -59,8 +59,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 - /* * Serial Port */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 864584bbbe9..b6501e87b41 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -54,7 +54,6 @@ #define CONFIG_SYS_DDR_RAW_TIMING #endif #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 5f6c2a00370..824078dd27d 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -77,8 +77,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 - /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL #ifndef CONFIG_DM_SERIAL diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 38bcb5cae31..fada8aa61db 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -79,8 +79,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 - /* * IFC Definitions */ diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index a517346c129..8bdfddcbc75 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -40,7 +40,6 @@ /* Miscellaneous configurable options */ /* Physical Memory Map */ -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index eb95f53a776..e9919cd05f7 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -12,7 +12,6 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Physical Memory Map */ -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index dbeafe33579..c904c9ca90b 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -12,7 +12,6 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Physical Memory Map */ -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index 14ad84a1ef4..8425d17992c 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -11,7 +11,6 @@ #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 #define CONFIG_SYS_UBOOT_BASE 0x40100000 diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index d77119a7b22..2972e3beac2 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -12,7 +12,6 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Physical Memory Map */ -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 8ed1dceb234..f6ff6903292 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -13,7 +13,6 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Physical Memory Map */ -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 33b70c8d8f6..965fdfead24 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -132,7 +132,6 @@ unsigned long long get_qixis_addr(void); #endif /* Physical Memory Map */ -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index f2725af0534..766da3969d2 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -139,7 +139,6 @@ unsigned long long get_qixis_addr(void); /* Physical Memory Map */ /* fixme: these need to be checked against the board */ -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 7554de1f6d3..1c59a89dbcf 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -27,7 +27,6 @@ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ #define CONFIG_DIMM_SLOTS_PER_CTLR 2 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 #endif diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 1c05b086778..de77872a709 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -37,7 +37,6 @@ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ #define CONFIG_DIMM_SLOTS_PER_CTLR 2 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 #endif diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index e31f8d087f7..c407fa8ba17 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -34,7 +34,6 @@ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ #define CONFIG_DIMM_SLOTS_PER_CTLR 2 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 #define CONFIG_SYS_MONITOR_LEN (936 * 1024) /* Miscellaneous configurable options */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 3a7adcc3f56..926318993ae 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -164,10 +164,8 @@ #if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 #else #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 #endif #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 88b3045efb1..296361aa038 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -43,8 +43,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_CHIP_SELECTS_PER_CTRL 0 - #define CONFIG_SYS_BOOT_BLOCK 0x00000000 /* boot TLB */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 482a920d33e..4d562d49c97 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -60,7 +60,6 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 /* I2C addresses of SPD EEPROMs */ #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ -- cgit v1.3.1 From c2b74edf156ca60af26e87fdfce13025b4312857 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 23 Feb 2022 15:10:33 +0100 Subject: mtd: nand: Update driver to match new DT binding New binding changed node name from flash@e1000000 to nand-controller@0,0 which should be reflected in the driver. Both names are supported for backward compatibility. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/61f6edd965e0c0b179184823d5283c6c61a1eb35.1645625433.git.michal.simek@xilinx.com --- drivers/mtd/nand/raw/zynq_nand.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c index d7925283706..10e9cd18b07 100644 --- a/drivers/mtd/nand/raw/zynq_nand.c +++ b/drivers/mtd/nand/raw/zynq_nand.c @@ -1086,10 +1086,13 @@ static int zynq_nand_probe(struct udevice *dev) int is_16bit_bw; smc->reg = (struct zynq_nand_smc_regs *)dev_read_addr(dev); - of_nand = dev_read_subnode(dev, "flash@e1000000"); + of_nand = dev_read_subnode(dev, "nand-controller@0,0"); if (!ofnode_valid(of_nand)) { - printf("Failed to find nand node in dt\n"); - return -ENODEV; + of_nand = dev_read_subnode(dev, "flash@e1000000"); + if (!ofnode_valid(of_nand)) { + printf("Failed to find nand node in dt\n"); + return -ENODEV; + } } if (!ofnode_is_available(of_nand)) { -- cgit v1.3.1 From c252b2774782360fd8785230072bb6c262a06709 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 23 Feb 2022 15:13:30 +0100 Subject: mmc: zynq_sdhci: Fix timeout issue In the workaround added with 'commit b6f44082d5cd ("mmc: zynq_sdhci: Wait till sd card detect state is stable")' the timeout variable has post decrement. Whenever timeout happens, this post decrement is making timeout=0xffffffff, so timeout error print and return statement are never reached. Fix it by decrementing it inside the while loop. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/61fc1160ada0dd622cd29e381a74af7bf3d9a200.1645625609.git.michal.simek@xilinx.com --- drivers/mmc/zynq_sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 5cea4c695e8..f4d69a2f709 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -773,8 +773,9 @@ static int arasan_sdhci_probe(struct udevice *dev) u32 timeout = 1000; while (((sdhci_readl(host, SDHCI_PRESENT_STATE) & - SDHCI_CARD_STATE_STABLE) == 0) && timeout--) { + SDHCI_CARD_STATE_STABLE) == 0) && timeout) { mdelay(1); + timeout--; } if (!timeout) { dev_err(dev, "Sdhci card detect state not stable\n"); -- cgit v1.3.1 From 8d32bca20535dea2f10d910b6458aec75d0c3fd9 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 23 Feb 2022 15:13:31 +0100 Subject: mmc: zynq_sdhci: Change granularity of timeout to 1us The timeout used in 'commit b6f44082d5cd ("mmc: zynq_sdhci: Wait till sd card detect state is stable")' workaround is 1000ms at a granularity of 1msec. Change it to 1usec, to not waste time incase the cd is stable. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f008d2bcf864702a01564789f14f9cdecb8acd45.1645625609.git.michal.simek@xilinx.com --- drivers/mmc/zynq_sdhci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index f4d69a2f709..7d62d05eda7 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -770,11 +770,11 @@ static int arasan_sdhci_probe(struct udevice *dev) * 1000msec till the card detect state gets stable. */ if (IS_ENABLED(CONFIG_ARCH_VERSAL)) { - u32 timeout = 1000; + u32 timeout = 1000000; while (((sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_STATE_STABLE) == 0) && timeout) { - mdelay(1); + udelay(1); timeout--; } if (!timeout) { -- cgit v1.3.1 From 980e55518fd9962ee4768a0f2c2f9382a2e11f8e Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 23 Feb 2022 15:13:32 +0100 Subject: mmc: zynq_sdhci: Enable card detect workaround for ZynqMP Card detect state stable issue is observed on few ZynqMP boards(SOM), so enable the workaround 'commit b6f44082d5cd ("mmc: zynq_sdhci: Wait till sd card detect state is stable")' for ZynqMP platforms also. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/0bf6154c79f24227d786efc5e2c1f506185b2bce.1645625609.git.michal.simek@xilinx.com --- drivers/mmc/zynq_sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 7d62d05eda7..33d00b06c77 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -769,7 +769,7 @@ static int arasan_sdhci_probe(struct udevice *dev) * causing sd card timeout error. Workaround this by adding a wait for * 1000msec till the card detect state gets stable. */ - if (IS_ENABLED(CONFIG_ARCH_VERSAL)) { + if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) || IS_ENABLED(CONFIG_ARCH_VERSAL)) { u32 timeout = 1000000; while (((sdhci_readl(host, SDHCI_PRESENT_STATE) & -- cgit v1.3.1 From 15efe0f3a57fc783526769fdd245bc2ebdbe2588 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Wed, 23 Feb 2022 16:21:30 +0100 Subject: gpio: slg7xl45106: Add support for slg7xl45106 i2c gpo expander slg7xl45106 is i2c based 8-bit gpo expander, gpo pins are set and get by writing and reading corresponding gpo bit value into its data register. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek Reviewed-by: Heiko Schocher Reviewed-by: Simon Glass Link: https://lore.kernel.org/r/839f475cc75c97ffb3496a4caa93de2faabdbca2.1645629688.git.michal.simek@xilinx.com --- MAINTAINERS | 1 + drivers/gpio/Kconfig | 8 +++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio_slg7xl45106.c | 115 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 125 insertions(+) create mode 100644 drivers/gpio/gpio_slg7xl45106.c (limited to 'drivers') diff --git a/MAINTAINERS b/MAINTAINERS index 0f39bc6bc92..bb6ea06933f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -636,6 +636,7 @@ F: arch/arm/mach-zynqmp/ F: drivers/clk/clk_zynqmp.c F: driver/firmware/firmware-zynqmp.c F: drivers/fpga/zynqpl.c +F: drivers/gpio/gpio_slg7xl45106.c F: drivers/gpio/zynq_gpio.c F: drivers/gpio/zynqmp_gpio_modepin.c F: drivers/i2c/i2c-cdns.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 522dfc195ec..a9e9b30f6c2 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -550,4 +550,12 @@ config SL28CPLD_GPIO help Support GPIO access on Kontron sl28cpld board management controllers. +config SLG7XL45106_I2C_GPO + bool "slg7xl45106 i2c gpo expander" + depends on DM_GPIO + help + Support for slg7xl45106 i2c gpo expander. It is an i2c based + 8-bit gpo expander, all gpo lines are controlled by writing + value into data register. + endif diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 33f7d41b7db..b2e78b0570e 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -72,3 +72,4 @@ obj-$(CONFIG_NOMADIK_GPIO) += nmk_gpio.o obj-$(CONFIG_MAX7320_GPIO) += max7320_gpio.o obj-$(CONFIG_SL28CPLD_GPIO) += sl28cpld-gpio.o obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o +obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o diff --git a/drivers/gpio/gpio_slg7xl45106.c b/drivers/gpio/gpio_slg7xl45106.c new file mode 100644 index 00000000000..2cbf7488ad6 --- /dev/null +++ b/drivers/gpio/gpio_slg7xl45106.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * slg7xl45106_i2c_gpo driver + * + * Copyright (C) 2021 Xilinx, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SLG7XL45106_REG 0xdb + +static int slg7xl45106_i2c_gpo_direction_input(struct udevice *dev, + unsigned int offset) +{ + return 0; +} + +static int slg7xl45106_i2c_gpo_xlate(struct udevice *dev, + struct gpio_desc *desc, + struct ofnode_phandle_args *args) +{ + desc->offset = (unsigned int)args->args[0]; + + return 0; +} + +static int slg7xl45106_i2c_gpo_set_value(struct udevice *dev, + unsigned int offset, int value) +{ + int ret; + u8 val; + + ret = dm_i2c_read(dev, SLG7XL45106_REG, &val, 1); + if (ret) + return ret; + + if (value) + val |= BIT(offset); + else + val &= ~BIT(offset); + + return dm_i2c_write(dev, SLG7XL45106_REG, &val, 1); +} + +static int slg7xl45106_i2c_gpo_direction_output(struct udevice *dev, + unsigned int offset, int value) +{ + return slg7xl45106_i2c_gpo_set_value(dev, offset, value); +} + +static int slg7xl45106_i2c_gpo_get_value(struct udevice *dev, + unsigned int offset) +{ + int ret; + u8 val; + + ret = dm_i2c_read(dev, SLG7XL45106_REG, &val, 1); + if (ret) + return ret; + + return !!(val & BIT(offset)); +} + +static int slg7xl45106_i2c_gpo_get_function(struct udevice *dev, + unsigned int offset) +{ + return GPIOF_OUTPUT; +} + +static const struct dm_gpio_ops slg7xl45106_i2c_gpo_ops = { + .direction_input = slg7xl45106_i2c_gpo_direction_input, + .direction_output = slg7xl45106_i2c_gpo_direction_output, + .get_value = slg7xl45106_i2c_gpo_get_value, + .set_value = slg7xl45106_i2c_gpo_set_value, + .get_function = slg7xl45106_i2c_gpo_get_function, + .xlate = slg7xl45106_i2c_gpo_xlate, +}; + +static int slg7xl45106_i2c_gpo_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + const void *label_ptr; + + label_ptr = dev_read_prop(dev, "label", NULL); + if (label_ptr) { + uc_priv->bank_name = strdup(label_ptr); + if (!uc_priv->bank_name) + return -ENOMEM; + } else { + uc_priv->bank_name = dev->name; + } + + uc_priv->gpio_count = 8; + + return 0; +} + +static const struct udevice_id slg7xl45106_i2c_gpo_ids[] = { + { .compatible = "dlg,slg7xl45106",}, + { } +}; + +U_BOOT_DRIVER(slg7xl45106_i2c_gpo) = { + .name = "slg7xl45106_i2c_gpo", + .id = UCLASS_GPIO, + .ops = &slg7xl45106_i2c_gpo_ops, + .of_match = slg7xl45106_i2c_gpo_ids, + .probe = slg7xl45106_i2c_gpo_probe, +}; -- cgit v1.3.1 From fda7cbfefd44448dc275508942b59fb38480c156 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 1 Mar 2022 09:10:59 +0100 Subject: power: zynqmp: Use zynqmp_pmufw_node() from firmware Remove private xpm_configobject[] and use zynqmp_pmufw_node() which provides the same functionality. Also add debug messages for easier debugging. Fixes: e0283cbdfd49 ("power: zynqmp: Add power domain driver for ZynqMP") Signed-off-by: Michal Simek Reviewed-by: Jaehoon Chung Link: https://lore.kernel.org/r/bddf11459b9b9e849fac9a50db2f1a5fdfae4119.1646122254.git.michal.simek@xilinx.com --- drivers/power/domain/zynqmp-power-domain.c | 29 +++++------------------------ 1 file changed, 5 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/power/domain/zynqmp-power-domain.c b/drivers/power/domain/zynqmp-power-domain.c index 5383d098969..6943658be42 100644 --- a/drivers/power/domain/zynqmp-power-domain.c +++ b/drivers/power/domain/zynqmp-power-domain.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -13,25 +14,6 @@ #include -#define NODE_ID_LOCATION 5 - -static unsigned int xpm_configobject[] = { - /* HEADER */ - 2, /* Number of remaining words in the header */ - 1, /* Number of sections included in config object */ - PM_CONFIG_OBJECT_TYPE_OVERLAY, /* Type of Config object as overlay */ - /* SLAVE SECTION */ - - PM_CONFIG_SLAVE_SECTION_ID, /* Section ID */ - 1, /* Number of slaves */ - - 0, /* Node ID which will be changed below */ - PM_SLAVE_FLAG_IS_SHAREABLE, - PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | - PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | - PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ -}; - static int zynqmp_pm_request_node(const u32 node, const u32 capabilities, const u32 qos, const enum zynqmp_pm_request_ack ack) { @@ -41,12 +23,9 @@ static int zynqmp_pm_request_node(const u32 node, const u32 capabilities, static int zynqmp_power_domain_request(struct power_domain *power_domain) { - /* Record power domain id */ - xpm_configobject[NODE_ID_LOCATION] = power_domain->id; - - zynqmp_pmufw_load_config_object(xpm_configobject, sizeof(xpm_configobject)); + dev_dbg(power_domain->dev, "Request for id: %ld\n", power_domain->id); - return 0; + return zynqmp_pmufw_node(power_domain->id); } static int zynqmp_power_domain_free(struct power_domain *power_domain) @@ -57,6 +36,8 @@ static int zynqmp_power_domain_free(struct power_domain *power_domain) static int zynqmp_power_domain_on(struct power_domain *power_domain) { + dev_dbg(power_domain->dev, "Domain ON for id: %ld\n", power_domain->id); + return zynqmp_pm_request_node(power_domain->id, ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS, -- cgit v1.3.1 From c19eaef7e0addbbe4f5bf316febe010a110ecdac Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Fri, 11 Feb 2022 19:18:35 +0100 Subject: gpio: bcm6345: allow to use this driver on arm bcm6753 This IP is also used on some arm SoC, so we allow to use it on arm bcm6753 too. Signed-off-by: Philippe Reynes --- drivers/gpio/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 8d0e47c67d9..1c963c2c536 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -87,7 +87,8 @@ config ALTERA_PIO config BCM6345_GPIO bool "BCM6345 GPIO driver" depends on DM_GPIO && (ARCH_BMIPS || ARCH_BCM68360 || \ - ARCH_BCM6858 || ARCH_BCM63158) + ARCH_BCM6858 || ARCH_BCM63158 || \ + ARCH_BCM6753) help This driver supports the GPIO banks on BCM6345 SoCs. -- cgit v1.3.1 From 0d32ebfcfab0f947c23d2cd24836d514aeb58b82 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Fri, 11 Feb 2022 19:18:36 +0100 Subject: nand: brcmnand: add bcm6753 support This adds the nand support for chipset bcm6753. Signed-off-by: Philippe Reynes --- drivers/mtd/nand/raw/Kconfig | 6 ++ drivers/mtd/nand/raw/brcmnand/Makefile | 1 + drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c | 124 +++++++++++++++++++++++++++ 3 files changed, 131 insertions(+) create mode 100644 drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c (limited to 'drivers') diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 0e826c19298..1eab21e2064 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -91,6 +91,12 @@ config NAND_BRCMNAND_6368 help Enable support for broadcom nand driver on bcm6368. +config NAND_BRCMNAND_6753 + bool "Support Broadcom NAND controller on bcm6753" + depends on NAND_BRCMNAND && ARCH_BCM6753 + help + Enable support for broadcom nand driver on bcm6753. + config NAND_BRCMNAND_68360 bool "Support Broadcom NAND controller on bcm68360" depends on NAND_BRCMNAND && ARCH_BCM68360 diff --git a/drivers/mtd/nand/raw/brcmnand/Makefile b/drivers/mtd/nand/raw/brcmnand/Makefile index 5d9e7e3f3b5..f46a7edae32 100644 --- a/drivers/mtd/nand/raw/brcmnand/Makefile +++ b/drivers/mtd/nand/raw/brcmnand/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_NAND_BRCMNAND_6368) += bcm6368_nand.o obj-$(CONFIG_NAND_BRCMNAND_63158) += bcm63158_nand.o +obj-$(CONFIG_NAND_BRCMNAND_6753) += bcm6753_nand.o obj-$(CONFIG_NAND_BRCMNAND_68360) += bcm68360_nand.o obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c new file mode 100644 index 00000000000..feae66ef25a --- /dev/null +++ b/drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "brcmnand.h" + +struct bcm6753_nand_soc { + struct brcmnand_soc soc; + void __iomem *base; +}; + +#define BCM6753_NAND_INT 0x00 +#define BCM6753_NAND_STATUS_SHIFT 0 +#define BCM6753_NAND_STATUS_MASK (0xfff << BCM6753_NAND_STATUS_SHIFT) + +#define BCM6753_NAND_INT_EN 0x04 +#define BCM6753_NAND_ENABLE_SHIFT 0 +#define BCM6753_NAND_ENABLE_MASK (0xffff << BCM6753_NAND_ENABLE_SHIFT) + +enum { + BCM6753_NP_READ = BIT(0), + BCM6753_BLOCK_ERASE = BIT(1), + BCM6753_COPY_BACK = BIT(2), + BCM6753_PAGE_PGM = BIT(3), + BCM6753_CTRL_READY = BIT(4), + BCM6753_DEV_RBPIN = BIT(5), + BCM6753_ECC_ERR_UNC = BIT(6), + BCM6753_ECC_ERR_CORR = BIT(7), +}; + +static bool bcm6753_nand_intc_ack(struct brcmnand_soc *soc) +{ + struct bcm6753_nand_soc *priv = + container_of(soc, struct bcm6753_nand_soc, soc); + void __iomem *mmio = priv->base + BCM6753_NAND_INT; + u32 val = brcmnand_readl(mmio); + + if (val & (BCM6753_CTRL_READY << BCM6753_NAND_STATUS_SHIFT)) { + /* Ack interrupt */ + val &= ~BCM6753_NAND_STATUS_MASK; + val |= BCM6753_CTRL_READY << BCM6753_NAND_STATUS_SHIFT; + brcmnand_writel(val, mmio); + return true; + } + + return false; +} + +static void bcm6753_nand_intc_set(struct brcmnand_soc *soc, bool en) +{ + struct bcm6753_nand_soc *priv = + container_of(soc, struct bcm6753_nand_soc, soc); + void __iomem *mmio = priv->base + BCM6753_NAND_INT_EN; + u32 val = brcmnand_readl(mmio); + + /* Don't ack any interrupts */ + val &= ~BCM6753_NAND_STATUS_MASK; + + if (en) + val |= BCM6753_CTRL_READY << BCM6753_NAND_ENABLE_SHIFT; + else + val &= ~(BCM6753_CTRL_READY << BCM6753_NAND_ENABLE_SHIFT); + + brcmnand_writel(val, mmio); +} + +static int bcm6753_nand_probe(struct udevice *dev) +{ + struct udevice *pdev = dev; + struct bcm6753_nand_soc *priv = dev_get_priv(dev); + struct brcmnand_soc *soc; + struct resource res; + + soc = &priv->soc; + + dev_read_resource_byname(pdev, "nand-int-base", &res); + priv->base = devm_ioremap(dev, res.start, resource_size(&res)); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + soc->ctlrdy_ack = bcm6753_nand_intc_ack; + soc->ctlrdy_set_enabled = bcm6753_nand_intc_set; + + /* Disable and ack all interrupts */ + brcmnand_writel(0, priv->base + BCM6753_NAND_INT_EN); + brcmnand_writel(0, priv->base + BCM6753_NAND_INT); + + return brcmnand_probe(pdev, soc); +} + +static const struct udevice_id bcm6753_nand_dt_ids[] = { + { + .compatible = "brcm,nand-bcm6753", + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(bcm6753_nand) = { + .name = "bcm6753-nand", + .id = UCLASS_MTD, + .of_match = bcm6753_nand_dt_ids, + .probe = bcm6753_nand_probe, + .priv_auto = sizeof(struct bcm6753_nand_soc), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(bcm6753_nand), &dev); + if (ret && ret != -ENODEV) + pr_err("Failed to initialize %s. (error %d)\n", dev->name, + ret); +} -- cgit v1.3.1 From 40ca58a8db158b320d545924bbf6730e7778dad5 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Fri, 11 Feb 2022 19:18:37 +0100 Subject: watchdog: bcm6345: allow to use this driver on arm bcm6753 This IP is also used on some arm SoC, so we allow to use it on arm bcm6753 too. Signed-off-by: Philippe Reynes --- drivers/watchdog/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index cabac290539..1f3ca99f9aa 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -129,7 +129,8 @@ config WDT_AT91 config WDT_BCM6345 bool "BCM6345 watchdog timer support" depends on WDT && (ARCH_BMIPS || ARCH_BCM68360 || \ - ARCH_BCM6858 || ARCH_BCM63158) + ARCH_BCM6858 || ARCH_BCM63158 || \ + ARCH_BCM6753) help Select this to enable watchdog timer for BCM6345 SoCs. The watchdog timer is stopped when initialized. -- cgit v1.3.1 From 0d2001b105b415f0cb974036696c6eb47d4dfe9c Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Thu, 17 Feb 2022 17:17:04 +0100 Subject: drivers: led: led_bcm6753: initial support Add the support of the LED IP for bcm6357. This LED IP supports blinking, fading and pulsating, but for the moment, only blinking is supported. Signed-off-by: Philippe Reynes --- drivers/led/Kconfig | 7 ++ drivers/led/Makefile | 1 + drivers/led/led_bcm6753.c | 270 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 278 insertions(+) create mode 100644 drivers/led/led_bcm6753.c (limited to 'drivers') diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index cc87fbf395b..430d0760ba5 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -28,6 +28,13 @@ config LED_BCM6358 LED HW controller accessed via MMIO registers. HW has no blinking capabilities and up to 32 LEDs can be controlled. +config LED_BCM6753 + bool "LED Support for BCM6753" + depends on LED && ARCH_BCM6753 + help + This option enables support for LEDs connected to the BCM6753 + HW has blinking and fading capabilities and up to 32 LEDs can be controlled. + config LED_BCM6858 bool "LED Support for BCM6858" depends on LED && (ARCH_BCM68360 || ARCH_BCM6858 || ARCH_BCM63158) diff --git a/drivers/led/Makefile b/drivers/led/Makefile index 8e3ae7f1465..2aa2c2173af 100644 --- a/drivers/led/Makefile +++ b/drivers/led/Makefile @@ -6,6 +6,7 @@ obj-y += led-uclass.o obj-$(CONFIG_LED_BCM6328) += led_bcm6328.o obj-$(CONFIG_LED_BCM6358) += led_bcm6358.o +obj-$(CONFIG_LED_BCM6753) += led_bcm6753.o obj-$(CONFIG_LED_BCM6858) += led_bcm6858.o obj-$(CONFIG_$(SPL_)LED_GPIO) += led_gpio.o obj-$(CONFIG_LED_CORTINA) += led_cortina.o diff --git a/drivers/led/led_bcm6753.c b/drivers/led/led_bcm6753.c new file mode 100644 index 00000000000..a32bd8204fa --- /dev/null +++ b/drivers/led/led_bcm6753.c @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Philippe Reynes + * + * based on: + * drivers/led/led_bcm6858.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define LEDS_MAX 32 +#define LEDS_WAIT 100 + +/* LED Mode register */ +#define LED_MODE_REG 0x0 +#define LED_MODE_OFF 0 +#define LED_MODE_ON 1 +#define LED_MODE_MASK 1 + +/* LED Controller Global settings register */ +#define CLED_CTRL_REG 0x00 +#define CLED_CTRL_SERIAL_LED_DATA_PPOL BIT(1) +#define CLED_CTRL_SERIAL_LED_CLK_POL BIT(2) +#define CLED_CTRL_SERIAL_LED_EN_POL BIT(3) +#define CLED_CTRL_SERIAL_LED_MSB_FIRST BIT(4) +#define CLED_CTRL_MASK 0x1E +/* LED Controller IP LED source select register */ +#define CLED_HW_LED_EN_REG 0x04 +/* Hardware LED Polarity register */ +#define CLED_HW_LED_IP_PPOL_REG 0x0c +/* Soft LED Set Register */ +#define CLED_SW_LED_IP_SET_REG 0x10 +/* Parallel LED Output Polarity Register */ +#define CLED_PLED_OP_PPOL_REG 0x18 +/* LED Channel activate register */ +#define CLED_LED_CH_ACTIVATE_REG 0x1c +/* LED 0 Config 0 reg */ +#define CLED_LED_0_CONFIG_0 0x20 +/* Soft LED Clear Register */ +#define CLED_SW_LED_IP_CLEAR_REG 0x444 +/* Soft LED Status Register */ +#define CLED_SW_LED_IP_STATUS_REG 0x448 + +/* Size of all registers used for the config of one LED */ +#define CLED_CONFIG_SIZE (4 * sizeof(u32)) + +#define CLED_CONFIG0_MODE 0 +#define CLED_CONFIG0_MODE_MASK (BIT(0) | BIT(1)) +#define CLED_CONFIG0_MODE_STEADY 0 +#define CLED_CONFIG0_MODE_FADING 1 +#define CLED_CONFIG0_MODE_PULSATING 2 + +#define CLED_CONFIG0_FLASH_CTRL_SHIFT 3 +#define CLED_CONFIG0_FLASH_CTRL_MASK (BIT(3) | BIT(4) | BIT(5)) + +struct bcm6753_led_priv { + void __iomem *regs; + u8 pin; +}; + +/* + * The value for flash rate are: + * 0 : no blinking + * 1 : rate is 25 Hz => 40 ms (period) + * 2 : rate is 12.5 Hz => 80 ms (period) + * 3 : rate is 6.25 Hz => 160 ms (period) + * 4 : rate is 3.125 Hz => 320 ms (period) + * 5 : rate is 1.5625 Hz => 640 ms (period) + * 6 : rate is 0.7815 Hz => 1280 ms (period) + * 7 : rate is 0.390625 Hz => 2560 ms (period) + */ +static const int bcm6753_flash_rate[8] = { + 0, 40, 80, 160, 320, 640, 1280, 2560 +}; + +static u32 bcm6753_flash_rate_value(int period_ms) +{ + unsigned long value = 7; + int i; + + for (i = 0; i < ARRAY_SIZE(bcm6753_flash_rate); i++) { + if (period_ms <= bcm6753_flash_rate[i]) { + value = i; + break; + } + } + + return value; +} + +static int bcm6753_led_set_period(struct udevice *dev, int period_ms) +{ + struct bcm6753_led_priv *priv = dev_get_priv(dev); + u32 offset, shift, value; + + offset = CLED_LED_0_CONFIG_0 + (CLED_CONFIG_SIZE * priv->pin); + value = bcm6753_flash_rate_value(period_ms); + shift = CLED_CONFIG0_FLASH_CTRL_SHIFT; + + /* set mode steady */ + clrbits_32(priv->regs + offset, CLED_CONFIG0_MODE_MASK); + setbits_32(priv->regs + offset, CLED_CONFIG0_MODE_STEADY); + + /* set flash rate */ + clrbits_32(priv->regs + offset, CLED_CONFIG0_FLASH_CTRL_MASK); + setbits_32(priv->regs + offset, value << shift); + + /* enable config */ + setbits_32(priv->regs + CLED_LED_CH_ACTIVATE_REG, 1 << priv->pin); + + return 0; +} + +static enum led_state_t bcm6753_led_get_state(struct udevice *dev) +{ + struct bcm6753_led_priv *priv = dev_get_priv(dev); + enum led_state_t state = LEDST_OFF; + u32 sw_led_ip_status; + + sw_led_ip_status = readl(priv->regs + CLED_SW_LED_IP_STATUS_REG); + if (sw_led_ip_status & (1 << priv->pin)) + state = LEDST_ON; + + return state; +} + +static int bcm6753_led_set_state(struct udevice *dev, enum led_state_t state) +{ + struct bcm6753_led_priv *priv = dev_get_priv(dev); + + switch (state) { + case LEDST_OFF: + setbits_32(priv->regs + CLED_SW_LED_IP_CLEAR_REG, (1 << priv->pin)); + if (IS_ENABLED(CONFIG_LED_BLINK)) + bcm6753_led_set_period(dev, 0); + break; + case LEDST_ON: + setbits_32(priv->regs + CLED_SW_LED_IP_SET_REG, (1 << priv->pin)); + if (IS_ENABLED(CONFIG_LED_BLINK)) + bcm6753_led_set_period(dev, 0); + break; + case LEDST_TOGGLE: + if (bcm6753_led_get_state(dev) == LEDST_OFF) + return bcm6753_led_set_state(dev, LEDST_ON); + else + return bcm6753_led_set_state(dev, LEDST_OFF); + break; +#ifdef CONFIG_LED_BLINK + case LEDST_BLINK: + setbits_32(priv->regs + CLED_SW_LED_IP_SET_REG, (1 << priv->pin)); + break; +#endif + default: + return -EINVAL; + } + + return 0; +} + +static const struct led_ops bcm6753_led_ops = { + .get_state = bcm6753_led_get_state, + .set_state = bcm6753_led_set_state, +#ifdef CONFIG_LED_BLINK + .set_period = bcm6753_led_set_period, +#endif +}; + +static int bcm6753_led_probe(struct udevice *dev) +{ + struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev); + + /* Top-level LED node */ + if (!uc_plat->label) { + void __iomem *regs; + u32 set_bits = 0; + + regs = dev_remap_addr(dev); + if (!regs) + return -EINVAL; + + if (dev_read_bool(dev, "brcm,serial-led-msb-first")) + set_bits |= CLED_CTRL_SERIAL_LED_MSB_FIRST; + if (dev_read_bool(dev, "brcm,serial-led-en-pol")) + set_bits |= CLED_CTRL_SERIAL_LED_EN_POL; + if (dev_read_bool(dev, "brcm,serial-led-clk-pol")) + set_bits |= CLED_CTRL_SERIAL_LED_CLK_POL; + if (dev_read_bool(dev, "brcm,serial-led-data-ppol")) + set_bits |= CLED_CTRL_SERIAL_LED_DATA_PPOL; + + clrsetbits_32(regs + CLED_CTRL_REG, CLED_CTRL_MASK, set_bits); + } else { + struct bcm6753_led_priv *priv = dev_get_priv(dev); + void __iomem *regs; + unsigned int pin; + + regs = dev_remap_addr(dev_get_parent(dev)); + if (!regs) + return -EINVAL; + + pin = dev_read_u32_default(dev, "reg", LEDS_MAX); + if (pin >= LEDS_MAX) + return -EINVAL; + + priv->regs = regs; + priv->pin = pin; + + /* this led is managed by software */ + clrbits_32(regs + CLED_HW_LED_EN_REG, 1 << pin); + + /* configure the polarity */ + if (dev_read_bool(dev, "active-low")) + clrbits_32(regs + CLED_PLED_OP_PPOL_REG, 1 << pin); + else + setbits_32(regs + CLED_PLED_OP_PPOL_REG, 1 << pin); + } + + return 0; +} + +static int bcm6753_led_bind(struct udevice *parent) +{ + ofnode node; + + dev_for_each_subnode(node, parent) { + struct led_uc_plat *uc_plat; + struct udevice *dev; + const char *label; + int ret; + + label = ofnode_read_string(node, "label"); + if (!label) { + debug("%s: node %s has no label\n", __func__, + ofnode_get_name(node)); + return -EINVAL; + } + + ret = device_bind_driver_to_node(parent, "bcm6753-led", + ofnode_get_name(node), + node, &dev); + if (ret) + return ret; + + uc_plat = dev_get_uclass_plat(dev); + uc_plat->label = label; + } + + return 0; +} + +static const struct udevice_id bcm6753_led_ids[] = { + { .compatible = "brcm,bcm6753-leds" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(bcm6753_led) = { + .name = "bcm6753-led", + .id = UCLASS_LED, + .of_match = bcm6753_led_ids, + .bind = bcm6753_led_bind, + .probe = bcm6753_led_probe, + .priv_auto = sizeof(struct bcm6753_led_priv), + .ops = &bcm6753_led_ops, +}; -- cgit v1.3.1 From 497f57cfc259d5fba4d1e5098c8fb90d43f14e96 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 18 Feb 2022 13:28:41 +0100 Subject: arm: mmc: Add "ti, am335-sdhci" compatible for TI's omap_hsmmc driver In the Linux kernel (v5.16) for this SoC there are two separate drivers - namely sdhci-omap.c and omap_hsmmc.c which have separate set of compatibles. The U-Boot's drivers/mmc/omap_hsmmc.c driver supports both eMMC and SD devices - hence the compatible for SDHCI can be added. After this change the am335x DTS description can be easier ported from Linux kernel. Signed-off-by: Lukasz Majewski Reviewed-by: Jaehoon Chung --- drivers/mmc/omap_hsmmc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 820065800fe..b2f4a4e7219 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -2019,6 +2019,7 @@ static const struct udevice_id omap_hsmmc_ids[] = { { .compatible = "ti,omap3-hsmmc" }, { .compatible = "ti,omap4-hsmmc" }, { .compatible = "ti,am33xx-hsmmc" }, + { .compatible = "ti,am335-sdhci" }, { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data }, { } }; -- cgit v1.3.1 From 7ad889b0f37a122b7cb8c2a43302914423d77292 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Wed, 16 Feb 2022 10:26:56 +1030 Subject: gpio: Add Aspeed GPIO driver The Aspeed GPIO driver supports the GPIO controllers found in the AST2400, AST2500 and AST2600 BMC SoCs. The implementation is a cut-down copy of the upstream Linux kernel driver, adapted for u-boot. Signed-off-by: Andrew Jeffery --- drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-aspeed.c | 299 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 307 insertions(+) create mode 100644 drivers/gpio/gpio-aspeed.c (limited to 'drivers') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 1c963c2c536..be64303d7f9 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -127,6 +127,13 @@ config ATMEL_PIO4 may be dedicated as a general purpose I/O or be assigned to a function of an embedded peripheral. +config ASPEED_GPIO + bool "Aspeed GPIO Driver" + help + Say yes here to support the Aspeed GPIO driver. The controller + is found in the AST2400, AST2500 and AST2600 BMC SoCs and + provides access to over 200 GPIOs on each chip. + config DA8XX_GPIO bool "DA8xx GPIO Driver" help diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 63e9be6034f..720297952cd 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_$(SPL_TPL_)DM_GPIO) += gpio-uclass.o obj-$(CONFIG_$(SPL_)DM_PCA953X) += pca953x_gpio.o +obj-$(CONFIG_ASPEED_GPIO) += gpio-aspeed.o obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c new file mode 100644 index 00000000000..a8a2afcb5c8 --- /dev/null +++ b/drivers/gpio/gpio-aspeed.c @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2015 IBM Corp. + * Joel Stanley + * Ryan Chen + * + * Implementation extracted from the Linux kernel and adapted for u-boot. + */ +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +struct aspeed_gpio_priv { + void *regs; +}; + +struct aspeed_gpio_bank { + u16 val_regs; /* +0: Rd: read input value, Wr: set write latch + * +4: Rd/Wr: Direction (0=in, 1=out) + */ + u16 rdata_reg; /* Rd: read write latch, Wr: */ + u16 irq_regs; + u16 debounce_regs; + u16 tolerance_regs; + u16 cmdsrc_regs; + const char names[4][3]; +}; + +static const struct aspeed_gpio_bank aspeed_gpio_banks[] = { + { + .val_regs = 0x0000, + .rdata_reg = 0x00c0, + .irq_regs = 0x0008, + .debounce_regs = 0x0040, + .tolerance_regs = 0x001c, + .cmdsrc_regs = 0x0060, + .names = { "A", "B", "C", "D" }, + }, + { + .val_regs = 0x0020, + .rdata_reg = 0x00c4, + .irq_regs = 0x0028, + .debounce_regs = 0x0048, + .tolerance_regs = 0x003c, + .cmdsrc_regs = 0x0068, + .names = { "E", "F", "G", "H" }, + }, + { + .val_regs = 0x0070, + .rdata_reg = 0x00c8, + .irq_regs = 0x0098, + .debounce_regs = 0x00b0, + .tolerance_regs = 0x00ac, + .cmdsrc_regs = 0x0090, + .names = { "I", "J", "K", "L" }, + }, + { + .val_regs = 0x0078, + .rdata_reg = 0x00cc, + .irq_regs = 0x00e8, + .debounce_regs = 0x0100, + .tolerance_regs = 0x00fc, + .cmdsrc_regs = 0x00e0, + .names = { "M", "N", "O", "P" }, + }, + { + .val_regs = 0x0080, + .rdata_reg = 0x00d0, + .irq_regs = 0x0118, + .debounce_regs = 0x0130, + .tolerance_regs = 0x012c, + .cmdsrc_regs = 0x0110, + .names = { "Q", "R", "S", "T" }, + }, + { + .val_regs = 0x0088, + .rdata_reg = 0x00d4, + .irq_regs = 0x0148, + .debounce_regs = 0x0160, + .tolerance_regs = 0x015c, + .cmdsrc_regs = 0x0140, + .names = { "U", "V", "W", "X" }, + }, + { + .val_regs = 0x01E0, + .rdata_reg = 0x00d8, + .irq_regs = 0x0178, + .debounce_regs = 0x0190, + .tolerance_regs = 0x018c, + .cmdsrc_regs = 0x0170, + .names = { "Y", "Z", "AA", "AB" }, + }, + { + .val_regs = 0x01e8, + .rdata_reg = 0x00dc, + .irq_regs = 0x01a8, + .debounce_regs = 0x01c0, + .tolerance_regs = 0x01bc, + .cmdsrc_regs = 0x01a0, + .names = { "AC", "", "", "" }, + }, +}; + +enum aspeed_gpio_reg { + reg_val, + reg_rdata, + reg_dir, + reg_irq_enable, + reg_irq_type0, + reg_irq_type1, + reg_irq_type2, + reg_irq_status, + reg_debounce_sel1, + reg_debounce_sel2, + reg_tolerance, + reg_cmdsrc0, + reg_cmdsrc1, +}; + +#define GPIO_VAL_VALUE 0x00 +#define GPIO_VAL_DIR 0x04 + +#define GPIO_IRQ_ENABLE 0x00 +#define GPIO_IRQ_TYPE0 0x04 +#define GPIO_IRQ_TYPE1 0x08 +#define GPIO_IRQ_TYPE2 0x0c +#define GPIO_IRQ_STATUS 0x10 + +#define GPIO_DEBOUNCE_SEL1 0x00 +#define GPIO_DEBOUNCE_SEL2 0x04 + +#define GPIO_CMDSRC_0 0x00 +#define GPIO_CMDSRC_1 0x04 +#define GPIO_CMDSRC_ARM 0 +#define GPIO_CMDSRC_LPC 1 +#define GPIO_CMDSRC_COLDFIRE 2 +#define GPIO_CMDSRC_RESERVED 3 + +/* This will be resolved at compile time */ +static inline void __iomem *bank_reg(struct aspeed_gpio_priv *gpio, + const struct aspeed_gpio_bank *bank, + const enum aspeed_gpio_reg reg) +{ + switch (reg) { + case reg_val: + return gpio->regs + bank->val_regs + GPIO_VAL_VALUE; + case reg_rdata: + return gpio->regs + bank->rdata_reg; + case reg_dir: + return gpio->regs + bank->val_regs + GPIO_VAL_DIR; + case reg_irq_enable: + return gpio->regs + bank->irq_regs + GPIO_IRQ_ENABLE; + case reg_irq_type0: + return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE0; + case reg_irq_type1: + return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE1; + case reg_irq_type2: + return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE2; + case reg_irq_status: + return gpio->regs + bank->irq_regs + GPIO_IRQ_STATUS; + case reg_debounce_sel1: + return gpio->regs + bank->debounce_regs + GPIO_DEBOUNCE_SEL1; + case reg_debounce_sel2: + return gpio->regs + bank->debounce_regs + GPIO_DEBOUNCE_SEL2; + case reg_tolerance: + return gpio->regs + bank->tolerance_regs; + case reg_cmdsrc0: + return gpio->regs + bank->cmdsrc_regs + GPIO_CMDSRC_0; + case reg_cmdsrc1: + return gpio->regs + bank->cmdsrc_regs + GPIO_CMDSRC_1; + } + BUG(); +} + +#define GPIO_BANK(x) ((x) >> 5) +#define GPIO_OFFSET(x) ((x) & 0x1f) +#define GPIO_BIT(x) BIT(GPIO_OFFSET(x)) + +static const struct aspeed_gpio_bank *to_bank(unsigned int offset) +{ + unsigned int bank = GPIO_BANK(offset); + + WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks)); + return &aspeed_gpio_banks[bank]; +} + +static int +aspeed_gpio_direction_input(struct udevice *dev, unsigned int offset) +{ + struct aspeed_gpio_priv *priv = dev_get_priv(dev); + const struct aspeed_gpio_bank *bank = to_bank(offset); + u32 dir = readl(bank_reg(priv, bank, reg_dir)); + + dir &= ~GPIO_BIT(offset); + writel(dir, bank_reg(priv, bank, reg_dir)); + + return 0; +} + +static int aspeed_gpio_direction_output(struct udevice *dev, unsigned int offset, + int value) +{ + struct aspeed_gpio_priv *priv = dev_get_priv(dev); + const struct aspeed_gpio_bank *bank = to_bank(offset); + u32 dir = readl(bank_reg(priv, bank, reg_dir)); + u32 output = readl(bank_reg(priv, bank, reg_val)); + + dir |= GPIO_BIT(offset); + writel(dir, bank_reg(priv, bank, reg_dir)); + + if (value) + output |= GPIO_BIT(offset); + else + output &= ~GPIO_BIT(offset); + + writel(output, bank_reg(priv, bank, reg_val)); + + return 0; +} + +static int aspeed_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct aspeed_gpio_priv *priv = dev_get_priv(dev); + const struct aspeed_gpio_bank *bank = to_bank(offset); + + return !!(readl(bank_reg(priv, bank, reg_val)) & GPIO_BIT(offset)); +} + +static int +aspeed_gpio_set_value(struct udevice *dev, unsigned int offset, int value) +{ + struct aspeed_gpio_priv *priv = dev_get_priv(dev); + const struct aspeed_gpio_bank *bank = to_bank(offset); + u32 data = readl(bank_reg(priv, bank, reg_val)); + + if (value) + data |= GPIO_BIT(offset); + else + data &= ~GPIO_BIT(offset); + + writel(data, bank_reg(priv, bank, reg_val)); + + return 0; +} + +static int aspeed_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct aspeed_gpio_priv *priv = dev_get_priv(dev); + const struct aspeed_gpio_bank *bank = to_bank(offset); + + if (readl(bank_reg(priv, bank, reg_dir)) & GPIO_BIT(offset)) + return GPIOF_OUTPUT; + + return GPIOF_INPUT; +} + +static const struct dm_gpio_ops aspeed_gpio_ops = { + .direction_input = aspeed_gpio_direction_input, + .direction_output = aspeed_gpio_direction_output, + .get_value = aspeed_gpio_get_value, + .set_value = aspeed_gpio_set_value, + .get_function = aspeed_gpio_get_function, +}; + +static int aspeed_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct aspeed_gpio_priv *priv = dev_get_priv(dev); + + uc_priv->bank_name = dev->name; + ofnode_read_u32(dev_ofnode(dev), "ngpios", &uc_priv->gpio_count); + priv->regs = devfdt_get_addr_ptr(dev); + + return 0; +} + +static const struct udevice_id aspeed_gpio_ids[] = { + { .compatible = "aspeed,ast2400-gpio", }, + { .compatible = "aspeed,ast2500-gpio", }, + { .compatible = "aspeed,ast2600-gpio", }, + { } +}; + +U_BOOT_DRIVER(gpio_aspeed) = { + .name = "gpio-aspeed", + .id = UCLASS_GPIO, + .of_match = aspeed_gpio_ids, + .ops = &aspeed_gpio_ops, + .probe = aspeed_gpio_probe, + .priv_auto = sizeof(struct aspeed_gpio_priv), +}; -- cgit v1.3.1 From 7d9ee4667240070407bf2612c36d82bfab8840ba Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 23 Feb 2022 15:36:03 +0100 Subject: firmware: zynqmp: Add support for set sd config and is function supported Add firmware API's to set SD configuration and to check if a purticular function is supported. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f64fa2f73e4775e9ad2f4d91339d6c74b43116a3.1645626962.git.michal.simek@xilinx.com --- drivers/firmware/firmware-zynqmp.c | 51 ++++++++++++++++++++++++++++++++++++++ include/zynqmp_firmware.h | 6 +++++ 2 files changed, 57 insertions(+) (limited to 'drivers') diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 8d8492d99f7..8916c558963 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -140,6 +140,57 @@ unsigned int zynqmp_firmware_version(void) return pm_api_version; }; +int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value) +{ + int ret; + + ret = xilinx_pm_request(PM_IOCTL, node, IOCTL_SET_SD_CONFIG, + config, value, NULL); + if (ret) + printf("%s: node %d: set_sd_config %d failed\n", + __func__, node, config); + + return ret; +} + +int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id) +{ + int ret; + u32 *bit_mask; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + /* Input arguments validation */ + if (id >= 64 || (api_id != PM_IOCTL && api_id != PM_QUERY_DATA)) + return -EINVAL; + + /* Check feature check API version */ + ret = xilinx_pm_request(PM_FEATURE_CHECK, PM_FEATURE_CHECK, 0, 0, 0, + ret_payload); + if (ret) + return ret; + + /* Check if feature check version 2 is supported or not */ + if ((ret_payload[1] & FIRMWARE_VERSION_MASK) == PM_API_VERSION_2) { + /* + * Call feature check for IOCTL/QUERY API to get IOCTL ID or + * QUERY ID feature status. + */ + + ret = xilinx_pm_request(PM_FEATURE_CHECK, api_id, 0, 0, 0, + ret_payload); + if (ret) + return ret; + + bit_mask = &ret_payload[2]; + if ((bit_mask[(id / 32)] & BIT((id % 32))) == 0) + return -EOPNOTSUPP; + } else { + return -ENODATA; + } + + return 0; +} + /** * Send a configuration object to the PMU firmware. * diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 9033cc0e738..60c3df3da41 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -395,6 +395,8 @@ int zynqmp_pmufw_config_close(void); void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size); int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 *ret_payload); +int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value); +int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); /* Type of Config Object */ #define PM_CONFIG_OBJECT_TYPE_BASE 0x1U @@ -426,5 +428,9 @@ enum zynqmp_pm_request_ack { #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U #define ZYNQMP_PM_MAX_QOS 100U +/* Firmware feature check version mask */ +#define FIRMWARE_VERSION_MASK GENMASK(15, 0) +/* PM API versions */ +#define PM_API_VERSION_2 2 #endif /* _ZYNQMP_FIRMWARE_H_ */ -- cgit v1.3.1 From 90ab7fafb65f13cff94c8260f96b73fed3ff8a21 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 23 Feb 2022 15:36:05 +0100 Subject: mmc: zynq_sdhci: Add support for dynamic configuration Add support for dynamic configuration which will takes care of configuring the SD secure space configuration registers using firmware APIs, performing SD reset assert and deassert. High level sequence: - Check for the PM dynamic configuration support, if no error proceed with SD dynamic configurations(next steps) otherwise skip the dynamic configuration. - Put the SD Controller in reset. - Configure SD Fixed configurations. - Configure the SD Slot Type. - Configure the BASE_CLOCK. - Configure the 8-bit support. - Bring the SD Controller out of reset. In the above steps, apart from the Fixed configurations, remaining all configurations are dynamic and they will be read from devicetree. And also remove hardcoded secure register writes, as dynamic sd config support is added. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/030a3ec041ff3efebd574b4d2b477ad85f12cbce.1645626962.git.michal.simek@xilinx.com --- drivers/mmc/zynq_sdhci.c | 101 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 99 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 33d00b06c77..d96f5d543f5 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -12,9 +12,12 @@ #include #include "mmc_private.h" #include +#include #include #include #include +#include +#include #include #include #include @@ -61,6 +64,7 @@ struct arasan_sdhci_priv { u8 deviceid; u8 bank; u8 no_1p8; + struct reset_ctl_bulk resets; }; /* For Versal platforms zynqmp_mmio_write() won't be available */ @@ -243,7 +247,7 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; u8 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0; - debug("%s\n", __func__); + dev_dbg(mmc->dev, "%s\n", __func__); host = priv->host; @@ -703,6 +707,87 @@ static const struct sdhci_ops arasan_ops = { }; #endif +#if defined(CONFIG_ARCH_ZYNQMP) +static int sdhci_zynqmp_set_dynamic_config(struct arasan_sdhci_priv *priv, + struct udevice *dev) +{ + int ret; + u32 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0; + struct clk clk; + unsigned long clock, mhz; + + ret = xilinx_pm_request(PM_REQUEST_NODE, node_id, ZYNQMP_PM_CAPABILITY_ACCESS, + ZYNQMP_PM_MAX_QOS, ZYNQMP_PM_REQUEST_ACK_NO, NULL); + if (ret) { + dev_err(dev, "Request node failed for %d\n", node_id); + return ret; + } + + ret = reset_get_bulk(dev, &priv->resets); + if (ret == -ENOTSUPP || ret == -ENOENT) { + dev_err(dev, "Reset not found\n"); + return 0; + } else if (ret) { + dev_err(dev, "Reset failed\n"); + return ret; + } + + ret = reset_assert_bulk(&priv->resets); + if (ret) { + dev_err(dev, "Reset assert failed\n"); + return ret; + } + + ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_FIXED, 0); + if (ret) { + dev_err(dev, "SD_CONFIG_FIXED failed\n"); + return ret; + } + + ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_EMMC_SEL, + dev_read_bool(dev, "non-removable")); + if (ret) { + dev_err(dev, "SD_CONFIG_EMMC_SEL failed\n"); + return ret; + } + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return ret; + } + + clock = clk_get_rate(&clk); + if (IS_ERR_VALUE(clock)) { + dev_err(dev, "failed to get rate\n"); + return clock; + } + + mhz = DIV64_U64_ROUND_UP(clock, 1000000); + + ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_BASECLK, mhz); + if (ret) { + dev_err(dev, "SD_CONFIG_BASECLK failed\n"); + return ret; + } + + ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_8BIT, + (dev_read_u32_default(dev, "bus-width", 1) == 8)); + if (ret) { + dev_err(dev, "SD_CONFIG_8BIT failed\n"); + return ret; + } + + ret = reset_deassert_bulk(&priv->resets); + if (ret) { + dev_err(dev, "Reset release failed\n"); + return ret; + } + + return 0; +} +#endif + static int arasan_sdhci_probe(struct udevice *dev) { struct arasan_sdhci_plat *plat = dev_get_plat(dev); @@ -715,6 +800,18 @@ static int arasan_sdhci_probe(struct udevice *dev) host = priv->host; +#if defined(CONFIG_ARCH_ZYNQMP) + if (device_is_compatible(dev, "xlnx,zynqmp-8.9a")) { + ret = zynqmp_pm_is_function_supported(PM_IOCTL, + IOCTL_SET_SD_CONFIG); + if (!ret) { + ret = sdhci_zynqmp_set_dynamic_config(priv, dev); + if (ret) + return ret; + } + } +#endif + ret = clk_get_by_index(dev, 0, &clk); if (ret < 0) { dev_err(dev, "failed to get clock\n"); @@ -727,7 +824,7 @@ static int arasan_sdhci_probe(struct udevice *dev) return clock; } - debug("%s: CLK %ld\n", __func__, clock); + dev_dbg(dev, "%s: CLK %ld\n", __func__, clock); ret = clk_enable(&clk); if (ret) { -- cgit v1.3.1 From 98cacab76542dba7fa7d42e32fc848d89d88d55a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 23 Feb 2022 15:52:02 +0100 Subject: video: Add skeleton driver for ZynqMP Display port driver The reason for this driver is to use call power management driver to enable it in PMUFW. There is missing functionality now but should be added in near future. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/598cb9515bbabc803f72e287464e3d107cd106a3.1645627920.git.michal.simek@xilinx.com --- drivers/video/Kconfig | 8 ++++++ drivers/video/Makefile | 1 + drivers/video/zynqmp_dpsub.c | 66 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 75 insertions(+) create mode 100644 drivers/video/zynqmp_dpsub.c (limited to 'drivers') diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index ff8e11f6489..646fec70262 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -680,6 +680,14 @@ config VIDEO_SEPS525 Enable support for the Syncoam PM-OLED display driver (RGB 160x128). Currently driver is supporting only SPI interface. +config VIDEO_ZYNQMP_DPSUB + bool "Enable video support for ZynqMP Display Port" + depends on DM_VIDEO && ZYNQMP_POWER_DOMAIN + help + Enable support for Xilinx ZynqMP Display Port. Currently this file + is used as placeholder for driver. The main reason is to record + compatible string and calling power domain driver. + source "drivers/video/nexell/Kconfig" config VIDEO diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 4038395b128..2530791eb43 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -74,6 +74,7 @@ obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o obj-$(CONFIG_VIDEO_VESA) += vesa.o obj-$(CONFIG_VIDEO_SEPS525) += seps525.o +obj-$(CONFIG_VIDEO_ZYNQMP_DPSUB) += zynqmp_dpsub.o obj-y += bridge/ obj-y += sunxi/ diff --git a/drivers/video/zynqmp_dpsub.c b/drivers/video/zynqmp_dpsub.c new file mode 100644 index 00000000000..4ead663cd59 --- /dev/null +++ b/drivers/video/zynqmp_dpsub.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Xilinx Inc. + */ + +#include +#include +#include +#include +#include +#include + +#define WIDTH 640 +#define HEIGHT 480 + +/** + * struct zynqmp_dpsub_priv - Private structure + * @dev: Device uclass for video_ops + */ +struct zynqmp_dpsub_priv { + struct udevice *dev; +}; + +static int zynqmp_dpsub_probe(struct udevice *dev) +{ + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct zynqmp_dpsub_priv *priv = dev_get_priv(dev); + + uc_priv->bpix = VIDEO_BPP16; + uc_priv->xsize = WIDTH; + uc_priv->ysize = HEIGHT; + uc_priv->rot = 0; + + priv->dev = dev; + + /* Only placeholder for power domain driver */ + return 0; +} + +static int zynqmp_dpsub_bind(struct udevice *dev) +{ + struct video_uc_plat *plat = dev_get_uclass_plat(dev); + + plat->size = WIDTH * HEIGHT * 16; + + return 0; +} + +static const struct video_ops zynqmp_dpsub_ops = { +}; + +static const struct udevice_id zynqmp_dpsub_ids[] = { + { .compatible = "xlnx,zynqmp-dpsub-1.7" }, + { } +}; + +U_BOOT_DRIVER(zynqmp_dpsub_video) = { + .name = "zynqmp_dpsub_video", + .id = UCLASS_VIDEO, + .of_match = zynqmp_dpsub_ids, + .ops = &zynqmp_dpsub_ops, + .plat_auto = sizeof(struct video_uc_plat), + .bind = zynqmp_dpsub_bind, + .probe = zynqmp_dpsub_probe, + .priv_auto = sizeof(struct zynqmp_dpsub_priv), +}; -- cgit v1.3.1 From d926695cc5680edfff9cfef36a14933ee3585fbf Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 23 Feb 2022 15:52:03 +0100 Subject: dma: xilinx: Add Display Port DMA driver Display Port (DP) has own dma driver that's why add this skeleton driver only for handling power domain setting and send configuration object to PMUFW to enable it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/fe8bc313bcd430b04e9fa6fb770d5799ef28b350.1645627920.git.michal.simek@xilinx.com --- drivers/dma/Kconfig | 7 +++++++ drivers/dma/Makefile | 1 + drivers/dma/xilinx_dpdma.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 51 insertions(+) create mode 100644 drivers/dma/xilinx_dpdma.c (limited to 'drivers') diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 9cacea88d0c..0af54604211 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -68,6 +68,13 @@ config APBH_DMA help Enable APBH DMA driver. +config XILINX_DPDMA + bool "Enable ZynqMP Display Port DMA driver" + depends on DMA && ZYNQMP_POWER_DOMAIN + help + Enable support for Xilinx ZynqMP Display DMA driver. Currently + this file is used as placeholder for driver. The main reason is + to record compatible string and calling power domain driver. if APBH_DMA config APBH_DMA_BURST diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index afab324461b..a75572fe5de 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -13,5 +13,6 @@ obj-$(CONFIG_SANDBOX_DMA) += sandbox-dma-test.o obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o obj-$(CONFIG_TI_EDMA3) += ti-edma3.o obj-$(CONFIG_DMA_LPC32XX) += lpc32xx_dma.o +obj-$(CONFIG_XILINX_DPDMA) += xilinx_dpdma.o obj-y += ti/ diff --git a/drivers/dma/xilinx_dpdma.c b/drivers/dma/xilinx_dpdma.c new file mode 100644 index 00000000000..d4ee21dfc07 --- /dev/null +++ b/drivers/dma/xilinx_dpdma.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Xilinx Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +/** + * struct zynqmp_dpdma_priv - Private structure + * @dev: Device uclass for video_ops + */ +struct zynqmp_dpdma_priv { + struct udevice *dev; +}; + +static int zynqmp_dpdma_probe(struct udevice *dev) +{ + /* Only placeholder for power domain driver */ + return 0; +} + +static const struct dma_ops zynqmp_dpdma_ops = { +}; + +static const struct udevice_id zynqmp_dpdma_ids[] = { + { .compatible = "xlnx,zynqmp-dpdma" }, + { } +}; + +U_BOOT_DRIVER(zynqmp_dpdma) = { + .name = "zynqmp_dpdma", + .id = UCLASS_DMA, + .of_match = zynqmp_dpdma_ids, + .ops = &zynqmp_dpdma_ops, + .probe = zynqmp_dpdma_probe, + .priv_auto = sizeof(struct zynqmp_dpdma_priv), +}; -- cgit v1.3.1 From 1bc2a79a4cde5f703b33342f2fcea8af208614ed Mon Sep 17 00:00:00 2001 From: Sai Pavan Boddu Date: Tue, 1 Mar 2022 09:16:50 +0100 Subject: i2c: i2c-cdns: Start read transaction after write to transfer_size reg Avoid a race condition where read transaction is started keeping expected bytes as 0. Which sometimes would result in sending STOP signal as no data is expected. Observed on QEMU platform. Signed-off-by: Sai Pavan Boddu Reviewed-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/487c8026791bfd60719403a2df2c54bb0ae99232.1646122610.git.michal.simek@xilinx.com --- drivers/i2c/i2c-cdns.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c index a650dd69b89..5736afb4519 100644 --- a/drivers/i2c/i2c-cdns.c +++ b/drivers/i2c/i2c-cdns.c @@ -375,7 +375,6 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, curr_recv_count = recv_count; } } else if (recv_count && !hold_quirk && !curr_recv_count) { - writel(addr, ®s->address); if (recv_count > CDNS_I2C_TRANSFER_SIZE) { writel(CDNS_I2C_TRANSFER_SIZE, ®s->transfer_size); @@ -384,6 +383,7 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, writel(recv_count, ®s->transfer_size); curr_recv_count = recv_count; } + writel(addr, ®s->address); } } -- cgit v1.3.1 From 94b3f3fc7d5eece585a688061fa7a32a1a1c8495 Mon Sep 17 00:00:00 2001 From: Sai Pavan Boddu Date: Tue, 1 Mar 2022 09:16:51 +0100 Subject: i2c: i2c-cdns: Fix write transaction state Start write transfer after loading data to FIFO. Signed-off-by: Sai Pavan Boddu Reviewed-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f0b3e443daa7758e00dfdcc245cf6b2120b0e907.1646122610.git.michal.simek@xilinx.com --- drivers/i2c/i2c-cdns.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c index 5736afb4519..07d53be11f1 100644 --- a/drivers/i2c/i2c-cdns.c +++ b/drivers/i2c/i2c-cdns.c @@ -251,6 +251,7 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, u8 *cur_data = data; struct cdns_i2c_regs *regs = i2c_bus->regs; u32 ret; + bool start = 1; /* Set the controller in Master transmit mode and clear FIFO */ setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO); @@ -269,6 +270,11 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, while (len-- && !is_arbitration_lost(regs)) { writel(*(cur_data++), ®s->data); + /* Trigger write only after loading data */ + if (start) { + writel(addr, ®s->address); + start = 0; + } if (len && readl(®s->transfer_size) == CDNS_I2C_FIFO_DEPTH) { ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP | CDNS_I2C_INTERRUPT_ARBLOST); -- cgit v1.3.1 From f76f86029d75df2546e734e3ae1a50fa62d72526 Mon Sep 17 00:00:00 2001 From: Sai Pavan Boddu Date: Tue, 1 Mar 2022 09:16:52 +0100 Subject: i2c: i2c-cdns: Prevent early termination of write During sequential loading of data, hold the bus to prevent controller from sending stop signal in case no data is available in fifo. Signed-off-by: Sai Pavan Boddu Reviewed-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/2407b39d305999cb42438c5423aebc3b514acabb.1646122610.git.michal.simek@xilinx.com --- drivers/i2c/i2c-cdns.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c index 07d53be11f1..0da9f6f35a9 100644 --- a/drivers/i2c/i2c-cdns.c +++ b/drivers/i2c/i2c-cdns.c @@ -257,16 +257,18 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO); clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW); - /* Check message size against FIFO depth, and set hold bus bit - * if it is greater than FIFO depth + /* + * For sequential data load hold the bus. */ - if (len > CDNS_I2C_FIFO_DEPTH) + if (len > 1) setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); /* Clear the interrupts in status register */ writel(CDNS_I2C_INTERRUPTS_MASK, ®s->interrupt_status); - writel(addr, ®s->address); + /* In case of Probe (i.e no data), start the transfer */ + if (!len) + writel(addr, ®s->address); while (len-- && !is_arbitration_lost(regs)) { writel(*(cur_data++), ®s->data); -- cgit v1.3.1 From db681d4929cac3f5d0a8ce638e7e5306fe6038d2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 23 Feb 2022 15:45:40 +0100 Subject: net: phy: Add new read ethernet phy id function Add new function to get ethernet phy id from compatible property of the mdio phy node. Signed-off-by: Michal Simek Signed-off-by: T Karthik Reddy Link: https://lore.kernel.org/r/16019efb3820a50330935fdaae191cec1f101b5c.1645627539.git.michal.simek@xilinx.com --- drivers/core/ofnode.c | 36 ++++++++++++++++++++++++++++++++++++ include/dm/ofnode.h | 13 +++++++++++++ 2 files changed, 49 insertions(+) (limited to 'drivers') diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 709bea272a6..8042847f3c1 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -898,6 +898,42 @@ int ofnode_read_pci_vendev(ofnode node, u16 *vendor, u16 *device) return -ENOENT; } +int ofnode_read_eth_phy_id(ofnode node, u16 *vendor, u16 *device) +{ + const char *list, *end; + int len; + + list = ofnode_get_property(node, "compatible", &len); + + if (!list) + return -ENOENT; + + end = list + len; + while (list < end) { + len = strlen(list); + + if (len >= strlen("ethernet-phy-idVVVV,DDDD")) { + char *s = strstr(list, "ethernet-phy-id"); + + /* + * check if the string is something like + * ethernet-phy-idVVVV,DDDD + */ + if (s && s[19] == '.') { + s += strlen("ethernet-phy-id"); + *vendor = simple_strtol(s, NULL, 16); + s += 5; + *device = simple_strtol(s, NULL, 16); + + return 0; + } + } + list += (len + 1); + } + + return -ENOENT; +} + int ofnode_read_addr_cells(ofnode node) { if (ofnode_is_np(node)) { diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 0cb324c8b0c..744dffe0a2d 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -894,6 +894,19 @@ int ofnode_read_pci_addr(ofnode node, enum fdt_pci_space type, */ int ofnode_read_pci_vendev(ofnode node, u16 *vendor, u16 *device); +/** + * ofnode_read_eth_phy_id() - look up eth phy vendor and device id + * + * Look at the compatible property of a device node that represents a eth phy + * device and extract phy vendor id and device id from it. + * + * @param node node to examine + * @param vendor vendor id of the eth phy device + * @param device device id of the eth phy device + * @return 0 if ok, negative on error + */ +int ofnode_read_eth_phy_id(ofnode node, u16 *vendor, u16 *device); + /** * ofnode_read_addr_cells() - Get the number of address cells for a node * -- cgit v1.3.1 From 3249116d8381a1a8f0d17c95acecd7c78b40e569 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 23 Feb 2022 15:45:41 +0100 Subject: net: phy: Remove static return type for phy_device_create() Remove static return type for phy_device_create() to avoid file scope for this function. Also add required prototype in phy.h. Signed-off-by: Michal Simek Signed-off-by: T Karthik Reddy Link: https://lore.kernel.org/r/1517f4053403fbd53e899d500e7485d068a4f0b6.1645627539.git.michal.simek@xilinx.com --- drivers/net/phy/phy.c | 6 +++--- include/phy.h | 13 +++++++++++++ 2 files changed, 16 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index c9fc20855ba..f63705e1b9a 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -659,9 +659,9 @@ static struct phy_driver *get_phy_driver(struct phy_device *phydev, return generic_for_interface(interface); } -static struct phy_device *phy_device_create(struct mii_dev *bus, int addr, - u32 phy_id, bool is_c45, - phy_interface_t interface) +struct phy_device *phy_device_create(struct mii_dev *bus, int addr, + u32 phy_id, bool is_c45, + phy_interface_t interface) { struct phy_device *dev; diff --git a/include/phy.h b/include/phy.h index c66fd43ea88..832d7a16957 100644 --- a/include/phy.h +++ b/include/phy.h @@ -454,6 +454,19 @@ void phy_connect_dev(struct phy_device *phydev, struct udevice *dev); struct phy_device *phy_connect(struct mii_dev *bus, int addr, struct udevice *dev, phy_interface_t interface); +/** + * phy_device_create() - Create a PHY device + * + * @bus: MII/MDIO bus that hosts the PHY + * @addr: PHY address on MDIO bus + * @phy_id: where to store the ID retrieved + * @is_c45: Device Identifiers if is_c45 + * @interface: interface between the MAC and PHY + * @return: pointer to phy_device if a PHY is found, or NULL otherwise + */ +struct phy_device *phy_device_create(struct mii_dev *bus, int addr, + u32 phy_id, bool is_c45, + phy_interface_t interface); static inline ofnode phy_get_ofnode(struct phy_device *phydev) { -- cgit v1.3.1 From a744a284e35420077b0c838598eb24c98710412a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 23 Feb 2022 15:45:42 +0100 Subject: net: phy: Add support for ethernet-phy-id with gpio reset Ethernet phy like dp83867 is using strapping resistors to setup PHY address. On Xilinx boards strapping is setup on wires which are connected to SOC where internal pull ups/downs influnce phy address. That's why there is a need to setup pins properly (via pinctrl driver for example) and then perform phy reset. I can be workarounded by reset gpio done for mdio bus but this is not working properly when multiply phys sitting on the same bus. That's why it needs to be done via ethernet-phy-id driver where dt binding has gpio reset per phy. DT binding is available here: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/net/ethernet-phy.yaml The driver is are reading the vendor and device id from valid phy node using ofnode_read_eth_phy_id() and creating a phy device. Kconfig PHY_ETHERNET_ID symbol is used because not every platform has gpio support. Signed-off-by: Michal Simek Signed-off-by: T Karthik Reddy Link: https://lore.kernel.org/r/70ab7d71c812b2c972d48c129e416c921af0d7f5.1645627539.git.michal.simek@xilinx.com --- MAINTAINERS | 1 + drivers/net/phy/Kconfig | 8 +++++ drivers/net/phy/Makefile | 1 + drivers/net/phy/ethernet_id.c | 69 +++++++++++++++++++++++++++++++++++++++++++ drivers/net/phy/phy.c | 5 ++++ include/phy.h | 13 ++++++++ 6 files changed, 97 insertions(+) create mode 100644 drivers/net/phy/ethernet_id.c (limited to 'drivers') diff --git a/MAINTAINERS b/MAINTAINERS index c58947fb2ff..4e740fb5d26 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -617,6 +617,7 @@ F: drivers/i2c/muxes/pca954x.c F: drivers/i2c/zynq_i2c.c F: drivers/mmc/zynq_sdhci.c F: drivers/mtd/nand/raw/zynq_nand.c +F: drivers/net/phy/ethernet_id.c F: drivers/net/phy/xilinx_phy.c F: drivers/net/zynq_gem.c F: drivers/serial/serial_zynq.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 4f8d33ce8fd..74339a25ca5 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -307,6 +307,14 @@ config PHY_XILINX_GMII2RGMII as bridge between MAC connected over GMII and external phy that is connected over RGMII interface. +config PHY_ETHERNET_ID + bool "Read ethernet PHY id" + depends on DM_GPIO + default y if ZYNQ_GEM + help + Enable this config to read ethernet phy id from the phy node of DT + and create a phy device using id. + config PHY_FIXED bool "Fixed-Link PHY" depends on DM_ETH diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 77f7f606215..b28440bc4e5 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_PHY_TI_DP83867) += dp83867.o obj-$(CONFIG_PHY_TI_DP83869) += dp83869.o obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o obj-$(CONFIG_PHY_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o +obj-$(CONFIG_PHY_ETHERNET_ID) += ethernet_id.o obj-$(CONFIG_PHY_VITESSE) += vitesse.o obj-$(CONFIG_PHY_MSCC) += mscc.o obj-$(CONFIG_PHY_FIXED) += fixed.o diff --git a/drivers/net/phy/ethernet_id.c b/drivers/net/phy/ethernet_id.c new file mode 100644 index 00000000000..5617ac3ad62 --- /dev/null +++ b/drivers/net/phy/ethernet_id.c @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ethernet phy reset driver + * + * Copyright (C) 2022 Xilinx, Inc. + */ + +#include +#include +#include +#include +#include + +struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev, + phy_interface_t interface) +{ + struct phy_device *phydev; + struct ofnode_phandle_args phandle_args; + struct gpio_desc gpio; + ofnode node; + u32 id, assert, deassert; + u16 vendor, device; + int ret; + + if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, + &phandle_args)) + return NULL; + + if (!ofnode_valid(phandle_args.node)) + return NULL; + + node = phandle_args.node; + + ret = ofnode_read_eth_phy_id(node, &vendor, &device); + if (ret) { + dev_err(dev, "Failed to read eth PHY id, err: %d\n", ret); + return NULL; + } + + ret = gpio_request_by_name_nodev(node, "reset-gpios", 0, &gpio, + GPIOD_ACTIVE_LOW); + if (!ret) { + assert = ofnode_read_u32_default(node, "reset-assert-us", 0); + deassert = ofnode_read_u32_default(node, + "reset-deassert-us", 0); + ret = dm_gpio_set_value(&gpio, 1); + if (ret) { + dev_err(dev, "Failed assert gpio, err: %d\n", ret); + return NULL; + } + + udelay(assert); + + ret = dm_gpio_set_value(&gpio, 0); + if (ret) { + dev_err(dev, "Failed deassert gpio, err: %d\n", ret); + return NULL; + } + + udelay(deassert); + } + + id = vendor << 16 | device; + phydev = phy_device_create(bus, 0, id, false, interface); + if (phydev) + phydev->node = node; + + return phydev; +} diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index f63705e1b9a..fffa10f68b3 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -1047,6 +1047,11 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr, phydev = phy_device_create(bus, 0, PHY_NCSI_ID, false, interface); #endif +#ifdef CONFIG_PHY_ETHERNET_ID + if (!phydev) + phydev = phy_connect_phy_id(bus, dev, interface); +#endif + #ifdef CONFIG_PHY_XILINX_GMII2RGMII if (!phydev) phydev = phy_connect_gmii2rgmii(bus, dev, interface); diff --git a/include/phy.h b/include/phy.h index 832d7a16957..9ea4bd42db4 100644 --- a/include/phy.h +++ b/include/phy.h @@ -468,6 +468,19 @@ struct phy_device *phy_device_create(struct mii_dev *bus, int addr, u32 phy_id, bool is_c45, phy_interface_t interface); +/** + * phy_connect_phy_id() - Connect to phy device by reading PHY id + * from phy node. + * + * @bus: MII/MDIO bus that hosts the PHY + * @dev: Ethernet device to associate to the PHY + * @interface: Interface between the MAC and PHY + * @return: pointer to phy_device if a PHY is found, + * or NULL otherwise + */ +struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev, + phy_interface_t interface); + static inline ofnode phy_get_ofnode(struct phy_device *phydev) { if (ofnode_valid(phydev->node)) -- cgit v1.3.1 From 5b896ed5856f768cdd55cdeb44c5f8f6b6a7a18a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 4 Mar 2022 08:43:03 -0700 Subject: event: Add events for device probe/remove Generate events when devices are probed or removed, allowing hooks to be added for these situations. This is controlled by the DM_EVENT config option. Signed-off-by: Simon Glass --- common/event.c | 6 ++++++ drivers/core/Kconfig | 10 ++++++++++ drivers/core/device-remove.c | 8 ++++++++ drivers/core/device.c | 9 +++++++++ include/dm/device-internal.h | 10 ++++++++++ include/event.h | 15 +++++++++++++++ test/common/event.c | 38 ++++++++++++++++++++++++++++++++++++++ 7 files changed, 96 insertions(+) (limited to 'drivers') diff --git a/common/event.c b/common/event.c index 366be245696..737d3ac9eaa 100644 --- a/common/event.c +++ b/common/event.c @@ -24,6 +24,12 @@ DECLARE_GLOBAL_DATA_PTR; const char *const type_name[] = { "none", "test", + + /* Events related to driver model */ + "dm_pre_probe", + "dm_post_probe", + "dm_pre_remove", + "dm_post_remove", }; _Static_assert(ARRAY_SIZE(type_name) == EVT_COUNT, "event type_name size"); diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 8f7703c8b58..5c3400417f9 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -77,6 +77,16 @@ config DM_DEVICE_REMOVE it causes unplugged devices to linger around in the dm-tree, and it causes USB host controllers to not be stopped when booting the OS. +config DM_EVENT + bool "Support events with driver model" + depends on DM + imply EVENT + default y if SANDBOX + help + This enables support for generating events related to driver model + operations, such as prbing or removing a device. Subsystems can + register a 'spy' function that is called when the event occurs. + config SPL_DM_DEVICE_REMOVE bool "Support device removal in SPL" depends on SPL_DM diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c index e6ec6ff4212..73d2e9e4208 100644 --- a/drivers/core/device-remove.c +++ b/drivers/core/device-remove.c @@ -207,6 +207,10 @@ int device_remove(struct udevice *dev, uint flags) if (!(dev_get_flags(dev) & DM_FLAG_ACTIVATED)) return 0; + ret = device_notify(dev, EVT_DM_PRE_REMOVE); + if (ret) + return ret; + /* * If the child returns EKEYREJECTED, continue. It just means that it * didn't match the flags. @@ -256,6 +260,10 @@ int device_remove(struct udevice *dev, uint flags) dev_bic_flags(dev, DM_FLAG_ACTIVATED); + ret = device_notify(dev, EVT_DM_POST_REMOVE); + if (ret) + goto err_remove; + return 0; err_remove: diff --git a/drivers/core/device.c b/drivers/core/device.c index 901c1e2f7db..1b356f12dd8 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -493,6 +494,10 @@ int device_probe(struct udevice *dev) if (dev_get_flags(dev) & DM_FLAG_ACTIVATED) return 0; + ret = device_notify(dev, EVT_DM_PRE_PROBE); + if (ret) + return ret; + drv = dev->driver; assert(drv); @@ -597,6 +602,10 @@ int device_probe(struct udevice *dev) dev->name, ret, errno_str(ret)); } + ret = device_notify(dev, EVT_DM_POST_PROBE); + if (ret) + return ret; + return 0; fail_uclass: if (device_remove(dev, DM_REMOVE_NORMAL)) { diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h index 02002acb787..c420726287e 100644 --- a/include/dm/device-internal.h +++ b/include/dm/device-internal.h @@ -10,6 +10,7 @@ #ifndef _DM_DEVICE_INTERNAL_H #define _DM_DEVICE_INTERNAL_H +#include #include #include @@ -426,4 +427,13 @@ static inline void devres_release_all(struct udevice *dev) } #endif /* ! CONFIG_DEVRES */ + +static inline int device_notify(const struct udevice *dev, enum event_t type) +{ +#if CONFIG_IS_ENABLED(DM_EVENT) + return event_notify(type, &dev, sizeof(dev)); +#else + return 0; +#endif +} #endif diff --git a/include/event.h b/include/event.h index effd58c7047..f4c12d768b4 100644 --- a/include/event.h +++ b/include/event.h @@ -19,6 +19,12 @@ enum event_t { EVT_NONE, EVT_TEST, + /* Events related to driver model */ + EVT_DM_PRE_PROBE, + EVT_DM_POST_PROBE, + EVT_DM_PRE_REMOVE, + EVT_DM_POST_REMOVE, + EVT_COUNT }; @@ -31,6 +37,15 @@ union event_data { struct event_data_test { int signal; } test; + + /** + * struct event_dm - driver model event + * + * @dev: Device this event relates to + */ + struct event_dm { + struct udevice *dev; + } dm; }; /** diff --git a/test/common/event.c b/test/common/event.c index dfaa66ea492..6037ae2ce3b 100644 --- a/test/common/event.c +++ b/test/common/event.c @@ -45,3 +45,41 @@ static int test_event_base(struct unit_test_state *uts) return 0; } COMMON_TEST(test_event_base, 0); + +static int h_probe(void *ctx, struct event *event) +{ + struct test_state *test_state = ctx; + + test_state->dev = event->data.dm.dev; + switch (event->type) { + case EVT_DM_PRE_PROBE: + test_state->val |= 1; + break; + case EVT_DM_POST_PROBE: + test_state->val |= 2; + break; + default: + break; + } + + return 0; +} + +static int test_event_probe(struct unit_test_state *uts) +{ + struct test_state state; + struct udevice *dev; + + state.val = 0; + ut_assertok(event_register("pre", EVT_DM_PRE_PROBE, h_probe, &state)); + ut_assertok(event_register("post", EVT_DM_POST_PROBE, h_probe, &state)); + + /* Probe a device */ + ut_assertok(uclass_first_device_err(UCLASS_TEST_FDT, &dev)); + + /* Check that the handler is called */ + ut_asserteq(3, state.val); + + return 0; +} +COMMON_TEST(test_event_probe, UT_TESTF_DM | UT_TESTF_SCAN_FDT); -- cgit v1.3.1 From 7fe32b3442f0d0e77a0768dcc1ee65fb352a080a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 4 Mar 2022 08:43:05 -0700 Subject: event: Convert arch_cpu_init_dm() to use events Instead of a special function, send an event after driver model is inited and adjust the boards which use this function. Signed-off-by: Simon Glass --- arch/Kconfig | 3 +++ arch/arm/Kconfig | 4 ++++ arch/arm/mach-imx/imx8/cpu.c | 4 +++- arch/arm/mach-imx/imx8m/soc.c | 4 +++- arch/arm/mach-imx/imx8ulp/soc.c | 4 +++- arch/arm/mach-omap2/am33xx/board.c | 4 +++- arch/arm/mach-omap2/hwinit-common.c | 5 ++++- arch/mips/Kconfig | 1 + arch/mips/mach-pic32/cpu.c | 4 +++- arch/nios2/cpu/cpu.c | 4 +++- arch/riscv/cpu/cpu.c | 5 ++++- arch/riscv/include/asm/system.h | 5 +++++ arch/riscv/lib/spl.c | 3 ++- arch/x86/cpu/baytrail/cpu.c | 4 +++- arch/x86/cpu/broadwell/cpu.c | 4 +++- arch/x86/cpu/ivybridge/cpu.c | 4 +++- arch/x86/cpu/quark/quark.c | 4 +++- arch/x86/include/asm/fsp2/fsp_api.h | 8 ++++++++ arch/x86/lib/fsp2/fsp_init.c | 4 +++- arch/x86/lib/spl.c | 5 +++-- arch/x86/lib/tpl.c | 10 ---------- common/board_f.c | 6 ------ common/event.c | 1 + drivers/core/root.c | 5 +++++ include/event.h | 1 + include/init.h | 11 ----------- 26 files changed, 74 insertions(+), 43 deletions(-) (limited to 'drivers') diff --git a/arch/Kconfig b/arch/Kconfig index e6191446a35..1b35fda64cc 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -94,6 +94,7 @@ config NIOS2 bool "Nios II architecture" select CPU select DM + imply DM_EVENT select OF_CONTROL select SUPPORT_OF_CONTROL imply CMD_DM @@ -113,6 +114,7 @@ config RISCV select DM imply DM_SERIAL imply DM_ETH + imply DM_EVENT imply DM_MMC imply DM_SPI imply DM_SPI_FLASH @@ -238,6 +240,7 @@ config X86 imply CMD_SF_TEST imply CMD_ZBOOT imply DM_ETH + imply DM_EVENT imply DM_GPIO imply DM_KEYBOARD imply DM_MMC diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8c7f3176970..a6f2e7a1008 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -774,6 +774,7 @@ config ARCH_OMAP2PLUS select SUPPORT_SPL imply TI_SYSC if DM && OF_CONTROL imply FIT + imply DM_EVENT config ARCH_MESON bool "Amlogic Meson" @@ -818,6 +819,7 @@ config ARCH_IMX8 select MACH_IMX select OF_CONTROL select ENABLE_ARM_SOC_BOOT0_HOOK + imply DM_EVENT config ARCH_IMX8M bool "NXP i.MX8M platform" @@ -831,6 +833,7 @@ config ARCH_IMX8M select DM select SUPPORT_SPL imply CMD_DM + imply DM_EVENT config ARCH_IMX8ULP bool "NXP i.MX8ULP platform" @@ -841,6 +844,7 @@ config ARCH_IMX8ULP select SUPPORT_SPL select GPIO_EXTRA_HEADER imply CMD_DM + imply DM_EVENT config ARCH_IMXRT bool "NXP i.MXRT platform" diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index ee5cc479039..359f8c796eb 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -66,7 +67,7 @@ int arch_cpu_init(void) return 0; } -int arch_cpu_init_dm(void) +static int imx8_init_mu(void *ctx, struct event *event) { struct udevice *devp; int node, ret; @@ -88,6 +89,7 @@ int arch_cpu_init_dm(void) return 0; } +EVENT_SPY(EVT_DM_POST_INIT, imx8_init_mu); int print_bootinfo(void) { diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 1a5a391443d..838f0a37496 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -494,7 +495,7 @@ static void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog3->wmcr); } -int arch_cpu_init_dm(void) +static int imx8m_check_clock(void *ctx, struct event *event) { struct udevice *dev; int ret; @@ -511,6 +512,7 @@ int arch_cpu_init_dm(void) return 0; } +EVENT_SPY(EVT_DM_POST_INIT, imx8m_check_clock); int arch_cpu_init(void) { diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 934b0ef038c..e6d417ed48b 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -569,7 +570,7 @@ int arch_cpu_init(void) return 0; } -int arch_cpu_init_dm(void) +static int imx8ulp_check_mu(void *ctx, struct event *event) { struct udevice *devp; int node, ret; @@ -584,6 +585,7 @@ int arch_cpu_init_dm(void) return 0; } +EVENT_SPY(EVT_DM_POST_INIT, imx8ulp_check_mu); #if defined(CONFIG_SPL_BUILD) __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index c44667668e9..bcc907ce362 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -596,7 +597,7 @@ void board_init_f(ulong dummy) #endif -int arch_cpu_init_dm(void) +static int am33xx_dm_post_init(void *ctx, struct event *event) { hw_data_init(); #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) @@ -604,3 +605,4 @@ int arch_cpu_init_dm(void) #endif return 0; } +EVENT_SPY(EVT_DM_POST_INIT, am33xx_dm_post_init); diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c index 3da50f974dc..c4a8eabc3eb 100644 --- a/arch/arm/mach-omap2/hwinit-common.c +++ b/arch/arm/mach-omap2/hwinit-common.c @@ -12,6 +12,7 @@ */ #include #include +#include #include #include #include @@ -239,11 +240,13 @@ void board_init_f(ulong dummy) } #endif -int arch_cpu_init_dm(void) +static int omap2_system_init(void *ctx, struct event *event) { early_system_init(); + return 0; } +EVENT_SPY(EVT_DM_POST_INIT, omap2_system_init); /* * Routine: wait_for_command_complete diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 28234aa0bb6..06cae68ee57 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -130,6 +130,7 @@ config MACH_PIC32 config TARGET_BOSTON bool "Support Boston" select DM + imply DM_EVENT select DM_SERIAL select MIPS_CM select SYS_CACHE_SHIFT_6 diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c index eac2fe5f8c9..de449e3c6a2 100644 --- a/arch/mips/mach-pic32/cpu.c +++ b/arch/mips/mach-pic32/cpu.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -95,12 +96,13 @@ static void prefetch_init(void) } /* arch specific CPU init after DM */ -int arch_cpu_init_dm(void) +static int pic32_flash_prefetch(void *ctx, struct event *event) { /* flash prefetch */ prefetch_init(); return 0; } +EVENT_SPY(EVT_DM_POST_INIT, pic32_flash_prefetch); /* Un-gate DDR2 modules (gated by default) */ static void ddr2_pmd_ungate(void) diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index b55c8fbc584..4dd9c10faa5 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -63,7 +64,7 @@ static void copy_exception_trampoline(void) } #endif -int arch_cpu_init_dm(void) +static int nios_cpu_setup(void *ctx, struct event *event) { struct udevice *dev; int ret; @@ -79,6 +80,7 @@ int arch_cpu_init_dm(void) return 0; } +EVENT_SPY(EVT_DM_POST_INIT, nios_cpu_setup); static int altera_nios2_get_desc(const struct udevice *dev, char *buf, int size) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 8d90c5e6b8a..3ffcbbd23fa 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -7,9 +7,11 @@ #include #include #include +#include #include #include #include +#include #include #include @@ -81,7 +83,7 @@ static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1) } #endif -int arch_cpu_init_dm(void) +int riscv_cpu_setup(void *ctx, struct event *event) { int ret; @@ -133,6 +135,7 @@ int arch_cpu_init_dm(void) return 0; } +EVENT_SPY(EVT_DM_POST_INIT, riscv_cpu_setup); int arch_early_init_r(void) { diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h index a3404758235..9d8e43e3942 100644 --- a/arch/riscv/include/asm/system.h +++ b/arch/riscv/include/asm/system.h @@ -7,6 +7,8 @@ #ifndef __ASM_RISCV_SYSTEM_H #define __ASM_RISCV_SYSTEM_H +struct event; + /* * Interrupt configuring macros. * @@ -14,4 +16,7 @@ * */ +/* Hook to set up the CPU (called from SPL too) */ +int riscv_cpu_setup(void *ctx, struct event *event); + #endif /* __ASM_RISCV_SYSTEM_H */ diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c index 8baee07beac..f4d3b67e5dd 100644 --- a/arch/riscv/lib/spl.c +++ b/arch/riscv/lib/spl.c @@ -11,6 +11,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -27,7 +28,7 @@ __weak void board_init_f(ulong dummy) if (ret) panic("spl_early_init() failed: %d\n", ret); - arch_cpu_init_dm(); + riscv_cpu_setup(NULL, NULL); preloader_console_init(); diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c index 309a50a1161..68bf40ba8e8 100644 --- a/arch/x86/cpu/baytrail/cpu.c +++ b/arch/x86/cpu/baytrail/cpu.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -44,7 +45,7 @@ static void hsuart_clock_set(void *base) * Configure the internal clock of both SIO HS-UARTs, if they are enabled * via FSP */ -int arch_cpu_init_dm(void) +static int baytrail_uart_init(void *ctx, struct event *event) { struct udevice *dev; void *base; @@ -63,6 +64,7 @@ int arch_cpu_init_dm(void) return 0; } +EVENT_SPY(EVT_DM_POST_INIT, baytrail_uart_init); static void set_max_freq(void) { diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index 3832a97f2c7..2adcf4b242c 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -24,7 +25,7 @@ #include #include -int arch_cpu_init_dm(void) +static int broadwell_init_cpu(void *ctx, struct event *event) { struct udevice *dev; int ret; @@ -41,6 +42,7 @@ int arch_cpu_init_dm(void) return 0; } +EVENT_SPY(EVT_DM_POST_INIT, broadwell_init_cpu); void set_max_freq(void) { diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index a02f4f9600e..cffc5d5b1d8 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -53,7 +54,7 @@ int arch_cpu_init(void) return x86_cpu_init_f(); } -int arch_cpu_init_dm(void) +static int ivybridge_cpu_init(void *ctx, struct event *ev) { struct pci_controller *hose; struct udevice *bus, *dev; @@ -85,6 +86,7 @@ int arch_cpu_init_dm(void) return 0; } +EVENT_SPY(EVT_DM_POST_INIT, ivybridge_cpu_init); #define PCH_EHCI0_TEMP_BAR0 0xe8000000 #define PCH_EHCI1_TEMP_BAR0 0xe8000400 diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 30b4711b9a5..e016fae04f9 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -247,7 +248,7 @@ int arch_cpu_init(void) return 0; } -int arch_cpu_init_dm(void) +static int quark_init_pcie(void *ctx, struct event *event) { /* * Initialize PCIe controller @@ -262,6 +263,7 @@ int arch_cpu_init_dm(void) return 0; } +EVENT_SPY(EVT_DM_POST_INIT, quark_init_pcie); int checkcpu(void) { diff --git a/arch/x86/include/asm/fsp2/fsp_api.h b/arch/x86/include/asm/fsp2/fsp_api.h index dccbfa45a1b..ca3f6848b61 100644 --- a/arch/x86/include/asm/fsp2/fsp_api.h +++ b/arch/x86/include/asm/fsp2/fsp_api.h @@ -60,4 +60,12 @@ int fsp_silicon_init(bool s3wake, bool use_spi_flash); typedef asmlinkage int (*fsp_silicon_init_func)(struct fsps_upd *params); +/** + * fsp_setup_pinctrl() - Set up the pinctrl for FSP + * + * @ctx: Event context (not used) + * @event: Event information (not used) + */ +int fsp_setup_pinctrl(void *ctx, struct event *event); + #endif diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c index 5afdce1e0d4..b15926e8247 100644 --- a/arch/x86/lib/fsp2/fsp_init.c +++ b/arch/x86/lib/fsp2/fsp_init.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -18,7 +19,7 @@ #include #include -int arch_cpu_init_dm(void) +int fsp_setup_pinctrl(void *ctx, struct event *event) { struct udevice *dev; ofnode node; @@ -41,6 +42,7 @@ int arch_cpu_init_dm(void) return ret; } +EVENT_SPY(EVT_DM_POST_INIT, fsp_setup_pinctrl); #if !defined(CONFIG_TPL_BUILD) binman_sym_declare(ulong, intel_fsp_m, image_pos); diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index b18c1cd6092..2d50c62964c 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -27,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR; -__weak int arch_cpu_init_dm(void) +__weak int fsp_setup_pinctrl(void *ctx, struct event *event) { return 0; } @@ -89,7 +90,7 @@ static int x86_spl_init(void) return ret; } #ifndef CONFIG_TPL - ret = arch_cpu_init_dm(); + ret = fsp_setup_pinctrl(NULL, NULL); if (ret) { debug("%s: arch_cpu_init_dm() failed\n", __func__); return ret; diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c index 5b57e53c2dd..18b05b2f672 100644 --- a/arch/x86/lib/tpl.c +++ b/arch/x86/lib/tpl.c @@ -19,11 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; -__weak int arch_cpu_init_dm(void) -{ - return 0; -} - static int x86_tpl_init(void) { int ret; @@ -44,11 +39,6 @@ static int x86_tpl_init(void) debug("%s: arch_cpu_init() failed\n", __func__); return ret; } - ret = arch_cpu_init_dm(); - if (ret) { - debug("%s: arch_cpu_init_dm() failed\n", __func__); - return ret; - } preloader_console_init(); return 0; diff --git a/common/board_f.c b/common/board_f.c index 0ef34c75759..5b655ad6efe 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -803,11 +803,6 @@ __weak int reserve_arch(void) return 0; } -__weak int arch_cpu_init_dm(void) -{ - return 0; -} - __weak int checkcpu(void) { return 0; @@ -848,7 +843,6 @@ static const init_fnc_t init_sequence_f[] = { arch_cpu_init, /* basic arch cpu dependent setup */ mach_cpu_init, /* SoC/machine dependent CPU setup */ initf_dm, - arch_cpu_init_dm, #if defined(CONFIG_BOARD_EARLY_INIT_F) board_early_init_f, #endif diff --git a/common/event.c b/common/event.c index 4270809d496..9d67a060a02 100644 --- a/common/event.c +++ b/common/event.c @@ -26,6 +26,7 @@ const char *const type_name[] = { "test", /* Events related to driver model */ + "dm_post_init", "dm_pre_probe", "dm_post_probe", "dm_pre_remove", diff --git a/drivers/core/root.c b/drivers/core/root.c index e3f87956d86..8efb4256b27 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -404,6 +404,11 @@ int dm_init_and_scan(bool pre_reloc_only) return ret; } } + if (CONFIG_IS_ENABLED(DM_EVENT)) { + ret = event_notify_null(EVT_DM_POST_INIT); + if (ret) + return log_msg_ret("ev", ret); + } return 0; } diff --git a/include/event.h b/include/event.h index 6b347e92f08..78a42374acb 100644 --- a/include/event.h +++ b/include/event.h @@ -20,6 +20,7 @@ enum event_t { EVT_TEST, /* Events related to driver model */ + EVT_DM_POST_INIT, EVT_DM_PRE_PROBE, EVT_DM_POST_PROBE, EVT_DM_PRE_REMOVE, diff --git a/include/init.h b/include/init.h index c03b29bb0db..74496500d29 100644 --- a/include/init.h +++ b/include/init.h @@ -45,17 +45,6 @@ void board_init_f(ulong dummy); */ int arch_cpu_init(void); -/** - * arch_cpu_init_dm() - init CPU after driver model is available - * - * This is called immediately after driver model is available before - * relocation. This is similar to arch_cpu_init() but is able to reference - * devices - * - * Return: 0 if OK, -ve on error - */ -int arch_cpu_init_dm(void); - /** * mach_cpu_init() - SoC/machine dependent CPU setup * -- cgit v1.3.1 From 5bb26a59c46c510828f99ccf009ec1a03c52409c Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 16 Feb 2022 18:23:22 +1030 Subject: ram: aspeed: Rework kconfig options Ensure the ASPEED related options are grouped together under the RAM option when enabling support. This also makes some minor grammar corrections and renames options so they present cleanly in menuconfig. There should be no functional change to the configuration or binary. Signed-off-by: Joel Stanley Reviewed-by: Dylan Hung --- drivers/ram/aspeed/Kconfig | 91 ++++++++++++++++++++++++++-------------------- 1 file changed, 51 insertions(+), 40 deletions(-) (limited to 'drivers') diff --git a/drivers/ram/aspeed/Kconfig b/drivers/ram/aspeed/Kconfig index 576d5af8688..0deab8649b6 100644 --- a/drivers/ram/aspeed/Kconfig +++ b/drivers/ram/aspeed/Kconfig @@ -1,66 +1,77 @@ -if RAM || SPL_RAM +menuconfig ASPEED_RAM + bool "ASPEED SDRAM configuration" + depends on RAM && ARCH_ASPEED + default ARCH_ASPEED + help + Configuration options for DDR SDRAM on ASPEED systems. + + RAM initialisation is always built in for the platform. This menu + allows customisation of the configuration used. + +if ASPEED_RAM config ASPEED_DDR4_DUALX8 bool "Enable Dual X8 DDR4 die" - depends on DM && OF_CONTROL && ARCH_ASPEED + depends on ASPEED_RAM + help + Say Y if dual X8 DDR4 die is used on the board. The ASPEED DDRM + SRAM controller needs to know if the memory chip mounted on the + board is dual x8 die or not, otherwise it may get the wrong + size of the memory space. + +config ASPEED_BYPASS_SELFTEST + depends on ASPEED_RAM + depends on ASPEED_AST2600 + bool "Bypass self test during initialization" + help + Say Y here to bypass DRAM self test to speed up the boot time. + +config ASPEED_ECC + bool "ASPEED SDRAM ECC" + depends on ASPEED_RAM + depends on ASPEED_AST2600 help - Say Y if dual X8 DDR4 die is used on the board. The aspeed ddr sdram - controller needs to know if the memory chip mounted on the board is dual - x8 die or not. Or it may get the wrong size of the memory space. + Enable SDRAM ECC function. This configures the SDRAM controller to + perform error detection and correction, sacrificing 1/9th of the + installed RAM to do so. -if ASPEED_AST2600 + +config ASPEED_ECC_SIZE + int "ECC size: 0=driver auto-caluated" + depends on ASPEED_ECC + default 0 + help + SDRAM size with the error correcting code enabled. The unit is + in Megabytes. Noted that only the 8/9 of the configured size + can be used by the system. The remaining 1/9 will be used by + the ECC engine. If the size is set to 0, the sdram driver will + calculate the SDRAM size and set the whole range be ECC enabled. choice - prompt "DDR4 target date rate" + prompt "AST2600 DDR4 target date rate" default ASPEED_DDR4_1600 + depends on ASPEED_RAM + depends on ASPEED_AST2600 config ASPEED_DDR4_400 - bool "DDR4 targets at 400Mbps" - depends on DM && OF_CONTROL && ARCH_ASPEED + bool "400Mbps" help select DDR4 target data rate at 400M config ASPEED_DDR4_800 - bool "DDR4 targets at 800Mbps" - depends on DM && OF_CONTROL && ARCH_ASPEED + bool "800Mbps" help select DDR4 target data rate at 800M config ASPEED_DDR4_1333 - bool "DDR4 targets at 1333Mbps" - depends on DM && OF_CONTROL && ARCH_ASPEED + bool "1333Mbps" help select DDR4 target data rate at 1333M config ASPEED_DDR4_1600 - bool "DDR4 targets at 1600Mbps" - depends on DM && OF_CONTROL && ARCH_ASPEED + bool "1600Mbps" help select DDR4 target data rate at 1600M endchoice -config ASPEED_BYPASS_SELFTEST - bool "bypass self test during DRAM initialization" - help - Say Y here to bypass DRAM self test to speed up the boot time - -config ASPEED_ECC - bool "aspeed SDRAM error correcting code" - depends on DM && OF_CONTROL && ARCH_ASPEED - help - enable SDRAM ECC function - -if ASPEED_ECC -config ASPEED_ECC_SIZE - int "ECC size: 0=driver auto-caluated" - depends on ASPEED_ECC - default 0 - help - SDRAM size with the error correcting code enabled. The unit is - in Megabytes. Noted that only the 8/9 of the configured size - can be used by the system. The remaining 1/9 will be used by - the ECC engine. If the size is set to 0, the sdram driver will - calculate the SDRAM size and set the whole range be ECC enabled. -endif # end of ASPEED_ECC -endif # end of ASPEED_AST2600 -endif # end of RAM || SPL_RAM +endif # End of ASPEED_RAM -- cgit v1.3.1 From dbd673f14da34148f5a6105a39cd4458a92cac67 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 23 Feb 2022 15:23:05 +0100 Subject: pinctrl: zynqmp: Add pinctrl driver Add pinctrl driver for Xilinx ZynqMP SOC. This driver is compatible with linux device tree parameters for configuring pinmux and pinconf. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/2d7eefa83c8c0129f7243a25de56a289e948f6c6.1645626183.git.michal.simek@xilinx.com --- MAINTAINERS | 1 + drivers/pinctrl/Kconfig | 10 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-zynqmp.c | 644 +++++++++++++++++++++++++++++++++++++++ include/zynqmp_firmware.h | 43 +++ 5 files changed, 699 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-zynqmp.c (limited to 'drivers') diff --git a/MAINTAINERS b/MAINTAINERS index 4e740fb5d26..915316a86e9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -620,6 +620,7 @@ F: drivers/mtd/nand/raw/zynq_nand.c F: drivers/net/phy/ethernet_id.c F: drivers/net/phy/xilinx_phy.c F: drivers/net/zynq_gem.c +F: drivers/pinctrl/pinctrl-zynqmp.c F: drivers/serial/serial_zynq.c F: drivers/spi/zynq_qspi.c F: drivers/spi/zynq_spi.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 03946245c7d..d7477d7c336 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -318,6 +318,16 @@ config PINCTRL_K210 Support pin multiplexing on the K210. The "FPIOA" can remap any supported function to any multifunctional IO pin. It can also perform basic GPIO functions, such as reading the current value of a pin. + +config PINCTRL_ZYNQMP + bool "Xilinx ZynqMP pin control driver" + depends on DM && PINCTRL_GENERIC && ARCH_ZYNQMP + default y + help + Support pin multiplexing control on Xilinx ZynqMP. The driver uses + Generic Pinctrl framework and is compatible with the Linux driver, + i.e. it uses the same device tree configuration. + endif source "drivers/pinctrl/broadcom/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index fd736a7f640..ddddd13433c 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -30,3 +30,4 @@ obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o obj-$(CONFIG_$(SPL_)PINCTRL_STMFX) += pinctrl-stmfx.o obj-y += broadcom/ +obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c new file mode 100644 index 00000000000..7c5a02db1b9 --- /dev/null +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -0,0 +1,644 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx pinctrl driver for ZynqMP + * + * Author(s): Ashok Reddy Soma + * Michal Simek + * + * Copyright (C) 2021 Xilinx, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PINCTRL_GET_FUNC_GROUPS_RESP_LEN 12 +#define PINCTRL_GET_PIN_GROUPS_RESP_LEN 12 +#define NUM_GROUPS_PER_RESP 6 +#define NA_GROUP -1 +#define RESERVED_GROUP -2 +#define MAX_GROUP_PIN 50 +#define MAX_PIN_GROUPS 50 +#define MAX_GROUP_NAME_LEN 32 +#define MAX_FUNC_NAME_LEN 16 + +#define DRIVE_STRENGTH_2MA 2 +#define DRIVE_STRENGTH_4MA 4 +#define DRIVE_STRENGTH_8MA 8 +#define DRIVE_STRENGTH_12MA 12 + +/* + * This driver works with very simple configuration that has the same name + * for group and function. This way it is compatible with the Linux Kernel + * driver. + */ +struct zynqmp_pinctrl_priv { + u32 npins; + u32 nfuncs; + u32 ngroups; + struct zynqmp_pmux_function *funcs; + struct zynqmp_pctrl_group *groups; +}; + +/** + * struct zynqmp_pinctrl_config - pinconfig parameters + * @slew: Slew rate slow or fast + * @bias: Bias enabled or disabled + * @pull_ctrl: Pull control pull up or pull down + * @input_type: CMOS or Schmitt + * @drive_strength: Drive strength 2mA/4mA/8mA/12mA + * @volt_sts: Voltage status 1.8V or 3.3V + * @tri_state: Tristate enabled or disabled + * + * This structure holds information about pin control config + * option that can be set for each pin. + */ +struct zynqmp_pinctrl_config { + u32 slew; + u32 bias; + u32 pull_ctrl; + u32 input_type; + u32 drive_strength; + u32 volt_sts; + u32 tri_state; +}; + +/** + * enum zynqmp_pin_config_param - possible pin configuration parameters + * @PIN_CONFIG_IOSTANDARD: if the pin can select an IO standard, + * the argument to this parameter (on a + * custom format) tells the driver which + * alternative IO standard to use + * @PIN_CONFIG_SCHMITTCMOS: this parameter (on a custom format) allows + * to select schmitt or cmos input for MIO pins + */ +enum zynqmp_pin_config_param { + PIN_CONFIG_IOSTANDARD = PIN_CONFIG_END + 1, + PIN_CONFIG_SCHMITTCMOS, +}; + +/** + * struct zynqmp_pmux_function - a pinmux function + * @name: Name of the pinmux function + * @groups: List of pingroups for this function + * @ngroups: Number of entries in @groups + * + * This structure holds information about pin control function + * and function group names supporting that function. + */ +struct zynqmp_pmux_function { + char name[MAX_FUNC_NAME_LEN]; + const char * const *groups; + unsigned int ngroups; +}; + +/** + * struct zynqmp_pctrl_group - Pin control group info + * @name: Group name + * @pins: Group pin numbers + * @npins: Number of pins in group + */ +struct zynqmp_pctrl_group { + const char *name; + unsigned int pins[MAX_GROUP_PIN]; + unsigned int npins; +}; + +static char pin_name[PINNAME_SIZE]; + +/** + * zynqmp_pm_query_data() - Get query data from firmware + * @qid: Value of enum pm_query_id + * @arg1: Argument 1 + * @arg2: Argument 2 + * @out: Returned output value + * + * Return: Returns status, either success or error+reason + */ +static int zynqmp_pm_query_data(enum pm_query_id qid, u32 arg1, u32 arg2, u32 *out) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + ret = xilinx_pm_request(PM_QUERY_DATA, qid, arg1, arg2, 0, ret_payload); + if (ret) + return ret; + + *out = ret_payload[1]; + + return ret; +} + +static int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param, u32 *value) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + /* Get config for the pin */ + ret = xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_GET, pin, param, 0, 0, ret_payload); + if (ret) { + printf("%s failed\n", __func__); + return ret; + } + + *value = ret_payload[1]; + + return ret; +} + +static int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, u32 value) +{ + int ret; + + /* Request the pin first */ + ret = xilinx_pm_request(PM_PINCTRL_REQUEST, pin, 0, 0, 0, NULL); + if (ret) { + printf("%s: pin request failed\n", __func__); + return ret; + } + + /* Set config for the pin */ + ret = xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, pin, param, value, 0, NULL); + if (ret) { + printf("%s failed\n", __func__); + return ret; + } + + return ret; +} + +static int zynqmp_pinctrl_get_function_groups(u32 fid, u32 index, u16 *groups) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + ret = xilinx_pm_request(PM_QUERY_DATA, PM_QID_PINCTRL_GET_FUNCTION_GROUPS, + fid, index, 0, ret_payload); + if (ret) { + printf("%s failed\n", __func__); + return ret; + } + + memcpy(groups, &ret_payload[1], PINCTRL_GET_FUNC_GROUPS_RESP_LEN); + + return ret; +} + +static int zynqmp_pinctrl_prepare_func_groups(u32 fid, + struct zynqmp_pmux_function *func, + struct zynqmp_pctrl_group *groups) +{ + const char **fgroups; + char name[MAX_GROUP_NAME_LEN]; + u16 resp[NUM_GROUPS_PER_RESP] = {0}; + int ret, index, i; + + fgroups = kcalloc(func->ngroups, sizeof(*fgroups), GFP_KERNEL); + if (!fgroups) + return -ENOMEM; + + for (index = 0; index < func->ngroups; index += NUM_GROUPS_PER_RESP) { + ret = zynqmp_pinctrl_get_function_groups(fid, index, resp); + if (ret) + return ret; + + for (i = 0; i < NUM_GROUPS_PER_RESP; i++) { + if (resp[i] == (u16)NA_GROUP) + goto done; + if (resp[i] == (u16)RESERVED_GROUP) + continue; + + snprintf(name, MAX_GROUP_NAME_LEN, "%s_%d_grp", + func->name, index + i); + fgroups[index + i] = strdup(name); + + snprintf(name, MAX_GROUP_NAME_LEN, "%s_%d_grp", + func->name, index + i); + groups[resp[i]].name = strdup(name); + } + } +done: + func->groups = fgroups; + + return ret; +} + +static int zynqmp_pinctrl_get_pin_groups(u32 pin, u32 index, u16 *groups) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + ret = xilinx_pm_request(PM_QUERY_DATA, PM_QID_PINCTRL_GET_PIN_GROUPS, + pin, index, 0, ret_payload); + if (ret) { + printf("%s failed to get pin groups\n", __func__); + return ret; + } + + memcpy(groups, &ret_payload[1], PINCTRL_GET_PIN_GROUPS_RESP_LEN); + + return ret; +} + +static void zynqmp_pinctrl_group_add_pin(struct zynqmp_pctrl_group *group, + unsigned int pin) +{ + group->pins[group->npins++] = pin; +} + +static int zynqmp_pinctrl_create_pin_groups(struct zynqmp_pctrl_group *groups, + unsigned int pin) +{ + u16 resp[NUM_GROUPS_PER_RESP] = {0}; + int ret, i, index = 0; + + do { + ret = zynqmp_pinctrl_get_pin_groups(pin, index, resp); + if (ret) + return ret; + + for (i = 0; i < NUM_GROUPS_PER_RESP; i++) { + if (resp[i] == (u16)NA_GROUP) + goto done; + if (resp[i] == (u16)RESERVED_GROUP) + continue; + zynqmp_pinctrl_group_add_pin(&groups[resp[i]], pin); + } + index += NUM_GROUPS_PER_RESP; + } while (index <= MAX_PIN_GROUPS); + +done: + return ret; +} + +static int zynqmp_pinctrl_probe(struct udevice *dev) +{ + struct zynqmp_pinctrl_priv *priv = dev_get_priv(dev); + int ret, i; + u32 pin; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + /* Get number of pins first */ + ret = zynqmp_pm_query_data(PM_QID_PINCTRL_GET_NUM_PINS, 0, 0, &priv->npins); + if (ret) { + printf("%s failed to get no of pins\n", __func__); + return ret; + } + + /* Get number of functions available */ + ret = zynqmp_pm_query_data(PM_QID_PINCTRL_GET_NUM_FUNCTIONS, 0, 0, &priv->nfuncs); + if (ret) { + printf("%s failed to get no of functions\n", __func__); + return ret; + } + + /* Allocating structures for functions and its groups */ + priv->funcs = kzalloc(sizeof(*priv->funcs) * priv->nfuncs, GFP_KERNEL); + if (!priv->funcs) + return -ENOMEM; + + for (i = 0; i < priv->nfuncs; i++) { + /* Get function name for the function and fill */ + xilinx_pm_request(PM_QUERY_DATA, PM_QID_PINCTRL_GET_FUNCTION_NAME, + i, 0, 0, ret_payload); + + memcpy((void *)priv->funcs[i].name, ret_payload, MAX_FUNC_NAME_LEN); + + /* And fill number of groups available for certain function */ + xilinx_pm_request(PM_QUERY_DATA, PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS, + i, 0, 0, ret_payload); + + priv->funcs[i].ngroups = ret_payload[1]; + priv->ngroups += priv->funcs[i].ngroups; + } + + /* Prepare all groups */ + priv->groups = kzalloc(sizeof(*priv->groups) * priv->ngroups, + GFP_KERNEL); + if (!priv->groups) + return -ENOMEM; + + for (i = 0; i < priv->nfuncs; i++) { + ret = zynqmp_pinctrl_prepare_func_groups(i, &priv->funcs[i], + priv->groups); + if (ret) { + printf("Failed to prepare_func_groups\n"); + return ret; + } + } + + for (pin = 0; pin < priv->npins; pin++) { + ret = zynqmp_pinctrl_create_pin_groups(priv->groups, pin); + if (ret) + return ret; + } + + return 0; +} + +static int zynqmp_pinctrl_get_functions_count(struct udevice *dev) +{ + struct zynqmp_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->nfuncs; +} + +static const char *zynqmp_pinctrl_get_function_name(struct udevice *dev, + unsigned int selector) +{ + struct zynqmp_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->funcs[selector].name; +} + +static int zynqmp_pinmux_set(struct udevice *dev, unsigned int selector, + unsigned int func_selector) +{ + int ret; + + /* Request the pin first */ + ret = xilinx_pm_request(PM_PINCTRL_REQUEST, selector, 0, 0, 0, NULL); + if (ret) { + printf("%s: pin request failed\n", __func__); + return ret; + } + + /* Set the pin function */ + ret = xilinx_pm_request(PM_PINCTRL_SET_FUNCTION, selector, func_selector, + 0, 0, NULL); + if (ret) { + printf("%s: Failed to set pinmux function\n", __func__); + return ret; + } + + return 0; +} + +static int zynqmp_pinmux_group_set(struct udevice *dev, unsigned int selector, + unsigned int func_selector) +{ + int i; + struct zynqmp_pinctrl_priv *priv = dev_get_priv(dev); + const struct zynqmp_pctrl_group *pgrp = &priv->groups[selector]; + + for (i = 0; i < pgrp->npins; i++) + zynqmp_pinmux_set(dev, pgrp->pins[i], func_selector); + + return 0; +} + +static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin, + unsigned int param, unsigned int arg) +{ + int ret = 0; + unsigned int value; + + switch (param) { + case PIN_CONFIG_SLEW_RATE: + param = PM_PINCTRL_CONFIG_SLEW_RATE; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; + case PIN_CONFIG_BIAS_PULL_UP: + param = PM_PINCTRL_CONFIG_PULL_CTRL; + arg = PM_PINCTRL_BIAS_PULL_UP; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + param = PM_PINCTRL_CONFIG_PULL_CTRL; + arg = PM_PINCTRL_BIAS_PULL_DOWN; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; + case PIN_CONFIG_BIAS_DISABLE: + param = PM_PINCTRL_CONFIG_BIAS_STATUS; + arg = PM_PINCTRL_BIAS_DISABLE; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; + case PIN_CONFIG_SCHMITTCMOS: + param = PM_PINCTRL_CONFIG_SCHMITT_CMOS; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + param = PM_PINCTRL_CONFIG_SCHMITT_CMOS; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; + case PIN_CONFIG_DRIVE_STRENGTH: + switch (arg) { + case DRIVE_STRENGTH_2MA: + value = PM_PINCTRL_DRIVE_STRENGTH_2MA; + break; + case DRIVE_STRENGTH_4MA: + value = PM_PINCTRL_DRIVE_STRENGTH_4MA; + break; + case DRIVE_STRENGTH_8MA: + value = PM_PINCTRL_DRIVE_STRENGTH_8MA; + break; + case DRIVE_STRENGTH_12MA: + value = PM_PINCTRL_DRIVE_STRENGTH_12MA; + break; + default: + /* Invalid drive strength */ + dev_warn(dev, "Invalid drive strength for pin %d\n", pin); + return -EINVAL; + } + + param = PM_PINCTRL_CONFIG_DRIVE_STRENGTH; + ret = zynqmp_pm_pinctrl_set_config(pin, param, value); + break; + case PIN_CONFIG_IOSTANDARD: + param = PM_PINCTRL_CONFIG_VOLTAGE_STATUS; + ret = zynqmp_pm_pinctrl_get_config(pin, param, &value); + if (arg != value) + dev_warn(dev, "Invalid IO Standard requested for pin %d\n", + pin); + break; + case PIN_CONFIG_POWER_SOURCE: + param = PM_PINCTRL_CONFIG_VOLTAGE_STATUS; + ret = zynqmp_pm_pinctrl_get_config(pin, param, &value); + if (arg != value) + dev_warn(dev, "Invalid IO Standard requested for pin %d\n", + pin); + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + case PIN_CONFIG_LOW_POWER_MODE: + /* + * This cases are mentioned in dts but configurable + * registers are unknown. So falling through to ignore + * boot time warnings as of now. + */ + ret = 0; + break; + default: + dev_warn(dev, "unsupported configuration parameter '%u'\n", + param); + ret = -ENOTSUPP; + break; + } + + return ret; +} + +static int zynqmp_pinconf_group_set(struct udevice *dev, + unsigned int group_selector, + unsigned int param, unsigned int arg) +{ + int i; + struct zynqmp_pinctrl_priv *priv = dev_get_priv(dev); + const struct zynqmp_pctrl_group *pgrp = &priv->groups[group_selector]; + + for (i = 0; i < pgrp->npins; i++) + zynqmp_pinconf_set(dev, pgrp->pins[i], param, arg); + + return 0; +} + +static int zynqmp_pinctrl_get_pins_count(struct udevice *dev) +{ + struct zynqmp_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->npins; +} + +static const char *zynqmp_pinctrl_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + snprintf(pin_name, PINNAME_SIZE, "MIO%d", selector); + + return pin_name; +} + +static int zynqmp_pinctrl_get_pin_muxing(struct udevice *dev, + unsigned int selector, + char *buf, + int size) +{ + struct zynqmp_pinctrl_config pinmux; + + zynqmp_pm_pinctrl_get_config(selector, PM_PINCTRL_CONFIG_SLEW_RATE, + &pinmux.slew); + zynqmp_pm_pinctrl_get_config(selector, PM_PINCTRL_CONFIG_BIAS_STATUS, + &pinmux.bias); + zynqmp_pm_pinctrl_get_config(selector, PM_PINCTRL_CONFIG_PULL_CTRL, + &pinmux.pull_ctrl); + zynqmp_pm_pinctrl_get_config(selector, PM_PINCTRL_CONFIG_SCHMITT_CMOS, + &pinmux.input_type); + zynqmp_pm_pinctrl_get_config(selector, PM_PINCTRL_CONFIG_DRIVE_STRENGTH, + &pinmux.drive_strength); + zynqmp_pm_pinctrl_get_config(selector, PM_PINCTRL_CONFIG_VOLTAGE_STATUS, + &pinmux.volt_sts); + + switch (pinmux.drive_strength) { + case PM_PINCTRL_DRIVE_STRENGTH_2MA: + pinmux.drive_strength = DRIVE_STRENGTH_2MA; + break; + case PM_PINCTRL_DRIVE_STRENGTH_4MA: + pinmux.drive_strength = DRIVE_STRENGTH_4MA; + break; + case PM_PINCTRL_DRIVE_STRENGTH_8MA: + pinmux.drive_strength = DRIVE_STRENGTH_8MA; + break; + case PM_PINCTRL_DRIVE_STRENGTH_12MA: + pinmux.drive_strength = DRIVE_STRENGTH_12MA; + break; + default: + /* Invalid drive strength */ + dev_warn(dev, "Invalid drive strength\n"); + return -EINVAL; + } + + snprintf(buf, size, "slew:%s\tbias:%s\tpull:%s\tinput:%s\tdrive:%dmA\tvolt:%s", + pinmux.slew ? "slow" : "fast", + pinmux.bias ? "enabled" : "disabled", + pinmux.pull_ctrl ? "up" : "down", + pinmux.input_type ? "schmitt" : "cmos", + pinmux.drive_strength, + pinmux.volt_sts ? "1.8" : "3.3"); + + return 0; +} + +static int zynqmp_pinctrl_get_groups_count(struct udevice *dev) +{ + struct zynqmp_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->ngroups; +} + +static const char *zynqmp_pinctrl_get_group_name(struct udevice *dev, + unsigned int selector) +{ + struct zynqmp_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->groups[selector].name; +} + +static const struct pinconf_param zynqmp_conf_params[] = { + { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, + { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, + { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, + { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 }, + { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 }, + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, + { "drive-strength-microamp", PIN_CONFIG_DRIVE_STRENGTH_UA, 0 }, + { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, + { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "input-schmitt", PIN_CONFIG_INPUT_SCHMITT, 0 }, + { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, + { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, + { "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 }, + { "low-power-enable", PIN_CONFIG_LOW_POWER_MODE, 1 }, + { "output-disable", PIN_CONFIG_OUTPUT_ENABLE, 0 }, + { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 }, + { "output-high", PIN_CONFIG_OUTPUT, 1, }, + { "output-low", PIN_CONFIG_OUTPUT, 0, }, + { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, + { "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 }, + { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, + { "skew-delay", PIN_CONFIG_SKEW_DELAY, 0 }, + /* zynqmp specific */ + {"io-standard", PIN_CONFIG_IOSTANDARD, IO_STANDARD_LVCMOS18}, + {"schmitt-cmos", PIN_CONFIG_SCHMITTCMOS, PM_PINCTRL_INPUT_TYPE_SCHMITT}, +}; + +static struct pinctrl_ops zynqmp_pinctrl_ops = { + .get_pins_count = zynqmp_pinctrl_get_pins_count, + .get_pin_name = zynqmp_pinctrl_get_pin_name, + .get_pin_muxing = zynqmp_pinctrl_get_pin_muxing, + .set_state = pinctrl_generic_set_state, + .get_groups_count = zynqmp_pinctrl_get_groups_count, + .get_group_name = zynqmp_pinctrl_get_group_name, + .get_functions_count = zynqmp_pinctrl_get_functions_count, + .get_function_name = zynqmp_pinctrl_get_function_name, + .pinmux_group_set = zynqmp_pinmux_group_set, + .pinmux_set = zynqmp_pinmux_set, + .pinconf_params = zynqmp_conf_params, + .pinconf_group_set = zynqmp_pinconf_group_set, + .pinconf_set = zynqmp_pinconf_set, + .pinconf_num_params = ARRAY_SIZE(zynqmp_conf_params), +}; + +static const struct udevice_id zynqmp_pinctrl_ids[] = { + { .compatible = "xlnx,zynqmp-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_zynqmp) = { + .name = "zynqmp-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = zynqmp_pinctrl_ids, + .priv_auto = sizeof(struct zynqmp_pinctrl_priv), + .ops = &zynqmp_pinctrl_ops, + .probe = zynqmp_pinctrl_probe, +}; diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 60c3df3da41..f577008736d 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -177,6 +177,49 @@ enum pm_query_id { PM_QID_CLOCK_GET_MAX_DIVISOR = 13, }; +enum pm_pinctrl_config_param { + PM_PINCTRL_CONFIG_SLEW_RATE = 0, + PM_PINCTRL_CONFIG_BIAS_STATUS = 1, + PM_PINCTRL_CONFIG_PULL_CTRL = 2, + PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3, + PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4, + PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5, + PM_PINCTRL_CONFIG_TRI_STATE = 6, + PM_PINCTRL_CONFIG_MAX = 7, +}; + +enum pm_pinctrl_slew_rate { + PM_PINCTRL_SLEW_RATE_FAST = 0, + PM_PINCTRL_SLEW_RATE_SLOW = 1, +}; + +enum pm_pinctrl_bias_status { + PM_PINCTRL_BIAS_DISABLE = 0, + PM_PINCTRL_BIAS_ENABLE = 1, +}; + +enum pm_pinctrl_pull_ctrl { + PM_PINCTRL_BIAS_PULL_DOWN = 0, + PM_PINCTRL_BIAS_PULL_UP = 1, +}; + +enum pm_pinctrl_schmitt_cmos { + PM_PINCTRL_INPUT_TYPE_CMOS = 0, + PM_PINCTRL_INPUT_TYPE_SCHMITT = 1, +}; + +enum pm_pinctrl_drive_strength { + PM_PINCTRL_DRIVE_STRENGTH_2MA = 0, + PM_PINCTRL_DRIVE_STRENGTH_4MA = 1, + PM_PINCTRL_DRIVE_STRENGTH_8MA = 2, + PM_PINCTRL_DRIVE_STRENGTH_12MA = 3, +}; + +enum pm_pinctrl_tri_state { + PM_PINCTRL_TRI_STATE_DISABLE = 0, + PM_PINCTRL_TRI_STATE_ENABLE = 1, +}; + enum zynqmp_pm_reset_action { PM_RESET_ACTION_RELEASE = 0, PM_RESET_ACTION_ASSERT = 1, -- cgit v1.3.1 From b07fb55747926afe36cb970335eb1700cc32eb6a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 11 Mar 2022 09:12:09 -0500 Subject: net: fec_mxc: Remove non-DM_ETH code Now that all boards have been converted, remove the non-DM_ETH code. Cc: Fabio Estevam Cc: Ramon Fried Cc: Stefano Babic Signed-off-by: Tom Rini --- drivers/net/fec_mxc.c | 245 -------------------------------------------------- 1 file changed, 245 deletions(-) (limited to 'drivers') diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 985b0384473..a26927582d2 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -408,20 +408,11 @@ static int fec_get_hwaddr(int dev_id, unsigned char *mac) return !is_valid_ethaddr(mac); } -#ifdef CONFIG_DM_ETH static int fecmxc_set_hwaddr(struct udevice *dev) -#else -static int fec_set_hwaddr(struct eth_device *dev) -#endif { -#ifdef CONFIG_DM_ETH struct fec_priv *fec = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); uchar *mac = pdata->enetaddr; -#else - uchar *mac = dev->enetaddr; - struct fec_priv *fec = (struct fec_priv *)dev->priv; -#endif writel(0, &fec->eth->iaddr1); writel(0, &fec->eth->iaddr2); @@ -468,17 +459,9 @@ static void fec_reg_setup(struct fec_priv *fec) * Start the FEC engine * @param[in] dev Our device to handle */ -#ifdef CONFIG_DM_ETH static int fec_open(struct udevice *dev) -#else -static int fec_open(struct eth_device *edev) -#endif { -#ifdef CONFIG_DM_ETH struct fec_priv *fec = dev_get_priv(dev); -#else - struct fec_priv *fec = (struct fec_priv *)edev->priv; -#endif int speed; ulong addr, size; int i; @@ -589,27 +572,15 @@ static int fec_open(struct eth_device *edev) return 0; } -#ifdef CONFIG_DM_ETH static int fecmxc_init(struct udevice *dev) -#else -static int fec_init(struct eth_device *dev, struct bd_info *bd) -#endif { -#ifdef CONFIG_DM_ETH struct fec_priv *fec = dev_get_priv(dev); -#else - struct fec_priv *fec = (struct fec_priv *)dev->priv; -#endif u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop; u8 *i; ulong addr; /* Initialize MAC address */ -#ifdef CONFIG_DM_ETH fecmxc_set_hwaddr(dev); -#else - fec_set_hwaddr(dev); -#endif /* Setup transmit descriptors, there are two in total. */ fec_tbd_init(fec); @@ -661,17 +632,9 @@ static int fec_init(struct eth_device *dev, struct bd_info *bd) * Halt the FEC engine * @param[in] dev Our device to handle */ -#ifdef CONFIG_DM_ETH static void fecmxc_halt(struct udevice *dev) -#else -static void fec_halt(struct eth_device *dev) -#endif { -#ifdef CONFIG_DM_ETH struct fec_priv *fec = dev_get_priv(dev); -#else - struct fec_priv *fec = (struct fec_priv *)dev->priv; -#endif int counter = 0xffff; /* issue graceful stop command to the FEC transmitter if necessary */ @@ -705,11 +668,7 @@ static void fec_halt(struct eth_device *dev) * @param[in] length Data count in bytes * Return: 0 on success */ -#ifdef CONFIG_DM_ETH static int fecmxc_send(struct udevice *dev, void *packet, int length) -#else -static int fec_send(struct eth_device *dev, void *packet, int length) -#endif { unsigned int status; u32 size; @@ -721,11 +680,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length) * This routine transmits one frame. This routine only accepts * 6-byte Ethernet addresses. */ -#ifdef CONFIG_DM_ETH struct fec_priv *fec = dev_get_priv(dev); -#else - struct fec_priv *fec = (struct fec_priv *)dev->priv; -#endif /* * Check for valid length of data. @@ -856,17 +811,9 @@ out: * @param[in] dev Our ethernet device to handle * Return: Length of packet read */ -#ifdef CONFIG_DM_ETH static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp) -#else -static int fec_recv(struct eth_device *dev) -#endif { -#ifdef CONFIG_DM_ETH struct fec_priv *fec = dev_get_priv(dev); -#else - struct fec_priv *fec = (struct fec_priv *)dev->priv; -#endif struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; unsigned long ievent; int frame_length, len = 0; @@ -874,28 +821,19 @@ static int fec_recv(struct eth_device *dev) ulong addr, size, end; int i; -#ifdef CONFIG_DM_ETH *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE); if (*packetp == 0) { printf("%s: error allocating packetp\n", __func__); return -ENOMEM; } -#else - ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE); -#endif /* Check if any critical events have happened */ ievent = readl(&fec->eth->ievent); writel(ievent, &fec->eth->ievent); debug("fec_recv: ievent 0x%lx\n", ievent); if (ievent & FEC_IEVENT_BABR) { -#ifdef CONFIG_DM_ETH fecmxc_halt(dev); fecmxc_init(dev); -#else - fec_halt(dev); - fec_init(dev, fec->bd); -#endif printf("some error: 0x%08lx\n", ievent); return 0; } @@ -907,18 +845,10 @@ static int fec_recv(struct eth_device *dev) if (ievent & FEC_IEVENT_GRA) { /* Graceful stop complete */ if (readl(&fec->eth->x_cntrl) & 0x00000001) { -#ifdef CONFIG_DM_ETH fecmxc_halt(dev); -#else - fec_halt(dev); -#endif writel(~0x00000001 & readl(&fec->eth->x_cntrl), &fec->eth->x_cntrl); -#ifdef CONFIG_DM_ETH fecmxc_init(dev); -#else - fec_init(dev, fec->bd); -#endif } } @@ -959,12 +889,7 @@ static int fec_recv(struct eth_device *dev) swap_packet((uint32_t *)addr, frame_length); #endif -#ifdef CONFIG_DM_ETH memcpy(*packetp, (char *)addr, frame_length); -#else - memcpy(buff, (char *)addr, frame_length); - net_process_received_packet(buff, frame_length); -#endif len = frame_length; } else { if (bd_status & FEC_RBD_ERR) @@ -1104,175 +1029,6 @@ struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) return bus; } -#ifndef CONFIG_DM_ETH -#ifdef CONFIG_PHYLIB -int fec_probe(struct bd_info *bd, int dev_id, uint32_t base_addr, - struct mii_dev *bus, struct phy_device *phydev) -#else -static int fec_probe(struct bd_info *bd, int dev_id, uint32_t base_addr, - struct mii_dev *bus, int phy_id) -#endif -{ - struct eth_device *edev; - struct fec_priv *fec; - unsigned char ethaddr[6]; - char mac[16]; - uint32_t start; - int ret = 0; - - /* create and fill edev struct */ - edev = (struct eth_device *)malloc(sizeof(struct eth_device)); - if (!edev) { - puts("fec_mxc: not enough malloc memory for eth_device\n"); - ret = -ENOMEM; - goto err1; - } - - fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); - if (!fec) { - puts("fec_mxc: not enough malloc memory for fec_priv\n"); - ret = -ENOMEM; - goto err2; - } - - memset(edev, 0, sizeof(*edev)); - memset(fec, 0, sizeof(*fec)); - - ret = fec_alloc_descs(fec); - if (ret) - goto err3; - - edev->priv = fec; - edev->init = fec_init; - edev->send = fec_send; - edev->recv = fec_recv; - edev->halt = fec_halt; - edev->write_hwaddr = fec_set_hwaddr; - - fec->eth = (struct ethernet_regs *)(ulong)base_addr; - fec->bd = bd; - - fec->xcv_type = CONFIG_FEC_XCV_TYPE; - - /* Reset chip. */ - writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); - start = get_timer(0); - while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { - if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { - printf("FEC MXC: Timeout resetting chip\n"); - goto err4; - } - udelay(10); - } - - fec_reg_setup(fec); - fec_set_dev_name(edev->name, dev_id); - fec->dev_id = (dev_id == -1) ? 0 : dev_id; - fec->bus = bus; - fec_mii_setspeed(bus->priv); -#ifdef CONFIG_PHYLIB - fec->phydev = phydev; - phy_connect_dev(phydev, edev); - /* Configure phy */ - phy_config(phydev); -#else - fec->phy_id = phy_id; -#endif - eth_register(edev); - /* only support one eth device, the index number pointed by dev_id */ - edev->index = fec->dev_id; - - if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) { - debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr); - memcpy(edev->enetaddr, ethaddr, 6); - if (fec->dev_id) - sprintf(mac, "eth%daddr", fec->dev_id); - else - strcpy(mac, "ethaddr"); - if (!env_get(mac)) - eth_env_set_enetaddr(mac, ethaddr); - } - return ret; -err4: - fec_free_descs(fec); -err3: - free(fec); -err2: - free(edev); -err1: - return ret; -} - -int fecmxc_initialize_multi(struct bd_info *bd, int dev_id, int phy_id, - uint32_t addr) -{ - uint32_t base_mii; - struct mii_dev *bus = NULL; -#ifdef CONFIG_PHYLIB - struct phy_device *phydev = NULL; -#endif - int ret; - - if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) { - if (enet_fused((ulong)addr)) { - printf("SoC fuse indicates Ethernet@0x%x is unavailable.\n", addr); - return -ENODEV; - } - } - -#ifdef CONFIG_FEC_MXC_MDIO_BASE - /* - * The i.MX28 has two ethernet interfaces, but they are not equal. - * Only the first one can access the MDIO bus. - */ - base_mii = CONFIG_FEC_MXC_MDIO_BASE; -#else - base_mii = addr; -#endif - debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); - bus = fec_get_miibus(base_mii, dev_id); - if (!bus) - return -ENOMEM; -#ifdef CONFIG_PHYLIB - phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII); - if (!phydev) { - mdio_unregister(bus); - free(bus); - return -ENOMEM; - } - ret = fec_probe(bd, dev_id, addr, bus, phydev); -#else - ret = fec_probe(bd, dev_id, addr, bus, phy_id); -#endif - if (ret) { -#ifdef CONFIG_PHYLIB - free(phydev); -#endif - mdio_unregister(bus); - free(bus); - } - return ret; -} - -#ifdef CONFIG_FEC_MXC_PHYADDR -int fecmxc_initialize(struct bd_info *bd) -{ - return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR, - IMX_FEC_BASE); -} -#endif - -#ifndef CONFIG_PHYLIB -int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) -{ - struct fec_priv *fec = (struct fec_priv *)dev->priv; - fec->mii_postcall = cb; - return 0; -} -#endif - -#else - static int fecmxc_read_rom_hwaddr(struct udevice *dev) { struct fec_priv *priv = dev_get_priv(dev); @@ -1626,4 +1382,3 @@ U_BOOT_DRIVER(fecmxc_gem) = { .priv_auto = sizeof(struct fec_priv), .plat_auto = sizeof(struct eth_pdata), }; -#endif -- cgit v1.3.1 From 08f1d58affa4a3ec1fb68717be088dd3556fe26a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 11 Mar 2022 09:12:10 -0500 Subject: net: fec_mxc: Drop CONFIG_FEC_XCV_TYPE With all boards now using DM_ETH we determine the value for CONFIG_FEC_XCV_TYPE at run time, except in the case of the default fall-back. Set the fallback directly now. Cc: Fabio Estevam Cc: Ramon Fried Cc: Stefano Babic Signed-off-by: Tom Rini --- doc/README.fec_mxc | 5 ----- drivers/net/fec_mxc.c | 10 +++------- include/configs/apalis-imx8x.h | 1 - include/configs/aristainetos2.h | 2 -- include/configs/brppt2.h | 1 - include/configs/capricorn-common.h | 3 --- include/configs/cgtqmx8.h | 1 - include/configs/cl-som-imx7.h | 1 - include/configs/cm_fx6.h | 1 - include/configs/dh_imx6.h | 1 - include/configs/imx6_logic.h | 1 - include/configs/imx8mm-cl-iot-gate.h | 1 - include/configs/imx8mm_beacon.h | 1 - include/configs/imx8mm_evk.h | 1 - include/configs/imx8mm_venice.h | 1 - include/configs/imx8mn_beacon.h | 1 - include/configs/imx8mn_var_som.h | 5 ----- include/configs/imx8mn_venice.h | 1 - include/configs/imx8mp_evk.h | 1 - include/configs/imx8mp_rsb3720.h | 1 - include/configs/imx8mq_evk.h | 1 - include/configs/imx8mq_phanbell.h | 1 - include/configs/imx8qm_mek.h | 3 --- include/configs/imx8qm_rom7720.h | 3 --- include/configs/imx8qxp_mek.h | 3 --- include/configs/imx8ulp_evk.h | 1 - include/configs/kontron_pitx_imx8m.h | 1 - include/configs/liteboard.h | 1 - include/configs/m53menlo.h | 1 - include/configs/mx6sxsabreauto.h | 2 -- include/configs/mx6sxsabresd.h | 2 -- include/configs/mx6ul_14x14_evk.h | 2 -- include/configs/mxs.h | 7 ------- include/configs/nitrogen6x.h | 1 - include/configs/npi_imx6ull.h | 1 - include/configs/o4-imx6ull-nano.h | 4 ---- include/configs/pico-imx6.h | 1 - include/configs/pico-imx6ul.h | 1 - include/configs/pico-imx8mq.h | 1 - include/configs/somlabs_visionsom_6ull.h | 1 - include/configs/tqma6_mba6.h | 2 -- include/configs/tqma6_wru4.h | 1 - include/configs/verdin-imx8mm.h | 1 - include/configs/verdin-imx8mp.h | 1 - include/configs/vf610twr.h | 1 - include/configs/vining_2000.h | 2 -- include/configs/xpress.h | 1 - 47 files changed, 3 insertions(+), 84 deletions(-) (limited to 'drivers') diff --git a/doc/README.fec_mxc b/doc/README.fec_mxc index 9ca6ac2fb59..d17dfb676f7 100644 --- a/doc/README.fec_mxc +++ b/doc/README.fec_mxc @@ -7,11 +7,6 @@ CONFIG_FEC_MXC CONFIG_MII Must be defined if CONFIG_FEC_MXC is defined. -CONFIG_FEC_XCV_TYPE - Defaults to MII100 for 100 Base-tx. - RGMII selects 1000 Base-tx reduced pin count interface. - RMII selects 100 Base-tx reduced pin count interface. - CONFIG_FEC_MXC_SWAP_PACKET Forced on iff MX28. Swaps the bytes order of all words(4 byte units) in the packet. diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index a26927582d2..e8ebef09032 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -54,10 +54,6 @@ DECLARE_GLOBAL_DATA_PTR; #error "CONFIG_MII has to be defined!" #endif -#ifndef CONFIG_FEC_XCV_TYPE -#define CONFIG_FEC_XCV_TYPE MII100 -#endif - /* * The i.MX28 operates with packets in big endian. We need to swap them before * sending and after receiving. @@ -1269,9 +1265,9 @@ static int fecmxc_probe(struct udevice *dev) priv->xcv_type = RGMII; break; default: - priv->xcv_type = CONFIG_FEC_XCV_TYPE; - printf("Unsupported interface type %d defaulting to %d\n", - priv->interface, priv->xcv_type); + priv->xcv_type = MII100; + printf("Unsupported interface type %d defaulting to MII100\n", + priv->interface); break; } diff --git a/include/configs/apalis-imx8x.h b/include/configs/apalis-imx8x.h index f43e166c908..71a80f38bbb 100644 --- a/include/configs/apalis-imx8x.h +++ b/include/configs/apalis-imx8x.h @@ -122,7 +122,6 @@ #define CONFIG_FEC_ENET_DEV 0 #define IMX_FEC_BASE 0x5b040000 #define CONFIG_FEC_MXC_PHYADDR 0x4 -#define CONFIG_FEC_XCV_TYPE RGMII #define PHY_ANEG_TIMEOUT 20000 #endif /* __APALIS_IMX8X_H */ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 96792028e02..fcf364be8df 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -21,8 +21,6 @@ #define CONSOLE_DEV "ttymxc0" #endif -#define CONFIG_FEC_XCV_TYPE RGMII - /* Framebuffer */ #define CONFIG_SYS_LDB_CLOCK 28341000 diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 4f89f9d9ef9..92f69ba9b0f 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -87,7 +87,6 @@ BUR_COMMON_ENV \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Ethernet */ -#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_FIXED_SPEED _1000BASET /* USB Configs */ diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index c521dddab77..58d7a3a8ce2 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -32,9 +32,6 @@ #define CONFIG_FACTORYSET -/* ENET Config */ -#define CONFIG_FEC_XCV_TYPE RMII - /* ENET1 connects to base board and MUX with ESAI */ #define CONFIG_FEC_ENET_DEV 1 #define CONFIG_FEC_MXC_PHYADDR 0x0 diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index ce36b2e3eae..bd5c072382a 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -136,7 +136,6 @@ /* Networking */ #define CONFIG_FEC_MXC_PHYADDR -1 -#define CONFIG_FEC_XCV_TYPE RGMII #define FEC_QUIRK_ENET_MAC #endif /* __CGTQMX8_H */ diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 0b059d7ab87..8af80f58f8e 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -13,7 +13,6 @@ #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* Network */ -#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 0 /* ENET1 */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index e41c76bfb92..90720c2f9b5 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -147,7 +147,6 @@ /* Ethernet */ #define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_FEC_XCV_TYPE RGMII #define IMX_FEC_BASE ENET_BASE_ADDR /* USB */ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 804dfb44805..3d3fab517e3 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -32,7 +32,6 @@ /* FEC ethernet */ #define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 7 /* MMC Configs */ diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index e6fc65e0d41..65f8944ccaf 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -23,7 +23,6 @@ /* Ethernet Configs */ -#define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_FEC_MXC_PHYADDR 0 #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index c97223eb29e..cd1eafdd5c9 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -151,7 +151,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 0 #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 2c568a68549..e4805951fae 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -105,7 +105,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 /* FEC*/ -#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 0 #define FEC_QUIRK_ENET_MAC #define IMX_FEC_BASE 0x30BE0000 diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 4f5fe6a7875..32c937abb0e 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -83,7 +83,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 0 #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 374b476d12e..1ec27f40f2b 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -101,7 +101,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 /* FEC */ -#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 0 #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 227cfda3e6b..7fed9a38c1d 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -122,7 +122,6 @@ /* ENET Config */ #if defined(CONFIG_FEC_MXC) -#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 0 #define FEC_QUIRK_ENET_MAC #define IMX_FEC_BASE 0x30BE0000 diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index 1540e4b49ad..318289b76bc 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -32,11 +32,6 @@ #include -/* ENET */ -#if defined(CONFIG_FEC_MXC) -#define CONFIG_FEC_XCV_TYPE RGMII -#endif /* CONFIG_FEC_MXC */ - #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index 1476431943e..c01a590c8af 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -97,7 +97,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 /* FEC */ -#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 0 #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index f08193a7f35..fe07a3cde62 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -33,7 +33,6 @@ #endif #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 1 #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 287782b2462..62e06d23034 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -41,7 +41,6 @@ /* ENET Config */ /* ENET1 */ #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 4 #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 4140dd7a9d1..8fff3bf632e 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -38,7 +38,6 @@ /* ENET Config */ /* ENET1 */ #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 0 #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 9d56e33e841..6919f6d660e 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -32,7 +32,6 @@ /* ENET Config */ /* ENET1 */ #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 0 #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index c12f383655b..0fe38e61c4b 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -133,7 +133,4 @@ /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 8000000 /* 8MHz */ -/* Networking */ -#define CONFIG_FEC_XCV_TYPE RGMII - #endif /* __IMX8QM_MEK_H */ diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 5fcc96325ad..7532c6e7551 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -127,8 +127,5 @@ /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 8000000 /* 8MHz */ -/* Networking */ -#define CONFIG_FEC_XCV_TYPE RGMII - #include #endif /* __IMX8QM_ROM7720_H */ diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index b1c51e72bf6..beb35c93435 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -136,9 +136,6 @@ #define CONFIG_PCA953X #endif -/* Networking */ -#define CONFIG_FEC_XCV_TYPE RGMII - /* Misc configuration */ #define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index 07d8d65f716..ddb3d444f03 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -31,7 +31,6 @@ #if defined(CONFIG_FEC_MXC) #define PHY_ANEG_TIMEOUT 20000 -#define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_FEC_MXC_PHYADDR 1 #define IMX_FEC_BASE 0x29950000 diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index e2c14c7373d..2c0ad96e0d4 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -32,7 +32,6 @@ /* ENET1 Config */ #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 0 #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 8d062aa4638..d0960bcaf9a 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -115,7 +115,6 @@ #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x0 -#define CONFIG_FEC_XCV_TYPE RMII #endif #endif diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 9ec249722c9..dd803e7053c 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -72,7 +72,6 @@ #define IMX_FEC_BASE FEC_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x0 #define CONFIG_DISCOVER_PHY -#define CONFIG_FEC_XCV_TYPE RMII #endif #define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index c2cf1f34ce6..372cf8dd711 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -101,8 +101,6 @@ #define IMX_FEC_BASE ENET2_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x0 -#define CONFIG_FEC_XCV_TYPE RGMII - #ifdef CONFIG_CMD_USB #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 7ab641f7c07..a46f515f10d 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -129,8 +129,6 @@ #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x1 -#define CONFIG_FEC_XCV_TYPE RGMII - #ifdef CONFIG_CMD_USB #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index fdea1cbc282..4be5d7897d8 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -137,11 +137,9 @@ #if (CONFIG_FEC_ENET_DEV == 0) #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x2 -#define CONFIG_FEC_XCV_TYPE RMII #elif (CONFIG_FEC_ENET_DEV == 1) #define IMX_FEC_BASE ENET2_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x1 -#define CONFIG_FEC_XCV_TYPE RMII #endif #endif diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 7a513c1ba90..8dcc45c9e5d 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -94,13 +94,6 @@ #define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } /* Default baudrate can be overridden by board! */ -/* FEC Ethernet on SoC */ -#ifdef CONFIG_FEC_MXC -#ifndef CONFIG_FEC_XCV_TYPE -#define CONFIG_FEC_XCV_TYPE RMII -#endif -#endif - /* NAND */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index d082fbd824f..afa4ca5b5af 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -29,7 +29,6 @@ #endif #define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 6 /* USB Configs */ diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 31cf63d8647..1e40fad9644 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -48,7 +48,6 @@ #ifdef CONFIG_CMD_NET #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x1 -#define CONFIG_FEC_XCV_TYPE RMII #endif #define CONFIG_FEC_ENET_DEV 1 diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h index 72515a32e16..7777935ba6e 100644 --- a/include/configs/o4-imx6ull-nano.h +++ b/include/configs/o4-imx6ull-nano.h @@ -17,10 +17,6 @@ # define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* CONFIG_CMD_USB */ -#if IS_ENABLED(CONFIG_FEC_MXC) -# define CONFIG_FEC_XCV_TYPE RMII -#endif /* CONFIG_FEC_MXC */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "mmcdev=0\0" \ "mmcpart=2\0" \ diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 4f9a0f03010..63f6b149d01 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -130,7 +130,6 @@ /* Ethernet Configuration */ #define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 1 /* Framebuffer */ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index d87bcf45d6e..f63ebb48117 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -29,7 +29,6 @@ #define IMX_FEC_BASE ENET2_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x1 -#define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_MXC_UART_BASE UART6_BASE_ADDR diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 85f6129337d..26946cd65ac 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -32,7 +32,6 @@ /* ENET Config */ /* ENET1 */ #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 1 #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index a9e8c264e9d..9946fe92fb4 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -80,7 +80,6 @@ #ifdef CONFIG_CMD_NET #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x1 -#define CONFIG_FEC_XCV_TYPE RMII #endif #endif diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h index 4233ecd64eb..899c218727f 100644 --- a/include/configs/tqma6_mba6.h +++ b/include/configs/tqma6_mba6.h @@ -9,8 +9,6 @@ #ifndef __CONFIG_TQMA6_MBA6_H #define __CONFIG_TQMA6_MBA6_H -#define CONFIG_FEC_XCV_TYPE RGMII - #define CONFIG_FEC_MXC_PHYADDR 0x03 #define CONFIG_MXC_UART_BASE UART2_BASE diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 88a652e6d00..90db96599c1 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -7,7 +7,6 @@ #define __CONFIG_TQMA6_WRU4_H /* Ethernet */ -#define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_FEC_MXC_PHYADDR 0x01 /* UART */ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 4811e98810b..de84e3b6635 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -103,7 +103,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 /* ENET */ -#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 7 #define FEC_QUIRK_ENET_MAC #define IMX_FEC_BASE 0x30BE0000 diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 6bfc121d106..9a7dedf1ea5 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -35,7 +35,6 @@ /* ENET Config */ /* ENET1 */ #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 7 #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index d90c2fa0534..ebae8223fe2 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -24,7 +24,6 @@ #define CONFIG_SYS_FSL_ESDHC_NUM 1 #define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_FEC_MXC_PHYADDR 0 /* I2C Configs */ diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 521f3250575..e101739858f 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -47,8 +47,6 @@ #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x0 -#define CONFIG_FEC_XCV_TYPE RMII - #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 91f6d67d274..13cfa2cd4bd 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -45,7 +45,6 @@ #define CONFIG_FEC_ENET_DEV 0 #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x0 -#define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_UBOOT_SECTOR_START 0x2 #define CONFIG_UBOOT_SECTOR_COUNT 0x3fe -- cgit v1.3.1 From 7aa9dbd0abd6a223da41e3ad363f0ed28a6109ad Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 28 Feb 2022 15:13:47 -0700 Subject: sandbox: Open host file for read-only access if needed Some files cannot be written but read-only access is still useful for tests. Add a fallback to read-only access when needed. This is useful in CI when opening a large data file provided by docker, where read/write access would result in copying the file, thus needing a lot of extra disk space. Signed-off-by: Simon Glass --- drivers/block/sandbox.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c index 53925ce9b69..1388498a1d3 100644 --- a/drivers/block/sandbox.c +++ b/drivers/block/sandbox.c @@ -125,9 +125,14 @@ int host_dev_bind(int devnum, char *filename, bool removable) fd = os_open(filename, OS_O_RDWR); if (fd == -1) { - printf("Failed to access host backing file '%s'\n", filename); - ret = -ENOENT; - goto err; + printf("Failed to access host backing file '%s', trying read-only\n", + filename); + fd = os_open(filename, OS_O_RDONLY); + if (fd == -1) { + printf("- still failed\n"); + ret = -ENOENT; + goto err; + } } ret = blk_create_device(gd->dm_root, "sandbox_host_blk", str, IF_TYPE_HOST, devnum, 512, -- cgit v1.3.1 From 7c19e4cbfe5271bd6a3cf0bf14d10751b5798739 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 28 Feb 2022 15:13:48 -0700 Subject: sandbox: Slow down the LCD sync rate There is seldom a need to refresh at 100Hz and it uses a lot of CPU. Reduce the rate to 10Hz which seems to be adequate. Signed-off-by: Simon Glass --- drivers/video/video-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 7d499bcec51..5215114b2d8 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -204,7 +204,7 @@ int video_sync(struct udevice *vid, bool force) struct video_priv *priv = dev_get_uclass_priv(vid); static ulong last_sync; - if (force || get_timer(last_sync) > 10) { + if (force || get_timer(last_sync) > 100) { sandbox_sdl_sync(priv->fb); last_sync = get_timer(0); } -- cgit v1.3.1 From 03d14ccdf6c4ae56e3351ca828d9b1ac6467aea5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Mar 2022 08:38:22 -0400 Subject: Convert CONFIG_RMII to Kconfig This converts the following to Kconfig: CONFIG_RMII Cc: Ramon Fried Signed-off-by: Tom Rini --- configs/axm_defconfig | 1 + configs/corvus_defconfig | 1 + configs/devkit3250_defconfig | 1 + configs/ethernut5_defconfig | 1 + configs/gurnard_defconfig | 1 + configs/meesc_dataflash_defconfig | 1 + configs/meesc_defconfig | 1 + configs/smartweb_defconfig | 1 + configs/snapper9260_defconfig | 1 + configs/snapper9g20_defconfig | 1 + configs/taurus_defconfig | 1 + configs/usb_a9263_dataflash_defconfig | 1 + configs/vinco_defconfig | 1 + drivers/net/Kconfig | 5 +++++ include/configs/corvus.h | 3 --- include/configs/devkit3250.h | 1 - include/configs/ethernut5.h | 1 - include/configs/meesc.h | 3 --- include/configs/smartweb.h | 8 -------- include/configs/snapper9260.h | 1 - include/configs/snapper9g45.h | 1 - include/configs/taurus.h | 3 --- include/configs/usb_a9263.h | 3 --- include/configs/vinco.h | 1 - 24 files changed, 18 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/configs/axm_defconfig b/configs/axm_defconfig index 3373e6291ea..c4ef342fa18 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -83,6 +83,7 @@ CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_MACB=y +CONFIG_RMII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_SPECIFY_CONSOLE_INDEX=y diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index c7a59c75cc1..3dd55c08bb1 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -75,6 +75,7 @@ CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 CONFIG_MACB=y +CONFIG_RMII=y CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index 2a24e01b08c..df8d0d15704 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -70,6 +70,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ADDR=31 CONFIG_PHY_SMSC=y +CONFIG_RMII=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_CONS_INDEX=5 CONFIG_SYS_NS16550=y diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig index 339e8d147ac..4a52228b923 100644 --- a/configs/ethernut5_defconfig +++ b/configs/ethernut5_defconfig @@ -75,6 +75,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_DATAFLASH=y CONFIG_MACB=y +CONFIG_RMII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_RTC_PCF8563=y diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig index b90437f94c5..47678e6c512 100644 --- a/configs/gurnard_defconfig +++ b/configs/gurnard_defconfig @@ -49,6 +49,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ATMEL=y CONFIG_ATMEL_NAND_HWECC=y CONFIG_MACB=y +CONFIG_RMII=y CONFIG_ATMEL_USART=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig index 5858a99abd2..54bea29032b 100644 --- a/configs/meesc_dataflash_defconfig +++ b/configs/meesc_dataflash_defconfig @@ -42,6 +42,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_DATAFLASH=y CONFIG_MACB=y +CONFIG_RMII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig index 9141bdfc749..312c15f7deb 100644 --- a/configs/meesc_defconfig +++ b/configs/meesc_defconfig @@ -43,6 +43,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_DATAFLASH=y CONFIG_MACB=y +CONFIG_RMII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index ecd689f6bf4..6ff89889359 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -75,6 +75,7 @@ CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 CONFIG_MACB=y +CONFIG_RMII=y CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_GADGET=y diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig index 33b2f14e12f..76b51d9fd4b 100644 --- a/configs/snapper9260_defconfig +++ b/configs/snapper9260_defconfig @@ -50,4 +50,5 @@ CONFIG_MTD_RAW_NAND=y # CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_MACB=y +CONFIG_RMII=y CONFIG_ATMEL_USART=y diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig index eb345072f26..c6eca225e27 100644 --- a/configs/snapper9g20_defconfig +++ b/configs/snapper9g20_defconfig @@ -49,4 +49,5 @@ CONFIG_MTD_RAW_NAND=y # CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_MACB=y +CONFIG_RMII=y CONFIG_ATMEL_USART=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index e7b66177679..76f902b1fa5 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -89,6 +89,7 @@ CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_MACB=y +CONFIG_RMII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_SPECIFY_CONSOLE_INDEX=y diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig index e38313b9baf..b609bbbb3e5 100644 --- a/configs/usb_a9263_dataflash_defconfig +++ b/configs/usb_a9263_dataflash_defconfig @@ -51,6 +51,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_DATAFLASH=y CONFIG_MACB=y +CONFIG_RMII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig index 85e9f62227a..2eb22829eeb 100644 --- a/configs/vinco_defconfig +++ b/configs/vinco_defconfig @@ -45,6 +45,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_SMSC=y CONFIG_ETH_DESIGNWARE=y CONFIG_MACB=y +CONFIG_RMII=y CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 71e0cbafb41..d63c0a986a8 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -535,6 +535,11 @@ config MII help Enable support of the Media-Independent Interface (MII) +config RMII + bool "Enable RMII" + help + Enable support of the Reduced Media-Independent Interface (MII) + config PCNET bool "AMD PCnet series Ethernet controller driver" help diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 66eb8e9302b..18bb5547fa9 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -55,9 +55,6 @@ #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 #endif -/* Ethernet */ -#define CONFIG_RMII - /* DFU class support */ #define DFU_MANIFEST_POLL_TIMEOUT 25000 diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index ff5ce55a03f..84098e75301 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -32,7 +32,6 @@ /* * Ethernet */ -#define CONFIG_RMII #define CONFIG_LPC32XX_ETH /* diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 860709a2770..3231f3cc035 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -54,7 +54,6 @@ /* JFFS2 */ /* Ethernet */ -#define CONFIG_RMII #define CONFIG_PHY_ID 0 #define CONFIG_MACB_SEARCH_PHY diff --git a/include/configs/meesc.h b/include/configs/meesc.h index fcc103cd29d..fa4513b2b99 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -66,9 +66,6 @@ # define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) #endif -/* Ethernet */ -#define CONFIG_RMII - /* hw-controller addresses */ #define CONFIG_ET1100_BASE 0x70000000 diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 7b6395581bf..a0b353902e7 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -76,14 +76,6 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS -/* - * Ethernet configuration - * - */ -#define CONFIG_RMII /* use reduced MII inteface */ - -/* BOOTP and DHCP options */ - #if !defined(CONFIG_SPL_BUILD) /* USB configuration */ #define CONFIG_USB_ATMEL diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index ff670565ce0..2f0309f0ccd 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -38,7 +38,6 @@ #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 /* Ethernet */ -#define CONFIG_RMII #define CONFIG_TFTP_PORT /* USB */ diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index 26a42c9b2d0..72611fe8503 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -39,7 +39,6 @@ #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 /* Ethernet */ -#define CONFIG_RMII #define CONFIG_TFTP_PORT /* LCD */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 6fd60e5dde7..b0d06e7b552 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -63,9 +63,6 @@ #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 #endif -/* Ethernet */ -#define CONFIG_RMII - /* USB */ #if defined(CONFIG_BOARD_TAURUS) #define CONFIG_USB_ATMEL diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index f6a4a4cbe00..2b6078a1cc9 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -43,9 +43,6 @@ #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) #endif -/* Ethernet */ -#define CONFIG_RMII - /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_ATMEL diff --git a/include/configs/vinco.h b/include/configs/vinco.h index a6511b34f52..16c020982b3 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -49,7 +49,6 @@ /* USB device */ /* Ethernet Hardware */ -#define CONFIG_RMII #define CONFIG_MACB_SEARCH_PHY #ifdef CONFIG_SPI_BOOT -- cgit v1.3.1 From 6329dda175ef6f2c41991be3fdcfe0b5e091b573 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Mar 2022 08:38:24 -0400 Subject: Convert CONFIG_LPC32XX_ETH to Kconfig This converts the following to Kconfig: CONFIG_LPC32XX_ETH Cc: Ramon Fried Signed-off-by: Tom Rini --- drivers/net/Kconfig | 5 +++++ include/configs/devkit3250.h | 5 ----- include/configs/work_92105.h | 7 ------- 3 files changed, 5 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index d63c0a986a8..a6171a7c7ff 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -423,6 +423,11 @@ config KSZ9477 This driver implements a DSA switch driver for the KSZ9477 family of GbE switches using the I2C interface. +config LPC32XX_ETH + bool "LPC32xx Ethernet MAC interface driver" + depends on ARCH_LPC32XX + default y + config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on ARCH_KIRKWOOD || ARCH_ORION5X diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 84098e75301..bc5282a4893 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -29,11 +29,6 @@ * GPIO */ -/* - * Ethernet - */ -#define CONFIG_LPC32XX_ETH - /* * NOR Flash */ diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 373af03b8b5..33245375979 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -22,13 +22,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ - GENERATED_GBL_DATA_SIZE) -/* - * Ethernet Driver - */ - -#define CONFIG_LPC32XX_ETH -/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */ - #define CONFIG_RTC_DS1374 /* -- cgit v1.3.1 From 16199a8b961fab60587011e9da5a592b94d3eaf4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Mar 2022 08:38:26 -0400 Subject: Convert CONFIG_PHY_RESET_DELAY to Kconfig This converts the following to Kconfig: CONFIG_PHY_RESET_DELAY Cc: Ramon Fried Signed-off-by: Tom Rini --- README | 7 ------- arch/arm/include/asm/arch-bcmcygnus/configs.h | 3 --- common/miiphyutil.c | 2 +- configs/bcm968380gerg_ram_defconfig | 1 + configs/comtrend_ar5315u_ram_defconfig | 1 + configs/comtrend_ar5387un_ram_defconfig | 1 + configs/comtrend_ct5361_ram_defconfig | 1 + configs/comtrend_vr3032u_ram_defconfig | 1 + configs/comtrend_wap5813n_ram_defconfig | 1 + configs/huawei_hg556a_ram_defconfig | 1 + configs/netgear_cg3100d_ram_defconfig | 1 + configs/netgear_dgnd3700v2_ram_defconfig | 1 + configs/sagem_f@st1704_ram_defconfig | 1 + configs/sfr_nb4-ser_ram_defconfig | 1 + configs/stv0991_defconfig | 1 + drivers/net/phy/Kconfig | 8 ++++++++ drivers/net/phy/phy.c | 2 +- include/configs/bmips_common.h | 3 --- include/configs/stv0991.h | 3 --- 19 files changed, 22 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/README b/README index effaef5574c..0072e03b631 100644 --- a/README +++ b/README @@ -1075,13 +1075,6 @@ The following options need to be configured: The clock frequency of the MII bus - CONFIG_PHY_RESET_DELAY - - Some PHY like Intel LXT971A need extra delay after - reset before any MII register access is possible. - For such PHY, set this option to the usec delay - required. (minimum 300usec for LXT971A) - CONFIG_PHY_CMD_DELAY (ppc4xx) Some PHY like Intel LXT971A need extra delay after diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h index 27f30d1d2e2..327c0e06977 100644 --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h @@ -19,7 +19,4 @@ #define CONFIG_SYS_NS16550_CLK_DIV 54 #define CONFIG_SYS_NS16550_COM3 0x18023000 -/* Ethernet */ -#define CONFIG_PHY_RESET_DELAY 10000 /* PHY reset delay in us*/ - #endif /* __ARCH_CONFIGS_H */ diff --git a/common/miiphyutil.c b/common/miiphyutil.c index 7d4d15ed918..194c84e7e89 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -366,7 +366,7 @@ int miiphy_reset(const char *devname, unsigned char addr) debug("PHY reset failed\n"); return -1; } -#ifdef CONFIG_PHY_RESET_DELAY +#if CONFIG_PHY_RESET_DELAY > 0 udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */ #endif /* diff --git a/configs/bcm968380gerg_ram_defconfig b/configs/bcm968380gerg_ram_defconfig index 7eb23bdc62b..95cce92e926 100644 --- a/configs/bcm968380gerg_ram_defconfig +++ b/configs/bcm968380gerg_ram_defconfig @@ -49,6 +49,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_BRCMNAND=y CONFIG_NAND_BRCMNAND_6838=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_PHY=y CONFIG_BCM6368_USBH_PHY=y CONFIG_PINCTRL=y diff --git a/configs/comtrend_ar5315u_ram_defconfig b/configs/comtrend_ar5315u_ram_defconfig index 45e8b765837..9268aea02ab 100644 --- a/configs/comtrend_ar5315u_ram_defconfig +++ b/configs/comtrend_ar5315u_ram_defconfig @@ -50,6 +50,7 @@ CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_ETH=y CONFIG_BCM6368_ETH=y CONFIG_PHY=y diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig index 5a944483d06..9d2fc0cbf1c 100644 --- a/configs/comtrend_ar5387un_ram_defconfig +++ b/configs/comtrend_ar5387un_ram_defconfig @@ -50,6 +50,7 @@ CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_ETH=y CONFIG_BCM6368_ETH=y CONFIG_PHY=y diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig index 6290b2a7208..ddb12508bf8 100644 --- a/configs/comtrend_ct5361_ram_defconfig +++ b/configs/comtrend_ct5361_ram_defconfig @@ -51,6 +51,7 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_PHY_FIXED=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_ETH=y CONFIG_BCM6348_ETH=y CONFIG_PHY=y diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig index 35bc13964e7..b2973fa0f34 100644 --- a/configs/comtrend_vr3032u_ram_defconfig +++ b/configs/comtrend_vr3032u_ram_defconfig @@ -52,6 +52,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_BRCMNAND=y CONFIG_NAND_BRCMNAND_6368=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_ETH=y CONFIG_BCM6368_ETH=y CONFIG_PHY=y diff --git a/configs/comtrend_wap5813n_ram_defconfig b/configs/comtrend_wap5813n_ram_defconfig index a2e5f9648c6..5ad85b10f50 100644 --- a/configs/comtrend_wap5813n_ram_defconfig +++ b/configs/comtrend_wap5813n_ram_defconfig @@ -50,6 +50,7 @@ CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_BCM6368_ETH=y diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig index 977450e351e..261e1bf693d 100644 --- a/configs/huawei_hg556a_ram_defconfig +++ b/configs/huawei_hg556a_ram_defconfig @@ -51,6 +51,7 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_PHY_FIXED=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_ETH=y CONFIG_BCM6348_ETH=y CONFIG_PHY=y diff --git a/configs/netgear_cg3100d_ram_defconfig b/configs/netgear_cg3100d_ram_defconfig index b961b58ac39..869d4c8e4e3 100644 --- a/configs/netgear_cg3100d_ram_defconfig +++ b/configs/netgear_cg3100d_ram_defconfig @@ -45,6 +45,7 @@ CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_RESET=y CONFIG_RESET_BCM6345=y CONFIG_DM_SERIAL=y diff --git a/configs/netgear_dgnd3700v2_ram_defconfig b/configs/netgear_dgnd3700v2_ram_defconfig index c3e626c9c34..8649f0ecd9f 100644 --- a/configs/netgear_dgnd3700v2_ram_defconfig +++ b/configs/netgear_dgnd3700v2_ram_defconfig @@ -47,6 +47,7 @@ CONFIG_LED=y CONFIG_LED_BCM6328=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_BCM6368_ETH=y diff --git a/configs/sagem_f@st1704_ram_defconfig b/configs/sagem_f@st1704_ram_defconfig index ac906a9dcf8..9ac5dbaae14 100644 --- a/configs/sagem_f@st1704_ram_defconfig +++ b/configs/sagem_f@st1704_ram_defconfig @@ -49,6 +49,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_FIXED=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_ETH=y CONFIG_BCM6348_ETH=y CONFIG_DM_RESET=y diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig index 5caad90fe91..e97c1f06bd7 100644 --- a/configs/sfr_nb4-ser_ram_defconfig +++ b/configs/sfr_nb4-ser_ram_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_PHY_FIXED=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_ETH=y CONFIG_BCM6348_ETH=y CONFIG_PHY=y diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index fa1ae108385..7b40329405c 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -35,6 +35,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_PHY_RESET_DELAY=10000 CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_CADENCE_QSPI=y diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 74339a25ca5..eed6eb18669 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -330,3 +330,11 @@ config PHY_NCSI depends on DM_ETH endif #PHYLIB + +config PHY_RESET_DELAY + int "Extra delay after reset before MII register access" + default 0 + help + Some PHYs need extra delay after reset before any MII register access + is possible. For such PHY, set this option to the usec delay + required. diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index fffa10f68b3..92fff5b72c0 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -872,7 +872,7 @@ int phy_reset(struct phy_device *phydev) return -1; } -#ifdef CONFIG_PHY_RESET_DELAY +#if CONFIG_PHY_RESET_DELAY > 0 udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */ #endif /* diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h index 57de9960956..0c357dea9d3 100644 --- a/include/configs/bmips_common.h +++ b/include/configs/bmips_common.h @@ -8,9 +8,6 @@ #include -/* ETH */ -#define CONFIG_PHY_RESET_DELAY 20 - /* UART */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index dd942168763..feec8695f2e 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -29,9 +29,6 @@ #define CONFIG_DW_ALTDESCRIPTOR -/* Command support defines */ -#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ - /* Misc configuration */ /* -- cgit v1.3.1 From cc386f161c3bd63c8370444df49d9fc36b60e403 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Mar 2022 08:38:27 -0400 Subject: Convert CONFIG_MII_INIT to Kconfig This converts the following to Kconfig: CONFIG_MII_INIT Signed-off-by: Tom Rini --- cmd/Kconfig | 4 ++++ configs/M5208EVBE_defconfig | 1 + configs/M5235EVB_Flash32_defconfig | 1 + configs/M5235EVB_defconfig | 1 + configs/M5272C3_defconfig | 1 + configs/M5275EVB_defconfig | 1 + configs/M5282EVB_defconfig | 1 + configs/M53017EVB_defconfig | 1 + configs/M5329AFEE_defconfig | 1 + configs/M5329BFEE_defconfig | 1 + configs/M5373EVB_defconfig | 1 + configs/MCR3000_defconfig | 1 + configs/eb_cpu5282_defconfig | 1 + configs/eb_cpu5282_internal_defconfig | 1 + drivers/net/mcfmii.c | 4 +--- include/configs/M5208EVBE.h | 1 - include/configs/M5235EVB.h | 1 - include/configs/M5272C3.h | 1 - include/configs/M5275EVB.h | 1 - include/configs/M5282EVB.h | 1 - include/configs/M53017EVB.h | 1 - include/configs/M5329EVB.h | 1 - include/configs/M5373EVB.h | 1 - include/configs/MCR3000.h | 1 - include/configs/cobra5272.h | 1 - include/configs/eb_cpu5282.h | 1 - include/configs/stmark2.h | 1 - scripts/config_whitelist.txt | 1 - 28 files changed, 18 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/cmd/Kconfig b/cmd/Kconfig index 564daa7bbc8..25c9fde4a7b 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1658,6 +1658,10 @@ config CMD_MII to management parameters and services. The interface is referred to as the MII management interface. +config MII_INIT + bool "Call mii_init() in the mii command" + depends on CMD_MII && (MPC8XX_FEC || FSLDMAFE || MCFFEC) + config CMD_MDIO bool "mdio" depends on PHYLIB diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig index 62b284b97ba..6d533d6bee8 100644 --- a/configs/M5208EVBE_defconfig +++ b/configs/M5208EVBE_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_PROMPT="-> " CONFIG_CMD_IMLS=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y +CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_FLASH=y diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig index a3762bb3d76..7552741395a 100644 --- a/configs/M5235EVB_Flash32_defconfig +++ b/configs/M5235EVB_Flash32_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_PCI=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_MII=y +CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_FLASH=y diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig index d4f32e45156..1bdb63ad1c6 100644 --- a/configs/M5235EVB_defconfig +++ b/configs/M5235EVB_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_PCI=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_MII=y +CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_FLASH=y diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig index c30b9498728..f0a6aac7612 100644 --- a/configs/M5272C3_defconfig +++ b/configs/M5272C3_defconfig @@ -17,6 +17,7 @@ CONFIG_CMD_IMLS=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_MII=y +CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_ENV_ADDR=0xFFE04000 diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig index 53ff8ee4aec..809bda0c068 100644 --- a/configs/M5275EVB_defconfig +++ b/configs/M5275EVB_defconfig @@ -21,6 +21,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_MII=y +CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_ENV_ADDR=0xFFE04000 diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig index 84363fbd924..69db87c0da2 100644 --- a/configs/M5282EVB_defconfig +++ b/configs/M5282EVB_defconfig @@ -17,6 +17,7 @@ CONFIG_CMD_IMLS=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_MII=y +CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_ENV_ADDR=0xFFE04000 diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig index b43478731c1..8283b52e626 100644 --- a/configs/M53017EVB_defconfig +++ b/configs/M53017EVB_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_PROMPT="-> " CONFIG_CMD_IMLS=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y +CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig index b8900f295f4..1092a1de51e 100644 --- a/configs/M5329AFEE_defconfig +++ b/configs/M5329AFEE_defconfig @@ -17,6 +17,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y +CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig index 47e6cb0ca2e..66347d5f096 100644 --- a/configs/M5329BFEE_defconfig +++ b/configs/M5329BFEE_defconfig @@ -17,6 +17,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y +CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig index c59ba94f2c2..38d20023d55 100644 --- a/configs/M5373EVB_defconfig +++ b/configs/M5373EVB_defconfig @@ -17,6 +17,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y +CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig index 04fe7565133..f174865806c 100644 --- a/configs/MCR3000_defconfig +++ b/configs/MCR3000_defconfig @@ -42,6 +42,7 @@ CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y +CONFIG_MII_INIT=y CONFIG_CMD_PING=y # CONFIG_CMD_SLEEP is not set CONFIG_OF_CONTROL=y diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig index a1aee405e97..ae1329c78a0 100644 --- a/configs/eb_cpu5282_defconfig +++ b/configs/eb_cpu5282_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_MII=y +CONFIG_MII_INIT=y CONFIG_CMD_DATE=y CONFIG_ENV_ADDR=0xFF040000 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig index 4adc0569762..02a9bb4646e 100644 --- a/configs/eb_cpu5282_internal_defconfig +++ b/configs/eb_cpu5282_internal_defconfig @@ -22,6 +22,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_MII=y +CONFIG_MII_INIT=y CONFIG_CMD_DATE=y CONFIG_ENV_ADDR=0xFF040000 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c index ca06b35316d..e2c8f41876e 100644 --- a/drivers/net/mcfmii.c +++ b/drivers/net/mcfmii.c @@ -200,9 +200,7 @@ int mii_discover_phy(fec_info_t *info) } #endif /* CONFIG_SYS_DISCOVER_PHY */ -void mii_init(void) __attribute__((weak,alias("__mii_init"))); - -void __mii_init(void) +__weak void mii_init(void) { #ifdef CONFIG_DM_ETH struct udevice *dev; diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index e30f1ebc35c..e73c656c384 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -18,7 +18,6 @@ #define CONFIG_WATCHDOG_TIMEOUT 5000 #ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ # ifndef CONFIG_SYS_DISCOVER_PHY diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index bc0e00cadd9..bbe12d10db6 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -23,7 +23,6 @@ #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ #ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ # ifndef CONFIG_SYS_DISCOVER_PHY diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index dec1e41936d..c4ee8c933d9 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -33,7 +33,6 @@ env/embedded.o(.text); #ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ # ifndef CONFIG_SYS_DISCOVER_PHY diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index dab512c70f0..5db85ad1842 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -36,7 +36,6 @@ /* Available command configuration */ #ifdef CONFIG_MCFFEC -#define CONFIG_MII_INIT 1 #define CONFIG_SYS_DISCOVER_PHY /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ #ifndef CONFIG_SYS_DISCOVER_PHY diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 974cfc343d4..cc64893b9af 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -31,7 +31,6 @@ env/embedded.o(.text*); #ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ # ifndef CONFIG_SYS_DISCOVER_PHY diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 80ca016d2be..431fa7406c6 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -25,7 +25,6 @@ #define CONFIG_SYS_UNIFY_CACHE #ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_TX_ETH_BUFFER 8 # define CONFIG_SYS_FEC_BUF_USE_SRAM diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index e4b887f02e2..d155f2cba04 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -25,7 +25,6 @@ #define CONFIG_SYS_UNIFY_CACHE #ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ # ifndef CONFIG_SYS_DISCOVER_PHY diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 9ad09e827e9..b0b0e2e13bf 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -27,7 +27,6 @@ #define CONFIG_SYS_UNIFY_CACHE #ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ # ifndef CONFIG_SYS_DISCOVER_PHY diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index 4a26ae8f7f1..e26b70a0823 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -88,7 +88,6 @@ /* Ethernet configuration part */ #define CONFIG_SYS_DISCOVER_PHY 1 -#define CONFIG_MII_INIT 1 /* NAND configuration part */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 607e76c349e..577936b5af9 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -89,7 +89,6 @@ env/embedded.o(.text); #ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ # ifndef CONFIG_SYS_DISCOVER_PHY diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 99d8e9e4e67..4d88657ca61 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -52,7 +52,6 @@ *----------------------------------------------------------------------*/ #ifdef CONFIG_MCFFEC -#define CONFIG_MII_INIT 1 #define CONFIG_SYS_DISCOVER_PHY #define CONFIG_OVERWRITE_ETHADDR_ONCE #endif diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index 9bfb8ca9b74..781dba542bd 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -132,7 +132,6 @@ CONFIG_SYS_INIT_RAM_SIZE - 12) #ifdef CONFIG_MCFFEC -#define CONFIG_MII_INIT 1 #define CONFIG_SYS_DISCOVER_PHY /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ #ifndef CONFIG_SYS_DISCOVER_PHY diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 8cbab7e20e8..bb8d310b79d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -499,7 +499,6 @@ CONFIG_MEM_INIT_VALUE CONFIG_MEM_REMAP CONFIG_MFG_ENV_SETTINGS CONFIG_MII_DEFAULT_TSEC -CONFIG_MII_INIT CONFIG_MISC_COMMON CONFIG_MIU_2BIT_21_7_INTERLEAVED CONFIG_MIU_2BIT_INTERLEAVED -- cgit v1.3.1 From 286c4531ad4bdc75ea0420201f388e9fb21076ef Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Mar 2022 08:38:28 -0400 Subject: Convert CONFIG_ATMEL_LCD et al to Kconfig This converts the following to Kconfig: CONFIG_ATMEL_LCD CONFIG_ATMEL_LCD_BGR555 CONFIG_ATMEL_LCD_RGB565 CONFIG_GURNARD_SPLASH Signed-off-by: Tom Rini --- README | 4 ---- board/bluewater/gurnard/Kconfig | 3 +++ configs/at91sam9261ek_dataflash_cs0_defconfig | 1 + configs/at91sam9261ek_dataflash_cs3_defconfig | 1 + configs/at91sam9261ek_nandflash_defconfig | 1 + configs/at91sam9263ek_dataflash_cs0_defconfig | 1 + configs/at91sam9263ek_dataflash_defconfig | 1 + configs/at91sam9263ek_nandflash_defconfig | 1 + configs/at91sam9263ek_norflash_boot_defconfig | 1 + configs/at91sam9263ek_norflash_defconfig | 1 + configs/gurnard_defconfig | 2 ++ configs/pm9261_defconfig | 2 ++ configs/pm9263_defconfig | 2 ++ drivers/video/Kconfig | 9 +++++++++ include/configs/at91sam9261ek.h | 4 ---- include/configs/at91sam9263ek.h | 2 -- include/configs/at91sam9m10g45ek.h | 2 -- include/configs/at91sam9n12ek.h | 1 - include/configs/at91sam9rlek.h | 2 -- include/configs/pm9261.h | 2 -- include/configs/pm9263.h | 2 -- include/configs/snapper9g45.h | 4 ---- 22 files changed, 26 insertions(+), 23 deletions(-) (limited to 'drivers') diff --git a/README b/README index 0072e03b631..805c8f0d048 100644 --- a/README +++ b/README @@ -994,10 +994,6 @@ The following options need to be configured: display); also select one of the supported displays by defining one of these: - CONFIG_ATMEL_LCD: - - HITACHI TX09D70VM1CCA, 3.5", 240x320. - CONFIG_NEC_NL6448AC33: NEC NL6448AC33-18. Active, color, single scan. diff --git a/board/bluewater/gurnard/Kconfig b/board/bluewater/gurnard/Kconfig index e2cd9f00df8..41ecbf7e22f 100644 --- a/board/bluewater/gurnard/Kconfig +++ b/board/bluewater/gurnard/Kconfig @@ -1,5 +1,8 @@ if TARGET_GURNARD +config GURNARD_SPLASH + def_bool y + config SYS_BOARD default "gurnard" diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig index 3b30a024294..5788b9d935f 100644 --- a/configs/at91sam9261ek_dataflash_cs0_defconfig +++ b/configs/at91sam9261ek_dataflash_cs0_defconfig @@ -64,3 +64,4 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig index 776130ed617..69d7931763f 100644 --- a/configs/at91sam9261ek_dataflash_cs3_defconfig +++ b/configs/at91sam9261ek_dataflash_cs3_defconfig @@ -64,3 +64,4 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig index b80d5a6a5f6..32945796300 100644 --- a/configs/at91sam9261ek_nandflash_defconfig +++ b/configs/at91sam9261ek_nandflash_defconfig @@ -62,3 +62,4 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig index 9de5028afa8..090ee405983 100644 --- a/configs/at91sam9263ek_dataflash_cs0_defconfig +++ b/configs/at91sam9263ek_dataflash_cs0_defconfig @@ -68,3 +68,4 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig index 9de5028afa8..090ee405983 100644 --- a/configs/at91sam9263ek_dataflash_defconfig +++ b/configs/at91sam9263ek_dataflash_defconfig @@ -68,3 +68,4 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig index ed12a9954fd..82d6ecdbc50 100644 --- a/configs/at91sam9263ek_nandflash_defconfig +++ b/configs/at91sam9263ek_nandflash_defconfig @@ -66,3 +66,4 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig index 34140444ca5..0e96b3a9c13 100644 --- a/configs/at91sam9263ek_norflash_boot_defconfig +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -66,3 +66,4 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig index aab31afc52e..20a105085ce 100644 --- a/configs/at91sam9263ek_norflash_defconfig +++ b/configs/at91sam9263ek_norflash_defconfig @@ -67,3 +67,4 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig index fc6c2b96b7b..20be0e3c29d 100644 --- a/configs/gurnard_defconfig +++ b/configs/gurnard_defconfig @@ -59,4 +59,6 @@ CONFIG_USB_EHCI_HCD=y CONFIG_DM_VIDEO=y # CONFIG_VIDEO_LOGO is not set # CONFIG_VIDEO_BPP32 is not set +CONFIG_ATMEL_LCD=y +CONFIG_LCD=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig index 7a640ff35ec..bda991795e2 100644 --- a/configs/pm9261_defconfig +++ b/configs/pm9261_defconfig @@ -60,5 +60,7 @@ CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP32 is not set +CONFIG_ATMEL_LCD=y +CONFIG_ATMEL_LCD_BGR555=y CONFIG_LCD=y CONFIG_REGEX=y diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig index 3c5f0b73abf..c9a8552266f 100644 --- a/configs/pm9263_defconfig +++ b/configs/pm9263_defconfig @@ -64,5 +64,7 @@ CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP32 is not set +CONFIG_ATMEL_LCD=y +CONFIG_ATMEL_LCD_BGR555=y CONFIG_LCD=y CONFIG_JFFS2_NAND=y diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 646fec70262..82d4569eab7 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -421,6 +421,15 @@ config VIDEO_LCD_ANX9804 from a parallel LCD interface and translate it on the fy into a DP interface for driving eDP TFT displays. It uses I2C for configuration. +config ATMEL_LCD + bool "Atmel LCD panel support" + depends on LCD && ARCH_AT91 + +config ATMEL_LCD_BGR555 + bool "Display in BGR555 mode" + help + Use the BGR555 output mode. Otherwise RGB565 is used. + config VIDEO_LCD_ORISETECH_OTM8009A bool "OTM8009A DSI LCD panel support" depends on DM_VIDEO diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 0b6706b95d9..dcad025541f 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -26,10 +26,6 @@ #undef LCD_TEST_PATTERN #define CONFIG_LCD_INFO #define CONFIG_LCD_INFO_BELOW_LOGO -#define CONFIG_ATMEL_LCD -#ifdef CONFIG_AT91SAM9261EK -#define CONFIG_ATMEL_LCD_BGR555 -#endif /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE 0x20000000 diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index c48810d8125..38ca1f80237 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -37,8 +37,6 @@ #undef LCD_TEST_PATTERN #define CONFIG_LCD_INFO 1 #define CONFIG_LCD_INFO_BELOW_LOGO 1 -#define CONFIG_ATMEL_LCD 1 -#define CONFIG_ATMEL_LCD_BGR555 1 /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 7e8e35b7aa6..ffa090ac123 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -22,8 +22,6 @@ #undef LCD_TEST_PATTERN #define CONFIG_LCD_INFO #define CONFIG_LCD_INFO_BELOW_LOGO -#define CONFIG_ATMEL_LCD -#define CONFIG_ATMEL_LCD_RGB565 /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE 0x70000000 diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 1771defa164..f02239c2505 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -21,7 +21,6 @@ #define CONFIG_LCD_LOGO #define CONFIG_LCD_INFO #define CONFIG_LCD_INFO_BELOW_LOGO -#define CONFIG_ATMEL_LCD_RGB565 #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 89cfcbd9517..369b981e3ee 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -26,8 +26,6 @@ #undef LCD_TEST_PATTERN #define CONFIG_LCD_INFO 1 #define CONFIG_LCD_INFO_BELOW_LOGO 1 -#define CONFIG_ATMEL_LCD 1 -#define CONFIG_ATMEL_LCD_RGB565 1 /* Let board_init_f handle the framebuffer allocation */ #undef CONFIG_FB_ADDR diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 3960a5cf96a..fb801b3d241 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -134,8 +134,6 @@ #undef LCD_TEST_PATTERN #define CONFIG_LCD_INFO 1 #define CONFIG_LCD_INFO_BELOW_LOGO 1 -#define CONFIG_ATMEL_LCD 1 -#define CONFIG_ATMEL_LCD_BGR555 1 /* SDRAM */ #define PHYS_SDRAM 0x20000000 diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 8ee8bbb2192..52cc0886a65 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -145,8 +145,6 @@ #undef LCD_TEST_PATTERN #define CONFIG_LCD_INFO 1 #define CONFIG_LCD_INFO_BELOW_LOGO 1 -#define CONFIG_ATMEL_LCD 1 -#define CONFIG_ATMEL_LCD_BGR555 1 #define CONFIG_LCD_IN_PSRAM 1 diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index 9e78fd219cc..0e3567f535b 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -38,10 +38,6 @@ #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 -/* LCD */ -#define CONFIG_ATMEL_LCD -#define CONFIG_GURNARD_SPLASH - /* UARTs/Serial console */ /* Boot options */ -- cgit v1.3.1 From 3e2ea3278efba6189dd9644438c64de4017fa027 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Mar 2022 08:38:29 -0400 Subject: Convert CONFIG_LCD_INFO et al to Kconfig This converts the following to Kconfig: CONFIG_LCD_INFO CONFIG_LCD_LOGO CONFIG_LCD_INFO_BELOW_LOGO CONFIG_LCD_IN_PSRAM Cc: Anatolij Gustschin Signed-off-by: Tom Rini --- board/ronetix/pm9263/Kconfig | 3 +++ configs/pm9261_defconfig | 2 ++ configs/pm9263_defconfig | 2 ++ drivers/video/Kconfig | 12 ++++++++++++ include/configs/at91sam9261ek.h | 3 --- include/configs/at91sam9263ek.h | 3 --- include/configs/at91sam9m10g45ek.h | 3 --- include/configs/at91sam9n12ek.h | 3 --- include/configs/at91sam9rlek.h | 3 --- include/configs/colibri_pxa270.h | 1 - include/configs/colibri_t20.h | 3 --- include/configs/pm9261.h | 3 --- include/configs/pm9263.h | 5 ----- 13 files changed, 19 insertions(+), 27 deletions(-) (limited to 'drivers') diff --git a/board/ronetix/pm9263/Kconfig b/board/ronetix/pm9263/Kconfig index 5b47d348450..d6b8cacef55 100644 --- a/board/ronetix/pm9263/Kconfig +++ b/board/ronetix/pm9263/Kconfig @@ -1,5 +1,8 @@ if TARGET_PM9263 +config LCD_IN_PSRAM + def_bool y + config SYS_BOARD default "pm9263" diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig index bda991795e2..8e5ebaa50b3 100644 --- a/configs/pm9261_defconfig +++ b/configs/pm9261_defconfig @@ -63,4 +63,6 @@ CONFIG_DM_VIDEO=y CONFIG_ATMEL_LCD=y CONFIG_ATMEL_LCD_BGR555=y CONFIG_LCD=y +CONFIG_LCD_INFO=y +CONFIG_LCD_LOGO=y CONFIG_REGEX=y diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig index c9a8552266f..2f8380d10a1 100644 --- a/configs/pm9263_defconfig +++ b/configs/pm9263_defconfig @@ -67,4 +67,6 @@ CONFIG_DM_VIDEO=y CONFIG_ATMEL_LCD=y CONFIG_ATMEL_LCD_BGR555=y CONFIG_LCD=y +CONFIG_LCD_INFO=y +CONFIG_LCD_LOGO=y CONFIG_JFFS2_NAND=y diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 82d4569eab7..1bf7f4a8084 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -828,6 +828,18 @@ config LCD CONFIG option. See the README for details. Drives which have been converted to driver model will instead used CONFIG_DM_VIDEO. +config LCD_INFO + bool "Show LCD info on-screen" + depends on LCD + +config LCD_LOGO + bool "Show a logo on screen" + depends on LCD + +config LCD_INFO_BELOW_LOGO + bool "Show LCD info below the on-screen logo" + depends on LCD_INFO && LCD_LOGO + config VIDEO_DW_HDMI bool help diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index dcad025541f..4f43736fc8b 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -22,10 +22,7 @@ /* LCD */ #define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO #undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO -#define CONFIG_LCD_INFO_BELOW_LOGO /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE 0x20000000 diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 38ca1f80237..b5ac6a48a8f 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -33,10 +33,7 @@ /* LCD */ #define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO 1 #undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO 1 -#define CONFIG_LCD_INFO_BELOW_LOGO 1 /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index ffa090ac123..f24e7d65313 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -18,10 +18,7 @@ /* LCD */ #define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO #undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO -#define CONFIG_LCD_INFO_BELOW_LOGO /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE 0x70000000 diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index f02239c2505..cd7c271cdc7 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -18,9 +18,6 @@ /* LCD */ #define LCD_BPP LCD_COLOR16 #define LCD_OUTPUT_BPP 24 -#define CONFIG_LCD_LOGO -#define CONFIG_LCD_INFO -#define CONFIG_LCD_INFO_BELOW_LOGO #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 369b981e3ee..822df8eb89f 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -22,10 +22,7 @@ /* LCD */ #define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO 1 #undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO 1 -#define CONFIG_LCD_INFO_BELOW_LOGO 1 /* Let board_init_f handle the framebuffer allocation */ #undef CONFIG_FB_ADDR diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index b34a5c9f242..17ff703d74b 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -38,7 +38,6 @@ #ifdef CONFIG_LCD #define CONFIG_PXA_LCD #define CONFIG_PXA_VGA -#define CONFIG_LCD_LOGO #endif /* diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index c377187b803..c45016a8358 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -15,9 +15,6 @@ #define CONFIG_TEGRA_UARTA_SDIO1 #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -/* LCD support */ -#define CONFIG_LCD_LOGO - /* NAND support */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index fb801b3d241..056d87488c0 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -130,10 +130,7 @@ /* LCD */ #define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO 1 #undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO 1 -#define CONFIG_LCD_INFO_BELOW_LOGO 1 /* SDRAM */ #define PHYS_SDRAM 0x20000000 diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 52cc0886a65..7b32e1b75bc 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -141,12 +141,7 @@ */ /* LCD */ #define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO 1 #undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO 1 -#define CONFIG_LCD_INFO_BELOW_LOGO 1 - -#define CONFIG_LCD_IN_PSRAM 1 /* SDRAM */ #define PHYS_SDRAM 0x20000000 -- cgit v1.3.1 From d7b904092d8066476975521dbf6f4ab05cd8d766 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Fri, 18 Feb 2022 13:18:40 +0100 Subject: pci: Add defines for normal and subtractive PCI bridges MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add following two new PCI class codes defines into pci_ids.h include file: PCI_CLASS_BRIDGE_PCI_NORMAL PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE And use these defines in all U-Boot code for describing PCI class codes for normal and subtractive PCI bridges. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- board/armltd/vexpress64/pcie.c | 2 +- drivers/pci/pci-aardvark.c | 2 +- drivers/pci/pci-rcar-gen3.c | 2 +- drivers/pci/pci_mvebu.c | 2 +- drivers/pci/pci_tegra.c | 4 ++-- drivers/pci/pcie_dw_mvebu.c | 4 ++-- drivers/pci/pcie_fsl.c | 2 +- drivers/pci/pcie_imx.c | 4 ++-- drivers/pci/pcie_iproc.c | 2 +- drivers/pci/pcie_rockchip.c | 2 +- include/pci_ids.h | 2 ++ 11 files changed, 15 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c index 1e74158630b..e553da86e0e 100644 --- a/board/armltd/vexpress64/pcie.c +++ b/board/armltd/vexpress64/pcie.c @@ -150,7 +150,7 @@ static void xr3pci_init(void) /* allow ECRC */ writel(0x6006, XR3_CONFIG_BASE + XR3PCI_PEX_SPC2); /* setup the correct class code for the host bridge */ - writel(PCI_CLASS_BRIDGE_PCI << 16, XR3_CONFIG_BASE + XR3PCI_BRIDGE_PCI_IDS); + writel(PCI_CLASS_BRIDGE_PCI_NORMAL << 8, XR3_CONFIG_BASE + XR3PCI_BRIDGE_PCI_IDS); /* reset phy and root complex */ writel(JUNO_RESET_CTRL_PHY | JUNO_RESET_CTRL_RC, diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 4f7e61ecf16..b0fc9caabbe 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -800,7 +800,7 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie) */ reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION); reg &= ~0xffffff00; - reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8; + reg |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8; advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION); /* Enable generation and checking of ECRC on PCIe Root Port */ diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index 34a561ef8b4..49029238d35 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -289,7 +289,7 @@ static int rcar_gen3_pcie_hw_init(struct udevice *dev) * class to match. Hardware takes care of propagating the IDSETR * settings, so there is no need to bother with a quirk. */ - writel(PCI_CLASS_BRIDGE_PCI << 16, priv->regs + IDSETR1); + writel(PCI_CLASS_BRIDGE_PCI_NORMAL << 8, priv->regs + IDSETR1); /* * Setup Secondary Bus Number & Subordinate Bus Number, even though diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index f07669374d7..d80f87e0cfc 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -440,7 +440,7 @@ static int mvebu_pcie_probe(struct udevice *dev) */ reg = readl(pcie->base + MVPCIE_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION); reg &= ~0xffffff00; - reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8; + reg |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8; writel(reg, pcie->base + MVPCIE_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION); /* diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index fc05ee00f1f..f8d66c0e1c6 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -325,8 +325,8 @@ static int pci_tegra_read_config(const struct udevice *bus, pci_dev_t bdf, /* fixup root port class */ if (PCI_BUS(bdf) == 0) { if ((offset & ~3) == PCI_CLASS_REVISION) { - value &= ~0x00ff0000; - value |= PCI_CLASS_BRIDGE_PCI << 16; + value &= ~0x00ffff00; + value |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8; } } #endif diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index 0490fd33770..99891dce61d 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -539,9 +539,9 @@ static int pcie_dw_mvebu_probe(struct udevice *dev) PCIE_ATU_TYPE_MEM, pcie->mem.phys_start, pcie->mem.bus_start, pcie->mem.size); - /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */ + /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI_NORMAL */ clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION, - 0xffff << 16, PCI_CLASS_BRIDGE_PCI << 16); + 0xffffff << 8, PCI_CLASS_BRIDGE_PCI_NORMAL << 8); pcie_dw_set_host_bars(pcie->ctrl_base); diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index cc6efdd5b46..f5ba34970f1 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -532,7 +532,7 @@ static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie) fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val); val &= 0xff; - val |= PCI_CLASS_BRIDGE_PCI << 16; + val |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8; fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val); if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 756166fd3ea..2cec3900e9a 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -300,9 +300,9 @@ static int imx_pcie_regions_setup(struct imx_pcie_priv *priv) setbits_le32(priv->dbi_base + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */ + /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI_NORMAL */ setbits_le32(priv->dbi_base + PCI_CLASS_REVISION, - PCI_CLASS_BRIDGE_PCI << 16); + PCI_CLASS_BRIDGE_PCI_NORMAL << 8); /* Region #0 is used for Outbound CFG space access. */ writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT); diff --git a/drivers/pci/pcie_iproc.c b/drivers/pci/pcie_iproc.c index 85dfab5c720..d6d3a9e2025 100644 --- a/drivers/pci/pcie_iproc.c +++ b/drivers/pci/pcie_iproc.c @@ -1123,7 +1123,7 @@ static int iproc_pcie_check_link(struct iproc_pcie *pcie) PCI_BRIDGE_CTRL_REG_OFFSET, 4, &class); class &= ~PCI_BRIDGE_CTRL_REG_CLASS_MASK; - class |= (PCI_CLASS_BRIDGE_PCI << 8); + class |= PCI_CLASS_BRIDGE_PCI_NORMAL; iproc_pci_raw_config_write32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, 4, class); diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c index 67039d2a29f..72b41398f27 100644 --- a/drivers/pci/pcie_rockchip.c +++ b/drivers/pci/pcie_rockchip.c @@ -351,7 +351,7 @@ static int rockchip_pcie_init_port(struct udevice *dev) /* Initialize Root Complex registers. */ writel(PCIE_LM_VENDOR_ROCKCHIP, priv->apb_base + PCIE_LM_VENDOR_ID); - writel(PCI_CLASS_BRIDGE_PCI << 16, + writel(PCI_CLASS_BRIDGE_PCI_NORMAL << 8, priv->apb_base + PCIE_RC_BASE + PCI_CLASS_REVISION); writel(PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS, priv->apb_base + PCIE_LM_RCBAR); diff --git a/include/pci_ids.h b/include/pci_ids.h index 3c5434c0eda..88b0a640458 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -55,6 +55,8 @@ #define PCI_CLASS_BRIDGE_EISA 0x0602 #define PCI_CLASS_BRIDGE_MC 0x0603 #define PCI_CLASS_BRIDGE_PCI 0x0604 +#define PCI_CLASS_BRIDGE_PCI_NORMAL 0x060400 +#define PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE 0x060401 #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 #define PCI_CLASS_BRIDGE_NUBUS 0x0606 #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 -- cgit v1.3.1 From fae101d6e8b247026145ecdc979133849c66e4e4 Mon Sep 17 00:00:00 2001 From: Billy Tsai Date: Tue, 8 Mar 2022 11:04:05 +0800 Subject: pwm: Add Aspeed ast2600 PWM support This patch add the support of PWM controller which can be found at aspeed ast2600 soc. The pwm supoorts up to 16 channels and it's part function of multi-function device "pwm-tach controller". Signed-off-by: Billy Tsai Reviewed-by: Simon Glass Reviewed-by: Chia-Wei Wang --- drivers/pwm/Kconfig | 8 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-aspeed.c | 251 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 260 insertions(+) create mode 100644 drivers/pwm/pwm-aspeed.c (limited to 'drivers') diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 669d3fa4fc5..6be612d58a9 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -9,6 +9,14 @@ config DM_PWM frequency/period can be controlled along with the proportion of that time that the signal is high. +config PWM_ASPEED + bool "Enable support for the Aspeed PWM" + depends on DM_PWM + help + This PWM is found on Ast2600 SoCs. It supports a programmable period + and duty cycle. It provides 16 channels which can be independently + programmed. + config PWM_AT91 bool "Enable support for PWM found on AT91 SoC's" depends on DM_PWM && ARCH_AT91 diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 55f2bc081d2..5d31812d52a 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_DM_PWM) += pwm-uclass.o +obj-$(CONFIG_PWM_ASPEED) += pwm-aspeed.o obj-$(CONFIG_PWM_AT91) += pwm-at91.o obj-$(CONFIG_PWM_CROS_EC) += cros_ec_pwm.o obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o diff --git a/drivers/pwm/pwm-aspeed.c b/drivers/pwm/pwm-aspeed.c new file mode 100644 index 00000000000..ba98641c866 --- /dev/null +++ b/drivers/pwm/pwm-aspeed.c @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Aspeed Technology Inc. + * + * PWM controller driver for Aspeed ast2600 SoCs. + * This drivers doesn't support earlier version of the IP. + * + * The formula of pwm period duration: + * period duration = ((DIV_L + 1) * (PERIOD + 1) << DIV_H) / input-clk + * + * The formula of pwm duty cycle duration: + * duty cycle duration = period duration * DUTY_CYCLE_FALLING_POINT / (PERIOD + 1) + * = ((DIV_L + 1) * DUTY_CYCLE_FALLING_POINT << DIV_H) / input-clk + * + * The software driver fixes the period to 255, which causes the high-frequency + * precision of the PWM to be coarse, in exchange for the fineness of the duty cycle. + * + * Register usage: + * PIN_ENABLE: When it is unset the pwm controller will always output low to the extern. + * Use to determine whether the PWM channel is enabled or disabled + * CLK_ENABLE: When it is unset the pwm controller will reset the duty counter to 0 and + * output low to the PIN_ENABLE mux after that the driver can still change the pwm period + * and duty and the value will apply when CLK_ENABLE be set again. + * Use to determine whether duty_cycle bigger than 0. + * PWM_ASPEED_CTRL_INVERSE: When it is toggled the output value will inverse immediately. + * PWM_ASPEED_DUTY_CYCLE_FALLING_POINT/PWM_ASPEED_DUTY_CYCLE_RISING_POINT: When these two + * values are equal it means the duty cycle = 100%. + * + * Limitations: + * - When changing both duty cycle and period, we cannot prevent in + * software that the output might produce a period with mixed + * settings. + * - Disabling the PWM doesn't complete the current period. + * + * Improvements: + * - When only changing one of duty cycle or period, our pwm controller will not + * generate the glitch, the configure will change at next cycle of pwm. + * This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* The channel number of Aspeed pwm controller */ +#define PWM_ASPEED_NR_PWMS 16 + +/* PWM Control Register */ +#define PWM_ASPEED_CTRL(ch) ((ch) * 0x10 + 0x00) +#define PWM_ASPEED_CTRL_LOAD_SEL_RISING_AS_WDT BIT(19) +#define PWM_ASPEED_CTRL_DUTY_LOAD_AS_WDT_ENABLE BIT(18) +#define PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE BIT(17) +#define PWM_ASPEED_CTRL_CLK_ENABLE BIT(16) +#define PWM_ASPEED_CTRL_LEVEL_OUTPUT BIT(15) +#define PWM_ASPEED_CTRL_INVERSE BIT(14) +#define PWM_ASPEED_CTRL_OPEN_DRAIN_ENABLE BIT(13) +#define PWM_ASPEED_CTRL_PIN_ENABLE BIT(12) +#define PWM_ASPEED_CTRL_CLK_DIV_H GENMASK(11, 8) +#define PWM_ASPEED_CTRL_CLK_DIV_L GENMASK(7, 0) + +/* PWM Duty Cycle Register */ +#define PWM_ASPEED_DUTY_CYCLE(ch) ((ch) * 0x10 + 0x04) +#define PWM_ASPEED_DUTY_CYCLE_PERIOD GENMASK(31, 24) +#define PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT GENMASK(23, 16) +#define PWM_ASPEED_DUTY_CYCLE_FALLING_POINT GENMASK(15, 8) +#define PWM_ASPEED_DUTY_CYCLE_RISING_POINT GENMASK(7, 0) + +/* PWM fixed value */ +#define PWM_ASPEED_FIXED_PERIOD 0xff + +#define NSEC_PER_SEC 1000000000L + +struct aspeed_pwm_priv { + struct clk clk; + struct regmap *regmap; + struct reset_ctl reset; +}; + +static int aspeed_pwm_set_invert(struct udevice *dev, uint channel, bool polarity) +{ + struct aspeed_pwm_priv *priv = dev_get_priv(dev); + + if (channel >= PWM_ASPEED_NR_PWMS) + return -EINVAL; + + regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel), + PWM_ASPEED_CTRL_INVERSE, + FIELD_PREP(PWM_ASPEED_CTRL_INVERSE, + polarity)); + return 0; +} + +static int aspeed_pwm_set_enable(struct udevice *dev, uint channel, bool enable) +{ + struct aspeed_pwm_priv *priv = dev_get_priv(dev); + + if (channel >= PWM_ASPEED_NR_PWMS) + return -EINVAL; + + regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel), + PWM_ASPEED_CTRL_PIN_ENABLE, + enable ? PWM_ASPEED_CTRL_PIN_ENABLE : 0); + return 0; +} + +static int aspeed_pwm_set_config(struct udevice *dev, uint channel, + uint period_ns, uint duty_ns) +{ + struct aspeed_pwm_priv *priv = dev_get_priv(dev); + u32 duty_pt; + unsigned long rate; + u64 div_h, div_l, divisor; + bool clk_en; + + if (channel >= PWM_ASPEED_NR_PWMS) + return -EINVAL; + dev_dbg(dev, "expect period: %dns, duty_cycle: %dns\n", period_ns, + duty_ns); + + rate = clk_get_rate(&priv->clk); + /* + * Pick the smallest value for div_h so that div_l can be the biggest + * which results in a finer resolution near the target period value. + */ + divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) * + (PWM_ASPEED_CTRL_CLK_DIV_L + 1); + div_h = order_base_2(div64_u64((u64)rate * period_ns + divisor - 1, divisor)); + if (div_h > 0xf) + div_h = 0xf; + + divisor = ((u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1)) << div_h; + div_l = div64_u64((u64)rate * period_ns, divisor); + + if (div_l == 0) + return -ERANGE; + + div_l -= 1; + + if (div_l > 255) + div_l = 255; + + dev_dbg(dev, "clk source: %ld div_h %lld, div_l : %lld\n", rate, div_h, + div_l); + /* duty_pt = duty_cycle * (PERIOD + 1) / period */ + duty_pt = div64_u64(duty_ns * (u64)rate, + (u64)NSEC_PER_SEC * (div_l + 1) << div_h); + dev_dbg(dev, "duty_cycle = %d, duty_pt = %d\n", duty_ns, + duty_pt); + + if (duty_pt == 0) { + clk_en = 0; + } else { + clk_en = 1; + if (duty_pt >= (PWM_ASPEED_FIXED_PERIOD + 1)) + duty_pt = 0; + /* + * Fixed DUTY_CYCLE_PERIOD to its max value to get a + * fine-grained resolution for duty_cycle at the expense of a + * coarser period resolution. + */ + regmap_update_bits(priv->regmap, PWM_ASPEED_DUTY_CYCLE(channel), + PWM_ASPEED_DUTY_CYCLE_PERIOD | + PWM_ASPEED_DUTY_CYCLE_RISING_POINT | + PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, + FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_PERIOD, + PWM_ASPEED_FIXED_PERIOD) | + FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, + duty_pt)); + } + + regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel), + PWM_ASPEED_CTRL_CLK_DIV_H | + PWM_ASPEED_CTRL_CLK_DIV_L | + PWM_ASPEED_CTRL_CLK_ENABLE, + FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_H, div_h) | + FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_L, div_l) | + FIELD_PREP(PWM_ASPEED_CTRL_CLK_ENABLE, clk_en)); + return 0; +} + +static int aspeed_pwm_probe(struct udevice *dev) +{ + int ret; + struct aspeed_pwm_priv *priv = dev_get_priv(dev); + struct udevice *parent_dev = dev_get_parent(dev); + + priv->regmap = syscon_node_to_regmap(dev_ofnode(dev->parent)); + if (IS_ERR(priv->regmap)) { + dev_err(dev, "Couldn't get regmap\n"); + return PTR_ERR(priv->regmap); + } + + ret = clk_get_by_index(parent_dev, 0, &priv->clk); + if (ret < 0) { + dev_err(dev, "get clock failed\n"); + return ret; + } + + ret = reset_get_by_index(parent_dev, 0, &priv->reset); + if (ret) { + dev_err(dev, "get reset failed\n"); + return ret; + } + ret = reset_deassert(&priv->reset); + if (ret) { + dev_err(dev, "cannot deassert reset control: %pe\n", + ERR_PTR(ret)); + return ret; + } + + return 0; +} + +static int aspeed_pwm_remove(struct udevice *dev) +{ + struct aspeed_pwm_priv *priv = dev_get_priv(dev); + + reset_assert(&priv->reset); + + return 0; +} + +static const struct pwm_ops aspeed_pwm_ops = { + .set_invert = aspeed_pwm_set_invert, + .set_config = aspeed_pwm_set_config, + .set_enable = aspeed_pwm_set_enable, +}; + +static const struct udevice_id aspeed_pwm_ids[] = { + { .compatible = "aspeed,ast2600-pwm" }, + { } +}; + +U_BOOT_DRIVER(aspeed_pwm) = { + .name = "aspeed_pwm", + .id = UCLASS_PWM, + .of_match = aspeed_pwm_ids, + .ops = &aspeed_pwm_ops, + .probe = aspeed_pwm_probe, + .remove = aspeed_pwm_remove, + .priv_auto = sizeof(struct aspeed_pwm_priv), +}; -- cgit v1.3.1 From 73ee1f261ee7f0fa67ec43276824dd6533c138fe Mon Sep 17 00:00:00 2001 From: Billy Tsai Date: Tue, 8 Mar 2022 11:04:06 +0800 Subject: pinctrl: Add the pinctrl setting for PWM. This patchs add the signal description array for PWM pinctrl settings. Signed-off-by: Billy Tsai Reviewed-by: Simon Glass Reviewed-by: Chia-Wei Wang --- arch/arm/dts/ast2600.dtsi | 80 +++++++++++++++++++++ drivers/pinctrl/aspeed/pinctrl_ast2600.c | 120 +++++++++++++++++++++++++++++++ 2 files changed, 200 insertions(+) (limited to 'drivers') diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi index 98840ce7b0b..ce006a37592 100644 --- a/arch/arm/dts/ast2600.dtsi +++ b/arch/arm/dts/ast2600.dtsi @@ -1626,6 +1626,86 @@ groups = "PWM7"; }; + pinctrl_pwm8g0_default: pwm8g0_default { + function = "PWM8G0"; + groups = "PWM8G0"; + }; + + pinctrl_pwm8g1_default: pwm8g1_default { + function = "PWM8G1"; + groups = "PWM8G1"; + }; + + pinctrl_pwm9g0_default: pwm9g0_default { + function = "PWM9G0"; + groups = "PWM9G0"; + }; + + pinctrl_pwm9g1_default: pwm9g1_default { + function = "PWM9G1"; + groups = "PWM9G1"; + }; + + pinctrl_pwm10g0_default: pwm10g0_default { + function = "PWM10G0"; + groups = "PWM10G0"; + }; + + pinctrl_pwm10g1_default: pwm10g1_default { + function = "PWM10G1"; + groups = "PWM10G1"; + }; + + pinctrl_pwm11g0_default: pwm11g0_default { + function = "PWM11G0"; + groups = "PWM11G0"; + }; + + pinctrl_pwm11g1_default: pwm11g1_default { + function = "PWM11G1"; + groups = "PWM11G1"; + }; + + pinctrl_pwm12g0_default: pwm12g0_default { + function = "PWM12G0"; + groups = "PWM12G0"; + }; + + pinctrl_pwm12g1_default: pwm12g1_default { + function = "PWM12G1"; + groups = "PWM12G1"; + }; + + pinctrl_pwm13g0_default: pwm13g0_default { + function = "PWM13G0"; + groups = "PWM13G0"; + }; + + pinctrl_pwm13g1_default: pwm13g1_default { + function = "PWM13G1"; + groups = "PWM13G1"; + }; + + pinctrl_pwm14g0_default: pwm14g0_default { + function = "PWM14G0"; + groups = "PWM14G0"; + }; + + pinctrl_pwm14g1_default: pwm14g1_default { + function = "PWM14G1"; + groups = "PWM14G1"; + }; + + pinctrl_pwm15g0_default: pwm15g0_default { + function = "PWM15G0"; + groups = "PWM15G0"; + }; + + pinctrl_pwm15g1_default: pwm15g1_default { + function = "PWM15G1"; + groups = "PWM15G1"; + }; + pinctrl_rgmii1_default: rgmii1_default { function = "RGMII1"; groups = "RGMII1"; diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2600.c b/drivers/pinctrl/aspeed/pinctrl_ast2600.c index 12cba83f6c0..97e8b4ec9b4 100644 --- a/drivers/pinctrl/aspeed/pinctrl_ast2600.c +++ b/drivers/pinctrl/aspeed/pinctrl_ast2600.c @@ -335,6 +335,102 @@ static struct aspeed_sig_desc pcie1rc_link[] = { { 0x500, BIT(24), 0 }, /* dedicate rc reset */ }; +static struct aspeed_sig_desc pwm0[] = { + {0x41c, BIT(16), 0}, +}; + +static struct aspeed_sig_desc pwm1[] = { + {0x41c, BIT(17), 0}, +}; + +static struct aspeed_sig_desc pwm2[] = { + {0x41c, BIT(18), 0}, +}; + +static struct aspeed_sig_desc pwm3[] = { + {0x41c, BIT(19), 0}, +}; + +static struct aspeed_sig_desc pwm4[] = { + {0x41c, BIT(20), 0}, +}; + +static struct aspeed_sig_desc pwm5[] = { + {0x41c, BIT(21), 0}, +}; + +static struct aspeed_sig_desc pwm6[] = { + {0x41c, BIT(22), 0}, +}; + +static struct aspeed_sig_desc pwm7[] = { + {0x41c, BIT(23), 0}, +}; + +static struct aspeed_sig_desc pwm8g0[] = { + {0x4B4, BIT(8), 0}, +}; + +static struct aspeed_sig_desc pwm8g1[] = { + {0x41c, BIT(24), 0}, +}; + +static struct aspeed_sig_desc pwm9g0[] = { + {0x4B4, BIT(9), 0}, +}; + +static struct aspeed_sig_desc pwm9g1[] = { + {0x41c, BIT(25), 0}, +}; + +static struct aspeed_sig_desc pwm10g0[] = { + {0x4B4, BIT(10), 0}, +}; + +static struct aspeed_sig_desc pwm10g1[] = { + {0x41c, BIT(26), 0}, +}; + +static struct aspeed_sig_desc pwm11g0[] = { + {0x4B4, BIT(11), 0}, +}; + +static struct aspeed_sig_desc pwm11g1[] = { + {0x41c, BIT(27), 0}, +}; + +static struct aspeed_sig_desc pwm12g0[] = { + {0x4B4, BIT(12), 0}, +}; + +static struct aspeed_sig_desc pwm12g1[] = { + {0x41c, BIT(28), 0}, +}; + +static struct aspeed_sig_desc pwm13g0[] = { + {0x4B4, BIT(13), 0}, +}; + +static struct aspeed_sig_desc pwm13g1[] = { + {0x41c, BIT(29), 0}, +}; + +static struct aspeed_sig_desc pwm14g0[] = { + {0x4B4, BIT(14), 0}, +}; + +static struct aspeed_sig_desc pwm14g1[] = { + {0x41c, BIT(30), 0}, +}; + +static struct aspeed_sig_desc pwm15g0[] = { + {0x4B4, BIT(15), 0}, +}; + +static struct aspeed_sig_desc pwm15g1[] = { + {0x41c, BIT(31), 0}, +}; + static const struct aspeed_group_config ast2600_groups[] = { { "MAC1LINK", ARRAY_SIZE(mac1_link), mac1_link }, { "MAC2LINK", ARRAY_SIZE(mac2_link), mac2_link }, @@ -394,6 +490,30 @@ static const struct aspeed_group_config ast2600_groups[] = { { "USB2BH", ARRAY_SIZE(usb2bh_link), usb2bh_link }, { "PCIE0RC", ARRAY_SIZE(pcie0rc_link), pcie0rc_link }, { "PCIE1RC", ARRAY_SIZE(pcie1rc_link), pcie1rc_link }, + { "PWM0", ARRAY_SIZE(pwm0), pwm0 }, + { "PWM1", ARRAY_SIZE(pwm1), pwm1 }, + { "PWM2", ARRAY_SIZE(pwm2), pwm2 }, + { "PWM3", ARRAY_SIZE(pwm3), pwm3 }, + { "PWM4", ARRAY_SIZE(pwm4), pwm4 }, + { "PWM5", ARRAY_SIZE(pwm5), pwm5 }, + { "PWM6", ARRAY_SIZE(pwm6), pwm6 }, + { "PWM7", ARRAY_SIZE(pwm7), pwm7 }, + { "PWM8G0", ARRAY_SIZE(pwm8g0), pwm8g0 }, + { "PWM8G1", ARRAY_SIZE(pwm8g1), pwm8g1 }, + { "PWM9G0", ARRAY_SIZE(pwm9g0), pwm9g0 }, + { "PWM9G1", ARRAY_SIZE(pwm9g1), pwm9g1 }, + { "PWM10G0", ARRAY_SIZE(pwm10g0), pwm10g0 }, + { "PWM10G1", ARRAY_SIZE(pwm10g1), pwm10g1 }, + { "PWM11G0", ARRAY_SIZE(pwm11g0), pwm11g0 }, + { "PWM11G1", ARRAY_SIZE(pwm11g1), pwm11g1 }, + { "PWM12G0", ARRAY_SIZE(pwm12g0), pwm12g0 }, + { "PWM12G1", ARRAY_SIZE(pwm12g1), pwm12g1 }, + { "PWM13G0", ARRAY_SIZE(pwm13g0), pwm13g0 }, + { "PWM13G1", ARRAY_SIZE(pwm13g1), pwm13g1 }, + { "PWM14G0", ARRAY_SIZE(pwm14g0), pwm14g0 }, + { "PWM14G1", ARRAY_SIZE(pwm14g1), pwm14g1 }, + { "PWM15G0", ARRAY_SIZE(pwm15g0), pwm15g0 }, + { "PWM15G1", ARRAY_SIZE(pwm15g1), pwm15g1 }, }; static int ast2600_pinctrl_get_groups_count(struct udevice *dev) -- cgit v1.3.1 From 88ca8e26958b67c05844e7be85a7e983eb594793 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 11 Mar 2022 12:10:01 -0700 Subject: disk: Add an option for partitions in SPL In some cases we do not want to enable partition support in SPL. Add an option to allow this. Signed-off-by: Simon Glass --- disk/Kconfig | 24 ++++++++++++++++++++---- disk/Makefile | 2 +- drivers/block/blk-uclass.c | 2 +- 3 files changed, 22 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/disk/Kconfig b/disk/Kconfig index cee16a80bc2..13700322e97 100644 --- a/disk/Kconfig +++ b/disk/Kconfig @@ -4,10 +4,6 @@ menu "Partition Types" config PARTITIONS bool "Enable Partition Labels (disklabels) support" default y - select SPL_SPRINTF if SPL - select TPL_SPRINTF if TPL - select SPL_STRTO if SPL - select TPL_STRTO if TPL help Partition Labels (disklabels) Supported: Zero or more of the following: @@ -23,6 +19,26 @@ config PARTITIONS you must configure support for at least one non-MTD partition type as well. +config SPL_PARTITIONS + bool "Enable Partition Labels (disklabels) support in SPL" + default y if PARTITIONS + select SPL_SPRINTF + select SPL_STRTO + help + Enable this for base partition support in SPL. The required + partition table types shold be enabled separately. This add a + small amount of size to SPL, typically 500 bytes. + +config TPL_PARTITIONS + bool "Enable Partition Labels (disklabels) support in TPL" + default y if PARTITIONS + select TPL_SPRINTF + select TPL_STRTO + help + Enable this for base partition support in SPL. The required + partition table types shold be enabled separately. This add a + small amount of size to SPL, typically 500 bytes. + config MAC_PARTITION bool "Enable Apple's MacOS partition table" depends on PARTITIONS diff --git a/disk/Makefile b/disk/Makefile index 6ce5a687b36..b197692c234 100644 --- a/disk/Makefile +++ b/disk/Makefile @@ -5,7 +5,7 @@ #ccflags-y += -DET_DEBUG -DDEBUG -obj-$(CONFIG_PARTITIONS) += part.o +obj-$(CONFIG_$(SPL_TPL_)PARTITIONS) += part.o obj-$(CONFIG_$(SPL_)MAC_PARTITION) += part_mac.o obj-$(CONFIG_$(SPL_)DOS_PARTITION) += part_dos.o obj-$(CONFIG_$(SPL_)ISO_PARTITION) += part_iso.o diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c index bee1cd6f0d8..f9f05f4e341 100644 --- a/drivers/block/blk-uclass.c +++ b/drivers/block/blk-uclass.c @@ -712,7 +712,7 @@ int blk_unbind_all(int if_type) static int blk_post_probe(struct udevice *dev) { - if (IS_ENABLED(CONFIG_PARTITIONS) && + if (CONFIG_IS_ENABLED(PARTITIONS) && IS_ENABLED(CONFIG_HAVE_BLOCK_DEVICE)) { struct blk_desc *desc = dev_get_uclass_plat(dev); -- cgit v1.3.1 From c537a36839964b66b6c56c7488c3809763de5a16 Mon Sep 17 00:00:00 2001 From: Philip Oberfichtner Date: Fri, 18 Mar 2022 12:04:38 +0100 Subject: bootcount: Add pmic pfuze100 bootcount driver Use the MEMA - MEMD registers on the PFUZE100 as bootcount registers. Based on work from Heiko Schocher . Signed-off-by: Philip Oberfichtner --- drivers/bootcount/Kconfig | 7 ++ drivers/bootcount/Makefile | 1 + drivers/bootcount/pmic_pfuze100.c | 161 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 169 insertions(+) create mode 100644 drivers/bootcount/pmic_pfuze100.c (limited to 'drivers') diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index 607027c968d..509d01d41ef 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -127,6 +127,13 @@ config DM_BOOTCOUNT_I2C_EEPROM pointing to the underlying i2c eeprom device) and an optional 'offset' property are supported. +config DM_BOOTCOUNT_PMIC_PFUZE100 + bool "Enable Bootcount driver for PMIC PFUZE100" + depends on DM_PMIC_PFUZE100 + help + Enable support for the bootcounter using PMIC PFUZE100 registers. + This works only, if the PMIC is not connected. + config DM_BOOTCOUNT_SPI_FLASH bool "Support SPI flash devices as a backing store for bootcount" depends on DM_SPI_FLASH diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile index 3a784bb0a64..b65959a384b 100644 --- a/drivers/bootcount/Makefile +++ b/drivers/bootcount/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_BOOTCOUNT_EXT) += bootcount_ext.o obj-$(CONFIG_BOOTCOUNT_AM33XX_NVMEM) += bootcount_nvmem.o obj-$(CONFIG_DM_BOOTCOUNT) += bootcount-uclass.o +obj-$(CONFIG_DM_BOOTCOUNT_PMIC_PFUZE100) += pmic_pfuze100.o obj-$(CONFIG_DM_BOOTCOUNT_RTC) += rtc.o obj-$(CONFIG_DM_BOOTCOUNT_I2C_EEPROM) += i2c-eeprom.o obj-$(CONFIG_DM_BOOTCOUNT_SPI_FLASH) += spi-flash.o diff --git a/drivers/bootcount/pmic_pfuze100.c b/drivers/bootcount/pmic_pfuze100.c new file mode 100644 index 00000000000..ad3bc03829d --- /dev/null +++ b/drivers/bootcount/pmic_pfuze100.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2022 Denx Software Engineering GmbH + * Heiko Schocher + * Philip Oberfichtner + * + * A bootcount driver using the registers MEMA - MEMD on the PFUZE100. + * This works only, if the PMIC is not connected. + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define PFUZE_BC_MAGIC 0xdead + +struct bootcount_pmic_priv { + struct udevice *pmic; +}; + +static int pfuze100_get_magic(struct udevice *dev, u32 *magic) +{ + int ret; + + ret = pmic_reg_read(dev, PFUZE100_MEMA); + if (ret < 0) + return ret; + *magic = ret; + + ret = pmic_reg_read(dev, PFUZE100_MEMB); + if (ret < 0) + return ret; + *magic += ret << 8; + + return 0; +} + +static int pfuze100_set_magic(struct udevice *dev) +{ + int ret; + + ret = pmic_reg_write(dev, PFUZE100_MEMA, PFUZE_BC_MAGIC & 0xff); + if (ret) + return ret; + + ret = pmic_reg_write(dev, PFUZE100_MEMB, (PFUZE_BC_MAGIC >> 8) & 0xff); + return ret; +} + +static int pfuze100_get_value(struct udevice *dev, u32 *a) +{ + int ret; + + ret = pmic_reg_read(dev, PFUZE100_MEMC); + if (ret < 0) + return ret; + *a = ret; + + ret = pmic_reg_read(dev, PFUZE100_MEMD); + if (ret < 0) + return ret; + *a += ret << 8; + + return 0; +} + +static int pfuze100_set_value(struct udevice *dev, u32 val) +{ + int ret; + + ret = pmic_reg_write(dev, PFUZE100_MEMC, val & 0xff); + if (ret) + return ret; + + ret = pmic_reg_write(dev, PFUZE100_MEMD, (val >> 8) & 0xff); + return ret; +} + +static int bootcount_pmic_set(struct udevice *dev, const u32 a) +{ + struct bootcount_pmic_priv *priv = dev_get_priv(dev); + + if (pfuze100_set_magic(priv->pmic)) { + debug("%s: writing magic failed\n", __func__); + return -EIO; + } + + if (pfuze100_set_value(priv->pmic, a)) { + debug("%s: writing value failed\n", __func__); + return -EIO; + } + + return 0; +} + +static int bootcount_pmic_get(struct udevice *dev, u32 *a) +{ + struct bootcount_pmic_priv *priv = dev_get_priv(dev); + u32 magic; + + if (pfuze100_get_magic(priv->pmic, &magic)) { + debug("%s: reading magic failed\n", __func__); + return -EIO; + } + + if (magic != PFUZE_BC_MAGIC) { + *a = 0; + return 0; + } + + if (pfuze100_get_value(priv->pmic, a)) { + debug("%s: reading value failed\n", __func__); + return -EIO; + } + + return 0; +} + +static int bootcount_pmic_probe(struct udevice *dev) +{ + struct ofnode_phandle_args phandle_args; + struct bootcount_pmic_priv *priv = dev_get_priv(dev); + struct udevice *pmic; + + if (dev_read_phandle_with_args(dev, "pmic", NULL, 0, 0, &phandle_args)) { + debug("%s: pmic backing device not specified\n", dev->name); + return -ENOENT; + } + + if (uclass_get_device_by_ofnode(UCLASS_PMIC, phandle_args.node, &pmic)) { + debug("%s: could not get backing device\n", dev->name); + return -ENODEV; + } + + priv->pmic = pmic; + + return 0; +} + +static const struct bootcount_ops bootcount_pmic_ops = { + .get = bootcount_pmic_get, + .set = bootcount_pmic_set, +}; + +static const struct udevice_id bootcount_pmic_ids[] = { + { .compatible = "u-boot,bootcount-pmic" }, + { } +}; + +U_BOOT_DRIVER(bootcount_pmic) = { + .name = "bootcount-pmic", + .id = UCLASS_BOOTCOUNT, + .priv_auto = sizeof(struct bootcount_pmic_priv), + .probe = bootcount_pmic_probe, + .of_match = bootcount_pmic_ids, + .ops = &bootcount_pmic_ops, +}; -- cgit v1.3.1 From 814dd92bdc22e2949e70b86440f0a83b50e6bc7a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 23 Jan 2022 07:04:02 -0700 Subject: video: Drop cfg_console The non-driver model video support was removed two years ago. Drop this driver, which is only used by nokia_rx51. Signed-off-by: Simon Glass --- README | 1 - cmd/cls.c | 2 - common/stdio.c | 1 - doc/usage/bootmenu.rst | 5 - drivers/video/Kconfig | 50 -- drivers/video/Makefile | 1 - drivers/video/cfb_console.c | 1865 ------------------------------------------- drivers/video/omap3_dss.c | 28 - 8 files changed, 1953 deletions(-) delete mode 100644 drivers/video/cfb_console.c (limited to 'drivers') diff --git a/README b/README index 805c8f0d048..e88b16c500e 100644 --- a/README +++ b/README @@ -978,7 +978,6 @@ The following options need to be configured: CONFIG_SYS_DIU_ADDR CONFIG_VIDEO - CONFIG_CFB_CONSOLE CONFIG_VIDEO_SW_CURSOR CONFIG_VGA_AS_SINGLE_DEVICE CONFIG_VIDEO_BMP_LOGO diff --git a/cmd/cls.c b/cmd/cls.c index bdeb49786d4..502d5ed697a 100644 --- a/cmd/cls.c +++ b/cmd/cls.c @@ -28,8 +28,6 @@ static int do_video_clear(struct cmd_tbl *cmdtp, int flag, int argc, if (video_clear(dev)) return CMD_RET_FAILURE; #endif -#elif defined(CONFIG_CFB_CONSOLE) - video_clear(); #elif defined(CONFIG_LCD) lcd_clear(); #else diff --git a/common/stdio.c b/common/stdio.c index 063c659bbc3..97f21ea3465 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -368,7 +368,6 @@ int stdio_add_devices(void) if (IS_ENABLED(CONFIG_LCD)) drv_lcd_init(); if (IS_ENABLED(CONFIG_VIDEO) || - IS_ENABLED(CONFIG_CFB_CONSOLE) || IS_ENABLED(CONFIG_VIDEO_VCXK)) drv_video_init(); } diff --git a/doc/usage/bootmenu.rst b/doc/usage/bootmenu.rst index 1f094ad6ed2..1016ac8cebd 100644 --- a/doc/usage/bootmenu.rst +++ b/doc/usage/bootmenu.rst @@ -88,8 +88,3 @@ To run the bootmenu at startup add these additional settings:: CONFIG_AUTOBOOT_KEYED=y CONFIG_BOOTDELAY=30 CONFIG_AUTOBOOT_MENU_SHOW=y - -When you intend to use the bootmenu on a color frame buffer console, -make sure to additionally define:: - - CONFIG_CFB_CONSOLE_ANSI=y diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 1bf7f4a8084..c8c85c69276 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -708,56 +708,6 @@ config VIDEO model. Video drivers typically provide a colour text console and cursor. -config CFB_CONSOLE - bool "Enable colour frame buffer console" - depends on VIDEO || ARCH_OMAP2PLUS - default y if VIDEO - help - Enables the colour frame buffer driver. This supports colour - output on a bitmap display from an in-memory frame buffer. - Several colour devices are supported along with various options to - adjust the supported features. The driver is implemented in - cfb_console.c - - The following defines are needed (cf. smiLynxEM, i8042) - VIDEO_FB_LITTLE_ENDIAN graphic memory organisation - (default big endian) - VIDEO_HW_RECTFILL graphic chip supports - rectangle fill (cf. smiLynxEM) - VIDEO_HW_BITBLT graphic chip supports - bit-blit (cf. smiLynxEM) - VIDEO_VISIBLE_COLS visible pixel columns (cols=pitch) - VIDEO_VISIBLE_ROWS visible pixel rows - VIDEO_PIXEL_SIZE bytes per pixel - VIDEO_DATA_FORMAT graphic data format - (0-5, cf. cfb_console.c) - VIDEO_FB_ADRS framebuffer address - VIDEO_KBD_INIT_FCT keyboard int fct (i.e. rx51_kp_init()) - VIDEO_TSTC_FCT test char fct (i.e. rx51_kp_tstc) - VIDEO_GETC_FCT get char fct (i.e. rx51_kp_getc) - CONFIG_VIDEO_LOGO display Linux logo in upper left corner - CONFIG_VIDEO_BMP_LOGO use bmp_logo.h instead of linux_logo.h - for logo. Requires CONFIG_VIDEO_LOGO - CONFIG_CONSOLE_EXTRA_INFO - additional board info beside - the logo - CONFIG_HIDE_LOGO_VERSION - do not display bootloader - version string - - When CONFIG_CFB_CONSOLE is defined, the video console is the - default console. The serial console can be forced by setting the - environment 'console=serial'. - -config CFB_CONSOLE_ANSI - bool "Support ANSI escape sequences" - depends on CFB_CONSOLE - help - This allows the colour buffer frame buffer driver to support - a limited number of ANSI escape sequences (cursor control, - erase functions and limited graphics rendition control). Normal - output from U-Boot will pass through this filter. - config VGA_AS_SINGLE_DEVICE bool "Set the video as an output-only device" depends on CFB_CONSOLE diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 2530791eb43..be52512d6fd 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -30,7 +30,6 @@ obj-y += ti/ obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o -obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o obj-$(CONFIG_FORMIKE) += formike.o obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o obj-$(CONFIG_IHS_VIDEO_OUT) += ihs_video_out.o diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c deleted file mode 100644 index 52b109f1551..00000000000 --- a/drivers/video/cfb_console.c +++ /dev/null @@ -1,1865 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - */ - -/* - * cfb_console.c - * - * Color Framebuffer Console driver for 8/15/16/24/32 bits per pixel. - * - * At the moment only the 8x16 font is tested and the font fore- and - * background color is limited to black/white/gray colors. The Linux - * logo can be placed in the upper left corner and additional board - * information strings (that normally goes to serial port) can be drawn. - * - * The console driver can use a keyboard interface for character input - * but this is deprecated. Only rk51 uses it. - * - * Character output goes to a memory-mapped video - * framebuffer with little or big-endian organisation. - * With environment setting 'console=serial' the console i/o can be - * forced to serial port. - * - * The driver uses graphic specific defines/parameters/functions: - * - * (for SMI LynxE graphic chip) - * - * VIDEO_FB_LITTLE_ENDIAN - framebuffer organisation default: big endian - * VIDEO_HW_RECTFILL - graphic driver supports hardware rectangle fill - * VIDEO_HW_BITBLT - graphic driver supports hardware bit blt - * - * Console Parameters are set by graphic drivers global struct: - * - * VIDEO_VISIBLE_COLS - x resolution - * VIDEO_VISIBLE_ROWS - y resolution - * VIDEO_PIXEL_SIZE - storage size in byte per pixel - * VIDEO_DATA_FORMAT - graphical data format GDF - * VIDEO_FB_ADRS - start of video memory - * - * VIDEO_KBD_INIT_FCT - init function for keyboard - * VIDEO_TSTC_FCT - keyboard_tstc function - * VIDEO_GETC_FCT - keyboard_getc function - * - * CONFIG_VIDEO_BMP_LOGO - use bmp_logo instead of linux_logo - * CONFIG_CONSOLE_EXTRA_INFO - display additional board information - * strings that normaly goes to serial - * port. This define requires a board - * specific function: - * video_drawstring (VIDEO_INFO_X, - * VIDEO_INFO_Y + i*VIDEO_FONT_HEIGHT, - * info); - * that fills a info buffer at i=row. - * s.a: board/eltec/bab7xx. - * - * CONFIG_VIDEO_SW_CURSOR: - Draws a cursor after the last - * character. No blinking is provided. - * Uses the macros CURSOR_SET and - * CURSOR_OFF. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc. - */ -#include - -#include - -/* - * some Macros - */ -#define VIDEO_VISIBLE_COLS (pGD->winSizeX) -#define VIDEO_VISIBLE_ROWS (pGD->winSizeY) -#define VIDEO_PIXEL_SIZE (pGD->gdfBytesPP) -#define VIDEO_DATA_FORMAT (pGD->gdfIndex) -#define VIDEO_FB_ADRS (pGD->frameAdrs) - -/* - * Console device - */ - -#include -#include -#include - -#if defined(CONFIG_CMD_DATE) -#include -#endif - -#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) -#include -#include -#include -#endif - -#if !defined(CONFIG_VIDEO_SW_CURSOR) -/* no Cursor defined */ -#define CURSOR_ON -#define CURSOR_OFF -#define CURSOR_SET -#endif - -#if defined(CONFIG_VIDEO_SW_CURSOR) -void console_cursor(int state); - -#define CURSOR_ON console_cursor(1) -#define CURSOR_OFF console_cursor(0) -#define CURSOR_SET video_set_cursor() -#endif /* CONFIG_VIDEO_SW_CURSOR */ - -#define VIDEO_COLS VIDEO_VISIBLE_COLS -#define VIDEO_ROWS VIDEO_VISIBLE_ROWS -#ifndef VIDEO_LINE_LEN -#define VIDEO_LINE_LEN (VIDEO_COLS * VIDEO_PIXEL_SIZE) -#endif -#define VIDEO_SIZE (VIDEO_ROWS * VIDEO_LINE_LEN) -#define VIDEO_BURST_LEN (VIDEO_COLS/8) - -#define CONSOLE_ROWS (VIDEO_ROWS / VIDEO_FONT_HEIGHT) - -#define CONSOLE_COLS (VIDEO_COLS / VIDEO_FONT_WIDTH) -#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * VIDEO_LINE_LEN) -#define CONSOLE_ROW_FIRST (video_console_address) -#define CONSOLE_ROW_SECOND (video_console_address + CONSOLE_ROW_SIZE) -#define CONSOLE_ROW_LAST (video_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE) -#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) - -/* By default we scroll by a single line */ -#ifndef CONFIG_CONSOLE_SCROLL_LINES -#define CONFIG_CONSOLE_SCROLL_LINES 1 -#endif - -/* Macros */ -#ifdef VIDEO_FB_LITTLE_ENDIAN -#define SWAP16(x) ((((x) & 0x00ff) << 8) | \ - ((x) >> 8) \ - ) -#define SWAP32(x) ((((x) & 0x000000ff) << 24) | \ - (((x) & 0x0000ff00) << 8) | \ - (((x) & 0x00ff0000) >> 8) | \ - (((x) & 0xff000000) >> 24) \ - ) -#define SHORTSWAP32(x) ((((x) & 0x000000ff) << 8) | \ - (((x) & 0x0000ff00) >> 8) | \ - (((x) & 0x00ff0000) << 8) | \ - (((x) & 0xff000000) >> 8) \ - ) -#else -#define SWAP16(x) (x) -#define SWAP32(x) (x) -#if defined(VIDEO_FB_16BPP_WORD_SWAP) -#define SHORTSWAP32(x) (((x) >> 16) | ((x) << 16)) -#else -#define SHORTSWAP32(x) (x) -#endif -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* Locals */ -static GraphicDevice *pGD; /* Pointer to Graphic array */ - -static void *video_fb_address; /* frame buffer address */ -static void *video_console_address; /* console buffer start address */ - -static int video_logo_height; /* not supported anymore */ - -static int __maybe_unused cursor_state; -static int __maybe_unused old_col; -static int __maybe_unused old_row; - -static int console_col; /* cursor col */ -static int console_row; /* cursor row */ - -static u32 eorx, fgx, bgx; /* color pats */ - -static int cfb_do_flush_cache; - -#ifdef CONFIG_CFB_CONSOLE_ANSI -static char ansi_buf[10]; -static int ansi_buf_size; -static int ansi_colors_need_revert; -static int ansi_cursor_hidden; -#endif - -static const int video_font_draw_table8[] = { - 0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff, - 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff, - 0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff, - 0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff -}; - -static const int video_font_draw_table15[] = { - 0x00000000, 0x00007fff, 0x7fff0000, 0x7fff7fff -}; - -static const int video_font_draw_table16[] = { - 0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff -}; - -static const int video_font_draw_table24[16][3] = { - {0x00000000, 0x00000000, 0x00000000}, - {0x00000000, 0x00000000, 0x00ffffff}, - {0x00000000, 0x0000ffff, 0xff000000}, - {0x00000000, 0x0000ffff, 0xffffffff}, - {0x000000ff, 0xffff0000, 0x00000000}, - {0x000000ff, 0xffff0000, 0x00ffffff}, - {0x000000ff, 0xffffffff, 0xff000000}, - {0x000000ff, 0xffffffff, 0xffffffff}, - {0xffffff00, 0x00000000, 0x00000000}, - {0xffffff00, 0x00000000, 0x00ffffff}, - {0xffffff00, 0x0000ffff, 0xff000000}, - {0xffffff00, 0x0000ffff, 0xffffffff}, - {0xffffffff, 0xffff0000, 0x00000000}, - {0xffffffff, 0xffff0000, 0x00ffffff}, - {0xffffffff, 0xffffffff, 0xff000000}, - {0xffffffff, 0xffffffff, 0xffffffff} -}; - -static const int video_font_draw_table32[16][4] = { - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, - {0x00000000, 0x00000000, 0x00000000, 0x00ffffff}, - {0x00000000, 0x00000000, 0x00ffffff, 0x00000000}, - {0x00000000, 0x00000000, 0x00ffffff, 0x00ffffff}, - {0x00000000, 0x00ffffff, 0x00000000, 0x00000000}, - {0x00000000, 0x00ffffff, 0x00000000, 0x00ffffff}, - {0x00000000, 0x00ffffff, 0x00ffffff, 0x00000000}, - {0x00000000, 0x00ffffff, 0x00ffffff, 0x00ffffff}, - {0x00ffffff, 0x00000000, 0x00000000, 0x00000000}, - {0x00ffffff, 0x00000000, 0x00000000, 0x00ffffff}, - {0x00ffffff, 0x00000000, 0x00ffffff, 0x00000000}, - {0x00ffffff, 0x00000000, 0x00ffffff, 0x00ffffff}, - {0x00ffffff, 0x00ffffff, 0x00000000, 0x00000000}, - {0x00ffffff, 0x00ffffff, 0x00000000, 0x00ffffff}, - {0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00000000}, - {0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff} -}; - -/* - * Implement a weak default function for boards that optionally - * need to skip the cfb initialization. - */ -__weak int board_cfb_skip(void) -{ - /* As default, don't skip cfb init */ - return 0; -} - -static void video_drawchars(int xx, int yy, unsigned char *s, int count) -{ - u8 *cdat, *dest, *dest0; - int rows, offset, c; - - offset = yy * VIDEO_LINE_LEN + xx * VIDEO_PIXEL_SIZE; - dest0 = video_fb_address + offset; - - switch (VIDEO_DATA_FORMAT) { - case GDF__8BIT_INDEX: - case GDF__8BIT_332RGB: - while (count--) { - c = *s; - cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; - for (rows = VIDEO_FONT_HEIGHT, dest = dest0; - rows--; dest += VIDEO_LINE_LEN) { - u8 bits = *cdat++; - - ((u32 *) dest)[0] = - (video_font_draw_table8[bits >> 4] & - eorx) ^ bgx; - - if (VIDEO_FONT_WIDTH == 4) - continue; - - ((u32 *) dest)[1] = - (video_font_draw_table8[bits & 15] & - eorx) ^ bgx; - } - dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; - s++; - } - break; - - case GDF_15BIT_555RGB: - while (count--) { - c = *s; - cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; - for (rows = VIDEO_FONT_HEIGHT, dest = dest0; - rows--; dest += VIDEO_LINE_LEN) { - u8 bits = *cdat++; - - ((u32 *) dest)[0] = - SHORTSWAP32((video_font_draw_table15 - [bits >> 6] & eorx) ^ - bgx); - ((u32 *) dest)[1] = - SHORTSWAP32((video_font_draw_table15 - [bits >> 4 & 3] & eorx) ^ - bgx); - - if (VIDEO_FONT_WIDTH == 4) - continue; - - ((u32 *) dest)[2] = - SHORTSWAP32((video_font_draw_table15 - [bits >> 2 & 3] & eorx) ^ - bgx); - ((u32 *) dest)[3] = - SHORTSWAP32((video_font_draw_table15 - [bits & 3] & eorx) ^ - bgx); - } - dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; - s++; - } - break; - - case GDF_16BIT_565RGB: - while (count--) { - c = *s; - cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; - for (rows = VIDEO_FONT_HEIGHT, dest = dest0; - rows--; dest += VIDEO_LINE_LEN) { - u8 bits = *cdat++; - - ((u32 *) dest)[0] = - SHORTSWAP32((video_font_draw_table16 - [bits >> 6] & eorx) ^ - bgx); - ((u32 *) dest)[1] = - SHORTSWAP32((video_font_draw_table16 - [bits >> 4 & 3] & eorx) ^ - bgx); - - if (VIDEO_FONT_WIDTH == 4) - continue; - - ((u32 *) dest)[2] = - SHORTSWAP32((video_font_draw_table16 - [bits >> 2 & 3] & eorx) ^ - bgx); - ((u32 *) dest)[3] = - SHORTSWAP32((video_font_draw_table16 - [bits & 3] & eorx) ^ - bgx); - } - dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; - s++; - } - break; - - case GDF_32BIT_X888RGB: - while (count--) { - c = *s; - cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; - for (rows = VIDEO_FONT_HEIGHT, dest = dest0; - rows--; dest += VIDEO_LINE_LEN) { - u8 bits = *cdat++; - - ((u32 *) dest)[0] = - SWAP32((video_font_draw_table32 - [bits >> 4][0] & eorx) ^ bgx); - ((u32 *) dest)[1] = - SWAP32((video_font_draw_table32 - [bits >> 4][1] & eorx) ^ bgx); - ((u32 *) dest)[2] = - SWAP32((video_font_draw_table32 - [bits >> 4][2] & eorx) ^ bgx); - ((u32 *) dest)[3] = - SWAP32((video_font_draw_table32 - [bits >> 4][3] & eorx) ^ bgx); - - - if (VIDEO_FONT_WIDTH == 4) - continue; - - ((u32 *) dest)[4] = - SWAP32((video_font_draw_table32 - [bits & 15][0] & eorx) ^ bgx); - ((u32 *) dest)[5] = - SWAP32((video_font_draw_table32 - [bits & 15][1] & eorx) ^ bgx); - ((u32 *) dest)[6] = - SWAP32((video_font_draw_table32 - [bits & 15][2] & eorx) ^ bgx); - ((u32 *) dest)[7] = - SWAP32((video_font_draw_table32 - [bits & 15][3] & eorx) ^ bgx); - } - dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; - s++; - } - break; - - case GDF_24BIT_888RGB: - while (count--) { - c = *s; - cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; - for (rows = VIDEO_FONT_HEIGHT, dest = dest0; - rows--; dest += VIDEO_LINE_LEN) { - u8 bits = *cdat++; - - ((u32 *) dest)[0] = - (video_font_draw_table24[bits >> 4][0] - & eorx) ^ bgx; - ((u32 *) dest)[1] = - (video_font_draw_table24[bits >> 4][1] - & eorx) ^ bgx; - ((u32 *) dest)[2] = - (video_font_draw_table24[bits >> 4][2] - & eorx) ^ bgx; - - if (VIDEO_FONT_WIDTH == 4) - continue; - - ((u32 *) dest)[3] = - (video_font_draw_table24[bits & 15][0] - & eorx) ^ bgx; - ((u32 *) dest)[4] = - (video_font_draw_table24[bits & 15][1] - & eorx) ^ bgx; - ((u32 *) dest)[5] = - (video_font_draw_table24[bits & 15][2] - & eorx) ^ bgx; - } - dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; - s++; - } - break; - } -} - -static inline void video_drawstring(int xx, int yy, unsigned char *s) -{ - video_drawchars(xx, yy, s, strlen((char *) s)); -} - -static void video_putchar(int xx, int yy, unsigned char c) -{ - video_drawchars(xx, yy + video_logo_height, &c, 1); -} - -#if defined(CONFIG_VIDEO_SW_CURSOR) -static void video_set_cursor(void) -{ - if (cursor_state) - console_cursor(0); - console_cursor(1); -} - -static void video_invertchar(int xx, int yy) -{ - int firstx = xx * VIDEO_PIXEL_SIZE; - int lastx = (xx + VIDEO_FONT_WIDTH) * VIDEO_PIXEL_SIZE; - int firsty = yy * VIDEO_LINE_LEN; - int lasty = (yy + VIDEO_FONT_HEIGHT) * VIDEO_LINE_LEN; - int x, y; - for (y = firsty; y < lasty; y += VIDEO_LINE_LEN) { - for (x = firstx; x < lastx; x++) { - u8 *dest = (u8 *)(video_fb_address) + x + y; - *dest = ~*dest; - } - } -} - -void console_cursor(int state) -{ - if (cursor_state != state) { - if (cursor_state) { - /* turn off the cursor */ - video_invertchar(old_col * VIDEO_FONT_WIDTH, - old_row * VIDEO_FONT_HEIGHT + - video_logo_height); - } else { - /* turn off the cursor and record where it is */ - video_invertchar(console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT + - video_logo_height); - old_col = console_col; - old_row = console_row; - } - cursor_state = state; - } - if (cfb_do_flush_cache) - flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE); -} -#endif - -#ifndef VIDEO_HW_RECTFILL -static void memsetl(int *p, int c, int v) -{ - while (c--) - *(p++) = v; -} -#endif - -#ifndef VIDEO_HW_BITBLT -static void memcpyl(int *d, int *s, int c) -{ - while (c--) - *(d++) = *(s++); -} -#endif - -static void console_clear_line(int line, int begin, int end) -{ -#ifdef VIDEO_HW_RECTFILL - video_hw_rectfill(VIDEO_PIXEL_SIZE, /* bytes per pixel */ - VIDEO_FONT_WIDTH * begin, /* dest pos x */ - video_logo_height + - VIDEO_FONT_HEIGHT * line, /* dest pos y */ - VIDEO_FONT_WIDTH * (end - begin + 1), /* fr. width */ - VIDEO_FONT_HEIGHT, /* frame height */ - bgx /* fill color */ - ); -#else - if (begin == 0 && (end + 1) == CONSOLE_COLS) { - memsetl(CONSOLE_ROW_FIRST + - CONSOLE_ROW_SIZE * line, /* offset of row */ - CONSOLE_ROW_SIZE >> 2, /* length of row */ - bgx /* fill color */ - ); - } else { - void *offset; - int i, size; - - offset = CONSOLE_ROW_FIRST + - CONSOLE_ROW_SIZE * line + /* offset of row */ - VIDEO_FONT_WIDTH * - VIDEO_PIXEL_SIZE * begin; /* offset of col */ - size = VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE * (end - begin + 1); - size >>= 2; /* length to end for memsetl() */ - /* fill at col offset of i'th line using bgx as fill color */ - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) - memsetl(offset + i * VIDEO_LINE_LEN, size, bgx); - } -#endif -} - -static void console_scrollup(void) -{ - const int rows = CONFIG_CONSOLE_SCROLL_LINES; - int i; - - /* copy up rows ignoring the first one */ - -#ifdef VIDEO_HW_BITBLT - video_hw_bitblt(VIDEO_PIXEL_SIZE, /* bytes per pixel */ - 0, /* source pos x */ - video_logo_height + - VIDEO_FONT_HEIGHT * rows, /* source pos y */ - 0, /* dest pos x */ - video_logo_height, /* dest pos y */ - VIDEO_VISIBLE_COLS, /* frame width */ - VIDEO_VISIBLE_ROWS - - video_logo_height - - VIDEO_FONT_HEIGHT * rows /* frame height */ - ); -#else - memcpyl(CONSOLE_ROW_FIRST, CONSOLE_ROW_FIRST + rows * CONSOLE_ROW_SIZE, - (CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows) >> 2); -#endif - /* clear the last one */ - for (i = 1; i <= rows; i++) - console_clear_line(CONSOLE_ROWS - i, 0, CONSOLE_COLS - 1); - - /* Decrement row number */ - console_row -= rows; -} - -static void console_back(void) -{ - console_col--; - - if (console_col < 0) { - console_col = CONSOLE_COLS - 1; - console_row--; - if (console_row < 0) - console_row = 0; - } -} - -#ifdef CONFIG_CFB_CONSOLE_ANSI - -static void console_clear(void) -{ -#ifdef VIDEO_HW_RECTFILL - video_hw_rectfill(VIDEO_PIXEL_SIZE, /* bytes per pixel */ - 0, /* dest pos x */ - video_logo_height, /* dest pos y */ - VIDEO_VISIBLE_COLS, /* frame width */ - VIDEO_VISIBLE_ROWS, /* frame height */ - bgx /* fill color */ - ); -#else - memsetl(CONSOLE_ROW_FIRST, CONSOLE_SIZE, bgx); -#endif -} - -static void console_cursor_fix(void) -{ - if (console_row < 0) - console_row = 0; - if (console_row >= CONSOLE_ROWS) - console_row = CONSOLE_ROWS - 1; - if (console_col < 0) - console_col = 0; - if (console_col >= CONSOLE_COLS) - console_col = CONSOLE_COLS - 1; -} - -static void console_cursor_up(int n) -{ - console_row -= n; - console_cursor_fix(); -} - -static void console_cursor_down(int n) -{ - console_row += n; - console_cursor_fix(); -} - -static void console_cursor_left(int n) -{ - console_col -= n; - console_cursor_fix(); -} - -static void console_cursor_right(int n) -{ - console_col += n; - console_cursor_fix(); -} - -static void console_cursor_set_position(int row, int col) -{ - if (console_row != -1) - console_row = row; - if (console_col != -1) - console_col = col; - console_cursor_fix(); -} - -static void console_previousline(int n) -{ - /* FIXME: also scroll terminal ? */ - console_row -= n; - console_cursor_fix(); -} - -static void console_swap_colors(void) -{ - eorx = fgx; - fgx = bgx; - bgx = eorx; - eorx = fgx ^ bgx; -} - -static inline int console_cursor_is_visible(void) -{ - return !ansi_cursor_hidden; -} -#else -static inline int console_cursor_is_visible(void) -{ - return 1; -} -#endif - -static void console_newline(int n) -{ - console_row += n; - console_col = 0; - - /* Check if we need to scroll the terminal */ - if (console_row >= CONSOLE_ROWS) { - /* Scroll everything up */ - console_scrollup(); - } -} - -static void console_cr(void) -{ - console_col = 0; -} - -static void parse_putc(const char c) -{ - static int nl = 1; - - if (console_cursor_is_visible()) - CURSOR_OFF; - - switch (c) { - case 13: /* back to first column */ - console_cr(); - break; - - case '\n': /* next line */ - if (console_col || nl) - console_newline(1); - nl = 1; - break; - - case 9: /* tab 8 */ - console_col |= 0x0008; - console_col &= ~0x0007; - - if (console_col >= CONSOLE_COLS) - console_newline(1); - break; - - case 8: /* backspace */ - console_back(); - break; - - case 7: /* bell */ - break; /* ignored */ - - default: /* draw the char */ - video_putchar(console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT, c); - console_col++; - - /* check for newline */ - if (console_col >= CONSOLE_COLS) { - console_newline(1); - nl = 0; - } - } - - if (console_cursor_is_visible()) - CURSOR_SET; -} - -static void cfb_video_putc(struct stdio_dev *dev, const char c) -{ -#ifdef CONFIG_CFB_CONSOLE_ANSI - int i; - - if (c == 27) { - for (i = 0; i < ansi_buf_size; ++i) - parse_putc(ansi_buf[i]); - ansi_buf[0] = 27; - ansi_buf_size = 1; - return; - } - - if (ansi_buf_size > 0) { - /* - * 0 - ESC - * 1 - [ - * 2 - num1 - * 3 - .. - * 4 - ; - * 5 - num2 - * 6 - .. - * - cchar - */ - int next = 0; - - int flush = 0; - int fail = 0; - - int num1 = 0; - int num2 = 0; - int cchar = 0; - - ansi_buf[ansi_buf_size++] = c; - - if (ansi_buf_size >= sizeof(ansi_buf)) - fail = 1; - - for (i = 0; i < ansi_buf_size; ++i) { - if (fail) - break; - - switch (next) { - case 0: - if (ansi_buf[i] == 27) - next = 1; - else - fail = 1; - break; - - case 1: - if (ansi_buf[i] == '[') - next = 2; - else - fail = 1; - break; - - case 2: - if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') { - num1 = ansi_buf[i]-'0'; - next = 3; - } else if (ansi_buf[i] != '?') { - --i; - num1 = 1; - next = 4; - } - break; - - case 3: - if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') { - num1 *= 10; - num1 += ansi_buf[i]-'0'; - } else { - --i; - next = 4; - } - break; - - case 4: - if (ansi_buf[i] != ';') { - --i; - next = 7; - } else - next = 5; - break; - - case 5: - if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') { - num2 = ansi_buf[i]-'0'; - next = 6; - } else - fail = 1; - break; - - case 6: - if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') { - num2 *= 10; - num2 += ansi_buf[i]-'0'; - } else { - --i; - next = 7; - } - break; - - case 7: - if ((ansi_buf[i] >= 'A' && ansi_buf[i] <= 'H') - || ansi_buf[i] == 'J' - || ansi_buf[i] == 'K' - || ansi_buf[i] == 'h' - || ansi_buf[i] == 'l' - || ansi_buf[i] == 'm') { - cchar = ansi_buf[i]; - flush = 1; - } else - fail = 1; - break; - } - } - - if (fail) { - for (i = 0; i < ansi_buf_size; ++i) - parse_putc(ansi_buf[i]); - ansi_buf_size = 0; - return; - } - - if (flush) { - if (!ansi_cursor_hidden) - CURSOR_OFF; - ansi_buf_size = 0; - switch (cchar) { - case 'A': - /* move cursor num1 rows up */ - console_cursor_up(num1); - break; - case 'B': - /* move cursor num1 rows down */ - console_cursor_down(num1); - break; - case 'C': - /* move cursor num1 columns forward */ - console_cursor_right(num1); - break; - case 'D': - /* move cursor num1 columns back */ - console_cursor_left(num1); - break; - case 'E': - /* move cursor num1 rows up at begin of row */ - console_previousline(num1); - break; - case 'F': - /* move cursor num1 rows down at begin of row */ - console_newline(num1); - break; - case 'G': - /* move cursor to column num1 */ - console_cursor_set_position(-1, num1-1); - break; - case 'H': - /* move cursor to row num1, column num2 */ - console_cursor_set_position(num1-1, num2-1); - break; - case 'J': - /* clear console and move cursor to 0, 0 */ - console_clear(); - console_cursor_set_position(0, 0); - break; - case 'K': - /* clear line */ - if (num1 == 0) - console_clear_line(console_row, - console_col, - CONSOLE_COLS-1); - else if (num1 == 1) - console_clear_line(console_row, - 0, console_col); - else - console_clear_line(console_row, - 0, CONSOLE_COLS-1); - break; - case 'h': - ansi_cursor_hidden = 0; - break; - case 'l': - ansi_cursor_hidden = 1; - break; - case 'm': - if (num1 == 0) { /* reset swapped colors */ - if (ansi_colors_need_revert) { - console_swap_colors(); - ansi_colors_need_revert = 0; - } - } else if (num1 == 7) { /* once swap colors */ - if (!ansi_colors_need_revert) { - console_swap_colors(); - ansi_colors_need_revert = 1; - } - } - break; - } - if (!ansi_cursor_hidden) - CURSOR_SET; - } - } else { - parse_putc(c); - } -#else - parse_putc(c); -#endif - if (cfb_do_flush_cache) - flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE); -} - -static void cfb_video_puts(struct stdio_dev *dev, const char *s) -{ - int flush = cfb_do_flush_cache; - int count = strlen(s); - - /* temporarily disable cache flush */ - cfb_do_flush_cache = 0; - - while (count--) - cfb_video_putc(dev, *s++); - - if (flush) { - cfb_do_flush_cache = flush; - flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE); - } -} - -/* - * Do not enforce drivers (or board code) to provide empty - * video_set_lut() if they do not support 8 bpp format. - * Implement weak default function instead. - */ -__weak void video_set_lut(unsigned int index, unsigned char r, - unsigned char g, unsigned char b) -{ -} - -#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) - -#define FILL_8BIT_332RGB(r,g,b) { \ - *fb = ((r>>5)<<5) | ((g>>5)<<2) | (b>>6); \ - fb ++; \ -} - -#define FILL_15BIT_555RGB(r,g,b) { \ - *(unsigned short *)fb = \ - SWAP16((unsigned short)(((r>>3)<<10) | \ - ((g>>3)<<5) | \ - (b>>3))); \ - fb += 2; \ -} - -#define FILL_16BIT_565RGB(r,g,b) { \ - *(unsigned short *)fb = \ - SWAP16((unsigned short)((((r)>>3)<<11)| \ - (((g)>>2)<<5) | \ - ((b)>>3))); \ - fb += 2; \ -} - -#define FILL_32BIT_X888RGB(r,g,b) { \ - *(u32 *)fb = \ - SWAP32((unsigned int)(((r<<16) | \ - (g<<8) | \ - b))); \ - fb += 4; \ -} - -#ifdef VIDEO_FB_LITTLE_ENDIAN -#define FILL_24BIT_888RGB(r,g,b) { \ - fb[0] = b; \ - fb[1] = g; \ - fb[2] = r; \ - fb += 3; \ -} -#else -#define FILL_24BIT_888RGB(r,g,b) { \ - fb[0] = r; \ - fb[1] = g; \ - fb[2] = b; \ - fb += 3; \ -} -#endif - -#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) -static inline void fill_555rgb_pswap(uchar *fb, int x, u8 r, u8 g, u8 b) -{ - ushort *dst = (ushort *) fb; - ushort color = (ushort) (((r >> 3) << 10) | - ((g >> 3) << 5) | - (b >> 3)); - if (x & 1) - *(--dst) = color; - else - *(++dst) = color; -} -#endif - -/* - * RLE8 bitmap support - */ - -#ifdef CONFIG_VIDEO_BMP_RLE8 -/* Pre-calculated color table entry */ -struct palette { - union { - unsigned short w; /* word */ - unsigned int dw; /* double word */ - } ce; /* color entry */ -}; - -/* - * Helper to draw encoded/unencoded run. - */ -static void draw_bitmap(uchar **fb, uchar *bm, struct palette *p, - int cnt, int enc) -{ - ulong addr = (ulong) *fb; - int *off; - int enc_off = 1; - int i; - - /* - * Setup offset of the color index in the bitmap. - * Color index of encoded run is at offset 1. - */ - off = enc ? &enc_off : &i; - - switch (VIDEO_DATA_FORMAT) { - case GDF__8BIT_INDEX: - for (i = 0; i < cnt; i++) - *(unsigned char *) addr++ = bm[*off]; - break; - case GDF_15BIT_555RGB: - case GDF_16BIT_565RGB: - /* differences handled while pre-calculating palette */ - for (i = 0; i < cnt; i++) { - *(unsigned short *) addr = p[bm[*off]].ce.w; - addr += 2; - } - break; - case GDF_32BIT_X888RGB: - for (i = 0; i < cnt; i++) { - *(u32 *) addr = p[bm[*off]].ce.dw; - addr += 4; - } - break; - } - *fb = (uchar *) addr; /* return modified address */ -} - -static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff, - int width, int height) -{ - unsigned char *bm; - unsigned char *fbp; - unsigned int cnt, runlen; - int decode = 1; - int x, y, bpp, i, ncolors; - struct palette p[256]; - struct bmp_color_table_entry cte; - int green_shift, red_off; - int limit = (VIDEO_LINE_LEN / VIDEO_PIXEL_SIZE) * VIDEO_ROWS; - int pixels = 0; - - x = 0; - y = __le32_to_cpu(img->header.height) - 1; - ncolors = __le32_to_cpu(img->header.colors_used); - bpp = VIDEO_PIXEL_SIZE; - fbp = (unsigned char *) ((unsigned int) video_fb_address + - (y + yoff) * VIDEO_LINE_LEN + - xoff * bpp); - - bm = (uchar *) img + __le32_to_cpu(img->header.data_offset); - - /* pre-calculate and setup palette */ - switch (VIDEO_DATA_FORMAT) { - case GDF__8BIT_INDEX: - for (i = 0; i < ncolors; i++) { - cte = img->color_table[i]; - video_set_lut(i, cte.red, cte.green, cte.blue); - } - break; - case GDF_15BIT_555RGB: - case GDF_16BIT_565RGB: - if (VIDEO_DATA_FORMAT == GDF_15BIT_555RGB) { - green_shift = 3; - red_off = 10; - } else { - green_shift = 2; - red_off = 11; - } - for (i = 0; i < ncolors; i++) { - cte = img->color_table[i]; - p[i].ce.w = SWAP16((unsigned short) - (((cte.red >> 3) << red_off) | - ((cte.green >> green_shift) << 5) | - cte.blue >> 3)); - } - break; - case GDF_32BIT_X888RGB: - for (i = 0; i < ncolors; i++) { - cte = img->color_table[i]; - p[i].ce.dw = SWAP32((cte.red << 16) | - (cte.green << 8) | - cte.blue); - } - break; - default: - printf("RLE Bitmap unsupported in video mode 0x%x\n", - VIDEO_DATA_FORMAT); - return -1; - } - - while (decode) { - switch (bm[0]) { - case 0: - switch (bm[1]) { - case 0: - /* scan line end marker */ - bm += 2; - x = 0; - y--; - fbp = (unsigned char *) - ((unsigned int) video_fb_address + - (y + yoff) * VIDEO_LINE_LEN + - xoff * bpp); - continue; - case 1: - /* end of bitmap data marker */ - decode = 0; - break; - case 2: - /* run offset marker */ - x += bm[2]; - y -= bm[3]; - fbp = (unsigned char *) - ((unsigned int) video_fb_address + - (y + yoff) * VIDEO_LINE_LEN + - xoff * bpp); - bm += 4; - break; - default: - /* unencoded run */ - cnt = bm[1]; - runlen = cnt; - pixels += cnt; - if (pixels > limit) - goto error; - - bm += 2; - if (y < height) { - if (x >= width) { - x += runlen; - goto next_run; - } - if (x + runlen > width) - cnt = width - x; - draw_bitmap(&fbp, bm, p, cnt, 0); - x += runlen; - } -next_run: - bm += runlen; - if (runlen & 1) - bm++; /* 0 padding if length is odd */ - } - break; - default: - /* encoded run */ - cnt = bm[0]; - runlen = cnt; - pixels += cnt; - if (pixels > limit) - goto error; - - if (y < height) { /* only draw into visible area */ - if (x >= width) { - x += runlen; - bm += 2; - continue; - } - if (x + runlen > width) - cnt = width - x; - draw_bitmap(&fbp, bm, p, cnt, 1); - x += runlen; - } - bm += 2; - break; - } - } - - if (cfb_do_flush_cache) - flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE); - - return 0; -error: - printf("Error: Too much encoded pixel data, validate your bitmap\n"); - return -1; -} -#endif - -/* - * Display the BMP file located at address bmp_image. - */ -int video_display_bitmap(ulong bmp_image, int x, int y) -{ - ushort xcount, ycount; - uchar *fb; - struct bmp_image *bmp = (struct bmp_image *)bmp_image; - uchar *bmap; - ushort padded_line; - unsigned long width, height, bpp; - unsigned colors; - unsigned long compression; - struct bmp_color_table_entry cte; - -#ifdef CONFIG_VIDEO_BMP_GZIP - unsigned char *dst = NULL; - ulong len; -#endif - - WATCHDOG_RESET(); - - if (!((bmp->header.signature[0] == 'B') && - (bmp->header.signature[1] == 'M'))) { - -#ifdef CONFIG_VIDEO_BMP_GZIP - /* - * Could be a gzipped bmp image, try to decrompress... - */ - len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE; - dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE); - if (dst == NULL) { - printf("Error: malloc in gunzip failed!\n"); - return 1; - } - /* - * NB: we need to force offset of +2 - * See doc/README.displaying-bmps - */ - if (gunzip(dst+2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE-2, - (uchar *) bmp_image, - &len) != 0) { - printf("Error: no valid bmp or bmp.gz image at %lx\n", - bmp_image); - free(dst); - return 1; - } - if (len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) { - printf("Image could be truncated " - "(increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n"); - } - - /* - * Set addr to decompressed image - */ - bmp = (struct bmp_image *)(dst+2); - - if (!((bmp->header.signature[0] == 'B') && - (bmp->header.signature[1] == 'M'))) { - printf("Error: no valid bmp.gz image at %lx\n", - bmp_image); - free(dst); - return 1; - } -#else - printf("Error: no valid bmp image at %lx\n", bmp_image); - return 1; -#endif /* CONFIG_VIDEO_BMP_GZIP */ - } - - width = le32_to_cpu(bmp->header.width); - height = le32_to_cpu(bmp->header.height); - bpp = le16_to_cpu(bmp->header.bit_count); - colors = le32_to_cpu(bmp->header.colors_used); - compression = le32_to_cpu(bmp->header.compression); - - debug("Display-bmp: %ld x %ld with %d colors\n", - width, height, colors); - - if (compression != BMP_BI_RGB -#ifdef CONFIG_VIDEO_BMP_RLE8 - && compression != BMP_BI_RLE8 -#endif - ) { - printf("Error: compression type %ld not supported\n", - compression); -#ifdef CONFIG_VIDEO_BMP_GZIP - if (dst) - free(dst); -#endif - return 1; - } - - padded_line = (((width * bpp + 7) / 8) + 3) & ~0x3; - -#ifdef CONFIG_SPLASH_SCREEN_ALIGN - if (x == BMP_ALIGN_CENTER) - x = max(0, (int)(VIDEO_VISIBLE_COLS - width) / 2); - else if (x < 0) - x = max(0, (int)(VIDEO_VISIBLE_COLS - width + x + 1)); - - if (y == BMP_ALIGN_CENTER) - y = max(0, (int)(VIDEO_VISIBLE_ROWS - height) / 2); - else if (y < 0) - y = max(0, (int)(VIDEO_VISIBLE_ROWS - height + y + 1)); -#endif /* CONFIG_SPLASH_SCREEN_ALIGN */ - - /* - * Just ignore elements which are completely beyond screen - * dimensions. - */ - if ((x >= VIDEO_VISIBLE_COLS) || (y >= VIDEO_VISIBLE_ROWS)) - return 0; - - if ((x + width) > VIDEO_VISIBLE_COLS) - width = VIDEO_VISIBLE_COLS - x; - if ((y + height) > VIDEO_VISIBLE_ROWS) - height = VIDEO_VISIBLE_ROWS - y; - - bmap = (uchar *) bmp + le32_to_cpu(bmp->header.data_offset); - fb = (uchar *) (video_fb_address + - ((y + height - 1) * VIDEO_LINE_LEN) + - x * VIDEO_PIXEL_SIZE); - -#ifdef CONFIG_VIDEO_BMP_RLE8 - if (compression == BMP_BI_RLE8) { - return display_rle8_bitmap(bmp, x, y, width, height); - } -#endif - - /* We handle only 4, 8, or 24 bpp bitmaps */ - switch (le16_to_cpu(bmp->header.bit_count)) { - case 4: - padded_line -= width / 2; - ycount = height; - - switch (VIDEO_DATA_FORMAT) { - case GDF_32BIT_X888RGB: - while (ycount--) { - WATCHDOG_RESET(); - /* - * Don't assume that 'width' is an - * even number - */ - for (xcount = 0; xcount < width; xcount++) { - uchar idx; - - if (xcount & 1) { - idx = *bmap & 0xF; - bmap++; - } else - idx = *bmap >> 4; - cte = bmp->color_table[idx]; - FILL_32BIT_X888RGB(cte.red, cte.green, - cte.blue); - } - bmap += padded_line; - fb -= VIDEO_LINE_LEN + width * - VIDEO_PIXEL_SIZE; - } - break; - default: - puts("4bpp bitmap unsupported with current " - "video mode\n"); - break; - } - break; - - case 8: - padded_line -= width; - if (VIDEO_DATA_FORMAT == GDF__8BIT_INDEX) { - /* Copy colormap */ - for (xcount = 0; xcount < colors; ++xcount) { - cte = bmp->color_table[xcount]; - video_set_lut(xcount, cte.red, cte.green, - cte.blue); - } - } - ycount = height; - switch (VIDEO_DATA_FORMAT) { - case GDF__8BIT_INDEX: - while (ycount--) { - WATCHDOG_RESET(); - xcount = width; - while (xcount--) { - *fb++ = *bmap++; - } - bmap += padded_line; - fb -= VIDEO_LINE_LEN + width * - VIDEO_PIXEL_SIZE; - } - break; - case GDF__8BIT_332RGB: - while (ycount--) { - WATCHDOG_RESET(); - xcount = width; - while (xcount--) { - cte = bmp->color_table[*bmap++]; - FILL_8BIT_332RGB(cte.red, cte.green, - cte.blue); - } - bmap += padded_line; - fb -= VIDEO_LINE_LEN + width * - VIDEO_PIXEL_SIZE; - } - break; - case GDF_15BIT_555RGB: - while (ycount--) { -#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) - int xpos = x; -#endif - WATCHDOG_RESET(); - xcount = width; - while (xcount--) { - cte = bmp->color_table[*bmap++]; -#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) - fill_555rgb_pswap(fb, xpos++, cte.red, - cte.green, - cte.blue); - fb += 2; -#else - FILL_15BIT_555RGB(cte.red, cte.green, - cte.blue); -#endif - } - bmap += padded_line; - fb -= VIDEO_LINE_LEN + width * - VIDEO_PIXEL_SIZE; - } - break; - case GDF_16BIT_565RGB: - while (ycount--) { - WATCHDOG_RESET(); - xcount = width; - while (xcount--) { - cte = bmp->color_table[*bmap++]; - FILL_16BIT_565RGB(cte.red, cte.green, - cte.blue); - } - bmap += padded_line; - fb -= VIDEO_LINE_LEN + width * - VIDEO_PIXEL_SIZE; - } - break; - case GDF_32BIT_X888RGB: - while (ycount--) { - WATCHDOG_RESET(); - xcount = width; - while (xcount--) { - cte = bmp->color_table[*bmap++]; - FILL_32BIT_X888RGB(cte.red, cte.green, - cte.blue); - } - bmap += padded_line; - fb -= VIDEO_LINE_LEN + width * - VIDEO_PIXEL_SIZE; - } - break; - case GDF_24BIT_888RGB: - while (ycount--) { - WATCHDOG_RESET(); - xcount = width; - while (xcount--) { - cte = bmp->color_table[*bmap++]; - FILL_24BIT_888RGB(cte.red, cte.green, - cte.blue); - } - bmap += padded_line; - fb -= VIDEO_LINE_LEN + width * - VIDEO_PIXEL_SIZE; - } - break; - } - break; - case 24: - padded_line -= 3 * width; - ycount = height; - switch (VIDEO_DATA_FORMAT) { - case GDF__8BIT_332RGB: - while (ycount--) { - WATCHDOG_RESET(); - xcount = width; - while (xcount--) { - FILL_8BIT_332RGB(bmap[2], bmap[1], - bmap[0]); - bmap += 3; - } - bmap += padded_line; - fb -= VIDEO_LINE_LEN + width * - VIDEO_PIXEL_SIZE; - } - break; - case GDF_15BIT_555RGB: - while (ycount--) { -#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) - int xpos = x; -#endif - WATCHDOG_RESET(); - xcount = width; - while (xcount--) { -#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) - fill_555rgb_pswap(fb, xpos++, bmap[2], - bmap[1], bmap[0]); - fb += 2; -#else - FILL_15BIT_555RGB(bmap[2], bmap[1], - bmap[0]); -#endif - bmap += 3; - } - bmap += padded_line; - fb -= VIDEO_LINE_LEN + width * - VIDEO_PIXEL_SIZE; - } - break; - case GDF_16BIT_565RGB: - while (ycount--) { - WATCHDOG_RESET(); - xcount = width; - while (xcount--) { - FILL_16BIT_565RGB(bmap[2], bmap[1], - bmap[0]); - bmap += 3; - } - bmap += padded_line; - fb -= VIDEO_LINE_LEN + width * - VIDEO_PIXEL_SIZE; - } - break; - case GDF_32BIT_X888RGB: - while (ycount--) { - WATCHDOG_RESET(); - xcount = width; - while (xcount--) { - FILL_32BIT_X888RGB(bmap[2], bmap[1], - bmap[0]); - bmap += 3; - } - bmap += padded_line; - fb -= VIDEO_LINE_LEN + width * - VIDEO_PIXEL_SIZE; - } - break; - case GDF_24BIT_888RGB: - while (ycount--) { - WATCHDOG_RESET(); - xcount = width; - while (xcount--) { - FILL_24BIT_888RGB(bmap[2], bmap[1], - bmap[0]); - bmap += 3; - } - bmap += padded_line; - fb -= VIDEO_LINE_LEN + width * - VIDEO_PIXEL_SIZE; - } - break; - default: - printf("Error: 24 bits/pixel bitmap incompatible " - "with current video mode\n"); - break; - } - break; - default: - printf("Error: %d bit/pixel bitmaps not supported by U-Boot\n", - le16_to_cpu(bmp->header.bit_count)); - break; - } - -#ifdef CONFIG_VIDEO_BMP_GZIP - if (dst) { - free(dst); - } -#endif - - if (cfb_do_flush_cache) - flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE); - return (0); -} -#endif - -static int cfb_fb_is_in_dram(void) -{ - struct bd_info *bd = gd->bd; - ulong start, end; - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - start = bd->bi_dram[i].start; - end = bd->bi_dram[i].start + bd->bi_dram[i].size - 1; - if ((ulong)video_fb_address >= start && - (ulong)video_fb_address < end) - return 1; - } - - return 0; -} - -void video_clear(void) -{ - if (!video_fb_address) - return; -#ifdef VIDEO_HW_RECTFILL - video_hw_rectfill(VIDEO_PIXEL_SIZE, /* bytes per pixel */ - 0, /* dest pos x */ - 0, /* dest pos y */ - VIDEO_VISIBLE_COLS, /* frame width */ - VIDEO_VISIBLE_ROWS, /* frame height */ - bgx /* fill color */ - ); -#else - memsetl(video_fb_address, - (VIDEO_VISIBLE_ROWS * VIDEO_LINE_LEN) / sizeof(int), bgx); -#endif -} - -static int cfg_video_init(void) -{ - unsigned char color8; - - pGD = video_hw_init(); - if (pGD == NULL) - return -1; - - video_fb_address = (void *) VIDEO_FB_ADRS; - - cfb_do_flush_cache = cfb_fb_is_in_dram() && dcache_status(); - - /* Init drawing pats */ - switch (VIDEO_DATA_FORMAT) { - case GDF__8BIT_INDEX: - video_set_lut(0x01, CONFIG_SYS_CONSOLE_FG_COL, - CONFIG_SYS_CONSOLE_FG_COL, - CONFIG_SYS_CONSOLE_FG_COL); - video_set_lut(0x00, CONFIG_SYS_CONSOLE_BG_COL, - CONFIG_SYS_CONSOLE_BG_COL, - CONFIG_SYS_CONSOLE_BG_COL); - fgx = 0x01010101; - bgx = 0x00000000; - break; - case GDF__8BIT_332RGB: - color8 = ((CONFIG_SYS_CONSOLE_FG_COL & 0xe0) | - ((CONFIG_SYS_CONSOLE_FG_COL >> 3) & 0x1c) | - CONFIG_SYS_CONSOLE_FG_COL >> 6); - fgx = (color8 << 24) | (color8 << 16) | (color8 << 8) | - color8; - color8 = ((CONFIG_SYS_CONSOLE_BG_COL & 0xe0) | - ((CONFIG_SYS_CONSOLE_BG_COL >> 3) & 0x1c) | - CONFIG_SYS_CONSOLE_BG_COL >> 6); - bgx = (color8 << 24) | (color8 << 16) | (color8 << 8) | - color8; - break; - case GDF_15BIT_555RGB: - fgx = (((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 26) | - ((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 21) | - ((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 16) | - ((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 10) | - ((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 5) | - (CONFIG_SYS_CONSOLE_FG_COL >> 3)); - bgx = (((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 26) | - ((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 21) | - ((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 16) | - ((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 10) | - ((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 5) | - (CONFIG_SYS_CONSOLE_BG_COL >> 3)); - break; - case GDF_16BIT_565RGB: - fgx = (((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 27) | - ((CONFIG_SYS_CONSOLE_FG_COL >> 2) << 21) | - ((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 16) | - ((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 11) | - ((CONFIG_SYS_CONSOLE_FG_COL >> 2) << 5) | - (CONFIG_SYS_CONSOLE_FG_COL >> 3)); - bgx = (((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 27) | - ((CONFIG_SYS_CONSOLE_BG_COL >> 2) << 21) | - ((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 16) | - ((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 11) | - ((CONFIG_SYS_CONSOLE_BG_COL >> 2) << 5) | - (CONFIG_SYS_CONSOLE_BG_COL >> 3)); - break; - case GDF_32BIT_X888RGB: - fgx = (CONFIG_SYS_CONSOLE_FG_COL << 16) | - (CONFIG_SYS_CONSOLE_FG_COL << 8) | - CONFIG_SYS_CONSOLE_FG_COL; - bgx = (CONFIG_SYS_CONSOLE_BG_COL << 16) | - (CONFIG_SYS_CONSOLE_BG_COL << 8) | - CONFIG_SYS_CONSOLE_BG_COL; - break; - case GDF_24BIT_888RGB: - fgx = (CONFIG_SYS_CONSOLE_FG_COL << 24) | - (CONFIG_SYS_CONSOLE_FG_COL << 16) | - (CONFIG_SYS_CONSOLE_FG_COL << 8) | - CONFIG_SYS_CONSOLE_FG_COL; - bgx = (CONFIG_SYS_CONSOLE_BG_COL << 24) | - (CONFIG_SYS_CONSOLE_BG_COL << 16) | - (CONFIG_SYS_CONSOLE_BG_COL << 8) | - CONFIG_SYS_CONSOLE_BG_COL; - break; - } - eorx = fgx ^ bgx; - - if (!CONFIG_IS_ENABLED(NO_FB_CLEAR)) - video_clear(); - -#ifdef CONFIG_VIDEO_LOGO - /* Plot the logo and get start point of console */ - debug("Video: Drawing the logo ...\n"); - video_console_address = video_logo(); -#else - video_console_address = video_fb_address; -#endif - - /* Initialize the console */ - console_col = 0; - console_row = 0; - - if (cfb_do_flush_cache) - flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE); - - return 0; -} - -/* - * Implement a weak default function for boards that optionally - * need to skip the video initialization. - */ -__weak int board_video_skip(void) -{ - /* As default, don't skip test */ - return 0; -} - -int drv_video_init(void) -{ - struct stdio_dev console_dev; - bool have_keyboard; - bool __maybe_unused keyboard_ok = false; - - /* Check if video initialization should be skipped */ - if (board_video_skip()) - return 0; - - /* Init video chip - returns with framebuffer cleared */ - if (cfg_video_init() == -1) - return 0; - - if (board_cfb_skip()) - return 0; - -#if defined(CONFIG_VGA_AS_SINGLE_DEVICE) - have_keyboard = false; -#elif defined(CONFIG_OF_CONTROL) - have_keyboard = !ofnode_conf_read_bool("u-boot,no-keyboard"); -#else - have_keyboard = true; -#endif - if (have_keyboard) { - debug("KBD: Keyboard init ...\n"); -#if !defined(CONFIG_VGA_AS_SINGLE_DEVICE) - keyboard_ok = !(VIDEO_KBD_INIT_FCT == -1); -#endif - } - - /* Init vga device */ - memset(&console_dev, 0, sizeof(console_dev)); - strcpy(console_dev.name, "vga"); - console_dev.flags = DEV_FLAGS_OUTPUT; - console_dev.putc = cfb_video_putc; /* 'putc' function */ - console_dev.puts = cfb_video_puts; /* 'puts' function */ - -#if !defined(CONFIG_VGA_AS_SINGLE_DEVICE) - if (have_keyboard && keyboard_ok) { - /* Also init console device */ - console_dev.flags |= DEV_FLAGS_INPUT; - console_dev.tstc = VIDEO_TSTC_FCT; /* 'tstc' function */ - console_dev.getc = VIDEO_GETC_FCT; /* 'getc' function */ - } -#endif - - if (stdio_register(&console_dev) != 0) - return 0; - - /* Return success */ - return 1; -} - -void video_position_cursor(unsigned col, unsigned row) -{ - console_col = min(col, CONSOLE_COLS - 1); - console_row = min(row, CONSOLE_ROWS - 1); -} - -int video_get_pixel_width(void) -{ - return VIDEO_VISIBLE_COLS; -} - -int video_get_pixel_height(void) -{ - return VIDEO_VISIBLE_ROWS; -} - -int video_get_screen_rows(void) -{ - return CONSOLE_ROWS; -} - -int video_get_screen_columns(void) -{ - return CONSOLE_COLS; -} diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c index 6efba122e78..dbd1408b6cf 100644 --- a/drivers/video/omap3_dss.c +++ b/drivers/video/omap3_dss.c @@ -137,31 +137,3 @@ void omap3_dss_enable(void) l |= LCD_ENABLE | GO_LCD | DIG_ENABLE | GO_DIG | GP_OUT0 | GP_OUT1; writel(l, &dispc->control); } - -#ifdef CONFIG_CFB_CONSOLE -int __board_video_init(void) -{ - return -1; -} - -int board_video_init(void) - __attribute__((weak, alias("__board_video_init"))); - -void *video_hw_init(void) -{ - static GraphicDevice dssfb; - GraphicDevice *pGD = &dssfb; - struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; - - if (board_video_init() || !readl(&dispc->gfx_ba0)) - return NULL; - - pGD->winSizeX = (readl(&dispc->size_lcd) & 0x7FF) + 1; - pGD->winSizeY = ((readl(&dispc->size_lcd) >> 16) & 0x7FF) + 1; - pGD->gdfBytesPP = 4; - pGD->gdfIndex = GDF_32BIT_X888RGB; - pGD->frameAdrs = readl(&dispc->gfx_ba0); - - return pGD; -} -#endif -- cgit v1.3.1 From 9b39da6e42815ebda9505138017f7396625a1c6e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 23 Jan 2022 07:04:05 -0700 Subject: video: nexell: Drop unused and invalid code Unfortunately this driver uses the old video structure to store things. This is not supported with driver model. Drop the old code and comment out the other pieces, so the maintainer can take a look. Signed-off-by: Simon Glass --- arch/arm/mach-nexell/include/mach/display_dev.h | 4 ++-- drivers/video/nexell_display.c | 14 +++----------- 2 files changed, 5 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/arch/arm/mach-nexell/include/mach/display_dev.h b/arch/arm/mach-nexell/include/mach/display_dev.h index 77eb614768c..0dd96f67957 100644 --- a/arch/arm/mach-nexell/include/mach/display_dev.h +++ b/arch/arm/mach-nexell/include/mach/display_dev.h @@ -15,8 +15,8 @@ #endif struct nx_display_dev { -#if defined CONFIG_VIDEO || defined CONFIG_DM_VIDEO - GraphicDevice graphic_device; +#if defined CONFIG_DM_VIDEO + /* GraphicDevice graphic_device; -- not defined anymore */ #elif defined CONFIG_LCD vidinfo_t *panel_info; #endif diff --git a/drivers/video/nexell_display.c b/drivers/video/nexell_display.c index c7621ef49c5..a0bd44c8b84 100644 --- a/drivers/video/nexell_display.c +++ b/drivers/video/nexell_display.c @@ -537,7 +537,6 @@ static int nx_display_probe(struct udevice *dev) struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct nx_display_plat *plat = dev_get_plat(dev); - static GraphicDevice *graphic_device; char addr[64]; debug("%s()\n", __func__); @@ -564,7 +563,7 @@ static int nx_display_probe(struct udevice *dev) } struct nx_display_dev *dp; - unsigned int pp_index = 0; + /* unsigned int pp_index = 0; */ dp = nx_display_setup(); if (!dp) { @@ -574,6 +573,7 @@ static int nx_display_probe(struct udevice *dev) } switch (dp->depth) { +#if 0 /* GDF_16BIT_565RGB is not defined in video.h */ case 2: pp_index = GDF_16BIT_565RGB; uc_priv->bpix = VIDEO_BPP16; @@ -586,6 +586,7 @@ static int nx_display_probe(struct udevice *dev) pp_index = GDF_32BIT_X888RGB; uc_priv->bpix = VIDEO_BPP32; break; +#endif default: printf("fail : not support LCD bit per pixel %d\n", dp->depth * 8); @@ -596,15 +597,6 @@ static int nx_display_probe(struct udevice *dev) uc_priv->ysize = dp->fb_plane->height; uc_priv->rot = 0; - graphic_device = &dp->graphic_device; - graphic_device->frameAdrs = dp->fb_addr; - graphic_device->gdfIndex = pp_index; - graphic_device->gdfBytesPP = dp->depth; - graphic_device->winSizeX = dp->fb_plane->width; - graphic_device->winSizeY = dp->fb_plane->height; - graphic_device->plnSizeX = - graphic_device->winSizeX * graphic_device->gdfBytesPP; - /* * set environment variable "fb_addr" (frame buffer address), required * for splash image. Because drv_video_init() in common/stdio.c is only -- cgit v1.3.1 From fff49e01d800decb9a653d228077c5b7fec58ddb Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 23 Jan 2022 07:04:06 -0700 Subject: video: Drop video_fb header This is not used now. Drop it. Signed-off-by: Simon Glass --- arch/arm/mach-nexell/include/mach/display_dev.h | 1 - board/aristainetos/aristainetos.c | 1 - board/freescale/t104xrdb/diu.c | 1 - board/socrates/socrates.c | 1 - drivers/pci/pci_rom.c | 1 - drivers/video/da8xx-fb.c | 1 - drivers/video/fsl_dcu_fb.c | 1 - drivers/video/fsl_diu_fb.c | 1 - drivers/video/imx/mxc_ipuv3_fb.c | 1 - drivers/video/mxsfb.c | 1 - drivers/video/nexell_display.c | 1 - drivers/video/omap3_dss.c | 1 - drivers/video/sunxi/sunxi_display.c | 1 - include/video_fb.h | 91 ------------------------- 14 files changed, 104 deletions(-) delete mode 100644 include/video_fb.h (limited to 'drivers') diff --git a/arch/arm/mach-nexell/include/mach/display_dev.h b/arch/arm/mach-nexell/include/mach/display_dev.h index 0dd96f67957..ffa45518d99 100644 --- a/arch/arm/mach-nexell/include/mach/display_dev.h +++ b/arch/arm/mach-nexell/include/mach/display_dev.h @@ -9,7 +9,6 @@ #define _NX__DISPLAY_DEV_H_ #if defined CONFIG_VIDEO || defined CONFIG_DM_VIDEO -#include #elif defined CONFIG_LCD #include #endif diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index f13fa116374..19af59606da 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -39,7 +39,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/t104xrdb/diu.c b/board/freescale/t104xrdb/diu.c index 25c8597202a..022d329713e 100644 --- a/board/freescale/t104xrdb/diu.c +++ b/board/freescale/t104xrdb/diu.c @@ -10,7 +10,6 @@ #include #include #include -#include #include "../common/diu_ch7301.h" diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index f6a3cc1793c..3430a1ed017 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -26,7 +26,6 @@ #include #include #include -#include #include "upm_table.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index f8b193058a3..73d15e797fc 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c index 462c318126d..db9a820377d 100644 --- a/drivers/video/da8xx-fb.c +++ b/drivers/video/da8xx-fb.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c index dc5b24c98bb..b8bd4727c96 100644 --- a/drivers/video/fsl_dcu_fb.c +++ b/drivers/video/fsl_dcu_fb.c @@ -17,7 +17,6 @@ #include #include #include -#include #include "videomodes.h" /* Convert the X,Y resolution pair into a single number */ diff --git a/drivers/video/fsl_diu_fb.c b/drivers/video/fsl_diu_fb.c index 2c21e293a2c..6e335b5f43d 100644 --- a/drivers/video/fsl_diu_fb.c +++ b/drivers/video/fsl_diu_fb.c @@ -12,7 +12,6 @@ #include #include "videomodes.h" -#include #include #include #include diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c index 98228f2ad67..49bbeefdd8e 100644 --- a/drivers/video/imx/mxc_ipuv3_fb.c +++ b/drivers/video/imx/mxc_ipuv3_fb.c @@ -22,7 +22,6 @@ #include #include #include -#include #include "../videomodes.h" #include "ipu.h" #include "mxcfb.h" diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 5f85c0c3eb7..99a15e0c25d 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include diff --git a/drivers/video/nexell_display.c b/drivers/video/nexell_display.c index a0bd44c8b84..0a9cea680fd 100644 --- a/drivers/video/nexell_display.c +++ b/drivers/video/nexell_display.c @@ -16,7 +16,6 @@ #include #include #include /* For struct video_uc_plat */ -#include #include #include #include diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c index dbd1408b6cf..432b16bfbfe 100644 --- a/drivers/video/omap3_dss.c +++ b/drivers/video/omap3_dss.c @@ -28,7 +28,6 @@ #include #include #include -#include /* Configure VENC for a given Mode (NTSC / PAL) */ void omap3_dss_venc_config(const struct venc_regs *venc_cfg, diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c index 5a21f7af668..2ee6212c58d 100644 --- a/drivers/video/sunxi/sunxi_display.c +++ b/drivers/video/sunxi/sunxi_display.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include "../videomodes.h" #include "../anx9804.h" diff --git a/include/video_fb.h b/include/video_fb.h deleted file mode 100644 index e4102265949..00000000000 --- a/include/video_fb.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 1997-2002 ELTEC Elektronik AG - * Frank Gottschling - */ - -/* - * smiLynxEM.h - * Silicon Motion graphic interface for sm810/sm710/sm712 accelerator - * - * - * modification history - * -------------------- - * 04-18-2002 Rewritten for U-Boot . - */ - -#ifndef _VIDEO_FB_H_ -#define _VIDEO_FB_H_ - -/* - * Graphic Data Format (GDF) bits for VIDEO_DATA_FORMAT - */ -#define GDF__8BIT_INDEX 0 -#define GDF_15BIT_555RGB 1 -#define GDF_16BIT_565RGB 2 -#define GDF_32BIT_X888RGB 3 -#define GDF_24BIT_888RGB 4 -#define GDF__8BIT_332RGB 5 - -/******************************************************************************/ -/* Export Graphic Driver Control */ -/******************************************************************************/ - -typedef struct graphic_device { - unsigned int isaBase; - unsigned int pciBase; - unsigned int dprBase; - unsigned int vprBase; - unsigned int cprBase; - unsigned int frameAdrs; - unsigned int memSize; - unsigned int mode; - unsigned int gdfIndex; - unsigned int gdfBytesPP; - unsigned int fg; - unsigned int bg; - unsigned int plnSizeX; - unsigned int plnSizeY; - unsigned int winSizeX; - unsigned int winSizeY; - char modeIdent[80]; -} GraphicDevice; - - -/******************************************************************************/ -/* Export Graphic Functions */ -/******************************************************************************/ - -void *video_hw_init (void); /* returns GraphicDevice struct or NULL */ - -#ifdef VIDEO_HW_BITBLT -void video_hw_bitblt ( - unsigned int bpp, /* bytes per pixel */ - unsigned int src_x, /* source pos x */ - unsigned int src_y, /* source pos y */ - unsigned int dst_x, /* dest pos x */ - unsigned int dst_y, /* dest pos y */ - unsigned int dim_x, /* frame width */ - unsigned int dim_y /* frame height */ - ); -#endif - -#ifdef VIDEO_HW_RECTFILL -void video_hw_rectfill ( - unsigned int bpp, /* bytes per pixel */ - unsigned int dst_x, /* dest pos x */ - unsigned int dst_y, /* dest pos y */ - unsigned int dim_x, /* frame width */ - unsigned int dim_y, /* frame height */ - unsigned int color /* fill color */ - ); -#endif - -void video_set_lut ( - unsigned int index, /* color number */ - unsigned char r, /* red */ - unsigned char g, /* green */ - unsigned char b /* blue */ - ); - -#endif /*_VIDEO_FB_H_ */ -- cgit v1.3.1 From 1fa43cad862591fe8917a0c1fe2f21f062c7502b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 23 Jan 2022 07:04:08 -0700 Subject: video: Drop references to CONFIG_VIDEO et al Drop the Kconfigs which are not used and all references to them. In particular, this drops CONFIG_VIDEO to avoid confusion and allow us to eventually rename CONFIG_DM_VIDEO to CONFIG_VIDEO. Also drop the prototype for video_get_info_str() which is no-longer used. Signed-off-by: Simon Glass Acked-by: Jason Liu --- README | 3 -- arch/arm/include/asm/mach-imx/mx5_video.h | 5 --- arch/arm/mach-nexell/include/mach/display_dev.h | 7 +--- board/freescale/mx51evk/Makefile | 1 - board/freescale/mx53loco/Makefile | 1 - board/kosagi/novena/novena_spl.c | 23 ---------- cmd/Kconfig | 2 +- cmd/bdinfo.c | 2 +- cmd/bmp.c | 4 +- common/fdt_support.c | 2 +- common/stdio.c | 3 +- drivers/video/Kconfig | 56 +------------------------ drivers/video/nexell_display.c | 8 +--- include/asm-generic/global_data.h | 2 +- include/configs/pxm2.h | 7 ---- include/configs/rut.h | 9 ---- lib/efi_loader/Kconfig | 1 - 17 files changed, 11 insertions(+), 125 deletions(-) (limited to 'drivers') diff --git a/README b/README index 1a413bf3461..138de72ffc6 100644 --- a/README +++ b/README @@ -977,9 +977,6 @@ The following options need to be configured: support, and should also define these other macros: CONFIG_SYS_DIU_ADDR - CONFIG_VIDEO - CONFIG_VIDEO_SW_CURSOR - CONFIG_VGA_AS_SINGLE_DEVICE The DIU driver will look for the 'video-mode' environment variable, and if defined, enable the DIU as a console during diff --git a/arch/arm/include/asm/mach-imx/mx5_video.h b/arch/arm/include/asm/mach-imx/mx5_video.h index dc6aa00c894..b55c0fe8971 100644 --- a/arch/arm/include/asm/mach-imx/mx5_video.h +++ b/arch/arm/include/asm/mach-imx/mx5_video.h @@ -6,12 +6,7 @@ #ifndef __MX5_VIDEO_H #define __MX5_VIDEO_H -#ifdef CONFIG_VIDEO -void lcd_enable(void); -void setup_iomux_lcd(void); -#else static inline void lcd_enable(void) { } static inline void setup_iomux_lcd(void) { } -#endif #endif diff --git a/arch/arm/mach-nexell/include/mach/display_dev.h b/arch/arm/mach-nexell/include/mach/display_dev.h index ffa45518d99..f24fb1739cf 100644 --- a/arch/arm/mach-nexell/include/mach/display_dev.h +++ b/arch/arm/mach-nexell/include/mach/display_dev.h @@ -8,15 +8,12 @@ #ifndef _NX__DISPLAY_DEV_H_ #define _NX__DISPLAY_DEV_H_ -#if defined CONFIG_VIDEO || defined CONFIG_DM_VIDEO -#elif defined CONFIG_LCD +#if !defined(CONFIG_DM_VIDEO) && defined(CONFIG_LCD) #include #endif struct nx_display_dev { -#if defined CONFIG_DM_VIDEO - /* GraphicDevice graphic_device; -- not defined anymore */ -#elif defined CONFIG_LCD +#if !defined(CONFIG_DM_VIDEO) && defined(CONFIG_LCD) vidinfo_t *panel_info; #endif unsigned long base; diff --git a/board/freescale/mx51evk/Makefile b/board/freescale/mx51evk/Makefile index 1a9581cabf9..808e35015e8 100644 --- a/board/freescale/mx51evk/Makefile +++ b/board/freescale/mx51evk/Makefile @@ -5,4 +5,3 @@ # (C) Copyright 2009 Freescale Semiconductor, Inc. obj-y += mx51evk.o -obj-$(CONFIG_VIDEO) += mx51evk_video.o diff --git a/board/freescale/mx53loco/Makefile b/board/freescale/mx53loco/Makefile index d2ebd94dca1..9befe426957 100644 --- a/board/freescale/mx53loco/Makefile +++ b/board/freescale/mx53loco/Makefile @@ -4,4 +4,3 @@ # Jason Liu obj-y += mx53loco.o -obj-$(CONFIG_VIDEO) += mx53loco_video.o diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c index 3d22f2019e9..24c0fb22268 100644 --- a/board/kosagi/novena/novena_spl.c +++ b/board/kosagi/novena/novena_spl.c @@ -379,30 +379,7 @@ static void novena_spl_setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); } -/* - * Video - */ -#ifdef CONFIG_VIDEO -static iomux_v3_cfg_t hdmi_pads[] = { - /* "Ghost HPD" pin */ - MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), - - /* LCD_PWR_CTL */ - MX6_PAD_CSI0_DAT10__GPIO5_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* LCD_BL_ON */ - MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* GPIO_PWM1 */ - MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void novena_spl_setup_iomux_video(void) -{ - imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads)); - gpio_direction_input(NOVENA_HDMI_GHOST_HPD); -} -#else static inline void novena_spl_setup_iomux_video(void) {} -#endif /* * SPL boots from uSDHC card diff --git a/cmd/Kconfig b/cmd/Kconfig index 25c9fde4a7b..1d8401236fb 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1786,7 +1786,7 @@ config CMD_CONITRACE config CMD_CLS bool "Enable clear screen command 'cls'" - depends on CFB_CONSOLE || DM_VIDEO || LCD || VIDEO + depends on DM_VIDEO || LCD || VIDEO default y if LCD help Enable the 'cls' command which clears the screen contents diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index c56b3f4f6ec..37cd8a57ebd 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -117,7 +117,7 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) bdinfo_print_num_l("fdt_size", (ulong)gd->fdt_size); if (IS_ENABLED(CONFIG_DM_VIDEO)) show_video_info(); -#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) +#if defined(CONFIG_LCD) bdinfo_print_num_l("FB base ", gd->fb_base); #endif #if CONFIG_IS_ENABLED(MULTI_DTB_FIT) diff --git a/cmd/bmp.c b/cmd/bmp.c index 071ba90b435..45f4c1296de 100644 --- a/cmd/bmp.c +++ b/cmd/bmp.c @@ -268,10 +268,8 @@ int bmp_display(ulong addr, int x, int y) } #elif defined(CONFIG_LCD) ret = lcd_display_bitmap(addr, x, y); -#elif defined(CONFIG_VIDEO) - ret = video_display_bitmap(addr, x, y); #else -# error bmp_display() requires CONFIG_LCD or CONFIG_VIDEO +# error bmp_display() requires CONFIG_LCD #endif if (bmp_alloc_addr) diff --git a/common/fdt_support.c b/common/fdt_support.c index ea18ea3f045..8662bd27a47 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -1725,7 +1725,7 @@ int fdt_set_status_by_pathf(void *fdt, enum fdt_status status, const char *fmt, return fdt_set_node_status(fdt, offset, status); } -#if defined(CONFIG_VIDEO) || defined(CONFIG_LCD) +#if defined(CONFIG_LCD) int fdt_add_edid(void *blob, const char *compat, unsigned char *edid_buf) { int noff; diff --git a/common/stdio.c b/common/stdio.c index 97f21ea3465..92161a0df87 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -367,8 +367,7 @@ int stdio_add_devices(void) } else { if (IS_ENABLED(CONFIG_LCD)) drv_lcd_init(); - if (IS_ENABLED(CONFIG_VIDEO) || - IS_ENABLED(CONFIG_VIDEO_VCXK)) + if (IS_ENABLED(CONFIG_VIDEO_VCXK)) drv_video_init(); } diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index c8c85c69276..d0745463b9a 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -708,39 +708,9 @@ config VIDEO model. Video drivers typically provide a colour text console and cursor. -config VGA_AS_SINGLE_DEVICE - bool "Set the video as an output-only device" - depends on CFB_CONSOLE - default y - help - If enable the framebuffer device will be initialized as an - output-only device. The Keyboard driver will not be set up. This - may be used if you have no keyboard device, or more than one - (USB Keyboard, AT Keyboard). - -config VIDEO_SW_CURSOR - bool "Enable a software cursor" - depends on CFB_CONSOLE - default y if CFB_CONSOLE - help - This draws a cursor after the last character. No blinking is - provided. This makes it possible to see the current cursor - position when entering text on the console. It is recommended to - enable this. - -config CONSOLE_EXTRA_INFO - bool "Display additional board information" - depends on CFB_CONSOLE - help - Display additional board information strings that normally go to - the serial port. When this option is enabled, a board-specific - function video_get_info_str() is called to get the string for - each line of the display. The function should return the string, - which can be empty if there is nothing to display for that line. - config CONSOLE_SCROLL_LINES int "Number of lines to scroll the console by" - depends on CFB_CONSOLE || DM_VIDEO || LCD + depends on DM_VIDEO || LCD default 1 help When the console need to be scrolled, this is the number of @@ -748,28 +718,6 @@ config CONSOLE_SCROLL_LINES console jump but can help speed up operation when scrolling is slow. -config SYS_CONSOLE_BG_COL - hex "Background colour" - depends on CFB_CONSOLE - default 0x00 - help - Defines the background colour for the console. The value is from - 0x00 to 0xff and the meaning depends on the graphics card. - Typically, 0x00 means black and 0xff means white. Do not set - the background and foreground to the same colour or you will see - nothing. - -config SYS_CONSOLE_FG_COL - hex "Foreground colour" - depends on CFB_CONSOLE - default 0xa0 - help - Defines the foreground colour for the console. The value is from - 0x00 to 0xff and the meaning depends on the graphics card. - Typically, 0x00 means black and 0xff means white. Do not set - the background and foreground to the same colour or you will see - nothing. - config LCD bool "Enable legacy LCD support" help @@ -967,7 +915,7 @@ config VIDEO_BMP_GZIP config VIDEO_BMP_RLE8 bool "Run length encoded BMP image (RLE8) support" - depends on DM_VIDEO || CFB_CONSOLE + depends on DM_VIDEO help If this option is set, the 8-bit RLE compressed BMP images is supported. diff --git a/drivers/video/nexell_display.c b/drivers/video/nexell_display.c index 0a9cea680fd..090fd6ea326 100644 --- a/drivers/video/nexell_display.c +++ b/drivers/video/nexell_display.c @@ -562,7 +562,6 @@ static int nx_display_probe(struct udevice *dev) } struct nx_display_dev *dp; - /* unsigned int pp_index = 0; */ dp = nx_display_setup(); if (!dp) { @@ -572,9 +571,7 @@ static int nx_display_probe(struct udevice *dev) } switch (dp->depth) { -#if 0 /* GDF_16BIT_565RGB is not defined in video.h */ case 2: - pp_index = GDF_16BIT_565RGB; uc_priv->bpix = VIDEO_BPP16; break; case 3: @@ -582,10 +579,8 @@ static int nx_display_probe(struct udevice *dev) * type video_log2_bpp */ case 4: - pp_index = GDF_32BIT_X888RGB; uc_priv->bpix = VIDEO_BPP32; break; -#endif default: printf("fail : not support LCD bit per pixel %d\n", dp->depth * 8); @@ -598,8 +593,7 @@ static int nx_display_probe(struct udevice *dev) /* * set environment variable "fb_addr" (frame buffer address), required - * for splash image. Because drv_video_init() in common/stdio.c is only - * called when CONFIG_VIDEO is set (and not if CONFIG_DM_VIDEO is set). + * for splash image, which is not set if CONFIG_DM_VIDEO is enabled). */ sprintf(addr, "0x%x", dp->fb_addr); debug("%s(): env_set(\"fb_addr\", %s) ...\n", __func__, addr); diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index e49f5bf2f7d..beb8bb90a64 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -67,7 +67,7 @@ struct global_data { * @mem_clk: memory clock rate in Hz */ unsigned long mem_clk; -#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO) +#if defined(CONFIG_LCD) || defined(CONFIG_DM_VIDEO) /** * @fb_base: base address of frame buffer memory */ diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 6cd7929db30..7272470d12e 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -74,11 +74,4 @@ #endif #endif /* CONFIG_SPL_BUILD */ -#if defined(CONFIG_VIDEO) -#define CONFIG_VIDEO_DA8XX -#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE -#define PWM_TICKS 0x1388 -#define PWM_DUTY 0x200 -#endif - #endif /* ! __CONFIG_PXM2_H */ diff --git a/include/configs/rut.h b/include/configs/rut.h index 410c6d379c3..b30b12af52c 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -67,13 +67,4 @@ #endif /* CONFIG_SPL_BUILD */ -#if defined(CONFIG_VIDEO) -#define CONFIG_VIDEO_DA8XX -#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE - -#define BOARD_LCD_RESET 115 /* Bank 3 pin 19 */ -#define CONFIG_FORMIKE -#define DISPL_PLL_SPREAD_SPECTRUM -#endif - #endif /* ! __CONFIG_RUT_H */ diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index e5e35fe51f6..28657f50c96 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -18,7 +18,6 @@ config EFI_LOADER select PARTITION_UUIDS select HAVE_BLOCK_DEVICE select REGEX - imply CFB_CONSOLE_ANSI imply FAT imply FAT_WRITE imply USB_KEYBOARD_FN_KEYS -- cgit v1.3.1 From 636b8b999cb30d44265d8adfdb14f6ebc78b0cd3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 23 Jan 2022 07:04:10 -0700 Subject: video: Drop da8xx-fb This is not used in U-Boot anymore. Drop it. Signed-off-by: Simon Glass --- drivers/video/Makefile | 1 - drivers/video/da8xx-fb.c | 1047 ------------------------------------------ drivers/video/da8xx-fb.h | 115 ----- scripts/config_whitelist.txt | 1 - 4 files changed, 1164 deletions(-) delete mode 100644 drivers/video/da8xx-fb.c delete mode 100644 drivers/video/da8xx-fb.h (limited to 'drivers') diff --git a/drivers/video/Makefile b/drivers/video/Makefile index be52512d6fd..16e5fd3bbbb 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -46,7 +46,6 @@ obj-$(CONFIG_VIDEO_ARM_MALIDP) += mali_dp.o obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o -obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o obj-$(CONFIG_VIDEO_DW_MIPI_DSI) += dw_mipi_dsi.o obj-$(CONFIG_VIDEO_EFI) += efi.o diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c deleted file mode 100644 index db9a820377d..00000000000 --- a/drivers/video/da8xx-fb.c +++ /dev/null @@ -1,1047 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Porting to u-boot: - * - * (C) Copyright 2011 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * Copyright (C) 2008-2009 MontaVista Software Inc. - * Copyright (C) 2008-2009 Texas Instruments Inc - * - * Based on the LCD driver for TI Avalanche processors written by - * Ajay Singh and Shalom Hai. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "videomodes.h" -#include "da8xx-fb.h" - -#if !defined(DA8XX_LCD_CNTL_BASE) -#define DA8XX_LCD_CNTL_BASE DAVINCI_LCD_CNTL_BASE -#endif - -#define DRIVER_NAME "da8xx_lcdc" - -#define LCD_VERSION_1 1 -#define LCD_VERSION_2 2 - -/* LCD Status Register */ -#define LCD_END_OF_FRAME1 (1 << 9) -#define LCD_END_OF_FRAME0 (1 << 8) -#define LCD_PL_LOAD_DONE (1 << 6) -#define LCD_FIFO_UNDERFLOW (1 << 5) -#define LCD_SYNC_LOST (1 << 2) - -/* LCD DMA Control Register */ -#define LCD_DMA_BURST_SIZE(x) ((x) << 4) -#define LCD_DMA_BURST_1 0x0 -#define LCD_DMA_BURST_2 0x1 -#define LCD_DMA_BURST_4 0x2 -#define LCD_DMA_BURST_8 0x3 -#define LCD_DMA_BURST_16 0x4 -#define LCD_V1_END_OF_FRAME_INT_ENA (1 << 2) -#define LCD_V2_END_OF_FRAME0_INT_ENA (1 << 8) -#define LCD_V2_END_OF_FRAME1_INT_ENA (1 << 9) -#define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0) - -#define LCD_V2_TFT_24BPP_MODE (1 << 25) -#define LCD_V2_TFT_24BPP_UNPACK (1 << 26) - -/* LCD Control Register */ -#define LCD_CLK_DIVISOR(x) ((x) << 8) -#define LCD_RASTER_MODE 0x01 - -/* LCD Raster Control Register */ -#define LCD_PALETTE_LOAD_MODE(x) ((x) << 20) -#define PALETTE_AND_DATA 0x00 -#define PALETTE_ONLY 0x01 -#define DATA_ONLY 0x02 - -#define LCD_MONO_8BIT_MODE (1 << 9) -#define LCD_RASTER_ORDER (1 << 8) -#define LCD_TFT_MODE (1 << 7) -#define LCD_V1_UNDERFLOW_INT_ENA (1 << 6) -#define LCD_V2_UNDERFLOW_INT_ENA (1 << 5) -#define LCD_V1_PL_INT_ENA (1 << 4) -#define LCD_V2_PL_INT_ENA (1 << 6) -#define LCD_MONOCHROME_MODE (1 << 1) -#define LCD_RASTER_ENABLE (1 << 0) -#define LCD_TFT_ALT_ENABLE (1 << 23) -#define LCD_STN_565_ENABLE (1 << 24) -#define LCD_V2_DMA_CLK_EN (1 << 2) -#define LCD_V2_LIDD_CLK_EN (1 << 1) -#define LCD_V2_CORE_CLK_EN (1 << 0) -#define LCD_V2_LPP_B10 26 -#define LCD_V2_TFT_24BPP_MODE (1 << 25) -#define LCD_V2_TFT_24BPP_UNPACK (1 << 26) - -/* LCD Raster Timing 2 Register */ -#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16) -#define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8) -#define LCD_SYNC_CTRL (1 << 25) -#define LCD_SYNC_EDGE (1 << 24) -#define LCD_INVERT_PIXEL_CLOCK (1 << 22) -#define LCD_INVERT_LINE_CLOCK (1 << 21) -#define LCD_INVERT_FRAME_CLOCK (1 << 20) - -/* Clock registers available only on Version 2 */ -#define LCD_CLK_MAIN_RESET (1 << 3) -/* LCD Block */ -struct da8xx_lcd_regs { - u32 revid; - u32 ctrl; - u32 stat; - u32 lidd_ctrl; - u32 lidd_cs0_conf; - u32 lidd_cs0_addr; - u32 lidd_cs0_data; - u32 lidd_cs1_conf; - u32 lidd_cs1_addr; - u32 lidd_cs1_data; - u32 raster_ctrl; - u32 raster_timing_0; - u32 raster_timing_1; - u32 raster_timing_2; - u32 raster_subpanel; - u32 reserved; - u32 dma_ctrl; - u32 dma_frm_buf_base_addr_0; - u32 dma_frm_buf_ceiling_addr_0; - u32 dma_frm_buf_base_addr_1; - u32 dma_frm_buf_ceiling_addr_1; - u32 resv1; - u32 raw_stat; - u32 masked_stat; - u32 int_ena_set; - u32 int_ena_clr; - u32 end_of_int_ind; - /* Clock registers available only on Version 2 */ - u32 clk_ena; - u32 clk_reset; -}; - -#define LCD_NUM_BUFFERS 1 - -#define WSI_TIMEOUT 50 -#define PALETTE_SIZE 256 -#define LEFT_MARGIN 64 -#define RIGHT_MARGIN 64 -#define UPPER_MARGIN 32 -#define LOWER_MARGIN 32 -#define WAIT_FOR_FRAME_DONE true -#define NO_WAIT_FOR_FRAME_DONE false - -#define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP) - -static struct da8xx_lcd_regs *da8xx_fb_reg_base; - -DECLARE_GLOBAL_DATA_PTR; - -/* graphics setup */ -static GraphicDevice gpanel; -static const struct da8xx_panel *lcd_panel; -static struct fb_info *da8xx_fb_info; -static int bits_x_pixel; -static unsigned int lcd_revision; -const struct lcd_ctrl_config *da8xx_lcd_cfg; - -static inline unsigned int lcdc_read(u32 *addr) -{ - return (unsigned int)readl(addr); -} - -static inline void lcdc_write(unsigned int val, u32 *addr) -{ - writel(val, addr); -} - -struct da8xx_fb_par { - u32 p_palette_base; - unsigned char *v_palette_base; - dma_addr_t vram_phys; - unsigned long vram_size; - void *vram_virt; - unsigned int dma_start; - unsigned int dma_end; - struct clk *lcdc_clk; - int irq; - unsigned short pseudo_palette[16]; - unsigned int palette_sz; - unsigned int pxl_clk; - int blank; - int vsync_flag; - int vsync_timeout; -}; - - -/* Variable Screen Information */ -static struct fb_var_screeninfo da8xx_fb_var = { - .xoffset = 0, - .yoffset = 0, - .transp = {0, 0, 0}, - .nonstd = 0, - .activate = 0, - .height = -1, - .width = -1, - .pixclock = 46666, /* 46us - AUO display */ - .accel_flags = 0, - .left_margin = LEFT_MARGIN, - .right_margin = RIGHT_MARGIN, - .upper_margin = UPPER_MARGIN, - .lower_margin = LOWER_MARGIN, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED -}; - -static struct fb_fix_screeninfo da8xx_fb_fix = { - .id = "DA8xx FB Drv", - .type = FB_TYPE_PACKED_PIXELS, - .type_aux = 0, - .visual = FB_VISUAL_PSEUDOCOLOR, - .xpanstep = 0, - .ypanstep = 1, - .ywrapstep = 0, - .accel = FB_ACCEL_NONE -}; - -/* Enable the Raster Engine of the LCD Controller */ -static inline void lcd_enable_raster(void) -{ - u32 reg; - - /* Put LCDC in reset for several cycles */ - if (lcd_revision == LCD_VERSION_2) - lcdc_write(LCD_CLK_MAIN_RESET, - &da8xx_fb_reg_base->clk_reset); - - udelay(1000); - /* Bring LCDC out of reset */ - if (lcd_revision == LCD_VERSION_2) - lcdc_write(0, - &da8xx_fb_reg_base->clk_reset); - - udelay(1000); - - reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); - if (!(reg & LCD_RASTER_ENABLE)) - lcdc_write(reg | LCD_RASTER_ENABLE, - &da8xx_fb_reg_base->raster_ctrl); -} - -/* Disable the Raster Engine of the LCD Controller */ -static inline void lcd_disable_raster(bool wait_for_frame_done) -{ - u32 reg; - u32 loop_cnt = 0; - u32 stat; - u32 i = 0; - - if (wait_for_frame_done) - loop_cnt = 5000; - - reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); - if (reg & LCD_RASTER_ENABLE) - lcdc_write(reg & ~LCD_RASTER_ENABLE, - &da8xx_fb_reg_base->raster_ctrl); - - /* Wait for the current frame to complete */ - do { - if (lcd_revision == LCD_VERSION_1) - stat = lcdc_read(&da8xx_fb_reg_base->stat); - else - stat = lcdc_read(&da8xx_fb_reg_base->raw_stat); - - mdelay(1); - } while (!(stat & 0x01) && (i++ < loop_cnt)); - - if (lcd_revision == LCD_VERSION_1) - lcdc_write(stat, &da8xx_fb_reg_base->stat); - else - lcdc_write(stat, &da8xx_fb_reg_base->raw_stat); - - if ((loop_cnt != 0) && (i >= loop_cnt)) { - printf("LCD Controller timed out\n"); - return; - } -} - -static void lcd_blit(int load_mode, struct da8xx_fb_par *par) -{ - u32 start; - u32 end; - u32 reg_ras; - u32 reg_dma; - u32 reg_int; - - /* init reg to clear PLM (loading mode) fields */ - reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); - reg_ras &= ~(3 << 20); - - reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl); - - if (load_mode == LOAD_DATA) { - start = par->dma_start; - end = par->dma_end; - - reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY); - if (lcd_revision == LCD_VERSION_1) { - reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA; - } else { - reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | - LCD_V2_END_OF_FRAME0_INT_ENA | - LCD_V2_END_OF_FRAME1_INT_ENA | - LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST; - lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); - } - -#if (LCD_NUM_BUFFERS == 2) - reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE; - lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); - lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); - lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); - lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); -#else - reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE; - lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); - lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); - lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); - lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); -#endif - - } else if (load_mode == LOAD_PALETTE) { - start = par->p_palette_base; - end = start + par->palette_sz - 1; - - reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY); - if (lcd_revision == LCD_VERSION_1) { - reg_ras |= LCD_V1_PL_INT_ENA; - } else { - reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | - LCD_V2_PL_INT_ENA; - lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); - } - - lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); - lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); - } - - lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl); - lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); - - /* - * The Raster enable bit must be set after all other control fields are - * set. - */ - lcd_enable_raster(); -} - -/* Configure the Burst Size of DMA */ -static int lcd_cfg_dma(int burst_size) -{ - u32 reg; - - reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001; - switch (burst_size) { - case 1: - reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1); - break; - case 2: - reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2); - break; - case 4: - reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4); - break; - case 8: - reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8); - break; - case 16: - reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16); - break; - default: - return -EINVAL; - } - lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl); - - return 0; -} - -static void lcd_cfg_ac_bias(int period, int transitions_per_int) -{ - u32 reg; - - /* Set the AC Bias Period and Number of Transitions per Interrupt */ - reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000; - reg |= LCD_AC_BIAS_FREQUENCY(period) | - LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int); - lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); -} - -static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width, - int front_porch) -{ - u32 reg; - - reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf; - reg |= ((back_porch & 0xff) << 24) - | ((front_porch & 0xff) << 16) - | ((pulse_width & 0x3f) << 10); - lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0); -} - -static void lcd_cfg_vertical_sync(int back_porch, int pulse_width, - int front_porch) -{ - u32 reg; - - reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff; - reg |= ((back_porch & 0xff) << 24) - | ((front_porch & 0xff) << 16) - | ((pulse_width & 0x3f) << 10); - lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1); -} - -static int lcd_cfg_display(const struct lcd_ctrl_config *cfg) -{ - u32 reg; - u32 reg_int; - - reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE | - LCD_MONO_8BIT_MODE | - LCD_MONOCHROME_MODE); - - switch (cfg->p_disp_panel->panel_shade) { - case MONOCHROME: - reg |= LCD_MONOCHROME_MODE; - if (cfg->mono_8bit_mode) - reg |= LCD_MONO_8BIT_MODE; - break; - case COLOR_ACTIVE: - reg |= LCD_TFT_MODE; - if (cfg->tft_alt_mode) - reg |= LCD_TFT_ALT_ENABLE; - break; - - case COLOR_PASSIVE: - if (cfg->stn_565_mode) - reg |= LCD_STN_565_ENABLE; - break; - - default: - return -EINVAL; - } - - /* enable additional interrupts here */ - if (lcd_revision == LCD_VERSION_1) { - reg |= LCD_V1_UNDERFLOW_INT_ENA; - } else { - reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | - LCD_V2_UNDERFLOW_INT_ENA; - lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); - } - - lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); - - reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2); - - if (cfg->sync_ctrl) - reg |= LCD_SYNC_CTRL; - else - reg &= ~LCD_SYNC_CTRL; - - if (cfg->sync_edge) - reg |= LCD_SYNC_EDGE; - else - reg &= ~LCD_SYNC_EDGE; - - if (cfg->invert_line_clock) - reg |= LCD_INVERT_LINE_CLOCK; - else - reg &= ~LCD_INVERT_LINE_CLOCK; - - if (cfg->invert_frm_clock) - reg |= LCD_INVERT_FRAME_CLOCK; - else - reg &= ~LCD_INVERT_FRAME_CLOCK; - - lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); - - return 0; -} - -static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, - u32 bpp, u32 raster_order) -{ - u32 reg; - - /* Set the Panel Width */ - /* Pixels per line = (PPL + 1)*16 */ - if (lcd_revision == LCD_VERSION_1) { - /* - * 0x3F in bits 4..9 gives max horizontal resolution = 1024 - * pixels - */ - width &= 0x3f0; - } else { - /* - * 0x7F in bits 4..10 gives max horizontal resolution = 2048 - * pixels. - */ - width &= 0x7f0; - } - reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0); - reg &= 0xfffffc00; - if (lcd_revision == LCD_VERSION_1) { - reg |= ((width >> 4) - 1) << 4; - } else { - width = (width >> 4) - 1; - reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3); - } - lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0); - - /* Set the Panel Height */ - /* Set bits 9:0 of Lines Per Pixel */ - reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1); - reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); - lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1); - - /* Set bit 10 of Lines Per Pixel */ - if (lcd_revision == LCD_VERSION_2) { - reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2); - reg |= ((height - 1) & 0x400) << 16; - lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); - } - - /* Set the Raster Order of the Frame Buffer */ - reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8); - if (raster_order) - reg |= LCD_RASTER_ORDER; - - if (bpp == 24) - reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE); - else if (bpp == 32) - reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE - | LCD_V2_TFT_24BPP_UNPACK); - - lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); - - switch (bpp) { - case 1: - case 2: - case 4: - case 16: - case 24: - case 32: - par->palette_sz = 16 * 2; - break; - - case 8: - par->palette_sz = 256 * 2; - break; - - default: - return -EINVAL; - } - - return 0; -} - -static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, - unsigned blue, unsigned transp, - struct fb_info *info) -{ - struct da8xx_fb_par *par = info->par; - unsigned short *palette = (unsigned short *) par->v_palette_base; - u_short pal; - int update_hw = 0; - - if (regno > 255) - return 1; - - if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) - return 1; - - if (info->var.bits_per_pixel == 8) { - red >>= 4; - green >>= 8; - blue >>= 12; - - pal = (red & 0x0f00); - pal |= (green & 0x00f0); - pal |= (blue & 0x000f); - - if (palette[regno] != pal) { - update_hw = 1; - palette[regno] = pal; - } - } else if ((info->var.bits_per_pixel == 16) && regno < 16) { - red >>= (16 - info->var.red.length); - red <<= info->var.red.offset; - - green >>= (16 - info->var.green.length); - green <<= info->var.green.offset; - - blue >>= (16 - info->var.blue.length); - blue <<= info->var.blue.offset; - - par->pseudo_palette[regno] = red | green | blue; - - if (palette[0] != 0x4000) { - update_hw = 1; - palette[0] = 0x4000; - } - } else if (((info->var.bits_per_pixel == 32) && regno < 32) || - ((info->var.bits_per_pixel == 24) && regno < 24)) { - red >>= (24 - info->var.red.length); - red <<= info->var.red.offset; - - green >>= (24 - info->var.green.length); - green <<= info->var.green.offset; - - blue >>= (24 - info->var.blue.length); - blue <<= info->var.blue.offset; - - par->pseudo_palette[regno] = red | green | blue; - - if (palette[0] != 0x4000) { - update_hw = 1; - palette[0] = 0x4000; - } - } - - /* Update the palette in the h/w as needed. */ - if (update_hw) - lcd_blit(LOAD_PALETTE, par); - - return 0; -} - -static void lcd_reset(struct da8xx_fb_par *par) -{ - /* Disable the Raster if previously Enabled */ - lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); - - /* DMA has to be disabled */ - lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl); - lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl); - - if (lcd_revision == LCD_VERSION_2) { - lcdc_write(0, &da8xx_fb_reg_base->int_ena_set); - /* Write 1 to reset */ - lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset); - lcdc_write(0, &da8xx_fb_reg_base->clk_reset); - } -} - -static void lcd_calc_clk_divider(struct da8xx_fb_par *par) -{ - unsigned int lcd_clk, div; - - /* Get clock from sysclk2 */ - lcd_clk = clk_get(2); - - div = lcd_clk / par->pxl_clk; - debug("LCD Clock: %d Divider: %d PixClk: %d\n", - lcd_clk, div, par->pxl_clk); - - /* Configure the LCD clock divisor. */ - lcdc_write(LCD_CLK_DIVISOR(div) | - (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl); - - if (lcd_revision == LCD_VERSION_2) - lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN | - LCD_V2_CORE_CLK_EN, - &da8xx_fb_reg_base->clk_ena); -} - -static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, - const struct da8xx_panel *panel) -{ - u32 bpp; - int ret = 0; - - lcd_reset(par); - - /* Calculate the divider */ - lcd_calc_clk_divider(par); - - if (panel->invert_pxl_clk) - lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) | - LCD_INVERT_PIXEL_CLOCK), - &da8xx_fb_reg_base->raster_timing_2); - else - lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & - ~LCD_INVERT_PIXEL_CLOCK), - &da8xx_fb_reg_base->raster_timing_2); - - /* Configure the DMA burst size. */ - ret = lcd_cfg_dma(cfg->dma_burst_sz); - if (ret < 0) - return ret; - - /* Configure the AC bias properties. */ - lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt); - - /* Configure the vertical and horizontal sync properties. */ - lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp); - lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp); - - /* Configure for display */ - ret = lcd_cfg_display(cfg); - if (ret < 0) - return ret; - - if ((QVGA != cfg->p_disp_panel->panel_type) && - (WVGA != cfg->p_disp_panel->panel_type)) - return -EINVAL; - - if (cfg->bpp <= cfg->p_disp_panel->max_bpp && - cfg->bpp >= cfg->p_disp_panel->min_bpp) - bpp = cfg->bpp; - else - bpp = cfg->p_disp_panel->max_bpp; - if (bpp == 12) - bpp = 16; - ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width, - (unsigned int)panel->height, bpp, - cfg->raster_order); - if (ret < 0) - return ret; - - /* Configure FDD */ - lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) | - (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl); - - return 0; -} - -static void lcdc_dma_start(void) -{ - struct da8xx_fb_par *par = da8xx_fb_info->par; - lcdc_write(par->dma_start, - &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); - lcdc_write(par->dma_end, - &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); - lcdc_write(0, - &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); - lcdc_write(0, - &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); -} - -static u32 lcdc_irq_handler_rev01(void) -{ - struct da8xx_fb_par *par = da8xx_fb_info->par; - u32 stat = lcdc_read(&da8xx_fb_reg_base->stat); - u32 reg_ras; - - if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { - debug("LCD_SYNC_LOST\n"); - lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); - lcdc_write(stat, &da8xx_fb_reg_base->stat); - lcd_enable_raster(); - return LCD_SYNC_LOST; - } else if (stat & LCD_PL_LOAD_DONE) { - debug("LCD_PL_LOAD_DONE\n"); - /* - * Must disable raster before changing state of any control bit. - * And also must be disabled before clearing the PL loading - * interrupt via the following write to the status register. If - * this is done after then one gets multiple PL done interrupts. - */ - lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); - - lcdc_write(stat, &da8xx_fb_reg_base->stat); - - /* Disable PL completion interrupt */ - reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); - reg_ras &= ~LCD_V1_PL_INT_ENA; - lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); - - /* Setup and start data loading mode */ - lcd_blit(LOAD_DATA, par); - return LCD_PL_LOAD_DONE; - } else { - lcdc_write(stat, &da8xx_fb_reg_base->stat); - - if (stat & LCD_END_OF_FRAME0) - debug("LCD_END_OF_FRAME0\n"); - - lcdc_write(par->dma_start, - &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); - lcdc_write(par->dma_end, - &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); - par->vsync_flag = 1; - return LCD_END_OF_FRAME0; - } - return stat; -} - -static u32 lcdc_irq_handler_rev02(void) -{ - struct da8xx_fb_par *par = da8xx_fb_info->par; - u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat); - u32 reg_int; - - if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { - debug("LCD_SYNC_LOST\n"); - lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); - lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); - lcd_enable_raster(); - lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); - return LCD_SYNC_LOST; - } else if (stat & LCD_PL_LOAD_DONE) { - debug("LCD_PL_LOAD_DONE\n"); - /* - * Must disable raster before changing state of any control bit. - * And also must be disabled before clearing the PL loading - * interrupt via the following write to the status register. If - * this is done after then one gets multiple PL done interrupts. - */ - lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); - - lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); - - /* Disable PL completion interrupt */ - reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) | - (LCD_V2_PL_INT_ENA); - lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr); - - /* Setup and start data loading mode */ - lcd_blit(LOAD_DATA, par); - lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); - return LCD_PL_LOAD_DONE; - } else { - lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); - - if (stat & LCD_END_OF_FRAME0) - debug("LCD_END_OF_FRAME0\n"); - - lcdc_write(par->dma_start, - &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); - lcdc_write(par->dma_end, - &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); - par->vsync_flag = 1; - lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); - return LCD_END_OF_FRAME0; - } - lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); - return stat; -} - -static u32 lcdc_irq_handler(void) -{ - if (lcd_revision == LCD_VERSION_1) - return lcdc_irq_handler_rev01(); - else - return lcdc_irq_handler_rev02(); -} - -static u32 wait_for_event(u32 event) -{ - u32 timeout = 50000; - u32 ret; - - do { - ret = lcdc_irq_handler(); - udelay(1000); - --timeout; - } while (!(ret & event) && timeout); - - if (!(ret & event)) { - printf("%s: event %d not hit\n", __func__, event); - return -1; - } - - return 0; - -} - -void *video_hw_init(void) -{ - struct da8xx_fb_par *par; - u32 size; - u32 rev; - char *p; - - if (!lcd_panel) { - printf("Display not initialized\n"); - return NULL; - } - gpanel.winSizeX = lcd_panel->width; - gpanel.winSizeY = lcd_panel->height; - gpanel.plnSizeX = lcd_panel->width; - gpanel.plnSizeY = lcd_panel->height; - - switch (bits_x_pixel) { - case 32: - gpanel.gdfBytesPP = 4; - gpanel.gdfIndex = GDF_32BIT_X888RGB; - break; - case 24: - gpanel.gdfBytesPP = 4; - gpanel.gdfIndex = GDF_32BIT_X888RGB; - break; - case 16: - gpanel.gdfBytesPP = 2; - gpanel.gdfIndex = GDF_16BIT_565RGB; - break; - default: - gpanel.gdfBytesPP = 1; - gpanel.gdfIndex = GDF__8BIT_INDEX; - break; - } - - da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DA8XX_LCD_CNTL_BASE; - - /* Determine LCD IP Version */ - rev = lcdc_read(&da8xx_fb_reg_base->revid); - switch (rev) { - case 0x4C100102: - lcd_revision = LCD_VERSION_1; - break; - case 0x4F200800: - case 0x4F201000: - lcd_revision = LCD_VERSION_2; - break; - default: - printf("Unknown PID Reg value 0x%x, defaulting to LCD revision 1\n", - rev); - lcd_revision = LCD_VERSION_1; - break; - } - - debug("rev: 0x%x Resolution: %dx%d %d\n", rev, - gpanel.winSizeX, - gpanel.winSizeY, - da8xx_lcd_cfg->bpp); - - size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par); - da8xx_fb_info = malloc_cache_aligned(size); - debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info); - - if (!da8xx_fb_info) { - printf("Memory allocation failed for fb_info\n"); - return NULL; - } - memset(da8xx_fb_info, 0, size); - p = (char *)da8xx_fb_info; - da8xx_fb_info->par = p + sizeof(struct fb_info); - debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par); - - par = da8xx_fb_info->par; - par->pxl_clk = lcd_panel->pxl_clk; - - if (lcd_init(par, da8xx_lcd_cfg, lcd_panel) < 0) { - printf("lcd_init failed\n"); - goto err_release_fb; - } - - /* allocate frame buffer */ - par->vram_size = lcd_panel->width * lcd_panel->height * - da8xx_lcd_cfg->bpp; - par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8; - - par->vram_virt = malloc_cache_aligned(par->vram_size); - - par->vram_phys = (dma_addr_t) par->vram_virt; - debug("Requesting 0x%x bytes for framebuffer at 0x%x\n", - (unsigned int)par->vram_size, - (unsigned int)par->vram_virt); - if (!par->vram_virt) { - printf("GLCD: malloc for frame buffer failed\n"); - goto err_release_fb; - } - gd->fb_base = (int)par->vram_virt; - - gpanel.frameAdrs = (unsigned int)par->vram_virt; - da8xx_fb_info->screen_base = (char *) par->vram_virt; - da8xx_fb_fix.smem_start = gpanel.frameAdrs; - da8xx_fb_fix.smem_len = par->vram_size; - da8xx_fb_fix.line_length = (lcd_panel->width * da8xx_lcd_cfg->bpp) / 8; - - par->dma_start = par->vram_phys; - par->dma_end = par->dma_start + lcd_panel->height * - da8xx_fb_fix.line_length - 1; - - /* allocate palette buffer */ - par->v_palette_base = malloc_cache_aligned(PALETTE_SIZE); - if (!par->v_palette_base) { - printf("GLCD: malloc for palette buffer failed\n"); - goto err_release_fb_mem; - } - memset(par->v_palette_base, 0, PALETTE_SIZE); - par->p_palette_base = (unsigned int)par->v_palette_base; - - /* Initialize par */ - da8xx_fb_info->var.bits_per_pixel = da8xx_lcd_cfg->bpp; - - da8xx_fb_var.xres = lcd_panel->width; - da8xx_fb_var.xres_virtual = lcd_panel->width; - - da8xx_fb_var.yres = lcd_panel->height; - da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS; - - da8xx_fb_var.grayscale = - da8xx_lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0; - da8xx_fb_var.bits_per_pixel = da8xx_lcd_cfg->bpp; - - da8xx_fb_var.hsync_len = lcd_panel->hsw; - da8xx_fb_var.vsync_len = lcd_panel->vsw; - - /* Initialize fbinfo */ - da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT; - da8xx_fb_info->fix = da8xx_fb_fix; - da8xx_fb_info->var = da8xx_fb_var; - da8xx_fb_info->pseudo_palette = par->pseudo_palette; - da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ? - FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; - - /* Clear interrupt */ - memset((void *)par->vram_virt, 0, par->vram_size); - lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); - if (lcd_revision == LCD_VERSION_1) - lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat); - else - lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat); - debug("Palette at 0x%x size %d\n", par->p_palette_base, - par->palette_sz); - lcdc_dma_start(); - - /* Load a default palette */ - fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info); - - /* Check that the palette is loaded */ - wait_for_event(LCD_PL_LOAD_DONE); - - /* Wait until DMA is working */ - wait_for_event(LCD_END_OF_FRAME0); - - return (void *)&gpanel; - -err_release_fb_mem: - free(par->vram_virt); - -err_release_fb: - free(da8xx_fb_info); - - return NULL; -} - -void da8xx_video_init(const struct da8xx_panel *panel, - const struct lcd_ctrl_config *lcd_cfg, int bits_pixel) -{ - lcd_panel = panel; - da8xx_lcd_cfg = lcd_cfg; - bits_x_pixel = bits_pixel; -} diff --git a/drivers/video/da8xx-fb.h b/drivers/video/da8xx-fb.h deleted file mode 100644 index 9b30d984741..00000000000 --- a/drivers/video/da8xx-fb.h +++ /dev/null @@ -1,115 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Porting to u-boot: - * - * (C) Copyright 2011 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * Copyright (C) 2008-2009 MontaVista Software Inc. - * Copyright (C) 2008-2009 Texas Instruments Inc - * - * Based on the LCD driver for TI Avalanche processors written by - * Ajay Singh and Shalom Hai. - */ - -#ifndef DA8XX_FB_H -#define DA8XX_FB_H - -enum panel_type { - QVGA = 0, - WVGA -}; - -enum panel_shade { - MONOCHROME = 0, - COLOR_ACTIVE, - COLOR_PASSIVE, -}; - -enum raster_load_mode { - LOAD_DATA = 1, - LOAD_PALETTE, -}; - -struct display_panel { - enum panel_type panel_type; /* QVGA */ - int max_bpp; - int min_bpp; - enum panel_shade panel_shade; -}; - -struct da8xx_panel { - const char name[25]; /* Full name _ */ - unsigned short width; - unsigned short height; - int hfp; /* Horizontal front porch */ - int hbp; /* Horizontal back porch */ - int hsw; /* Horizontal Sync Pulse Width */ - int vfp; /* Vertical front porch */ - int vbp; /* Vertical back porch */ - int vsw; /* Vertical Sync Pulse Width */ - unsigned int pxl_clk; /* Pixel clock */ - unsigned char invert_pxl_clk; /* Invert Pixel clock */ -}; - -struct da8xx_lcdc_platform_data { - const char manu_name[10]; - void *controller_data; - const char type[25]; - void (*panel_power_ctrl)(int); -}; - -struct lcd_ctrl_config { - const struct display_panel *p_disp_panel; - - /* AC Bias Pin Frequency */ - int ac_bias; - - /* AC Bias Pin Transitions per Interrupt */ - int ac_bias_intrpt; - - /* DMA burst size */ - int dma_burst_sz; - - /* Bits per pixel */ - int bpp; - - /* FIFO DMA Request Delay */ - int fdd; - - /* TFT Alternative Signal Mapping (Only for active) */ - unsigned char tft_alt_mode; - - /* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */ - unsigned char stn_565_mode; - - /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */ - unsigned char mono_8bit_mode; - - /* Invert line clock */ - unsigned char invert_line_clock; - - /* Invert frame clock */ - unsigned char invert_frm_clock; - - /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */ - unsigned char sync_edge; - - /* Horizontal and Vertical Sync: Control: 0=ignore */ - unsigned char sync_ctrl; - - /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */ - unsigned char raster_order; -}; - -struct lcd_sync_arg { - int back_porch; - int front_porch; - int pulse_width; -}; - -void da8xx_video_init(const struct da8xx_panel *panel, - const struct lcd_ctrl_config *lcd_cfg, - int bits_pixel); - -#endif /* ifndef DA8XX_FB_H */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 284a1efa175..273f1f160df 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2009,7 +2009,6 @@ CONFIG_U_BOOT_HDR_SIZE CONFIG_VAR_SIZE_SPL CONFIG_VERY_BIG_RAM CONFIG_VIDEO_BCM2835 -CONFIG_VIDEO_DA8XX CONFIG_VSC7385_ENET CONFIG_VSC7385_IMAGE CONFIG_VSC7385_IMAGE_SIZE -- cgit v1.3.1 From 77f46f06075a192da8f43cc8826117e0e28fcb59 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 23 Jan 2022 07:04:11 -0700 Subject: video: fsl: colibri_vf: Drop FSL DCU driver This does not use driver model and is more than two years past the migration date. Drop it. It can be added back later if needed. Signed-off-by: Simon Glass --- arch/arm/cpu/armv7/ls102xa/soc.c | 4 - arch/arm/include/asm/arch-ls102xa/config.h | 1 - board/freescale/common/Makefile | 2 - board/freescale/common/dcu_sii9022a.c | 248 ------------- board/freescale/common/dcu_sii9022a.h | 12 - board/freescale/ls1021aiot/Makefile | 1 - board/freescale/ls1021aiot/dcu.c | 48 --- board/freescale/ls1021aqds/Makefile | 1 - board/freescale/ls1021aqds/dcu.c | 110 ------ board/freescale/ls1021atwr/Makefile | 1 - board/freescale/ls1021atwr/dcu.c | 48 --- board/toradex/colibri_vf/Makefile | 1 - board/toradex/colibri_vf/colibri_vf.c | 62 ---- board/toradex/colibri_vf/dcu.c | 38 -- configs/colibri_vf_defconfig | 1 - drivers/video/Kconfig | 15 - drivers/video/Makefile | 1 - drivers/video/fsl_dcu_fb.c | 548 ----------------------------- include/configs/colibri_vf.h | 7 - include/configs/ls1021aqds.h | 10 - include/configs/ls1021atwr.h | 13 - include/fsl_dcu_fb.h | 22 -- scripts/config_whitelist.txt | 3 - 23 files changed, 1197 deletions(-) delete mode 100644 board/freescale/common/dcu_sii9022a.c delete mode 100644 board/freescale/common/dcu_sii9022a.h delete mode 100644 board/freescale/ls1021aiot/dcu.c delete mode 100644 board/freescale/ls1021aqds/dcu.c delete mode 100644 board/freescale/ls1021atwr/dcu.c delete mode 100644 board/toradex/colibri_vf/dcu.c delete mode 100644 drivers/video/fsl_dcu_fb.c delete mode 100644 include/fsl_dcu_fb.h (limited to 'drivers') diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index c131d92b993..728efc46f90 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -174,10 +174,6 @@ int arch_soc_init(void) out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); #endif -#ifdef CONFIG_VIDEO_FSL_DCU_FB - out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); -#endif - /* Configure Little endian for SAI, ASRC and SPDIF */ out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 86a4e1f6bf3..3b1d9a3f0c4 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -88,7 +88,6 @@ #define CONFIG_SYS_FSL_ESDHC_BE #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE -#define CONFIG_SYS_FSL_DCU_BE #define CONFIG_SYS_FSL_SEC_MON_LE #define CONFIG_SYS_FSL_SFP_VER_3_2 #define CONFIG_SYS_FSL_SFP_BE diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 0ddfb59d7de..c8f62bfc198 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -52,8 +52,6 @@ else obj-$(CONFIG_DEEP_SLEEP) += mpc85xx_sleep.o endif -obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o - obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o diff --git a/board/freescale/common/dcu_sii9022a.c b/board/freescale/common/dcu_sii9022a.c deleted file mode 100644 index 9137d246ea0..00000000000 --- a/board/freescale/common/dcu_sii9022a.c +++ /dev/null @@ -1,248 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2019 NXP - */ - -#include -#include -#include -#include -#include - -#define PIXEL_CLK_LSB_REG 0x00 -#define PIXEL_CLK_MSB_REG 0x01 -#define VERT_FREQ_LSB_REG 0x02 -#define VERT_FREQ_MSB_REG 0x03 -#define TOTAL_PIXELS_LSB_REG 0x04 -#define TOTAL_PIXELS_MSB_REG 0x05 -#define TOTAL_LINES_LSB_REG 0x06 -#define TOTAL_LINES_MSB_REG 0x07 -#define TPI_INBUS_FMT_REG 0x08 -#define TPI_INPUT_FMT_REG 0x09 -#define TPI_OUTPUT_FMT_REG 0x0A -#define TPI_SYS_CTRL_REG 0x1A -#define TPI_PWR_STAT_REG 0x1E -#define TPI_AUDIO_HANDING_REG 0x25 -#define TPI_AUDIO_INTF_REG 0x26 -#define TPI_AUDIO_FREQ_REG 0x27 -#define TPI_SET_PAGE_REG 0xBC -#define TPI_SET_OFFSET_REG 0xBD -#define TPI_RW_ACCESS_REG 0xBE -#define TPI_TRANS_MODE_REG 0xC7 - -#define TPI_INBUS_CLOCK_RATIO_1 (1 << 6) -#define TPI_INBUS_FULL_PIXEL_WIDE (1 << 5) -#define TPI_INBUS_RISING_EDGE (1 << 4) -#define TPI_INPUT_CLR_DEPTH_8BIT (0 << 6) -#define TPI_INPUT_VRANGE_EXPAN_AUTO (0 << 2) -#define TPI_INPUT_CLR_RGB (0 << 0) -#define TPI_OUTPUT_CLR_DEPTH_8BIT (0 << 6) -#define TPI_OUTPUT_VRANGE_COMPRE_AUTO (0 << 2) -#define TPI_OUTPUT_CLR_HDMI_RGB (0 << 0) -#define TPI_SYS_TMDS_OUTPUT (0 << 4) -#define TPI_SYS_AV_NORAML (0 << 3) -#define TPI_SYS_AV_MUTE (1 << 3) -#define TPI_SYS_DVI_MODE (0 << 0) -#define TPI_SYS_HDMI_MODE (1 << 0) -#define TPI_PWR_STAT_MASK (3 << 0) -#define TPI_PWR_STAT_D0 (0 << 0) -#define TPI_AUDIO_PASS_BASIC (0 << 0) -#define TPI_AUDIO_INTF_I2S (2 << 6) -#define TPI_AUDIO_INTF_NORMAL (0 << 4) -#define TPI_AUDIO_TYPE_PCM (1 << 0) -#define TPI_AUDIO_SAMP_SIZE_16BIT (1 << 6) -#define TPI_AUDIO_SAMP_FREQ_44K (2 << 3) -#define TPI_SET_PAGE_SII9022A 0x01 -#define TPI_SET_OFFSET_SII9022A 0x82 -#define TPI_RW_EN_SRC_TERMIN (1 << 0) -#define TPI_TRANS_MODE_ENABLE (0 << 7) - -/* Programming of Silicon SIi9022a HDMI Transmitter */ -int dcu_set_dvi_encoder(struct fb_videomode *videomode) -{ - u8 temp; - u16 temp1, temp2; - u32 temp3; -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM, - CONFIG_SYS_I2C_DVI_ADDR, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - CONFIG_SYS_I2C_DVI_BUS_NUM); - return ret; - } - - /* Enable TPI transmitter mode */ - temp = TPI_TRANS_MODE_ENABLE; - dm_i2c_write(dev, TPI_TRANS_MODE_REG, &temp, 1); - - /* Enter into D0 state, full operation */ - dm_i2c_read(dev, TPI_PWR_STAT_REG, &temp, 1); - temp &= ~TPI_PWR_STAT_MASK; - temp |= TPI_PWR_STAT_D0; - dm_i2c_write(dev, TPI_PWR_STAT_REG, &temp, 1); - - /* Enable source termination */ - temp = TPI_SET_PAGE_SII9022A; - dm_i2c_write(dev, TPI_SET_PAGE_REG, &temp, 1); - temp = TPI_SET_OFFSET_SII9022A; - dm_i2c_write(dev, TPI_SET_OFFSET_REG, &temp, 1); - - dm_i2c_read(dev, TPI_RW_ACCESS_REG, &temp, 1); - temp |= TPI_RW_EN_SRC_TERMIN; - dm_i2c_write(dev, TPI_RW_ACCESS_REG, &temp, 1); - - /* Set TPI system control */ - temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE; - dm_i2c_write(dev, TPI_SYS_CTRL_REG, &temp, 1); - - /* Set pixel clock */ - temp1 = PICOS2KHZ(videomode->pixclock) / 10; - temp = (u8)(temp1 & 0xFF); - dm_i2c_write(dev, PIXEL_CLK_LSB_REG, &temp, 1); - temp = (u8)(temp1 >> 8); - dm_i2c_write(dev, PIXEL_CLK_MSB_REG, &temp, 1); - - /* Set total pixels per line */ - temp1 = videomode->hsync_len + videomode->left_margin + - videomode->xres + videomode->right_margin; - temp = (u8)(temp1 & 0xFF); - dm_i2c_write(dev, TOTAL_PIXELS_LSB_REG, &temp, 1); - temp = (u8)(temp1 >> 8); - dm_i2c_write(dev, TOTAL_PIXELS_MSB_REG, &temp, 1); - - /* Set total lines */ - temp2 = videomode->vsync_len + videomode->upper_margin + - videomode->yres + videomode->lower_margin; - temp = (u8)(temp2 & 0xFF); - dm_i2c_write(dev, TOTAL_LINES_LSB_REG, &temp, 1); - temp = (u8)(temp2 >> 8); - dm_i2c_write(dev, TOTAL_LINES_MSB_REG, &temp, 1); - - /* Set vertical frequency in Hz */ - temp3 = temp1 * temp2; - temp3 = (PICOS2KHZ(videomode->pixclock) * 1000) / temp3; - temp1 = (u16)temp3 * 100; - temp = (u8)(temp1 & 0xFF); - dm_i2c_write(dev, VERT_FREQ_LSB_REG, &temp, 1); - temp = (u8)(temp1 >> 8); - dm_i2c_write(dev, VERT_FREQ_MSB_REG, &temp, 1); - - /* Set TPI input bus and pixel repetition data */ - temp = TPI_INBUS_CLOCK_RATIO_1 | TPI_INBUS_FULL_PIXEL_WIDE | - TPI_INBUS_RISING_EDGE; - dm_i2c_write(dev, TPI_INBUS_FMT_REG, &temp, 1); - - /* Set TPI AVI Input format data */ - temp = TPI_INPUT_CLR_DEPTH_8BIT | TPI_INPUT_VRANGE_EXPAN_AUTO | - TPI_INPUT_CLR_RGB; - dm_i2c_write(dev, TPI_INPUT_FMT_REG, &temp, 1); - - /* Set TPI AVI Output format data */ - temp = TPI_OUTPUT_CLR_DEPTH_8BIT | TPI_OUTPUT_VRANGE_COMPRE_AUTO | - TPI_OUTPUT_CLR_HDMI_RGB; - dm_i2c_write(dev, TPI_OUTPUT_FMT_REG, &temp, 1); - - /* Set TPI audio configuration write data */ - temp = TPI_AUDIO_PASS_BASIC; - dm_i2c_write(dev, TPI_AUDIO_HANDING_REG, &temp, 1); - - temp = TPI_AUDIO_INTF_I2S | TPI_AUDIO_INTF_NORMAL | - TPI_AUDIO_TYPE_PCM; - dm_i2c_write(dev, TPI_AUDIO_INTF_REG, &temp, 1); - - temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K; - dm_i2c_write(dev, TPI_AUDIO_FREQ_REG, &temp, 1); -#else - i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM); - - /* Enable TPI transmitter mode */ - temp = TPI_TRANS_MODE_ENABLE; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_TRANS_MODE_REG, 1, &temp, 1); - - /* Enter into D0 state, full operation */ - i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1); - temp &= ~TPI_PWR_STAT_MASK; - temp |= TPI_PWR_STAT_D0; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1); - - /* Enable source termination */ - temp = TPI_SET_PAGE_SII9022A; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_PAGE_REG, 1, &temp, 1); - temp = TPI_SET_OFFSET_SII9022A; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_OFFSET_REG, 1, &temp, 1); - - i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1); - temp |= TPI_RW_EN_SRC_TERMIN; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1); - - /* Set TPI system control */ - temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SYS_CTRL_REG, 1, &temp, 1); - - /* Set pixel clock */ - temp1 = PICOS2KHZ(videomode->pixclock) / 10; - temp = (u8)(temp1 & 0xFF); - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, PIXEL_CLK_LSB_REG, 1, &temp, 1); - temp = (u8)(temp1 >> 8); - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, PIXEL_CLK_MSB_REG, 1, &temp, 1); - - /* Set total pixels per line */ - temp1 = videomode->hsync_len + videomode->left_margin + - videomode->xres + videomode->right_margin; - temp = (u8)(temp1 & 0xFF); - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_PIXELS_LSB_REG, 1, &temp, 1); - temp = (u8)(temp1 >> 8); - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_PIXELS_MSB_REG, 1, &temp, 1); - - /* Set total lines */ - temp2 = videomode->vsync_len + videomode->upper_margin + - videomode->yres + videomode->lower_margin; - temp = (u8)(temp2 & 0xFF); - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_LINES_LSB_REG, 1, &temp, 1); - temp = (u8)(temp2 >> 8); - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_LINES_MSB_REG, 1, &temp, 1); - - /* Set vertical frequency in Hz */ - temp3 = temp1 * temp2; - temp3 = (PICOS2KHZ(videomode->pixclock) * 1000) / temp3; - temp1 = (u16)temp3 * 100; - temp = (u8)(temp1 & 0xFF); - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, VERT_FREQ_LSB_REG, 1, &temp, 1); - temp = (u8)(temp1 >> 8); - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, VERT_FREQ_MSB_REG, 1, &temp, 1); - - /* Set TPI input bus and pixel repetition data */ - temp = TPI_INBUS_CLOCK_RATIO_1 | TPI_INBUS_FULL_PIXEL_WIDE | - TPI_INBUS_RISING_EDGE; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_INBUS_FMT_REG, 1, &temp, 1); - - /* Set TPI AVI Input format data */ - temp = TPI_INPUT_CLR_DEPTH_8BIT | TPI_INPUT_VRANGE_EXPAN_AUTO | - TPI_INPUT_CLR_RGB; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_INPUT_FMT_REG, 1, &temp, 1); - - /* Set TPI AVI Output format data */ - temp = TPI_OUTPUT_CLR_DEPTH_8BIT | TPI_OUTPUT_VRANGE_COMPRE_AUTO | - TPI_OUTPUT_CLR_HDMI_RGB; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_OUTPUT_FMT_REG, 1, &temp, 1); - - /* Set TPI audio configuration write data */ - temp = TPI_AUDIO_PASS_BASIC; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_HANDING_REG, 1, &temp, 1); - - temp = TPI_AUDIO_INTF_I2S | TPI_AUDIO_INTF_NORMAL | - TPI_AUDIO_TYPE_PCM; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_INTF_REG, 1, &temp, 1); - - temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_FREQ_REG, 1, &temp, 1); -#endif - - return 0; -} diff --git a/board/freescale/common/dcu_sii9022a.h b/board/freescale/common/dcu_sii9022a.h deleted file mode 100644 index 7851775530d..00000000000 --- a/board/freescale/common/dcu_sii9022a.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DCU_HDMI_SII9022A__ -#define __DCU_HDMI_SII9022A__ - -/* Programming of Silicon SII9022A connector HDMI Transmitter*/ -int dcu_set_dvi_encoder(struct fb_videomode *videomode); - -#endif diff --git a/board/freescale/ls1021aiot/Makefile b/board/freescale/ls1021aiot/Makefile index bec151fd2ac..587bbd79ddf 100644 --- a/board/freescale/ls1021aiot/Makefile +++ b/board/freescale/ls1021aiot/Makefile @@ -3,5 +3,4 @@ # Copyright 2016 Freescale Semiconductor, Inc. obj-y += ls1021aiot.o -obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021aiot/dcu.c b/board/freescale/ls1021aiot/dcu.c deleted file mode 100644 index e4fbcbcaad3..00000000000 --- a/board/freescale/ls1021aiot/dcu.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * - * FSL DCU Framebuffer driver - */ - -#include -#include -#include -#include "div64.h" -#include "../common/dcu_sii9022a.h" - -DECLARE_GLOBAL_DATA_PTR; - -unsigned int dcu_set_pixel_clock(unsigned int pixclock) -{ - unsigned long long div; - - div = (unsigned long long)(gd->bus_clk / 1000); - div *= (unsigned long long)pixclock; - do_div(div, 1000000000); - - return div; -} - -int platform_dcu_init(struct fb_info *fbinfo, - unsigned int xres, unsigned int yres, - const char *port, - struct fb_videomode *dcu_fb_videomode) -{ - const char *name; - unsigned int pixel_format; - - if (strncmp(port, "twr_lcd", 4) == 0) { - name = "TWR_LCD_RGB card"; - } else { - name = "HDMI"; - dcu_set_dvi_encoder(dcu_fb_videomode); - } - - printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres); - - pixel_format = 32; - fsl_dcu_init(fbinfo, xres, yres, pixel_format); - - return 0; -} diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile index 1e50e468a32..65030342be3 100644 --- a/board/freescale/ls1021aqds/Makefile +++ b/board/freescale/ls1021aqds/Makefile @@ -7,5 +7,4 @@ obj-y += ls1021aqds.o obj-y += ddr.o obj-y += eth.o -obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021aqds/dcu.c b/board/freescale/ls1021aqds/dcu.c deleted file mode 100644 index b5fee06b5b0..00000000000 --- a/board/freescale/ls1021aqds/dcu.c +++ /dev/null @@ -1,110 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2019 NXP - * - * FSL DCU Framebuffer driver - */ - -#include -#include -#include -#include -#include -#include "../common/i2c_mux.h" -#include "div64.h" -#include "../common/diu_ch7301.h" -#include "ls1021aqds_qixis.h" - -DECLARE_GLOBAL_DATA_PTR; - -unsigned int dcu_set_pixel_clock(unsigned int pixclock) -{ - unsigned long long div; - - div = (unsigned long long)(gd->bus_clk / 1000); - div *= (unsigned long long)pixclock; - do_div(div, 1000000000); - - return div; -} - -int platform_dcu_init(struct fb_info *fbinfo, - unsigned int xres, - unsigned int yres, - const char *port, - struct fb_videomode *dcu_fb_videomode) -{ - const char *name; - unsigned int pixel_format; - int ret; - u8 ch; - - /* Mux I2C3+I2C4 as HSYNC+VSYNC */ -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - - /* QIXIS device mount on I2C1 bus*/ - ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_QIXIS_ADDR, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - 0); - return ret; - } - ret = dm_i2c_read(dev, QIXIS_DCU_BRDCFG5, &ch, 1); - if (ret) { - printf("Error: failed to read I2C @%02x\n", - CONFIG_SYS_I2C_QIXIS_ADDR); - return ret; - } - ch &= 0x1F; - ch |= 0xA0; - ret = dm_i2c_write(dev, QIXIS_DCU_BRDCFG5, &ch, 1); - -#else - ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5, - 1, &ch, 1); - if (ret) { - printf("Error: failed to read I2C @%02x\n", - CONFIG_SYS_I2C_QIXIS_ADDR); - return ret; - } - ch &= 0x1F; - ch |= 0xA0; - ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5, - 1, &ch, 1); -#endif - if (ret) { - printf("Error: failed to write I2C @%02x\n", - CONFIG_SYS_I2C_QIXIS_ADDR); - return ret; - } - - if (strncmp(port, "hdmi", 4) == 0) { - unsigned long pixval; - - name = "HDMI"; - - pixval = 1000000000 / dcu_fb_videomode->pixclock; - pixval *= 1000; - -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM); -#endif - select_i2c_ch_pca9547(I2C_MUX_CH_CH7301, - CONFIG_SYS_I2C_DVI_BUS_NUM); - diu_set_dvi_encoder(pixval); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, - CONFIG_SYS_I2C_DVI_BUS_NUM); - } else { - return 0; - } - - printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres); - - pixel_format = 32; - fsl_dcu_init(fbinfo, xres, yres, pixel_format); - - return 0; -} diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile index d9a2f52f2b6..cfa6c0c8540 100644 --- a/board/freescale/ls1021atwr/Makefile +++ b/board/freescale/ls1021atwr/Makefile @@ -5,5 +5,4 @@ # obj-y += ls1021atwr.o -obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021atwr/dcu.c b/board/freescale/ls1021atwr/dcu.c deleted file mode 100644 index 7bf283e3d66..00000000000 --- a/board/freescale/ls1021atwr/dcu.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * FSL DCU Framebuffer driver - */ - -#include -#include -#include -#include "div64.h" -#include "../common/dcu_sii9022a.h" - -DECLARE_GLOBAL_DATA_PTR; - -unsigned int dcu_set_pixel_clock(unsigned int pixclock) -{ - unsigned long long div; - - div = (unsigned long long)(gd->bus_clk / 1000); - div *= (unsigned long long)pixclock; - do_div(div, 1000000000); - - return div; -} - -int platform_dcu_init(struct fb_info *fbinfo, - unsigned int xres, unsigned int yres, - const char *port, - struct fb_videomode *dcu_fb_videomode) -{ - const char *name; - unsigned int pixel_format; - - if (strncmp(port, "twr_lcd", 4) == 0) { - name = "TWR_LCD_RGB card"; - } else { - name = "HDMI"; - dcu_set_dvi_encoder(dcu_fb_videomode); - } - - printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres); - - pixel_format = 32; - fsl_dcu_init(fbinfo, xres, yres, pixel_format); - - return 0; -} diff --git a/board/toradex/colibri_vf/Makefile b/board/toradex/colibri_vf/Makefile index 6272a774963..9be2cbc037b 100644 --- a/board/toradex/colibri_vf/Makefile +++ b/board/toradex/colibri_vf/Makefile @@ -3,4 +3,3 @@ # Copyright 2013 Freescale Semiconductor, Inc. obj-y := colibri_vf.o -obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index c09591e5436..dcef2db360a 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -205,49 +204,6 @@ static void setup_iomux_gpio(void) } #endif -#ifdef CONFIG_VIDEO_FSL_DCU_FB -static void setup_iomux_fsl_dcu(void) -{ - static const iomux_v3_cfg_t dcu0_pads[] = { - VF610_PAD_PTE0__DCU0_HSYNC, - VF610_PAD_PTE1__DCU0_VSYNC, - VF610_PAD_PTE2__DCU0_PCLK, - VF610_PAD_PTE4__DCU0_DE, - VF610_PAD_PTE5__DCU0_R0, - VF610_PAD_PTE6__DCU0_R1, - VF610_PAD_PTE7__DCU0_R2, - VF610_PAD_PTE8__DCU0_R3, - VF610_PAD_PTE9__DCU0_R4, - VF610_PAD_PTE10__DCU0_R5, - VF610_PAD_PTE11__DCU0_R6, - VF610_PAD_PTE12__DCU0_R7, - VF610_PAD_PTE13__DCU0_G0, - VF610_PAD_PTE14__DCU0_G1, - VF610_PAD_PTE15__DCU0_G2, - VF610_PAD_PTE16__DCU0_G3, - VF610_PAD_PTE17__DCU0_G4, - VF610_PAD_PTE18__DCU0_G5, - VF610_PAD_PTE19__DCU0_G6, - VF610_PAD_PTE20__DCU0_G7, - VF610_PAD_PTE21__DCU0_B0, - VF610_PAD_PTE22__DCU0_B1, - VF610_PAD_PTE23__DCU0_B2, - VF610_PAD_PTE24__DCU0_B3, - VF610_PAD_PTE25__DCU0_B4, - VF610_PAD_PTE26__DCU0_B5, - VF610_PAD_PTE27__DCU0_B6, - VF610_PAD_PTE28__DCU0_B7, - }; - - imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads)); -} - -static void setup_tcon(void) -{ - setbits_le32(TCON0_BASE_ADDR, (1 << 29)); -} -#endif - static inline int is_colibri_vf61(void) { struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR; @@ -353,11 +309,6 @@ static void clock_init(void) CCM_CSCDR3_NFC_PRE_DIV(3)); clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, CCM_CSCMR2_RMII_CLK_SEL(2)); - -#ifdef CONFIG_VIDEO_FSL_DCU_FB - setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK); - setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK); -#endif } static void mscm_init(void) @@ -378,11 +329,6 @@ int board_early_init_f(void) setup_iomux_gpio(); #endif -#ifdef CONFIG_VIDEO_FSL_DCU_FB - setup_tcon(); - setup_iomux_fsl_dcu(); -#endif - return 0; } @@ -433,9 +379,6 @@ int checkboard(void) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { -#if defined(CONFIG_VIDEO_FSL_DCU_FB) && !defined(CONFIG_DM_VIDEO) - int ret = 0; -#endif #ifdef CONFIG_FDT_FIXUP_PARTITIONS static const struct node_info nodes[] = { { "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */ @@ -445,11 +388,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) puts(" Updating MTD partitions...\n"); fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); #endif -#if defined(CONFIG_VIDEO_FSL_DCU_FB) && !defined(CONFIG_DM_VIDEO) - ret = fsl_dcu_fixedfb_setup(blob); - if (ret) - return ret; -#endif return ft_common_board_setup(blob, bd); } diff --git a/board/toradex/colibri_vf/dcu.c b/board/toradex/colibri_vf/dcu.c deleted file mode 100644 index c688ed79ffd..00000000000 --- a/board/toradex/colibri_vf/dcu.c +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2017 Toradex AG - * - * FSL DCU platform driver - */ - -#include -#include -#include -#include -#include "div64.h" - -unsigned int dcu_set_pixel_clock(unsigned int pixclock) -{ - struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; - unsigned long long div; - - clrbits_le32(&ccm->cscmr1, CCM_CSCMR1_DCU0_CLK_SEL); - clrsetbits_le32(&ccm->cscdr3, - CCM_CSCDR3_DCU0_DIV_MASK | CCM_CSCDR3_DCU0_EN, - CCM_CSCDR3_DCU0_DIV(0) | CCM_CSCDR3_DCU0_EN); - div = (unsigned long long)(PLL1_PFD2_FREQ / 1000); - do_div(div, pixclock); - - return div; -} - -int platform_dcu_init(struct fb_info *fbinfo, - unsigned int xres, - unsigned int yres, - const char *port, - struct fb_videomode *dcu_fb_videomode) -{ - fsl_dcu_init(fbinfo, xres, yres, 32); - - return 0; -} diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index 8cf8a31beb0..99e6623b81e 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -101,7 +101,6 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set # CONFIG_VIDEO_BPP16 is not set -CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index d0745463b9a..743fd8bbb25 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -610,21 +610,6 @@ config VIDEO_IVYBRIDGE_IGD a special tool which configures the VGA ROM, but the graphics resolution can be selected in U-Boot. -config VIDEO_FSL_DCU_FB - bool "Enable Freescale Display Control Unit" - depends on VIDEO || DM_VIDEO - help - This enables support for Freescale Display Control Unit (DCU4) - module found on Freescale Vybrid and QorIQ family of SoCs. - -config VIDEO_FSL_DCU_MAX_FB_SIZE_MB - int "Freescale DCU framebuffer size" - depends on VIDEO_FSL_DCU_FB - default 4194304 - help - Set maximum framebuffer size to be used for Freescale Display - Controller Unit (DCU4). - source "drivers/video/rockchip/Kconfig" config VIDEO_ARM_MALIDP diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 16e5fd3bbbb..dc51e04f3de 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -49,7 +49,6 @@ obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o obj-$(CONFIG_VIDEO_DW_MIPI_DSI) += dw_mipi_dsi.o obj-$(CONFIG_VIDEO_EFI) += efi.o -obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o obj-$(CONFIG_VIDEO_IPUV3) += imx/ obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c deleted file mode 100644 index b8bd4727c96..00000000000 --- a/drivers/video/fsl_dcu_fb.c +++ /dev/null @@ -1,548 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2019 Toradex AG - * - * FSL DCU Framebuffer driver - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "videomodes.h" - -/* Convert the X,Y resolution pair into a single number */ -#define RESOLUTION(x, y) (((u32)(x) << 16) | (y)) - -#ifdef CONFIG_SYS_FSL_DCU_LE -#define dcu_read32 in_le32 -#define dcu_write32 out_le32 -#elif defined(CONFIG_SYS_FSL_DCU_BE) -#define dcu_read32 in_be32 -#define dcu_write32 out_be32 -#endif - -#define DCU_MODE_BLEND_ITER(x) ((x) << 20) -#define DCU_MODE_RASTER_EN (1 << 14) -#define DCU_MODE_NORMAL 1 -#define DCU_MODE_COLORBAR 3 -#define DCU_BGND_R(x) ((x) << 16) -#define DCU_BGND_G(x) ((x) << 8) -#define DCU_BGND_B(x) (x) -#define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16) -#define DCU_DISP_SIZE_DELTA_X(x) (x) -#define DCU_HSYN_PARA_BP(x) ((x) << 22) -#define DCU_HSYN_PARA_PW(x) ((x) << 11) -#define DCU_HSYN_PARA_FP(x) (x) -#define DCU_VSYN_PARA_BP(x) ((x) << 22) -#define DCU_VSYN_PARA_PW(x) ((x) << 11) -#define DCU_VSYN_PARA_FP(x) (x) -#define DCU_SYN_POL_INV_PXCK_FALL (1 << 6) -#define DCU_SYN_POL_NEG_REMAIN (0 << 5) -#define DCU_SYN_POL_INV_VS_LOW (1 << 1) -#define DCU_SYN_POL_INV_HS_LOW (1) -#define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16) -#define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8) -#define DCU_THRESHOLD_OUT_BUF_LOW(x) (x) -#define DCU_UPDATE_MODE_MODE (1 << 31) -#define DCU_UPDATE_MODE_READREG (1 << 30) - -#define DCU_CTRLDESCLN_1_HEIGHT(x) ((x) << 16) -#define DCU_CTRLDESCLN_1_WIDTH(x) (x) -#define DCU_CTRLDESCLN_2_POSY(x) ((x) << 16) -#define DCU_CTRLDESCLN_2_POSX(x) (x) -#define DCU_CTRLDESCLN_4_EN (1 << 31) -#define DCU_CTRLDESCLN_4_TILE_EN (1 << 30) -#define DCU_CTRLDESCLN_4_DATA_SEL_CLUT (1 << 29) -#define DCU_CTRLDESCLN_4_SAFETY_EN (1 << 28) -#define DCU_CTRLDESCLN_4_TRANS(x) ((x) << 20) -#define DCU_CTRLDESCLN_4_BPP(x) ((x) << 16) -#define DCU_CTRLDESCLN_4_RLE_EN (1 << 15) -#define DCU_CTRLDESCLN_4_LUOFFS(x) ((x) << 4) -#define DCU_CTRLDESCLN_4_BB_ON (1 << 2) -#define DCU_CTRLDESCLN_4_AB(x) (x) -#define DCU_CTRLDESCLN_5_CKMAX_R(x) ((x) << 16) -#define DCU_CTRLDESCLN_5_CKMAX_G(x) ((x) << 8) -#define DCU_CTRLDESCLN_5_CKMAX_B(x) (x) -#define DCU_CTRLDESCLN_6_CKMIN_R(x) ((x) << 16) -#define DCU_CTRLDESCLN_6_CKMIN_G(x) ((x) << 8) -#define DCU_CTRLDESCLN_6_CKMIN_B(x) (x) -#define DCU_CTRLDESCLN_7_TILE_VER(x) ((x) << 16) -#define DCU_CTRLDESCLN_7_TILE_HOR(x) (x) -#define DCU_CTRLDESCLN_8_FG_FCOLOR(x) (x) -#define DCU_CTRLDESCLN_9_BG_BCOLOR(x) (x) - -#define BPP_16_RGB565 4 -#define BPP_24_RGB888 5 -#define BPP_32_ARGB8888 6 - -DECLARE_GLOBAL_DATA_PTR; - -/* - * This setting is used for the TWR_LCD_RGB card - */ -static struct fb_videomode fsl_dcu_mode_480_272 = { - .name = "480x272-60", - .refresh = 60, - .xres = 480, - .yres = 272, - .pixclock = 91996, - .left_margin = 2, - .right_margin = 2, - .upper_margin = 1, - .lower_margin = 1, - .hsync_len = 41, - .vsync_len = 2, - .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED -}; - -/* - * This setting is used for Siliconimage SiI9022A HDMI - */ -static struct fb_videomode fsl_dcu_cea_mode_640_480 = { - .name = "640x480-60", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 39722, - .left_margin = 48, - .right_margin = 16, - .upper_margin = 33, - .lower_margin = 10, - .hsync_len = 96, - .vsync_len = 2, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, -}; - -static struct fb_videomode fsl_dcu_mode_640_480 = { - .name = "640x480-60", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 25175, - .left_margin = 40, - .right_margin = 24, - .upper_margin = 32, - .lower_margin = 11, - .hsync_len = 96, - .vsync_len = 2, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, -}; - -static struct fb_videomode fsl_dcu_mode_800_480 = { - .name = "800x480-60", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 33260, - .left_margin = 216, - .right_margin = 40, - .upper_margin = 35, - .lower_margin = 10, - .hsync_len = 128, - .vsync_len = 2, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, -}; - -static struct fb_videomode fsl_dcu_mode_1024_600 = { - .name = "1024x600-60", - .refresh = 60, - .xres = 1024, - .yres = 600, - .pixclock = 48000, - .left_margin = 104, - .right_margin = 43, - .upper_margin = 24, - .lower_margin = 20, - .hsync_len = 5, - .vsync_len = 5, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, -}; - -/* - * DCU register map - */ -struct dcu_reg { - u32 desc_cursor[4]; - u32 mode; - u32 bgnd; - u32 disp_size; - u32 hsyn_para; - u32 vsyn_para; - u32 synpol; - u32 threshold; - u32 int_status; - u32 int_mask; - u32 colbar[8]; - u32 div_ratio; - u32 sign_calc[2]; - u32 crc_val; - u8 res_064[0x6c-0x64]; - u32 parr_err_status1; - u8 res_070[0x7c-0x70]; - u32 parr_err_status3; - u32 mparr_err_status1; - u8 res_084[0x90-0x84]; - u32 mparr_err_status3; - u32 threshold_inp_buf[2]; - u8 res_09c[0xa0-0x9c]; - u32 luma_comp; - u32 chroma_red; - u32 chroma_green; - u32 chroma_blue; - u32 crc_pos; - u32 lyr_intpol_en; - u32 lyr_luma_comp; - u32 lyr_chrm_red; - u32 lyr_chrm_grn; - u32 lyr_chrm_blue; - u8 res_0c4[0xcc-0xc8]; - u32 update_mode; - u32 underrun; - u8 res_0d4[0x100-0xd4]; - u32 gpr; - u32 slr_l[2]; - u32 slr_disp_size; - u32 slr_hvsync_para; - u32 slr_pol; - u32 slr_l_transp[2]; - u8 res_120[0x200-0x120]; - u32 ctrldescl[DCU_LAYER_MAX_NUM][16]; -}; - -static void reset_total_layers(void) -{ - struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; - int i; - - for (i = 0; i < DCU_LAYER_MAX_NUM; i++) { - dcu_write32(®s->ctrldescl[i][0], 0); - dcu_write32(®s->ctrldescl[i][1], 0); - dcu_write32(®s->ctrldescl[i][2], 0); - dcu_write32(®s->ctrldescl[i][3], 0); - dcu_write32(®s->ctrldescl[i][4], 0); - dcu_write32(®s->ctrldescl[i][5], 0); - dcu_write32(®s->ctrldescl[i][6], 0); - dcu_write32(®s->ctrldescl[i][7], 0); - dcu_write32(®s->ctrldescl[i][8], 0); - dcu_write32(®s->ctrldescl[i][9], 0); - dcu_write32(®s->ctrldescl[i][10], 0); - } -} - -static int layer_ctrldesc_init(struct fb_info fbinfo, - int index, u32 pixel_format) -{ - struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; - unsigned int bpp = BPP_24_RGB888; - - dcu_write32(®s->ctrldescl[index][0], - DCU_CTRLDESCLN_1_HEIGHT(fbinfo.var.yres) | - DCU_CTRLDESCLN_1_WIDTH(fbinfo.var.xres)); - - dcu_write32(®s->ctrldescl[index][1], - DCU_CTRLDESCLN_2_POSY(0) | - DCU_CTRLDESCLN_2_POSX(0)); - - dcu_write32(®s->ctrldescl[index][2], - (unsigned int)fbinfo.screen_base); - - switch (pixel_format) { - case 16: - bpp = BPP_16_RGB565; - break; - case 24: - bpp = BPP_24_RGB888; - break; - case 32: - bpp = BPP_32_ARGB8888; - break; - default: - printf("unsupported color depth: %u\n", pixel_format); - } - - dcu_write32(®s->ctrldescl[index][3], - DCU_CTRLDESCLN_4_EN | - DCU_CTRLDESCLN_4_TRANS(0xff) | - DCU_CTRLDESCLN_4_BPP(bpp) | - DCU_CTRLDESCLN_4_AB(0)); - - dcu_write32(®s->ctrldescl[index][4], - DCU_CTRLDESCLN_5_CKMAX_R(0xff) | - DCU_CTRLDESCLN_5_CKMAX_G(0xff) | - DCU_CTRLDESCLN_5_CKMAX_B(0xff)); - dcu_write32(®s->ctrldescl[index][5], - DCU_CTRLDESCLN_6_CKMIN_R(0) | - DCU_CTRLDESCLN_6_CKMIN_G(0) | - DCU_CTRLDESCLN_6_CKMIN_B(0)); - - dcu_write32(®s->ctrldescl[index][6], - DCU_CTRLDESCLN_7_TILE_VER(0) | - DCU_CTRLDESCLN_7_TILE_HOR(0)); - - dcu_write32(®s->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0)); - dcu_write32(®s->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0)); - - return 0; -} - -int fsl_dcu_init(struct fb_info *fbinfo, unsigned int xres, - unsigned int yres, unsigned int pixel_format) -{ - struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; - unsigned int div, mode; -/* - * When DM_VIDEO is enabled reservation of framebuffer is done - * in advance during bind() call. - */ -#if !CONFIG_IS_ENABLED(DM_VIDEO) - fbinfo->screen_size = fbinfo->var.xres * fbinfo->var.yres * - (fbinfo->var.bits_per_pixel / 8); - - if (fbinfo->screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) { - fbinfo->screen_size = 0; - return -ENOMEM; - } - /* Reserve framebuffer at the end of memory */ - gd->fb_base = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size - fbinfo->screen_size; - fbinfo->screen_base = (char *)gd->fb_base; - - memset(fbinfo->screen_base, 0, fbinfo->screen_size); -#endif - - reset_total_layers(); - - dcu_write32(®s->disp_size, - DCU_DISP_SIZE_DELTA_Y(fbinfo->var.yres) | - DCU_DISP_SIZE_DELTA_X(fbinfo->var.xres / 16)); - - dcu_write32(®s->hsyn_para, - DCU_HSYN_PARA_BP(fbinfo->var.left_margin) | - DCU_HSYN_PARA_PW(fbinfo->var.hsync_len) | - DCU_HSYN_PARA_FP(fbinfo->var.right_margin)); - - dcu_write32(®s->vsyn_para, - DCU_VSYN_PARA_BP(fbinfo->var.upper_margin) | - DCU_VSYN_PARA_PW(fbinfo->var.vsync_len) | - DCU_VSYN_PARA_FP(fbinfo->var.lower_margin)); - - dcu_write32(®s->synpol, - DCU_SYN_POL_INV_PXCK_FALL | - DCU_SYN_POL_NEG_REMAIN | - DCU_SYN_POL_INV_VS_LOW | - DCU_SYN_POL_INV_HS_LOW); - - dcu_write32(®s->bgnd, - DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0)); - - dcu_write32(®s->mode, - DCU_MODE_BLEND_ITER(2) | - DCU_MODE_RASTER_EN); - - dcu_write32(®s->threshold, - DCU_THRESHOLD_LS_BF_VS(0x3) | - DCU_THRESHOLD_OUT_BUF_HIGH(0x78) | - DCU_THRESHOLD_OUT_BUF_LOW(0)); - - mode = dcu_read32(®s->mode); - dcu_write32(®s->mode, mode | DCU_MODE_NORMAL); - - layer_ctrldesc_init(*fbinfo, 0, pixel_format); - - div = dcu_set_pixel_clock(fbinfo->var.pixclock); - dcu_write32(®s->div_ratio, (div - 1)); - - dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG); - - return 0; -} - -ulong board_get_usable_ram_top(ulong total_size) -{ - return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB; -} - -int fsl_probe_common(struct fb_info *fbinfo, unsigned int *win_x, - unsigned int *win_y) -{ - const char *options; - unsigned int depth = 0, freq = 0; - - struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272; - - if (!video_get_video_mode(win_x, win_y, &depth, &freq, - &options)) - return -EINVAL; - - /* Find the monitor port, which is a required option */ - if (!options) - return -EINVAL; - - if (strncmp(options, "monitor=", 8) != 0) - return -EINVAL; - - switch (RESOLUTION(*win_x, *win_y)) { - case RESOLUTION(480, 272): - fsl_dcu_mode_db = &fsl_dcu_mode_480_272; - break; - case RESOLUTION(640, 480): - if (!strncmp(options, "monitor=hdmi", 12)) - fsl_dcu_mode_db = &fsl_dcu_cea_mode_640_480; - else - fsl_dcu_mode_db = &fsl_dcu_mode_640_480; - break; - case RESOLUTION(800, 480): - fsl_dcu_mode_db = &fsl_dcu_mode_800_480; - break; - case RESOLUTION(1024, 600): - fsl_dcu_mode_db = &fsl_dcu_mode_1024_600; - break; - default: - printf("unsupported resolution %ux%u\n", - *win_x, *win_y); - } - - fbinfo->var.xres = fsl_dcu_mode_db->xres; - fbinfo->var.yres = fsl_dcu_mode_db->yres; - fbinfo->var.bits_per_pixel = 32; - fbinfo->var.pixclock = fsl_dcu_mode_db->pixclock; - fbinfo->var.left_margin = fsl_dcu_mode_db->left_margin; - fbinfo->var.right_margin = fsl_dcu_mode_db->right_margin; - fbinfo->var.upper_margin = fsl_dcu_mode_db->upper_margin; - fbinfo->var.lower_margin = fsl_dcu_mode_db->lower_margin; - fbinfo->var.hsync_len = fsl_dcu_mode_db->hsync_len; - fbinfo->var.vsync_len = fsl_dcu_mode_db->vsync_len; - fbinfo->var.sync = fsl_dcu_mode_db->sync; - fbinfo->var.vmode = fsl_dcu_mode_db->vmode; - fbinfo->fix.line_length = fbinfo->var.xres * - fbinfo->var.bits_per_pixel / 8; - - return platform_dcu_init(fbinfo, *win_x, *win_y, - options + 8, fsl_dcu_mode_db); -} - -#ifndef CONFIG_DM_VIDEO -static struct fb_info info; - -#if defined(CONFIG_OF_BOARD_SETUP) -int fsl_dcu_fixedfb_setup(void *blob) -{ - u64 start, size; - int ret; - - start = gd->bd->bi_dram[0].start; - size = gd->bd->bi_dram[0].size - info.screen_size; - - /* - * Align size on section size (1 MiB). - */ - size &= 0xfff00000; - ret = fdt_fixup_memory_banks(blob, &start, &size, 1); - if (ret) { - eprintf("Cannot setup fb: Error reserving memory\n"); - return ret; - } - - return 0; -} -#endif - -void *video_hw_init(void) -{ - static GraphicDevice ctfb; - - if (fsl_probe_common(&info, &ctfb.winSizeX, &ctfb.winSizeY) < 0) - return NULL; - - ctfb.frameAdrs = (unsigned int)info.screen_base; - ctfb.plnSizeX = ctfb.winSizeX; - ctfb.plnSizeY = ctfb.winSizeY; - - ctfb.gdfBytesPP = 4; - ctfb.gdfIndex = GDF_32BIT_X888RGB; - - ctfb.memSize = info.screen_size; - - return &ctfb; -} - -#else /* ifndef CONFIG_DM_VIDEO */ - -static int fsl_dcu_video_probe(struct udevice *dev) -{ - struct video_uc_plat *plat = dev_get_uclass_plat(dev); - struct video_priv *uc_priv = dev_get_uclass_priv(dev); - struct fb_info fbinfo = { 0 }; - unsigned int win_x; - unsigned int win_y; - u32 fb_start, fb_end; - int ret = 0; - - fb_start = plat->base & ~(MMU_SECTION_SIZE - 1); - fb_end = plat->base + plat->size; - fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT); - - fbinfo.screen_base = (char *)fb_start; - fbinfo.screen_size = plat->size; - - ret = fsl_probe_common(&fbinfo, &win_x, &win_y); - if (ret < 0) - return ret; - - uc_priv->bpix = VIDEO_BPP32; - uc_priv->xsize = win_x; - uc_priv->ysize = win_y; - - /* Enable dcache for the frame buffer */ - mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start, - DCACHE_WRITEBACK); - video_set_flush_dcache(dev, true); - return ret; -} - -static int fsl_dcu_video_bind(struct udevice *dev) -{ - struct video_uc_plat *plat = dev_get_uclass_plat(dev); - unsigned int win_x; - unsigned int win_y; - unsigned int depth = 0, freq = 0; - const char *options; - int ret = 0; - - ret = video_get_video_mode(&win_x, &win_y, &depth, &freq, &options); - if (ret < 0) - return ret; - - plat->size = win_x * win_y * 32; - - return 0; -} - -static const struct udevice_id fsl_dcu_video_ids[] = { - { .compatible = "fsl,vf610-dcu" }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(fsl_dcu_video) = { - .name = "fsl_dcu_video", - .id = UCLASS_VIDEO, - .of_match = fsl_dcu_video_ids, - .bind = fsl_dcu_video_bind, - .probe = fsl_dcu_video_probe, - .flags = DM_FLAG_PRE_RELOC, -}; -#endif /* ifndef CONFIG_DM_VIDEO */ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 3711e429a70..2e7b640357e 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -14,13 +14,6 @@ #include #include -#ifdef CONFIG_VIDEO_FSL_DCU_FB -#define CONFIG_SYS_FSL_DCU_LE - -#define CONFIG_SYS_DCU_ADDR DCU0_BASE_ADDR -#define DCU_LAYER_MAX_NUM 64 -#endif - /* NAND support */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 4c53de9bc4b..6a27111465f 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -299,16 +299,6 @@ * MMC */ -/* - * Video - */ -#ifdef CONFIG_VIDEO_FSL_DCU_FB -#define CONFIG_FSL_DIU_CH7301 -#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 -#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 -#define CONFIG_SYS_I2C_DVI_ADDR 0x75 -#endif - /* * eTSEC */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index e1762889809..03a4ce51994 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -185,19 +185,6 @@ #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 1 -/* - * MMC - */ - -/* - * Video - */ -#ifdef CONFIG_VIDEO_FSL_DCU_FB -#define CONFIG_FSL_DCU_SII9022A -#define CONFIG_SYS_I2C_DVI_BUS_NUM 1 -#define CONFIG_SYS_I2C_DVI_ADDR 0x39 -#endif - /* PCIe */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ diff --git a/include/fsl_dcu_fb.h b/include/fsl_dcu_fb.h deleted file mode 100644 index 7a5347a9247..00000000000 --- a/include/fsl_dcu_fb.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * FSL DCU Framebuffer driver - */ -#include - -int fsl_dcu_init(struct fb_info *fbinfo, - unsigned int xres, - unsigned int yres, - unsigned int pixel_format); - -int fsl_dcu_fixedfb_setup(void *blob); - -/* Prototypes for external board-specific functions */ -int platform_dcu_init(struct fb_info *fbinfo, - unsigned int xres, - unsigned int yres, - const char *port, - struct fb_videomode *dcu_fb_videomode); -unsigned int dcu_set_pixel_clock(unsigned int pixclock); diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 273f1f160df..62fce7cb300 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -157,7 +157,6 @@ CONFIG_FPGA_STRATIX_V CONFIG_FSL_CADMUS CONFIG_FSL_CORENET CONFIG_FSL_CPLD -CONFIG_FSL_DCU_SII9022A CONFIG_FSL_DEVICE_DISABLE CONFIG_FSL_DIU_CH7301 CONFIG_FSL_DIU_FB @@ -1131,8 +1130,6 @@ CONFIG_SYS_FSL_DCSR_DDR2_ADDR CONFIG_SYS_FSL_DCSR_DDR3_ADDR CONFIG_SYS_FSL_DCSR_DDR4_ADDR CONFIG_SYS_FSL_DCSR_DDR_ADDR -CONFIG_SYS_FSL_DCU_BE -CONFIG_SYS_FSL_DCU_LE CONFIG_SYS_FSL_DDR2_ADDR CONFIG_SYS_FSL_DDR3_ADDR CONFIG_SYS_FSL_DDR_ADDR -- cgit v1.3.1 From 92e3fb8b5e7fbace4b347bfa0f97bf9c06ed97c9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 23 Jan 2022 07:04:12 -0700 Subject: video: Drop FSL DIU driver This does not use driver model and is more than two years past the migration date. Drop it. It can be added back later if needed. Signed-off-by: Simon Glass --- README | 13 -- board/freescale/common/Makefile | 2 - board/freescale/common/diu_ch7301.c | 217 ------------------- board/freescale/common/diu_ch7301.h | 12 -- board/freescale/t104xrdb/Makefile | 1 - board/freescale/t104xrdb/diu.c | 83 -------- drivers/video/Makefile | 1 - drivers/video/fsl_diu_fb.c | 415 ------------------------------------ include/configs/T102xRDB.h | 11 - include/configs/T104xRDB.h | 19 -- include/fsl_diu_fb.h | 14 -- scripts/config_whitelist.txt | 3 - 12 files changed, 791 deletions(-) delete mode 100644 board/freescale/common/diu_ch7301.c delete mode 100644 board/freescale/common/diu_ch7301.h delete mode 100644 board/freescale/t104xrdb/diu.c delete mode 100644 drivers/video/fsl_diu_fb.c delete mode 100644 include/fsl_diu_fb.h (limited to 'drivers') diff --git a/README b/README index 138de72ffc6..8b05bfb53a1 100644 --- a/README +++ b/README @@ -970,19 +970,6 @@ The following options need to be configured: - Keyboard Support: See Kconfig help for available keyboard drivers. -- Video support: - CONFIG_FSL_DIU_FB - Enable the Freescale DIU video driver. Reference boards for - SOCs that have a DIU should define this macro to enable DIU - support, and should also define these other macros: - - CONFIG_SYS_DIU_ADDR - - The DIU driver will look for the 'video-mode' environment - variable, and if defined, enable the DIU as a console during - boot. See the documentation file doc/README.video for a - description of this variable. - - LCD Support: CONFIG_LCD Define this to enable LCD support (for output to LCD diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index c8f62bfc198..f13965daf2e 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -44,8 +44,6 @@ ifndef CONFIG_RAMBOOT_PBL obj-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o endif -obj-$(CONFIG_FSL_DIU_CH7301) += diu_ch7301.o - ifdef CONFIG_ARM obj-$(CONFIG_DEEP_SLEEP) += arm_sleep.o else diff --git a/board/freescale/common/diu_ch7301.c b/board/freescale/common/diu_ch7301.c deleted file mode 100644 index 05e6a3acf11..00000000000 --- a/board/freescale/common/diu_ch7301.c +++ /dev/null @@ -1,217 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2019 NXP - * Authors: Priyanka Jain - * Wang Dongsheng - * - * This file is copied and modified from the original t1040qds/diu.c. - * Encoder can be used in T104x and LSx Platform. - */ - -#include -#include -#include -#include - -#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F -#define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33 -#define I2C_DVI_PLL_DIVIDER_REG 0x34 -#define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35 -#define I2C_DVI_PLL_FILTER_REG 0x36 -#define I2C_DVI_TEST_PATTERN_REG 0x48 -#define I2C_DVI_POWER_MGMT_REG 0x49 -#define I2C_DVI_LOCK_STATE_REG 0x4D -#define I2C_DVI_SYNC_POLARITY_REG 0x56 - -/* - * Set VSYNC/HSYNC to active high. This is polarity of sync signals - * from DIU->DVI. The DIU default is active igh, so DVI is set to - * active high. - */ -#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98 - -#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06 -#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26 -#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0 -#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08 -#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16 -#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60 - -/* Clear test pattern */ -#define I2C_DVI_TEST_PATTERN_VAL 0x18 -/* Exit Power-down mode */ -#define I2C_DVI_POWER_MGMT_VAL 0xC0 - -/* Monitor polarity is handled via DVI Sync Polarity Register */ -#define I2C_DVI_SYNC_POLARITY_VAL 0x00 - -/* Programming of HDMI Chrontel CH7301 connector */ -int diu_set_dvi_encoder(unsigned int pixclock) -{ - int ret; - u8 temp; - - temp = I2C_DVI_TEST_PATTERN_VAL; -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM, - CONFIG_SYS_I2C_DVI_ADDR, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - CONFIG_SYS_I2C_DVI_BUS_NUM); - return ret; - } - ret = dm_i2c_write(dev, I2C_DVI_TEST_PATTERN_REG, &temp, 1); - if (ret) { - puts("I2C: failed to select proper dvi test pattern\n"); - return ret; - } - temp = I2C_DVI_INPUT_DATA_FORMAT_VAL; - ret = dm_i2c_write(dev, I2C_DVI_INPUT_DATA_FORMAT_REG, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi input data format\n"); - return ret; - } - - /* Set Sync polarity register */ - temp = I2C_DVI_SYNC_POLARITY_VAL; - ret = dm_i2c_write(dev, I2C_DVI_SYNC_POLARITY_REG, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi syc polarity\n"); - return ret; - } - - /* Set PLL registers based on pixel clock rate*/ - if (pixclock > 65000000) { - temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL; - ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll charge_cntl\n"); - return ret; - } - temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL; - ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll divider\n"); - return ret; - } - temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL; - ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll filter\n"); - return ret; - } - } else { - temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL; - ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll charge_cntl\n"); - return ret; - } - temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL; - ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll divider\n"); - return ret; - } - temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL; - ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll filter\n"); - return ret; - } - } - - temp = I2C_DVI_POWER_MGMT_VAL; - ret = dm_i2c_write(dev, I2C_DVI_POWER_MGMT_REG, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi power mgmt\n"); - return ret; - } -#else - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1, - &temp, 1); - if (ret) { - puts("I2C: failed to select proper dvi test pattern\n"); - return ret; - } - temp = I2C_DVI_INPUT_DATA_FORMAT_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG, - 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi input data format\n"); - return ret; - } - - /* Set Sync polarity register */ - temp = I2C_DVI_SYNC_POLARITY_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1, - &temp, 1); - if (ret) { - puts("I2C: failed to select dvi syc polarity\n"); - return ret; - } - - /* Set PLL registers based on pixel clock rate*/ - if (pixclock > 65000000) { - temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll charge_cntl\n"); - return ret; - } - temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll divider\n"); - return ret; - } - temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll filter\n"); - return ret; - } - } else { - temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll charge_cntl\n"); - return ret; - } - temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll divider\n"); - return ret; - } - temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll filter\n"); - return ret; - } - } - - temp = I2C_DVI_POWER_MGMT_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1, - &temp, 1); - if (ret) { - puts("I2C: failed to select dvi power mgmt\n"); - return ret; - } -#endif - - udelay(500); - - return 0; -} diff --git a/board/freescale/common/diu_ch7301.h b/board/freescale/common/diu_ch7301.h deleted file mode 100644 index f35661cdc49..00000000000 --- a/board/freescale/common/diu_ch7301.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DIU_HDMI_CH7301__ -#define __DIU_HDMI_CH7301__ - -/* Programming of HDMI Chrontel CH7301 connector */ -int diu_set_dvi_encoder(unsigned int pixclock); - -#endif diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile index d67e9412ecd..a9495019430 100644 --- a/board/freescale/t104xrdb/Makefile +++ b/board/freescale/t104xrdb/Makefile @@ -8,7 +8,6 @@ else obj-y += t104xrdb.o obj-y += cpld.o obj-y += eth.o -obj-$(CONFIG_FSL_DIU_FB)+= diu.o endif obj-y += ddr.o obj-y += law.o diff --git a/board/freescale/t104xrdb/diu.c b/board/freescale/t104xrdb/diu.c deleted file mode 100644 index 022d329713e..00000000000 --- a/board/freescale/t104xrdb/diu.c +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Author: Priyanka Jain - */ - -#include -#include -#include -#include -#include -#include - -#include "../common/diu_ch7301.h" - -#include "cpld.h" -#include "t104xrdb.h" - -/* - * DIU Area Descriptor - * - * Note that we need to byte-swap the value before it's written to the AD - * register. So even though the registers don't look like they're in the same - * bit positions as they are on the MPC8610, the same value is written to the - * AD register on the MPC8610 and on the P1022. - */ -#define AD_BYTE_F 0x10000000 -#define AD_ALPHA_C_SHIFT 25 -#define AD_BLUE_C_SHIFT 23 -#define AD_GREEN_C_SHIFT 21 -#define AD_RED_C_SHIFT 19 -#define AD_PIXEL_S_SHIFT 16 -#define AD_COMP_3_SHIFT 12 -#define AD_COMP_2_SHIFT 8 -#define AD_COMP_1_SHIFT 4 -#define AD_COMP_0_SHIFT 0 - -void diu_set_pixel_clock(unsigned int pixclock) -{ - unsigned long speed_ccb, temp; - u32 pixval; - int ret; - - speed_ccb = get_bus_freq(0); - temp = 1000000000 / pixclock; - temp *= 1000; - pixval = speed_ccb / temp; - - /* Program HDMI encoder */ - ret = diu_set_dvi_encoder(temp); - if (ret) { - puts("Failed to set DVI encoder\n"); - return; - } - - /* Program pixel clock */ - out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, - ((pixval << PXCK_BITS_START) & PXCK_MASK)); - - /* enable clock*/ - out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK | - ((pixval << PXCK_BITS_START) & PXCK_MASK)); -} - -int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) -{ - u32 pixel_format; - u8 sw; - - /*Configure Display ouput port as HDMI*/ - sw = CPLD_READ(sfp_ctl_status); - CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP)); - - pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | - (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | - (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | - (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | - (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); - - printf("DIU: Switching to monitor DVI @ %ux%u\n", xres, yres); - - return fsl_diu_init(xres, yres, pixel_format, 0); -} diff --git a/drivers/video/Makefile b/drivers/video/Makefile index dc51e04f3de..616e76f584f 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -31,7 +31,6 @@ obj-y += ti/ obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o obj-$(CONFIG_FORMIKE) += formike.o -obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o obj-$(CONFIG_IHS_VIDEO_OUT) += ihs_video_out.o obj-$(CONFIG_LD9040) += ld9040.o obj-$(CONFIG_LG4573) += lg4573.o diff --git a/drivers/video/fsl_diu_fb.c b/drivers/video/fsl_diu_fb.c deleted file mode 100644 index 6e335b5f43d..00000000000 --- a/drivers/video/fsl_diu_fb.c +++ /dev/null @@ -1,415 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. - * Authors: York Sun - * Timur Tabi - * - * FSL DIU Framebuffer driver - */ - -#include -#include -#include - -#include "videomodes.h" -#include -#include -#include - -/* This setting is used for the ifm pdm360ng with PRIMEVIEW PM070WL3 */ -static struct fb_videomode fsl_diu_mode_800_480 = { - .name = "800x480-60", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 31250, - .left_margin = 86, - .right_margin = 42, - .upper_margin = 33, - .lower_margin = 10, - .hsync_len = 128, - .vsync_len = 2, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED -}; - -/* For the SHARP LQ084S3LG01, used on the P1022DS board */ -static struct fb_videomode fsl_diu_mode_800_600 = { - .name = "800x600-60", - .refresh = 60, - .xres = 800, - .yres = 600, - .pixclock = 25000, - .left_margin = 88, - .right_margin = 40, - .upper_margin = 23, - .lower_margin = 1, - .hsync_len = 128, - .vsync_len = 4, - .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED -}; - -/* - * These parameters give default parameters - * for video output 1024x768, - * FIXME - change timing to proper amounts - * hsync 31.5kHz, vsync 60Hz - */ -static struct fb_videomode fsl_diu_mode_1024_768 = { - .name = "1024x768-60", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 160, - .right_margin = 24, - .upper_margin = 29, - .lower_margin = 3, - .hsync_len = 136, - .vsync_len = 6, - .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED -}; - -static struct fb_videomode fsl_diu_mode_1280_1024 = { - .name = "1280x1024-60", - .refresh = 60, - .xres = 1280, - .yres = 1024, - .pixclock = 9375, - .left_margin = 38, - .right_margin = 128, - .upper_margin = 2, - .lower_margin = 7, - .hsync_len = 216, - .vsync_len = 37, - .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED -}; - -static struct fb_videomode fsl_diu_mode_1280_720 = { - .name = "1280x720-60", - .refresh = 60, - .xres = 1280, - .yres = 720, - .pixclock = 13426, - .left_margin = 192, - .right_margin = 64, - .upper_margin = 22, - .lower_margin = 1, - .hsync_len = 136, - .vsync_len = 3, - .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED -}; - -static struct fb_videomode fsl_diu_mode_1920_1080 = { - .name = "1920x1080-60", - .refresh = 60, - .xres = 1920, - .yres = 1080, - .pixclock = 5787, - .left_margin = 328, - .right_margin = 120, - .upper_margin = 34, - .lower_margin = 1, - .hsync_len = 208, - .vsync_len = 3, - .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED -}; - -/* - * These are the fields of area descriptor(in DDR memory) for every plane - */ -struct diu_ad { - /* Word 0(32-bit) in DDR memory */ - __le32 pix_fmt; /* hard coding pixel format */ - /* Word 1(32-bit) in DDR memory */ - __le32 addr; - /* Word 2(32-bit) in DDR memory */ - __le32 src_size_g_alpha; - /* Word 3(32-bit) in DDR memory */ - __le32 aoi_size; - /* Word 4(32-bit) in DDR memory */ - __le32 offset_xyi; - /* Word 5(32-bit) in DDR memory */ - __le32 offset_xyd; - /* Word 6(32-bit) in DDR memory */ - __le32 ckmax_r:8; - __le32 ckmax_g:8; - __le32 ckmax_b:8; - __le32 res9:8; - /* Word 7(32-bit) in DDR memory */ - __le32 ckmin_r:8; - __le32 ckmin_g:8; - __le32 ckmin_b:8; - __le32 res10:8; - /* Word 8(32-bit) in DDR memory */ - __le32 next_ad; - /* Word 9(32-bit) in DDR memory, just for 64-bit aligned */ - __le32 res[3]; -} __attribute__ ((packed)); - -/* - * DIU register map - */ -struct diu { - __be32 desc[3]; - __be32 gamma; - __be32 pallete; - __be32 cursor; - __be32 curs_pos; - __be32 diu_mode; - __be32 bgnd; - __be32 bgnd_wb; - __be32 disp_size; - __be32 wb_size; - __be32 wb_mem_addr; - __be32 hsyn_para; - __be32 vsyn_para; - __be32 syn_pol; - __be32 thresholds; - __be32 int_status; - __be32 int_mask; - __be32 colorbar[8]; - __be32 filling; - __be32 plut; -} __attribute__ ((packed)); - -struct diu_addr { - void *vaddr; /* Virtual address */ - u32 paddr; /* 32-bit physical address */ - unsigned int offset; /* Alignment offset */ -}; - -static struct fb_info info; - -/* - * Align to 64-bit(8-byte), 32-byte, etc. - */ -static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align) -{ - u32 offset, ssize; - u32 mask; - - ssize = size + bytes_align; - buf->vaddr = malloc(ssize); - if (!buf->vaddr) - return -1; - - memset(buf->vaddr, 0, ssize); - mask = bytes_align - 1; - offset = (u32)buf->vaddr & mask; - if (offset) { - buf->offset = bytes_align - offset; - buf->vaddr += offset; - } else - buf->offset = 0; - - buf->paddr = virt_to_phys(buf->vaddr); - return 0; -} - -/* - * Allocate a framebuffer and an Area Descriptor that points to it. Both - * are created in the same memory block. The Area Descriptor is updated to - * point to the framebuffer memory. Memory is aligned as needed. - */ -static struct diu_ad *allocate_fb(unsigned int xres, unsigned int yres, - unsigned int depth, char **fb) -{ - unsigned long size = xres * yres * depth; - struct diu_addr addr; - struct diu_ad *ad; - size_t ad_size = roundup(sizeof(struct diu_ad), 32); - - /* - * Allocate a memory block that holds the Area Descriptor and the - * frame buffer right behind it. To keep the code simple, everything - * is aligned on a 32-byte address. - */ - if (allocate_buf(&addr, ad_size + size, 32) < 0) - return NULL; - - ad = addr.vaddr; - ad->addr = cpu_to_le32(addr.paddr + ad_size); - ad->aoi_size = cpu_to_le32((yres << 16) | xres); - ad->src_size_g_alpha = cpu_to_le32((yres << 12) | xres); - ad->offset_xyi = 0; - ad->offset_xyd = 0; - - if (fb) - *fb = addr.vaddr + ad_size; - - return ad; -} - -int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int gamma_fix) -{ - struct fb_videomode *fsl_diu_mode_db; - struct diu_ad *ad; - struct diu *hw = (struct diu *)CONFIG_SYS_DIU_ADDR; - u8 *gamma_table_base; - unsigned int i, j; - struct diu_addr gamma; - struct diu_addr cursor; - -/* Convert the X,Y resolution pair into a single number */ -#define RESOLUTION(x, y) (((u32)(x) << 16) | (y)) - - switch (RESOLUTION(xres, yres)) { - case RESOLUTION(800, 480): - fsl_diu_mode_db = &fsl_diu_mode_800_480; - break; - case RESOLUTION(800, 600): - fsl_diu_mode_db = &fsl_diu_mode_800_600; - break; - case RESOLUTION(1024, 768): - fsl_diu_mode_db = &fsl_diu_mode_1024_768; - break; - case RESOLUTION(1280, 1024): - fsl_diu_mode_db = &fsl_diu_mode_1280_1024; - break; - case RESOLUTION(1280, 720): - fsl_diu_mode_db = &fsl_diu_mode_1280_720; - break; - case RESOLUTION(1920, 1080): - fsl_diu_mode_db = &fsl_diu_mode_1920_1080; - break; - default: - printf("DIU: Unsupported resolution %ux%u\n", xres, yres); - return -1; - } - - /* read mode info */ - info.var.xres = fsl_diu_mode_db->xres; - info.var.yres = fsl_diu_mode_db->yres; - info.var.bits_per_pixel = 32; - info.var.pixclock = fsl_diu_mode_db->pixclock; - info.var.left_margin = fsl_diu_mode_db->left_margin; - info.var.right_margin = fsl_diu_mode_db->right_margin; - info.var.upper_margin = fsl_diu_mode_db->upper_margin; - info.var.lower_margin = fsl_diu_mode_db->lower_margin; - info.var.hsync_len = fsl_diu_mode_db->hsync_len; - info.var.vsync_len = fsl_diu_mode_db->vsync_len; - info.var.sync = fsl_diu_mode_db->sync; - info.var.vmode = fsl_diu_mode_db->vmode; - info.fix.line_length = info.var.xres * info.var.bits_per_pixel / 8; - - /* Memory allocation for framebuffer */ - info.screen_size = - info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8); - ad = allocate_fb(info.var.xres, info.var.yres, - info.var.bits_per_pixel / 8, &info.screen_base); - if (!ad) { - printf("DIU: Out of memory\n"); - return -1; - } - - ad->pix_fmt = pixel_format; - - /* Disable chroma keying function */ - ad->ckmax_r = 0; - ad->ckmax_g = 0; - ad->ckmax_b = 0; - - ad->ckmin_r = 255; - ad->ckmin_g = 255; - ad->ckmin_b = 255; - - /* Initialize the gamma table */ - if (allocate_buf(&gamma, 256 * 3, 32) < 0) { - printf("DIU: Out of memory\n"); - return -1; - } - gamma_table_base = gamma.vaddr; - for (i = 0; i <= 2; i++) - for (j = 0; j < 256; j++) - *gamma_table_base++ = j; - - if (gamma_fix == 1) { /* fix the gamma */ - gamma_table_base = gamma.vaddr; - for (i = 0; i < 256 * 3; i++) { - gamma_table_base[i] = (gamma_table_base[i] << 2) - | ((gamma_table_base[i] >> 6) & 0x03); - } - } - - /* Initialize the cursor */ - if (allocate_buf(&cursor, 32 * 32 * 2, 32) < 0) { - printf("DIU: Can't alloc cursor data\n"); - return -1; - } - - /* Program DIU registers */ - out_be32(&hw->diu_mode, 0); /* Temporarily disable the DIU */ - - out_be32(&hw->gamma, gamma.paddr); - out_be32(&hw->cursor, cursor.paddr); - out_be32(&hw->bgnd, 0x007F7F7F); - out_be32(&hw->disp_size, info.var.yres << 16 | info.var.xres); - out_be32(&hw->hsyn_para, info.var.left_margin << 22 | - info.var.hsync_len << 11 | - info.var.right_margin); - - out_be32(&hw->vsyn_para, info.var.upper_margin << 22 | - info.var.vsync_len << 11 | - info.var.lower_margin); - - /* Pixel Clock configuration */ - diu_set_pixel_clock(info.var.pixclock); - - /* Set the frame buffers */ - out_be32(&hw->desc[0], virt_to_phys(ad)); - out_be32(&hw->desc[1], 0); - out_be32(&hw->desc[2], 0); - - /* Enable the DIU, set display to all three planes */ - out_be32(&hw->diu_mode, 1); - - return 0; -} - -void *video_hw_init(void) -{ - static GraphicDevice ctfb; - const char *options; - unsigned int depth = 0, freq = 0; - - if (!video_get_video_mode(&ctfb.winSizeX, &ctfb.winSizeY, &depth, &freq, - &options)) - return NULL; - - /* Find the monitor port, which is a required option */ - if (!options) - return NULL; - if (strncmp(options, "monitor=", 8) != 0) - return NULL; - - if (platform_diu_init(ctfb.winSizeX, ctfb.winSizeY, options + 8) < 0) - return NULL; - - /* fill in Graphic device struct */ - sprintf(ctfb.modeIdent, "%ix%ix%i %ikHz %iHz", - ctfb.winSizeX, ctfb.winSizeY, depth, 64, freq); - - ctfb.frameAdrs = (unsigned int)info.screen_base; - ctfb.plnSizeX = ctfb.winSizeX; - ctfb.plnSizeY = ctfb.winSizeY; - - ctfb.gdfBytesPP = 4; - ctfb.gdfIndex = GDF_32BIT_X888RGB; - - ctfb.isaBase = 0; - ctfb.pciBase = 0; - ctfb.memSize = info.screen_size; - - /* Cursor Start Address */ - ctfb.dprBase = 0; - ctfb.vprBase = 0; - ctfb.cprBase = 0; - - return &ctfb; -} diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 00fabd61634..1fa1fc09aaa 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -365,17 +365,6 @@ #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) -/* Video */ -#undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) -/* - * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so - * disable empty flash sector detection, which is I/O-intensive. - */ -#undef CONFIG_SYS_FLASH_EMPTY_INFO -#endif - /* I2C */ #define I2C_PCA6408_BUS_NUM 1 diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 16298a7eaa6..562f7b37ac7 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -345,18 +345,6 @@ #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) -#if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) -/* Video */ -#define CONFIG_FSL_DIU_FB - -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_FSL_DIU_CH7301 -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) -#endif -#endif - -/* I2C */ - /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 #define I2C_MUX_CH_DEFAULT 0x8 @@ -558,18 +546,11 @@ #define FDTFILE "t1042rdb/t1042d4rdb.dtb" #endif -#ifdef CONFIG_FSL_DIU_FB -#define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" -#else -#define DIU_ENVIRONMENT -#endif - #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ - "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ "tftpflash=tftpboot $loadaddr $uboot && " \ diff --git a/include/fsl_diu_fb.h b/include/fsl_diu_fb.h deleted file mode 100644 index 139851ba1a8..00000000000 --- a/include/fsl_diu_fb.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2007, 2011 Freescale Semiconductor, Inc. - * Authors: York Sun - * Timur Tabi - * - * FSL DIU Framebuffer driver - */ - -int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int gamma_fix); - -/* Prototypes for external board-specific functions */ -int platform_diu_init(unsigned int xres, unsigned int yres, const char *port); -void diu_set_pixel_clock(unsigned int pixclock); diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 62fce7cb300..ac0a949071e 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -158,8 +158,6 @@ CONFIG_FSL_CADMUS CONFIG_FSL_CORENET CONFIG_FSL_CPLD CONFIG_FSL_DEVICE_DISABLE -CONFIG_FSL_DIU_CH7301 -CONFIG_FSL_DIU_FB CONFIG_FSL_DSPI1 CONFIG_FSL_ESDHC_PIN_MUX CONFIG_FSL_FIXED_MMC_LOCATION @@ -988,7 +986,6 @@ CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS CONFIG_SYS_DIALOG_PMIC_I2C_ADDR CONFIG_SYS_DIRECT_FLASH_TFTP CONFIG_SYS_DISCOVER_PHY -CONFIG_SYS_DIU_ADDR CONFIG_SYS_DPAA_DCE CONFIG_SYS_DPAA_FMAN CONFIG_SYS_DPAA_PME -- cgit v1.3.1 From bfd7a1a33cf120dce6154b42643aabb05ec444d5 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 23 Jan 2022 07:04:13 -0700 Subject: video: mxs: Drop old video code This is no-longer used and is the last reference to video_hw_init(). Drop it. Signed-off-by: Simon Glass --- drivers/video/mxsfb.c | 89 --------------------------------------------------- 1 file changed, 89 deletions(-) (limited to 'drivers') diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 99a15e0c25d..10433949bb8 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -252,94 +252,6 @@ static int mxs_remove_common(u32 fb) return 0; } -#ifndef CONFIG_DM_VIDEO - -static GraphicDevice panel; - -void lcdif_power_down(void) -{ - mxs_remove_common(panel.frameAdrs); -} - -void *video_hw_init(void) -{ - int bpp = -1; - int ret = 0; - char *penv; - void *fb = NULL; - struct ctfb_res_modes mode; - struct display_timing timings; - - puts("Video: "); - - /* Suck display configuration from "videomode" variable */ - penv = env_get("videomode"); - if (!penv) { - puts("MXSFB: 'videomode' variable not set!\n"); - return NULL; - } - - bpp = video_get_params(&mode, penv); - - /* fill in Graphic device struct */ - sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp); - - panel.winSizeX = mode.xres; - panel.winSizeY = mode.yres; - panel.plnSizeX = mode.xres; - panel.plnSizeY = mode.yres; - - switch (bpp) { - case 24: - case 18: - panel.gdfBytesPP = 4; - panel.gdfIndex = GDF_32BIT_X888RGB; - break; - case 16: - panel.gdfBytesPP = 2; - panel.gdfIndex = GDF_16BIT_565RGB; - break; - case 8: - panel.gdfBytesPP = 1; - panel.gdfIndex = GDF__8BIT_INDEX; - break; - default: - printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp); - return NULL; - } - - panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP; - - /* Allocate framebuffer */ - fb = memalign(ARCH_DMA_MINALIGN, - roundup(panel.memSize, ARCH_DMA_MINALIGN)); - if (!fb) { - printf("MXSFB: Error allocating framebuffer!\n"); - return NULL; - } - - /* Wipe framebuffer */ - memset(fb, 0, panel.memSize); - - panel.frameAdrs = (u32)fb; - - printf("%s\n", panel.modeIdent); - - video_ctfb_mode_to_display_timing(&mode, &timings); - - ret = mxs_probe_common(NULL, &timings, bpp, (u32)fb); - if (ret) - goto dealloc_fb; - - return (void *)&panel; - -dealloc_fb: - free(fb); - - return NULL; -} -#else /* ifndef CONFIG_DM_VIDEO */ - static int mxs_of_get_timings(struct udevice *dev, struct display_timing *timings, u32 *bpp) @@ -489,4 +401,3 @@ U_BOOT_DRIVER(mxs_video) = { .remove = mxs_video_remove, .flags = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE, }; -#endif /* ifndef CONFIG_DM_VIDEO */ -- cgit v1.3.1 From 2cbc1c019b3e63548a069427feeca7566ffe5915 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 23 Jan 2022 07:04:14 -0700 Subject: video: Convert CONFIG_VIDEO_BCM2835 to Kconfig This converts the following to Kconfig: CONFIG_VIDEO_BCM2835 This is the final ad-hoc CONFIG_VIDEO_... to convert. Signed-off-by: Simon Glass Acked-by: Matthias Brugger --- configs/rpi_0_w_defconfig | 1 + configs/rpi_2_defconfig | 1 + configs/rpi_3_32b_defconfig | 1 + configs/rpi_3_b_plus_defconfig | 1 + configs/rpi_3_defconfig | 1 + configs/rpi_4_32b_defconfig | 1 + configs/rpi_4_defconfig | 1 + configs/rpi_arm64_defconfig | 1 + configs/rpi_defconfig | 1 + drivers/video/Kconfig | 8 ++++++++ include/configs/rpi.h | 1 - scripts/config_whitelist.txt | 1 - 12 files changed, 17 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig index 195541c6e76..819618280f7 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig @@ -41,6 +41,7 @@ CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set # CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index eb63fbdd8d9..9ccd69cbd88 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -42,6 +42,7 @@ CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set # CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index 46102899f03..de4a14e69ce 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -45,6 +45,7 @@ CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set # CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig index 91b63b62721..1d4346c0ec8 100644 --- a/configs/rpi_3_b_plus_defconfig +++ b/configs/rpi_3_b_plus_defconfig @@ -44,6 +44,7 @@ CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set # CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index 528b12ea5b5..c7615403d33 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -44,6 +44,7 @@ CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set # CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index 8f87a4336d2..d9d9331f580 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -59,6 +59,7 @@ CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set # CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y CONFIG_ADDR_MAP=y diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index 461a7655ab9..eac55ccbcb8 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -59,6 +59,7 @@ CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set # CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index 351d247daeb..a0cbdbef02f 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -51,6 +51,7 @@ CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set # CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index 0baef3b6abf..bd4e3dc42d7 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -41,6 +41,7 @@ CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set # CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 743fd8bbb25..965b5879274 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -430,6 +430,14 @@ config ATMEL_LCD_BGR555 help Use the BGR555 output mode. Otherwise RGB565 is used. +config VIDEO_BCM2835 + bool "Display support for BCM2835" + help + The graphics processor already sets up the display so this driver + simply checks the resolution and then sets up the frame buffer with + that same resolution (or as near as possible) and 32bpp depth, so + that U-Boot can access it with full colour depth. + config VIDEO_LCD_ORISETECH_OTM8009A bool "OTM8009A DSI LCD panel support" depends on DM_VIDEO diff --git a/include/configs/rpi.h b/include/configs/rpi.h index d5e064fb379..c439ec1b302 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -44,7 +44,6 @@ /* GPIO */ #define CONFIG_BCM2835_GPIO /* LCD */ -#define CONFIG_VIDEO_BCM2835 /* DFU over USB/UDC */ #ifdef CONFIG_CMD_DFU diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index ac0a949071e..41c8baa6a7a 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2002,7 +2002,6 @@ CONFIG_USE_ONENAND_BOARD_INIT CONFIG_U_BOOT_HDR_SIZE CONFIG_VAR_SIZE_SPL CONFIG_VERY_BIG_RAM -CONFIG_VIDEO_BCM2835 CONFIG_VSC7385_ENET CONFIG_VSC7385_IMAGE CONFIG_VSC7385_IMAGE_SIZE -- cgit v1.3.1 From 39161e08803ff769002f69b68374949805a1000d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 23 Jan 2022 07:04:15 -0700 Subject: video: Drop formike driver This is not used. Drop it. Signed-off-by: Simon Glass --- drivers/video/Makefile | 1 - drivers/video/formike.c | 513 ------------------------------------------- scripts/config_whitelist.txt | 1 - 3 files changed, 515 deletions(-) delete mode 100644 drivers/video/formike.c (limited to 'drivers') diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 616e76f584f..259658074bc 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -30,7 +30,6 @@ obj-y += ti/ obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o -obj-$(CONFIG_FORMIKE) += formike.o obj-$(CONFIG_IHS_VIDEO_OUT) += ihs_video_out.o obj-$(CONFIG_LD9040) += ld9040.o obj-$(CONFIG_LG4573) += lg4573.o diff --git a/drivers/video/formike.c b/drivers/video/formike.c deleted file mode 100644 index 5cbe50d4cbd..00000000000 --- a/drivers/video/formike.c +++ /dev/null @@ -1,513 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * LCD: Formike, TFT 4.3", 480x800, RGB24, KWH043ST20-F01, DriverIC NT35510-16 - * LCD initialization via SPI - * Based on: - * - */ -#include -#include -#include -#include -#include - -#define TAG_READ 0x80 -#define TAG_WRITE 0x00 - -#define TAG_DATA 0x40 -#define TAG_COMMAND 0x00 - -#define TAG_ADDR_H 0x20 -#define TAG_ADDR_L 0x00 - -static int spi_write_tag_val(struct spi_slave *spi, unsigned char tag, - unsigned char val) -{ - unsigned long flags = SPI_XFER_BEGIN; - u8 buf[2]; - int ret; - - buf[0] = tag; - ret = spi_xfer(spi, 8, buf, NULL, flags); - buf[0] = val; - flags = SPI_XFER_END; - ret = spi_xfer(spi, 8, buf, NULL, flags); - -#ifdef KWH043ST20_F01_SPI_DEBUG - printf("spi_write_tag_val: tag=%02X, val=%02X ret: %d\n", - tag, val, ret); -#endif /* KWH043ST20_F01_SPI_DEBUG */ - if (ret) - debug("%s: Failed to send: %d\n", __func__, ret); - - return ret; -} - -static void spi_write_dat(struct spi_slave *spi, unsigned int val) -{ - spi_write_tag_val(spi, TAG_WRITE|TAG_DATA, val); -} - -static void spi_write_com(struct spi_slave *spi, unsigned int addr) -{ - spi_write_tag_val(spi, TAG_WRITE|TAG_COMMAND|TAG_ADDR_H, - (addr & 0xff00) >> 8); - spi_write_tag_val(spi, TAG_WRITE|TAG_COMMAND|TAG_ADDR_L, - (addr & 0x00ff) >> 0); -} - -int kwh043st20_f01_spi_startup(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int spi_mode) -{ - struct spi_slave *spi; - int ret; - - spi = spi_setup_slave(bus, cs, max_hz, spi_mode); - if (!spi) { - debug("%s: Failed to set up slave\n", __func__); - return -1; - } - - ret = spi_claim_bus(spi); - if (ret) { - debug("%s: Failed to claim SPI bus: %d\n", __func__, ret); - goto err_claim_bus; - } - - - /* LV2 Page 1 enable */ - spi_write_com(spi, 0xF000); spi_write_dat(spi, 0x55); - spi_write_com(spi, 0xF001); spi_write_dat(spi, 0xAA); - spi_write_com(spi, 0xF002); spi_write_dat(spi, 0x52); - spi_write_com(spi, 0xF003); spi_write_dat(spi, 0x08); - spi_write_com(spi, 0xF004); spi_write_dat(spi, 0x01); - - /* AVDD Set AVDD 5.2V */ - spi_write_com(spi, 0xB000); spi_write_dat(spi, 0x0D); - spi_write_com(spi, 0xB001); spi_write_dat(spi, 0x0D); - spi_write_com(spi, 0xB002); spi_write_dat(spi, 0x0D); - - /* AVDD ratio */ - spi_write_com(spi, 0xB600); spi_write_dat(spi, 0x34); - spi_write_com(spi, 0xB601); spi_write_dat(spi, 0x34); - spi_write_com(spi, 0xB602); spi_write_dat(spi, 0x34); - - /* AVEE -5.2V */ - spi_write_com(spi, 0xB100); spi_write_dat(spi, 0x0D); - spi_write_com(spi, 0xB101); spi_write_dat(spi, 0x0D); - spi_write_com(spi, 0xB102); spi_write_dat(spi, 0x0D); - - /* AVEE ratio */ - spi_write_com(spi, 0xB700); spi_write_dat(spi, 0x35); - spi_write_com(spi, 0xB701); spi_write_dat(spi, 0x35); - spi_write_com(spi, 0xB702); spi_write_dat(spi, 0x35); - - /* VCL -2.5V */ - spi_write_com(spi, 0xB200); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xB201); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xB202); spi_write_dat(spi, 0x00); - - /* VCL ratio */ - spi_write_com(spi, 0xB800); spi_write_dat(spi, 0x24); - spi_write_com(spi, 0xB801); spi_write_dat(spi, 0x24); - spi_write_com(spi, 0xB802); spi_write_dat(spi, 0x24); - - /* VGH 15V */ - spi_write_com(spi, 0xBF00); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xB300); spi_write_dat(spi, 0x08); - spi_write_com(spi, 0xB301); spi_write_dat(spi, 0x08); - spi_write_com(spi, 0xB302); spi_write_dat(spi, 0x08); - - /* VGH ratio */ - spi_write_com(spi, 0xB900); spi_write_dat(spi, 0x34); - spi_write_com(spi, 0xB901); spi_write_dat(spi, 0x34); - spi_write_com(spi, 0xB902); spi_write_dat(spi, 0x34); - - /* VGLX ratio */ - spi_write_com(spi, 0xBA00); spi_write_dat(spi, 0x24); - spi_write_com(spi, 0xBA01); spi_write_dat(spi, 0x24); - spi_write_com(spi, 0xBA02); spi_write_dat(spi, 0x24); - - /* VGMP/VGSP 4.7V/0V */ - spi_write_com(spi, 0xBC00); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xBC01); spi_write_dat(spi, 0x88); - spi_write_com(spi, 0xBC02); spi_write_dat(spi, 0x00); - - /* VGMN/VGSN -4.7V/0V */ - spi_write_com(spi, 0xBD00); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xBD01); spi_write_dat(spi, 0x88); - spi_write_com(spi, 0xBD02); spi_write_dat(spi, 0x00); - - /* VCOM 1.525V */ - spi_write_com(spi, 0xBE00); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xBE01); spi_write_dat(spi, 0x7A); - - /* Gamma Setting */ - spi_write_com(spi, 0xD100); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD101); spi_write_dat(spi, 0x05); - spi_write_com(spi, 0xD102); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD103); spi_write_dat(spi, 0x15); - spi_write_com(spi, 0xD104); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD105); spi_write_dat(spi, 0x30); - spi_write_com(spi, 0xD106); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD107); spi_write_dat(spi, 0x47); - spi_write_com(spi, 0xD108); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD109); spi_write_dat(spi, 0x5B); - spi_write_com(spi, 0xD10A); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD10B); spi_write_dat(spi, 0x7D); - spi_write_com(spi, 0xD10C); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD10D); spi_write_dat(spi, 0x9D); - spi_write_com(spi, 0xD10E); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD10F); spi_write_dat(spi, 0xCC); - spi_write_com(spi, 0xD110); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD111); spi_write_dat(spi, 0xF3); - spi_write_com(spi, 0xD112); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD113); spi_write_dat(spi, 0x32); - spi_write_com(spi, 0xD114); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD115); spi_write_dat(spi, 0x63); - spi_write_com(spi, 0xD116); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD117); spi_write_dat(spi, 0xB1); - spi_write_com(spi, 0xD118); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD119); spi_write_dat(spi, 0xF0); - spi_write_com(spi, 0xD11A); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD11B); spi_write_dat(spi, 0xF2); - spi_write_com(spi, 0xD11C); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD11D); spi_write_dat(spi, 0x2A); - spi_write_com(spi, 0xD11E); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD11F); spi_write_dat(spi, 0x67); - spi_write_com(spi, 0xD120); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD121); spi_write_dat(spi, 0x90); - spi_write_com(spi, 0xD122); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD123); spi_write_dat(spi, 0xCB); - spi_write_com(spi, 0xD124); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD125); spi_write_dat(spi, 0xF2); - spi_write_com(spi, 0xD126); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD127); spi_write_dat(spi, 0x2A); - spi_write_com(spi, 0xD128); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD129); spi_write_dat(spi, 0x51); - spi_write_com(spi, 0xD12A); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD12B); spi_write_dat(spi, 0x80); - spi_write_com(spi, 0xD12C); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD12D); spi_write_dat(spi, 0x9F); - spi_write_com(spi, 0xD12E); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD12F); spi_write_dat(spi, 0xBE); - spi_write_com(spi, 0xD130); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD131); spi_write_dat(spi, 0xF9); - spi_write_com(spi, 0xD132); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD133); spi_write_dat(spi, 0xFF); - - spi_write_com(spi, 0xD200); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD201); spi_write_dat(spi, 0x05); - spi_write_com(spi, 0xD202); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD203); spi_write_dat(spi, 0x15); - spi_write_com(spi, 0xD204); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD205); spi_write_dat(spi, 0x30); - spi_write_com(spi, 0xD206); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD207); spi_write_dat(spi, 0x47); - spi_write_com(spi, 0xD208); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD209); spi_write_dat(spi, 0x5B); - spi_write_com(spi, 0xD20A); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD20B); spi_write_dat(spi, 0x7D); - spi_write_com(spi, 0xD20C); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD20D); spi_write_dat(spi, 0x9D); - spi_write_com(spi, 0xD20E); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD20F); spi_write_dat(spi, 0xCC); - spi_write_com(spi, 0xD210); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD211); spi_write_dat(spi, 0xF3); - spi_write_com(spi, 0xD212); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD213); spi_write_dat(spi, 0x32); - spi_write_com(spi, 0xD214); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD215); spi_write_dat(spi, 0x63); - spi_write_com(spi, 0xD216); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD217); spi_write_dat(spi, 0xB1); - spi_write_com(spi, 0xD218); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD219); spi_write_dat(spi, 0xF0); - spi_write_com(spi, 0xD21A); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD21B); spi_write_dat(spi, 0xF2); - spi_write_com(spi, 0xD21C); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD21D); spi_write_dat(spi, 0x2A); - spi_write_com(spi, 0xD21E); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD21F); spi_write_dat(spi, 0x67); - spi_write_com(spi, 0xD220); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD221); spi_write_dat(spi, 0x90); - spi_write_com(spi, 0xD222); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD223); spi_write_dat(spi, 0xCB); - spi_write_com(spi, 0xD224); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD225); spi_write_dat(spi, 0xF2); - spi_write_com(spi, 0xD226); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD227); spi_write_dat(spi, 0x2A); - spi_write_com(spi, 0xD228); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD229); spi_write_dat(spi, 0x51); - spi_write_com(spi, 0xD22A); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD22B); spi_write_dat(spi, 0x80); - spi_write_com(spi, 0xD22C); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD22D); spi_write_dat(spi, 0x9F); - spi_write_com(spi, 0xD22E); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD22F); spi_write_dat(spi, 0xBE); - spi_write_com(spi, 0xD230); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD231); spi_write_dat(spi, 0xF9); - spi_write_com(spi, 0xD232); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD233); spi_write_dat(spi, 0xFF); - - spi_write_com(spi, 0xD300); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD301); spi_write_dat(spi, 0x05); - spi_write_com(spi, 0xD302); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD303); spi_write_dat(spi, 0x15); - spi_write_com(spi, 0xD304); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD305); spi_write_dat(spi, 0x30); - spi_write_com(spi, 0xD306); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD307); spi_write_dat(spi, 0x47); - spi_write_com(spi, 0xD308); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD309); spi_write_dat(spi, 0x5B); - spi_write_com(spi, 0xD30A); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD30B); spi_write_dat(spi, 0x7D); - spi_write_com(spi, 0xD30C); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD30D); spi_write_dat(spi, 0x9D); - spi_write_com(spi, 0xD30E); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD30F); spi_write_dat(spi, 0xCC); - spi_write_com(spi, 0xD310); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD311); spi_write_dat(spi, 0xF3); - spi_write_com(spi, 0xD312); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD313); spi_write_dat(spi, 0x32); - spi_write_com(spi, 0xD314); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD315); spi_write_dat(spi, 0x63); - spi_write_com(spi, 0xD316); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD317); spi_write_dat(spi, 0xB1); - spi_write_com(spi, 0xD318); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD319); spi_write_dat(spi, 0xF0); - spi_write_com(spi, 0xD31A); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD31B); spi_write_dat(spi, 0xF2); - spi_write_com(spi, 0xD31C); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD31D); spi_write_dat(spi, 0x2A); - spi_write_com(spi, 0xD31E); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD31F); spi_write_dat(spi, 0x67); - spi_write_com(spi, 0xD320); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD321); spi_write_dat(spi, 0x90); - spi_write_com(spi, 0xD322); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD323); spi_write_dat(spi, 0xCB); - spi_write_com(spi, 0xD324); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD325); spi_write_dat(spi, 0xF2); - spi_write_com(spi, 0xD326); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD327); spi_write_dat(spi, 0x2A); - spi_write_com(spi, 0xD328); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD329); spi_write_dat(spi, 0x51); - spi_write_com(spi, 0xD32A); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD32B); spi_write_dat(spi, 0x80); - spi_write_com(spi, 0xD32C); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD32D); spi_write_dat(spi, 0x9F); - spi_write_com(spi, 0xD32E); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD32F); spi_write_dat(spi, 0xBE); - spi_write_com(spi, 0xD330); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD331); spi_write_dat(spi, 0xF9); - spi_write_com(spi, 0xD332); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD333); spi_write_dat(spi, 0xFF); - - spi_write_com(spi, 0xD400); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD401); spi_write_dat(spi, 0x05); - spi_write_com(spi, 0xD402); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD403); spi_write_dat(spi, 0x15); - spi_write_com(spi, 0xD404); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD405); spi_write_dat(spi, 0x30); - spi_write_com(spi, 0xD406); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD407); spi_write_dat(spi, 0x47); - spi_write_com(spi, 0xD408); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD409); spi_write_dat(spi, 0x5B); - spi_write_com(spi, 0xD40A); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD40B); spi_write_dat(spi, 0x7D); - spi_write_com(spi, 0xD40C); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD40D); spi_write_dat(spi, 0x9D); - spi_write_com(spi, 0xD40E); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD40F); spi_write_dat(spi, 0xCC); - spi_write_com(spi, 0xD410); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD411); spi_write_dat(spi, 0xF3); - spi_write_com(spi, 0xD412); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD413); spi_write_dat(spi, 0x32); - spi_write_com(spi, 0xD414); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD415); spi_write_dat(spi, 0x63); - spi_write_com(spi, 0xD416); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD417); spi_write_dat(spi, 0xB1); - spi_write_com(spi, 0xD418); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD419); spi_write_dat(spi, 0xF0); - spi_write_com(spi, 0xD41A); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD41B); spi_write_dat(spi, 0xF2); - spi_write_com(spi, 0xD41C); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD41D); spi_write_dat(spi, 0x2A); - spi_write_com(spi, 0xD41E); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD41F); spi_write_dat(spi, 0x67); - spi_write_com(spi, 0xD420); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD421); spi_write_dat(spi, 0x90); - spi_write_com(spi, 0xD422); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD423); spi_write_dat(spi, 0xCB); - spi_write_com(spi, 0xD424); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD425); spi_write_dat(spi, 0xF2); - spi_write_com(spi, 0xD426); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD427); spi_write_dat(spi, 0x2A); - spi_write_com(spi, 0xD428); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD429); spi_write_dat(spi, 0x51); - spi_write_com(spi, 0xD42A); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD42B); spi_write_dat(spi, 0x80); - spi_write_com(spi, 0xD42C); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD42D); spi_write_dat(spi, 0x9F); - spi_write_com(spi, 0xD42E); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD42F); spi_write_dat(spi, 0xBE); - spi_write_com(spi, 0xD430); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD431); spi_write_dat(spi, 0xF9); - spi_write_com(spi, 0xD432); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD433); spi_write_dat(spi, 0xFF); - - spi_write_com(spi, 0xD500); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD501); spi_write_dat(spi, 0x05); - spi_write_com(spi, 0xD502); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD503); spi_write_dat(spi, 0x15); - spi_write_com(spi, 0xD504); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD505); spi_write_dat(spi, 0x30); - spi_write_com(spi, 0xD506); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD507); spi_write_dat(spi, 0x47); - spi_write_com(spi, 0xD508); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD509); spi_write_dat(spi, 0x5B); - spi_write_com(spi, 0xD50A); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD50B); spi_write_dat(spi, 0x7D); - spi_write_com(spi, 0xD50C); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD50D); spi_write_dat(spi, 0x9D); - spi_write_com(spi, 0xD50E); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD50F); spi_write_dat(spi, 0xCC); - spi_write_com(spi, 0xD510); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD511); spi_write_dat(spi, 0xF3); - spi_write_com(spi, 0xD512); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD513); spi_write_dat(spi, 0x32); - spi_write_com(spi, 0xD514); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD515); spi_write_dat(spi, 0x63); - spi_write_com(spi, 0xD516); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD517); spi_write_dat(spi, 0xB1); - spi_write_com(spi, 0xD518); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD519); spi_write_dat(spi, 0xF0); - spi_write_com(spi, 0xD51A); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD51B); spi_write_dat(spi, 0xF2); - spi_write_com(spi, 0xD51C); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD51D); spi_write_dat(spi, 0x2A); - spi_write_com(spi, 0xD51E); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD51F); spi_write_dat(spi, 0x67); - spi_write_com(spi, 0xD520); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD521); spi_write_dat(spi, 0x90); - spi_write_com(spi, 0xD522); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD523); spi_write_dat(spi, 0xCB); - spi_write_com(spi, 0xD524); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD525); spi_write_dat(spi, 0xF2); - spi_write_com(spi, 0xD526); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD527); spi_write_dat(spi, 0x2A); - spi_write_com(spi, 0xD528); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD529); spi_write_dat(spi, 0x51); - spi_write_com(spi, 0xD52A); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD52B); spi_write_dat(spi, 0x80); - spi_write_com(spi, 0xD52C); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD52D); spi_write_dat(spi, 0x9F); - spi_write_com(spi, 0xD52E); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD52F); spi_write_dat(spi, 0xBE); - spi_write_com(spi, 0xD530); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD531); spi_write_dat(spi, 0xF9); - spi_write_com(spi, 0xD532); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD533); spi_write_dat(spi, 0xFF); - - spi_write_com(spi, 0xD600); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD601); spi_write_dat(spi, 0x05); - spi_write_com(spi, 0xD602); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD603); spi_write_dat(spi, 0x15); - spi_write_com(spi, 0xD604); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD605); spi_write_dat(spi, 0x30); - spi_write_com(spi, 0xD606); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD607); spi_write_dat(spi, 0x47); - spi_write_com(spi, 0xD608); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD609); spi_write_dat(spi, 0x5B); - spi_write_com(spi, 0xD60A); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD60B); spi_write_dat(spi, 0x7D); - spi_write_com(spi, 0xD60C); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD60D); spi_write_dat(spi, 0x9D); - spi_write_com(spi, 0xD60E); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD60F); spi_write_dat(spi, 0xCC); - spi_write_com(spi, 0xD610); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xD611); spi_write_dat(spi, 0xF3); - spi_write_com(spi, 0xD612); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD613); spi_write_dat(spi, 0x32); - spi_write_com(spi, 0xD614); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD615); spi_write_dat(spi, 0x63); - spi_write_com(spi, 0xD616); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD617); spi_write_dat(spi, 0xB1); - spi_write_com(spi, 0xD618); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD619); spi_write_dat(spi, 0xF0); - spi_write_com(spi, 0xD61A); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xD61B); spi_write_dat(spi, 0xF2); - spi_write_com(spi, 0xD61C); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD61D); spi_write_dat(spi, 0x2A); - spi_write_com(spi, 0xD61E); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD61F); spi_write_dat(spi, 0x67); - spi_write_com(spi, 0xD620); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD621); spi_write_dat(spi, 0x90); - spi_write_com(spi, 0xD622); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD623); spi_write_dat(spi, 0xCB); - spi_write_com(spi, 0xD624); spi_write_dat(spi, 0x02); - spi_write_com(spi, 0xD625); spi_write_dat(spi, 0xF2); - spi_write_com(spi, 0xD626); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD627); spi_write_dat(spi, 0x2A); - spi_write_com(spi, 0xD628); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD629); spi_write_dat(spi, 0x51); - spi_write_com(spi, 0xD62A); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD62B); spi_write_dat(spi, 0x80); - spi_write_com(spi, 0xD62C); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD62D); spi_write_dat(spi, 0x9F); - spi_write_com(spi, 0xD62E); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD62F); spi_write_dat(spi, 0xBE); - spi_write_com(spi, 0xD630); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD631); spi_write_dat(spi, 0xF9); - spi_write_com(spi, 0xD632); spi_write_dat(spi, 0x03); - spi_write_com(spi, 0xD633); spi_write_dat(spi, 0xFF); - - /* LV2 Page 0 enable */ - spi_write_com(spi, 0xF000); spi_write_dat(spi, 0x55); - spi_write_com(spi, 0xF001); spi_write_dat(spi, 0xAA); - spi_write_com(spi, 0xF002); spi_write_dat(spi, 0x52); - spi_write_com(spi, 0xF003); spi_write_dat(spi, 0x08); - spi_write_com(spi, 0xF004); spi_write_dat(spi, 0x00); - - /* Display control */ - spi_write_com(spi, 0xB100); spi_write_dat(spi, 0xFC); - spi_write_com(spi, 0xB101); spi_write_dat(spi, 0x00); - - /* Source hold time */ - spi_write_com(spi, 0xB600); spi_write_dat(spi, 0x05); - - /* Gate EQ control */ - spi_write_com(spi, 0xB700); spi_write_dat(spi, 0x70); - spi_write_com(spi, 0xB701); spi_write_dat(spi, 0x70); - - /* Source EQ control (Mode 2) */ - spi_write_com(spi, 0xB800); spi_write_dat(spi, 0x01); - spi_write_com(spi, 0xB801); spi_write_dat(spi, 0x05); - spi_write_com(spi, 0xB802); spi_write_dat(spi, 0x05); - spi_write_com(spi, 0xB803); spi_write_dat(spi, 0x05); - - /* Inversion mode (Column) */ - spi_write_com(spi, 0xBC00); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xBC01); spi_write_dat(spi, 0x00); - spi_write_com(spi, 0xBC02); spi_write_dat(spi, 0x00); - - /* Timing control 8phase dual side/4H/4delay/RST_EN */ - spi_write_com(spi, 0xC900); spi_write_dat(spi, 0xD0); - spi_write_com(spi, 0xC901); spi_write_dat(spi, 0x82); - spi_write_com(spi, 0xC902); spi_write_dat(spi, 0x50); - spi_write_com(spi, 0xC903); spi_write_dat(spi, 0x50); - spi_write_com(spi, 0xC904); spi_write_dat(spi, 0x50); - - spi_write_com(spi, 0x3A00); spi_write_dat(spi, 0x55); - mdelay(120); - spi_write_com(spi, 0x1100); - mdelay(120); - spi_write_com(spi, 0x2900); - mdelay(120); - /* spi_write_com(spi, 0x2100); spi_write_dat(spi, 0x00); */ - spi_write_com(spi, 0x2C00); - - return 0; -err_claim_bus: - spi_free_slave(spi); - return -1; -} diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 41c8baa6a7a..c797b30827d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -151,7 +151,6 @@ CONFIG_FLASH_SHOW_PROGRESS CONFIG_FLASH_SPANSION_S29WS_N CONFIG_FLASH_VERIFY CONFIG_FM_PLAT_CLK_DIV -CONFIG_FORMIKE CONFIG_FPGA_COUNT CONFIG_FPGA_STRATIX_V CONFIG_FSL_CADMUS -- cgit v1.3.1 From 276d446757e462c210768eb0bbd48450ae254f51 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 15 Jan 2022 17:24:58 -0500 Subject: clk: Make rfree return void When freeing a clock there is not much we can do if there is an error, and most callers do not actually check the return value. Even e.g. checking to make sure that clk->id is valid should have been done in request() in the first place (unless someone is messing with the driver behind our back). Just return void and don't bother returning an error. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass Link: https://lore.kernel.org/r/20220115222504.617013-2-seanga2@gmail.com --- drivers/clk/clk-uclass.c | 7 +++---- drivers/clk/clk_sandbox.c | 6 +++--- include/clk-uclass.h | 8 +++----- 3 files changed, 9 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index c20c928bf1d..2cc798e9368 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -481,10 +481,9 @@ int clk_free(struct clk *clk) return 0; ops = clk_dev_ops(clk->dev); - if (!ops->rfree) - return 0; - - return ops->rfree(clk); + if (ops->rfree) + ops->rfree(clk); + return 0; } ulong clk_get_rate(struct clk *clk) diff --git a/drivers/clk/clk_sandbox.c b/drivers/clk/clk_sandbox.c index 57acf7d8553..636914db8ca 100644 --- a/drivers/clk/clk_sandbox.c +++ b/drivers/clk/clk_sandbox.c @@ -101,15 +101,15 @@ static int sandbox_clk_request(struct clk *clk) return 0; } -static int sandbox_clk_free(struct clk *clk) +static void sandbox_clk_free(struct clk *clk) { struct sandbox_clk_priv *priv = dev_get_priv(clk->dev); if (clk->id >= SANDBOX_CLK_ID_COUNT) - return -EINVAL; + return; priv->requested[clk->id] = false; - return 0; + return; } static struct clk_ops sandbox_clk_ops = { diff --git a/include/clk-uclass.h b/include/clk-uclass.h index e44f1caf516..65ebff9ed27 100644 --- a/include/clk-uclass.h +++ b/include/clk-uclass.h @@ -32,7 +32,7 @@ struct clk_ops { int (*of_xlate)(struct clk *clock, struct ofnode_phandle_args *args); int (*request)(struct clk *clock); - int (*rfree)(struct clk *clock); + void (*rfree)(struct clk *clock); ulong (*round_rate)(struct clk *clk, ulong rate); ulong (*get_rate)(struct clk *clk); ulong (*set_rate)(struct clk *clk, ulong rate); @@ -81,11 +81,9 @@ int request(struct clk *clock); * rfree() - Free a previously requested clock. * @clock: The clock to free. * - * This is the implementation of the client clk_free() API. - * - * Return: 0 if OK, or a negative error code. + * Free any resources allocated in request(). */ -int rfree(struct clk *clock); +void rfree(struct clk *clock); /** * round_rate() - Adjust a rate to the exact rate a clock can provide. -- cgit v1.3.1 From 454af567edc0b02842c83aaf1a60bbcb766af0cd Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 15 Jan 2022 17:24:59 -0500 Subject: dma: bcm6348: Don't check clk_free This function always succeeds, so don't check its return value. Signed-off-by: Sean Anderson Link: https://lore.kernel.org/r/20220115222504.617013-3-seanga2@gmail.com --- drivers/dma/bcm6348-iudma.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/bcm6348-iudma.c b/drivers/dma/bcm6348-iudma.c index c04aa55cb42..4fc650272d9 100644 --- a/drivers/dma/bcm6348-iudma.c +++ b/drivers/dma/bcm6348-iudma.c @@ -596,11 +596,7 @@ static int bcm6348_iudma_probe(struct udevice *dev) return ret; } - ret = clk_free(&clk); - if (ret < 0) { - pr_err("error freeing clock %d\n", i); - return ret; - } + clk_free(&clk); } /* try to perform resets */ -- cgit v1.3.1 From b2e0889abacfd453131359156fe279996727d95b Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 15 Jan 2022 17:25:00 -0500 Subject: net: bcm63xx: Don't check clk_free This function always succeeds, so don't check its return value. Signed-off-by: Sean Anderson Link: https://lore.kernel.org/r/20220115222504.617013-4-seanga2@gmail.com --- drivers/net/bcm6348-eth.c | 6 +----- drivers/net/bcm6368-eth.c | 6 +----- 2 files changed, 2 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/net/bcm6348-eth.c b/drivers/net/bcm6348-eth.c index aad7b612134..06e0dd74a5b 100644 --- a/drivers/net/bcm6348-eth.c +++ b/drivers/net/bcm6348-eth.c @@ -461,11 +461,7 @@ static int bcm6348_eth_probe(struct udevice *dev) return ret; } - ret = clk_free(&clk); - if (ret < 0) { - pr_err("%s: error freeing clock %d\n", __func__, i); - return ret; - } + clk_free(&clk); } /* try to perform resets */ diff --git a/drivers/net/bcm6368-eth.c b/drivers/net/bcm6368-eth.c index 29abe7fc969..c2a8b9f0576 100644 --- a/drivers/net/bcm6368-eth.c +++ b/drivers/net/bcm6368-eth.c @@ -546,11 +546,7 @@ static int bcm6368_eth_probe(struct udevice *dev) return ret; } - ret = clk_free(&clk); - if (ret < 0) { - pr_err("%s: error freeing clock %d\n", __func__, i); - return ret; - } + clk_free(&clk); } /* try to perform resets */ -- cgit v1.3.1 From ad20358c7462159d5f9012facba9dec1e197aaca Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 15 Jan 2022 17:25:01 -0500 Subject: phy: bcm63xx: Don't check clk_free This function always succeeds, so don't check its return value. Signed-off-by: Sean Anderson Link: https://lore.kernel.org/r/20220115222504.617013-5-seanga2@gmail.com --- drivers/phy/bcm6318-usbh-phy.c | 4 +--- drivers/phy/bcm6348-usbh-phy.c | 4 +--- drivers/phy/bcm6368-usbh-phy.c | 8 ++------ 3 files changed, 4 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/phy/bcm6318-usbh-phy.c b/drivers/phy/bcm6318-usbh-phy.c index 60608a55bc2..1c10853940a 100644 --- a/drivers/phy/bcm6318-usbh-phy.c +++ b/drivers/phy/bcm6318-usbh-phy.c @@ -98,9 +98,7 @@ static int bcm6318_usbh_probe(struct udevice *dev) if (ret < 0) return ret; - ret = clk_free(&clk); - if (ret < 0) - return ret; + clk_free(&clk); /* enable power domain */ ret = power_domain_get(dev, &pwr_dom); diff --git a/drivers/phy/bcm6348-usbh-phy.c b/drivers/phy/bcm6348-usbh-phy.c index 1b6b5ad177e..ce6be3d7dab 100644 --- a/drivers/phy/bcm6348-usbh-phy.c +++ b/drivers/phy/bcm6348-usbh-phy.c @@ -62,9 +62,7 @@ static int bcm6348_usbh_probe(struct udevice *dev) if (ret < 0) return ret; - ret = clk_free(&clk); - if (ret < 0) - return ret; + clk_free(&clk); /* perform reset */ ret = reset_get_by_index(dev, 0, &rst_ctl); diff --git a/drivers/phy/bcm6368-usbh-phy.c b/drivers/phy/bcm6368-usbh-phy.c index 4d3a63faada..d057f1f52e8 100644 --- a/drivers/phy/bcm6368-usbh-phy.c +++ b/drivers/phy/bcm6368-usbh-phy.c @@ -137,9 +137,7 @@ static int bcm6368_usbh_probe(struct udevice *dev) if (ret < 0) return ret; - ret = clk_free(&clk); - if (ret < 0) - return ret; + clk_free(&clk); #if defined(CONFIG_POWER_DOMAIN) /* enable power domain */ @@ -176,9 +174,7 @@ static int bcm6368_usbh_probe(struct udevice *dev) if (ret < 0) return ret; - ret = clk_free(&clk); - if (ret < 0) - return ret; + clk_free(&clk); } mdelay(100); -- cgit v1.3.1 From dfdb227c3d018983f37cc97fe003e231a81a46ea Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 15 Jan 2022 17:25:02 -0500 Subject: spi: bcm63xx: Don't check clk_free This function always succeeds, so don't check its return value. Signed-off-by: Sean Anderson Link: https://lore.kernel.org/r/20220115222504.617013-6-seanga2@gmail.com --- drivers/spi/bcm63xx_hsspi.c | 8 ++------ drivers/spi/bcm63xx_spi.c | 4 +--- 2 files changed, 3 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c index 85108df565c..47002f8b566 100644 --- a/drivers/spi/bcm63xx_hsspi.c +++ b/drivers/spi/bcm63xx_hsspi.c @@ -355,9 +355,7 @@ static int bcm63xx_hsspi_probe(struct udevice *dev) if (ret < 0 && ret != -ENOSYS) return ret; - ret = clk_free(&clk); - if (ret < 0 && ret != -ENOSYS) - return ret; + clk_free(&clk); /* get clock rate */ ret = clk_get_by_name(dev, "pll", &clk); @@ -366,9 +364,7 @@ static int bcm63xx_hsspi_probe(struct udevice *dev) priv->clk_rate = clk_get_rate(&clk); - ret = clk_free(&clk); - if (ret < 0 && ret != -ENOSYS) - return ret; + clk_free(&clk); /* perform reset */ ret = reset_get_by_index(dev, 0, &rst_ctl); diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c index dd5e62b2fe1..0600d56c69e 100644 --- a/drivers/spi/bcm63xx_spi.c +++ b/drivers/spi/bcm63xx_spi.c @@ -391,9 +391,7 @@ static int bcm63xx_spi_probe(struct udevice *dev) if (ret < 0) return ret; - ret = clk_free(&clk); - if (ret < 0) - return ret; + clk_free(&clk); /* perform reset */ ret = reset_get_by_index(dev, 0, &rst_ctl); -- cgit v1.3.1 From 3cbdd4cab951b8bd3f2e76066e6911f9780c4eb1 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 15 Jan 2022 17:25:03 -0500 Subject: spi: dw: Don't check clk_free This function always succeeds, so don't check its return value. Signed-off-by: Sean Anderson Link: https://lore.kernel.org/r/20220115222504.617013-7-seanga2@gmail.com --- drivers/spi/designware_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 47bea0b376a..1c7d0ca310b 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -732,7 +732,7 @@ static int dw_spi_remove(struct udevice *bus) if (ret) return ret; - ret = clk_free(&priv->clk); + clk_free(&priv->clk); if (ret) return ret; #endif -- cgit v1.3.1 From ac15e789caecec19d29ee9c5869305d3c3ddfb42 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 15 Jan 2022 17:25:04 -0500 Subject: clk: Make clk_free return void Most callers of this function do not check the return value, and it is unclear what action they should take if it fails. If a function is freeing multiple clocks, it should not stop just because the first one failed. Since the callbacks can no longer fail, just convert the return type to void. Signed-off-by: Sean Anderson Link: https://lore.kernel.org/r/20220115222504.617013-8-seanga2@gmail.com --- drivers/clk/clk-uclass.c | 10 ++++------ drivers/clk/clk_sandbox_test.c | 9 +++------ include/clk.h | 8 ++++---- 3 files changed, 11 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 2cc798e9368..d003bdde743 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -447,9 +447,7 @@ int clk_release_all(struct clk *clk, int count) if (ret && ret != -ENOSYS) return ret; - ret = clk_free(&clk[i]); - if (ret && ret != -ENOSYS) - return ret; + clk_free(&clk[i]); } return 0; @@ -472,18 +470,18 @@ int clk_request(struct udevice *dev, struct clk *clk) return ops->request(clk); } -int clk_free(struct clk *clk) +void clk_free(struct clk *clk) { const struct clk_ops *ops; debug("%s(clk=%p)\n", __func__, clk); if (!clk_valid(clk)) - return 0; + return; ops = clk_dev_ops(clk->dev); if (ops->rfree) ops->rfree(clk); - return 0; + return; } ulong clk_get_rate(struct clk *clk) diff --git a/drivers/clk/clk_sandbox_test.c b/drivers/clk/clk_sandbox_test.c index f665fd3cc45..5807a454f3b 100644 --- a/drivers/clk/clk_sandbox_test.c +++ b/drivers/clk/clk_sandbox_test.c @@ -137,14 +137,11 @@ int sandbox_clk_test_disable_bulk(struct udevice *dev) int sandbox_clk_test_free(struct udevice *dev) { struct sandbox_clk_test *sbct = dev_get_priv(dev); - int i, ret; + int i; devm_clk_put(dev, sbct->clkps[SANDBOX_CLK_TEST_ID_DEVM1]); - for (i = 0; i < SANDBOX_CLK_TEST_NON_DEVM_COUNT; i++) { - ret = clk_free(&sbct->clks[i]); - if (ret) - return ret; - } + for (i = 0; i < SANDBOX_CLK_TEST_NON_DEVM_COUNT; i++) + clk_free(&sbct->clks[i]); return 0; } diff --git a/include/clk.h b/include/clk.h index 23e4d4ea729..76bb64bb5ee 100644 --- a/include/clk.h +++ b/include/clk.h @@ -414,9 +414,9 @@ int clk_request(struct udevice *dev, struct clk *clk); * @clk: A clock struct that was previously successfully requested by * clk_request/get_by_*(). * - * Return: 0 if OK, or a negative error code. + * Free resources allocated by clk_request() (or any clk_get_* function). */ -int clk_free(struct clk *clk); +void clk_free(struct clk *clk); /** * clk_get_rate() - Get current clock rate. @@ -562,9 +562,9 @@ static inline int clk_request(struct udevice *dev, struct clk *clk) return -ENOSYS; } -static inline int clk_free(struct clk *clk) +static inline void clk_free(struct clk *clk) { - return 0; + return; } static inline ulong clk_get_rate(struct clk *clk) -- cgit v1.3.1 From e7075ff7b3dce82e4fd6246b87f3c44fabf6323b Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sun, 27 Feb 2022 14:01:13 -0500 Subject: clk: Consolidate some clock functions These functions are exactly the same as their "nodev" varients, except they accept a device and not an ofnode. Rewrite them to just call the other function. Signed-off-by: Sean Anderson Link: https://lore.kernel.org/r/20220227190113.1617498-1-seanga2@gmail.com --- drivers/clk/clk-uclass.c | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index d003bdde743..b89c77bf794 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -138,14 +138,7 @@ static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name, int clk_get_by_index(struct udevice *dev, int index, struct clk *clk) { - struct ofnode_phandle_args args; - int ret; - - ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0, - index, &args); - - return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks", - index, clk); + return clk_get_by_index_nodev(dev_ofnode(dev), index, clk); } int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk) @@ -400,18 +393,7 @@ int clk_set_defaults(struct udevice *dev, enum clk_defaults_stage stage) int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk) { - int index; - - debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk); - clk->dev = NULL; - - index = dev_read_stringlist_search(dev, "clock-names", name); - if (index < 0) { - debug("fdt_stringlist_search() failed: %d\n", index); - return index; - } - - return clk_get_by_index(dev, index, clk); + return clk_get_by_name_nodev(dev_ofnode(dev), name, clk); } #endif /* OF_REAL */ -- cgit v1.3.1 From 3a11b5ae65c269ef9f7bb1e18826e85fc164f161 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sun, 20 Mar 2022 16:34:45 -0400 Subject: clk: ccf: Add some helper functions for clock ops Most CCF drivers follow a common pattern where their clock ops defer the actual operation to the backing CCF clock. Add some generic implementations of these functions to reduce duplication of code. Signed-off-by: Sean Anderson Reviewed-by: Peng Fan Link: https://lore.kernel.org/r/20220320203446.740178-1-seanga2@gmail.com --- drivers/clk/clk.c | 65 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/clk-provider.h | 8 ++++++ 2 files changed, 73 insertions(+) (limited to 'drivers') diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index eff0fa134f7..a5a3461b66c 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -74,3 +74,68 @@ bool clk_dev_binded(struct clk *clk) return false; } + +/* Helper functions for clock ops */ + +ulong ccf_clk_get_rate(struct clk *clk) +{ + struct clk *c; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + return clk_get_rate(c); +} + +ulong ccf_clk_set_rate(struct clk *clk, unsigned long rate) +{ + struct clk *c; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + return clk_set_rate(c, rate); +} + +int ccf_clk_set_parent(struct clk *clk, struct clk *parent) +{ + struct clk *c, *p; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + + err = clk_get_by_id(parent->id, &p); + if (err) + return err; + + return clk_set_parent(c, p); +} + +static int ccf_clk_endisable(struct clk *clk, bool enable) +{ + struct clk *c; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + return enable ? clk_enable(c) : clk_disable(c); +} + +int ccf_clk_enable(struct clk *clk) +{ + return ccf_clk_endisable(clk, true); +} + +int ccf_clk_disable(struct clk *clk) +{ + return ccf_clk_endisable(clk, false); +} + +const struct clk_ops ccf_clk_ops = { + .set_rate = ccf_clk_set_rate, + .get_rate = ccf_clk_get_rate, + .set_parent = ccf_clk_set_parent, + .enable = ccf_clk_enable, + .disable = ccf_clk_disable, +}; diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 9a6116646de..2d04882d053 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -254,4 +254,12 @@ const char *clk_hw_get_name(const struct clk *hw); ulong clk_generic_get_rate(struct clk *clk); struct clk *dev_get_clk_ptr(struct udevice *dev); + +ulong ccf_clk_get_rate(struct clk *clk); +ulong ccf_clk_set_rate(struct clk *clk, unsigned long rate); +int ccf_clk_set_parent(struct clk *clk, struct clk *parent); +int ccf_clk_enable(struct clk *clk); +int ccf_clk_disable(struct clk *clk); +extern const struct clk_ops ccf_clk_ops; + #endif /* __LINUX_CLK_PROVIDER_H */ -- cgit v1.3.1 From 682e73d23555afdd733c20810d282d9cc2bc0e0f Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sun, 20 Mar 2022 16:34:46 -0400 Subject: clk: Use generic CCF ops where possible This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson Reviewed-by: Claudiu Beznea Reviewed-by: Peng Fan Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson --- drivers/clk/at91/pmc.c | 57 +++---------------------- drivers/clk/imx/clk-imx6q.c | 73 ++++---------------------------- drivers/clk/imx/clk-imx8mm.c | 88 +-------------------------------------- drivers/clk/imx/clk-imx8mn.c | 88 +-------------------------------------- drivers/clk/imx/clk-imx8mp.c | 90 +--------------------------------------- drivers/clk/imx/clk-imxrt1020.c | 65 ++--------------------------- drivers/clk/imx/clk-imxrt1050.c | 85 +------------------------------------ drivers/clk/microchip/mpfs_clk.c | 67 +----------------------------- 8 files changed, 22 insertions(+), 591 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c index 1fa42d728b5..270892517a9 100644 --- a/drivers/clk/at91/pmc.c +++ b/drivers/clk/at91/pmc.c @@ -7,6 +7,7 @@ #include #include #include +#include #include "pmc.h" static int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) @@ -21,60 +22,12 @@ static int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) return 0; } -static ulong at91_clk_get_rate(struct clk *clk) -{ - struct clk *c; - int ret; - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - return clk_get_rate(c); -} - -static ulong at91_clk_set_rate(struct clk *clk, ulong rate) -{ - struct clk *c; - int ret; - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - return clk_set_rate(c, rate); -} - -static int at91_clk_enable(struct clk *clk) -{ - struct clk *c; - int ret; - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - return clk_enable(c); -} - -static int at91_clk_disable(struct clk *clk) -{ - struct clk *c; - int ret; - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - return clk_disable(c); -} - const struct clk_ops at91_clk_ops = { .of_xlate = at91_clk_of_xlate, - .set_rate = at91_clk_set_rate, - .get_rate = at91_clk_get_rate, - .enable = at91_clk_enable, - .disable = at91_clk_disable, + .set_rate = ccf_clk_set_rate, + .get_rate = ccf_clk_get_rate, + .enable = ccf_clk_enable, + .disable = ccf_clk_disable, }; /** diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 5343036babd..67825af89b8 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -14,79 +14,22 @@ #include "clk.h" -static int imx6q_check_id(ulong id) +static int imx6q_clk_request(struct clk *clk) { - if (id < IMX6QDL_CLK_DUMMY || id >= IMX6QDL_CLK_END) { - printf("%s: Invalid clk ID #%lu\n", __func__, id); + if (clk->id < IMX6QDL_CLK_DUMMY || clk->id >= IMX6QDL_CLK_END) { + printf("%s: Invalid clk ID #%lu\n", __func__, clk->id); return -EINVAL; } return 0; } -static ulong imx6q_clk_get_rate(struct clk *clk) -{ - struct clk *c; - int ret; - - debug("%s(#%lu)\n", __func__, clk->id); - - ret = imx6q_check_id(clk->id); - if (ret) - return ret; - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - return clk_get_rate(c); -} - -static ulong imx6q_clk_set_rate(struct clk *clk, unsigned long rate) -{ - debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate); - - return rate; -} - -static int __imx6q_clk_enable(struct clk *clk, bool enable) -{ - struct clk *c; - int ret = 0; - - debug("%s(#%lu) en: %d\n", __func__, clk->id, enable); - - ret = imx6q_check_id(clk->id); - if (ret) - return ret; - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - if (enable) - ret = clk_enable(c); - else - ret = clk_disable(c); - - return ret; -} - -static int imx6q_clk_disable(struct clk *clk) -{ - return __imx6q_clk_enable(clk, 0); -} - -static int imx6q_clk_enable(struct clk *clk) -{ - return __imx6q_clk_enable(clk, 1); -} - static struct clk_ops imx6q_clk_ops = { - .set_rate = imx6q_clk_set_rate, - .get_rate = imx6q_clk_get_rate, - .enable = imx6q_clk_enable, - .disable = imx6q_clk_disable, + .request = imx6q_clk_request, + .set_rate = ccf_clk_set_rate, + .get_rate = ccf_clk_get_rate, + .enable = ccf_clk_enable, + .disable = ccf_clk_disable, }; static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 3aa8c641f9a..443bbdae332 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -140,92 +140,6 @@ static const char *imx8mm_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sy static const char *imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static ulong imx8mm_clk_get_rate(struct clk *clk) -{ - struct clk *c; - int ret; - - debug("%s(#%lu)\n", __func__, clk->id); - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - return clk_get_rate(c); -} - -static ulong imx8mm_clk_set_rate(struct clk *clk, unsigned long rate) -{ - struct clk *c; - int ret; - - debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate); - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - return clk_set_rate(c, rate); -} - -static int __imx8mm_clk_enable(struct clk *clk, bool enable) -{ - struct clk *c; - int ret; - - debug("%s(#%lu) en: %d\n", __func__, clk->id, enable); - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - if (enable) - ret = clk_enable(c); - else - ret = clk_disable(c); - - return ret; -} - -static int imx8mm_clk_disable(struct clk *clk) -{ - return __imx8mm_clk_enable(clk, 0); -} - -static int imx8mm_clk_enable(struct clk *clk) -{ - return __imx8mm_clk_enable(clk, 1); -} - -static int imx8mm_clk_set_parent(struct clk *clk, struct clk *parent) -{ - struct clk *c, *cp; - int ret; - - debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id); - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - ret = clk_get_by_id(parent->id, &cp); - if (ret) - return ret; - - ret = clk_set_parent(c, cp); - c->dev->parent = cp->dev; - - return ret; -} - -static struct clk_ops imx8mm_clk_ops = { - .set_rate = imx8mm_clk_set_rate, - .get_rate = imx8mm_clk_get_rate, - .enable = imx8mm_clk_enable, - .disable = imx8mm_clk_disable, - .set_parent = imx8mm_clk_set_parent, -}; - static int imx8mm_clk_probe(struct udevice *dev) { void __iomem *base; @@ -470,7 +384,7 @@ U_BOOT_DRIVER(imx8mm_clk) = { .name = "clk_imx8mm", .id = UCLASS_CLK, .of_match = imx8mm_clk_ids, - .ops = &imx8mm_clk_ops, + .ops = &ccf_clk_ops, .probe = imx8mm_clk_probe, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index e398d7de02a..bb62138f8ca 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -148,92 +148,6 @@ static const char * const imx8mn_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_10 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; -static ulong imx8mn_clk_get_rate(struct clk *clk) -{ - struct clk *c; - int ret; - - debug("%s(#%lu)\n", __func__, clk->id); - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - return clk_get_rate(c); -} - -static ulong imx8mn_clk_set_rate(struct clk *clk, unsigned long rate) -{ - struct clk *c; - int ret; - - debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate); - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - return clk_set_rate(c, rate); -} - -static int __imx8mn_clk_enable(struct clk *clk, bool enable) -{ - struct clk *c; - int ret; - - debug("%s(#%lu) en: %d\n", __func__, clk->id, enable); - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - if (enable) - ret = clk_enable(c); - else - ret = clk_disable(c); - - return ret; -} - -static int imx8mn_clk_disable(struct clk *clk) -{ - return __imx8mn_clk_enable(clk, 0); -} - -static int imx8mn_clk_enable(struct clk *clk) -{ - return __imx8mn_clk_enable(clk, 1); -} - -static int imx8mn_clk_set_parent(struct clk *clk, struct clk *parent) -{ - struct clk *c, *cp; - int ret; - - debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id); - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - ret = clk_get_by_id(parent->id, &cp); - if (ret) - return ret; - - ret = clk_set_parent(c, cp); - c->dev->parent = cp->dev; - - return ret; -} - -static struct clk_ops imx8mn_clk_ops = { - .set_rate = imx8mn_clk_set_rate, - .get_rate = imx8mn_clk_get_rate, - .enable = imx8mn_clk_enable, - .disable = imx8mn_clk_disable, - .set_parent = imx8mn_clk_set_parent, -}; - static int imx8mn_clk_probe(struct udevice *dev) { void __iomem *base; @@ -481,7 +395,7 @@ U_BOOT_DRIVER(imx8mn_clk) = { .name = "clk_imx8mn", .id = UCLASS_CLK, .of_match = imx8mn_clk_ids, - .ops = &imx8mn_clk_ops, + .ops = &ccf_clk_ops, .probe = imx8mn_clk_probe, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index c77500bcce0..ad84ce38ede 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -186,94 +186,6 @@ static const char *imx8mp_enet_phy_ref_sels[] = {"clock-osc-24m", "sys_pll2_50m" static const char *imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; - -static ulong imx8mp_clk_get_rate(struct clk *clk) -{ - struct clk *c; - int ret; - - debug("%s(#%lu)\n", __func__, clk->id); - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - return clk_get_rate(c); -} - -static ulong imx8mp_clk_set_rate(struct clk *clk, unsigned long rate) -{ - struct clk *c; - int ret; - - debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate); - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - return clk_set_rate(c, rate); -} - -static int __imx8mp_clk_enable(struct clk *clk, bool enable) -{ - struct clk *c; - int ret; - - debug("%s(#%lu) en: %d\n", __func__, clk->id, enable); - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - if (enable) - ret = clk_enable(c); - else - ret = clk_disable(c); - - return ret; -} - -static int imx8mp_clk_disable(struct clk *clk) -{ - return __imx8mp_clk_enable(clk, 0); -} - -static int imx8mp_clk_enable(struct clk *clk) -{ - return __imx8mp_clk_enable(clk, 1); -} - -static int imx8mp_clk_set_parent(struct clk *clk, struct clk *parent) -{ - struct clk *c, *cp; - int ret; - - debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id); - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - ret = clk_get_by_id(parent->id, &cp); - if (ret) - return ret; - - ret = clk_set_parent(c, cp); - - c->dev->parent = cp->dev; - - return ret; -} - -static struct clk_ops imx8mp_clk_ops = { - .set_rate = imx8mp_clk_set_rate, - .get_rate = imx8mp_clk_get_rate, - .enable = imx8mp_clk_enable, - .disable = imx8mp_clk_disable, - .set_parent = imx8mp_clk_set_parent, -}; - static int imx8mp_clk_probe(struct udevice *dev) { void __iomem *base; @@ -409,7 +321,7 @@ U_BOOT_DRIVER(imx8mp_clk) = { .name = "clk_imx8mp", .id = UCLASS_CLK, .of_match = imx8mp_clk_ids, - .ops = &imx8mp_clk_ops, + .ops = &ccf_clk_ops, .probe = imx8mp_clk_probe, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c index 840f783940f..3f8b4df3c5a 100644 --- a/drivers/clk/imx/clk-imxrt1020.c +++ b/drivers/clk/imx/clk-imxrt1020.c @@ -14,68 +14,11 @@ #include "clk.h" -static ulong imxrt1020_clk_get_rate(struct clk *clk) -{ - struct clk *c; - int ret; - - debug("%s(#%lu)\n", __func__, clk->id); - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - return clk_get_rate(c); -} - -static ulong imxrt1020_clk_set_rate(struct clk *clk, unsigned long rate) -{ - struct clk *c; - int ret; - - debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate); - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - return clk_set_rate(c, rate); -} - -static int __imxrt1020_clk_enable(struct clk *clk, bool enable) -{ - struct clk *c; - int ret; - - debug("%s(#%lu) en: %d\n", __func__, clk->id, enable); - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - if (enable) - ret = clk_enable(c); - else - ret = clk_disable(c); - - return ret; -} - -static int imxrt1020_clk_disable(struct clk *clk) -{ - return __imxrt1020_clk_enable(clk, 0); -} - -static int imxrt1020_clk_enable(struct clk *clk) -{ - return __imxrt1020_clk_enable(clk, 1); -} - static struct clk_ops imxrt1020_clk_ops = { - .set_rate = imxrt1020_clk_set_rate, - .get_rate = imxrt1020_clk_get_rate, - .enable = imxrt1020_clk_enable, - .disable = imxrt1020_clk_disable, + .set_rate = ccf_clk_set_rate, + .get_rate = ccf_clk_get_rate, + .enable = ccf_clk_enable, + .disable = ccf_clk_disable, }; static const char * const pll2_bypass_sels[] = {"pll2_sys", "osc", }; diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index 3e171610024..5cb5e3bc15a 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -15,89 +15,6 @@ #include "clk.h" -static ulong imxrt1050_clk_get_rate(struct clk *clk) -{ - struct clk *c; - int ret; - - debug("%s(#%lu)\n", __func__, clk->id); - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - return clk_get_rate(c); -} - -static ulong imxrt1050_clk_set_rate(struct clk *clk, ulong rate) -{ - struct clk *c; - int ret; - - debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate); - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - return clk_set_rate(c, rate); -} - -static int __imxrt1050_clk_enable(struct clk *clk, bool enable) -{ - struct clk *c; - int ret; - - debug("%s(#%lu) en: %d\n", __func__, clk->id, enable); - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - if (enable) - ret = clk_enable(c); - else - ret = clk_disable(c); - - return ret; -} - -static int imxrt1050_clk_disable(struct clk *clk) -{ - return __imxrt1050_clk_enable(clk, 0); -} - -static int imxrt1050_clk_enable(struct clk *clk) -{ - return __imxrt1050_clk_enable(clk, 1); -} - -static int imxrt1050_clk_set_parent(struct clk *clk, struct clk *parent) -{ - struct clk *c, *cp; - int ret; - - debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id); - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - ret = clk_get_by_id(parent->id, &cp); - if (ret) - return ret; - - return clk_set_parent(c, cp); -} - -static struct clk_ops imxrt1050_clk_ops = { - .set_rate = imxrt1050_clk_set_rate, - .get_rate = imxrt1050_clk_get_rate, - .enable = imxrt1050_clk_enable, - .disable = imxrt1050_clk_disable, - .set_parent = imxrt1050_clk_set_parent, -}; - static const char * const pll_ref_sels[] = {"osc", "dummy", }; static const char * const pll1_bypass_sels[] = {"pll1_arm", "pll1_arm_ref_sel", }; static const char * const pll2_bypass_sels[] = {"pll2_sys", "pll2_sys_ref_sel", }; @@ -317,7 +234,7 @@ U_BOOT_DRIVER(imxrt1050_clk) = { .name = "clk_imxrt1050", .id = UCLASS_CLK, .of_match = imxrt1050_clk_ids, - .ops = &imxrt1050_clk_ops, + .ops = &ccf_clk_ops, .probe = imxrt1050_clk_probe, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c index 05d7647206c..67828c9bf40 100644 --- a/drivers/clk/microchip/mpfs_clk.c +++ b/drivers/clk/microchip/mpfs_clk.c @@ -15,63 +15,6 @@ #include "mpfs_clk.h" -/* All methods are delegated to CCF clocks */ - -static ulong mpfs_clk_get_rate(struct clk *clk) -{ - struct clk *c; - int err = clk_get_by_id(clk->id, &c); - - if (err) - return err; - return clk_get_rate(c); -} - -static ulong mpfs_clk_set_rate(struct clk *clk, unsigned long rate) -{ - struct clk *c; - int err = clk_get_by_id(clk->id, &c); - - if (err) - return err; - return clk_set_rate(c, rate); -} - -static int mpfs_clk_set_parent(struct clk *clk, struct clk *parent) -{ - struct clk *c, *p; - int err = clk_get_by_id(clk->id, &c); - - if (err) - return err; - - err = clk_get_by_id(parent->id, &p); - if (err) - return err; - - return clk_set_parent(c, p); -} - -static int mpfs_clk_endisable(struct clk *clk, bool enable) -{ - struct clk *c; - int err = clk_get_by_id(clk->id, &c); - - if (err) - return err; - return enable ? clk_enable(c) : clk_disable(c); -} - -static int mpfs_clk_enable(struct clk *clk) -{ - return mpfs_clk_endisable(clk, true); -} - -static int mpfs_clk_disable(struct clk *clk) -{ - return mpfs_clk_endisable(clk, false); -} - static int mpfs_clk_probe(struct udevice *dev) { int ret; @@ -100,14 +43,6 @@ static int mpfs_clk_probe(struct udevice *dev) return ret; } -static const struct clk_ops mpfs_clk_ops = { - .set_rate = mpfs_clk_set_rate, - .get_rate = mpfs_clk_get_rate, - .set_parent = mpfs_clk_set_parent, - .enable = mpfs_clk_enable, - .disable = mpfs_clk_disable, -}; - static const struct udevice_id mpfs_of_match[] = { { .compatible = "microchip,mpfs-clkcfg" }, { } @@ -117,7 +52,7 @@ U_BOOT_DRIVER(mpfs_clk) = { .name = "mpfs_clk", .id = UCLASS_CLK, .of_match = mpfs_of_match, - .ops = &mpfs_clk_ops, + .ops = &ccf_clk_ops, .probe = mpfs_clk_probe, .priv_auto = sizeof(struct clk), .flags = DM_FLAG_PRE_RELOC, -- cgit v1.3.1 From 70fb1ae9dd30b1dc6cf0c6ba585f822ef58106e5 Mon Sep 17 00:00:00 2001 From: Clément Léger Date: Thu, 31 Mar 2022 10:55:06 +0200 Subject: timer: atmel_tcb_timer: add atmel_tcb driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea Signed-off-by: Clément Léger --- MAINTAINERS | 1 + arch/arm/mach-at91/armv7/Makefile | 2 + drivers/timer/Kconfig | 8 ++ drivers/timer/Makefile | 1 + drivers/timer/atmel_tcb_timer.c | 161 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 173 insertions(+) create mode 100644 drivers/timer/atmel_tcb_timer.c (limited to 'drivers') diff --git a/MAINTAINERS b/MAINTAINERS index 74d5263fb1a..b22aaa30b07 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -352,6 +352,7 @@ F: arch/arm/mach-at91/ F: board/atmel/ F: drivers/cpu/at91_cpu.c F: drivers/misc/microchip_flexcom.c +F: drivers/timer/atmel_tcb_timer.c F: include/dt-bindings/mfd/atmel-flexcom.h F: drivers/timer/mchp-pit64b-timer.c diff --git a/arch/arm/mach-at91/armv7/Makefile b/arch/arm/mach-at91/armv7/Makefile index 246050b67bb..f395b55c3de 100644 --- a/arch/arm/mach-at91/armv7/Makefile +++ b/arch/arm/mach-at91/armv7/Makefile @@ -14,9 +14,11 @@ obj-y += cpu.o ifndef CONFIG_$(SPL_TPL_)SYSRESET obj-y += reset.o endif +ifneq ($(CONFIG_ATMEL_TCB_TIMER),y) ifneq ($(CONFIG_ATMEL_PIT_TIMER),y) ifneq ($(CONFIG_MCHP_PIT64B_TIMER),y) # old non-DM timer driver obj-y += timer.o endif endif +endif diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 89131426542..8fad59b81aa 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -96,6 +96,14 @@ config ATMEL_PIT_TIMER it is designed to offer maximum accuracy and efficient management, even for systems with long response time. +config ATMEL_TCB_TIMER + bool "Atmel timer counter support" + depends on TIMER + depends on ARCH_AT91 + help + Select this to enable the use of the timer counter as a monotonic + counter. + config CADENCE_TTC_TIMER bool "Cadence TTC (Triple Timer Counter)" depends on TIMER diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index e2bd530eb04..58da6c1e846 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_ARC_TIMER) += arc_timer.o obj-$(CONFIG_AST_TIMER) += ast_timer.o obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o +obj-$(CONFIG_ATMEL_TCB_TIMER) += atmel_tcb_timer.o obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o diff --git a/drivers/timer/atmel_tcb_timer.c b/drivers/timer/atmel_tcb_timer.c new file mode 100644 index 00000000000..8c17987c7d7 --- /dev/null +++ b/drivers/timer/atmel_tcb_timer.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Microchip Corporation + * + * Author: Clément Léger + */ + +#include +#include +#include +#include +#include +#include + +#define TCB_CHAN(chan) ((chan) * 0x40) + +#define TCB_CCR(chan) (0x0 + TCB_CHAN(chan)) +#define TCB_CCR_CLKEN (1 << 0) + +#define TCB_CMR(chan) (0x4 + TCB_CHAN(chan)) +#define TCB_CMR_WAVE (1 << 15) +#define TCB_CMR_TIMER_CLOCK2 1 +#define TCB_CMR_XC1 6 +#define TCB_CMR_ACPA_SET (1 << 16) +#define TCB_CMR_ACPC_CLEAR (2 << 18) + +#define TCB_CV(chan) (0x10 + TCB_CHAN(chan)) + +#define TCB_RA(chan) (0x14 + TCB_CHAN(chan)) +#define TCB_RC(chan) (0x1c + TCB_CHAN(chan)) + +#define TCB_IDR(chan) (0x28 + TCB_CHAN(chan)) + +#define TCB_BCR 0xc0 +#define TCB_BCR_SYNC (1 << 0) + +#define TCB_BMR 0xc4 +#define TCB_BMR_TC1XC1S_TIOA0 (2 << 2) + +#define TCB_WPMR 0xe4 +#define TCB_WPMR_WAKEY 0x54494d + +#define TCB_CLK_DIVISOR 8 +struct atmel_tcb_plat { + void __iomem *base; +}; + +static u64 atmel_tcb_get_count(struct udevice *dev) +{ + struct atmel_tcb_plat *plat = dev_get_plat(dev); + u64 cv0 = 0; + u64 cv1 = 0; + + do { + cv1 = readl(plat->base + TCB_CV(1)); + cv0 = readl(plat->base + TCB_CV(0)); + } while (readl(plat->base + TCB_CV(1)) != cv1); + + cv0 |= cv1 << 32; + + return cv0; +} + +static void atmel_tcb_configure(void __iomem *base) +{ + /* Disable write protection */ + writel(TCB_WPMR_WAKEY, base + TCB_WPMR); + + /* Disable all irqs for both channel 0 & 1 */ + writel(0xff, base + TCB_IDR(0)); + writel(0xff, base + TCB_IDR(1)); + + /* + * In order to avoid wrapping, use a 64 bit counter by chaining + * two channels. + * Channel 0 is configured to generate a clock on TIOA0 which is cleared + * when reaching 0x80000000 and set when reaching 0. + */ + writel(TCB_CMR_TIMER_CLOCK2 | TCB_CMR_WAVE | TCB_CMR_ACPA_SET + | TCB_CMR_ACPC_CLEAR, base + TCB_CMR(0)); + writel(0x80000000, base + TCB_RC(0)); + writel(0x1, base + TCB_RA(0)); + writel(TCB_CCR_CLKEN, base + TCB_CCR(0)); + + /* Channel 1 is configured to use TIOA0 as input */ + writel(TCB_CMR_XC1 | TCB_CMR_WAVE, base + TCB_CMR(1)); + writel(TCB_CCR_CLKEN, base + TCB_CCR(1)); + + /* Set XC1 input to be TIOA0 (ie output of Channel 0) */ + writel(TCB_BMR_TC1XC1S_TIOA0, base + TCB_BMR); + + /* Sync & start all timers */ + writel(TCB_BCR_SYNC, base + TCB_BCR); +} + +static int atmel_tcb_probe(struct udevice *dev) +{ + struct atmel_tcb_plat *plat = dev_get_plat(dev); + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct clk clk; + ulong clk_rate; + int ret; + + if (!device_is_compatible(dev->parent, "atmel,sama5d2-tcb")) + return -EINVAL; + + /* Currently, we only support channel 0 and 1 to be chained */ + if (dev_read_addr_index(dev, 0) != 0 && + dev_read_addr_index(dev, 1) != 1) { + printf("Error: only chained timers 0 and 1 are supported\n"); + return -EINVAL; + } + + ret = clk_get_by_name(dev->parent, "t0_clk", &clk); + if (ret) + return -EINVAL; + + ret = clk_enable(&clk); + if (ret) + return ret; + + clk_rate = clk_get_rate(&clk); + if (!clk_rate) { + clk_disable(&clk); + return -EINVAL; + } + + uc_priv->clock_rate = clk_rate / TCB_CLK_DIVISOR; + + atmel_tcb_configure(plat->base); + + return 0; +} + +static int atmel_tcb_of_to_plat(struct udevice *dev) +{ + struct atmel_tcb_plat *plat = dev_get_plat(dev); + + plat->base = dev_read_addr_ptr(dev->parent); + + return 0; +} + +static const struct timer_ops atmel_tcb_ops = { + .get_count = atmel_tcb_get_count, +}; + +static const struct udevice_id atmel_tcb_ids[] = { + { .compatible = "atmel,tcb-timer" }, + { } +}; + +U_BOOT_DRIVER(atmel_tcb) = { + .name = "atmel_tcb", + .id = UCLASS_TIMER, + .of_match = atmel_tcb_ids, + .of_to_plat = atmel_tcb_of_to_plat, + .plat_auto = sizeof(struct atmel_tcb_plat), + .probe = atmel_tcb_probe, + .ops = &atmel_tcb_ops, +}; -- cgit v1.3.1 From 797c2b4a1af1e790bcb5163be7dd409c49527354 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 21 Mar 2022 21:33:30 -0400 Subject: Convert CONFIG_BCM2835_GPIO to Kconfig This converts the following to Kconfig: CONFIG_BCM2835_GPIO Signed-off-by: Tom Rini --- configs/rpi_0_w_defconfig | 1 + configs/rpi_2_defconfig | 1 + configs/rpi_3_32b_defconfig | 1 + configs/rpi_3_b_plus_defconfig | 1 + configs/rpi_3_defconfig | 1 + configs/rpi_4_32b_defconfig | 1 + configs/rpi_4_defconfig | 1 + configs/rpi_arm64_defconfig | 1 + configs/rpi_defconfig | 1 + drivers/gpio/Kconfig | 4 ++++ include/configs/rpi.h | 2 -- 11 files changed, 13 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig index 819618280f7..a46c68d3c00 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig @@ -24,6 +24,7 @@ CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y +CONFIG_BCM2835_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index 9ccd69cbd88..a45999b15e0 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -25,6 +25,7 @@ CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y +CONFIG_BCM2835_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index de4a14e69ce..5ae1bd04d9c 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -26,6 +26,7 @@ CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y +CONFIG_BCM2835_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_PHYLIB=y diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig index 1d4346c0ec8..607305841d9 100644 --- a/configs/rpi_3_b_plus_defconfig +++ b/configs/rpi_3_b_plus_defconfig @@ -25,6 +25,7 @@ CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y +CONFIG_BCM2835_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_PHYLIB=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index c7615403d33..58af5de0ff1 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -25,6 +25,7 @@ CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y +CONFIG_BCM2835_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_PHYLIB=y diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index d9d9331f580..3eb57c4ffcb 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -29,6 +29,7 @@ CONFIG_DM_DMA=y CONFIG_DFU_MMC=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000 +CONFIG_BCM2835_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_BCM2835=y diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index eac55ccbcb8..59472d77102 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -29,6 +29,7 @@ CONFIG_DM_DMA=y CONFIG_DFU_MMC=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000 +CONFIG_BCM2835_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_BCM2835=y diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index a0cbdbef02f..639a3a8a3c2 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -24,6 +24,7 @@ CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y CONFIG_DM_DMA=y +CONFIG_BCM2835_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_BCM2835=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index bd4e3dc42d7..66c82024b1d 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -24,6 +24,7 @@ CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y +CONFIG_BCM2835_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index c3f110933a0..a55e3686934 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -84,6 +84,10 @@ config ALTERA_PIO Select this to enable PIO for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config BCM2835_GPIO + bool "BCM2835 GPIO driver" + depends on DM_GPIO + config BCM6345_GPIO bool "BCM6345 GPIO driver" depends on DM_GPIO && (ARCH_BMIPS || ARCH_BCM68360 || \ diff --git a/include/configs/rpi.h b/include/configs/rpi.h index c439ec1b302..7a5f0851b53 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -41,8 +41,6 @@ #endif /* Devices */ -/* GPIO */ -#define CONFIG_BCM2835_GPIO /* LCD */ /* DFU over USB/UDC */ -- cgit v1.3.1 From 448dfb407f7af23b3d85d8ce9039e1e2bd287245 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 21 Mar 2022 21:33:31 -0400 Subject: Convert CONFIG_BITBANGMII_MULTI to Kconfig This converts the following to Kconfig: CONFIG_BITBANGMII_MULTI Signed-off-by: Tom Rini --- configs/alt_defconfig | 1 + configs/armadillo-800eva_defconfig | 1 + configs/controlcenterdc_defconfig | 1 + configs/gose_defconfig | 1 + configs/grpeach_defconfig | 1 + configs/hihope_rzg2_defconfig | 1 + configs/koelsch_defconfig | 1 + configs/lager_defconfig | 1 + configs/porter_defconfig | 1 + configs/r8a77970_eagle_defconfig | 1 + configs/r8a77980_condor_defconfig | 1 + configs/r8a77990_ebisu_defconfig | 1 + configs/r8a77995_draak_defconfig | 1 + configs/r8a779a0_falcon_defconfig | 1 + configs/rcar3_salvator-x_defconfig | 1 + configs/rcar3_ulcb_defconfig | 1 + configs/rzg2_beacon_defconfig | 1 + configs/silinux_ek874_defconfig | 1 + configs/silk_defconfig | 1 + configs/stout_defconfig | 1 + drivers/net/phy/Kconfig | 4 ++++ include/configs/alt.h | 1 - include/configs/armadillo-800eva.h | 1 - include/configs/beacon-rzg2m.h | 3 --- include/configs/condor.h | 4 ---- include/configs/controlcenterdc.h | 5 ----- include/configs/draak.h | 3 --- include/configs/eagle.h | 3 --- include/configs/ebisu.h | 3 --- include/configs/falcon.h | 3 --- include/configs/gose.h | 1 - include/configs/grpeach.h | 1 - include/configs/hihope-rzg2.h | 3 --- include/configs/koelsch.h | 1 - include/configs/lager.h | 1 - include/configs/porter.h | 1 - include/configs/salvator-x.h | 3 --- include/configs/silinux-ek874.h | 3 --- include/configs/silk.h | 1 - include/configs/stout.h | 1 - include/configs/ulcb.h | 3 --- 41 files changed, 24 insertions(+), 45 deletions(-) (limited to 'drivers') diff --git a/configs/alt_defconfig b/configs/alt_defconfig index 0930645c92b..432f29cacae 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -76,6 +76,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_DM_ETH=y diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig index 2f5c115d84f..4f00b203ea1 100644 --- a/configs/armadillo-800eva_defconfig +++ b/configs/armadillo-800eva_defconfig @@ -41,6 +41,7 @@ CONFIG_ENV_ADDR=0x40000 CONFIG_VERSION_VARIABLE=y # CONFIG_MMC is not set CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_SMSC=y CONFIG_SH_ETHER=y CONFIG_SCIF_CONSOLE=y diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig index abbb5cc3d93..953364f7416 100644 --- a/configs/controlcenterdc_defconfig +++ b/configs/controlcenterdc_defconfig @@ -73,6 +73,7 @@ CONFIG_MMC_SDHCI_MV=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_STMICRO=y CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y diff --git a/configs/gose_defconfig b/configs/gose_defconfig index a24a8acdd9d..1200f728e4c 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -74,6 +74,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_DM_ETH=y diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig index 678dbd31d5c..d37b48d9aae 100644 --- a/configs/grpeach_defconfig +++ b/configs/grpeach_defconfig @@ -44,6 +44,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_DM_ETH=y CONFIG_SH_ETHER=y CONFIG_PINCTRL=y diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig index 109c1d66fd6..03534a078d3 100644 --- a/configs/hihope_rzg2_defconfig +++ b/configs/hihope_rzg2_defconfig @@ -62,6 +62,7 @@ CONFIG_RENESAS_SDHI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y CONFIG_RENESAS_RAVB=y diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index 9f9e4687eb2..145e7bbd523 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -74,6 +74,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_DM_ETH=y diff --git a/configs/lager_defconfig b/configs/lager_defconfig index 4cff6e834f6..5185169a9af 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -76,6 +76,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_DM_ETH=y diff --git a/configs/porter_defconfig b/configs/porter_defconfig index ccf2b3f7b9f..b54b48e8310 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -74,6 +74,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_DM_ETH=y diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index 4ccc6f1c367..7e73eb32d38 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -58,6 +58,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig index 36b39c1461d..b5ec2e9c047 100644 --- a/configs/r8a77980_condor_defconfig +++ b/configs/r8a77980_condor_defconfig @@ -59,6 +59,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index 0d8c9d54577..fc5fc575877 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -77,6 +77,7 @@ CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index de9cfd9bab1..e24dfeadfee 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -70,6 +70,7 @@ CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/r8a779a0_falcon_defconfig b/configs/r8a779a0_falcon_defconfig index 9fce6c26f92..c1685aa8c2a 100644 --- a/configs/r8a779a0_falcon_defconfig +++ b/configs/r8a779a0_falcon_defconfig @@ -57,6 +57,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index 5fb27d257af..120b02c411c 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -78,6 +78,7 @@ CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig index ade9286e25d..9c3596e5c84 100644 --- a/configs/rcar3_ulcb_defconfig +++ b/configs/rcar3_ulcb_defconfig @@ -79,6 +79,7 @@ CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/rzg2_beacon_defconfig b/configs/rzg2_beacon_defconfig index 91b3fa29481..5babd4898ab 100644 --- a/configs/rzg2_beacon_defconfig +++ b/configs/rzg2_beacon_defconfig @@ -62,6 +62,7 @@ CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y CONFIG_RENESAS_RAVB=y diff --git a/configs/silinux_ek874_defconfig b/configs/silinux_ek874_defconfig index 5b01f1e5118..0dafb706757 100644 --- a/configs/silinux_ek874_defconfig +++ b/configs/silinux_ek874_defconfig @@ -57,6 +57,7 @@ CONFIG_RENESAS_SDHI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y CONFIG_RENESAS_RAVB=y diff --git a/configs/silk_defconfig b/configs/silk_defconfig index 6ad3252005f..fe28514dc07 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -76,6 +76,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_DM_ETH=y diff --git a/configs/stout_defconfig b/configs/stout_defconfig index f6982913872..0502ae5d306 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -74,6 +74,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_DM_ETH=y diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index eed6eb18669..014a4de223e 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -2,6 +2,10 @@ config BITBANGMII bool "Bit-banged ethernet MII management channel support" +config BITBANGMII_MULTI + bool "Enable the multi bus support" + depends on BITBANGMII + config MV88E6352_SWITCH bool "Marvell 88E6352 switch support" diff --git a/include/configs/alt.h b/include/configs/alt.h index 37b5800d6ef..acc416de06b 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -31,7 +31,6 @@ #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 -#define CONFIG_BITBANGMII_MULTI /* Board Clock */ diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index d24ba2f0d62..b7d6bf213be 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -68,7 +68,6 @@ #define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000 #define CONFIG_SH_ETHER_SH7734_MII (0x01) #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII -#define CONFIG_BITBANGMII_MULTI /* Board Clock */ #define CONFIG_SH_SCIF_CLK_FREQ get_board_sys_clk() diff --git a/include/configs/beacon-rzg2m.h b/include/configs/beacon-rzg2m.h index 7eaafb0d451..2713b158438 100644 --- a/include/configs/beacon-rzg2m.h +++ b/include/configs/beacon-rzg2m.h @@ -8,9 +8,6 @@ #include "rcar-gen3-common.h" -/* Ethernet RAVB */ -#define CONFIG_BITBANGMII_MULTI - #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/condor.h b/include/configs/condor.h index 822ef7118e1..213e68f1587 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -11,9 +11,6 @@ #include "rcar-gen3-common.h" -/* Ethernet RAVB */ -#define CONFIG_BITBANGMII_MULTI - /* Environment compatibility */ /* SH Ether */ @@ -23,7 +20,6 @@ #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 -#define CONFIG_BITBANGMII_MULTI /* Board Clock */ /* XTAL_CLK : 33.33MHz */ diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index cad5796cbce..a7d922c3a23 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -27,11 +27,6 @@ #define CONFIG_PCI_SCAN_SHOW #endif -/* - * Software (bit-bang) MII driver configuration - */ -#define CONFIG_BITBANGMII_MULTI - /* SPL */ /* * Select the boot device here diff --git a/include/configs/draak.h b/include/configs/draak.h index c66a481dadb..5bd8740c6f8 100644 --- a/include/configs/draak.h +++ b/include/configs/draak.h @@ -11,9 +11,6 @@ #include "rcar-gen3-common.h" -/* Ethernet RAVB */ -#define CONFIG_BITBANGMII_MULTI - /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ diff --git a/include/configs/eagle.h b/include/configs/eagle.h index b8a7b5a9169..42fe0577167 100644 --- a/include/configs/eagle.h +++ b/include/configs/eagle.h @@ -11,9 +11,6 @@ #include "rcar-gen3-common.h" -/* Ethernet RAVB */ -#define CONFIG_BITBANGMII_MULTI - /* Environment compatibility */ /* Board Clock */ diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h index cbd1445636f..ce31a462fcf 100644 --- a/include/configs/ebisu.h +++ b/include/configs/ebisu.h @@ -13,9 +13,6 @@ #include "rcar-gen3-common.h" -/* Ethernet RAVB */ -#define CONFIG_BITBANGMII_MULTI - /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ diff --git a/include/configs/falcon.h b/include/configs/falcon.h index 1d6a9b9b734..52dcf19ccad 100644 --- a/include/configs/falcon.h +++ b/include/configs/falcon.h @@ -21,9 +21,6 @@ #define GICD_BASE 0xF1000000 #define GICR_BASE 0xF1060000 -/* Ethernet RAVB */ -#define CONFIG_BITBANGMII_MULTI - /* Board Clock */ /* XTAL_CLK : 16.66MHz */ diff --git a/include/configs/gose.h b/include/configs/gose.h index 01657d7a669..dfa139dc7dc 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -27,7 +27,6 @@ #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 -#define CONFIG_BITBANGMII_MULTI /* Board Clock */ diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index fb01c5614b6..347845f1d50 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -28,6 +28,5 @@ #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 -#define CONFIG_BITBANGMII_MULTI #endif /* __GRPEACH_H */ diff --git a/include/configs/hihope-rzg2.h b/include/configs/hihope-rzg2.h index 68a51176e38..e46eb07a5e9 100644 --- a/include/configs/hihope-rzg2.h +++ b/include/configs/hihope-rzg2.h @@ -11,9 +11,6 @@ #include "rcar-gen3-common.h" -/* Ethernet RAVB */ -#define CONFIG_BITBANGMII_MULTI - /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index eca8998a515..84603e35402 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -27,7 +27,6 @@ #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 -#define CONFIG_BITBANGMII_MULTI /* Board Clock */ diff --git a/include/configs/lager.h b/include/configs/lager.h index 4c291aa89be..8cabad2853c 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -28,7 +28,6 @@ #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 -#define CONFIG_BITBANGMII_MULTI /* Board Clock */ diff --git a/include/configs/porter.h b/include/configs/porter.h index 867dadaedd0..661b7ea0cd2 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -32,7 +32,6 @@ #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 -#define CONFIG_BITBANGMII_MULTI /* Board Clock */ diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 1b3aa304d69..764bc1bbf29 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -11,9 +11,6 @@ #include "rcar-gen3-common.h" -/* Ethernet RAVB */ -#define CONFIG_BITBANGMII_MULTI - /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ diff --git a/include/configs/silinux-ek874.h b/include/configs/silinux-ek874.h index 25c0cd2335c..a99babb48b0 100644 --- a/include/configs/silinux-ek874.h +++ b/include/configs/silinux-ek874.h @@ -11,9 +11,6 @@ #include "rcar-gen3-common.h" -/* Ethernet RAVB */ -#define CONFIG_BITBANGMII_MULTI - /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ diff --git a/include/configs/silk.h b/include/configs/silk.h index 29350a635b2..fa195c62d56 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -32,7 +32,6 @@ #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 -#define CONFIG_BITBANGMII_MULTI /* Board Clock */ diff --git a/include/configs/stout.h b/include/configs/stout.h index df2d9676b5e..f9574be3f77 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -36,7 +36,6 @@ #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 -#define CONFIG_BITBANGMII_MULTI /* Board Clock */ diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index 57e6863cc43..c991bff0e88 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -11,9 +11,6 @@ #include "rcar-gen3-common.h" -/* Ethernet RAVB */ -#define CONFIG_BITBANGMII_MULTI - /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ -- cgit v1.3.1 From 3c205a6e4a7a96c9727a286a47fbaaade9adb9ed Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 23 Mar 2022 17:19:51 -0400 Subject: Convert CONFIG_MCFRTC et al to Kconfig This converts the following to Kconfig: CONFIG_MCFRTC CONFIG_SYS_MCFRTC_BASE While at it, remove '#undef RTC_DEBUG' from these config files. Signed-off-by: Tom Rini --- arch/m68k/include/asm/immap.h | 4 ---- configs/M53017EVB_defconfig | 2 ++ configs/M5329AFEE_defconfig | 2 ++ configs/M5329BFEE_defconfig | 2 ++ configs/M5373EVB_defconfig | 2 ++ configs/astro_mcf5373l_defconfig | 2 ++ drivers/rtc/Kconfig | 8 ++++++++ drivers/rtc/mcfrtc.c | 4 ---- include/configs/M53017EVB.h | 2 -- include/configs/M5329EVB.h | 3 --- include/configs/M5373EVB.h | 3 --- include/configs/astro_mcf5373l.h | 3 --- include/configs/stmark2.h | 1 - 13 files changed, 18 insertions(+), 20 deletions(-) (limited to 'drivers') diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index 02aa95aaf26..ead62cd0387 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -225,8 +225,6 @@ #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) -#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) - /* Timer */ #ifdef CONFIG_MCFTMR #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) @@ -249,7 +247,6 @@ #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) -#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) /* Timer */ #ifdef CONFIG_MCFTMR @@ -283,7 +280,6 @@ #endif #define MMAP_DSPI MMAP_DSPI0 -#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) /* Timer */ #ifdef CONFIG_MCFTMR diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig index 52daf5dfe25..784796664a8 100644 --- a/configs/M53017EVB_defconfig +++ b/configs/M53017EVB_defconfig @@ -39,4 +39,6 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y CONFIG_MCFFEC=y CONFIG_MII=y +CONFIG_MCFRTC=y +CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 CONFIG_MCFUART=y diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig index 4cf68639e28..134ddfb2a14 100644 --- a/configs/M5329AFEE_defconfig +++ b/configs/M5329AFEE_defconfig @@ -41,4 +41,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_DM_ETH=y CONFIG_MCFFEC=y CONFIG_MII=y +CONFIG_MCFRTC=y +CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 CONFIG_MCFUART=y diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig index efe320784a6..a86c754e221 100644 --- a/configs/M5329BFEE_defconfig +++ b/configs/M5329BFEE_defconfig @@ -41,4 +41,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_DM_ETH=y CONFIG_MCFFEC=y CONFIG_MII=y +CONFIG_MCFRTC=y +CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 CONFIG_MCFUART=y diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig index 643637399bd..ac9680ba2e9 100644 --- a/configs/M5373EVB_defconfig +++ b/configs/M5373EVB_defconfig @@ -41,4 +41,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_DM_ETH=y CONFIG_MCFFEC=y CONFIG_MII=y +CONFIG_MCFRTC=y +CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 CONFIG_MCFUART=y diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig index 81f5ccd9911..9eb985c92b7 100644 --- a/configs/astro_mcf5373l_defconfig +++ b/configs/astro_mcf5373l_defconfig @@ -40,5 +40,7 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_MCFRTC=y +CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 CONFIG_MCFUART=y CONFIG_WATCHDOG=y diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 71777cdd05f..7a6c6efb4b0 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -168,6 +168,14 @@ config RTC_MC146818 clock with a wide array of features and 50 bytes of general-purpose, battery-backed RAM. The driver supports access to the clock and RAM. +config MCFRTC + bool "Use common CF RTC driver" + depends on M68K + +config SYS_MCFRTC_BASE + hex "Base address for RTC in immap.h" + depends on MCFRTC + config RTC_M41T62 bool "Enable M41T62 driver" help diff --git a/drivers/rtc/mcfrtc.c b/drivers/rtc/mcfrtc.c index e10638ec7dd..d2ac889c309 100644 --- a/drivers/rtc/mcfrtc.c +++ b/drivers/rtc/mcfrtc.c @@ -13,10 +13,6 @@ #undef RTC_DEBUG -#ifndef CONFIG_SYS_MCFRTC_BASE -#error RTC_BASE is not defined! -#endif - #define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0) #define STARTOFTIME 1970 diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 6e2bdbe6122..7011a4b81f7 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -36,8 +36,6 @@ # endif /* CONFIG_SYS_DISCOVER_PHY */ #endif -#define CONFIG_MCFRTC -#undef RTC_DEBUG #define CONFIG_SYS_RTC_CNT (0x8000) #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index b6b53960c76..cfb2507a7b4 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -33,9 +33,6 @@ # endif /* CONFIG_SYS_DISCOVER_PHY */ #endif -#define CONFIG_MCFRTC -#undef RTC_DEBUG - /* I2C */ #ifdef CONFIG_MCFFEC diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index b45f15be0e9..20102a2b9a2 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -35,9 +35,6 @@ # endif /* CONFIG_SYS_DISCOVER_PHY */ #endif -#define CONFIG_MCFRTC -#undef RTC_DEBUG - /* I2C */ #ifdef CONFIG_MCFFEC diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index b84b7db2e64..f81f84550aa 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -51,9 +51,6 @@ #define ENABLE_JFFS 1 #endif -#define CONFIG_MCFRTC -#undef RTC_DEBUG - /* I2C */ /* diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index e1f2ee0a22b..994be1c2202 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -35,7 +35,6 @@ "" /* Realtime clock */ -#undef CONFIG_MCFRTC #define CONFIG_RTC_MCFRRTC #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 -- cgit v1.3.1 From db48e5258432838bc215bdea9fb8e83017afe972 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 23 Mar 2022 17:20:00 -0400 Subject: Convert CONFIG_LPUART et al to Kconfig This converts the following to Kconfig: CONFIG_LPUART CONFIG_LPUART_32B_REG And note that CONFIG_LPUART_32B_REG is unused in code. Signed-off-by: Tom Rini --- configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 2 +- configs/ls1021aqds_nor_lpuart_defconfig | 2 +- configs/ls1021atwr_nor_lpuart_defconfig | 2 +- configs/ls1028aqds_tfa_lpuart_defconfig | 2 +- configs/ls1043aqds_lpuart_defconfig | 2 +- configs/ls1046aqds_lpuart_defconfig | 2 +- drivers/serial/Kconfig | 4 ++++ include/configs/ls1021aqds.h | 4 +--- include/configs/ls1021atwr.h | 4 +--- include/configs/ls1028aqds.h | 1 - include/configs/ls1043aqds.h | 5 ----- include/configs/ls1046aqds.h | 1 - 12 files changed, 12 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index aedc12a4693..7766f1244c6 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -20,7 +20,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="LPUART" CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y @@ -88,6 +87,7 @@ CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_LPUART=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 56e00a70b11..43f93f4324d 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -20,7 +20,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="LPUART" CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y @@ -89,6 +88,7 @@ CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_LPUART=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index 5bb3175df41..973b499fc92 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -20,7 +20,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="LPUART" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" @@ -76,6 +75,7 @@ CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_LPUART=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig index 1d0e303da2e..0f4a33c66d1 100644 --- a/configs/ls1028aqds_tfa_lpuart_defconfig +++ b/configs/ls1028aqds_tfa_lpuart_defconfig @@ -22,7 +22,6 @@ CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="LPUART" CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" @@ -90,6 +89,7 @@ CONFIG_DM_SCSI=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_LPUART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index d583573f179..105fc5a0d89 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -25,7 +25,6 @@ CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="LPUART" CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -92,6 +91,7 @@ CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_LPUART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index 282cb435007..47636f10e21 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -25,7 +25,6 @@ CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="LPUART" CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y @@ -93,6 +92,7 @@ CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_LPUART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 345d1881f55..610f8062c76 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -647,6 +647,10 @@ config FSL_LPUART Select this to enable a Low Power UART for Freescale VF610 and QorIQ Layerscape devices. +config LPUART + bool "Use the LPUART as console" + depends on FSL_LPUART + config MVEBU_A3700_UART bool "UART support for Armada 3700" help diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 6a27111465f..773cc9bf203 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -268,9 +268,7 @@ /* * Serial Port */ -#ifdef CONFIG_LPUART -#define CONFIG_LPUART_32B_REG -#else +#ifndef CONFIG_LPUART #define CONFIG_SYS_NS16550_SERIAL #ifndef CONFIG_DM_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 03a4ce51994..b607dd37e2f 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -165,9 +165,7 @@ /* * Serial Port */ -#ifdef CONFIG_LPUART -#define CONFIG_LPUART_32B_REG -#else +#ifndef CONFIG_LPUART #define CONFIG_SYS_NS16550_SERIAL #ifndef CONFIG_DM_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index 1b4d181310f..843cd599150 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -66,7 +66,6 @@ /* LPUART */ #ifdef CONFIG_LPUART -#define CONFIG_LPUART_32B_REG #define CFG_LPUART_MUX_MASK 0xf0 #define CFG_LPUART_EN 0xf0 #endif diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index e9919cd05f7..bc02ac5ccb6 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -39,11 +39,6 @@ #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB #endif -/* LPUART */ -#ifdef CONFIG_LPUART -#define CONFIG_LPUART_32B_REG -#endif - /* SATA */ /* EEPROM */ diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 2972e3beac2..ce68d3f929f 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -54,7 +54,6 @@ /* LPUART */ #ifdef CONFIG_LPUART -#define CONFIG_LPUART_32B_REG #define CFG_UART_MUX_MASK 0x6 #define CFG_UART_MUX_SHIFT 1 #define CFG_LPUART_EN 0x2 -- cgit v1.3.1 From 225aaacf361dbd894a4a8b81bf5beba484c0e3cd Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 24 Mar 2022 17:17:56 -0400 Subject: db-mv784mp-gp: Rename CONFIG_DB_784MP_GP to CONFIG_TARGET_DB_MV784MP_GP The value CONFIG_DB_784MP_GP is only used in the DDR code to refer to CONFIG_TARGET_DB_MV784MP_GP so just use that second value directly. Cc: Stefan Roese Signed-off-by: Tom Rini Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c | 2 +- drivers/ddr/marvell/axp/ddr3_axp.h | 2 +- drivers/ddr/marvell/axp/ddr3_axp_config.h | 2 +- include/configs/db-mv784mp-gp.h | 5 ----- 4 files changed, 3 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c index 0b63664dd8b..68f8eade272 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c @@ -62,7 +62,7 @@ static u32 board_id_get(void) return DB_78X60_AMC_ID; #elif defined(CONFIG_DB_78X60_PCAC_REV2) return DB_78X60_PCAC_REV2_ID; -#elif defined(CONFIG_DB_784MP_GP) +#elif defined(CONFIG_TARGET_DB_MV784MP_GP) return DB_784MP_GP_ID; #elif defined(CONFIG_RD_78460_CUSTOMER) return RD_78460_CUSTOMER_ID; diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h index 970651f8702..a14c766dda7 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp.h +++ b/drivers/ddr/marvell/axp/ddr3_axp.h @@ -37,7 +37,7 @@ #define ECC_SUPPORT #endif #define NEW_FABRIC_TWSI_ADDR 0x4E -#ifdef CONFIG_DB_784MP_GP +#ifdef CONFIG_TARGET_DB_MV784MP_GP #define BUS_WIDTH_ECC_TWSI_ADDR 0x4E #else #define BUS_WIDTH_ECC_TWSI_ADDR 0x4F diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h index 437a02efbac..ab09e72623a 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp_config.h +++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h @@ -138,7 +138,7 @@ * Enables I2C auto detection different options */ #if defined(CONFIG_DB_88F78X60) || defined(CONFIG_DB_88F78X60_REV2) || \ - defined(CONFIG_DB_784MP_GP) + defined(CONFIG_TARGET_DB_MV784MP_GP) #define AUTO_DETECTION_SUPPORT #endif #endif diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index 41d469d7952..d6850bd32e7 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -6,11 +6,6 @@ #ifndef _CONFIG_DB_MV7846MP_GP_H #define _CONFIG_DB_MV7846MP_GP_H -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_DB_784MP_GP /* Board target name for DDR training */ - /* * TEXT_BASE needs to be below 16MiB, since this area is scrubbed * for DDR ECC byte filling in the SPL before loading the main -- cgit v1.3.1 From 74d11d37e2d33c616748d5572fd5718944826d17 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:24 -0400 Subject: serial: Add semihosting driver This adds a serial driver which uses semihosting calls to read and write to the host's console. For convenience, if CONFIG_DM_SERIAL is enabled, we will instantiate a serial driver. This allows users to enable this driver (which has no physical device) without modifying their device trees or board files. We also implement a non-DM driver for SPL, or for much faster output in U-Boot proper. There are three ways to print to the console: Method Baud ================== ===== smh_putc in a loop 170 smh_puts 1600 smh_write with :tt 20000 ================== ===== These speeds were measured using a 175 character message with a J-Link adapter. For reference, U-Boot typically prints around 2700 characters during boot on this board. There are two major factors affecting the speed of these functions. First, each breakpoint incurs a delay. Second, each debugger memory transaction incurs a delay. smh_putc has a breakpoint and memory transaction for every character. smh_puts has one breakpoint, but still has to use a transaction for every character. This is because we don't know the length up front, so OpenOCD has to check if each character is nul. smh_write has only one breakpoint and one memory transfer. DM serial drivers can only implement a putc interface, so we are stuck with the slowest API. Non-DM drivers can implement puts, which is vastly more efficient. When the driver starts up, we try to open :tt. Since this is an extension, this may fail. If it does, we fall back to smh_puts. We don't check :semihosting-features, since there are nonconforming implementations (OpenOCD) which don't implement it (but *do* implement :tt). Some semihosting implementations (QEMU) don't handle READC properly. To work around this, we try to use open/read (much like for stdin) if possible. There is no non-blocking I/O available, so we don't implement pending. This will cause __serial_tstc to always return true. If CONFIG_SERIAL_RX_BUFFER is enabled, _serial_tstc will try and read characters forever. To avoid this, we depend on this config being disabled. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- drivers/serial/Kconfig | 22 ++++++ drivers/serial/Makefile | 1 + drivers/serial/serial.c | 2 + drivers/serial/serial_semihosting.c | 147 ++++++++++++++++++++++++++++++++++++ include/serial.h | 1 + 5 files changed, 173 insertions(+) create mode 100644 drivers/serial/serial_semihosting.c (limited to 'drivers') diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 610f8062c76..a07fab225fd 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -399,6 +399,15 @@ config DEBUG_UART_SANDBOX start up driver model. The driver will be available until the real driver model serial is running. +config DEBUG_UART_SEMIHOSTING + bool "semihosting" + depends on SEMIHOSTING_SERIAL + help + Select this to enable the debug UART using the semihosting driver. + This provides basic serial output from the console without needing to + start up driver model. The driver will be available until the real + driver model serial is running. + config DEBUG_UART_SIFIVE bool "SiFive UART" depends on SIFIVE_SERIAL @@ -782,6 +791,19 @@ config SCIF_CONSOLE on systems with RCar or SH SoCs, say Y to this option. If unsure, say N. +config SEMIHOSTING_SERIAL + bool "Semihosting UART support" + depends on SEMIHOSTING && !SERIAL_RX_BUFFER + help + Select this to enable a serial UART using semihosting. Special halt + instructions will be issued which an external debugger (such as a + JTAG emulator) may interpret. The debugger will display U-Boot's + console output on the host system. + + Enable this option only if you are using a debugger which supports + semihosting. If you are not using a debugger, this driver will halt + the boot. + config UNIPHIER_SERIAL bool "Support for UniPhier on-chip UART" depends on ARCH_UNIPHIER diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 52e70aa1917..b68b5e7b2bf 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -52,6 +52,7 @@ endif obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o obj-$(CONFIG_SCIF_CONSOLE) += serial_sh.o +obj-$(CONFIG_SEMIHOSTING_SERIAL) += serial_semihosting.o obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o obj-$(CONFIG_FSL_LINFLEXUART) += serial_linflexuart.o diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index ebbd21916d7..6cdbb89841c 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -126,6 +126,7 @@ serial_initfunc(mxc_serial_initialize); serial_initfunc(ns16550_serial_initialize); serial_initfunc(pl01x_serial_initialize); serial_initfunc(pxa_serial_initialize); +serial_initfunc(smh_serial_initialize); serial_initfunc(sh_serial_initialize); serial_initfunc(mtk_serial_initialize); @@ -180,6 +181,7 @@ int serial_initialize(void) ns16550_serial_initialize(); pl01x_serial_initialize(); pxa_serial_initialize(); + smh_serial_initialize(); sh_serial_initialize(); mtk_serial_initialize(); diff --git a/drivers/serial/serial_semihosting.c b/drivers/serial/serial_semihosting.c new file mode 100644 index 00000000000..7c7c5d94558 --- /dev/null +++ b/drivers/serial/serial_semihosting.c @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Sean Anderson + */ + +#include +#include +#include +#include + +/** + * struct smh_serial_priv - Semihosting serial private data + * @infd: stdin file descriptor (or error) + */ +struct smh_serial_priv { + int infd; + int outfd; +}; + +#if CONFIG_IS_ENABLED(DM_SERIAL) +static int smh_serial_getc(struct udevice *dev) +{ + char ch = 0; + struct smh_serial_priv *priv = dev_get_priv(dev); + + if (priv->infd < 0) + return smh_getc(); + + smh_read(priv->infd, &ch, sizeof(ch)); + return ch; +} + +static int smh_serial_putc(struct udevice *dev, const char ch) +{ + smh_putc(ch); + return 0; +} + +static const struct dm_serial_ops smh_serial_ops = { + .putc = smh_serial_putc, + .getc = smh_serial_getc, +}; + +static int smh_serial_probe(struct udevice *dev) +{ + struct smh_serial_priv *priv = dev_get_priv(dev); + + priv->infd = smh_open(":tt", MODE_READ); + return 0; +} + +U_BOOT_DRIVER(smh_serial) = { + .name = "serial_semihosting", + .id = UCLASS_SERIAL, + .probe = smh_serial_probe, + .priv_auto = sizeof(struct smh_serial_priv), + .ops = &smh_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRVINFO(smh_serial) = { + .name = "serial_semihosting", +}; +#else /* DM_SERIAL */ +static int infd = -ENODEV; +static int outfd = -ENODEV; + +static int smh_serial_start(void) +{ + infd = smh_open(":tt", MODE_READ); + outfd = smh_open(":tt", MODE_WRITE); + return 0; +} + +static int smh_serial_stop(void) +{ + if (outfd >= 0) + smh_close(outfd); + return 0; +} + +static void smh_serial_setbrg(void) +{ +} + +static int smh_serial_getc(void) +{ + char ch = 0; + + if (infd < 0) + return smh_getc(); + + smh_read(infd, &ch, sizeof(ch)); + return ch; +} + +static int smh_serial_tstc(void) +{ + return 1; +} + +static void smh_serial_puts(const char *s) +{ + ulong unused; + + if (outfd < 0) + smh_puts(s); + else + smh_write(outfd, s, strlen(s), &unused); +} + +struct serial_device serial_smh_device = { + .name = "serial_smh", + .start = smh_serial_start, + .stop = smh_serial_stop, + .setbrg = smh_serial_setbrg, + .getc = smh_serial_getc, + .tstc = smh_serial_tstc, + .putc = smh_putc, + .puts = smh_serial_puts, +}; + +void smh_serial_initialize(void) +{ + serial_register(&serial_smh_device); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &serial_smh_device; +} +#endif + +#ifdef CONFIG_DEBUG_UART_SEMIHOSTING +#include + +static inline void _debug_uart_init(void) +{ +} + +static inline void _debug_uart_putc(int c) +{ + smh_putc(c); +} + +DEBUG_UART_FUNCS +#endif diff --git a/include/serial.h b/include/serial.h index 19a8c0c67d2..2681d26c829 100644 --- a/include/serial.h +++ b/include/serial.h @@ -23,6 +23,7 @@ struct serial_device { void default_serial_puts(const char *s); extern struct serial_device serial_smc_device; +extern struct serial_device serial_smh_device; extern struct serial_device serial_scc_device; extern struct serial_device *default_serial_console(void); -- cgit v1.3.1 From 2332590c48ac15926d7ec23b0fa17b9ea4e305ed Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:32 -0400 Subject: serial: smh: Initialize serial only if semihosting is enabled If semihosting is disabled, then the user has no debugger attached, and will not see any messages. Don't create a serial device in this instance, to (hopefully) fall back on another working serial device. Signed-off-by: Sean Anderson --- drivers/serial/serial_semihosting.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/serial/serial_semihosting.c b/drivers/serial/serial_semihosting.c index 7c7c5d94558..62b1b2241b3 100644 --- a/drivers/serial/serial_semihosting.c +++ b/drivers/serial/serial_semihosting.c @@ -41,6 +41,13 @@ static const struct dm_serial_ops smh_serial_ops = { .getc = smh_serial_getc, }; +static int smh_serial_bind(struct udevice *dev) +{ + if (semihosting_enabled()) + return 0; + return -ENOENT; +} + static int smh_serial_probe(struct udevice *dev) { struct smh_serial_priv *priv = dev_get_priv(dev); @@ -52,6 +59,7 @@ static int smh_serial_probe(struct udevice *dev) U_BOOT_DRIVER(smh_serial) = { .name = "serial_semihosting", .id = UCLASS_SERIAL, + .bind = smh_serial_bind, .probe = smh_serial_probe, .priv_auto = sizeof(struct smh_serial_priv), .ops = &smh_serial_ops, @@ -122,7 +130,8 @@ struct serial_device serial_smh_device = { void smh_serial_initialize(void) { - serial_register(&serial_smh_device); + if (semihosting_enabled()) + serial_register(&serial_smh_device); } __weak struct serial_device *default_serial_console(void) -- cgit v1.3.1 From 7a763471894feb58d5a1bdf78ea7014c7a952264 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:34 -0400 Subject: serial: dm: Add support for puts Some serial drivers can be vastly more efficient when printing multiple characters at once. Non-DM serial has had a puts option for these sorts of drivers; implement it for DM serial as well. Because we have to add carriage returns, we can't just pass the whole string directly to the serial driver. Instead, we print up to the newline, then print a carriage return, and then continue on. This is less efficient, but it is better than printing each character individually. It also avoids having to allocate memory just to add a few characters. Drivers may perform short writes (such as filling a FIFO) and return the number of characters written in len. We loop over them in the same way that _serial_putc loops over putc. This results in around sizeof(void *) growth for all boards with DM_SERIAL. The full implementation takes around 140 bytes. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- drivers/serial/Kconfig | 13 +++++++++++++ drivers/serial/serial-uclass.c | 26 ++++++++++++++++++++++++-- include/serial.h | 18 ++++++++++++++++++ 3 files changed, 55 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index a07fab225fd..76171e7146a 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -133,6 +133,19 @@ config SERIAL_RX_BUFFER_SIZE help The size of the RX buffer (needs to be power of 2) +config SERIAL_PUTS + bool "Enable printing strings all at once" + depends on DM_SERIAL + help + Some serial drivers are much more efficient when printing multiple + characters at once rather than printing characters individually. This + can be because they can load a fifo, or because individual print + calls have a constant overhead. With this option set, the serial + subsystem will try to provide serial drivers with as many characters + at once as possible, instead of printing characters one by one. Most + serial drivers do not need this config to print efficiently. If + unsure, say N. + config SERIAL_SEARCH_ALL bool "Search for serial devices after default one failed" depends on DM_SERIAL diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index f30f352bd7a..10d6b800e2f 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -200,8 +200,30 @@ static void _serial_putc(struct udevice *dev, char ch) static void _serial_puts(struct udevice *dev, const char *str) { - while (*str) - _serial_putc(dev, *str++); + struct dm_serial_ops *ops = serial_get_ops(dev); + + if (!CONFIG_IS_ENABLED(SERIAL_PUTS) || !ops->puts) { + while (*str) + _serial_putc(dev, *str++); + return; + } + + do { + const char *newline = strchrnul(str, '\n'); + size_t len = newline - str + !!*newline; + + do { + ssize_t written = ops->puts(dev, str, len); + + if (written < 0) + return; + str += written; + len -= written; + } while (len); + + if (*newline) + _serial_putc(dev, '\r'); + } while (*str); } static int __serial_getc(struct udevice *dev) diff --git a/include/serial.h b/include/serial.h index 2681d26c829..8c2e7adbc32 100644 --- a/include/serial.h +++ b/include/serial.h @@ -195,6 +195,24 @@ struct dm_serial_ops { * @return 0 if OK, -ve on error */ int (*putc)(struct udevice *dev, const char ch); + /** + * puts() - Write a string + * + * This writes a string. This function should be implemented only if + * writing multiple characters at once is more performant than just + * calling putc() in a loop. + * + * If the whole string cannot be written at once, then this function + * should return the number of characters written. Returning a negative + * error code implies that no characters were written. If this function + * returns 0, then it will be called again with the same arguments. + * + * @dev: Device pointer + * @s: The string to write + * @len: The length of the string to write. + * @return The number of characters written on success, or -ve on error + */ + ssize_t (*puts)(struct udevice *dev, const char *s, size_t len); /** * pending() - Check if input/output characters are waiting * -- cgit v1.3.1