From 0cb1fddb743da8312be469920c17559bd2043f46 Mon Sep 17 00:00:00 2001 From: Sebastian Kropatsch Date: Tue, 23 Jul 2024 23:13:14 +0200 Subject: phy: rockchip: naneng-combphy: Introduce PHY-IDs to fix RK3588 muxing Fix multiplex configuration for PCIe1L0 and PCIe1L1 in PCIESEL_CON for RK3588 to correctly select between Combo PHYs and PCIe3 PHY. Currently, the code incorrectly muxes both ports to Combo PHYs, interfering with PCIe3 PHY settings. Introduce PHY identifiers to identify the correct Combo PHY and set the necessary bits accordingly. This fix is adapted from the upstream Linux commit by Sebastian Reichel: d16d4002fea6 ("phy: rockchip: naneng-combphy: Fix mux on rk3588") Fixes: b37260bca1aa ("phy: rockchip: naneng-combphy: Use signal from comb PHY on RK3588") Reviewed-by: Kever Yang Signed-off-by: Sebastian Kropatsch --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 46 ++++++++++++++++++++-- 1 file changed, 43 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 1b85cbcce8d..5145b517aa4 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -67,12 +67,15 @@ struct rockchip_combphy_grfcfg { }; struct rockchip_combphy_cfg { + unsigned int num_phys; + unsigned int phy_ids[3]; const struct rockchip_combphy_grfcfg *grfcfg; int (*combphy_cfg)(struct rockchip_combphy_priv *priv); }; struct rockchip_combphy_priv { u32 mode; + int id; void __iomem *mmio; struct udevice *dev; struct regmap *pipe_grf; @@ -270,8 +273,13 @@ static int rockchip_combphy_probe(struct udevice *udev) { struct rockchip_combphy_priv *priv = dev_get_priv(udev); const struct rockchip_combphy_cfg *phy_cfg; + fdt_addr_t addr = dev_read_addr(udev); + if (addr == FDT_ADDR_T_NONE) { + dev_err(udev, "No valid device address found\n"); + return -EINVAL; + } - priv->mmio = (void __iomem *)dev_read_addr(udev); + priv->mmio = (void __iomem *)addr; if (IS_ERR(priv->mmio)) return PTR_ERR(priv->mmio); @@ -281,6 +289,20 @@ static int rockchip_combphy_probe(struct udevice *udev) return -EINVAL; } + /* Find the phy-id based on the device's I/O-address */ + priv->id = -ENODEV; + for (int id = 0; id < phy_cfg->num_phys; id++) { + if (addr == phy_cfg->phy_ids[id]) { + priv->id = id; + break; + } + } + + if (priv->id == -ENODEV) { + dev_err(udev, "Failed to find PHY ID\n"); + return -ENODEV; + } + priv->dev = udev; priv->mode = PHY_TYPE_SATA; priv->cfg = phy_cfg; @@ -421,6 +443,12 @@ static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { }; static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { + .num_phys = 3, + .phy_ids = { + 0xfe820000, + 0xfe830000, + 0xfe840000, + }, .grfcfg = &rk3568_combphy_grfcfgs, .combphy_cfg = rk3568_combphy_cfg, }; @@ -436,8 +464,14 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) param_write(priv->phy_grf, &cfg->con1_for_pcie, true); param_write(priv->phy_grf, &cfg->con2_for_pcie, true); param_write(priv->phy_grf, &cfg->con3_for_pcie, true); - param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true); - param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true); + switch (priv->id) { + case 1: + param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true); + break; + case 2: + param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true); + break; + } break; case PHY_TYPE_USB3: param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); @@ -515,6 +549,12 @@ static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { }; static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { + .num_phys = 3, + .phy_ids = { + 0xfee00000, + 0xfee10000, + 0xfee20000, + }, .grfcfg = &rk3588_combphy_grfcfgs, .combphy_cfg = rk3588_combphy_cfg, }; -- cgit v1.2.3 From 2dc3600d360a88861f076cda6769d7e1ad3204b0 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 24 Jul 2024 06:55:36 +0000 Subject: mmc: rockchip_dw_mmc: Allow 4-bit mode when 8-bit mode is supported Hosts capable of 8-bit can also do 4 bits, fix use of 4-bit mode when 8-bit mode is supported. This fixes use of 1-bit mode with SD NAND on ROCK Pi S using the DT in v6.11-rc1 that chage to use 8-bit bus to also support eMMC. With this 4-bit mode is used with SD NAND and 8-bit mode with eMMC, same as in Linux kernel. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/mmc/rockchip_dw_mmc.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 1a10b7057a4..549fb80f198 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -159,6 +159,10 @@ static int rockchip_dwmmc_probe(struct udevice *dev) host->mmc->dev = dev; upriv->mmc = host->mmc; + /* Hosts capable of 8-bit can also do 4 bits */ + if (host->buswidth == 8) + plat->cfg.host_caps |= MMC_MODE_4BIT; + return dwmci_probe(dev); } -- cgit v1.2.3 From 28a0c184580c3a71e37a22a4c2063511594ec372 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 24 Jul 2024 06:58:15 +0000 Subject: rockchip: io-domain: Add support for RK3308 Port the RK3308 part of the Rockchip IO Domain driver from linux. This differs from linux version in that vccio3 iodomain bit is enabled in the write ops instead of in an init ops as in linux, this way we can avoid keeping a full state of all supply that have been configured. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/misc/rockchip-io-domain.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'drivers') diff --git a/drivers/misc/rockchip-io-domain.c b/drivers/misc/rockchip-io-domain.c index cf4f7c3984c..025b6049a9f 100644 --- a/drivers/misc/rockchip-io-domain.c +++ b/drivers/misc/rockchip-io-domain.c @@ -31,6 +31,10 @@ #define PX30_IO_VSEL_VCCIO6_SRC BIT(0) #define PX30_IO_VSEL_VCCIO6_SUPPLY_NUM 1 +#define RK3308_SOC_CON0 0x300 +#define RK3308_SOC_CON0_VCCIO3 BIT(8) +#define RK3308_SOC_VCCIO3_SUPPLY_NUM 3 + #define RK3328_SOC_CON4 0x410 #define RK3328_SOC_CON4_VCCIO2 BIT(7) #define RK3328_SOC_VCCIO2_SUPPLY_NUM 1 @@ -119,6 +123,22 @@ static int px30_iodomain_write(struct regmap *grf, uint offset, int idx, int uV) return ret; } +static int rk3308_iodomain_write(struct regmap *grf, uint offset, int idx, int uV) +{ + int ret = rockchip_iodomain_write(grf, offset, idx, uV); + + if (!ret && idx == RK3308_SOC_VCCIO3_SUPPLY_NUM) { + /* + * set vccio3 iodomain to also use this framework + * instead of a special gpio. + */ + u32 val = RK3308_SOC_CON0_VCCIO3 | (RK3308_SOC_CON0_VCCIO3 << 16); + ret = regmap_write(grf, RK3308_SOC_CON0, val); + } + + return ret; +} + static int rk3328_iodomain_write(struct regmap *grf, uint offset, int idx, int uV) { int ret = rockchip_iodomain_write(grf, offset, idx, uV); @@ -189,6 +209,19 @@ static const struct rockchip_iodomain_soc_data soc_data_px30_pmu = { .write = rockchip_iodomain_write, }; +static const struct rockchip_iodomain_soc_data soc_data_rk3308 = { + .grf_offset = 0x300, + .supply_names = { + "vccio0-supply", + "vccio1-supply", + "vccio2-supply", + "vccio3-supply", + "vccio4-supply", + "vccio5-supply", + }, + .write = rk3308_iodomain_write, +}; + static const struct rockchip_iodomain_soc_data soc_data_rk3328 = { .grf_offset = 0x410, .supply_names = { @@ -256,6 +289,10 @@ static const struct udevice_id rockchip_iodomain_ids[] = { .compatible = "rockchip,px30-pmu-io-voltage-domain", .data = (ulong)&soc_data_px30_pmu, }, + { + .compatible = "rockchip,rk3308-io-voltage-domain", + .data = (ulong)&soc_data_rk3308, + }, { .compatible = "rockchip,rk3328-io-voltage-domain", .data = (ulong)&soc_data_rk3328, -- cgit v1.2.3 From 232af1e58a977f3857074d3aba3709c860bd8058 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 2 Aug 2024 22:12:22 +0000 Subject: dm: adc: Add SPL_ADC Kconfig symbol for use of ADC in SPL What model of Radxa ZERO 3W/3E board can be identified using ADC at runtime, add a Kconfig symbol to allow use of ADC in SPL. This will be used to identify board model in SPL to allow loading correct FIT configuration and FDT for U-Boot proper at SPL phase. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/Makefile | 2 +- drivers/adc/Kconfig | 5 +++++ drivers/adc/Makefile | 2 +- 3 files changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/Makefile b/drivers/Makefile index 9195dafd37e..1acd94f3c17 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ +obj-$(CONFIG_$(SPL_TPL_)ADC) += adc/ obj-$(CONFIG_$(SPL_TPL_)BIOSEMU) += bios_emulator/ obj-$(CONFIG_$(SPL_TPL_)BLK) += block/ obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/ @@ -81,7 +82,6 @@ endif ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) -obj-y += adc/ obj-y += ata/ obj-$(CONFIG_DM_DEMO) += demo/ obj-y += block/ diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index c9cdbe6942d..37235f557a3 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -1,5 +1,6 @@ config ADC bool "Enable ADC drivers using Driver Model" + depends on DM help This enables ADC API for drivers, which allows driving ADC features by single and multi-channel methods for: @@ -11,6 +12,10 @@ config ADC - support supply's phandle with auto-enable - supply polarity setting in fdt +config SPL_ADC + bool "Enable ADC drivers using Driver Model in SPL" + depends on SPL_DM + config ADC_EXYNOS bool "Enable Exynos 54xx ADC driver" depends on ADC diff --git a/drivers/adc/Makefile b/drivers/adc/Makefile index 5336c820973..dca0b39c2e2 100644 --- a/drivers/adc/Makefile +++ b/drivers/adc/Makefile @@ -4,7 +4,7 @@ # Przemyslaw Marczak # -obj-$(CONFIG_ADC) += adc-uclass.o +obj-$(CONFIG_$(SPL_TPL_)ADC) += adc-uclass.o obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o obj-$(CONFIG_ADC_SANDBOX) += sandbox.o obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o -- cgit v1.2.3